drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "display/intel_crt.h"
  46 #include "display/intel_ddi.h"
  47 #include "display/intel_dp.h"
  48 #include "display/intel_dp_mst.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ilk_pch_clock_get(struct intel_crtc *crtc,
 149                               struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
 168 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 169 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 170                                          struct drm_modeset_acquire_ctx *ctx);
 171 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
 172
 173 struct intel_limit {
 174         struct {
 175                 int min, max;
 176         } dot, vco, n, m, m1, m2, p, p1;
 177
 178         struct {
 179                 int dot_limit;
 180                 int p2_slow, p2_fast;
 181         } p2;
 182 };
 183
 184 /* returns HPLL frequency in kHz */
 185 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 186 {
 187         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 188
 189         /* Obtain SKU information */
 190         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 191                 CCK_FUSE_HPLL_FREQ_MASK;
 192
 193         return vco_freq[hpll_freq] * 1000;
 194 }
 195
 196 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 197                       const char *name, u32 reg, int ref_freq)
 198 {
 199         u32 val;
 200         int divider;
 201
 202         val = vlv_cck_read(dev_priv, reg);
 203         divider = val & CCK_FREQUENCY_VALUES;
 204
 205         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 206                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 207                  "%s change in progress\n", name);
 208
 209         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 210 }
 211
 212 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 213                            const char *name, u32 reg)
 214 {
 215         int hpll;
 216
 217         vlv_cck_get(dev_priv);
 218
 219         if (dev_priv->hpll_freq == 0)
 220                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 221
 222         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 223
 224         vlv_cck_put(dev_priv);
 225
 226         return hpll;
 227 }
 228
 229 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 230 {
 231         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 232                 return;
 233
 234         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 235                                                       CCK_CZ_CLOCK_CONTROL);
 236
 237         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 238                 dev_priv->czclk_freq);
 239 }
 240
 241 /* units of 100MHz */
 242 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 243                                const struct intel_crtc_state *pipe_config)
 244 {
 245         if (HAS_DDI(dev_priv))
 246                 return pipe_config->port_clock; /* SPLL */
 247         else
 248                 return dev_priv->fdi_pll_freq;
 249 }
 250
 251 static const struct intel_limit intel_limits_i8xx_dac = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 2 },
 262 };
 263
 264 static const struct intel_limit intel_limits_i8xx_dvo = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 4 },
 275 };
 276
 277 static const struct intel_limit intel_limits_i8xx_lvds = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 1, .max = 6 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 14, .p2_fast = 7 },
 288 };
 289
 290 static const struct intel_limit intel_limits_i9xx_sdvo = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 200000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301 };
 302
 303 static const struct intel_limit intel_limits_i9xx_lvds = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 7, .max = 98 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 112000,
 313                 .p2_slow = 14, .p2_fast = 7 },
 314 };
 315
 316
 317 static const struct intel_limit intel_limits_g4x_sdvo = {
 318         .dot = { .min = 25000, .max = 270000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 17, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 10, .max = 30 },
 325         .p1 = { .min = 1, .max = 3},
 326         .p2 = { .dot_limit = 270000,
 327                 .p2_slow = 10,
 328                 .p2_fast = 10
 329         },
 330 };
 331
 332 static const struct intel_limit intel_limits_g4x_hdmi = {
 333         .dot = { .min = 22000, .max = 400000 },
 334         .vco = { .min = 1750000, .max = 3500000},
 335         .n = { .min = 1, .max = 4 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 16, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 5, .max = 80 },
 340         .p1 = { .min = 1, .max = 8},
 341         .p2 = { .dot_limit = 165000,
 342                 .p2_slow = 10, .p2_fast = 5 },
 343 };
 344
 345 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 346         .dot = { .min = 20000, .max = 115000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 14, .p2_fast = 14
 356         },
 357 };
 358
 359 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 360         .dot = { .min = 80000, .max = 224000 },
 361         .vco = { .min = 1750000, .max = 3500000 },
 362         .n = { .min = 1, .max = 3 },
 363         .m = { .min = 104, .max = 138 },
 364         .m1 = { .min = 17, .max = 23 },
 365         .m2 = { .min = 5, .max = 11 },
 366         .p = { .min = 14, .max = 42 },
 367         .p1 = { .min = 2, .max = 6 },
 368         .p2 = { .dot_limit = 0,
 369                 .p2_slow = 7, .p2_fast = 7
 370         },
 371 };
 372
 373 static const struct intel_limit pnv_limits_sdvo = {
 374         .dot = { .min = 20000, .max = 400000},
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         /* Pineview's Ncounter is a ring counter */
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         /* Pineview only has one combined m divider, which we treat as m2. */
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 5, .max = 80 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 200000,
 385                 .p2_slow = 10, .p2_fast = 5 },
 386 };
 387
 388 static const struct intel_limit pnv_limits_lvds = {
 389         .dot = { .min = 20000, .max = 400000 },
 390         .vco = { .min = 1700000, .max = 3500000 },
 391         .n = { .min = 3, .max = 6 },
 392         .m = { .min = 2, .max = 256 },
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 7, .max = 112 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 112000,
 398                 .p2_slow = 14, .p2_fast = 14 },
 399 };
 400
 401 /* Ironlake / Sandybridge
 402  *
 403  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 404  * the range value for them is (actual_value - 2).
 405  */
 406 static const struct intel_limit ilk_limits_dac = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 5 },
 410         .m = { .min = 79, .max = 127 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 5, .max = 80 },
 414         .p1 = { .min = 1, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 10, .p2_fast = 5 },
 417 };
 418
 419 static const struct intel_limit ilk_limits_single_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 118 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 28, .max = 112 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 14, .p2_fast = 14 },
 430 };
 431
 432 static const struct intel_limit ilk_limits_dual_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 127 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 14, .max = 56 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 7, .p2_fast = 7 },
 443 };
 444
 445 /* LVDS 100mhz refclk limits. */
 446 static const struct intel_limit ilk_limits_single_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 2 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 28, .max = 112 },
 454         .p1 = { .min = 2, .max = 8 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 14, .p2_fast = 14 },
 457 };
 458
 459 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 3 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 14, .max = 42 },
 467         .p1 = { .min = 2, .max = 6 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 7, .p2_fast = 7 },
 470 };
 471
 472 static const struct intel_limit intel_limits_vlv = {
 473          /*
 474           * These are the data rate limits (measured in fast clocks)
 475           * since those are the strictest limits we have. The fast
 476           * clock and actual rate limits are more relaxed, so checking
 477           * them would make no difference.
 478           */
 479         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 480         .vco = { .min = 4000000, .max = 6000000 },
 481         .n = { .min = 1, .max = 7 },
 482         .m1 = { .min = 2, .max = 3 },
 483         .m2 = { .min = 11, .max = 156 },
 484         .p1 = { .min = 2, .max = 3 },
 485         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 486 };
 487
 488 static const struct intel_limit intel_limits_chv = {
 489         /*
 490          * These are the data rate limits (measured in fast clocks)
 491          * since those are the strictest limits we have.  The fast
 492          * clock and actual rate limits are more relaxed, so checking
 493          * them would make no difference.
 494          */
 495         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 496         .vco = { .min = 4800000, .max = 6480000 },
 497         .n = { .min = 1, .max = 1 },
 498         .m1 = { .min = 2, .max = 2 },
 499         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 500         .p1 = { .min = 2, .max = 4 },
 501         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 502 };
 503
 504 static const struct intel_limit intel_limits_bxt = {
 505         /* FIXME: find real dot limits */
 506         .dot = { .min = 0, .max = INT_MAX },
 507         .vco = { .min = 4800000, .max = 6700000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         /* FIXME: find real m2 limits */
 511         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 514 };
 515
 516 /* WA Display #0827: Gen9:all */
 517 static void
 518 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 519 {
 520         if (enable)
 521                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 522                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 523         else
 524                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 525                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 526 }
 527
 528 /* Wa_2006604312:icl,ehl */
 529 static void
 530 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 531                        bool enable)
 532 {
 533         if (enable)
 534                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 535                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 536         else
 537                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 538                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 539 }
 540
 541 static bool
 542 needs_modeset(const struct intel_crtc_state *state)
 543 {
 544         return drm_atomic_crtc_needs_modeset(&state->uapi);
 545 }
 546
 547 static bool
 548 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 549 {
 550         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 551 }
 552
 553 static bool
 554 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 555 {
 556         return crtc_state->sync_mode_slaves_mask != 0;
 557 }
 558
 559 bool
 560 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 561 {
 562         return is_trans_port_sync_master(crtc_state) ||
 563                 is_trans_port_sync_slave(crtc_state);
 564 }
 565
 566 /*
 567  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 568  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 569  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 570  * The helpers' return value is the rate of the clock that is fed to the
 571  * display engine's pipe which can be the above fast dot clock rate or a
 572  * divided-down version of it.
 573  */
 574 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 575 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 576 {
 577         clock->m = clock->m2 + 2;
 578         clock->p = clock->p1 * clock->p2;
 579         if (WARN_ON(clock->n == 0 || clock->p == 0))
 580                 return 0;
 581         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 582         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 583
 584         return clock->dot;
 585 }
 586
 587 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 588 {
 589         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 590 }
 591
 592 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 593 {
 594         clock->m = i9xx_dpll_compute_m(clock);
 595         clock->p = clock->p1 * clock->p2;
 596         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 597                 return 0;
 598         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 599         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 600
 601         return clock->dot;
 602 }
 603
 604 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 605 {
 606         clock->m = clock->m1 * clock->m2;
 607         clock->p = clock->p1 * clock->p2;
 608         if (WARN_ON(clock->n == 0 || clock->p == 0))
 609                 return 0;
 610         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 611         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 612
 613         return clock->dot / 5;
 614 }
 615
 616 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 617 {
 618         clock->m = clock->m1 * clock->m2;
 619         clock->p = clock->p1 * clock->p2;
 620         if (WARN_ON(clock->n == 0 || clock->p == 0))
 621                 return 0;
 622         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 623                                            clock->n << 22);
 624         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 625
 626         return clock->dot / 5;
 627 }
 628
 629 /*
 630  * Returns whether the given set of divisors are valid for a given refclk with
 631  * the given connectors.
 632  */
 633 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 634                                const struct intel_limit *limit,
 635                                const struct dpll *clock)
 636 {
 637         if (clock->n < limit->n.min || limit->n.max < clock->n)
 638                 return false;
 639         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 640                 return false;
 641         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 642                 return false;
 643         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 644                 return false;
 645
 646         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 647             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 648                 if (clock->m1 <= clock->m2)
 649                         return false;
 650
 651         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 652             !IS_GEN9_LP(dev_priv)) {
 653                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 654                         return false;
 655                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 656                         return false;
 657         }
 658
 659         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 660                 return false;
 661         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 662          * connector, etc., rather than just a single range.
 663          */
 664         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 665                 return false;
 666
 667         return true;
 668 }
 669
 670 static int
 671 i9xx_select_p2_div(const struct intel_limit *limit,
 672                    const struct intel_crtc_state *crtc_state,
 673                    int target)
 674 {
 675         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 676
 677         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 678                 /*
 679                  * For LVDS just rely on its current settings for dual-channel.
 680                  * We haven't figured out how to reliably set up different
 681                  * single/dual channel state, if we even can.
 682                  */
 683                 if (intel_is_dual_link_lvds(dev_priv))
 684                         return limit->p2.p2_fast;
 685                 else
 686                         return limit->p2.p2_slow;
 687         } else {
 688                 if (target < limit->p2.dot_limit)
 689                         return limit->p2.p2_slow;
 690                 else
 691                         return limit->p2.p2_fast;
 692         }
 693 }
 694
 695 /*
 696  * Returns a set of divisors for the desired target clock with the given
 697  * refclk, or FALSE.  The returned values represent the clock equation:
 698  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 699  *
 700  * Target and reference clocks are specified in kHz.
 701  *
 702  * If match_clock is provided, then best_clock P divider must match the P
 703  * divider from @match_clock used for LVDS downclocking.
 704  */
 705 static bool
 706 i9xx_find_best_dpll(const struct intel_limit *limit,
 707                     struct intel_crtc_state *crtc_state,
 708                     int target, int refclk, struct dpll *match_clock,
 709                     struct dpll *best_clock)
 710 {
 711         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 712         struct dpll clock;
 713         int err = target;
 714
 715         memset(best_clock, 0, sizeof(*best_clock));
 716
 717         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 718
 719         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 720              clock.m1++) {
 721                 for (clock.m2 = limit->m2.min;
 722                      clock.m2 <= limit->m2.max; clock.m2++) {
 723                         if (clock.m2 >= clock.m1)
 724                                 break;
 725                         for (clock.n = limit->n.min;
 726                              clock.n <= limit->n.max; clock.n++) {
 727                                 for (clock.p1 = limit->p1.min;
 728                                         clock.p1 <= limit->p1.max; clock.p1++) {
 729                                         int this_err;
 730
 731                                         i9xx_calc_dpll_params(refclk, &clock);
 732                                         if (!intel_pll_is_valid(to_i915(dev),
 733                                                                 limit,
 734                                                                 &clock))
 735                                                 continue;
 736                                         if (match_clock &&
 737                                             clock.p != match_clock->p)
 738                                                 continue;
 739
 740                                         this_err = abs(clock.dot - target);
 741                                         if (this_err < err) {
 742                                                 *best_clock = clock;
 743                                                 err = this_err;
 744                                         }
 745                                 }
 746                         }
 747                 }
 748         }
 749
 750         return (err != target);
 751 }
 752
 753 /*
 754  * Returns a set of divisors for the desired target clock with the given
 755  * refclk, or FALSE.  The returned values represent the clock equation:
 756  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 757  *
 758  * Target and reference clocks are specified in kHz.
 759  *
 760  * If match_clock is provided, then best_clock P divider must match the P
 761  * divider from @match_clock used for LVDS downclocking.
 762  */
 763 static bool
 764 pnv_find_best_dpll(const struct intel_limit *limit,
 765                    struct intel_crtc_state *crtc_state,
 766                    int target, int refclk, struct dpll *match_clock,
 767                    struct dpll *best_clock)
 768 {
 769         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 770         struct dpll clock;
 771         int err = target;
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774
 775         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 776
 777         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 778              clock.m1++) {
 779                 for (clock.m2 = limit->m2.min;
 780                      clock.m2 <= limit->m2.max; clock.m2++) {
 781                         for (clock.n = limit->n.min;
 782                              clock.n <= limit->n.max; clock.n++) {
 783                                 for (clock.p1 = limit->p1.min;
 784                                         clock.p1 <= limit->p1.max; clock.p1++) {
 785                                         int this_err;
 786
 787                                         pnv_calc_dpll_params(refclk, &clock);
 788                                         if (!intel_pll_is_valid(to_i915(dev),
 789                                                                 limit,
 790                                                                 &clock))
 791                                                 continue;
 792                                         if (match_clock &&
 793                                             clock.p != match_clock->p)
 794                                                 continue;
 795
 796                                         this_err = abs(clock.dot - target);
 797                                         if (this_err < err) {
 798                                                 *best_clock = clock;
 799                                                 err = this_err;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805
 806         return (err != target);
 807 }
 808
 809 /*
 810  * Returns a set of divisors for the desired target clock with the given
 811  * refclk, or FALSE.  The returned values represent the clock equation:
 812  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 813  *
 814  * Target and reference clocks are specified in kHz.
 815  *
 816  * If match_clock is provided, then best_clock P divider must match the P
 817  * divider from @match_clock used for LVDS downclocking.
 818  */
 819 static bool
 820 g4x_find_best_dpll(const struct intel_limit *limit,
 821                    struct intel_crtc_state *crtc_state,
 822                    int target, int refclk, struct dpll *match_clock,
 823                    struct dpll *best_clock)
 824 {
 825         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 826         struct dpll clock;
 827         int max_n;
 828         bool found = false;
 829         /* approximately equals target * 0.00585 */
 830         int err_most = (target >> 8) + (target >> 9);
 831
 832         memset(best_clock, 0, sizeof(*best_clock));
 833
 834         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 835
 836         max_n = limit->n.max;
 837         /* based on hardware requirement, prefer smaller n to precision */
 838         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 839                 /* based on hardware requirement, prefere larger m1,m2 */
 840                 for (clock.m1 = limit->m1.max;
 841                      clock.m1 >= limit->m1.min; clock.m1--) {
 842                         for (clock.m2 = limit->m2.max;
 843                              clock.m2 >= limit->m2.min; clock.m2--) {
 844                                 for (clock.p1 = limit->p1.max;
 845                                      clock.p1 >= limit->p1.min; clock.p1--) {
 846                                         int this_err;
 847
 848                                         i9xx_calc_dpll_params(refclk, &clock);
 849                                         if (!intel_pll_is_valid(to_i915(dev),
 850                                                                 limit,
 851                                                                 &clock))
 852                                                 continue;
 853
 854                                         this_err = abs(clock.dot - target);
 855                                         if (this_err < err_most) {
 856                                                 *best_clock = clock;
 857                                                 err_most = this_err;
 858                                                 max_n = clock.n;
 859                                                 found = true;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865         return found;
 866 }
 867
 868 /*
 869  * Check if the calculated PLL configuration is more optimal compared to the
 870  * best configuration and error found so far. Return the calculated error.
 871  */
 872 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 873                                const struct dpll *calculated_clock,
 874                                const struct dpll *best_clock,
 875                                unsigned int best_error_ppm,
 876                                unsigned int *error_ppm)
 877 {
 878         /*
 879          * For CHV ignore the error and consider only the P value.
 880          * Prefer a bigger P value based on HW requirements.
 881          */
 882         if (IS_CHERRYVIEW(to_i915(dev))) {
 883                 *error_ppm = 0;
 884
 885                 return calculated_clock->p > best_clock->p;
 886         }
 887
 888         if (drm_WARN_ON_ONCE(dev, !target_freq))
 889                 return false;
 890
 891         *error_ppm = div_u64(1000000ULL *
 892                                 abs(target_freq - calculated_clock->dot),
 893                              target_freq);
 894         /*
 895          * Prefer a better P value over a better (smaller) error if the error
 896          * is small. Ensure this preference for future configurations too by
 897          * setting the error to 0.
 898          */
 899         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 900                 *error_ppm = 0;
 901
 902                 return true;
 903         }
 904
 905         return *error_ppm + 10 < best_error_ppm;
 906 }
 907
 908 /*
 909  * Returns a set of divisors for the desired target clock with the given
 910  * refclk, or FALSE.  The returned values represent the clock equation:
 911  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 912  */
 913 static bool
 914 vlv_find_best_dpll(const struct intel_limit *limit,
 915                    struct intel_crtc_state *crtc_state,
 916                    int target, int refclk, struct dpll *match_clock,
 917                    struct dpll *best_clock)
 918 {
 919         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 920         struct drm_device *dev = crtc->base.dev;
 921         struct dpll clock;
 922         unsigned int bestppm = 1000000;
 923         /* min update 19.2 MHz */
 924         int max_n = min(limit->n.max, refclk / 19200);
 925         bool found = false;
 926
 927         target *= 5; /* fast clock */
 928
 929         memset(best_clock, 0, sizeof(*best_clock));
 930
 931         /* based on hardware requirement, prefer smaller n to precision */
 932         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 933                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 934                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 935                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 936                                 clock.p = clock.p1 * clock.p2;
 937                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 938                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 939                                         unsigned int ppm;
 940
 941                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 942                                                                      refclk * clock.m1);
 943
 944                                         vlv_calc_dpll_params(refclk, &clock);
 945
 946                                         if (!intel_pll_is_valid(to_i915(dev),
 947                                                                 limit,
 948                                                                 &clock))
 949                                                 continue;
 950
 951                                         if (!vlv_PLL_is_optimal(dev, target,
 952                                                                 &clock,
 953                                                                 best_clock,
 954                                                                 bestppm, &ppm))
 955                                                 continue;
 956
 957                                         *best_clock = clock;
 958                                         bestppm = ppm;
 959                                         found = true;
 960                                 }
 961                         }
 962                 }
 963         }
 964
 965         return found;
 966 }
 967
 968 /*
 969  * Returns a set of divisors for the desired target clock with the given
 970  * refclk, or FALSE.  The returned values represent the clock equation:
 971  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 972  */
 973 static bool
 974 chv_find_best_dpll(const struct intel_limit *limit,
 975                    struct intel_crtc_state *crtc_state,
 976                    int target, int refclk, struct dpll *match_clock,
 977                    struct dpll *best_clock)
 978 {
 979         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 980         struct drm_device *dev = crtc->base.dev;
 981         unsigned int best_error_ppm;
 982         struct dpll clock;
 983         u64 m2;
 984         int found = false;
 985
 986         memset(best_clock, 0, sizeof(*best_clock));
 987         best_error_ppm = 1000000;
 988
 989         /*
 990          * Based on hardware doc, the n always set to 1, and m1 always
 991          * set to 2.  If requires to support 200Mhz refclk, we need to
 992          * revisit this because n may not 1 anymore.
 993          */
 994         clock.n = 1, clock.m1 = 2;
 995         target *= 5;    /* fast clock */
 996
 997         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 998                 for (clock.p2 = limit->p2.p2_fast;
 999                                 clock.p2 >= limit->p2.p2_slow;
1000                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1001                         unsigned int error_ppm;
1002
1003                         clock.p = clock.p1 * clock.p2;
1004
1005                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1006                                                    refclk * clock.m1);
1007
1008                         if (m2 > INT_MAX/clock.m1)
1009                                 continue;
1010
1011                         clock.m2 = m2;
1012
1013                         chv_calc_dpll_params(refclk, &clock);
1014
1015                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1016                                 continue;
1017
1018                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1019                                                 best_error_ppm, &error_ppm))
1020                                 continue;
1021
1022                         *best_clock = clock;
1023                         best_error_ppm = error_ppm;
1024                         found = true;
1025                 }
1026         }
1027
1028         return found;
1029 }
1030
1031 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1032                         struct dpll *best_clock)
1033 {
1034         int refclk = 100000;
1035         const struct intel_limit *limit = &intel_limits_bxt;
1036
1037         return chv_find_best_dpll(limit, crtc_state,
1038                                   crtc_state->port_clock, refclk,
1039                                   NULL, best_clock);
1040 }
1041
1042 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1043                                     enum pipe pipe)
1044 {
1045         i915_reg_t reg = PIPEDSL(pipe);
1046         u32 line1, line2;
1047         u32 line_mask;
1048
1049         if (IS_GEN(dev_priv, 2))
1050                 line_mask = DSL_LINEMASK_GEN2;
1051         else
1052                 line_mask = DSL_LINEMASK_GEN3;
1053
1054         line1 = intel_de_read(dev_priv, reg) & line_mask;
1055         msleep(5);
1056         line2 = intel_de_read(dev_priv, reg) & line_mask;
1057
1058         return line1 != line2;
1059 }
1060
1061 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1062 {
1063         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1064         enum pipe pipe = crtc->pipe;
1065
1066         /* Wait for the display line to settle/start moving */
1067         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1068                 drm_err(&dev_priv->drm,
1069                         "pipe %c scanline %s wait timed out\n",
1070                         pipe_name(pipe), onoff(state));
1071 }
1072
1073 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1074 {
1075         wait_for_pipe_scanline_moving(crtc, false);
1076 }
1077
1078 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1079 {
1080         wait_for_pipe_scanline_moving(crtc, true);
1081 }
1082
1083 static void
1084 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1085 {
1086         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1087         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1088
1089         if (INTEL_GEN(dev_priv) >= 4) {
1090                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1091                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1092
1093                 /* Wait for the Pipe State to go off */
1094                 if (intel_de_wait_for_clear(dev_priv, reg,
1095                                             I965_PIPECONF_ACTIVE, 100))
1096                         drm_WARN(&dev_priv->drm, 1,
1097                                  "pipe_off wait timed out\n");
1098         } else {
1099                 intel_wait_for_pipe_scanline_stopped(crtc);
1100         }
1101 }
1102
1103 /* Only for pre-ILK configs */
1104 void assert_pll(struct drm_i915_private *dev_priv,
1105                 enum pipe pipe, bool state)
1106 {
1107         u32 val;
1108         bool cur_state;
1109
1110         val = intel_de_read(dev_priv, DPLL(pipe));
1111         cur_state = !!(val & DPLL_VCO_ENABLE);
1112         I915_STATE_WARN(cur_state != state,
1113              "PLL state assertion failure (expected %s, current %s)\n",
1114                         onoff(state), onoff(cur_state));
1115 }
1116
1117 /* XXX: the dsi pll is shared between MIPI DSI ports */
1118 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         vlv_cck_get(dev_priv);
1124         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1125         vlv_cck_put(dev_priv);
1126
1127         cur_state = val & DSI_PLL_VCO_EN;
1128         I915_STATE_WARN(cur_state != state,
1129              "DSI PLL state assertion failure (expected %s, current %s)\n",
1130                         onoff(state), onoff(cur_state));
1131 }
1132
1133 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1134                           enum pipe pipe, bool state)
1135 {
1136         bool cur_state;
1137
1138         if (HAS_DDI(dev_priv)) {
1139                 /*
1140                  * DDI does not have a specific FDI_TX register.
1141                  *
1142                  * FDI is never fed from EDP transcoder
1143                  * so pipe->transcoder cast is fine here.
1144                  */
1145                 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1146                 u32 val = intel_de_read(dev_priv,
1147                                         TRANS_DDI_FUNC_CTL(cpu_transcoder));
1148                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1149         } else {
1150                 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1151                 cur_state = !!(val & FDI_TX_ENABLE);
1152         }
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI TX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1158 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1159
1160 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1161                           enum pipe pipe, bool state)
1162 {
1163         u32 val;
1164         bool cur_state;
1165
1166         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1167         cur_state = !!(val & FDI_RX_ENABLE);
1168         I915_STATE_WARN(cur_state != state,
1169              "FDI RX state assertion failure (expected %s, current %s)\n",
1170                         onoff(state), onoff(cur_state));
1171 }
1172 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1173 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1174
1175 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1176                                       enum pipe pipe)
1177 {
1178         u32 val;
1179
1180         /* ILK FDI PLL is always enabled */
1181         if (IS_GEN(dev_priv, 5))
1182                 return;
1183
1184         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1185         if (HAS_DDI(dev_priv))
1186                 return;
1187
1188         val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1189         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1193                        enum pipe pipe, bool state)
1194 {
1195         u32 val;
1196         bool cur_state;
1197
1198         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1199         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1200         I915_STATE_WARN(cur_state != state,
1201              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1202                         onoff(state), onoff(cur_state));
1203 }
1204
1205 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1206 {
1207         i915_reg_t pp_reg;
1208         u32 val;
1209         enum pipe panel_pipe = INVALID_PIPE;
1210         bool locked = true;
1211
1212         if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1213                 return;
1214
1215         if (HAS_PCH_SPLIT(dev_priv)) {
1216                 u32 port_sel;
1217
1218                 pp_reg = PP_CONTROL(0);
1219                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1220
1221                 switch (port_sel) {
1222                 case PANEL_PORT_SELECT_LVDS:
1223                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1224                         break;
1225                 case PANEL_PORT_SELECT_DPA:
1226                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1227                         break;
1228                 case PANEL_PORT_SELECT_DPC:
1229                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1230                         break;
1231                 case PANEL_PORT_SELECT_DPD:
1232                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1233                         break;
1234                 default:
1235                         MISSING_CASE(port_sel);
1236                         break;
1237                 }
1238         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1239                 /* presumably write lock depends on pipe, not port select */
1240                 pp_reg = PP_CONTROL(pipe);
1241                 panel_pipe = pipe;
1242         } else {
1243                 u32 port_sel;
1244
1245                 pp_reg = PP_CONTROL(0);
1246                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1247
1248                 drm_WARN_ON(&dev_priv->drm,
1249                             port_sel != PANEL_PORT_SELECT_LVDS);
1250                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1251         }
1252
1253         val = intel_de_read(dev_priv, pp_reg);
1254         if (!(val & PANEL_POWER_ON) ||
1255             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1256                 locked = false;
1257
1258         I915_STATE_WARN(panel_pipe == pipe && locked,
1259              "panel assertion failure, pipe %c regs locked\n",
1260              pipe_name(pipe));
1261 }
1262
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264                  enum transcoder cpu_transcoder, bool state)
1265 {
1266         bool cur_state;
1267         enum intel_display_power_domain power_domain;
1268         intel_wakeref_t wakeref;
1269
1270         /* we keep both pipes enabled on 830 */
1271         if (IS_I830(dev_priv))
1272                 state = true;
1273
1274         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1275         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1276         if (wakeref) {
1277                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1278                 cur_state = !!(val & PIPECONF_ENABLE);
1279
1280                 intel_display_power_put(dev_priv, power_domain, wakeref);
1281         } else {
1282                 cur_state = false;
1283         }
1284
1285         I915_STATE_WARN(cur_state != state,
1286                         "transcoder %s assertion failure (expected %s, current %s)\n",
1287                         transcoder_name(cpu_transcoder),
1288                         onoff(state), onoff(cur_state));
1289 }
1290
1291 static void assert_plane(struct intel_plane *plane, bool state)
1292 {
1293         enum pipe pipe;
1294         bool cur_state;
1295
1296         cur_state = plane->get_hw_state(plane, &pipe);
1297
1298         I915_STATE_WARN(cur_state != state,
1299                         "%s assertion failure (expected %s, current %s)\n",
1300                         plane->base.name, onoff(state), onoff(cur_state));
1301 }
1302
1303 #define assert_plane_enabled(p) assert_plane(p, true)
1304 #define assert_plane_disabled(p) assert_plane(p, false)
1305
1306 static void assert_planes_disabled(struct intel_crtc *crtc)
1307 {
1308         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1309         struct intel_plane *plane;
1310
1311         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1312                 assert_plane_disabled(plane);
1313 }
1314
1315 static void assert_vblank_disabled(struct drm_crtc *crtc)
1316 {
1317         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1318                 drm_crtc_vblank_put(crtc);
1319 }
1320
1321 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322                                     enum pipe pipe)
1323 {
1324         u32 val;
1325         bool enabled;
1326
1327         val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1328         enabled = !!(val & TRANS_ENABLE);
1329         I915_STATE_WARN(enabled,
1330              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331              pipe_name(pipe));
1332 }
1333
1334 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1335                                    enum pipe pipe, enum port port,
1336                                    i915_reg_t dp_reg)
1337 {
1338         enum pipe port_pipe;
1339         bool state;
1340
1341         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1342
1343         I915_STATE_WARN(state && port_pipe == pipe,
1344                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1345                         port_name(port), pipe_name(pipe));
1346
1347         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1348                         "IBX PCH DP %c still using transcoder B\n",
1349                         port_name(port));
1350 }
1351
1352 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1353                                      enum pipe pipe, enum port port,
1354                                      i915_reg_t hdmi_reg)
1355 {
1356         enum pipe port_pipe;
1357         bool state;
1358
1359         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1360
1361         I915_STATE_WARN(state && port_pipe == pipe,
1362                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1363                         port_name(port), pipe_name(pipe));
1364
1365         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1366                         "IBX PCH HDMI %c still using transcoder B\n",
1367                         port_name(port));
1368 }
1369
1370 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1371                                       enum pipe pipe)
1372 {
1373         enum pipe port_pipe;
1374
1375         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1376         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1377         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1378
1379         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1380                         port_pipe == pipe,
1381                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1382                         pipe_name(pipe));
1383
1384         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1385                         port_pipe == pipe,
1386                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1387                         pipe_name(pipe));
1388
1389         /* PCH SDVOB multiplex with HDMIB */
1390         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1391         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1392         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1393 }
1394
1395 static void _vlv_enable_pll(struct intel_crtc *crtc,
1396                             const struct intel_crtc_state *pipe_config)
1397 {
1398         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1399         enum pipe pipe = crtc->pipe;
1400
1401         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1402         intel_de_posting_read(dev_priv, DPLL(pipe));
1403         udelay(150);
1404
1405         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1406                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1407 }
1408
1409 static void vlv_enable_pll(struct intel_crtc *crtc,
1410                            const struct intel_crtc_state *pipe_config)
1411 {
1412         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1413         enum pipe pipe = crtc->pipe;
1414
1415         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1416
1417         /* PLL is protected by panel, make sure we can write it */
1418         assert_panel_unlocked(dev_priv, pipe);
1419
1420         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1421                 _vlv_enable_pll(crtc, pipe_config);
1422
1423         intel_de_write(dev_priv, DPLL_MD(pipe),
1424                        pipe_config->dpll_hw_state.dpll_md);
1425         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1426 }
1427
1428
1429 static void _chv_enable_pll(struct intel_crtc *crtc,
1430                             const struct intel_crtc_state *pipe_config)
1431 {
1432         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1433         enum pipe pipe = crtc->pipe;
1434         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1435         u32 tmp;
1436
1437         vlv_dpio_get(dev_priv);
1438
1439         /* Enable back the 10bit clock to display controller */
1440         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1441         tmp |= DPIO_DCLKP_EN;
1442         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1443
1444         vlv_dpio_put(dev_priv);
1445
1446         /*
1447          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1448          */
1449         udelay(1);
1450
1451         /* Enable PLL */
1452         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1453
1454         /* Check PLL is locked */
1455         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1456                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1457 }
1458
1459 static void chv_enable_pll(struct intel_crtc *crtc,
1460                            const struct intel_crtc_state *pipe_config)
1461 {
1462         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1463         enum pipe pipe = crtc->pipe;
1464
1465         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1466
1467         /* PLL is protected by panel, make sure we can write it */
1468         assert_panel_unlocked(dev_priv, pipe);
1469
1470         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1471                 _chv_enable_pll(crtc, pipe_config);
1472
1473         if (pipe != PIPE_A) {
1474                 /*
1475                  * WaPixelRepeatModeFixForC0:chv
1476                  *
1477                  * DPLLCMD is AWOL. Use chicken bits to propagate
1478                  * the value from DPLLBMD to either pipe B or C.
1479                  */
1480                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1481                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1482                                pipe_config->dpll_hw_state.dpll_md);
1483                 intel_de_write(dev_priv, CBR4_VLV, 0);
1484                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1485
1486                 /*
1487                  * DPLLB VGA mode also seems to cause problems.
1488                  * We should always have it disabled.
1489                  */
1490                 drm_WARN_ON(&dev_priv->drm,
1491                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1492                              DPLL_VGA_MODE_DIS) == 0);
1493         } else {
1494                 intel_de_write(dev_priv, DPLL_MD(pipe),
1495                                pipe_config->dpll_hw_state.dpll_md);
1496                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1497         }
1498 }
1499
1500 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1501 {
1502         if (IS_I830(dev_priv))
1503                 return false;
1504
1505         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1506 }
1507
1508 static void i9xx_enable_pll(struct intel_crtc *crtc,
1509                             const struct intel_crtc_state *crtc_state)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1512         i915_reg_t reg = DPLL(crtc->pipe);
1513         u32 dpll = crtc_state->dpll_hw_state.dpll;
1514         int i;
1515
1516         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         if (i9xx_has_pps(dev_priv))
1520                 assert_panel_unlocked(dev_priv, crtc->pipe);
1521
1522         /*
1523          * Apparently we need to have VGA mode enabled prior to changing
1524          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1525          * dividers, even though the register value does change.
1526          */
1527         intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1528         intel_de_write(dev_priv, reg, dpll);
1529
1530         /* Wait for the clocks to stabilize. */
1531         intel_de_posting_read(dev_priv, reg);
1532         udelay(150);
1533
1534         if (INTEL_GEN(dev_priv) >= 4) {
1535                 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1536                                crtc_state->dpll_hw_state.dpll_md);
1537         } else {
1538                 /* The pixel multiplier can only be updated once the
1539                  * DPLL is enabled and the clocks are stable.
1540                  *
1541                  * So write it again.
1542                  */
1543                 intel_de_write(dev_priv, reg, dpll);
1544         }
1545
1546         /* We do this three times for luck */
1547         for (i = 0; i < 3; i++) {
1548                 intel_de_write(dev_priv, reg, dpll);
1549                 intel_de_posting_read(dev_priv, reg);
1550                 udelay(150); /* wait for warmup */
1551         }
1552 }
1553
1554 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1555 {
1556         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1558         enum pipe pipe = crtc->pipe;
1559
1560         /* Don't disable pipe or pipe PLLs if needed */
1561         if (IS_I830(dev_priv))
1562                 return;
1563
1564         /* Make sure the pipe isn't still relying on us */
1565         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1566
1567         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1568         intel_de_posting_read(dev_priv, DPLL(pipe));
1569 }
1570
1571 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1572 {
1573         u32 val;
1574
1575         /* Make sure the pipe isn't still relying on us */
1576         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1577
1578         val = DPLL_INTEGRATED_REF_CLK_VLV |
1579                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1580         if (pipe != PIPE_A)
1581                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1582
1583         intel_de_write(dev_priv, DPLL(pipe), val);
1584         intel_de_posting_read(dev_priv, DPLL(pipe));
1585 }
1586
1587 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1588 {
1589         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1590         u32 val;
1591
1592         /* Make sure the pipe isn't still relying on us */
1593         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1594
1595         val = DPLL_SSC_REF_CLK_CHV |
1596                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1597         if (pipe != PIPE_A)
1598                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1599
1600         intel_de_write(dev_priv, DPLL(pipe), val);
1601         intel_de_posting_read(dev_priv, DPLL(pipe));
1602
1603         vlv_dpio_get(dev_priv);
1604
1605         /* Disable 10bit clock to display controller */
1606         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1607         val &= ~DPIO_DCLKP_EN;
1608         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1609
1610         vlv_dpio_put(dev_priv);
1611 }
1612
1613 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1614                          struct intel_digital_port *dport,
1615                          unsigned int expected_mask)
1616 {
1617         u32 port_mask;
1618         i915_reg_t dpll_reg;
1619
1620         switch (dport->base.port) {
1621         case PORT_B:
1622                 port_mask = DPLL_PORTB_READY_MASK;
1623                 dpll_reg = DPLL(0);
1624                 break;
1625         case PORT_C:
1626                 port_mask = DPLL_PORTC_READY_MASK;
1627                 dpll_reg = DPLL(0);
1628                 expected_mask <<= 4;
1629                 break;
1630         case PORT_D:
1631                 port_mask = DPLL_PORTD_READY_MASK;
1632                 dpll_reg = DPIO_PHY_STATUS;
1633                 break;
1634         default:
1635                 BUG();
1636         }
1637
1638         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1639                                        port_mask, expected_mask, 1000))
1640                 drm_WARN(&dev_priv->drm, 1,
1641                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1642                          dport->base.base.base.id, dport->base.base.name,
1643                          intel_de_read(dev_priv, dpll_reg) & port_mask,
1644                          expected_mask);
1645 }
1646
1647 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1648 {
1649         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1650         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1651         enum pipe pipe = crtc->pipe;
1652         i915_reg_t reg;
1653         u32 val, pipeconf_val;
1654
1655         /* Make sure PCH DPLL is enabled */
1656         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1657
1658         /* FDI must be feeding us bits for PCH ports */
1659         assert_fdi_tx_enabled(dev_priv, pipe);
1660         assert_fdi_rx_enabled(dev_priv, pipe);
1661
1662         if (HAS_PCH_CPT(dev_priv)) {
1663                 reg = TRANS_CHICKEN2(pipe);
1664                 val = intel_de_read(dev_priv, reg);
1665                 /*
1666                  * Workaround: Set the timing override bit
1667                  * before enabling the pch transcoder.
1668                  */
1669                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1670                 /* Configure frame start delay to match the CPU */
1671                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1672                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1673                 intel_de_write(dev_priv, reg, val);
1674         }
1675
1676         reg = PCH_TRANSCONF(pipe);
1677         val = intel_de_read(dev_priv, reg);
1678         pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1679
1680         if (HAS_PCH_IBX(dev_priv)) {
1681                 /* Configure frame start delay to match the CPU */
1682                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1683                 val |= TRANS_FRAME_START_DELAY(0);
1684
1685                 /*
1686                  * Make the BPC in transcoder be consistent with
1687                  * that in pipeconf reg. For HDMI we must use 8bpc
1688                  * here for both 8bpc and 12bpc.
1689                  */
1690                 val &= ~PIPECONF_BPC_MASK;
1691                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1692                         val |= PIPECONF_8BPC;
1693                 else
1694                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1695         }
1696
1697         val &= ~TRANS_INTERLACE_MASK;
1698         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1699                 if (HAS_PCH_IBX(dev_priv) &&
1700                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1701                         val |= TRANS_LEGACY_INTERLACED_ILK;
1702                 else
1703                         val |= TRANS_INTERLACED;
1704         } else {
1705                 val |= TRANS_PROGRESSIVE;
1706         }
1707
1708         intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1709         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1710                 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1711                         pipe_name(pipe));
1712 }
1713
1714 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1715                                       enum transcoder cpu_transcoder)
1716 {
1717         u32 val, pipeconf_val;
1718
1719         /* FDI must be feeding us bits for PCH ports */
1720         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1721         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1722
1723         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1724         /* Workaround: set timing override bit. */
1725         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1726         /* Configure frame start delay to match the CPU */
1727         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1728         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1729         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1730
1731         val = TRANS_ENABLE;
1732         pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1733
1734         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1735             PIPECONF_INTERLACED_ILK)
1736                 val |= TRANS_INTERLACED;
1737         else
1738                 val |= TRANS_PROGRESSIVE;
1739
1740         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1741         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1742                                   TRANS_STATE_ENABLE, 100))
1743                 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1744 }
1745
1746 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1747                                        enum pipe pipe)
1748 {
1749         i915_reg_t reg;
1750         u32 val;
1751
1752         /* FDI relies on the transcoder */
1753         assert_fdi_tx_disabled(dev_priv, pipe);
1754         assert_fdi_rx_disabled(dev_priv, pipe);
1755
1756         /* Ports must be off as well */
1757         assert_pch_ports_disabled(dev_priv, pipe);
1758
1759         reg = PCH_TRANSCONF(pipe);
1760         val = intel_de_read(dev_priv, reg);
1761         val &= ~TRANS_ENABLE;
1762         intel_de_write(dev_priv, reg, val);
1763         /* wait for PCH transcoder off, transcoder state */
1764         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1765                 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1766                         pipe_name(pipe));
1767
1768         if (HAS_PCH_CPT(dev_priv)) {
1769                 /* Workaround: Clear the timing override chicken bit again. */
1770                 reg = TRANS_CHICKEN2(pipe);
1771                 val = intel_de_read(dev_priv, reg);
1772                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1773                 intel_de_write(dev_priv, reg, val);
1774         }
1775 }
1776
1777 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1778 {
1779         u32 val;
1780
1781         val = intel_de_read(dev_priv, LPT_TRANSCONF);
1782         val &= ~TRANS_ENABLE;
1783         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1784         /* wait for PCH transcoder off, transcoder state */
1785         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1786                                     TRANS_STATE_ENABLE, 50))
1787                 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1788
1789         /* Workaround: clear timing override bit. */
1790         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1791         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1792         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1793 }
1794
1795 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1796 {
1797         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1798
1799         if (HAS_PCH_LPT(dev_priv))
1800                 return PIPE_A;
1801         else
1802                 return crtc->pipe;
1803 }
1804
1805 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1806 {
1807         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1808
1809         /*
1810          * On i965gm the hardware frame counter reads
1811          * zero when the TV encoder is enabled :(
1812          */
1813         if (IS_I965GM(dev_priv) &&
1814             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1815                 return 0;
1816
1817         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1818                 return 0xffffffff; /* full 32 bit counter */
1819         else if (INTEL_GEN(dev_priv) >= 3)
1820                 return 0xffffff; /* only 24 bits of frame count */
1821         else
1822                 return 0; /* Gen2 doesn't have a hardware frame counter */
1823 }
1824
1825 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1826 {
1827         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1828
1829         assert_vblank_disabled(&crtc->base);
1830         drm_crtc_set_max_vblank_count(&crtc->base,
1831                                       intel_crtc_max_vblank_count(crtc_state));
1832         drm_crtc_vblank_on(&crtc->base);
1833 }
1834
1835 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1836 {
1837         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1838
1839         drm_crtc_vblank_off(&crtc->base);
1840         assert_vblank_disabled(&crtc->base);
1841 }
1842
1843 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1844 {
1845         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1847         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1848         enum pipe pipe = crtc->pipe;
1849         i915_reg_t reg;
1850         u32 val;
1851
1852         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1853
1854         assert_planes_disabled(crtc);
1855
1856         /*
1857          * A pipe without a PLL won't actually be able to drive bits from
1858          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1859          * need the check.
1860          */
1861         if (HAS_GMCH(dev_priv)) {
1862                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1863                         assert_dsi_pll_enabled(dev_priv);
1864                 else
1865                         assert_pll_enabled(dev_priv, pipe);
1866         } else {
1867                 if (new_crtc_state->has_pch_encoder) {
1868                         /* if driving the PCH, we need FDI enabled */
1869                         assert_fdi_rx_pll_enabled(dev_priv,
1870                                                   intel_crtc_pch_transcoder(crtc));
1871                         assert_fdi_tx_pll_enabled(dev_priv,
1872                                                   (enum pipe) cpu_transcoder);
1873                 }
1874                 /* FIXME: assert CPU port conditions for SNB+ */
1875         }
1876
1877         trace_intel_pipe_enable(crtc);
1878
1879         reg = PIPECONF(cpu_transcoder);
1880         val = intel_de_read(dev_priv, reg);
1881         if (val & PIPECONF_ENABLE) {
1882                 /* we keep both pipes enabled on 830 */
1883                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1884                 return;
1885         }
1886
1887         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1888         intel_de_posting_read(dev_priv, reg);
1889
1890         /*
1891          * Until the pipe starts PIPEDSL reads will return a stale value,
1892          * which causes an apparent vblank timestamp jump when PIPEDSL
1893          * resets to its proper value. That also messes up the frame count
1894          * when it's derived from the timestamps. So let's wait for the
1895          * pipe to start properly before we call drm_crtc_vblank_on()
1896          */
1897         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1898                 intel_wait_for_pipe_scanline_moving(crtc);
1899 }
1900
1901 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1902 {
1903         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1904         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1905         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1906         enum pipe pipe = crtc->pipe;
1907         i915_reg_t reg;
1908         u32 val;
1909
1910         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1911
1912         /*
1913          * Make sure planes won't keep trying to pump pixels to us,
1914          * or we might hang the display.
1915          */
1916         assert_planes_disabled(crtc);
1917
1918         trace_intel_pipe_disable(crtc);
1919
1920         reg = PIPECONF(cpu_transcoder);
1921         val = intel_de_read(dev_priv, reg);
1922         if ((val & PIPECONF_ENABLE) == 0)
1923                 return;
1924
1925         /*
1926          * Double wide has implications for planes
1927          * so best keep it disabled when not needed.
1928          */
1929         if (old_crtc_state->double_wide)
1930                 val &= ~PIPECONF_DOUBLE_WIDE;
1931
1932         /* Don't disable pipe or pipe PLLs if needed */
1933         if (!IS_I830(dev_priv))
1934                 val &= ~PIPECONF_ENABLE;
1935
1936         intel_de_write(dev_priv, reg, val);
1937         if ((val & PIPECONF_ENABLE) == 0)
1938                 intel_wait_for_pipe_off(old_crtc_state);
1939 }
1940
1941 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1942 {
1943         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1944 }
1945
1946 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1947 {
1948         if (!is_ccs_modifier(fb->modifier))
1949                 return false;
1950
1951         return plane >= fb->format->num_planes / 2;
1952 }
1953
1954 static bool is_gen12_ccs_modifier(u64 modifier)
1955 {
1956         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1957                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1958
1959 }
1960
1961 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1962 {
1963         return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1964 }
1965
1966 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1967 {
1968         if (is_ccs_modifier(fb->modifier))
1969                 return is_ccs_plane(fb, plane);
1970
1971         return plane == 1;
1972 }
1973
1974 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1975 {
1976         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1977                     (main_plane && main_plane >= fb->format->num_planes / 2));
1978
1979         return fb->format->num_planes / 2 + main_plane;
1980 }
1981
1982 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1983 {
1984         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1985                     ccs_plane < fb->format->num_planes / 2);
1986
1987         return ccs_plane - fb->format->num_planes / 2;
1988 }
1989
1990 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1991 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1992 {
1993         if (is_ccs_modifier(fb->modifier))
1994                 return main_to_ccs_plane(fb, main_plane);
1995
1996         return 1;
1997 }
1998
1999 bool
2000 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2001                                     uint64_t modifier)
2002 {
2003         return info->is_yuv &&
2004                info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2005 }
2006
2007 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2008                                    int color_plane)
2009 {
2010         return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2011                color_plane == 1;
2012 }
2013
2014 static unsigned int
2015 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2016 {
2017         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2018         unsigned int cpp = fb->format->cpp[color_plane];
2019
2020         switch (fb->modifier) {
2021         case DRM_FORMAT_MOD_LINEAR:
2022                 return intel_tile_size(dev_priv);
2023         case I915_FORMAT_MOD_X_TILED:
2024                 if (IS_GEN(dev_priv, 2))
2025                         return 128;
2026                 else
2027                         return 512;
2028         case I915_FORMAT_MOD_Y_TILED_CCS:
2029                 if (is_ccs_plane(fb, color_plane))
2030                         return 128;
2031                 /* fall through */
2032         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2033         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2034                 if (is_ccs_plane(fb, color_plane))
2035                         return 64;
2036                 /* fall through */
2037         case I915_FORMAT_MOD_Y_TILED:
2038                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2039                         return 128;
2040                 else
2041                         return 512;
2042         case I915_FORMAT_MOD_Yf_TILED_CCS:
2043                 if (is_ccs_plane(fb, color_plane))
2044                         return 128;
2045                 /* fall through */
2046         case I915_FORMAT_MOD_Yf_TILED:
2047                 switch (cpp) {
2048                 case 1:
2049                         return 64;
2050                 case 2:
2051                 case 4:
2052                         return 128;
2053                 case 8:
2054                 case 16:
2055                         return 256;
2056                 default:
2057                         MISSING_CASE(cpp);
2058                         return cpp;
2059                 }
2060                 break;
2061         default:
2062                 MISSING_CASE(fb->modifier);
2063                 return cpp;
2064         }
2065 }
2066
2067 static unsigned int
2068 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2069 {
2070         if (is_gen12_ccs_plane(fb, color_plane))
2071                 return 1;
2072
2073         return intel_tile_size(to_i915(fb->dev)) /
2074                 intel_tile_width_bytes(fb, color_plane);
2075 }
2076
2077 /* Return the tile dimensions in pixel units */
2078 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2079                             unsigned int *tile_width,
2080                             unsigned int *tile_height)
2081 {
2082         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2083         unsigned int cpp = fb->format->cpp[color_plane];
2084
2085         *tile_width = tile_width_bytes / cpp;
2086         *tile_height = intel_tile_height(fb, color_plane);
2087 }
2088
2089 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2090                                         int color_plane)
2091 {
2092         unsigned int tile_width, tile_height;
2093
2094         intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2095
2096         return fb->pitches[color_plane] * tile_height;
2097 }
2098
2099 unsigned int
2100 intel_fb_align_height(const struct drm_framebuffer *fb,
2101                       int color_plane, unsigned int height)
2102 {
2103         unsigned int tile_height = intel_tile_height(fb, color_plane);
2104
2105         return ALIGN(height, tile_height);
2106 }
2107
2108 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2109 {
2110         unsigned int size = 0;
2111         int i;
2112
2113         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2114                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2115
2116         return size;
2117 }
2118
2119 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2120 {
2121         unsigned int size = 0;
2122         int i;
2123
2124         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2125                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2126
2127         return size;
2128 }
2129
2130 static void
2131 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2132                         const struct drm_framebuffer *fb,
2133                         unsigned int rotation)
2134 {
2135         view->type = I915_GGTT_VIEW_NORMAL;
2136         if (drm_rotation_90_or_270(rotation)) {
2137                 view->type = I915_GGTT_VIEW_ROTATED;
2138                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2139         }
2140 }
2141
2142 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2143 {
2144         if (IS_I830(dev_priv))
2145                 return 16 * 1024;
2146         else if (IS_I85X(dev_priv))
2147                 return 256;
2148         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2149                 return 32;
2150         else
2151                 return 4 * 1024;
2152 }
2153
2154 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2155 {
2156         if (INTEL_GEN(dev_priv) >= 9)
2157                 return 256 * 1024;
2158         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2159                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2160                 return 128 * 1024;
2161         else if (INTEL_GEN(dev_priv) >= 4)
2162                 return 4 * 1024;
2163         else
2164                 return 0;
2165 }
2166
2167 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2168                                          int color_plane)
2169 {
2170         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2171
2172         /* AUX_DIST needs only 4K alignment */
2173         if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2174             is_ccs_plane(fb, color_plane))
2175                 return 4096;
2176
2177         switch (fb->modifier) {
2178         case DRM_FORMAT_MOD_LINEAR:
2179                 return intel_linear_alignment(dev_priv);
2180         case I915_FORMAT_MOD_X_TILED:
2181                 if (INTEL_GEN(dev_priv) >= 9)
2182                         return 256 * 1024;
2183                 return 0;
2184         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2185                 if (is_semiplanar_uv_plane(fb, color_plane))
2186                         return intel_tile_row_size(fb, color_plane);
2187                 /* Fall-through */
2188         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2189                 return 16 * 1024;
2190         case I915_FORMAT_MOD_Y_TILED_CCS:
2191         case I915_FORMAT_MOD_Yf_TILED_CCS:
2192         case I915_FORMAT_MOD_Y_TILED:
2193                 if (INTEL_GEN(dev_priv) >= 12 &&
2194                     is_semiplanar_uv_plane(fb, color_plane))
2195                         return intel_tile_row_size(fb, color_plane);
2196                 /* Fall-through */
2197         case I915_FORMAT_MOD_Yf_TILED:
2198                 return 1 * 1024 * 1024;
2199         default:
2200                 MISSING_CASE(fb->modifier);
2201                 return 0;
2202         }
2203 }
2204
2205 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2206 {
2207         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2208         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2209
2210         return INTEL_GEN(dev_priv) < 4 ||
2211                 (plane->has_fbc &&
2212                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2213 }
2214
2215 struct i915_vma *
2216 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2217                            const struct i915_ggtt_view *view,
2218                            bool uses_fence,
2219                            unsigned long *out_flags)
2220 {
2221         struct drm_device *dev = fb->dev;
2222         struct drm_i915_private *dev_priv = to_i915(dev);
2223         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2224         intel_wakeref_t wakeref;
2225         struct i915_vma *vma;
2226         unsigned int pinctl;
2227         u32 alignment;
2228
2229         if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2230                 return ERR_PTR(-EINVAL);
2231
2232         alignment = intel_surf_alignment(fb, 0);
2233         if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2234                 return ERR_PTR(-EINVAL);
2235
2236         /* Note that the w/a also requires 64 PTE of padding following the
2237          * bo. We currently fill all unused PTE with the shadow page and so
2238          * we should always have valid PTE following the scanout preventing
2239          * the VT-d warning.
2240          */
2241         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2242                 alignment = 256 * 1024;
2243
2244         /*
2245          * Global gtt pte registers are special registers which actually forward
2246          * writes to a chunk of system memory. Which means that there is no risk
2247          * that the register values disappear as soon as we call
2248          * intel_runtime_pm_put(), so it is correct to wrap only the
2249          * pin/unpin/fence and not more.
2250          */
2251         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2252
2253         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2254
2255         /*
2256          * Valleyview is definitely limited to scanning out the first
2257          * 512MiB. Lets presume this behaviour was inherited from the
2258          * g4x display engine and that all earlier gen are similarly
2259          * limited. Testing suggests that it is a little more
2260          * complicated than this. For example, Cherryview appears quite
2261          * happy to scanout from anywhere within its global aperture.
2262          */
2263         pinctl = 0;
2264         if (HAS_GMCH(dev_priv))
2265                 pinctl |= PIN_MAPPABLE;
2266
2267         vma = i915_gem_object_pin_to_display_plane(obj,
2268                                                    alignment, view, pinctl);
2269         if (IS_ERR(vma))
2270                 goto err;
2271
2272         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2273                 int ret;
2274
2275                 /*
2276                  * Install a fence for tiled scan-out. Pre-i965 always needs a
2277                  * fence, whereas 965+ only requires a fence if using
2278                  * framebuffer compression.  For simplicity, we always, when
2279                  * possible, install a fence as the cost is not that onerous.
2280                  *
2281                  * If we fail to fence the tiled scanout, then either the
2282                  * modeset will reject the change (which is highly unlikely as
2283                  * the affected systems, all but one, do not have unmappable
2284                  * space) or we will not be able to enable full powersaving
2285                  * techniques (also likely not to apply due to various limits
2286                  * FBC and the like impose on the size of the buffer, which
2287                  * presumably we violated anyway with this unmappable buffer).
2288                  * Anyway, it is presumably better to stumble onwards with
2289                  * something and try to run the system in a "less than optimal"
2290                  * mode that matches the user configuration.
2291                  */
2292                 ret = i915_vma_pin_fence(vma);
2293                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2294                         i915_gem_object_unpin_from_display_plane(vma);
2295                         vma = ERR_PTR(ret);
2296                         goto err;
2297                 }
2298
2299                 if (ret == 0 && vma->fence)
2300                         *out_flags |= PLANE_HAS_FENCE;
2301         }
2302
2303         i915_vma_get(vma);
2304 err:
2305         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2306         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2307         return vma;
2308 }
2309
2310 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2311 {
2312         i915_gem_object_lock(vma->obj);
2313         if (flags & PLANE_HAS_FENCE)
2314                 i915_vma_unpin_fence(vma);
2315         i915_gem_object_unpin_from_display_plane(vma);
2316         i915_gem_object_unlock(vma->obj);
2317
2318         i915_vma_put(vma);
2319 }
2320
2321 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2322                           unsigned int rotation)
2323 {
2324         if (drm_rotation_90_or_270(rotation))
2325                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2326         else
2327                 return fb->pitches[color_plane];
2328 }
2329
2330 /*
2331  * Convert the x/y offsets into a linear offset.
2332  * Only valid with 0/180 degree rotation, which is fine since linear
2333  * offset is only used with linear buffers on pre-hsw and tiled buffers
2334  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2335  */
2336 u32 intel_fb_xy_to_linear(int x, int y,
2337                           const struct intel_plane_state *state,
2338                           int color_plane)
2339 {
2340         const struct drm_framebuffer *fb = state->hw.fb;
2341         unsigned int cpp = fb->format->cpp[color_plane];
2342         unsigned int pitch = state->color_plane[color_plane].stride;
2343
2344         return y * pitch + x * cpp;
2345 }
2346
2347 /*
2348  * Add the x/y offsets derived from fb->offsets[] to the user
2349  * specified plane src x/y offsets. The resulting x/y offsets
2350  * specify the start of scanout from the beginning of the gtt mapping.
2351  */
2352 void intel_add_fb_offsets(int *x, int *y,
2353                           const struct intel_plane_state *state,
2354                           int color_plane)
2355
2356 {
2357         *x += state->color_plane[color_plane].x;
2358         *y += state->color_plane[color_plane].y;
2359 }
2360
2361 static u32 intel_adjust_tile_offset(int *x, int *y,
2362                                     unsigned int tile_width,
2363                                     unsigned int tile_height,
2364                                     unsigned int tile_size,
2365                                     unsigned int pitch_tiles,
2366                                     u32 old_offset,
2367                                     u32 new_offset)
2368 {
2369         unsigned int pitch_pixels = pitch_tiles * tile_width;
2370         unsigned int tiles;
2371
2372         WARN_ON(old_offset & (tile_size - 1));
2373         WARN_ON(new_offset & (tile_size - 1));
2374         WARN_ON(new_offset > old_offset);
2375
2376         tiles = (old_offset - new_offset) / tile_size;
2377
2378         *y += tiles / pitch_tiles * tile_height;
2379         *x += tiles % pitch_tiles * tile_width;
2380
2381         /* minimize x in case it got needlessly big */
2382         *y += *x / pitch_pixels * tile_height;
2383         *x %= pitch_pixels;
2384
2385         return new_offset;
2386 }
2387
2388 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2389 {
2390         return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2391                is_gen12_ccs_plane(fb, color_plane);
2392 }
2393
2394 static u32 intel_adjust_aligned_offset(int *x, int *y,
2395                                        const struct drm_framebuffer *fb,
2396                                        int color_plane,
2397                                        unsigned int rotation,
2398                                        unsigned int pitch,
2399                                        u32 old_offset, u32 new_offset)
2400 {
2401         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2402         unsigned int cpp = fb->format->cpp[color_plane];
2403
2404         drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2405
2406         if (!is_surface_linear(fb, color_plane)) {
2407                 unsigned int tile_size, tile_width, tile_height;
2408                 unsigned int pitch_tiles;
2409
2410                 tile_size = intel_tile_size(dev_priv);
2411                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2412
2413                 if (drm_rotation_90_or_270(rotation)) {
2414                         pitch_tiles = pitch / tile_height;
2415                         swap(tile_width, tile_height);
2416                 } else {
2417                         pitch_tiles = pitch / (tile_width * cpp);
2418                 }
2419
2420                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2421                                          tile_size, pitch_tiles,
2422                                          old_offset, new_offset);
2423         } else {
2424                 old_offset += *y * pitch + *x * cpp;
2425
2426                 *y = (old_offset - new_offset) / pitch;
2427                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2428         }
2429
2430         return new_offset;
2431 }
2432
2433 /*
2434  * Adjust the tile offset by moving the difference into
2435  * the x/y offsets.
2436  */
2437 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2438                                              const struct intel_plane_state *state,
2439                                              int color_plane,
2440                                              u32 old_offset, u32 new_offset)
2441 {
2442         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2443                                            state->hw.rotation,
2444                                            state->color_plane[color_plane].stride,
2445                                            old_offset, new_offset);
2446 }
2447
2448 /*
2449  * Computes the aligned offset to the base tile and adjusts
2450  * x, y. bytes per pixel is assumed to be a power-of-two.
2451  *
2452  * In the 90/270 rotated case, x and y are assumed
2453  * to be already rotated to match the rotated GTT view, and
2454  * pitch is the tile_height aligned framebuffer height.
2455  *
2456  * This function is used when computing the derived information
2457  * under intel_framebuffer, so using any of that information
2458  * here is not allowed. Anything under drm_framebuffer can be
2459  * used. This is why the user has to pass in the pitch since it
2460  * is specified in the rotated orientation.
2461  */
2462 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2463                                         int *x, int *y,
2464                                         const struct drm_framebuffer *fb,
2465                                         int color_plane,
2466                                         unsigned int pitch,
2467                                         unsigned int rotation,
2468                                         u32 alignment)
2469 {
2470         unsigned int cpp = fb->format->cpp[color_plane];
2471         u32 offset, offset_aligned;
2472
2473         if (!is_surface_linear(fb, color_plane)) {
2474                 unsigned int tile_size, tile_width, tile_height;
2475                 unsigned int tile_rows, tiles, pitch_tiles;
2476
2477                 tile_size = intel_tile_size(dev_priv);
2478                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2479
2480                 if (drm_rotation_90_or_270(rotation)) {
2481                         pitch_tiles = pitch / tile_height;
2482                         swap(tile_width, tile_height);
2483                 } else {
2484                         pitch_tiles = pitch / (tile_width * cpp);
2485                 }
2486
2487                 tile_rows = *y / tile_height;
2488                 *y %= tile_height;
2489
2490                 tiles = *x / tile_width;
2491                 *x %= tile_width;
2492
2493                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2494
2495                 offset_aligned = offset;
2496                 if (alignment)
2497                         offset_aligned = rounddown(offset_aligned, alignment);
2498
2499                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2500                                          tile_size, pitch_tiles,
2501                                          offset, offset_aligned);
2502         } else {
2503                 offset = *y * pitch + *x * cpp;
2504                 offset_aligned = offset;
2505                 if (alignment) {
2506                         offset_aligned = rounddown(offset_aligned, alignment);
2507                         *y = (offset % alignment) / pitch;
2508                         *x = ((offset % alignment) - *y * pitch) / cpp;
2509                 } else {
2510                         *y = *x = 0;
2511                 }
2512         }
2513
2514         return offset_aligned;
2515 }
2516
2517 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2518                                               const struct intel_plane_state *state,
2519                                               int color_plane)
2520 {
2521         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2522         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2523         const struct drm_framebuffer *fb = state->hw.fb;
2524         unsigned int rotation = state->hw.rotation;
2525         int pitch = state->color_plane[color_plane].stride;
2526         u32 alignment;
2527
2528         if (intel_plane->id == PLANE_CURSOR)
2529                 alignment = intel_cursor_alignment(dev_priv);
2530         else
2531                 alignment = intel_surf_alignment(fb, color_plane);
2532
2533         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2534                                             pitch, rotation, alignment);
2535 }
2536
2537 /* Convert the fb->offset[] into x/y offsets */
2538 static int intel_fb_offset_to_xy(int *x, int *y,
2539                                  const struct drm_framebuffer *fb,
2540                                  int color_plane)
2541 {
2542         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2543         unsigned int height;
2544         u32 alignment;
2545
2546         if (INTEL_GEN(dev_priv) >= 12 &&
2547             is_semiplanar_uv_plane(fb, color_plane))
2548                 alignment = intel_tile_row_size(fb, color_plane);
2549         else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2550                 alignment = intel_tile_size(dev_priv);
2551         else
2552                 alignment = 0;
2553
2554         if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2555                 drm_dbg_kms(&dev_priv->drm,
2556                             "Misaligned offset 0x%08x for color plane %d\n",
2557                             fb->offsets[color_plane], color_plane);
2558                 return -EINVAL;
2559         }
2560
2561         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2562         height = ALIGN(height, intel_tile_height(fb, color_plane));
2563
2564         /* Catch potential overflows early */
2565         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2566                             fb->offsets[color_plane])) {
2567                 drm_dbg_kms(&dev_priv->drm,
2568                             "Bad offset 0x%08x or pitch %d for color plane %d\n",
2569                             fb->offsets[color_plane], fb->pitches[color_plane],
2570                             color_plane);
2571                 return -ERANGE;
2572         }
2573
2574         *x = 0;
2575         *y = 0;
2576
2577         intel_adjust_aligned_offset(x, y,
2578                                     fb, color_plane, DRM_MODE_ROTATE_0,
2579                                     fb->pitches[color_plane],
2580                                     fb->offsets[color_plane], 0);
2581
2582         return 0;
2583 }
2584
2585 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2586 {
2587         switch (fb_modifier) {
2588         case I915_FORMAT_MOD_X_TILED:
2589                 return I915_TILING_X;
2590         case I915_FORMAT_MOD_Y_TILED:
2591         case I915_FORMAT_MOD_Y_TILED_CCS:
2592         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2593         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2594                 return I915_TILING_Y;
2595         default:
2596                 return I915_TILING_NONE;
2597         }
2598 }
2599
2600 /*
2601  * From the Sky Lake PRM:
2602  * "The Color Control Surface (CCS) contains the compression status of
2603  *  the cache-line pairs. The compression state of the cache-line pair
2604  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2605  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2606  *  cache-line-pairs. CCS is always Y tiled."
2607  *
2608  * Since cache line pairs refers to horizontally adjacent cache lines,
2609  * each cache line in the CCS corresponds to an area of 32x16 cache
2610  * lines on the main surface. Since each pixel is 4 bytes, this gives
2611  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2612  * main surface.
2613  */
2614 static const struct drm_format_info skl_ccs_formats[] = {
2615         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2616           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2617         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2618           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2619         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2620           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2621         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2622           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2623 };
2624
2625 /*
2626  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2627  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2628  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2629  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2630  * the main surface.
2631  */
2632 static const struct drm_format_info gen12_ccs_formats[] = {
2633         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2634           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2635           .hsub = 1, .vsub = 1, },
2636         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2637           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2638           .hsub = 1, .vsub = 1, },
2639         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2640           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2641           .hsub = 1, .vsub = 1, .has_alpha = true },
2642         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2643           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2644           .hsub = 1, .vsub = 1, .has_alpha = true },
2645         { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2646           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2647           .hsub = 2, .vsub = 1, .is_yuv = true },
2648         { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2649           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2650           .hsub = 2, .vsub = 1, .is_yuv = true },
2651         { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2652           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653           .hsub = 2, .vsub = 1, .is_yuv = true },
2654         { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2655           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656           .hsub = 2, .vsub = 1, .is_yuv = true },
2657         { .format = DRM_FORMAT_NV12, .num_planes = 4,
2658           .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2659           .hsub = 2, .vsub = 2, .is_yuv = true },
2660         { .format = DRM_FORMAT_P010, .num_planes = 4,
2661           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2662           .hsub = 2, .vsub = 2, .is_yuv = true },
2663         { .format = DRM_FORMAT_P012, .num_planes = 4,
2664           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2665           .hsub = 2, .vsub = 2, .is_yuv = true },
2666         { .format = DRM_FORMAT_P016, .num_planes = 4,
2667           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2668           .hsub = 2, .vsub = 2, .is_yuv = true },
2669 };
2670
2671 static const struct drm_format_info *
2672 lookup_format_info(const struct drm_format_info formats[],
2673                    int num_formats, u32 format)
2674 {
2675         int i;
2676
2677         for (i = 0; i < num_formats; i++) {
2678                 if (formats[i].format == format)
2679                         return &formats[i];
2680         }
2681
2682         return NULL;
2683 }
2684
2685 static const struct drm_format_info *
2686 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2687 {
2688         switch (cmd->modifier[0]) {
2689         case I915_FORMAT_MOD_Y_TILED_CCS:
2690         case I915_FORMAT_MOD_Yf_TILED_CCS:
2691                 return lookup_format_info(skl_ccs_formats,
2692                                           ARRAY_SIZE(skl_ccs_formats),
2693                                           cmd->pixel_format);
2694         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2695         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2696                 return lookup_format_info(gen12_ccs_formats,
2697                                           ARRAY_SIZE(gen12_ccs_formats),
2698                                           cmd->pixel_format);
2699         default:
2700                 return NULL;
2701         }
2702 }
2703
2704 bool is_ccs_modifier(u64 modifier)
2705 {
2706         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2707                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2708                modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2709                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2710 }
2711
2712 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2713 {
2714         return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2715                             512) * 64;
2716 }
2717
2718 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2719                               u32 pixel_format, u64 modifier)
2720 {
2721         struct intel_crtc *crtc;
2722         struct intel_plane *plane;
2723
2724         /*
2725          * We assume the primary plane for pipe A has
2726          * the highest stride limits of them all,
2727          * if in case pipe A is disabled, use the first pipe from pipe_mask.
2728          */
2729         crtc = intel_get_first_crtc(dev_priv);
2730         if (!crtc)
2731                 return 0;
2732
2733         plane = to_intel_plane(crtc->base.primary);
2734
2735         return plane->max_stride(plane, pixel_format, modifier,
2736                                  DRM_MODE_ROTATE_0);
2737 }
2738
2739 static
2740 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2741                         u32 pixel_format, u64 modifier)
2742 {
2743         /*
2744          * Arbitrary limit for gen4+ chosen to match the
2745          * render engine max stride.
2746          *
2747          * The new CCS hash mode makes remapping impossible
2748          */
2749         if (!is_ccs_modifier(modifier)) {
2750                 if (INTEL_GEN(dev_priv) >= 7)
2751                         return 256*1024;
2752                 else if (INTEL_GEN(dev_priv) >= 4)
2753                         return 128*1024;
2754         }
2755
2756         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2757 }
2758
2759 static u32
2760 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2761 {
2762         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2763         u32 tile_width;
2764
2765         if (is_surface_linear(fb, color_plane)) {
2766                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2767                                                            fb->format->format,
2768                                                            fb->modifier);
2769
2770                 /*
2771                  * To make remapping with linear generally feasible
2772                  * we need the stride to be page aligned.
2773                  */
2774                 if (fb->pitches[color_plane] > max_stride &&
2775                     !is_ccs_modifier(fb->modifier))
2776                         return intel_tile_size(dev_priv);
2777                 else
2778                         return 64;
2779         }
2780
2781         tile_width = intel_tile_width_bytes(fb, color_plane);
2782         if (is_ccs_modifier(fb->modifier)) {
2783                 /*
2784                  * Display WA #0531: skl,bxt,kbl,glk
2785                  *
2786                  * Render decompression and plane width > 3840
2787                  * combined with horizontal panning requires the
2788                  * plane stride to be a multiple of 4. We'll just
2789                  * require the entire fb to accommodate that to avoid
2790                  * potential runtime errors at plane configuration time.
2791                  */
2792                 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2793                         tile_width *= 4;
2794                 /*
2795                  * The main surface pitch must be padded to a multiple of four
2796                  * tile widths.
2797                  */
2798                 else if (INTEL_GEN(dev_priv) >= 12)
2799                         tile_width *= 4;
2800         }
2801         return tile_width;
2802 }
2803
2804 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2805 {
2806         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2807         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2808         const struct drm_framebuffer *fb = plane_state->hw.fb;
2809         int i;
2810
2811         /* We don't want to deal with remapping with cursors */
2812         if (plane->id == PLANE_CURSOR)
2813                 return false;
2814
2815         /*
2816          * The display engine limits already match/exceed the
2817          * render engine limits, so not much point in remapping.
2818          * Would also need to deal with the fence POT alignment
2819          * and gen2 2KiB GTT tile size.
2820          */
2821         if (INTEL_GEN(dev_priv) < 4)
2822                 return false;
2823
2824         /*
2825          * The new CCS hash mode isn't compatible with remapping as
2826          * the virtual address of the pages affects the compressed data.
2827          */
2828         if (is_ccs_modifier(fb->modifier))
2829                 return false;
2830
2831         /* Linear needs a page aligned stride for remapping */
2832         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2833                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2834
2835                 for (i = 0; i < fb->format->num_planes; i++) {
2836                         if (fb->pitches[i] & alignment)
2837                                 return false;
2838                 }
2839         }
2840
2841         return true;
2842 }
2843
2844 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2845 {
2846         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2847         const struct drm_framebuffer *fb = plane_state->hw.fb;
2848         unsigned int rotation = plane_state->hw.rotation;
2849         u32 stride, max_stride;
2850
2851         /*
2852          * No remapping for invisible planes since we don't have
2853          * an actual source viewport to remap.
2854          */
2855         if (!plane_state->uapi.visible)
2856                 return false;
2857
2858         if (!intel_plane_can_remap(plane_state))
2859                 return false;
2860
2861         /*
2862          * FIXME: aux plane limits on gen9+ are
2863          * unclear in Bspec, for now no checking.
2864          */
2865         stride = intel_fb_pitch(fb, 0, rotation);
2866         max_stride = plane->max_stride(plane, fb->format->format,
2867                                        fb->modifier, rotation);
2868
2869         return stride > max_stride;
2870 }
2871
2872 static void
2873 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2874                                const struct drm_framebuffer *fb,
2875                                int color_plane)
2876 {
2877         int main_plane;
2878
2879         if (color_plane == 0) {
2880                 *hsub = 1;
2881                 *vsub = 1;
2882
2883                 return;
2884         }
2885
2886         /*
2887          * TODO: Deduct the subsampling from the char block for all CCS
2888          * formats and planes.
2889          */
2890         if (!is_gen12_ccs_plane(fb, color_plane)) {
2891                 *hsub = fb->format->hsub;
2892                 *vsub = fb->format->vsub;
2893
2894                 return;
2895         }
2896
2897         main_plane = ccs_to_main_plane(fb, color_plane);
2898         *hsub = drm_format_info_block_width(fb->format, color_plane) /
2899                 drm_format_info_block_width(fb->format, main_plane);
2900
2901         /*
2902          * The min stride check in the core framebuffer_check() function
2903          * assumes that format->hsub applies to every plane except for the
2904          * first plane. That's incorrect for the CCS AUX plane of the first
2905          * plane, but for the above check to pass we must define the block
2906          * width with that subsampling applied to it. Adjust the width here
2907          * accordingly, so we can calculate the actual subsampling factor.
2908          */
2909         if (main_plane == 0)
2910                 *hsub *= fb->format->hsub;
2911
2912         *vsub = 32;
2913 }
2914 static int
2915 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2916 {
2917         struct drm_i915_private *i915 = to_i915(fb->dev);
2918         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2919         int main_plane;
2920         int hsub, vsub;
2921         int tile_width, tile_height;
2922         int ccs_x, ccs_y;
2923         int main_x, main_y;
2924
2925         if (!is_ccs_plane(fb, ccs_plane))
2926                 return 0;
2927
2928         intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2929         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2930
2931         tile_width *= hsub;
2932         tile_height *= vsub;
2933
2934         ccs_x = (x * hsub) % tile_width;
2935         ccs_y = (y * vsub) % tile_height;
2936
2937         main_plane = ccs_to_main_plane(fb, ccs_plane);
2938         main_x = intel_fb->normal[main_plane].x % tile_width;
2939         main_y = intel_fb->normal[main_plane].y % tile_height;
2940
2941         /*
2942          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2943          * x/y offsets must match between CCS and the main surface.
2944          */
2945         if (main_x != ccs_x || main_y != ccs_y) {
2946                 drm_dbg_kms(&i915->drm,
2947                               "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2948                               main_x, main_y,
2949                               ccs_x, ccs_y,
2950                               intel_fb->normal[main_plane].x,
2951                               intel_fb->normal[main_plane].y,
2952                               x, y);
2953                 return -EINVAL;
2954         }
2955
2956         return 0;
2957 }
2958
2959 static void
2960 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2961 {
2962         int main_plane = is_ccs_plane(fb, color_plane) ?
2963                          ccs_to_main_plane(fb, color_plane) : 0;
2964         int main_hsub, main_vsub;
2965         int hsub, vsub;
2966
2967         intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2968         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2969         *w = fb->width / main_hsub / hsub;
2970         *h = fb->height / main_vsub / vsub;
2971 }
2972
2973 /*
2974  * Setup the rotated view for an FB plane and return the size the GTT mapping
2975  * requires for this view.
2976  */
2977 static u32
2978 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2979                   u32 gtt_offset_rotated, int x, int y,
2980                   unsigned int width, unsigned int height,
2981                   unsigned int tile_size,
2982                   unsigned int tile_width, unsigned int tile_height,
2983                   struct drm_framebuffer *fb)
2984 {
2985         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2986         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2987         unsigned int pitch_tiles;
2988         struct drm_rect r;
2989
2990         /* Y or Yf modifiers required for 90/270 rotation */
2991         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2992             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
2993                 return 0;
2994
2995         if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
2996                 return 0;
2997
2998         rot_info->plane[plane] = *plane_info;
2999
3000         intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3001
3002         /* rotate the x/y offsets to match the GTT view */
3003         drm_rect_init(&r, x, y, width, height);
3004         drm_rect_rotate(&r,
3005                         plane_info->width * tile_width,
3006                         plane_info->height * tile_height,
3007                         DRM_MODE_ROTATE_270);
3008         x = r.x1;
3009         y = r.y1;
3010
3011         /* rotate the tile dimensions to match the GTT view */
3012         pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3013         swap(tile_width, tile_height);
3014
3015         /*
3016          * We only keep the x/y offsets, so push all of the
3017          * gtt offset into the x/y offsets.
3018          */
3019         intel_adjust_tile_offset(&x, &y,
3020                                  tile_width, tile_height,
3021                                  tile_size, pitch_tiles,
3022                                  gtt_offset_rotated * tile_size, 0);
3023
3024         /*
3025          * First pixel of the framebuffer from
3026          * the start of the rotated gtt mapping.
3027          */
3028         intel_fb->rotated[plane].x = x;
3029         intel_fb->rotated[plane].y = y;
3030
3031         return plane_info->width * plane_info->height;
3032 }
3033
3034 static int
3035 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3036                    struct drm_framebuffer *fb)
3037 {
3038         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3039         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3040         u32 gtt_offset_rotated = 0;
3041         unsigned int max_size = 0;
3042         int i, num_planes = fb->format->num_planes;
3043         unsigned int tile_size = intel_tile_size(dev_priv);
3044
3045         for (i = 0; i < num_planes; i++) {
3046                 unsigned int width, height;
3047                 unsigned int cpp, size;
3048                 u32 offset;
3049                 int x, y;
3050                 int ret;
3051
3052                 cpp = fb->format->cpp[i];
3053                 intel_fb_plane_dims(&width, &height, fb, i);
3054
3055                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3056                 if (ret) {
3057                         drm_dbg_kms(&dev_priv->drm,
3058                                     "bad fb plane %d offset: 0x%x\n",
3059                                     i, fb->offsets[i]);
3060                         return ret;
3061                 }
3062
3063                 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3064                 if (ret)
3065                         return ret;
3066
3067                 /*
3068                  * The fence (if used) is aligned to the start of the object
3069                  * so having the framebuffer wrap around across the edge of the
3070                  * fenced region doesn't really work. We have no API to configure
3071                  * the fence start offset within the object (nor could we probably
3072                  * on gen2/3). So it's just easier if we just require that the
3073                  * fb layout agrees with the fence layout. We already check that the
3074                  * fb stride matches the fence stride elsewhere.
3075                  */
3076                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3077                     (x + width) * cpp > fb->pitches[i]) {
3078                         drm_dbg_kms(&dev_priv->drm,
3079                                     "bad fb plane %d offset: 0x%x\n",
3080                                      i, fb->offsets[i]);
3081                         return -EINVAL;
3082                 }
3083
3084                 /*
3085                  * First pixel of the framebuffer from
3086                  * the start of the normal gtt mapping.
3087                  */
3088                 intel_fb->normal[i].x = x;
3089                 intel_fb->normal[i].y = y;
3090
3091                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3092                                                       fb->pitches[i],
3093                                                       DRM_MODE_ROTATE_0,
3094                                                       tile_size);
3095                 offset /= tile_size;
3096
3097                 if (!is_surface_linear(fb, i)) {
3098                         struct intel_remapped_plane_info plane_info;
3099                         unsigned int tile_width, tile_height;
3100
3101                         intel_tile_dims(fb, i, &tile_width, &tile_height);
3102
3103                         plane_info.offset = offset;
3104                         plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3105                                                          tile_width * cpp);
3106                         plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3107                         plane_info.height = DIV_ROUND_UP(y + height,
3108                                                          tile_height);
3109
3110                         /* how many tiles does this plane need */
3111                         size = plane_info.stride * plane_info.height;
3112                         /*
3113                          * If the plane isn't horizontally tile aligned,
3114                          * we need one more tile.
3115                          */
3116                         if (x != 0)
3117                                 size++;
3118
3119                         gtt_offset_rotated +=
3120                                 setup_fb_rotation(i, &plane_info,
3121                                                   gtt_offset_rotated,
3122                                                   x, y, width, height,
3123                                                   tile_size,
3124                                                   tile_width, tile_height,
3125                                                   fb);
3126                 } else {
3127                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3128                                             x * cpp, tile_size);
3129                 }
3130
3131                 /* how many tiles in total needed in the bo */
3132                 max_size = max(max_size, offset + size);
3133         }
3134
3135         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3136                 drm_dbg_kms(&dev_priv->drm,
3137                             "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3138                             mul_u32_u32(max_size, tile_size), obj->base.size);
3139                 return -EINVAL;
3140         }
3141
3142         return 0;
3143 }
3144
3145 static void
3146 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3147 {
3148         struct drm_i915_private *dev_priv =
3149                 to_i915(plane_state->uapi.plane->dev);
3150         struct drm_framebuffer *fb = plane_state->hw.fb;
3151         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3152         struct intel_rotation_info *info = &plane_state->view.rotated;
3153         unsigned int rotation = plane_state->hw.rotation;
3154         int i, num_planes = fb->format->num_planes;
3155         unsigned int tile_size = intel_tile_size(dev_priv);
3156         unsigned int src_x, src_y;
3157         unsigned int src_w, src_h;
3158         u32 gtt_offset = 0;
3159
3160         memset(&plane_state->view, 0, sizeof(plane_state->view));
3161         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3162                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3163
3164         src_x = plane_state->uapi.src.x1 >> 16;
3165         src_y = plane_state->uapi.src.y1 >> 16;
3166         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3167         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3168
3169         drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3170
3171         /* Make src coordinates relative to the viewport */
3172         drm_rect_translate(&plane_state->uapi.src,
3173                            -(src_x << 16), -(src_y << 16));
3174
3175         /* Rotate src coordinates to match rotated GTT view */
3176         if (drm_rotation_90_or_270(rotation))
3177                 drm_rect_rotate(&plane_state->uapi.src,
3178                                 src_w << 16, src_h << 16,
3179                                 DRM_MODE_ROTATE_270);
3180
3181         for (i = 0; i < num_planes; i++) {
3182                 unsigned int hsub = i ? fb->format->hsub : 1;
3183                 unsigned int vsub = i ? fb->format->vsub : 1;
3184                 unsigned int cpp = fb->format->cpp[i];
3185                 unsigned int tile_width, tile_height;
3186                 unsigned int width, height;
3187                 unsigned int pitch_tiles;
3188                 unsigned int x, y;
3189                 u32 offset;
3190
3191                 intel_tile_dims(fb, i, &tile_width, &tile_height);
3192
3193                 x = src_x / hsub;
3194                 y = src_y / vsub;
3195                 width = src_w / hsub;
3196                 height = src_h / vsub;
3197
3198                 /*
3199                  * First pixel of the src viewport from the
3200                  * start of the normal gtt mapping.
3201                  */
3202                 x += intel_fb->normal[i].x;
3203                 y += intel_fb->normal[i].y;
3204
3205                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3206                                                       fb, i, fb->pitches[i],
3207                                                       DRM_MODE_ROTATE_0, tile_size);
3208                 offset /= tile_size;
3209
3210                 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3211                 info->plane[i].offset = offset;
3212                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3213                                                      tile_width * cpp);
3214                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3215                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3216
3217                 if (drm_rotation_90_or_270(rotation)) {
3218                         struct drm_rect r;
3219
3220                         /* rotate the x/y offsets to match the GTT view */
3221                         drm_rect_init(&r, x, y, width, height);
3222                         drm_rect_rotate(&r,
3223                                         info->plane[i].width * tile_width,
3224                                         info->plane[i].height * tile_height,
3225                                         DRM_MODE_ROTATE_270);
3226                         x = r.x1;
3227                         y = r.y1;
3228
3229                         pitch_tiles = info->plane[i].height;
3230                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3231
3232                         /* rotate the tile dimensions to match the GTT view */
3233                         swap(tile_width, tile_height);
3234                 } else {
3235                         pitch_tiles = info->plane[i].width;
3236                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3237                 }
3238
3239                 /*
3240                  * We only keep the x/y offsets, so push all of the
3241                  * gtt offset into the x/y offsets.
3242                  */
3243                 intel_adjust_tile_offset(&x, &y,
3244                                          tile_width, tile_height,
3245                                          tile_size, pitch_tiles,
3246                                          gtt_offset * tile_size, 0);
3247
3248                 gtt_offset += info->plane[i].width * info->plane[i].height;
3249
3250                 plane_state->color_plane[i].offset = 0;
3251                 plane_state->color_plane[i].x = x;
3252                 plane_state->color_plane[i].y = y;
3253         }
3254 }
3255
3256 static int
3257 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3258 {
3259         const struct intel_framebuffer *fb =
3260                 to_intel_framebuffer(plane_state->hw.fb);
3261         unsigned int rotation = plane_state->hw.rotation;
3262         int i, num_planes;
3263
3264         if (!fb)
3265                 return 0;
3266
3267         num_planes = fb->base.format->num_planes;
3268
3269         if (intel_plane_needs_remap(plane_state)) {
3270                 intel_plane_remap_gtt(plane_state);
3271
3272                 /*
3273                  * Sometimes even remapping can't overcome
3274                  * the stride limitations :( Can happen with
3275                  * big plane sizes and suitably misaligned
3276                  * offsets.
3277                  */
3278                 return intel_plane_check_stride(plane_state);
3279         }
3280
3281         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3282
3283         for (i = 0; i < num_planes; i++) {
3284                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3285                 plane_state->color_plane[i].offset = 0;
3286
3287                 if (drm_rotation_90_or_270(rotation)) {
3288                         plane_state->color_plane[i].x = fb->rotated[i].x;
3289                         plane_state->color_plane[i].y = fb->rotated[i].y;
3290                 } else {
3291                         plane_state->color_plane[i].x = fb->normal[i].x;
3292                         plane_state->color_plane[i].y = fb->normal[i].y;
3293                 }
3294         }
3295
3296         /* Rotate src coordinates to match rotated GTT view */
3297         if (drm_rotation_90_or_270(rotation))
3298                 drm_rect_rotate(&plane_state->uapi.src,
3299                                 fb->base.width << 16, fb->base.height << 16,
3300                                 DRM_MODE_ROTATE_270);
3301
3302         return intel_plane_check_stride(plane_state);
3303 }
3304
3305 static int i9xx_format_to_fourcc(int format)
3306 {
3307         switch (format) {
3308         case DISPPLANE_8BPP:
3309                 return DRM_FORMAT_C8;
3310         case DISPPLANE_BGRA555:
3311                 return DRM_FORMAT_ARGB1555;
3312         case DISPPLANE_BGRX555:
3313                 return DRM_FORMAT_XRGB1555;
3314         case DISPPLANE_BGRX565:
3315                 return DRM_FORMAT_RGB565;
3316         default:
3317         case DISPPLANE_BGRX888:
3318                 return DRM_FORMAT_XRGB8888;
3319         case DISPPLANE_RGBX888:
3320                 return DRM_FORMAT_XBGR8888;
3321         case DISPPLANE_BGRA888:
3322                 return DRM_FORMAT_ARGB8888;
3323         case DISPPLANE_RGBA888:
3324                 return DRM_FORMAT_ABGR8888;
3325         case DISPPLANE_BGRX101010:
3326                 return DRM_FORMAT_XRGB2101010;
3327         case DISPPLANE_RGBX101010:
3328                 return DRM_FORMAT_XBGR2101010;
3329         case DISPPLANE_BGRA101010:
3330                 return DRM_FORMAT_ARGB2101010;
3331         case DISPPLANE_RGBA101010:
3332                 return DRM_FORMAT_ABGR2101010;
3333         case DISPPLANE_RGBX161616:
3334                 return DRM_FORMAT_XBGR16161616F;
3335         }
3336 }
3337
3338 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3339 {
3340         switch (format) {
3341         case PLANE_CTL_FORMAT_RGB_565:
3342                 return DRM_FORMAT_RGB565;
3343         case PLANE_CTL_FORMAT_NV12:
3344                 return DRM_FORMAT_NV12;
3345         case PLANE_CTL_FORMAT_XYUV:
3346                 return DRM_FORMAT_XYUV8888;
3347         case PLANE_CTL_FORMAT_P010:
3348                 return DRM_FORMAT_P010;
3349         case PLANE_CTL_FORMAT_P012:
3350                 return DRM_FORMAT_P012;
3351         case PLANE_CTL_FORMAT_P016:
3352                 return DRM_FORMAT_P016;
3353         case PLANE_CTL_FORMAT_Y210:
3354                 return DRM_FORMAT_Y210;
3355         case PLANE_CTL_FORMAT_Y212:
3356                 return DRM_FORMAT_Y212;
3357         case PLANE_CTL_FORMAT_Y216:
3358                 return DRM_FORMAT_Y216;
3359         case PLANE_CTL_FORMAT_Y410:
3360                 return DRM_FORMAT_XVYU2101010;
3361         case PLANE_CTL_FORMAT_Y412:
3362                 return DRM_FORMAT_XVYU12_16161616;
3363         case PLANE_CTL_FORMAT_Y416:
3364                 return DRM_FORMAT_XVYU16161616;
3365         default:
3366         case PLANE_CTL_FORMAT_XRGB_8888:
3367                 if (rgb_order) {
3368                         if (alpha)
3369                                 return DRM_FORMAT_ABGR8888;
3370                         else
3371                                 return DRM_FORMAT_XBGR8888;
3372                 } else {
3373                         if (alpha)
3374                                 return DRM_FORMAT_ARGB8888;
3375                         else
3376                                 return DRM_FORMAT_XRGB8888;
3377                 }
3378         case PLANE_CTL_FORMAT_XRGB_2101010:
3379                 if (rgb_order) {
3380                         if (alpha)
3381                                 return DRM_FORMAT_ABGR2101010;
3382                         else
3383                                 return DRM_FORMAT_XBGR2101010;
3384                 } else {
3385                         if (alpha)
3386                                 return DRM_FORMAT_ARGB2101010;
3387                         else
3388                                 return DRM_FORMAT_XRGB2101010;
3389                 }
3390         case PLANE_CTL_FORMAT_XRGB_16161616F:
3391                 if (rgb_order) {
3392                         if (alpha)
3393                                 return DRM_FORMAT_ABGR16161616F;
3394                         else
3395                                 return DRM_FORMAT_XBGR16161616F;
3396                 } else {
3397                         if (alpha)
3398                                 return DRM_FORMAT_ARGB16161616F;
3399                         else
3400                                 return DRM_FORMAT_XRGB16161616F;
3401                 }
3402         }
3403 }
3404
3405 static struct i915_vma *
3406 initial_plane_vma(struct drm_i915_private *i915,
3407                   struct intel_initial_plane_config *plane_config)
3408 {
3409         struct drm_i915_gem_object *obj;
3410         struct i915_vma *vma;
3411         u32 base, size;
3412
3413         if (plane_config->size == 0)
3414                 return NULL;
3415
3416         base = round_down(plane_config->base,
3417                           I915_GTT_MIN_ALIGNMENT);
3418         size = round_up(plane_config->base + plane_config->size,
3419                         I915_GTT_MIN_ALIGNMENT);
3420         size -= base;
3421
3422         /*
3423          * If the FB is too big, just don't use it since fbdev is not very
3424          * important and we should probably use that space with FBC or other
3425          * features.
3426          */
3427         if (size * 2 > i915->stolen_usable_size)
3428                 return NULL;
3429
3430         obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3431         if (IS_ERR(obj))
3432                 return NULL;
3433
3434         switch (plane_config->tiling) {
3435         case I915_TILING_NONE:
3436                 break;
3437         case I915_TILING_X:
3438         case I915_TILING_Y:
3439                 obj->tiling_and_stride =
3440                         plane_config->fb->base.pitches[0] |
3441                         plane_config->tiling;
3442                 break;
3443         default:
3444                 MISSING_CASE(plane_config->tiling);
3445                 goto err_obj;
3446         }
3447
3448         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3449         if (IS_ERR(vma))
3450                 goto err_obj;
3451
3452         if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3453                 goto err_obj;
3454
3455         if (i915_gem_object_is_tiled(obj) &&
3456             !i915_vma_is_map_and_fenceable(vma))
3457                 goto err_obj;
3458
3459         return vma;
3460
3461 err_obj:
3462         i915_gem_object_put(obj);
3463         return NULL;
3464 }
3465
3466 static bool
3467 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3468                               struct intel_initial_plane_config *plane_config)
3469 {
3470         struct drm_device *dev = crtc->base.dev;
3471         struct drm_i915_private *dev_priv = to_i915(dev);
3472         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3473         struct drm_framebuffer *fb = &plane_config->fb->base;
3474         struct i915_vma *vma;
3475
3476         switch (fb->modifier) {
3477         case DRM_FORMAT_MOD_LINEAR:
3478         case I915_FORMAT_MOD_X_TILED:
3479         case I915_FORMAT_MOD_Y_TILED:
3480                 break;
3481         default:
3482                 drm_dbg(&dev_priv->drm,
3483                         "Unsupported modifier for initial FB: 0x%llx\n",
3484                         fb->modifier);
3485                 return false;
3486         }
3487
3488         vma = initial_plane_vma(dev_priv, plane_config);
3489         if (!vma)
3490                 return false;
3491
3492         mode_cmd.pixel_format = fb->format->format;
3493         mode_cmd.width = fb->width;
3494         mode_cmd.height = fb->height;
3495         mode_cmd.pitches[0] = fb->pitches[0];
3496         mode_cmd.modifier[0] = fb->modifier;
3497         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3498
3499         if (intel_framebuffer_init(to_intel_framebuffer(fb),
3500                                    vma->obj, &mode_cmd)) {
3501                 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3502                 goto err_vma;
3503         }
3504
3505         plane_config->vma = vma;
3506         return true;
3507
3508 err_vma:
3509         i915_vma_put(vma);
3510         return false;
3511 }
3512
3513 static void
3514 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3515                         struct intel_plane_state *plane_state,
3516                         bool visible)
3517 {
3518         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3519
3520         plane_state->uapi.visible = visible;
3521
3522         if (visible)
3523                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3524         else
3525                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3526 }
3527
3528 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3529 {
3530         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3531         struct drm_plane *plane;
3532
3533         /*
3534          * Active_planes aliases if multiple "primary" or cursor planes
3535          * have been used on the same (or wrong) pipe. plane_mask uses
3536          * unique ids, hence we can use that to reconstruct active_planes.
3537          */
3538         crtc_state->active_planes = 0;
3539
3540         drm_for_each_plane_mask(plane, &dev_priv->drm,
3541                                 crtc_state->uapi.plane_mask)
3542                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3543 }
3544
3545 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3546                                          struct intel_plane *plane)
3547 {
3548         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3549         struct intel_crtc_state *crtc_state =
3550                 to_intel_crtc_state(crtc->base.state);
3551         struct intel_plane_state *plane_state =
3552                 to_intel_plane_state(plane->base.state);
3553
3554         drm_dbg_kms(&dev_priv->drm,
3555                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3556                     plane->base.base.id, plane->base.name,
3557                     crtc->base.base.id, crtc->base.name);
3558
3559         intel_set_plane_visible(crtc_state, plane_state, false);
3560         fixup_active_planes(crtc_state);
3561         crtc_state->data_rate[plane->id] = 0;
3562         crtc_state->min_cdclk[plane->id] = 0;
3563
3564         if (plane->id == PLANE_PRIMARY)
3565                 hsw_disable_ips(crtc_state);
3566
3567         /*
3568          * Vblank time updates from the shadow to live plane control register
3569          * are blocked if the memory self-refresh mode is active at that
3570          * moment. So to make sure the plane gets truly disabled, disable
3571          * first the self-refresh mode. The self-refresh enable bit in turn
3572          * will be checked/applied by the HW only at the next frame start
3573          * event which is after the vblank start event, so we need to have a
3574          * wait-for-vblank between disabling the plane and the pipe.
3575          */
3576         if (HAS_GMCH(dev_priv) &&
3577             intel_set_memory_cxsr(dev_priv, false))
3578                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3579
3580         /*
3581          * Gen2 reports pipe underruns whenever all planes are disabled.
3582          * So disable underrun reporting before all the planes get disabled.
3583          */
3584         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3585                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3586
3587         intel_disable_plane(plane, crtc_state);
3588 }
3589
3590 static struct intel_frontbuffer *
3591 to_intel_frontbuffer(struct drm_framebuffer *fb)
3592 {
3593         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3594 }
3595
3596 static void
3597 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3598                              struct intel_initial_plane_config *plane_config)
3599 {
3600         struct drm_device *dev = intel_crtc->base.dev;
3601         struct drm_i915_private *dev_priv = to_i915(dev);
3602         struct drm_crtc *c;
3603         struct drm_plane *primary = intel_crtc->base.primary;
3604         struct drm_plane_state *plane_state = primary->state;
3605         struct intel_plane *intel_plane = to_intel_plane(primary);
3606         struct intel_plane_state *intel_state =
3607                 to_intel_plane_state(plane_state);
3608         struct drm_framebuffer *fb;
3609         struct i915_vma *vma;
3610
3611         if (!plane_config->fb)
3612                 return;
3613
3614         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3615                 fb = &plane_config->fb->base;
3616                 vma = plane_config->vma;
3617                 goto valid_fb;
3618         }
3619
3620         /*
3621          * Failed to alloc the obj, check to see if we should share
3622          * an fb with another CRTC instead
3623          */
3624         for_each_crtc(dev, c) {
3625                 struct intel_plane_state *state;
3626
3627                 if (c == &intel_crtc->base)
3628                         continue;
3629
3630                 if (!to_intel_crtc(c)->active)
3631                         continue;
3632
3633                 state = to_intel_plane_state(c->primary->state);
3634                 if (!state->vma)
3635                         continue;
3636
3637                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3638                         fb = state->hw.fb;
3639                         vma = state->vma;
3640                         goto valid_fb;
3641                 }
3642         }
3643
3644         /*
3645          * We've failed to reconstruct the BIOS FB.  Current display state
3646          * indicates that the primary plane is visible, but has a NULL FB,
3647          * which will lead to problems later if we don't fix it up.  The
3648          * simplest solution is to just disable the primary plane now and
3649          * pretend the BIOS never had it enabled.
3650          */
3651         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3652
3653         return;
3654
3655 valid_fb:
3656         intel_state->hw.rotation = plane_config->rotation;
3657         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3658                                 intel_state->hw.rotation);
3659         intel_state->color_plane[0].stride =
3660                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3661
3662         __i915_vma_pin(vma);
3663         intel_state->vma = i915_vma_get(vma);
3664         if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3665                 if (vma->fence)
3666                         intel_state->flags |= PLANE_HAS_FENCE;
3667
3668         plane_state->src_x = 0;
3669         plane_state->src_y = 0;
3670         plane_state->src_w = fb->width << 16;
3671         plane_state->src_h = fb->height << 16;
3672
3673         plane_state->crtc_x = 0;
3674         plane_state->crtc_y = 0;
3675         plane_state->crtc_w = fb->width;
3676         plane_state->crtc_h = fb->height;
3677
3678         intel_state->uapi.src = drm_plane_state_src(plane_state);
3679         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3680
3681         if (plane_config->tiling)
3682                 dev_priv->preserve_bios_swizzle = true;
3683
3684         plane_state->fb = fb;
3685         drm_framebuffer_get(fb);
3686
3687         plane_state->crtc = &intel_crtc->base;
3688         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3689
3690         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3691
3692         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3693                   &to_intel_frontbuffer(fb)->bits);
3694 }
3695
3696 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3697                                int color_plane,
3698                                unsigned int rotation)
3699 {
3700         int cpp = fb->format->cpp[color_plane];
3701
3702         switch (fb->modifier) {
3703         case DRM_FORMAT_MOD_LINEAR:
3704         case I915_FORMAT_MOD_X_TILED:
3705                 /*
3706                  * Validated limit is 4k, but has 5k should
3707                  * work apart from the following features:
3708                  * - Ytile (already limited to 4k)
3709                  * - FP16 (already limited to 4k)
3710                  * - render compression (already limited to 4k)
3711                  * - KVMR sprite and cursor (don't care)
3712                  * - horizontal panning (TODO verify this)
3713                  * - pipe and plane scaling (TODO verify this)
3714                  */
3715                 if (cpp == 8)
3716                         return 4096;
3717                 else
3718                         return 5120;
3719         case I915_FORMAT_MOD_Y_TILED_CCS:
3720         case I915_FORMAT_MOD_Yf_TILED_CCS:
3721         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3722                 /* FIXME AUX plane? */
3723         case I915_FORMAT_MOD_Y_TILED:
3724         case I915_FORMAT_MOD_Yf_TILED:
3725                 if (cpp == 8)
3726                         return 2048;
3727                 else
3728                         return 4096;
3729         default:
3730                 MISSING_CASE(fb->modifier);
3731                 return 2048;
3732         }
3733 }
3734
3735 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3736                                int color_plane,
3737                                unsigned int rotation)
3738 {
3739         int cpp = fb->format->cpp[color_plane];
3740
3741         switch (fb->modifier) {
3742         case DRM_FORMAT_MOD_LINEAR:
3743         case I915_FORMAT_MOD_X_TILED:
3744                 if (cpp == 8)
3745                         return 4096;
3746                 else
3747                         return 5120;
3748         case I915_FORMAT_MOD_Y_TILED_CCS:
3749         case I915_FORMAT_MOD_Yf_TILED_CCS:
3750                 /* FIXME AUX plane? */
3751         case I915_FORMAT_MOD_Y_TILED:
3752         case I915_FORMAT_MOD_Yf_TILED:
3753                 if (cpp == 8)
3754                         return 2048;
3755                 else
3756                         return 5120;
3757         default:
3758                 MISSING_CASE(fb->modifier);
3759                 return 2048;
3760         }
3761 }
3762
3763 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3764                                int color_plane,
3765                                unsigned int rotation)
3766 {
3767         return 5120;
3768 }
3769
3770 static int skl_max_plane_height(void)
3771 {
3772         return 4096;
3773 }
3774
3775 static int icl_max_plane_height(void)
3776 {
3777         return 4320;
3778 }
3779
3780 static bool
3781 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3782                                int main_x, int main_y, u32 main_offset,
3783                                int ccs_plane)
3784 {
3785         const struct drm_framebuffer *fb = plane_state->hw.fb;
3786         int aux_x = plane_state->color_plane[ccs_plane].x;
3787         int aux_y = plane_state->color_plane[ccs_plane].y;
3788         u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3789         u32 alignment = intel_surf_alignment(fb, ccs_plane);
3790         int hsub;
3791         int vsub;
3792
3793         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3794         while (aux_offset >= main_offset && aux_y <= main_y) {
3795                 int x, y;
3796
3797                 if (aux_x == main_x && aux_y == main_y)
3798                         break;
3799
3800                 if (aux_offset == 0)
3801                         break;
3802
3803                 x = aux_x / hsub;
3804                 y = aux_y / vsub;
3805                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3806                                                                plane_state,
3807                                                                ccs_plane,
3808                                                                aux_offset,
3809                                                                aux_offset -
3810                                                                 alignment);
3811                 aux_x = x * hsub + aux_x % hsub;
3812                 aux_y = y * vsub + aux_y % vsub;
3813         }
3814
3815         if (aux_x != main_x || aux_y != main_y)
3816                 return false;
3817
3818         plane_state->color_plane[ccs_plane].offset = aux_offset;
3819         plane_state->color_plane[ccs_plane].x = aux_x;
3820         plane_state->color_plane[ccs_plane].y = aux_y;
3821
3822         return true;
3823 }
3824
3825 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3826 {
3827         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3828         const struct drm_framebuffer *fb = plane_state->hw.fb;
3829         unsigned int rotation = plane_state->hw.rotation;
3830         int x = plane_state->uapi.src.x1 >> 16;
3831         int y = plane_state->uapi.src.y1 >> 16;
3832         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3833         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3834         int max_width;
3835         int max_height;
3836         u32 alignment;
3837         u32 offset;
3838         int aux_plane = intel_main_to_aux_plane(fb, 0);
3839         u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3840
3841         if (INTEL_GEN(dev_priv) >= 11)
3842                 max_width = icl_max_plane_width(fb, 0, rotation);
3843         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3844                 max_width = glk_max_plane_width(fb, 0, rotation);
3845         else
3846                 max_width = skl_max_plane_width(fb, 0, rotation);
3847
3848         if (INTEL_GEN(dev_priv) >= 11)
3849                 max_height = icl_max_plane_height();
3850         else
3851                 max_height = skl_max_plane_height();
3852
3853         if (w > max_width || h > max_height) {
3854                 drm_dbg_kms(&dev_priv->drm,
3855                             "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3856                             w, h, max_width, max_height);
3857                 return -EINVAL;
3858         }
3859
3860         intel_add_fb_offsets(&x, &y, plane_state, 0);
3861         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3862         alignment = intel_surf_alignment(fb, 0);
3863         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3864                 return -EINVAL;
3865
3866         /*
3867          * AUX surface offset is specified as the distance from the
3868          * main surface offset, and it must be non-negative. Make
3869          * sure that is what we will get.
3870          */
3871         if (offset > aux_offset)
3872                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3873                                                            offset, aux_offset & ~(alignment - 1));
3874
3875         /*
3876          * When using an X-tiled surface, the plane blows up
3877          * if the x offset + width exceed the stride.
3878          *
3879          * TODO: linear and Y-tiled seem fine, Yf untested,
3880          */
3881         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3882                 int cpp = fb->format->cpp[0];
3883
3884                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3885                         if (offset == 0) {
3886                                 drm_dbg_kms(&dev_priv->drm,
3887                                             "Unable to find suitable display surface offset due to X-tiling\n");
3888                                 return -EINVAL;
3889                         }
3890
3891                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3892                                                                    offset, offset - alignment);
3893                 }
3894         }
3895
3896         /*
3897          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3898          * they match with the main surface x/y offsets.
3899          */
3900         if (is_ccs_modifier(fb->modifier)) {
3901                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3902                                                        offset, aux_plane)) {
3903                         if (offset == 0)
3904                                 break;
3905
3906                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3907                                                                    offset, offset - alignment);
3908                 }
3909
3910                 if (x != plane_state->color_plane[aux_plane].x ||
3911                     y != plane_state->color_plane[aux_plane].y) {
3912                         drm_dbg_kms(&dev_priv->drm,
3913                                     "Unable to find suitable display surface offset due to CCS\n");
3914                         return -EINVAL;
3915                 }
3916         }
3917
3918         plane_state->color_plane[0].offset = offset;
3919         plane_state->color_plane[0].x = x;
3920         plane_state->color_plane[0].y = y;
3921
3922         /*
3923          * Put the final coordinates back so that the src
3924          * coordinate checks will see the right values.
3925          */
3926         drm_rect_translate_to(&plane_state->uapi.src,
3927                               x << 16, y << 16);
3928
3929         return 0;
3930 }
3931
3932 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3933 {
3934         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
3935         const struct drm_framebuffer *fb = plane_state->hw.fb;
3936         unsigned int rotation = plane_state->hw.rotation;
3937         int uv_plane = 1;
3938         int max_width = skl_max_plane_width(fb, uv_plane, rotation);
3939         int max_height = 4096;
3940         int x = plane_state->uapi.src.x1 >> 17;
3941         int y = plane_state->uapi.src.y1 >> 17;
3942         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3943         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3944         u32 offset;
3945
3946         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
3947         offset = intel_plane_compute_aligned_offset(&x, &y,
3948                                                     plane_state, uv_plane);
3949
3950         /* FIXME not quite sure how/if these apply to the chroma plane */
3951         if (w > max_width || h > max_height) {
3952                 drm_dbg_kms(&i915->drm,
3953                             "CbCr source size %dx%d too big (limit %dx%d)\n",
3954                             w, h, max_width, max_height);
3955                 return -EINVAL;
3956         }
3957
3958         if (is_ccs_modifier(fb->modifier)) {
3959                 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
3960                 int aux_offset = plane_state->color_plane[ccs_plane].offset;
3961                 int alignment = intel_surf_alignment(fb, uv_plane);
3962
3963                 if (offset > aux_offset)
3964                         offset = intel_plane_adjust_aligned_offset(&x, &y,
3965                                                                    plane_state,
3966                                                                    uv_plane,
3967                                                                    offset,
3968                                                                    aux_offset & ~(alignment - 1));
3969
3970                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3971                                                        offset, ccs_plane)) {
3972                         if (offset == 0)
3973                                 break;
3974
3975                         offset = intel_plane_adjust_aligned_offset(&x, &y,
3976                                                                    plane_state,
3977                                                                    uv_plane,
3978                                                                    offset, offset - alignment);
3979                 }
3980
3981                 if (x != plane_state->color_plane[ccs_plane].x ||
3982                     y != plane_state->color_plane[ccs_plane].y) {
3983                         drm_dbg_kms(&i915->drm,
3984                                     "Unable to find suitable display surface offset due to CCS\n");
3985                         return -EINVAL;
3986                 }
3987         }
3988
3989         plane_state->color_plane[uv_plane].offset = offset;
3990         plane_state->color_plane[uv_plane].x = x;
3991         plane_state->color_plane[uv_plane].y = y;
3992
3993         return 0;
3994 }
3995
3996 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3997 {
3998         const struct drm_framebuffer *fb = plane_state->hw.fb;
3999         int src_x = plane_state->uapi.src.x1 >> 16;
4000         int src_y = plane_state->uapi.src.y1 >> 16;
4001         u32 offset;
4002         int ccs_plane;
4003
4004         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4005                 int main_hsub, main_vsub;
4006                 int hsub, vsub;
4007                 int x, y;
4008
4009                 if (!is_ccs_plane(fb, ccs_plane))
4010                         continue;
4011
4012                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4013                                                ccs_to_main_plane(fb, ccs_plane));
4014                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4015
4016                 hsub *= main_hsub;
4017                 vsub *= main_vsub;
4018                 x = src_x / hsub;
4019                 y = src_y / vsub;
4020
4021                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4022
4023                 offset = intel_plane_compute_aligned_offset(&x, &y,
4024                                                             plane_state,
4025                                                             ccs_plane);
4026
4027                 plane_state->color_plane[ccs_plane].offset = offset;
4028                 plane_state->color_plane[ccs_plane].x = (x * hsub +
4029                                                          src_x % hsub) /
4030                                                         main_hsub;
4031                 plane_state->color_plane[ccs_plane].y = (y * vsub +
4032                                                          src_y % vsub) /
4033                                                         main_vsub;
4034         }
4035
4036         return 0;
4037 }
4038
4039 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4040 {
4041         const struct drm_framebuffer *fb = plane_state->hw.fb;
4042         int ret;
4043         bool needs_aux = false;
4044
4045         ret = intel_plane_compute_gtt(plane_state);
4046         if (ret)
4047                 return ret;
4048
4049         if (!plane_state->uapi.visible)
4050                 return 0;
4051
4052         /*
4053          * Handle the AUX surface first since the main surface setup depends on
4054          * it.
4055          */
4056         if (is_ccs_modifier(fb->modifier)) {
4057                 needs_aux = true;
4058                 ret = skl_check_ccs_aux_surface(plane_state);
4059                 if (ret)
4060                         return ret;
4061         }
4062
4063         if (intel_format_info_is_yuv_semiplanar(fb->format,
4064                                                 fb->modifier)) {
4065                 needs_aux = true;
4066                 ret = skl_check_nv12_aux_surface(plane_state);
4067                 if (ret)
4068                         return ret;
4069         }
4070
4071         if (!needs_aux) {
4072                 int i;
4073
4074                 for (i = 1; i < fb->format->num_planes; i++) {
4075                         plane_state->color_plane[i].offset = ~0xfff;
4076                         plane_state->color_plane[i].x = 0;
4077                         plane_state->color_plane[i].y = 0;
4078                 }
4079         }
4080
4081         ret = skl_check_main_surface(plane_state);
4082         if (ret)
4083                 return ret;
4084
4085         return 0;
4086 }
4087
4088 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4089                              const struct intel_plane_state *plane_state,
4090                              unsigned int *num, unsigned int *den)
4091 {
4092         const struct drm_framebuffer *fb = plane_state->hw.fb;
4093         unsigned int cpp = fb->format->cpp[0];
4094
4095         /*
4096          * g4x bspec says 64bpp pixel rate can't exceed 80%
4097          * of cdclk when the sprite plane is enabled on the
4098          * same pipe. ilk/snb bspec says 64bpp pixel rate is
4099          * never allowed to exceed 80% of cdclk. Let's just go
4100          * with the ilk/snb limit always.
4101          */
4102         if (cpp == 8) {
4103                 *num = 10;
4104                 *den = 8;
4105         } else {
4106                 *num = 1;
4107                 *den = 1;
4108         }
4109 }
4110
4111 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4112                                 const struct intel_plane_state *plane_state)
4113 {
4114         unsigned int pixel_rate;
4115         unsigned int num, den;
4116
4117         /*
4118          * Note that crtc_state->pixel_rate accounts for both
4119          * horizontal and vertical panel fitter downscaling factors.
4120          * Pre-HSW bspec tells us to only consider the horizontal
4121          * downscaling factor here. We ignore that and just consider
4122          * both for simplicity.
4123          */
4124         pixel_rate = crtc_state->pixel_rate;
4125
4126         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4127
4128         /* two pixels per clock with double wide pipe */
4129         if (crtc_state->double_wide)
4130                 den *= 2;
4131
4132         return DIV_ROUND_UP(pixel_rate * num, den);
4133 }
4134
4135 unsigned int
4136 i9xx_plane_max_stride(struct intel_plane *plane,
4137                       u32 pixel_format, u64 modifier,
4138                       unsigned int rotation)
4139 {
4140         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4141
4142         if (!HAS_GMCH(dev_priv)) {
4143                 return 32*1024;
4144         } else if (INTEL_GEN(dev_priv) >= 4) {
4145                 if (modifier == I915_FORMAT_MOD_X_TILED)
4146                         return 16*1024;
4147                 else
4148                         return 32*1024;
4149         } else if (INTEL_GEN(dev_priv) >= 3) {
4150                 if (modifier == I915_FORMAT_MOD_X_TILED)
4151                         return 8*1024;
4152                 else
4153                         return 16*1024;
4154         } else {
4155                 if (plane->i9xx_plane == PLANE_C)
4156                         return 4*1024;
4157                 else
4158                         return 8*1024;
4159         }
4160 }
4161
4162 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4163 {
4164         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4165         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4166         u32 dspcntr = 0;
4167
4168         if (crtc_state->gamma_enable)
4169                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4170
4171         if (crtc_state->csc_enable)
4172                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4173
4174         if (INTEL_GEN(dev_priv) < 5)
4175                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4176
4177         return dspcntr;
4178 }
4179
4180 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4181                           const struct intel_plane_state *plane_state)
4182 {
4183         struct drm_i915_private *dev_priv =
4184                 to_i915(plane_state->uapi.plane->dev);
4185         const struct drm_framebuffer *fb = plane_state->hw.fb;
4186         unsigned int rotation = plane_state->hw.rotation;
4187         u32 dspcntr;
4188
4189         dspcntr = DISPLAY_PLANE_ENABLE;
4190
4191         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4192             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4193                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4194
4195         switch (fb->format->format) {
4196         case DRM_FORMAT_C8:
4197                 dspcntr |= DISPPLANE_8BPP;
4198                 break;
4199         case DRM_FORMAT_XRGB1555:
4200                 dspcntr |= DISPPLANE_BGRX555;
4201                 break;
4202         case DRM_FORMAT_ARGB1555:
4203                 dspcntr |= DISPPLANE_BGRA555;
4204                 break;
4205         case DRM_FORMAT_RGB565:
4206                 dspcntr |= DISPPLANE_BGRX565;
4207                 break;
4208         case DRM_FORMAT_XRGB8888:
4209                 dspcntr |= DISPPLANE_BGRX888;
4210                 break;
4211         case DRM_FORMAT_XBGR8888:
4212                 dspcntr |= DISPPLANE_RGBX888;
4213                 break;
4214         case DRM_FORMAT_ARGB8888:
4215                 dspcntr |= DISPPLANE_BGRA888;
4216                 break;
4217         case DRM_FORMAT_ABGR8888:
4218                 dspcntr |= DISPPLANE_RGBA888;
4219                 break;
4220         case DRM_FORMAT_XRGB2101010:
4221                 dspcntr |= DISPPLANE_BGRX101010;
4222                 break;
4223         case DRM_FORMAT_XBGR2101010:
4224                 dspcntr |= DISPPLANE_RGBX101010;
4225                 break;
4226         case DRM_FORMAT_ARGB2101010:
4227                 dspcntr |= DISPPLANE_BGRA101010;
4228                 break;
4229         case DRM_FORMAT_ABGR2101010:
4230                 dspcntr |= DISPPLANE_RGBA101010;
4231                 break;
4232         case DRM_FORMAT_XBGR16161616F:
4233                 dspcntr |= DISPPLANE_RGBX161616;
4234                 break;
4235         default:
4236                 MISSING_CASE(fb->format->format);
4237                 return 0;
4238         }
4239
4240         if (INTEL_GEN(dev_priv) >= 4 &&
4241             fb->modifier == I915_FORMAT_MOD_X_TILED)
4242                 dspcntr |= DISPPLANE_TILED;
4243
4244         if (rotation & DRM_MODE_ROTATE_180)
4245                 dspcntr |= DISPPLANE_ROTATE_180;
4246
4247         if (rotation & DRM_MODE_REFLECT_X)
4248                 dspcntr |= DISPPLANE_MIRROR;
4249
4250         return dspcntr;
4251 }
4252
4253 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4254 {
4255         struct drm_i915_private *dev_priv =
4256                 to_i915(plane_state->uapi.plane->dev);
4257         const struct drm_framebuffer *fb = plane_state->hw.fb;
4258         int src_x, src_y, src_w;
4259         u32 offset;
4260         int ret;
4261
4262         ret = intel_plane_compute_gtt(plane_state);
4263         if (ret)
4264                 return ret;
4265
4266         if (!plane_state->uapi.visible)
4267                 return 0;
4268
4269         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4270         src_x = plane_state->uapi.src.x1 >> 16;
4271         src_y = plane_state->uapi.src.y1 >> 16;
4272
4273         /* Undocumented hardware limit on i965/g4x/vlv/chv */
4274         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4275                 return -EINVAL;
4276
4277         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4278
4279         if (INTEL_GEN(dev_priv) >= 4)
4280                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4281                                                             plane_state, 0);
4282         else
4283                 offset = 0;
4284
4285         /*
4286          * Put the final coordinates back so that the src
4287          * coordinate checks will see the right values.
4288          */
4289         drm_rect_translate_to(&plane_state->uapi.src,
4290                               src_x << 16, src_y << 16);
4291
4292         /* HSW/BDW do this automagically in hardware */
4293         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4294                 unsigned int rotation = plane_state->hw.rotation;
4295                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4296                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4297
4298                 if (rotation & DRM_MODE_ROTATE_180) {
4299                         src_x += src_w - 1;
4300                         src_y += src_h - 1;
4301                 } else if (rotation & DRM_MODE_REFLECT_X) {
4302                         src_x += src_w - 1;
4303                 }
4304         }
4305
4306         plane_state->color_plane[0].offset = offset;
4307         plane_state->color_plane[0].x = src_x;
4308         plane_state->color_plane[0].y = src_y;
4309
4310         return 0;
4311 }
4312
4313 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4314 {
4315         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4316         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4317
4318         if (IS_CHERRYVIEW(dev_priv))
4319                 return i9xx_plane == PLANE_B;
4320         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4321                 return false;
4322         else if (IS_GEN(dev_priv, 4))
4323                 return i9xx_plane == PLANE_C;
4324         else
4325                 return i9xx_plane == PLANE_B ||
4326                         i9xx_plane == PLANE_C;
4327 }
4328
4329 static int
4330 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4331                  struct intel_plane_state *plane_state)
4332 {
4333         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4334         int ret;
4335
4336         ret = chv_plane_check_rotation(plane_state);
4337         if (ret)
4338                 return ret;
4339
4340         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4341                                                   &crtc_state->uapi,
4342                                                   DRM_PLANE_HELPER_NO_SCALING,
4343                                                   DRM_PLANE_HELPER_NO_SCALING,
4344                                                   i9xx_plane_has_windowing(plane),
4345                                                   true);
4346         if (ret)
4347                 return ret;
4348
4349         ret = i9xx_check_plane_surface(plane_state);
4350         if (ret)
4351                 return ret;
4352
4353         if (!plane_state->uapi.visible)
4354                 return 0;
4355
4356         ret = intel_plane_check_src_coordinates(plane_state);
4357         if (ret)
4358                 return ret;
4359
4360         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4361
4362         return 0;
4363 }
4364
4365 static void i9xx_update_plane(struct intel_plane *plane,
4366                               const struct intel_crtc_state *crtc_state,
4367                               const struct intel_plane_state *plane_state)
4368 {
4369         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4370         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4371         u32 linear_offset;
4372         int x = plane_state->color_plane[0].x;
4373         int y = plane_state->color_plane[0].y;
4374         int crtc_x = plane_state->uapi.dst.x1;
4375         int crtc_y = plane_state->uapi.dst.y1;
4376         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4377         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4378         unsigned long irqflags;
4379         u32 dspaddr_offset;
4380         u32 dspcntr;
4381
4382         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4383
4384         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4385
4386         if (INTEL_GEN(dev_priv) >= 4)
4387                 dspaddr_offset = plane_state->color_plane[0].offset;
4388         else
4389                 dspaddr_offset = linear_offset;
4390
4391         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4392
4393         intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4394                           plane_state->color_plane[0].stride);
4395
4396         if (INTEL_GEN(dev_priv) < 4) {
4397                 /*
4398                  * PLANE_A doesn't actually have a full window
4399                  * generator but let's assume we still need to
4400                  * program whatever is there.
4401                  */
4402                 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4403                                   (crtc_y << 16) | crtc_x);
4404                 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4405                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4406         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4407                 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4408                                   (crtc_y << 16) | crtc_x);
4409                 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4410                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4411                 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4412         }
4413
4414         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4415                 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4416                                   (y << 16) | x);
4417         } else if (INTEL_GEN(dev_priv) >= 4) {
4418                 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4419                                   linear_offset);
4420                 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4421                                   (y << 16) | x);
4422         }
4423
4424         /*
4425          * The control register self-arms if the plane was previously
4426          * disabled. Try to make the plane enable atomic by writing
4427          * the control register just before the surface register.
4428          */
4429         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4430         if (INTEL_GEN(dev_priv) >= 4)
4431                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4432                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4433         else
4434                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4435                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4436
4437         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4438 }
4439
4440 static void i9xx_disable_plane(struct intel_plane *plane,
4441                                const struct intel_crtc_state *crtc_state)
4442 {
4443         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4444         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4445         unsigned long irqflags;
4446         u32 dspcntr;
4447
4448         /*
4449          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4450          * enable on ilk+ affect the pipe bottom color as
4451          * well, so we must configure them even if the plane
4452          * is disabled.
4453          *
4454          * On pre-g4x there is no way to gamma correct the
4455          * pipe bottom color but we'll keep on doing this
4456          * anyway so that the crtc state readout works correctly.
4457          */
4458         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4459
4460         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4461
4462         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4463         if (INTEL_GEN(dev_priv) >= 4)
4464                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4465         else
4466                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4467
4468         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4469 }
4470
4471 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4472                                     enum pipe *pipe)
4473 {
4474         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4475         enum intel_display_power_domain power_domain;
4476         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4477         intel_wakeref_t wakeref;
4478         bool ret;
4479         u32 val;
4480
4481         /*
4482          * Not 100% correct for planes that can move between pipes,
4483          * but that's only the case for gen2-4 which don't have any
4484          * display power wells.
4485          */
4486         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4487         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4488         if (!wakeref)
4489                 return false;
4490
4491         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4492
4493         ret = val & DISPLAY_PLANE_ENABLE;
4494
4495         if (INTEL_GEN(dev_priv) >= 5)
4496                 *pipe = plane->pipe;
4497         else
4498                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4499                         DISPPLANE_SEL_PIPE_SHIFT;
4500
4501         intel_display_power_put(dev_priv, power_domain, wakeref);
4502
4503         return ret;
4504 }
4505
4506 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4507 {
4508         struct drm_device *dev = intel_crtc->base.dev;
4509         struct drm_i915_private *dev_priv = to_i915(dev);
4510         unsigned long irqflags;
4511
4512         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4513
4514         intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4515         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4516         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4517
4518         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4519 }
4520
4521 /*
4522  * This function detaches (aka. unbinds) unused scalers in hardware
4523  */
4524 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4525 {
4526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4527         const struct intel_crtc_scaler_state *scaler_state =
4528                 &crtc_state->scaler_state;
4529         int i;
4530
4531         /* loop through and disable scalers that aren't in use */
4532         for (i = 0; i < intel_crtc->num_scalers; i++) {
4533                 if (!scaler_state->scalers[i].in_use)
4534                         skl_detach_scaler(intel_crtc, i);
4535         }
4536 }
4537
4538 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4539                                           int color_plane, unsigned int rotation)
4540 {
4541         /*
4542          * The stride is either expressed as a multiple of 64 bytes chunks for
4543          * linear buffers or in number of tiles for tiled buffers.
4544          */
4545         if (is_surface_linear(fb, color_plane))
4546                 return 64;
4547         else if (drm_rotation_90_or_270(rotation))
4548                 return intel_tile_height(fb, color_plane);
4549         else
4550                 return intel_tile_width_bytes(fb, color_plane);
4551 }
4552
4553 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4554                      int color_plane)
4555 {
4556         const struct drm_framebuffer *fb = plane_state->hw.fb;
4557         unsigned int rotation = plane_state->hw.rotation;
4558         u32 stride = plane_state->color_plane[color_plane].stride;
4559
4560         if (color_plane >= fb->format->num_planes)
4561                 return 0;
4562
4563         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4564 }
4565
4566 static u32 skl_plane_ctl_format(u32 pixel_format)
4567 {
4568         switch (pixel_format) {
4569         case DRM_FORMAT_C8:
4570                 return PLANE_CTL_FORMAT_INDEXED;
4571         case DRM_FORMAT_RGB565:
4572                 return PLANE_CTL_FORMAT_RGB_565;
4573         case DRM_FORMAT_XBGR8888:
4574         case DRM_FORMAT_ABGR8888:
4575                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4576         case DRM_FORMAT_XRGB8888:
4577         case DRM_FORMAT_ARGB8888:
4578                 return PLANE_CTL_FORMAT_XRGB_8888;
4579         case DRM_FORMAT_XBGR2101010:
4580         case DRM_FORMAT_ABGR2101010:
4581                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4582         case DRM_FORMAT_XRGB2101010:
4583         case DRM_FORMAT_ARGB2101010:
4584                 return PLANE_CTL_FORMAT_XRGB_2101010;
4585         case DRM_FORMAT_XBGR16161616F:
4586         case DRM_FORMAT_ABGR16161616F:
4587                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4588         case DRM_FORMAT_XRGB16161616F:
4589         case DRM_FORMAT_ARGB16161616F:
4590                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4591         case DRM_FORMAT_XYUV8888:
4592                 return PLANE_CTL_FORMAT_XYUV;
4593         case DRM_FORMAT_YUYV:
4594                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4595         case DRM_FORMAT_YVYU:
4596                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4597         case DRM_FORMAT_UYVY:
4598                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4599         case DRM_FORMAT_VYUY:
4600                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4601         case DRM_FORMAT_NV12:
4602                 return PLANE_CTL_FORMAT_NV12;
4603         case DRM_FORMAT_P010:
4604                 return PLANE_CTL_FORMAT_P010;
4605         case DRM_FORMAT_P012:
4606                 return PLANE_CTL_FORMAT_P012;
4607         case DRM_FORMAT_P016:
4608                 return PLANE_CTL_FORMAT_P016;
4609         case DRM_FORMAT_Y210:
4610                 return PLANE_CTL_FORMAT_Y210;
4611         case DRM_FORMAT_Y212:
4612                 return PLANE_CTL_FORMAT_Y212;
4613         case DRM_FORMAT_Y216:
4614                 return PLANE_CTL_FORMAT_Y216;
4615         case DRM_FORMAT_XVYU2101010:
4616                 return PLANE_CTL_FORMAT_Y410;
4617         case DRM_FORMAT_XVYU12_16161616:
4618                 return PLANE_CTL_FORMAT_Y412;
4619         case DRM_FORMAT_XVYU16161616:
4620                 return PLANE_CTL_FORMAT_Y416;
4621         default:
4622                 MISSING_CASE(pixel_format);
4623         }
4624
4625         return 0;
4626 }
4627
4628 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4629 {
4630         if (!plane_state->hw.fb->format->has_alpha)
4631                 return PLANE_CTL_ALPHA_DISABLE;
4632
4633         switch (plane_state->hw.pixel_blend_mode) {
4634         case DRM_MODE_BLEND_PIXEL_NONE:
4635                 return PLANE_CTL_ALPHA_DISABLE;
4636         case DRM_MODE_BLEND_PREMULTI:
4637                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4638         case DRM_MODE_BLEND_COVERAGE:
4639                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4640         default:
4641                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4642                 return PLANE_CTL_ALPHA_DISABLE;
4643         }
4644 }
4645
4646 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4647 {
4648         if (!plane_state->hw.fb->format->has_alpha)
4649                 return PLANE_COLOR_ALPHA_DISABLE;
4650
4651         switch (plane_state->hw.pixel_blend_mode) {
4652         case DRM_MODE_BLEND_PIXEL_NONE:
4653                 return PLANE_COLOR_ALPHA_DISABLE;
4654         case DRM_MODE_BLEND_PREMULTI:
4655                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4656         case DRM_MODE_BLEND_COVERAGE:
4657                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4658         default:
4659                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4660                 return PLANE_COLOR_ALPHA_DISABLE;
4661         }
4662 }
4663
4664 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4665 {
4666         switch (fb_modifier) {
4667         case DRM_FORMAT_MOD_LINEAR:
4668                 break;
4669         case I915_FORMAT_MOD_X_TILED:
4670                 return PLANE_CTL_TILED_X;
4671         case I915_FORMAT_MOD_Y_TILED:
4672                 return PLANE_CTL_TILED_Y;
4673         case I915_FORMAT_MOD_Y_TILED_CCS:
4674                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4675         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4676                 return PLANE_CTL_TILED_Y |
4677                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4678                        PLANE_CTL_CLEAR_COLOR_DISABLE;
4679         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4680                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4681         case I915_FORMAT_MOD_Yf_TILED:
4682                 return PLANE_CTL_TILED_YF;
4683         case I915_FORMAT_MOD_Yf_TILED_CCS:
4684                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4685         default:
4686                 MISSING_CASE(fb_modifier);
4687         }
4688
4689         return 0;
4690 }
4691
4692 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4693 {
4694         switch (rotate) {
4695         case DRM_MODE_ROTATE_0:
4696                 break;
4697         /*
4698          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4699          * while i915 HW rotation is clockwise, thats why this swapping.
4700          */
4701         case DRM_MODE_ROTATE_90:
4702                 return PLANE_CTL_ROTATE_270;
4703         case DRM_MODE_ROTATE_180:
4704                 return PLANE_CTL_ROTATE_180;
4705         case DRM_MODE_ROTATE_270:
4706                 return PLANE_CTL_ROTATE_90;
4707         default:
4708                 MISSING_CASE(rotate);
4709         }
4710
4711         return 0;
4712 }
4713
4714 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4715 {
4716         switch (reflect) {
4717         case 0:
4718                 break;
4719         case DRM_MODE_REFLECT_X:
4720                 return PLANE_CTL_FLIP_HORIZONTAL;
4721         case DRM_MODE_REFLECT_Y:
4722         default:
4723                 MISSING_CASE(reflect);
4724         }
4725
4726         return 0;
4727 }
4728
4729 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4730 {
4731         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4732         u32 plane_ctl = 0;
4733
4734         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4735                 return plane_ctl;
4736
4737         if (crtc_state->gamma_enable)
4738                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4739
4740         if (crtc_state->csc_enable)
4741                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4742
4743         return plane_ctl;
4744 }
4745
4746 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4747                   const struct intel_plane_state *plane_state)
4748 {
4749         struct drm_i915_private *dev_priv =
4750                 to_i915(plane_state->uapi.plane->dev);
4751         const struct drm_framebuffer *fb = plane_state->hw.fb;
4752         unsigned int rotation = plane_state->hw.rotation;
4753         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4754         u32 plane_ctl;
4755
4756         plane_ctl = PLANE_CTL_ENABLE;
4757
4758         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4759                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4760                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4761
4762                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4763                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4764
4765                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4766                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4767         }
4768
4769         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4770         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4771         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4772
4773         if (INTEL_GEN(dev_priv) >= 10)
4774                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4775                                                 DRM_MODE_REFLECT_MASK);
4776
4777         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4778                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4779         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4780                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4781
4782         return plane_ctl;
4783 }
4784
4785 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4786 {
4787         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4788         u32 plane_color_ctl = 0;
4789
4790         if (INTEL_GEN(dev_priv) >= 11)
4791                 return plane_color_ctl;
4792
4793         if (crtc_state->gamma_enable)
4794                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4795
4796         if (crtc_state->csc_enable)
4797                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4798
4799         return plane_color_ctl;
4800 }
4801
4802 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4803                         const struct intel_plane_state *plane_state)
4804 {
4805         struct drm_i915_private *dev_priv =
4806                 to_i915(plane_state->uapi.plane->dev);
4807         const struct drm_framebuffer *fb = plane_state->hw.fb;
4808         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4809         u32 plane_color_ctl = 0;
4810
4811         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4812         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4813
4814         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4815                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4816                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4817                 else
4818                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4819
4820                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4821                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4822         } else if (fb->format->is_yuv) {
4823                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4824         }
4825
4826         return plane_color_ctl;
4827 }
4828
4829 static int
4830 __intel_display_resume(struct drm_device *dev,
4831                        struct drm_atomic_state *state,
4832                        struct drm_modeset_acquire_ctx *ctx)
4833 {
4834         struct drm_crtc_state *crtc_state;
4835         struct drm_crtc *crtc;
4836         int i, ret;
4837
4838         intel_modeset_setup_hw_state(dev, ctx);
4839         intel_vga_redisable(to_i915(dev));
4840
4841         if (!state)
4842                 return 0;
4843
4844         /*
4845          * We've duplicated the state, pointers to the old state are invalid.
4846          *
4847          * Don't attempt to use the old state until we commit the duplicated state.
4848          */
4849         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4850                 /*
4851                  * Force recalculation even if we restore
4852                  * current state. With fast modeset this may not result
4853                  * in a modeset when the state is compatible.
4854                  */
4855                 crtc_state->mode_changed = true;
4856         }
4857
4858         /* ignore any reset values/BIOS leftovers in the WM registers */
4859         if (!HAS_GMCH(to_i915(dev)))
4860                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4861
4862         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4863
4864         drm_WARN_ON(dev, ret == -EDEADLK);
4865         return ret;
4866 }
4867
4868 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4869 {
4870         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4871                 intel_has_gpu_reset(&dev_priv->gt));
4872 }
4873
4874 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4875 {
4876         struct drm_device *dev = &dev_priv->drm;
4877         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4878         struct drm_atomic_state *state;
4879         int ret;
4880
4881         /* reset doesn't touch the display */
4882         if (!i915_modparams.force_reset_modeset_test &&
4883             !gpu_reset_clobbers_display(dev_priv))
4884                 return;
4885
4886         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4887         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4888         smp_mb__after_atomic();
4889         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4890
4891         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4892                 drm_dbg_kms(&dev_priv->drm,
4893                             "Modeset potentially stuck, unbreaking through wedging\n");
4894                 intel_gt_set_wedged(&dev_priv->gt);
4895         }
4896
4897         /*
4898          * Need mode_config.mutex so that we don't
4899          * trample ongoing ->detect() and whatnot.
4900          */
4901         mutex_lock(&dev->mode_config.mutex);
4902         drm_modeset_acquire_init(ctx, 0);
4903         while (1) {
4904                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4905                 if (ret != -EDEADLK)
4906                         break;
4907
4908                 drm_modeset_backoff(ctx);
4909         }
4910         /*
4911          * Disabling the crtcs gracefully seems nicer. Also the
4912          * g33 docs say we should at least disable all the planes.
4913          */
4914         state = drm_atomic_helper_duplicate_state(dev, ctx);
4915         if (IS_ERR(state)) {
4916                 ret = PTR_ERR(state);
4917                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
4918                         ret);
4919                 return;
4920         }
4921
4922         ret = drm_atomic_helper_disable_all(dev, ctx);
4923         if (ret) {
4924                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4925                         ret);
4926                 drm_atomic_state_put(state);
4927                 return;
4928         }
4929
4930         dev_priv->modeset_restore_state = state;
4931         state->acquire_ctx = ctx;
4932 }
4933
4934 void intel_finish_reset(struct drm_i915_private *dev_priv)
4935 {
4936         struct drm_device *dev = &dev_priv->drm;
4937         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4938         struct drm_atomic_state *state;
4939         int ret;
4940
4941         /* reset doesn't touch the display */
4942         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4943                 return;
4944
4945         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4946         if (!state)
4947                 goto unlock;
4948
4949         /* reset doesn't touch the display */
4950         if (!gpu_reset_clobbers_display(dev_priv)) {
4951                 /* for testing only restore the display */
4952                 ret = __intel_display_resume(dev, state, ctx);
4953                 if (ret)
4954                         drm_err(&dev_priv->drm,
4955                                 "Restoring old state failed with %i\n", ret);
4956         } else {
4957                 /*
4958                  * The display has been reset as well,
4959                  * so need a full re-initialization.
4960                  */
4961                 intel_pps_unlock_regs_wa(dev_priv);
4962                 intel_modeset_init_hw(dev_priv);
4963                 intel_init_clock_gating(dev_priv);
4964
4965                 spin_lock_irq(&dev_priv->irq_lock);
4966                 if (dev_priv->display.hpd_irq_setup)
4967                         dev_priv->display.hpd_irq_setup(dev_priv);
4968                 spin_unlock_irq(&dev_priv->irq_lock);
4969
4970                 ret = __intel_display_resume(dev, state, ctx);
4971                 if (ret)
4972                         drm_err(&dev_priv->drm,
4973                                 "Restoring old state failed with %i\n", ret);
4974
4975                 intel_hpd_init(dev_priv);
4976         }
4977
4978         drm_atomic_state_put(state);
4979 unlock:
4980         drm_modeset_drop_locks(ctx);
4981         drm_modeset_acquire_fini(ctx);
4982         mutex_unlock(&dev->mode_config.mutex);
4983
4984         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4985 }
4986
4987 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4988 {
4989         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4990         enum pipe pipe = crtc->pipe;
4991         u32 tmp;
4992
4993         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
4994
4995         /*
4996          * Display WA #1153: icl
4997          * enable hardware to bypass the alpha math
4998          * and rounding for per-pixel values 00 and 0xff
4999          */
5000         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5001         /*
5002          * Display WA # 1605353570: icl
5003          * Set the pixel rounding bit to 1 for allowing
5004          * passthrough of Frame buffer pixels unmodified
5005          * across pipe
5006          */
5007         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5008         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5009 }
5010
5011 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5012 {
5013         struct drm_device *dev = crtc->base.dev;
5014         struct drm_i915_private *dev_priv = to_i915(dev);
5015         enum pipe pipe = crtc->pipe;
5016         i915_reg_t reg;
5017         u32 temp;
5018
5019         /* enable normal train */
5020         reg = FDI_TX_CTL(pipe);
5021         temp = intel_de_read(dev_priv, reg);
5022         if (IS_IVYBRIDGE(dev_priv)) {
5023                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5024                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5025         } else {
5026                 temp &= ~FDI_LINK_TRAIN_NONE;
5027                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5028         }
5029         intel_de_write(dev_priv, reg, temp);
5030
5031         reg = FDI_RX_CTL(pipe);
5032         temp = intel_de_read(dev_priv, reg);
5033         if (HAS_PCH_CPT(dev_priv)) {
5034                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5035                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5036         } else {
5037                 temp &= ~FDI_LINK_TRAIN_NONE;
5038                 temp |= FDI_LINK_TRAIN_NONE;
5039         }
5040         intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5041
5042         /* wait one idle pattern time */
5043         intel_de_posting_read(dev_priv, reg);
5044         udelay(1000);
5045
5046         /* IVB wants error correction enabled */
5047         if (IS_IVYBRIDGE(dev_priv))
5048                 intel_de_write(dev_priv, reg,
5049                                intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5050 }
5051
5052 /* The FDI link training functions for ILK/Ibexpeak. */
5053 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5054                                const struct intel_crtc_state *crtc_state)
5055 {
5056         struct drm_device *dev = crtc->base.dev;
5057         struct drm_i915_private *dev_priv = to_i915(dev);
5058         enum pipe pipe = crtc->pipe;
5059         i915_reg_t reg;
5060         u32 temp, tries;
5061
5062         /* FDI needs bits from pipe first */
5063         assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5064
5065         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5066            for train result */
5067         reg = FDI_RX_IMR(pipe);
5068         temp = intel_de_read(dev_priv, reg);
5069         temp &= ~FDI_RX_SYMBOL_LOCK;
5070         temp &= ~FDI_RX_BIT_LOCK;
5071         intel_de_write(dev_priv, reg, temp);
5072         intel_de_read(dev_priv, reg);
5073         udelay(150);
5074
5075         /* enable CPU FDI TX and PCH FDI RX */
5076         reg = FDI_TX_CTL(pipe);
5077         temp = intel_de_read(dev_priv, reg);
5078         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5079         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5080         temp &= ~FDI_LINK_TRAIN_NONE;
5081         temp |= FDI_LINK_TRAIN_PATTERN_1;
5082         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5083
5084         reg = FDI_RX_CTL(pipe);
5085         temp = intel_de_read(dev_priv, reg);
5086         temp &= ~FDI_LINK_TRAIN_NONE;
5087         temp |= FDI_LINK_TRAIN_PATTERN_1;
5088         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5089
5090         intel_de_posting_read(dev_priv, reg);
5091         udelay(150);
5092
5093         /* Ironlake workaround, enable clock pointer after FDI enable*/
5094         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5095                        FDI_RX_PHASE_SYNC_POINTER_OVR);
5096         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5097                        FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5098
5099         reg = FDI_RX_IIR(pipe);
5100         for (tries = 0; tries < 5; tries++) {
5101                 temp = intel_de_read(dev_priv, reg);
5102                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5103
5104                 if ((temp & FDI_RX_BIT_LOCK)) {
5105                         drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5106                         intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5107                         break;
5108                 }
5109         }
5110         if (tries == 5)
5111                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5112
5113         /* Train 2 */
5114         reg = FDI_TX_CTL(pipe);
5115         temp = intel_de_read(dev_priv, reg);
5116         temp &= ~FDI_LINK_TRAIN_NONE;
5117         temp |= FDI_LINK_TRAIN_PATTERN_2;
5118         intel_de_write(dev_priv, reg, temp);
5119
5120         reg = FDI_RX_CTL(pipe);
5121         temp = intel_de_read(dev_priv, reg);
5122         temp &= ~FDI_LINK_TRAIN_NONE;
5123         temp |= FDI_LINK_TRAIN_PATTERN_2;
5124         intel_de_write(dev_priv, reg, temp);
5125
5126         intel_de_posting_read(dev_priv, reg);
5127         udelay(150);
5128
5129         reg = FDI_RX_IIR(pipe);
5130         for (tries = 0; tries < 5; tries++) {
5131                 temp = intel_de_read(dev_priv, reg);
5132                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5133
5134                 if (temp & FDI_RX_SYMBOL_LOCK) {
5135                         intel_de_write(dev_priv, reg,
5136                                        temp | FDI_RX_SYMBOL_LOCK);
5137                         drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5138                         break;
5139                 }
5140         }
5141         if (tries == 5)
5142                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5143
5144         drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5145
5146 }
5147
5148 static const int snb_b_fdi_train_param[] = {
5149         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5150         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5151         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5152         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5153 };
5154
5155 /* The FDI link training functions for SNB/Cougarpoint. */
5156 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5157                                 const struct intel_crtc_state *crtc_state)
5158 {
5159         struct drm_device *dev = crtc->base.dev;
5160         struct drm_i915_private *dev_priv = to_i915(dev);
5161         enum pipe pipe = crtc->pipe;
5162         i915_reg_t reg;
5163         u32 temp, i, retry;
5164
5165         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5166            for train result */
5167         reg = FDI_RX_IMR(pipe);
5168         temp = intel_de_read(dev_priv, reg);
5169         temp &= ~FDI_RX_SYMBOL_LOCK;
5170         temp &= ~FDI_RX_BIT_LOCK;
5171         intel_de_write(dev_priv, reg, temp);
5172
5173         intel_de_posting_read(dev_priv, reg);
5174         udelay(150);
5175
5176         /* enable CPU FDI TX and PCH FDI RX */
5177         reg = FDI_TX_CTL(pipe);
5178         temp = intel_de_read(dev_priv, reg);
5179         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5180         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5181         temp &= ~FDI_LINK_TRAIN_NONE;
5182         temp |= FDI_LINK_TRAIN_PATTERN_1;
5183         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5184         /* SNB-B */
5185         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5186         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5187
5188         intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5189                        FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5190
5191         reg = FDI_RX_CTL(pipe);
5192         temp = intel_de_read(dev_priv, reg);
5193         if (HAS_PCH_CPT(dev_priv)) {
5194                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5195                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5196         } else {
5197                 temp &= ~FDI_LINK_TRAIN_NONE;
5198                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5199         }
5200         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5201
5202         intel_de_posting_read(dev_priv, reg);
5203         udelay(150);
5204
5205         for (i = 0; i < 4; i++) {
5206                 reg = FDI_TX_CTL(pipe);
5207                 temp = intel_de_read(dev_priv, reg);
5208                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5209                 temp |= snb_b_fdi_train_param[i];
5210                 intel_de_write(dev_priv, reg, temp);
5211
5212                 intel_de_posting_read(dev_priv, reg);
5213                 udelay(500);
5214
5215                 for (retry = 0; retry < 5; retry++) {
5216                         reg = FDI_RX_IIR(pipe);
5217                         temp = intel_de_read(dev_priv, reg);
5218                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5219                         if (temp & FDI_RX_BIT_LOCK) {
5220                                 intel_de_write(dev_priv, reg,
5221                                                temp | FDI_RX_BIT_LOCK);
5222                                 drm_dbg_kms(&dev_priv->drm,
5223                                             "FDI train 1 done.\n");
5224                                 break;
5225                         }
5226                         udelay(50);
5227                 }
5228                 if (retry < 5)
5229                         break;
5230         }
5231         if (i == 4)
5232                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5233
5234         /* Train 2 */
5235         reg = FDI_TX_CTL(pipe);
5236         temp = intel_de_read(dev_priv, reg);
5237         temp &= ~FDI_LINK_TRAIN_NONE;
5238         temp |= FDI_LINK_TRAIN_PATTERN_2;
5239         if (IS_GEN(dev_priv, 6)) {
5240                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5241                 /* SNB-B */
5242                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5243         }
5244         intel_de_write(dev_priv, reg, temp);
5245
5246         reg = FDI_RX_CTL(pipe);
5247         temp = intel_de_read(dev_priv, reg);
5248         if (HAS_PCH_CPT(dev_priv)) {
5249                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5250                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5251         } else {
5252                 temp &= ~FDI_LINK_TRAIN_NONE;
5253                 temp |= FDI_LINK_TRAIN_PATTERN_2;
5254         }
5255         intel_de_write(dev_priv, reg, temp);
5256
5257         intel_de_posting_read(dev_priv, reg);
5258         udelay(150);
5259
5260         for (i = 0; i < 4; i++) {
5261                 reg = FDI_TX_CTL(pipe);
5262                 temp = intel_de_read(dev_priv, reg);
5263                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5264                 temp |= snb_b_fdi_train_param[i];
5265                 intel_de_write(dev_priv, reg, temp);
5266
5267                 intel_de_posting_read(dev_priv, reg);
5268                 udelay(500);
5269
5270                 for (retry = 0; retry < 5; retry++) {
5271                         reg = FDI_RX_IIR(pipe);
5272                         temp = intel_de_read(dev_priv, reg);
5273                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5274                         if (temp & FDI_RX_SYMBOL_LOCK) {
5275                                 intel_de_write(dev_priv, reg,
5276                                                temp | FDI_RX_SYMBOL_LOCK);
5277                                 drm_dbg_kms(&dev_priv->drm,
5278                                             "FDI train 2 done.\n");
5279                                 break;
5280                         }
5281                         udelay(50);
5282                 }
5283                 if (retry < 5)
5284                         break;
5285         }
5286         if (i == 4)
5287                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5288
5289         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5290 }
5291
5292 /* Manual link training for Ivy Bridge A0 parts */
5293 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5294                                       const struct intel_crtc_state *crtc_state)
5295 {
5296         struct drm_device *dev = crtc->base.dev;
5297         struct drm_i915_private *dev_priv = to_i915(dev);
5298         enum pipe pipe = crtc->pipe;
5299         i915_reg_t reg;
5300         u32 temp, i, j;
5301
5302         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5303            for train result */
5304         reg = FDI_RX_IMR(pipe);
5305         temp = intel_de_read(dev_priv, reg);
5306         temp &= ~FDI_RX_SYMBOL_LOCK;
5307         temp &= ~FDI_RX_BIT_LOCK;
5308         intel_de_write(dev_priv, reg, temp);
5309
5310         intel_de_posting_read(dev_priv, reg);
5311         udelay(150);
5312
5313         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5314                     intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5315
5316         /* Try each vswing and preemphasis setting twice before moving on */
5317         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5318                 /* disable first in case we need to retry */
5319                 reg = FDI_TX_CTL(pipe);
5320                 temp = intel_de_read(dev_priv, reg);
5321                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5322                 temp &= ~FDI_TX_ENABLE;
5323                 intel_de_write(dev_priv, reg, temp);
5324
5325                 reg = FDI_RX_CTL(pipe);
5326                 temp = intel_de_read(dev_priv, reg);
5327                 temp &= ~FDI_LINK_TRAIN_AUTO;
5328                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5329                 temp &= ~FDI_RX_ENABLE;
5330                 intel_de_write(dev_priv, reg, temp);
5331
5332                 /* enable CPU FDI TX and PCH FDI RX */
5333                 reg = FDI_TX_CTL(pipe);
5334                 temp = intel_de_read(dev_priv, reg);
5335                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5336                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5337                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5338                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5339                 temp |= snb_b_fdi_train_param[j/2];
5340                 temp |= FDI_COMPOSITE_SYNC;
5341                 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5342
5343                 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5344                                FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5345
5346                 reg = FDI_RX_CTL(pipe);
5347                 temp = intel_de_read(dev_priv, reg);
5348                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5349                 temp |= FDI_COMPOSITE_SYNC;
5350                 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5351
5352                 intel_de_posting_read(dev_priv, reg);
5353                 udelay(1); /* should be 0.5us */
5354
5355                 for (i = 0; i < 4; i++) {
5356                         reg = FDI_RX_IIR(pipe);
5357                         temp = intel_de_read(dev_priv, reg);
5358                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5359
5360                         if (temp & FDI_RX_BIT_LOCK ||
5361                             (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5362                                 intel_de_write(dev_priv, reg,
5363                                                temp | FDI_RX_BIT_LOCK);
5364                                 drm_dbg_kms(&dev_priv->drm,
5365                                             "FDI train 1 done, level %i.\n",
5366                                             i);
5367                                 break;
5368                         }
5369                         udelay(1); /* should be 0.5us */
5370                 }
5371                 if (i == 4) {
5372                         drm_dbg_kms(&dev_priv->drm,
5373                                     "FDI train 1 fail on vswing %d\n", j / 2);
5374                         continue;
5375                 }
5376
5377                 /* Train 2 */
5378                 reg = FDI_TX_CTL(pipe);
5379                 temp = intel_de_read(dev_priv, reg);
5380                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5381                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5382                 intel_de_write(dev_priv, reg, temp);
5383
5384                 reg = FDI_RX_CTL(pipe);
5385                 temp = intel_de_read(dev_priv, reg);
5386                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5387                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5388                 intel_de_write(dev_priv, reg, temp);
5389
5390                 intel_de_posting_read(dev_priv, reg);
5391                 udelay(2); /* should be 1.5us */
5392
5393                 for (i = 0; i < 4; i++) {
5394                         reg = FDI_RX_IIR(pipe);
5395                         temp = intel_de_read(dev_priv, reg);
5396                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5397
5398                         if (temp & FDI_RX_SYMBOL_LOCK ||
5399                             (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5400                                 intel_de_write(dev_priv, reg,
5401                                                temp | FDI_RX_SYMBOL_LOCK);
5402                                 drm_dbg_kms(&dev_priv->drm,
5403                                             "FDI train 2 done, level %i.\n",
5404                                             i);
5405                                 goto train_done;
5406                         }
5407                         udelay(2); /* should be 1.5us */
5408                 }
5409                 if (i == 4)
5410                         drm_dbg_kms(&dev_priv->drm,
5411                                     "FDI train 2 fail on vswing %d\n", j / 2);
5412         }
5413
5414 train_done:
5415         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5416 }
5417
5418 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5419 {
5420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5421         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5422         enum pipe pipe = intel_crtc->pipe;
5423         i915_reg_t reg;
5424         u32 temp;
5425
5426         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5427         reg = FDI_RX_CTL(pipe);
5428         temp = intel_de_read(dev_priv, reg);
5429         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5430         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5431         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5432         intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5433
5434         intel_de_posting_read(dev_priv, reg);
5435         udelay(200);
5436
5437         /* Switch from Rawclk to PCDclk */
5438         temp = intel_de_read(dev_priv, reg);
5439         intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5440
5441         intel_de_posting_read(dev_priv, reg);
5442         udelay(200);
5443
5444         /* Enable CPU FDI TX PLL, always on for Ironlake */
5445         reg = FDI_TX_CTL(pipe);
5446         temp = intel_de_read(dev_priv, reg);
5447         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5448                 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5449
5450                 intel_de_posting_read(dev_priv, reg);
5451                 udelay(100);
5452         }
5453 }
5454
5455 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5456 {
5457         struct drm_device *dev = intel_crtc->base.dev;
5458         struct drm_i915_private *dev_priv = to_i915(dev);
5459         enum pipe pipe = intel_crtc->pipe;
5460         i915_reg_t reg;
5461         u32 temp;
5462
5463         /* Switch from PCDclk to Rawclk */
5464         reg = FDI_RX_CTL(pipe);
5465         temp = intel_de_read(dev_priv, reg);
5466         intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5467
5468         /* Disable CPU FDI TX PLL */
5469         reg = FDI_TX_CTL(pipe);
5470         temp = intel_de_read(dev_priv, reg);
5471         intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5472
5473         intel_de_posting_read(dev_priv, reg);
5474         udelay(100);
5475
5476         reg = FDI_RX_CTL(pipe);
5477         temp = intel_de_read(dev_priv, reg);
5478         intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5479
5480         /* Wait for the clocks to turn off. */
5481         intel_de_posting_read(dev_priv, reg);
5482         udelay(100);
5483 }
5484
5485 static void ilk_fdi_disable(struct intel_crtc *crtc)
5486 {
5487         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5488         enum pipe pipe = crtc->pipe;
5489         i915_reg_t reg;
5490         u32 temp;
5491
5492         /* disable CPU FDI tx and PCH FDI rx */
5493         reg = FDI_TX_CTL(pipe);
5494         temp = intel_de_read(dev_priv, reg);
5495         intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5496         intel_de_posting_read(dev_priv, reg);
5497
5498         reg = FDI_RX_CTL(pipe);
5499         temp = intel_de_read(dev_priv, reg);
5500         temp &= ~(0x7 << 16);
5501         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5502         intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5503
5504         intel_de_posting_read(dev_priv, reg);
5505         udelay(100);
5506
5507         /* Ironlake workaround, disable clock pointer after downing FDI */
5508         if (HAS_PCH_IBX(dev_priv))
5509                 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5510                                FDI_RX_PHASE_SYNC_POINTER_OVR);
5511
5512         /* still set train pattern 1 */
5513         reg = FDI_TX_CTL(pipe);
5514         temp = intel_de_read(dev_priv, reg);
5515         temp &= ~FDI_LINK_TRAIN_NONE;
5516         temp |= FDI_LINK_TRAIN_PATTERN_1;
5517         intel_de_write(dev_priv, reg, temp);
5518
5519         reg = FDI_RX_CTL(pipe);
5520         temp = intel_de_read(dev_priv, reg);
5521         if (HAS_PCH_CPT(dev_priv)) {
5522                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5523                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5524         } else {
5525                 temp &= ~FDI_LINK_TRAIN_NONE;
5526                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5527         }
5528         /* BPC in FDI rx is consistent with that in PIPECONF */
5529         temp &= ~(0x07 << 16);
5530         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5531         intel_de_write(dev_priv, reg, temp);
5532
5533         intel_de_posting_read(dev_priv, reg);
5534         udelay(100);
5535 }
5536
5537 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5538 {
5539         struct drm_crtc *crtc;
5540         bool cleanup_done;
5541
5542         drm_for_each_crtc(crtc, &dev_priv->drm) {
5543                 struct drm_crtc_commit *commit;
5544                 spin_lock(&crtc->commit_lock);
5545                 commit = list_first_entry_or_null(&crtc->commit_list,
5546                                                   struct drm_crtc_commit, commit_entry);
5547                 cleanup_done = commit ?
5548                         try_wait_for_completion(&commit->cleanup_done) : true;
5549                 spin_unlock(&crtc->commit_lock);
5550
5551                 if (cleanup_done)
5552                         continue;
5553
5554                 drm_crtc_wait_one_vblank(crtc);
5555
5556                 return true;
5557         }
5558
5559         return false;
5560 }
5561
5562 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5563 {
5564         u32 temp;
5565
5566         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5567
5568         mutex_lock(&dev_priv->sb_lock);
5569
5570         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5571         temp |= SBI_SSCCTL_DISABLE;
5572         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5573
5574         mutex_unlock(&dev_priv->sb_lock);
5575 }
5576
5577 /* Program iCLKIP clock to the desired frequency */
5578 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5579 {
5580         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5581         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5582         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5583         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5584         u32 temp;
5585
5586         lpt_disable_iclkip(dev_priv);
5587
5588         /* The iCLK virtual clock root frequency is in MHz,
5589          * but the adjusted_mode->crtc_clock in in KHz. To get the
5590          * divisors, it is necessary to divide one by another, so we
5591          * convert the virtual clock precision to KHz here for higher
5592          * precision.
5593          */
5594         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5595                 u32 iclk_virtual_root_freq = 172800 * 1000;
5596                 u32 iclk_pi_range = 64;
5597                 u32 desired_divisor;
5598
5599                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5600                                                     clock << auxdiv);
5601                 divsel = (desired_divisor / iclk_pi_range) - 2;
5602                 phaseinc = desired_divisor % iclk_pi_range;
5603
5604                 /*
5605                  * Near 20MHz is a corner case which is
5606                  * out of range for the 7-bit divisor
5607                  */
5608                 if (divsel <= 0x7f)
5609                         break;
5610         }
5611
5612         /* This should not happen with any sane values */
5613         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5614                     ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5615         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5616                     ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5617
5618         drm_dbg_kms(&dev_priv->drm,
5619                     "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5620                     clock, auxdiv, divsel, phasedir, phaseinc);
5621
5622         mutex_lock(&dev_priv->sb_lock);
5623
5624         /* Program SSCDIVINTPHASE6 */
5625         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5626         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5627         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5628         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5629         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5630         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5631         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5632         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5633
5634         /* Program SSCAUXDIV */
5635         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5636         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5637         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5638         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5639
5640         /* Enable modulator and associated divider */
5641         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5642         temp &= ~SBI_SSCCTL_DISABLE;
5643         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5644
5645         mutex_unlock(&dev_priv->sb_lock);
5646
5647         /* Wait for initialization time */
5648         udelay(24);
5649
5650         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5651 }
5652
5653 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5654 {
5655         u32 divsel, phaseinc, auxdiv;
5656         u32 iclk_virtual_root_freq = 172800 * 1000;
5657         u32 iclk_pi_range = 64;
5658         u32 desired_divisor;
5659         u32 temp;
5660
5661         if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5662                 return 0;
5663
5664         mutex_lock(&dev_priv->sb_lock);
5665
5666         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5667         if (temp & SBI_SSCCTL_DISABLE) {
5668                 mutex_unlock(&dev_priv->sb_lock);
5669                 return 0;
5670         }
5671
5672         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5673         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5674                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5675         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5676                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5677
5678         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5679         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5680                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5681
5682         mutex_unlock(&dev_priv->sb_lock);
5683
5684         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5685
5686         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5687                                  desired_divisor << auxdiv);
5688 }
5689
5690 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5691                                            enum pipe pch_transcoder)
5692 {
5693         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5694         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5695         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5696
5697         intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5698                        intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5699         intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5700                        intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5701         intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5702                        intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5703
5704         intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5705                        intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5706         intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5707                        intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5708         intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5709                        intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5710         intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5711                        intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5712 }
5713
5714 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5715 {
5716         u32 temp;
5717
5718         temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5719         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5720                 return;
5721
5722         drm_WARN_ON(&dev_priv->drm,
5723                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5724                     FDI_RX_ENABLE);
5725         drm_WARN_ON(&dev_priv->drm,
5726                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5727                     FDI_RX_ENABLE);
5728
5729         temp &= ~FDI_BC_BIFURCATION_SELECT;
5730         if (enable)
5731                 temp |= FDI_BC_BIFURCATION_SELECT;
5732
5733         drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5734                     enable ? "en" : "dis");
5735         intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5736         intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5737 }
5738
5739 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5740 {
5741         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5742         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5743
5744         switch (crtc->pipe) {
5745         case PIPE_A:
5746                 break;
5747         case PIPE_B:
5748                 if (crtc_state->fdi_lanes > 2)
5749                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5750                 else
5751                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5752
5753                 break;
5754         case PIPE_C:
5755                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5756
5757                 break;
5758         default:
5759                 BUG();
5760         }
5761 }
5762
5763 /*
5764  * Finds the encoder associated with the given CRTC. This can only be
5765  * used when we know that the CRTC isn't feeding multiple encoders!
5766  */
5767 static struct intel_encoder *
5768 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5769                            const struct intel_crtc_state *crtc_state)
5770 {
5771         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5772         const struct drm_connector_state *connector_state;
5773         const struct drm_connector *connector;
5774         struct intel_encoder *encoder = NULL;
5775         int num_encoders = 0;
5776         int i;
5777
5778         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5779                 if (connector_state->crtc != &crtc->base)
5780                         continue;
5781
5782                 encoder = to_intel_encoder(connector_state->best_encoder);
5783                 num_encoders++;
5784         }
5785
5786         drm_WARN(encoder->base.dev, num_encoders != 1,
5787                  "%d encoders for pipe %c\n",
5788                  num_encoders, pipe_name(crtc->pipe));
5789
5790         return encoder;
5791 }
5792
5793 /*
5794  * Enable PCH resources required for PCH ports:
5795  *   - PCH PLLs
5796  *   - FDI training & RX/TX
5797  *   - update transcoder timings
5798  *   - DP transcoding bits
5799  *   - transcoder
5800  */
5801 static void ilk_pch_enable(const struct intel_atomic_state *state,
5802                            const struct intel_crtc_state *crtc_state)
5803 {
5804         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5805         struct drm_device *dev = crtc->base.dev;
5806         struct drm_i915_private *dev_priv = to_i915(dev);
5807         enum pipe pipe = crtc->pipe;
5808         u32 temp;
5809
5810         assert_pch_transcoder_disabled(dev_priv, pipe);
5811
5812         if (IS_IVYBRIDGE(dev_priv))
5813                 ivb_update_fdi_bc_bifurcation(crtc_state);
5814
5815         /* Write the TU size bits before fdi link training, so that error
5816          * detection works. */
5817         intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5818                        intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5819
5820         /* For PCH output, training FDI link */
5821         dev_priv->display.fdi_link_train(crtc, crtc_state);
5822
5823         /* We need to program the right clock selection before writing the pixel
5824          * mutliplier into the DPLL. */
5825         if (HAS_PCH_CPT(dev_priv)) {
5826                 u32 sel;
5827
5828                 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5829                 temp |= TRANS_DPLL_ENABLE(pipe);
5830                 sel = TRANS_DPLLB_SEL(pipe);
5831                 if (crtc_state->shared_dpll ==
5832                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5833                         temp |= sel;
5834                 else
5835                         temp &= ~sel;
5836                 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5837         }
5838
5839         /* XXX: pch pll's can be enabled any time before we enable the PCH
5840          * transcoder, and we actually should do this to not upset any PCH
5841          * transcoder that already use the clock when we share it.
5842          *
5843          * Note that enable_shared_dpll tries to do the right thing, but
5844          * get_shared_dpll unconditionally resets the pll - we need that to have
5845          * the right LVDS enable sequence. */
5846         intel_enable_shared_dpll(crtc_state);
5847
5848         /* set transcoder timing, panel must allow it */
5849         assert_panel_unlocked(dev_priv, pipe);
5850         ilk_pch_transcoder_set_timings(crtc_state, pipe);
5851
5852         intel_fdi_normal_train(crtc);
5853
5854         /* For PCH DP, enable TRANS_DP_CTL */
5855         if (HAS_PCH_CPT(dev_priv) &&
5856             intel_crtc_has_dp_encoder(crtc_state)) {
5857                 const struct drm_display_mode *adjusted_mode =
5858                         &crtc_state->hw.adjusted_mode;
5859                 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5860                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5861                 enum port port;
5862
5863                 temp = intel_de_read(dev_priv, reg);
5864                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5865                           TRANS_DP_SYNC_MASK |
5866                           TRANS_DP_BPC_MASK);
5867                 temp |= TRANS_DP_OUTPUT_ENABLE;
5868                 temp |= bpc << 9; /* same format but at 11:9 */
5869
5870                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5871                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5872                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5873                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5874
5875                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5876                 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5877                 temp |= TRANS_DP_PORT_SEL(port);
5878
5879                 intel_de_write(dev_priv, reg, temp);
5880         }
5881
5882         ilk_enable_pch_transcoder(crtc_state);
5883 }
5884
5885 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5886 {
5887         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5888         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5889         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5890
5891         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5892
5893         lpt_program_iclkip(crtc_state);
5894
5895         /* Set transcoder timing. */
5896         ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5897
5898         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5899 }
5900
5901 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5902                                enum pipe pipe)
5903 {
5904         i915_reg_t dslreg = PIPEDSL(pipe);
5905         u32 temp;
5906
5907         temp = intel_de_read(dev_priv, dslreg);
5908         udelay(500);
5909         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5910                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5911                         drm_err(&dev_priv->drm,
5912                                 "mode set failed: pipe %c stuck\n",
5913                                 pipe_name(pipe));
5914         }
5915 }
5916
5917 /*
5918  * The hardware phase 0.0 refers to the center of the pixel.
5919  * We want to start from the top/left edge which is phase
5920  * -0.5. That matches how the hardware calculates the scaling
5921  * factors (from top-left of the first pixel to bottom-right
5922  * of the last pixel, as opposed to the pixel centers).
5923  *
5924  * For 4:2:0 subsampled chroma planes we obviously have to
5925  * adjust that so that the chroma sample position lands in
5926  * the right spot.
5927  *
5928  * Note that for packed YCbCr 4:2:2 formats there is no way to
5929  * control chroma siting. The hardware simply replicates the
5930  * chroma samples for both of the luma samples, and thus we don't
5931  * actually get the expected MPEG2 chroma siting convention :(
5932  * The same behaviour is observed on pre-SKL platforms as well.
5933  *
5934  * Theory behind the formula (note that we ignore sub-pixel
5935  * source coordinates):
5936  * s = source sample position
5937  * d = destination sample position
5938  *
5939  * Downscaling 4:1:
5940  * -0.5
5941  * | 0.0
5942  * | |     1.5 (initial phase)
5943  * | |     |
5944  * v v     v
5945  * | s | s | s | s |
5946  * |       d       |
5947  *
5948  * Upscaling 1:4:
5949  * -0.5
5950  * | -0.375 (initial phase)
5951  * | |     0.0
5952  * | |     |
5953  * v v     v
5954  * |       s       |
5955  * | d | d | d | d |
5956  */
5957 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5958 {
5959         int phase = -0x8000;
5960         u16 trip = 0;
5961
5962         if (chroma_cosited)
5963                 phase += (sub - 1) * 0x8000 / sub;
5964
5965         phase += scale / (2 * sub);
5966
5967         /*
5968          * Hardware initial phase limited to [-0.5:1.5].
5969          * Since the max hardware scale factor is 3.0, we
5970          * should never actually excdeed 1.0 here.
5971          */
5972         WARN_ON(phase < -0x8000 || phase > 0x18000);
5973
5974         if (phase < 0)
5975                 phase = 0x10000 + phase;
5976         else
5977                 trip = PS_PHASE_TRIP;
5978
5979         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5980 }
5981
5982 #define SKL_MIN_SRC_W 8
5983 #define SKL_MAX_SRC_W 4096
5984 #define SKL_MIN_SRC_H 8
5985 #define SKL_MAX_SRC_H 4096
5986 #define SKL_MIN_DST_W 8
5987 #define SKL_MAX_DST_W 4096
5988 #define SKL_MIN_DST_H 8
5989 #define SKL_MAX_DST_H 4096
5990 #define ICL_MAX_SRC_W 5120
5991 #define ICL_MAX_SRC_H 4096
5992 #define ICL_MAX_DST_W 5120
5993 #define ICL_MAX_DST_H 4096
5994 #define SKL_MIN_YUV_420_SRC_W 16
5995 #define SKL_MIN_YUV_420_SRC_H 16
5996
5997 static int
5998 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5999                   unsigned int scaler_user, int *scaler_id,
6000                   int src_w, int src_h, int dst_w, int dst_h,
6001                   const struct drm_format_info *format,
6002                   u64 modifier, bool need_scaler)
6003 {
6004         struct intel_crtc_scaler_state *scaler_state =
6005                 &crtc_state->scaler_state;
6006         struct intel_crtc *intel_crtc =
6007                 to_intel_crtc(crtc_state->uapi.crtc);
6008         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6009         const struct drm_display_mode *adjusted_mode =
6010                 &crtc_state->hw.adjusted_mode;
6011
6012         /*
6013          * Src coordinates are already rotated by 270 degrees for
6014          * the 90/270 degree plane rotation cases (to match the
6015          * GTT mapping), hence no need to account for rotation here.
6016          */
6017         if (src_w != dst_w || src_h != dst_h)
6018                 need_scaler = true;
6019
6020         /*
6021          * Scaling/fitting not supported in IF-ID mode in GEN9+
6022          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6023          * Once NV12 is enabled, handle it here while allocating scaler
6024          * for NV12.
6025          */
6026         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6027             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6028                 drm_dbg_kms(&dev_priv->drm,
6029                             "Pipe/Plane scaling not supported with IF-ID mode\n");
6030                 return -EINVAL;
6031         }
6032
6033         /*
6034          * if plane is being disabled or scaler is no more required or force detach
6035          *  - free scaler binded to this plane/crtc
6036          *  - in order to do this, update crtc->scaler_usage
6037          *
6038          * Here scaler state in crtc_state is set free so that
6039          * scaler can be assigned to other user. Actual register
6040          * update to free the scaler is done in plane/panel-fit programming.
6041          * For this purpose crtc/plane_state->scaler_id isn't reset here.
6042          */
6043         if (force_detach || !need_scaler) {
6044                 if (*scaler_id >= 0) {
6045                         scaler_state->scaler_users &= ~(1 << scaler_user);
6046                         scaler_state->scalers[*scaler_id].in_use = 0;
6047
6048                         drm_dbg_kms(&dev_priv->drm,
6049                                     "scaler_user index %u.%u: "
6050                                     "Staged freeing scaler id %d scaler_users = 0x%x\n",
6051                                     intel_crtc->pipe, scaler_user, *scaler_id,
6052                                     scaler_state->scaler_users);
6053                         *scaler_id = -1;
6054                 }
6055                 return 0;
6056         }
6057
6058         if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6059             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6060                 drm_dbg_kms(&dev_priv->drm,
6061                             "Planar YUV: src dimensions not met\n");
6062                 return -EINVAL;
6063         }
6064
6065         /* range checks */
6066         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6067             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6068             (INTEL_GEN(dev_priv) >= 11 &&
6069              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6070               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6071             (INTEL_GEN(dev_priv) < 11 &&
6072              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6073               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6074                 drm_dbg_kms(&dev_priv->drm,
6075                             "scaler_user index %u.%u: src %ux%u dst %ux%u "
6076                             "size is out of scaler range\n",
6077                             intel_crtc->pipe, scaler_user, src_w, src_h,
6078                             dst_w, dst_h);
6079                 return -EINVAL;
6080         }
6081
6082         /* mark this plane as a scaler user in crtc_state */
6083         scaler_state->scaler_users |= (1 << scaler_user);
6084         drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6085                     "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6086                     intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6087                     scaler_state->scaler_users);
6088
6089         return 0;
6090 }
6091
6092 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6093 {
6094         const struct drm_display_mode *adjusted_mode =
6095                 &crtc_state->hw.adjusted_mode;
6096         int width, height;
6097
6098         if (crtc_state->pch_pfit.enabled) {
6099                 u32 pfit_size = crtc_state->pch_pfit.size;
6100
6101                 width = pfit_size >> 16;
6102                 height = pfit_size & 0xffff;
6103         } else {
6104                 width = adjusted_mode->crtc_hdisplay;
6105                 height = adjusted_mode->crtc_vdisplay;
6106         }
6107
6108         return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6109                                  SKL_CRTC_INDEX,
6110                                  &crtc_state->scaler_state.scaler_id,
6111                                  crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6112                                  width, height, NULL, 0,
6113                                  crtc_state->pch_pfit.enabled);
6114 }
6115
6116 /**
6117  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6118  * @crtc_state: crtc's scaler state
6119  * @plane_state: atomic plane state to update
6120  *
6121  * Return
6122  *     0 - scaler_usage updated successfully
6123  *    error - requested scaling cannot be supported or other error condition
6124  */
6125 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6126                                    struct intel_plane_state *plane_state)
6127 {
6128         struct intel_plane *intel_plane =
6129                 to_intel_plane(plane_state->uapi.plane);
6130         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6131         struct drm_framebuffer *fb = plane_state->hw.fb;
6132         int ret;
6133         bool force_detach = !fb || !plane_state->uapi.visible;
6134         bool need_scaler = false;
6135
6136         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6137         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6138             fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6139                 need_scaler = true;
6140
6141         ret = skl_update_scaler(crtc_state, force_detach,
6142                                 drm_plane_index(&intel_plane->base),
6143                                 &plane_state->scaler_id,
6144                                 drm_rect_width(&plane_state->uapi.src) >> 16,
6145                                 drm_rect_height(&plane_state->uapi.src) >> 16,
6146                                 drm_rect_width(&plane_state->uapi.dst),
6147                                 drm_rect_height(&plane_state->uapi.dst),
6148                                 fb ? fb->format : NULL,
6149                                 fb ? fb->modifier : 0,
6150                                 need_scaler);
6151
6152         if (ret || plane_state->scaler_id < 0)
6153                 return ret;
6154
6155         /* check colorkey */
6156         if (plane_state->ckey.flags) {
6157                 drm_dbg_kms(&dev_priv->drm,
6158                             "[PLANE:%d:%s] scaling with color key not allowed",
6159                             intel_plane->base.base.id,
6160                             intel_plane->base.name);
6161                 return -EINVAL;
6162         }
6163
6164         /* Check src format */
6165         switch (fb->format->format) {
6166         case DRM_FORMAT_RGB565:
6167         case DRM_FORMAT_XBGR8888:
6168         case DRM_FORMAT_XRGB8888:
6169         case DRM_FORMAT_ABGR8888:
6170         case DRM_FORMAT_ARGB8888:
6171         case DRM_FORMAT_XRGB2101010:
6172         case DRM_FORMAT_XBGR2101010:
6173         case DRM_FORMAT_ARGB2101010:
6174         case DRM_FORMAT_ABGR2101010:
6175         case DRM_FORMAT_YUYV:
6176         case DRM_FORMAT_YVYU:
6177         case DRM_FORMAT_UYVY:
6178         case DRM_FORMAT_VYUY:
6179         case DRM_FORMAT_NV12:
6180         case DRM_FORMAT_XYUV8888:
6181         case DRM_FORMAT_P010:
6182         case DRM_FORMAT_P012:
6183         case DRM_FORMAT_P016:
6184         case DRM_FORMAT_Y210:
6185         case DRM_FORMAT_Y212:
6186         case DRM_FORMAT_Y216:
6187         case DRM_FORMAT_XVYU2101010:
6188         case DRM_FORMAT_XVYU12_16161616:
6189         case DRM_FORMAT_XVYU16161616:
6190                 break;
6191         case DRM_FORMAT_XBGR16161616F:
6192         case DRM_FORMAT_ABGR16161616F:
6193         case DRM_FORMAT_XRGB16161616F:
6194         case DRM_FORMAT_ARGB16161616F:
6195                 if (INTEL_GEN(dev_priv) >= 11)
6196                         break;
6197                 /* fall through */
6198         default:
6199                 drm_dbg_kms(&dev_priv->drm,
6200                             "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6201                             intel_plane->base.base.id, intel_plane->base.name,
6202                             fb->base.id, fb->format->format);
6203                 return -EINVAL;
6204         }
6205
6206         return 0;
6207 }
6208
6209 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6210 {
6211         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6212         int i;
6213
6214         for (i = 0; i < crtc->num_scalers; i++)
6215                 skl_detach_scaler(crtc, i);
6216 }
6217
6218 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6219 {
6220         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6221         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6222         enum pipe pipe = crtc->pipe;
6223         const struct intel_crtc_scaler_state *scaler_state =
6224                 &crtc_state->scaler_state;
6225
6226         if (crtc_state->pch_pfit.enabled) {
6227                 u16 uv_rgb_hphase, uv_rgb_vphase;
6228                 int pfit_w, pfit_h, hscale, vscale;
6229                 unsigned long irqflags;
6230                 int id;
6231
6232                 if (drm_WARN_ON(&dev_priv->drm,
6233                                 crtc_state->scaler_state.scaler_id < 0))
6234                         return;
6235
6236                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
6237                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
6238
6239                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
6240                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
6241
6242                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6243                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6244
6245                 id = scaler_state->scaler_id;
6246
6247                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6248
6249                 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6250                                   PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6251                 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6252                                   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6253                 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6254                                   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6255                 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6256                                   crtc_state->pch_pfit.pos);
6257                 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6258                                   crtc_state->pch_pfit.size);
6259
6260                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6261         }
6262 }
6263
6264 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6265 {
6266         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6267         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6268         enum pipe pipe = crtc->pipe;
6269
6270         if (crtc_state->pch_pfit.enabled) {
6271                 /* Force use of hard-coded filter coefficients
6272                  * as some pre-programmed values are broken,
6273                  * e.g. x201.
6274                  */
6275                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6276                         intel_de_write(dev_priv, PF_CTL(pipe),
6277                                        PF_ENABLE | PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6278                 else
6279                         intel_de_write(dev_priv, PF_CTL(pipe),
6280                                        PF_ENABLE | PF_FILTER_MED_3x3);
6281                 intel_de_write(dev_priv, PF_WIN_POS(pipe),
6282                                crtc_state->pch_pfit.pos);
6283                 intel_de_write(dev_priv, PF_WIN_SZ(pipe),
6284                                crtc_state->pch_pfit.size);
6285         }
6286 }
6287
6288 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6289 {
6290         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6291         struct drm_device *dev = crtc->base.dev;
6292         struct drm_i915_private *dev_priv = to_i915(dev);
6293
6294         if (!crtc_state->ips_enabled)
6295                 return;
6296
6297         /*
6298          * We can only enable IPS after we enable a plane and wait for a vblank
6299          * This function is called from post_plane_update, which is run after
6300          * a vblank wait.
6301          */
6302         drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6303
6304         if (IS_BROADWELL(dev_priv)) {
6305                 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6306                                                          IPS_ENABLE | IPS_PCODE_CONTROL));
6307                 /* Quoting Art Runyan: "its not safe to expect any particular
6308                  * value in IPS_CTL bit 31 after enabling IPS through the
6309                  * mailbox." Moreover, the mailbox may return a bogus state,
6310                  * so we need to just enable it and continue on.
6311                  */
6312         } else {
6313                 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6314                 /* The bit only becomes 1 in the next vblank, so this wait here
6315                  * is essentially intel_wait_for_vblank. If we don't have this
6316                  * and don't wait for vblanks until the end of crtc_enable, then
6317                  * the HW state readout code will complain that the expected
6318                  * IPS_CTL value is not the one we read. */
6319                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6320                         drm_err(&dev_priv->drm,
6321                                 "Timed out waiting for IPS enable\n");
6322         }
6323 }
6324
6325 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6326 {
6327         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6328         struct drm_device *dev = crtc->base.dev;
6329         struct drm_i915_private *dev_priv = to_i915(dev);
6330
6331         if (!crtc_state->ips_enabled)
6332                 return;
6333
6334         if (IS_BROADWELL(dev_priv)) {
6335                 drm_WARN_ON(dev,
6336                             sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6337                 /*
6338                  * Wait for PCODE to finish disabling IPS. The BSpec specified
6339                  * 42ms timeout value leads to occasional timeouts so use 100ms
6340                  * instead.
6341                  */
6342                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6343                         drm_err(&dev_priv->drm,
6344                                 "Timed out waiting for IPS disable\n");
6345         } else {
6346                 intel_de_write(dev_priv, IPS_CTL, 0);
6347                 intel_de_posting_read(dev_priv, IPS_CTL);
6348         }
6349
6350         /* We need to wait for a vblank before we can disable the plane. */
6351         intel_wait_for_vblank(dev_priv, crtc->pipe);
6352 }
6353
6354 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6355 {
6356         if (intel_crtc->overlay)
6357                 (void) intel_overlay_switch_off(intel_crtc->overlay);
6358
6359         /* Let userspace switch the overlay on again. In most cases userspace
6360          * has to recompute where to put it anyway.
6361          */
6362 }
6363
6364 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6365                                        const struct intel_crtc_state *new_crtc_state)
6366 {
6367         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6368         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6369
6370         if (!old_crtc_state->ips_enabled)
6371                 return false;
6372
6373         if (needs_modeset(new_crtc_state))
6374                 return true;
6375
6376         /*
6377          * Workaround : Do not read or write the pipe palette/gamma data while
6378          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6379          *
6380          * Disable IPS before we program the LUT.
6381          */
6382         if (IS_HASWELL(dev_priv) &&
6383             (new_crtc_state->uapi.color_mgmt_changed ||
6384              new_crtc_state->update_pipe) &&
6385             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6386                 return true;
6387
6388         return !new_crtc_state->ips_enabled;
6389 }
6390
6391 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6392                                        const struct intel_crtc_state *new_crtc_state)
6393 {
6394         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6395         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6396
6397         if (!new_crtc_state->ips_enabled)
6398                 return false;
6399
6400         if (needs_modeset(new_crtc_state))
6401                 return true;
6402
6403         /*
6404          * Workaround : Do not read or write the pipe palette/gamma data while
6405          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6406          *
6407          * Re-enable IPS after the LUT has been programmed.
6408          */
6409         if (IS_HASWELL(dev_priv) &&
6410             (new_crtc_state->uapi.color_mgmt_changed ||
6411              new_crtc_state->update_pipe) &&
6412             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6413                 return true;
6414
6415         /*
6416          * We can't read out IPS on broadwell, assume the worst and
6417          * forcibly enable IPS on the first fastset.
6418          */
6419         if (new_crtc_state->update_pipe &&
6420             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
6421                 return true;
6422
6423         return !old_crtc_state->ips_enabled;
6424 }
6425
6426 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6427 {
6428         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6429
6430         if (!crtc_state->nv12_planes)
6431                 return false;
6432
6433         /* WA Display #0827: Gen9:all */
6434         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6435                 return true;
6436
6437         return false;
6438 }
6439
6440 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6441 {
6442         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6443
6444         /* Wa_2006604312:icl,ehl */
6445         if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6446                 return true;
6447
6448         return false;
6449 }
6450
6451 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6452                             const struct intel_crtc_state *new_crtc_state)
6453 {
6454         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6455                 new_crtc_state->active_planes;
6456 }
6457
6458 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6459                              const struct intel_crtc_state *new_crtc_state)
6460 {
6461         return old_crtc_state->active_planes &&
6462                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6463 }
6464
6465 static void intel_post_plane_update(struct intel_atomic_state *state,
6466                                     struct intel_crtc *crtc)
6467 {
6468         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6469         const struct intel_crtc_state *old_crtc_state =
6470                 intel_atomic_get_old_crtc_state(state, crtc);
6471         const struct intel_crtc_state *new_crtc_state =
6472                 intel_atomic_get_new_crtc_state(state, crtc);
6473         enum pipe pipe = crtc->pipe;
6474
6475         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6476
6477         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6478                 intel_update_watermarks(crtc);
6479
6480         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6481                 hsw_enable_ips(new_crtc_state);
6482
6483         intel_fbc_post_update(state, crtc);
6484
6485         if (needs_nv12_wa(old_crtc_state) &&
6486             !needs_nv12_wa(new_crtc_state))
6487                 skl_wa_827(dev_priv, pipe, false);
6488
6489         if (needs_scalerclk_wa(old_crtc_state) &&
6490             !needs_scalerclk_wa(new_crtc_state))
6491                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6492 }
6493
6494 static void intel_pre_plane_update(struct intel_atomic_state *state,
6495                                    struct intel_crtc *crtc)
6496 {
6497         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6498         const struct intel_crtc_state *old_crtc_state =
6499                 intel_atomic_get_old_crtc_state(state, crtc);
6500         const struct intel_crtc_state *new_crtc_state =
6501                 intel_atomic_get_new_crtc_state(state, crtc);
6502         enum pipe pipe = crtc->pipe;
6503
6504         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6505                 hsw_disable_ips(old_crtc_state);
6506
6507         if (intel_fbc_pre_update(state, crtc))
6508                 intel_wait_for_vblank(dev_priv, pipe);
6509
6510         /* Display WA 827 */
6511         if (!needs_nv12_wa(old_crtc_state) &&
6512             needs_nv12_wa(new_crtc_state))
6513                 skl_wa_827(dev_priv, pipe, true);
6514
6515         /* Wa_2006604312:icl,ehl */
6516         if (!needs_scalerclk_wa(old_crtc_state) &&
6517             needs_scalerclk_wa(new_crtc_state))
6518                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6519
6520         /*
6521          * Vblank time updates from the shadow to live plane control register
6522          * are blocked if the memory self-refresh mode is active at that
6523          * moment. So to make sure the plane gets truly disabled, disable
6524          * first the self-refresh mode. The self-refresh enable bit in turn
6525          * will be checked/applied by the HW only at the next frame start
6526          * event which is after the vblank start event, so we need to have a
6527          * wait-for-vblank between disabling the plane and the pipe.
6528          */
6529         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6530             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6531                 intel_wait_for_vblank(dev_priv, pipe);
6532
6533         /*
6534          * IVB workaround: must disable low power watermarks for at least
6535          * one frame before enabling scaling.  LP watermarks can be re-enabled
6536          * when scaling is disabled.
6537          *
6538          * WaCxSRDisabledForSpriteScaling:ivb
6539          */
6540         if (old_crtc_state->hw.active &&
6541             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6542                 intel_wait_for_vblank(dev_priv, pipe);
6543
6544         /*
6545          * If we're doing a modeset we don't need to do any
6546          * pre-vblank watermark programming here.
6547          */
6548         if (!needs_modeset(new_crtc_state)) {
6549                 /*
6550                  * For platforms that support atomic watermarks, program the
6551                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6552                  * will be the intermediate values that are safe for both pre- and
6553                  * post- vblank; when vblank happens, the 'active' values will be set
6554                  * to the final 'target' values and we'll do this again to get the
6555                  * optimal watermarks.  For gen9+ platforms, the values we program here
6556                  * will be the final target values which will get automatically latched
6557                  * at vblank time; no further programming will be necessary.
6558                  *
6559                  * If a platform hasn't been transitioned to atomic watermarks yet,
6560                  * we'll continue to update watermarks the old way, if flags tell
6561                  * us to.
6562                  */
6563                 if (dev_priv->display.initial_watermarks)
6564                         dev_priv->display.initial_watermarks(state, crtc);
6565                 else if (new_crtc_state->update_wm_pre)
6566                         intel_update_watermarks(crtc);
6567         }
6568
6569         /*
6570          * Gen2 reports pipe underruns whenever all planes are disabled.
6571          * So disable underrun reporting before all the planes get disabled.
6572          *
6573          * We do this after .initial_watermarks() so that we have a
6574          * chance of catching underruns with the intermediate watermarks
6575          * vs. the old plane configuration.
6576          */
6577         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6578                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6579 }
6580
6581 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6582                                       struct intel_crtc *crtc)
6583 {
6584         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6585         const struct intel_crtc_state *new_crtc_state =
6586                 intel_atomic_get_new_crtc_state(state, crtc);
6587         unsigned int update_mask = new_crtc_state->update_planes;
6588         const struct intel_plane_state *old_plane_state;
6589         struct intel_plane *plane;
6590         unsigned fb_bits = 0;
6591         int i;
6592
6593         intel_crtc_dpms_overlay_disable(crtc);
6594
6595         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6596                 if (crtc->pipe != plane->pipe ||
6597                     !(update_mask & BIT(plane->id)))
6598                         continue;
6599
6600                 intel_disable_plane(plane, new_crtc_state);
6601
6602                 if (old_plane_state->uapi.visible)
6603                         fb_bits |= plane->frontbuffer_bit;
6604         }
6605
6606         intel_frontbuffer_flip(dev_priv, fb_bits);
6607 }
6608
6609 /*
6610  * intel_connector_primary_encoder - get the primary encoder for a connector
6611  * @connector: connector for which to return the encoder
6612  *
6613  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6614  * all connectors to their encoder, except for DP-MST connectors which have
6615  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6616  * pointed to by as many DP-MST connectors as there are pipes.
6617  */
6618 static struct intel_encoder *
6619 intel_connector_primary_encoder(struct intel_connector *connector)
6620 {
6621         struct intel_encoder *encoder;
6622
6623         if (connector->mst_port)
6624                 return &dp_to_dig_port(connector->mst_port)->base;
6625
6626         encoder = intel_attached_encoder(connector);
6627         drm_WARN_ON(connector->base.dev, !encoder);
6628
6629         return encoder;
6630 }
6631
6632 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6633 {
6634         struct drm_connector_state *new_conn_state;
6635         struct drm_connector *connector;
6636         int i;
6637
6638         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6639                                         i) {
6640                 struct intel_connector *intel_connector;
6641                 struct intel_encoder *encoder;
6642                 struct intel_crtc *crtc;
6643
6644                 if (!intel_connector_needs_modeset(state, connector))
6645                         continue;
6646
6647                 intel_connector = to_intel_connector(connector);
6648                 encoder = intel_connector_primary_encoder(intel_connector);
6649                 if (!encoder->update_prepare)
6650                         continue;
6651
6652                 crtc = new_conn_state->crtc ?
6653                         to_intel_crtc(new_conn_state->crtc) : NULL;
6654                 encoder->update_prepare(state, encoder, crtc);
6655         }
6656 }
6657
6658 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6659 {
6660         struct drm_connector_state *new_conn_state;
6661         struct drm_connector *connector;
6662         int i;
6663
6664         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6665                                         i) {
6666                 struct intel_connector *intel_connector;
6667                 struct intel_encoder *encoder;
6668                 struct intel_crtc *crtc;
6669
6670                 if (!intel_connector_needs_modeset(state, connector))
6671                         continue;
6672
6673                 intel_connector = to_intel_connector(connector);
6674                 encoder = intel_connector_primary_encoder(intel_connector);
6675                 if (!encoder->update_complete)
6676                         continue;
6677
6678                 crtc = new_conn_state->crtc ?
6679                         to_intel_crtc(new_conn_state->crtc) : NULL;
6680                 encoder->update_complete(state, encoder, crtc);
6681         }
6682 }
6683
6684 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6685                                           struct intel_crtc *crtc)
6686 {
6687         const struct intel_crtc_state *crtc_state =
6688                 intel_atomic_get_new_crtc_state(state, crtc);
6689         const struct drm_connector_state *conn_state;
6690         struct drm_connector *conn;
6691         int i;
6692
6693         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6694                 struct intel_encoder *encoder =
6695                         to_intel_encoder(conn_state->best_encoder);
6696
6697                 if (conn_state->crtc != &crtc->base)
6698                         continue;
6699
6700                 if (encoder->pre_pll_enable)
6701                         encoder->pre_pll_enable(state, encoder,
6702                                                 crtc_state, conn_state);
6703         }
6704 }
6705
6706 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6707                                       struct intel_crtc *crtc)
6708 {
6709         const struct intel_crtc_state *crtc_state =
6710                 intel_atomic_get_new_crtc_state(state, crtc);
6711         const struct drm_connector_state *conn_state;
6712         struct drm_connector *conn;
6713         int i;
6714
6715         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6716                 struct intel_encoder *encoder =
6717                         to_intel_encoder(conn_state->best_encoder);
6718
6719                 if (conn_state->crtc != &crtc->base)
6720                         continue;
6721
6722                 if (encoder->pre_enable)
6723                         encoder->pre_enable(state, encoder,
6724                                             crtc_state, conn_state);
6725         }
6726 }
6727
6728 static void intel_encoders_enable(struct intel_atomic_state *state,
6729                                   struct intel_crtc *crtc)
6730 {
6731         const struct intel_crtc_state *crtc_state =
6732                 intel_atomic_get_new_crtc_state(state, crtc);
6733         const struct drm_connector_state *conn_state;
6734         struct drm_connector *conn;
6735         int i;
6736
6737         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6738                 struct intel_encoder *encoder =
6739                         to_intel_encoder(conn_state->best_encoder);
6740
6741                 if (conn_state->crtc != &crtc->base)
6742                         continue;
6743
6744                 if (encoder->enable)
6745                         encoder->enable(state, encoder,
6746                                         crtc_state, conn_state);
6747                 intel_opregion_notify_encoder(encoder, true);
6748         }
6749 }
6750
6751 static void intel_encoders_disable(struct intel_atomic_state *state,
6752                                    struct intel_crtc *crtc)
6753 {
6754         const struct intel_crtc_state *old_crtc_state =
6755                 intel_atomic_get_old_crtc_state(state, crtc);
6756         const struct drm_connector_state *old_conn_state;
6757         struct drm_connector *conn;
6758         int i;
6759
6760         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6761                 struct intel_encoder *encoder =
6762                         to_intel_encoder(old_conn_state->best_encoder);
6763
6764                 if (old_conn_state->crtc != &crtc->base)
6765                         continue;
6766
6767                 intel_opregion_notify_encoder(encoder, false);
6768                 if (encoder->disable)
6769                         encoder->disable(state, encoder,
6770                                          old_crtc_state, old_conn_state);
6771         }
6772 }
6773
6774 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6775                                         struct intel_crtc *crtc)
6776 {
6777         const struct intel_crtc_state *old_crtc_state =
6778                 intel_atomic_get_old_crtc_state(state, crtc);
6779         const struct drm_connector_state *old_conn_state;
6780         struct drm_connector *conn;
6781         int i;
6782
6783         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6784                 struct intel_encoder *encoder =
6785                         to_intel_encoder(old_conn_state->best_encoder);
6786
6787                 if (old_conn_state->crtc != &crtc->base)
6788                         continue;
6789
6790                 if (encoder->post_disable)
6791                         encoder->post_disable(state, encoder,
6792                                               old_crtc_state, old_conn_state);
6793         }
6794 }
6795
6796 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6797                                             struct intel_crtc *crtc)
6798 {
6799         const struct intel_crtc_state *old_crtc_state =
6800                 intel_atomic_get_old_crtc_state(state, crtc);
6801         const struct drm_connector_state *old_conn_state;
6802         struct drm_connector *conn;
6803         int i;
6804
6805         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6806                 struct intel_encoder *encoder =
6807                         to_intel_encoder(old_conn_state->best_encoder);
6808
6809                 if (old_conn_state->crtc != &crtc->base)
6810                         continue;
6811
6812                 if (encoder->post_pll_disable)
6813                         encoder->post_pll_disable(state, encoder,
6814                                                   old_crtc_state, old_conn_state);
6815         }
6816 }
6817
6818 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6819                                        struct intel_crtc *crtc)
6820 {
6821         const struct intel_crtc_state *crtc_state =
6822                 intel_atomic_get_new_crtc_state(state, crtc);
6823         const struct drm_connector_state *conn_state;
6824         struct drm_connector *conn;
6825         int i;
6826
6827         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6828                 struct intel_encoder *encoder =
6829                         to_intel_encoder(conn_state->best_encoder);
6830
6831                 if (conn_state->crtc != &crtc->base)
6832                         continue;
6833
6834                 if (encoder->update_pipe)
6835                         encoder->update_pipe(state, encoder,
6836                                              crtc_state, conn_state);
6837         }
6838 }
6839
6840 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6841 {
6842         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6843         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6844
6845         plane->disable_plane(plane, crtc_state);
6846 }
6847
6848 static void ilk_crtc_enable(struct intel_atomic_state *state,
6849                             struct intel_crtc *crtc)
6850 {
6851         const struct intel_crtc_state *new_crtc_state =
6852                 intel_atomic_get_new_crtc_state(state, crtc);
6853         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6854         enum pipe pipe = crtc->pipe;
6855
6856         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6857                 return;
6858
6859         /*
6860          * Sometimes spurious CPU pipe underruns happen during FDI
6861          * training, at least with VGA+HDMI cloning. Suppress them.
6862          *
6863          * On ILK we get an occasional spurious CPU pipe underruns
6864          * between eDP port A enable and vdd enable. Also PCH port
6865          * enable seems to result in the occasional CPU pipe underrun.
6866          *
6867          * Spurious PCH underruns also occur during PCH enabling.
6868          */
6869         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6870         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6871
6872         if (new_crtc_state->has_pch_encoder)
6873                 intel_prepare_shared_dpll(new_crtc_state);
6874
6875         if (intel_crtc_has_dp_encoder(new_crtc_state))
6876                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6877
6878         intel_set_pipe_timings(new_crtc_state);
6879         intel_set_pipe_src_size(new_crtc_state);
6880
6881         if (new_crtc_state->has_pch_encoder)
6882                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6883                                              &new_crtc_state->fdi_m_n, NULL);
6884
6885         ilk_set_pipeconf(new_crtc_state);
6886
6887         crtc->active = true;
6888
6889         intel_encoders_pre_enable(state, crtc);
6890
6891         if (new_crtc_state->has_pch_encoder) {
6892                 /* Note: FDI PLL enabling _must_ be done before we enable the
6893                  * cpu pipes, hence this is separate from all the other fdi/pch
6894                  * enabling. */
6895                 ilk_fdi_pll_enable(new_crtc_state);
6896         } else {
6897                 assert_fdi_tx_disabled(dev_priv, pipe);
6898                 assert_fdi_rx_disabled(dev_priv, pipe);
6899         }
6900
6901         ilk_pfit_enable(new_crtc_state);
6902
6903         /*
6904          * On ILK+ LUT must be loaded before the pipe is running but with
6905          * clocks enabled
6906          */
6907         intel_color_load_luts(new_crtc_state);
6908         intel_color_commit(new_crtc_state);
6909         /* update DSPCNTR to configure gamma for pipe bottom color */
6910         intel_disable_primary_plane(new_crtc_state);
6911
6912         if (dev_priv->display.initial_watermarks)
6913                 dev_priv->display.initial_watermarks(state, crtc);
6914         intel_enable_pipe(new_crtc_state);
6915
6916         if (new_crtc_state->has_pch_encoder)
6917                 ilk_pch_enable(state, new_crtc_state);
6918
6919         intel_crtc_vblank_on(new_crtc_state);
6920
6921         intel_encoders_enable(state, crtc);
6922
6923         if (HAS_PCH_CPT(dev_priv))
6924                 cpt_verify_modeset(dev_priv, pipe);
6925
6926         /*
6927          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6928          * And a second vblank wait is needed at least on ILK with
6929          * some interlaced HDMI modes. Let's do the double wait always
6930          * in case there are more corner cases we don't know about.
6931          */
6932         if (new_crtc_state->has_pch_encoder) {
6933                 intel_wait_for_vblank(dev_priv, pipe);
6934                 intel_wait_for_vblank(dev_priv, pipe);
6935         }
6936         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6937         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6938 }
6939
6940 /* IPS only exists on ULT machines and is tied to pipe A. */
6941 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6942 {
6943         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6944 }
6945
6946 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6947                                             enum pipe pipe, bool apply)
6948 {
6949         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
6950         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6951
6952         if (apply)
6953                 val |= mask;
6954         else
6955                 val &= ~mask;
6956
6957         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
6958 }
6959
6960 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6961 {
6962         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6963         enum pipe pipe = crtc->pipe;
6964         u32 val;
6965
6966         val = MBUS_DBOX_A_CREDIT(2);
6967
6968         if (INTEL_GEN(dev_priv) >= 12) {
6969                 val |= MBUS_DBOX_BW_CREDIT(2);
6970                 val |= MBUS_DBOX_B_CREDIT(12);
6971         } else {
6972                 val |= MBUS_DBOX_BW_CREDIT(1);
6973                 val |= MBUS_DBOX_B_CREDIT(8);
6974         }
6975
6976         intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
6977 }
6978
6979 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
6980 {
6981         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6982         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6983
6984         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
6985                        HSW_LINETIME(crtc_state->linetime) |
6986                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
6987 }
6988
6989 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6990 {
6991         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6992         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6993         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
6994         u32 val;
6995
6996         val = intel_de_read(dev_priv, reg);
6997         val &= ~HSW_FRAME_START_DELAY_MASK;
6998         val |= HSW_FRAME_START_DELAY(0);
6999         intel_de_write(dev_priv, reg, val);
7000 }
7001
7002 static void hsw_crtc_enable(struct intel_atomic_state *state,
7003                             struct intel_crtc *crtc)
7004 {
7005         const struct intel_crtc_state *new_crtc_state =
7006                 intel_atomic_get_new_crtc_state(state, crtc);
7007         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7008         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7009         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7010         bool psl_clkgate_wa;
7011
7012         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7013                 return;
7014
7015         intel_encoders_pre_pll_enable(state, crtc);
7016
7017         if (new_crtc_state->shared_dpll)
7018                 intel_enable_shared_dpll(new_crtc_state);
7019
7020         intel_encoders_pre_enable(state, crtc);
7021
7022         if (!transcoder_is_dsi(cpu_transcoder))
7023                 intel_set_pipe_timings(new_crtc_state);
7024
7025         intel_set_pipe_src_size(new_crtc_state);
7026
7027         if (cpu_transcoder != TRANSCODER_EDP &&
7028             !transcoder_is_dsi(cpu_transcoder))
7029                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7030                                new_crtc_state->pixel_multiplier - 1);
7031
7032         if (new_crtc_state->has_pch_encoder)
7033                 intel_cpu_transcoder_set_m_n(new_crtc_state,
7034                                              &new_crtc_state->fdi_m_n, NULL);
7035
7036         if (!transcoder_is_dsi(cpu_transcoder)) {
7037                 hsw_set_frame_start_delay(new_crtc_state);
7038                 hsw_set_pipeconf(new_crtc_state);
7039         }
7040
7041         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7042                 bdw_set_pipemisc(new_crtc_state);
7043
7044         crtc->active = true;
7045
7046         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7047         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7048                 new_crtc_state->pch_pfit.enabled;
7049         if (psl_clkgate_wa)
7050                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7051
7052         if (INTEL_GEN(dev_priv) >= 9)
7053                 skl_pfit_enable(new_crtc_state);
7054         else
7055                 ilk_pfit_enable(new_crtc_state);
7056
7057         /*
7058          * On ILK+ LUT must be loaded before the pipe is running but with
7059          * clocks enabled
7060          */
7061         intel_color_load_luts(new_crtc_state);
7062         intel_color_commit(new_crtc_state);
7063         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7064         if (INTEL_GEN(dev_priv) < 9)
7065                 intel_disable_primary_plane(new_crtc_state);
7066
7067         hsw_set_linetime_wm(new_crtc_state);
7068
7069         if (INTEL_GEN(dev_priv) >= 11)
7070                 icl_set_pipe_chicken(crtc);
7071
7072         if (dev_priv->display.initial_watermarks)
7073                 dev_priv->display.initial_watermarks(state, crtc);
7074
7075         if (INTEL_GEN(dev_priv) >= 11)
7076                 icl_pipe_mbus_enable(crtc);
7077
7078         intel_encoders_enable(state, crtc);
7079
7080         if (psl_clkgate_wa) {
7081                 intel_wait_for_vblank(dev_priv, pipe);
7082                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7083         }
7084
7085         /* If we change the relative order between pipe/planes enabling, we need
7086          * to change the workaround. */
7087         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7088         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7089                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7090                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7091         }
7092 }
7093
7094 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7095 {
7096         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7097         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7098         enum pipe pipe = crtc->pipe;
7099
7100         /* To avoid upsetting the power well on haswell only disable the pfit if
7101          * it's in use. The hw state code will make sure we get this right. */
7102         if (old_crtc_state->pch_pfit.enabled) {
7103                 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7104                 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7105                 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7106         }
7107 }
7108
7109 static void ilk_crtc_disable(struct intel_atomic_state *state,
7110                              struct intel_crtc *crtc)
7111 {
7112         const struct intel_crtc_state *old_crtc_state =
7113                 intel_atomic_get_old_crtc_state(state, crtc);
7114         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7115         enum pipe pipe = crtc->pipe;
7116
7117         /*
7118          * Sometimes spurious CPU pipe underruns happen when the
7119          * pipe is already disabled, but FDI RX/TX is still enabled.
7120          * Happens at least with VGA+HDMI cloning. Suppress them.
7121          */
7122         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7123         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7124
7125         intel_encoders_disable(state, crtc);
7126
7127         intel_crtc_vblank_off(old_crtc_state);
7128
7129         intel_disable_pipe(old_crtc_state);
7130
7131         ilk_pfit_disable(old_crtc_state);
7132
7133         if (old_crtc_state->has_pch_encoder)
7134                 ilk_fdi_disable(crtc);
7135
7136         intel_encoders_post_disable(state, crtc);
7137
7138         if (old_crtc_state->has_pch_encoder) {
7139                 ilk_disable_pch_transcoder(dev_priv, pipe);
7140
7141                 if (HAS_PCH_CPT(dev_priv)) {
7142                         i915_reg_t reg;
7143                         u32 temp;
7144
7145                         /* disable TRANS_DP_CTL */
7146                         reg = TRANS_DP_CTL(pipe);
7147                         temp = intel_de_read(dev_priv, reg);
7148                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7149                                   TRANS_DP_PORT_SEL_MASK);
7150                         temp |= TRANS_DP_PORT_SEL_NONE;
7151                         intel_de_write(dev_priv, reg, temp);
7152
7153                         /* disable DPLL_SEL */
7154                         temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7155                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7156                         intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7157                 }
7158
7159                 ilk_fdi_pll_disable(crtc);
7160         }
7161
7162         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7163         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7164 }
7165
7166 static void hsw_crtc_disable(struct intel_atomic_state *state,
7167                              struct intel_crtc *crtc)
7168 {
7169         /*
7170          * FIXME collapse everything to one hook.
7171          * Need care with mst->ddi interactions.
7172          */
7173         intel_encoders_disable(state, crtc);
7174         intel_encoders_post_disable(state, crtc);
7175 }
7176
7177 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7178 {
7179         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7180         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7181
7182         if (!crtc_state->gmch_pfit.control)
7183                 return;
7184
7185         /*
7186          * The panel fitter should only be adjusted whilst the pipe is disabled,
7187          * according to register description and PRM.
7188          */
7189         drm_WARN_ON(&dev_priv->drm,
7190                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7191         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7192
7193         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7194                        crtc_state->gmch_pfit.pgm_ratios);
7195         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7196
7197         /* Border color in case we don't scale up to the full screen. Black by
7198          * default, change to something else for debugging. */
7199         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7200 }
7201
7202 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7203 {
7204         if (phy == PHY_NONE)
7205                 return false;
7206
7207         if (IS_ELKHARTLAKE(dev_priv))
7208                 return phy <= PHY_C;
7209
7210         if (INTEL_GEN(dev_priv) >= 11)
7211                 return phy <= PHY_B;
7212
7213         return false;
7214 }
7215
7216 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7217 {
7218         if (INTEL_GEN(dev_priv) >= 12)
7219                 return phy >= PHY_D && phy <= PHY_I;
7220
7221         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
7222                 return phy >= PHY_C && phy <= PHY_F;
7223
7224         return false;
7225 }
7226
7227 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7228 {
7229         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
7230                 return PHY_A;
7231
7232         return (enum phy)port;
7233 }
7234
7235 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7236 {
7237         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7238                 return PORT_TC_NONE;
7239
7240         if (INTEL_GEN(dev_priv) >= 12)
7241                 return port - PORT_D;
7242
7243         return port - PORT_C;
7244 }
7245
7246 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7247 {
7248         switch (port) {
7249         case PORT_A:
7250                 return POWER_DOMAIN_PORT_DDI_A_LANES;
7251         case PORT_B:
7252                 return POWER_DOMAIN_PORT_DDI_B_LANES;
7253         case PORT_C:
7254                 return POWER_DOMAIN_PORT_DDI_C_LANES;
7255         case PORT_D:
7256                 return POWER_DOMAIN_PORT_DDI_D_LANES;
7257         case PORT_E:
7258                 return POWER_DOMAIN_PORT_DDI_E_LANES;
7259         case PORT_F:
7260                 return POWER_DOMAIN_PORT_DDI_F_LANES;
7261         case PORT_G:
7262                 return POWER_DOMAIN_PORT_DDI_G_LANES;
7263         default:
7264                 MISSING_CASE(port);
7265                 return POWER_DOMAIN_PORT_OTHER;
7266         }
7267 }
7268
7269 enum intel_display_power_domain
7270 intel_aux_power_domain(struct intel_digital_port *dig_port)
7271 {
7272         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7273         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7274
7275         if (intel_phy_is_tc(dev_priv, phy) &&
7276             dig_port->tc_mode == TC_PORT_TBT_ALT) {
7277                 switch (dig_port->aux_ch) {
7278                 case AUX_CH_C:
7279                         return POWER_DOMAIN_AUX_C_TBT;
7280                 case AUX_CH_D:
7281                         return POWER_DOMAIN_AUX_D_TBT;
7282                 case AUX_CH_E:
7283                         return POWER_DOMAIN_AUX_E_TBT;
7284                 case AUX_CH_F:
7285                         return POWER_DOMAIN_AUX_F_TBT;
7286                 case AUX_CH_G:
7287                         return POWER_DOMAIN_AUX_G_TBT;
7288                 default:
7289                         MISSING_CASE(dig_port->aux_ch);
7290                         return POWER_DOMAIN_AUX_C_TBT;
7291                 }
7292         }
7293
7294         return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7295 }
7296
7297 /*
7298  * Converts aux_ch to power_domain without caring about TBT ports for that use
7299  * intel_aux_power_domain()
7300  */
7301 enum intel_display_power_domain
7302 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7303 {
7304         switch (aux_ch) {
7305         case AUX_CH_A:
7306                 return POWER_DOMAIN_AUX_A;
7307         case AUX_CH_B:
7308                 return POWER_DOMAIN_AUX_B;
7309         case AUX_CH_C:
7310                 return POWER_DOMAIN_AUX_C;
7311         case AUX_CH_D:
7312                 return POWER_DOMAIN_AUX_D;
7313         case AUX_CH_E:
7314                 return POWER_DOMAIN_AUX_E;
7315         case AUX_CH_F:
7316                 return POWER_DOMAIN_AUX_F;
7317         case AUX_CH_G:
7318                 return POWER_DOMAIN_AUX_G;
7319         default:
7320                 MISSING_CASE(aux_ch);
7321                 return POWER_DOMAIN_AUX_A;
7322         }
7323 }
7324
7325 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7326 {
7327         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7328         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7329         struct drm_encoder *encoder;
7330         enum pipe pipe = crtc->pipe;
7331         u64 mask;
7332         enum transcoder transcoder = crtc_state->cpu_transcoder;
7333
7334         if (!crtc_state->hw.active)
7335                 return 0;
7336
7337         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7338         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7339         if (crtc_state->pch_pfit.enabled ||
7340             crtc_state->pch_pfit.force_thru)
7341                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7342
7343         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7344                                   crtc_state->uapi.encoder_mask) {
7345                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7346
7347                 mask |= BIT_ULL(intel_encoder->power_domain);
7348         }
7349
7350         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7351                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7352
7353         if (crtc_state->shared_dpll)
7354                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7355
7356         return mask;
7357 }
7358
7359 static u64
7360 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7361 {
7362         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7363         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7364         enum intel_display_power_domain domain;
7365         u64 domains, new_domains, old_domains;
7366
7367         old_domains = crtc->enabled_power_domains;
7368         crtc->enabled_power_domains = new_domains =
7369                 get_crtc_power_domains(crtc_state);
7370
7371         domains = new_domains & ~old_domains;
7372
7373         for_each_power_domain(domain, domains)
7374                 intel_display_power_get(dev_priv, domain);
7375
7376         return old_domains & ~new_domains;
7377 }
7378
7379 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7380                                       u64 domains)
7381 {
7382         enum intel_display_power_domain domain;
7383
7384         for_each_power_domain(domain, domains)
7385                 intel_display_power_put_unchecked(dev_priv, domain);
7386 }
7387
7388 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7389                                    struct intel_crtc *crtc)
7390 {
7391         const struct intel_crtc_state *new_crtc_state =
7392                 intel_atomic_get_new_crtc_state(state, crtc);
7393         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7394         enum pipe pipe = crtc->pipe;
7395
7396         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7397                 return;
7398
7399         if (intel_crtc_has_dp_encoder(new_crtc_state))
7400                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7401
7402         intel_set_pipe_timings(new_crtc_state);
7403         intel_set_pipe_src_size(new_crtc_state);
7404
7405         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7406                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7407                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7408         }
7409
7410         i9xx_set_pipeconf(new_crtc_state);
7411
7412         crtc->active = true;
7413
7414         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7415
7416         intel_encoders_pre_pll_enable(state, crtc);
7417
7418         if (IS_CHERRYVIEW(dev_priv)) {
7419                 chv_prepare_pll(crtc, new_crtc_state);
7420                 chv_enable_pll(crtc, new_crtc_state);
7421         } else {
7422                 vlv_prepare_pll(crtc, new_crtc_state);
7423                 vlv_enable_pll(crtc, new_crtc_state);
7424         }
7425
7426         intel_encoders_pre_enable(state, crtc);
7427
7428         i9xx_pfit_enable(new_crtc_state);
7429
7430         intel_color_load_luts(new_crtc_state);
7431         intel_color_commit(new_crtc_state);
7432         /* update DSPCNTR to configure gamma for pipe bottom color */
7433         intel_disable_primary_plane(new_crtc_state);
7434
7435         dev_priv->display.initial_watermarks(state, crtc);
7436         intel_enable_pipe(new_crtc_state);
7437
7438         intel_crtc_vblank_on(new_crtc_state);
7439
7440         intel_encoders_enable(state, crtc);
7441 }
7442
7443 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7444 {
7445         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7446         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7447
7448         intel_de_write(dev_priv, FP0(crtc->pipe),
7449                        crtc_state->dpll_hw_state.fp0);
7450         intel_de_write(dev_priv, FP1(crtc->pipe),
7451                        crtc_state->dpll_hw_state.fp1);
7452 }
7453
7454 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7455                              struct intel_crtc *crtc)
7456 {
7457         const struct intel_crtc_state *new_crtc_state =
7458                 intel_atomic_get_new_crtc_state(state, crtc);
7459         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7460         enum pipe pipe = crtc->pipe;
7461
7462         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7463                 return;
7464
7465         i9xx_set_pll_dividers(new_crtc_state);
7466
7467         if (intel_crtc_has_dp_encoder(new_crtc_state))
7468                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7469
7470         intel_set_pipe_timings(new_crtc_state);
7471         intel_set_pipe_src_size(new_crtc_state);
7472
7473         i9xx_set_pipeconf(new_crtc_state);
7474
7475         crtc->active = true;
7476
7477         if (!IS_GEN(dev_priv, 2))
7478                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7479
7480         intel_encoders_pre_enable(state, crtc);
7481
7482         i9xx_enable_pll(crtc, new_crtc_state);
7483
7484         i9xx_pfit_enable(new_crtc_state);
7485
7486         intel_color_load_luts(new_crtc_state);
7487         intel_color_commit(new_crtc_state);
7488         /* update DSPCNTR to configure gamma for pipe bottom color */
7489         intel_disable_primary_plane(new_crtc_state);
7490
7491         if (dev_priv->display.initial_watermarks)
7492                 dev_priv->display.initial_watermarks(state, crtc);
7493         else
7494                 intel_update_watermarks(crtc);
7495         intel_enable_pipe(new_crtc_state);
7496
7497         intel_crtc_vblank_on(new_crtc_state);
7498
7499         intel_encoders_enable(state, crtc);
7500 }
7501
7502 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7503 {
7504         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7505         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7506
7507         if (!old_crtc_state->gmch_pfit.control)
7508                 return;
7509
7510         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7511
7512         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7513                     intel_de_read(dev_priv, PFIT_CONTROL));
7514         intel_de_write(dev_priv, PFIT_CONTROL, 0);
7515 }
7516
7517 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7518                               struct intel_crtc *crtc)
7519 {
7520         struct intel_crtc_state *old_crtc_state =
7521                 intel_atomic_get_old_crtc_state(state, crtc);
7522         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7523         enum pipe pipe = crtc->pipe;
7524
7525         /*
7526          * On gen2 planes are double buffered but the pipe isn't, so we must
7527          * wait for planes to fully turn off before disabling the pipe.
7528          */
7529         if (IS_GEN(dev_priv, 2))
7530                 intel_wait_for_vblank(dev_priv, pipe);
7531
7532         intel_encoders_disable(state, crtc);
7533
7534         intel_crtc_vblank_off(old_crtc_state);
7535
7536         intel_disable_pipe(old_crtc_state);
7537
7538         i9xx_pfit_disable(old_crtc_state);
7539
7540         intel_encoders_post_disable(state, crtc);
7541
7542         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7543                 if (IS_CHERRYVIEW(dev_priv))
7544                         chv_disable_pll(dev_priv, pipe);
7545                 else if (IS_VALLEYVIEW(dev_priv))
7546                         vlv_disable_pll(dev_priv, pipe);
7547                 else
7548                         i9xx_disable_pll(old_crtc_state);
7549         }
7550
7551         intel_encoders_post_pll_disable(state, crtc);
7552
7553         if (!IS_GEN(dev_priv, 2))
7554                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7555
7556         if (!dev_priv->display.initial_watermarks)
7557                 intel_update_watermarks(crtc);
7558
7559         /* clock the pipe down to 640x480@60 to potentially save power */
7560         if (IS_I830(dev_priv))
7561                 i830_enable_pipe(dev_priv, pipe);
7562 }
7563
7564 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7565                                         struct drm_modeset_acquire_ctx *ctx)
7566 {
7567         struct intel_encoder *encoder;
7568         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7569         struct intel_bw_state *bw_state =
7570                 to_intel_bw_state(dev_priv->bw_obj.state);
7571         struct intel_cdclk_state *cdclk_state =
7572                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7573         struct intel_crtc_state *crtc_state =
7574                 to_intel_crtc_state(crtc->base.state);
7575         enum intel_display_power_domain domain;
7576         struct intel_plane *plane;
7577         struct drm_atomic_state *state;
7578         struct intel_crtc_state *temp_crtc_state;
7579         enum pipe pipe = crtc->pipe;
7580         u64 domains;
7581         int ret;
7582
7583         if (!crtc_state->hw.active)
7584                 return;
7585
7586         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7587                 const struct intel_plane_state *plane_state =
7588                         to_intel_plane_state(plane->base.state);
7589
7590                 if (plane_state->uapi.visible)
7591                         intel_plane_disable_noatomic(crtc, plane);
7592         }
7593
7594         state = drm_atomic_state_alloc(&dev_priv->drm);
7595         if (!state) {
7596                 drm_dbg_kms(&dev_priv->drm,
7597                             "failed to disable [CRTC:%d:%s], out of memory",
7598                             crtc->base.base.id, crtc->base.name);
7599                 return;
7600         }
7601
7602         state->acquire_ctx = ctx;
7603
7604         /* Everything's already locked, -EDEADLK can't happen. */
7605         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7606         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7607
7608         drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7609
7610         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7611
7612         drm_atomic_state_put(state);
7613
7614         drm_dbg_kms(&dev_priv->drm,
7615                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7616                     crtc->base.base.id, crtc->base.name);
7617
7618         crtc->active = false;
7619         crtc->base.enabled = false;
7620
7621         drm_WARN_ON(&dev_priv->drm,
7622                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7623         crtc_state->uapi.active = false;
7624         crtc_state->uapi.connector_mask = 0;
7625         crtc_state->uapi.encoder_mask = 0;
7626         intel_crtc_free_hw_state(crtc_state);
7627         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7628
7629         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7630                 encoder->base.crtc = NULL;
7631
7632         intel_fbc_disable(crtc);
7633         intel_update_watermarks(crtc);
7634         intel_disable_shared_dpll(crtc_state);
7635
7636         domains = crtc->enabled_power_domains;
7637         for_each_power_domain(domain, domains)
7638                 intel_display_power_put_unchecked(dev_priv, domain);
7639         crtc->enabled_power_domains = 0;
7640
7641         dev_priv->active_pipes &= ~BIT(pipe);
7642         cdclk_state->min_cdclk[pipe] = 0;
7643         cdclk_state->min_voltage_level[pipe] = 0;
7644         cdclk_state->active_pipes &= ~BIT(pipe);
7645
7646         bw_state->data_rate[pipe] = 0;
7647         bw_state->num_active_planes[pipe] = 0;
7648 }
7649
7650 /*
7651  * turn all crtc's off, but do not adjust state
7652  * This has to be paired with a call to intel_modeset_setup_hw_state.
7653  */
7654 int intel_display_suspend(struct drm_device *dev)
7655 {
7656         struct drm_i915_private *dev_priv = to_i915(dev);
7657         struct drm_atomic_state *state;
7658         int ret;
7659
7660         state = drm_atomic_helper_suspend(dev);
7661         ret = PTR_ERR_OR_ZERO(state);
7662         if (ret)
7663                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7664                         ret);
7665         else
7666                 dev_priv->modeset_restore_state = state;
7667         return ret;
7668 }
7669
7670 void intel_encoder_destroy(struct drm_encoder *encoder)
7671 {
7672         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7673
7674         drm_encoder_cleanup(encoder);
7675         kfree(intel_encoder);
7676 }
7677
7678 /* Cross check the actual hw state with our own modeset state tracking (and it's
7679  * internal consistency). */
7680 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7681                                          struct drm_connector_state *conn_state)
7682 {
7683         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7684         struct drm_i915_private *i915 = to_i915(connector->base.dev);
7685
7686         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7687                     connector->base.base.id, connector->base.name);
7688
7689         if (connector->get_hw_state(connector)) {
7690                 struct intel_encoder *encoder = intel_attached_encoder(connector);
7691
7692                 I915_STATE_WARN(!crtc_state,
7693                          "connector enabled without attached crtc\n");
7694
7695                 if (!crtc_state)
7696                         return;
7697
7698                 I915_STATE_WARN(!crtc_state->hw.active,
7699                                 "connector is active, but attached crtc isn't\n");
7700
7701                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7702                         return;
7703
7704                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7705                         "atomic encoder doesn't match attached encoder\n");
7706
7707                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7708                         "attached encoder crtc differs from connector crtc\n");
7709         } else {
7710                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7711                                 "attached crtc is active, but connector isn't\n");
7712                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7713                         "best encoder set without crtc!\n");
7714         }
7715 }
7716
7717 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7718 {
7719         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7720                 return crtc_state->fdi_lanes;
7721
7722         return 0;
7723 }
7724
7725 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7726                                struct intel_crtc_state *pipe_config)
7727 {
7728         struct drm_i915_private *dev_priv = to_i915(dev);
7729         struct drm_atomic_state *state = pipe_config->uapi.state;
7730         struct intel_crtc *other_crtc;
7731         struct intel_crtc_state *other_crtc_state;
7732
7733         drm_dbg_kms(&dev_priv->drm,
7734                     "checking fdi config on pipe %c, lanes %i\n",
7735                     pipe_name(pipe), pipe_config->fdi_lanes);
7736         if (pipe_config->fdi_lanes > 4) {
7737                 drm_dbg_kms(&dev_priv->drm,
7738                             "invalid fdi lane config on pipe %c: %i lanes\n",
7739                             pipe_name(pipe), pipe_config->fdi_lanes);
7740                 return -EINVAL;
7741         }
7742
7743         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7744                 if (pipe_config->fdi_lanes > 2) {
7745                         drm_dbg_kms(&dev_priv->drm,
7746                                     "only 2 lanes on haswell, required: %i lanes\n",
7747                                     pipe_config->fdi_lanes);
7748                         return -EINVAL;
7749                 } else {
7750                         return 0;
7751                 }
7752         }
7753
7754         if (INTEL_NUM_PIPES(dev_priv) == 2)
7755                 return 0;
7756
7757         /* Ivybridge 3 pipe is really complicated */
7758         switch (pipe) {
7759         case PIPE_A:
7760                 return 0;
7761         case PIPE_B:
7762                 if (pipe_config->fdi_lanes <= 2)
7763                         return 0;
7764
7765                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7766                 other_crtc_state =
7767                         intel_atomic_get_crtc_state(state, other_crtc);
7768                 if (IS_ERR(other_crtc_state))
7769                         return PTR_ERR(other_crtc_state);
7770
7771                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7772                         drm_dbg_kms(&dev_priv->drm,
7773                                     "invalid shared fdi lane config on pipe %c: %i lanes\n",
7774                                     pipe_name(pipe), pipe_config->fdi_lanes);
7775                         return -EINVAL;
7776                 }
7777                 return 0;
7778         case PIPE_C:
7779                 if (pipe_config->fdi_lanes > 2) {
7780                         drm_dbg_kms(&dev_priv->drm,
7781                                     "only 2 lanes on pipe %c: required %i lanes\n",
7782                                     pipe_name(pipe), pipe_config->fdi_lanes);
7783                         return -EINVAL;
7784                 }
7785
7786                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7787                 other_crtc_state =
7788                         intel_atomic_get_crtc_state(state, other_crtc);
7789                 if (IS_ERR(other_crtc_state))
7790                         return PTR_ERR(other_crtc_state);
7791
7792                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7793                         drm_dbg_kms(&dev_priv->drm,
7794                                     "fdi link B uses too many lanes to enable link C\n");
7795                         return -EINVAL;
7796                 }
7797                 return 0;
7798         default:
7799                 BUG();
7800         }
7801 }
7802
7803 #define RETRY 1
7804 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7805                                   struct intel_crtc_state *pipe_config)
7806 {
7807         struct drm_device *dev = intel_crtc->base.dev;
7808         struct drm_i915_private *i915 = to_i915(dev);
7809         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7810         int lane, link_bw, fdi_dotclock, ret;
7811         bool needs_recompute = false;
7812
7813 retry:
7814         /* FDI is a binary signal running at ~2.7GHz, encoding
7815          * each output octet as 10 bits. The actual frequency
7816          * is stored as a divider into a 100MHz clock, and the
7817          * mode pixel clock is stored in units of 1KHz.
7818          * Hence the bw of each lane in terms of the mode signal
7819          * is:
7820          */
7821         link_bw = intel_fdi_link_freq(i915, pipe_config);
7822
7823         fdi_dotclock = adjusted_mode->crtc_clock;
7824
7825         lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7826                                       pipe_config->pipe_bpp);
7827
7828         pipe_config->fdi_lanes = lane;
7829
7830         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7831                                link_bw, &pipe_config->fdi_m_n, false, false);
7832
7833         ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7834         if (ret == -EDEADLK)
7835                 return ret;
7836
7837         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7838                 pipe_config->pipe_bpp -= 2*3;
7839                 drm_dbg_kms(&i915->drm,
7840                             "fdi link bw constraint, reducing pipe bpp to %i\n",
7841                             pipe_config->pipe_bpp);
7842                 needs_recompute = true;
7843                 pipe_config->bw_constrained = true;
7844
7845                 goto retry;
7846         }
7847
7848         if (needs_recompute)
7849                 return RETRY;
7850
7851         return ret;
7852 }
7853
7854 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7855 {
7856         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7857         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7858
7859         /* IPS only exists on ULT machines and is tied to pipe A. */
7860         if (!hsw_crtc_supports_ips(crtc))
7861                 return false;
7862
7863         if (!i915_modparams.enable_ips)
7864                 return false;
7865
7866         if (crtc_state->pipe_bpp > 24)
7867                 return false;
7868
7869         /*
7870          * We compare against max which means we must take
7871          * the increased cdclk requirement into account when
7872          * calculating the new cdclk.
7873          *
7874          * Should measure whether using a lower cdclk w/o IPS
7875          */
7876         if (IS_BROADWELL(dev_priv) &&
7877             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7878                 return false;
7879
7880         return true;
7881 }
7882
7883 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7884 {
7885         struct drm_i915_private *dev_priv =
7886                 to_i915(crtc_state->uapi.crtc->dev);
7887         struct intel_atomic_state *state =
7888                 to_intel_atomic_state(crtc_state->uapi.state);
7889
7890         crtc_state->ips_enabled = false;
7891
7892         if (!hsw_crtc_state_ips_capable(crtc_state))
7893                 return 0;
7894
7895         /*
7896          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7897          * enabled and disabled dynamically based on package C states,
7898          * user space can't make reliable use of the CRCs, so let's just
7899          * completely disable it.
7900          */
7901         if (crtc_state->crc_enabled)
7902                 return 0;
7903
7904         /* IPS should be fine as long as at least one plane is enabled. */
7905         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7906                 return 0;
7907
7908         if (IS_BROADWELL(dev_priv)) {
7909                 const struct intel_cdclk_state *cdclk_state;
7910
7911                 cdclk_state = intel_atomic_get_cdclk_state(state);
7912                 if (IS_ERR(cdclk_state))
7913                         return PTR_ERR(cdclk_state);
7914
7915                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7916                 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
7917                         return 0;
7918         }
7919
7920         crtc_state->ips_enabled = true;
7921
7922         return 0;
7923 }
7924
7925 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7926 {
7927         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7928
7929         /* GDG double wide on either pipe, otherwise pipe A only */
7930         return INTEL_GEN(dev_priv) < 4 &&
7931                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7932 }
7933
7934 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7935 {
7936         u32 pixel_rate;
7937
7938         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7939
7940         /*
7941          * We only use IF-ID interlacing. If we ever use
7942          * PF-ID we'll need to adjust the pixel_rate here.
7943          */
7944
7945         if (pipe_config->pch_pfit.enabled) {
7946                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7947                 u32 pfit_size = pipe_config->pch_pfit.size;
7948
7949                 pipe_w = pipe_config->pipe_src_w;
7950                 pipe_h = pipe_config->pipe_src_h;
7951
7952                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7953                 pfit_h = pfit_size & 0xFFFF;
7954                 if (pipe_w < pfit_w)
7955                         pipe_w = pfit_w;
7956                 if (pipe_h < pfit_h)
7957                         pipe_h = pfit_h;
7958
7959                 if (drm_WARN_ON(pipe_config->uapi.crtc->dev,
7960                                 !pfit_w || !pfit_h))
7961                         return pixel_rate;
7962
7963                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7964                                      pfit_w * pfit_h);
7965         }
7966
7967         return pixel_rate;
7968 }
7969
7970 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7971 {
7972         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7973
7974         if (HAS_GMCH(dev_priv))
7975                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7976                 crtc_state->pixel_rate =
7977                         crtc_state->hw.adjusted_mode.crtc_clock;
7978         else
7979                 crtc_state->pixel_rate =
7980                         ilk_pipe_pixel_rate(crtc_state);
7981 }
7982
7983 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7984                                      struct intel_crtc_state *pipe_config)
7985 {
7986         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7987         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7988         int clock_limit = dev_priv->max_dotclk_freq;
7989
7990         if (INTEL_GEN(dev_priv) < 4) {
7991                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7992
7993                 /*
7994                  * Enable double wide mode when the dot clock
7995                  * is > 90% of the (display) core speed.
7996                  */
7997                 if (intel_crtc_supports_double_wide(crtc) &&
7998                     adjusted_mode->crtc_clock > clock_limit) {
7999                         clock_limit = dev_priv->max_dotclk_freq;
8000                         pipe_config->double_wide = true;
8001                 }
8002         }
8003
8004         if (adjusted_mode->crtc_clock > clock_limit) {
8005                 drm_dbg_kms(&dev_priv->drm,
8006                             "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8007                             adjusted_mode->crtc_clock, clock_limit,
8008                             yesno(pipe_config->double_wide));
8009                 return -EINVAL;
8010         }
8011
8012         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8013              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8014              pipe_config->hw.ctm) {
8015                 /*
8016                  * There is only one pipe CSC unit per pipe, and we need that
8017                  * for output conversion from RGB->YCBCR. So if CTM is already
8018                  * applied we can't support YCBCR420 output.
8019                  */
8020                 drm_dbg_kms(&dev_priv->drm,
8021                             "YCBCR420 and CTM together are not possible\n");
8022                 return -EINVAL;
8023         }
8024
8025         /*
8026          * Pipe horizontal size must be even in:
8027          * - DVO ganged mode
8028          * - LVDS dual channel mode
8029          * - Double wide pipe
8030          */
8031         if (pipe_config->pipe_src_w & 1) {
8032                 if (pipe_config->double_wide) {
8033                         drm_dbg_kms(&dev_priv->drm,
8034                                     "Odd pipe source width not supported with double wide pipe\n");
8035                         return -EINVAL;
8036                 }
8037
8038                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8039                     intel_is_dual_link_lvds(dev_priv)) {
8040                         drm_dbg_kms(&dev_priv->drm,
8041                                     "Odd pipe source width not supported with dual link LVDS\n");
8042                         return -EINVAL;
8043                 }
8044         }
8045
8046         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8047          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8048          */
8049         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8050                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8051                 return -EINVAL;
8052
8053         intel_crtc_compute_pixel_rate(pipe_config);
8054
8055         if (pipe_config->has_pch_encoder)
8056                 return ilk_fdi_compute_config(crtc, pipe_config);
8057
8058         return 0;
8059 }
8060
8061 static void
8062 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8063 {
8064         while (*num > DATA_LINK_M_N_MASK ||
8065                *den > DATA_LINK_M_N_MASK) {
8066                 *num >>= 1;
8067                 *den >>= 1;
8068         }
8069 }
8070
8071 static void compute_m_n(unsigned int m, unsigned int n,
8072                         u32 *ret_m, u32 *ret_n,
8073                         bool constant_n)
8074 {
8075         /*
8076          * Several DP dongles in particular seem to be fussy about
8077          * too large link M/N values. Give N value as 0x8000 that
8078          * should be acceptable by specific devices. 0x8000 is the
8079          * specified fixed N value for asynchronous clock mode,
8080          * which the devices expect also in synchronous clock mode.
8081          */
8082         if (constant_n)
8083                 *ret_n = 0x8000;
8084         else
8085                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8086
8087         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8088         intel_reduce_m_n_ratio(ret_m, ret_n);
8089 }
8090
8091 void
8092 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8093                        int pixel_clock, int link_clock,
8094                        struct intel_link_m_n *m_n,
8095                        bool constant_n, bool fec_enable)
8096 {
8097         u32 data_clock = bits_per_pixel * pixel_clock;
8098
8099         if (fec_enable)
8100                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8101
8102         m_n->tu = 64;
8103         compute_m_n(data_clock,
8104                     link_clock * nlanes * 8,
8105                     &m_n->gmch_m, &m_n->gmch_n,
8106                     constant_n);
8107
8108         compute_m_n(pixel_clock, link_clock,
8109                     &m_n->link_m, &m_n->link_n,
8110                     constant_n);
8111 }
8112
8113 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8114 {
8115         /*
8116          * There may be no VBT; and if the BIOS enabled SSC we can
8117          * just keep using it to avoid unnecessary flicker.  Whereas if the
8118          * BIOS isn't using it, don't assume it will work even if the VBT
8119          * indicates as much.
8120          */
8121         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8122                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8123                                                        PCH_DREF_CONTROL) &
8124                         DREF_SSC1_ENABLE;
8125
8126                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8127                         drm_dbg_kms(&dev_priv->drm,
8128                                     "SSC %s by BIOS, overriding VBT which says %s\n",
8129                                     enableddisabled(bios_lvds_use_ssc),
8130                                     enableddisabled(dev_priv->vbt.lvds_use_ssc));
8131                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8132                 }
8133         }
8134 }
8135
8136 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8137 {
8138         if (i915_modparams.panel_use_ssc >= 0)
8139                 return i915_modparams.panel_use_ssc != 0;
8140         return dev_priv->vbt.lvds_use_ssc
8141                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8142 }
8143
8144 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8145 {
8146         return (1 << dpll->n) << 16 | dpll->m2;
8147 }
8148
8149 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8150 {
8151         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8152 }
8153
8154 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8155                                      struct intel_crtc_state *crtc_state,
8156                                      struct dpll *reduced_clock)
8157 {
8158         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8159         u32 fp, fp2 = 0;
8160
8161         if (IS_PINEVIEW(dev_priv)) {
8162                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8163                 if (reduced_clock)
8164                         fp2 = pnv_dpll_compute_fp(reduced_clock);
8165         } else {
8166                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8167                 if (reduced_clock)
8168                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
8169         }
8170
8171         crtc_state->dpll_hw_state.fp0 = fp;
8172
8173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8174             reduced_clock) {
8175                 crtc_state->dpll_hw_state.fp1 = fp2;
8176         } else {
8177                 crtc_state->dpll_hw_state.fp1 = fp;
8178         }
8179 }
8180
8181 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8182                 pipe)
8183 {
8184         u32 reg_val;
8185
8186         /*
8187          * PLLB opamp always calibrates to max value of 0x3f, force enable it
8188          * and set it to a reasonable value instead.
8189          */
8190         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8191         reg_val &= 0xffffff00;
8192         reg_val |= 0x00000030;
8193         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8194
8195         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8196         reg_val &= 0x00ffffff;
8197         reg_val |= 0x8c000000;
8198         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8199
8200         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8201         reg_val &= 0xffffff00;
8202         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8203
8204         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8205         reg_val &= 0x00ffffff;
8206         reg_val |= 0xb0000000;
8207         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8208 }
8209
8210 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8211                                          const struct intel_link_m_n *m_n)
8212 {
8213         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8214         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8215         enum pipe pipe = crtc->pipe;
8216
8217         intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8218                        TU_SIZE(m_n->tu) | m_n->gmch_m);
8219         intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8220         intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8221         intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8222 }
8223
8224 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8225                                  enum transcoder transcoder)
8226 {
8227         if (IS_HASWELL(dev_priv))
8228                 return transcoder == TRANSCODER_EDP;
8229
8230         /*
8231          * Strictly speaking some registers are available before
8232          * gen7, but we only support DRRS on gen7+
8233          */
8234         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8235 }
8236
8237 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8238                                          const struct intel_link_m_n *m_n,
8239                                          const struct intel_link_m_n *m2_n2)
8240 {
8241         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8242         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8243         enum pipe pipe = crtc->pipe;
8244         enum transcoder transcoder = crtc_state->cpu_transcoder;
8245
8246         if (INTEL_GEN(dev_priv) >= 5) {
8247                 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8248                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8249                 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8250                                m_n->gmch_n);
8251                 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8252                                m_n->link_m);
8253                 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8254                                m_n->link_n);
8255                 /*
8256                  *  M2_N2 registers are set only if DRRS is supported
8257                  * (to make sure the registers are not unnecessarily accessed).
8258                  */
8259                 if (m2_n2 && crtc_state->has_drrs &&
8260                     transcoder_has_m2_n2(dev_priv, transcoder)) {
8261                         intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8262                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8263                         intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8264                                        m2_n2->gmch_n);
8265                         intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8266                                        m2_n2->link_m);
8267                         intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8268                                        m2_n2->link_n);
8269                 }
8270         } else {
8271                 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8272                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8273                 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8274                 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8275                 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8276         }
8277 }
8278
8279 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8280 {
8281         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8282         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8283
8284         if (m_n == M1_N1) {
8285                 dp_m_n = &crtc_state->dp_m_n;
8286                 dp_m2_n2 = &crtc_state->dp_m2_n2;
8287         } else if (m_n == M2_N2) {
8288
8289                 /*
8290                  * M2_N2 registers are not supported. Hence m2_n2 divider value
8291                  * needs to be programmed into M1_N1.
8292                  */
8293                 dp_m_n = &crtc_state->dp_m2_n2;
8294         } else {
8295                 drm_err(&i915->drm, "Unsupported divider value\n");
8296                 return;
8297         }
8298
8299         if (crtc_state->has_pch_encoder)
8300                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8301         else
8302                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8303 }
8304
8305 static void vlv_compute_dpll(struct intel_crtc *crtc,
8306                              struct intel_crtc_state *pipe_config)
8307 {
8308         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8309                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8310         if (crtc->pipe != PIPE_A)
8311                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8312
8313         /* DPLL not used with DSI, but still need the rest set up */
8314         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8315                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8316                         DPLL_EXT_BUFFER_ENABLE_VLV;
8317
8318         pipe_config->dpll_hw_state.dpll_md =
8319                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8320 }
8321
8322 static void chv_compute_dpll(struct intel_crtc *crtc,
8323                              struct intel_crtc_state *pipe_config)
8324 {
8325         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8326                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8327         if (crtc->pipe != PIPE_A)
8328                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8329
8330         /* DPLL not used with DSI, but still need the rest set up */
8331         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8332                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8333
8334         pipe_config->dpll_hw_state.dpll_md =
8335                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8336 }
8337
8338 static void vlv_prepare_pll(struct intel_crtc *crtc,
8339                             const struct intel_crtc_state *pipe_config)
8340 {
8341         struct drm_device *dev = crtc->base.dev;
8342         struct drm_i915_private *dev_priv = to_i915(dev);
8343         enum pipe pipe = crtc->pipe;
8344         u32 mdiv;
8345         u32 bestn, bestm1, bestm2, bestp1, bestp2;
8346         u32 coreclk, reg_val;
8347
8348         /* Enable Refclk */
8349         intel_de_write(dev_priv, DPLL(pipe),
8350                        pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8351
8352         /* No need to actually set up the DPLL with DSI */
8353         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8354                 return;
8355
8356         vlv_dpio_get(dev_priv);
8357
8358         bestn = pipe_config->dpll.n;
8359         bestm1 = pipe_config->dpll.m1;
8360         bestm2 = pipe_config->dpll.m2;
8361         bestp1 = pipe_config->dpll.p1;
8362         bestp2 = pipe_config->dpll.p2;
8363
8364         /* See eDP HDMI DPIO driver vbios notes doc */
8365
8366         /* PLL B needs special handling */
8367         if (pipe == PIPE_B)
8368                 vlv_pllb_recal_opamp(dev_priv, pipe);
8369
8370         /* Set up Tx target for periodic Rcomp update */
8371         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8372
8373         /* Disable target IRef on PLL */
8374         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8375         reg_val &= 0x00ffffff;
8376         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8377
8378         /* Disable fast lock */
8379         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8380
8381         /* Set idtafcrecal before PLL is enabled */
8382         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8383         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8384         mdiv |= ((bestn << DPIO_N_SHIFT));
8385         mdiv |= (1 << DPIO_K_SHIFT);
8386
8387         /*
8388          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8389          * but we don't support that).
8390          * Note: don't use the DAC post divider as it seems unstable.
8391          */
8392         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8393         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8394
8395         mdiv |= DPIO_ENABLE_CALIBRATION;
8396         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8397
8398         /* Set HBR and RBR LPF coefficients */
8399         if (pipe_config->port_clock == 162000 ||
8400             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8401             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8402                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8403                                  0x009f0003);
8404         else
8405                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8406                                  0x00d0000f);
8407
8408         if (intel_crtc_has_dp_encoder(pipe_config)) {
8409                 /* Use SSC source */
8410                 if (pipe == PIPE_A)
8411                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8412                                          0x0df40000);
8413                 else
8414                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8415                                          0x0df70000);
8416         } else { /* HDMI or VGA */
8417                 /* Use bend source */
8418                 if (pipe == PIPE_A)
8419                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8420                                          0x0df70000);
8421                 else
8422                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8423                                          0x0df40000);
8424         }
8425
8426         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8427         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8428         if (intel_crtc_has_dp_encoder(pipe_config))
8429                 coreclk |= 0x01000000;
8430         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8431
8432         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8433
8434         vlv_dpio_put(dev_priv);
8435 }
8436
8437 static void chv_prepare_pll(struct intel_crtc *crtc,
8438                             const struct intel_crtc_state *pipe_config)
8439 {
8440         struct drm_device *dev = crtc->base.dev;
8441         struct drm_i915_private *dev_priv = to_i915(dev);
8442         enum pipe pipe = crtc->pipe;
8443         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8444         u32 loopfilter, tribuf_calcntr;
8445         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8446         u32 dpio_val;
8447         int vco;
8448
8449         /* Enable Refclk and SSC */
8450         intel_de_write(dev_priv, DPLL(pipe),
8451                        pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8452
8453         /* No need to actually set up the DPLL with DSI */
8454         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8455                 return;
8456
8457         bestn = pipe_config->dpll.n;
8458         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8459         bestm1 = pipe_config->dpll.m1;
8460         bestm2 = pipe_config->dpll.m2 >> 22;
8461         bestp1 = pipe_config->dpll.p1;
8462         bestp2 = pipe_config->dpll.p2;
8463         vco = pipe_config->dpll.vco;
8464         dpio_val = 0;
8465         loopfilter = 0;
8466
8467         vlv_dpio_get(dev_priv);
8468
8469         /* p1 and p2 divider */
8470         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8471                         5 << DPIO_CHV_S1_DIV_SHIFT |
8472                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8473                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8474                         1 << DPIO_CHV_K_DIV_SHIFT);
8475
8476         /* Feedback post-divider - m2 */
8477         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8478
8479         /* Feedback refclk divider - n and m1 */
8480         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8481                         DPIO_CHV_M1_DIV_BY_2 |
8482                         1 << DPIO_CHV_N_DIV_SHIFT);
8483
8484         /* M2 fraction division */
8485         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8486
8487         /* M2 fraction division enable */
8488         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8489         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8490         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8491         if (bestm2_frac)
8492                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8493         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8494
8495         /* Program digital lock detect threshold */
8496         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8497         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8498                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8499         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8500         if (!bestm2_frac)
8501                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8502         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8503
8504         /* Loop filter */
8505         if (vco == 5400000) {
8506                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8507                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8508                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8509                 tribuf_calcntr = 0x9;
8510         } else if (vco <= 6200000) {
8511                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8512                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8513                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8514                 tribuf_calcntr = 0x9;
8515         } else if (vco <= 6480000) {
8516                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8517                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8518                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8519                 tribuf_calcntr = 0x8;
8520         } else {
8521                 /* Not supported. Apply the same limits as in the max case */
8522                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8523                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8524                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8525                 tribuf_calcntr = 0;
8526         }
8527         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8528
8529         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8530         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8531         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8532         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8533
8534         /* AFC Recal */
8535         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8536                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8537                         DPIO_AFC_RECAL);
8538
8539         vlv_dpio_put(dev_priv);
8540 }
8541
8542 /**
8543  * vlv_force_pll_on - forcibly enable just the PLL
8544  * @dev_priv: i915 private structure
8545  * @pipe: pipe PLL to enable
8546  * @dpll: PLL configuration
8547  *
8548  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8549  * in cases where we need the PLL enabled even when @pipe is not going to
8550  * be enabled.
8551  */
8552 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8553                      const struct dpll *dpll)
8554 {
8555         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8556         struct intel_crtc_state *pipe_config;
8557
8558         pipe_config = intel_crtc_state_alloc(crtc);
8559         if (!pipe_config)
8560                 return -ENOMEM;
8561
8562         pipe_config->cpu_transcoder = (enum transcoder)pipe;
8563         pipe_config->pixel_multiplier = 1;
8564         pipe_config->dpll = *dpll;
8565
8566         if (IS_CHERRYVIEW(dev_priv)) {
8567                 chv_compute_dpll(crtc, pipe_config);
8568                 chv_prepare_pll(crtc, pipe_config);
8569                 chv_enable_pll(crtc, pipe_config);
8570         } else {
8571                 vlv_compute_dpll(crtc, pipe_config);
8572                 vlv_prepare_pll(crtc, pipe_config);
8573                 vlv_enable_pll(crtc, pipe_config);
8574         }
8575
8576         kfree(pipe_config);
8577
8578         return 0;
8579 }
8580
8581 /**
8582  * vlv_force_pll_off - forcibly disable just the PLL
8583  * @dev_priv: i915 private structure
8584  * @pipe: pipe PLL to disable
8585  *
8586  * Disable the PLL for @pipe. To be used in cases where we need
8587  * the PLL enabled even when @pipe is not going to be enabled.
8588  */
8589 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8590 {
8591         if (IS_CHERRYVIEW(dev_priv))
8592                 chv_disable_pll(dev_priv, pipe);
8593         else
8594                 vlv_disable_pll(dev_priv, pipe);
8595 }
8596
8597 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8598                               struct intel_crtc_state *crtc_state,
8599                               struct dpll *reduced_clock)
8600 {
8601         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8602         u32 dpll;
8603         struct dpll *clock = &crtc_state->dpll;
8604
8605         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8606
8607         dpll = DPLL_VGA_MODE_DIS;
8608
8609         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8610                 dpll |= DPLLB_MODE_LVDS;
8611         else
8612                 dpll |= DPLLB_MODE_DAC_SERIAL;
8613
8614         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8615             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8616                 dpll |= (crtc_state->pixel_multiplier - 1)
8617                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8618         }
8619
8620         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8621             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8622                 dpll |= DPLL_SDVO_HIGH_SPEED;
8623
8624         if (intel_crtc_has_dp_encoder(crtc_state))
8625                 dpll |= DPLL_SDVO_HIGH_SPEED;
8626
8627         /* compute bitmask from p1 value */
8628         if (IS_PINEVIEW(dev_priv))
8629                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8630         else {
8631                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8632                 if (IS_G4X(dev_priv) && reduced_clock)
8633                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8634         }
8635         switch (clock->p2) {
8636         case 5:
8637                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8638                 break;
8639         case 7:
8640                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8641                 break;
8642         case 10:
8643                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8644                 break;
8645         case 14:
8646                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8647                 break;
8648         }
8649         if (INTEL_GEN(dev_priv) >= 4)
8650                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8651
8652         if (crtc_state->sdvo_tv_clock)
8653                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8654         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8655                  intel_panel_use_ssc(dev_priv))
8656                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8657         else
8658                 dpll |= PLL_REF_INPUT_DREFCLK;
8659
8660         dpll |= DPLL_VCO_ENABLE;
8661         crtc_state->dpll_hw_state.dpll = dpll;
8662
8663         if (INTEL_GEN(dev_priv) >= 4) {
8664                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8665                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8666                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8667         }
8668 }
8669
8670 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8671                               struct intel_crtc_state *crtc_state,
8672                               struct dpll *reduced_clock)
8673 {
8674         struct drm_device *dev = crtc->base.dev;
8675         struct drm_i915_private *dev_priv = to_i915(dev);
8676         u32 dpll;
8677         struct dpll *clock = &crtc_state->dpll;
8678
8679         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8680
8681         dpll = DPLL_VGA_MODE_DIS;
8682
8683         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8684                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8685         } else {
8686                 if (clock->p1 == 2)
8687                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8688                 else
8689                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8690                 if (clock->p2 == 4)
8691                         dpll |= PLL_P2_DIVIDE_BY_4;
8692         }
8693
8694         /*
8695          * Bspec:
8696          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8697          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8698          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8699          *  Enable) must be set to “1” in both the DPLL A Control Register
8700          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8701          *
8702          * For simplicity We simply keep both bits always enabled in
8703          * both DPLLS. The spec says we should disable the DVO 2X clock
8704          * when not needed, but this seems to work fine in practice.
8705          */
8706         if (IS_I830(dev_priv) ||
8707             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8708                 dpll |= DPLL_DVO_2X_MODE;
8709
8710         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8711             intel_panel_use_ssc(dev_priv))
8712                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8713         else
8714                 dpll |= PLL_REF_INPUT_DREFCLK;
8715
8716         dpll |= DPLL_VCO_ENABLE;
8717         crtc_state->dpll_hw_state.dpll = dpll;
8718 }
8719
8720 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8721 {
8722         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8723         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8724         enum pipe pipe = crtc->pipe;
8725         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8726         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8727         u32 crtc_vtotal, crtc_vblank_end;
8728         int vsyncshift = 0;
8729
8730         /* We need to be careful not to changed the adjusted mode, for otherwise
8731          * the hw state checker will get angry at the mismatch. */
8732         crtc_vtotal = adjusted_mode->crtc_vtotal;
8733         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8734
8735         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8736                 /* the chip adds 2 halflines automatically */
8737                 crtc_vtotal -= 1;
8738                 crtc_vblank_end -= 1;
8739
8740                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8741                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8742                 else
8743                         vsyncshift = adjusted_mode->crtc_hsync_start -
8744                                 adjusted_mode->crtc_htotal / 2;
8745                 if (vsyncshift < 0)
8746                         vsyncshift += adjusted_mode->crtc_htotal;
8747         }
8748
8749         if (INTEL_GEN(dev_priv) > 3)
8750                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8751                                vsyncshift);
8752
8753         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8754                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8755         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8756                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8757         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8758                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8759
8760         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8761                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8762         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8763                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8764         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8765                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8766
8767         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8768          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8769          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8770          * bits. */
8771         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8772             (pipe == PIPE_B || pipe == PIPE_C))
8773                 intel_de_write(dev_priv, VTOTAL(pipe),
8774                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8775
8776 }
8777
8778 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8779 {
8780         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8781         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8782         enum pipe pipe = crtc->pipe;
8783
8784         /* pipesrc controls the size that is scaled from, which should
8785          * always be the user's requested size.
8786          */
8787         intel_de_write(dev_priv, PIPESRC(pipe),
8788                        ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8789 }
8790
8791 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8792 {
8793         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8794         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8795
8796         if (IS_GEN(dev_priv, 2))
8797                 return false;
8798
8799         if (INTEL_GEN(dev_priv) >= 9 ||
8800             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8801                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8802         else
8803                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8804 }
8805
8806 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8807                                    struct intel_crtc_state *pipe_config)
8808 {
8809         struct drm_device *dev = crtc->base.dev;
8810         struct drm_i915_private *dev_priv = to_i915(dev);
8811         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8812         u32 tmp;
8813
8814         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8815         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8816         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8817
8818         if (!transcoder_is_dsi(cpu_transcoder)) {
8819                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8820                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8821                                                         (tmp & 0xffff) + 1;
8822                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8823                                                 ((tmp >> 16) & 0xffff) + 1;
8824         }
8825         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8826         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8827         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8828
8829         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8830         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8831         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8832
8833         if (!transcoder_is_dsi(cpu_transcoder)) {
8834                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8835                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8836                                                         (tmp & 0xffff) + 1;
8837                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8838                                                 ((tmp >> 16) & 0xffff) + 1;
8839         }
8840         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8841         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8842         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8843
8844         if (intel_pipe_is_interlaced(pipe_config)) {
8845                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8846                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8847                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8848         }
8849 }
8850
8851 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8852                                     struct intel_crtc_state *pipe_config)
8853 {
8854         struct drm_device *dev = crtc->base.dev;
8855         struct drm_i915_private *dev_priv = to_i915(dev);
8856         u32 tmp;
8857
8858         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
8859         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8860         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8861
8862         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8863         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8864 }
8865
8866 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8867                                  struct intel_crtc_state *pipe_config)
8868 {
8869         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8870         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8871         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8872         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8873
8874         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8875         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8876         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8877         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8878
8879         mode->flags = pipe_config->hw.adjusted_mode.flags;
8880         mode->type = DRM_MODE_TYPE_DRIVER;
8881
8882         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8883
8884         mode->hsync = drm_mode_hsync(mode);
8885         mode->vrefresh = drm_mode_vrefresh(mode);
8886         drm_mode_set_name(mode);
8887 }
8888
8889 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8890 {
8891         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8892         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8893         u32 pipeconf;
8894
8895         pipeconf = 0;
8896
8897         /* we keep both pipes enabled on 830 */
8898         if (IS_I830(dev_priv))
8899                 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8900
8901         if (crtc_state->double_wide)
8902                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8903
8904         /* only g4x and later have fancy bpc/dither controls */
8905         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8906             IS_CHERRYVIEW(dev_priv)) {
8907                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8908                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8909                         pipeconf |= PIPECONF_DITHER_EN |
8910                                     PIPECONF_DITHER_TYPE_SP;
8911
8912                 switch (crtc_state->pipe_bpp) {
8913                 case 18:
8914                         pipeconf |= PIPECONF_6BPC;
8915                         break;
8916                 case 24:
8917                         pipeconf |= PIPECONF_8BPC;
8918                         break;
8919                 case 30:
8920                         pipeconf |= PIPECONF_10BPC;
8921                         break;
8922                 default:
8923                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8924                         BUG();
8925                 }
8926         }
8927
8928         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8929                 if (INTEL_GEN(dev_priv) < 4 ||
8930                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8931                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8932                 else
8933                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8934         } else {
8935                 pipeconf |= PIPECONF_PROGRESSIVE;
8936         }
8937
8938         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8939              crtc_state->limited_color_range)
8940                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8941
8942         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8943
8944         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8945
8946         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
8947         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
8948 }
8949
8950 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8951                                    struct intel_crtc_state *crtc_state)
8952 {
8953         struct drm_device *dev = crtc->base.dev;
8954         struct drm_i915_private *dev_priv = to_i915(dev);
8955         const struct intel_limit *limit;
8956         int refclk = 48000;
8957
8958         memset(&crtc_state->dpll_hw_state, 0,
8959                sizeof(crtc_state->dpll_hw_state));
8960
8961         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8962                 if (intel_panel_use_ssc(dev_priv)) {
8963                         refclk = dev_priv->vbt.lvds_ssc_freq;
8964                         drm_dbg_kms(&dev_priv->drm,
8965                                     "using SSC reference clock of %d kHz\n",
8966                                     refclk);
8967                 }
8968
8969                 limit = &intel_limits_i8xx_lvds;
8970         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8971                 limit = &intel_limits_i8xx_dvo;
8972         } else {
8973                 limit = &intel_limits_i8xx_dac;
8974         }
8975
8976         if (!crtc_state->clock_set &&
8977             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8978                                  refclk, NULL, &crtc_state->dpll)) {
8979                 drm_err(&dev_priv->drm,
8980                         "Couldn't find PLL settings for mode!\n");
8981                 return -EINVAL;
8982         }
8983
8984         i8xx_compute_dpll(crtc, crtc_state, NULL);
8985
8986         return 0;
8987 }
8988
8989 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8990                                   struct intel_crtc_state *crtc_state)
8991 {
8992         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8993         const struct intel_limit *limit;
8994         int refclk = 96000;
8995
8996         memset(&crtc_state->dpll_hw_state, 0,
8997                sizeof(crtc_state->dpll_hw_state));
8998
8999         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9000                 if (intel_panel_use_ssc(dev_priv)) {
9001                         refclk = dev_priv->vbt.lvds_ssc_freq;
9002                         drm_dbg_kms(&dev_priv->drm,
9003                                     "using SSC reference clock of %d kHz\n",
9004                                     refclk);
9005                 }
9006
9007                 if (intel_is_dual_link_lvds(dev_priv))
9008                         limit = &intel_limits_g4x_dual_channel_lvds;
9009                 else
9010                         limit = &intel_limits_g4x_single_channel_lvds;
9011         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9012                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9013                 limit = &intel_limits_g4x_hdmi;
9014         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9015                 limit = &intel_limits_g4x_sdvo;
9016         } else {
9017                 /* The option is for other outputs */
9018                 limit = &intel_limits_i9xx_sdvo;
9019         }
9020
9021         if (!crtc_state->clock_set &&
9022             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9023                                 refclk, NULL, &crtc_state->dpll)) {
9024                 drm_err(&dev_priv->drm,
9025                         "Couldn't find PLL settings for mode!\n");
9026                 return -EINVAL;
9027         }
9028
9029         i9xx_compute_dpll(crtc, crtc_state, NULL);
9030
9031         return 0;
9032 }
9033
9034 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9035                                   struct intel_crtc_state *crtc_state)
9036 {
9037         struct drm_device *dev = crtc->base.dev;
9038         struct drm_i915_private *dev_priv = to_i915(dev);
9039         const struct intel_limit *limit;
9040         int refclk = 96000;
9041
9042         memset(&crtc_state->dpll_hw_state, 0,
9043                sizeof(crtc_state->dpll_hw_state));
9044
9045         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9046                 if (intel_panel_use_ssc(dev_priv)) {
9047                         refclk = dev_priv->vbt.lvds_ssc_freq;
9048                         drm_dbg_kms(&dev_priv->drm,
9049                                     "using SSC reference clock of %d kHz\n",
9050                                     refclk);
9051                 }
9052
9053                 limit = &pnv_limits_lvds;
9054         } else {
9055                 limit = &pnv_limits_sdvo;
9056         }
9057
9058         if (!crtc_state->clock_set &&
9059             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9060                                 refclk, NULL, &crtc_state->dpll)) {
9061                 drm_err(&dev_priv->drm,
9062                         "Couldn't find PLL settings for mode!\n");
9063                 return -EINVAL;
9064         }
9065
9066         i9xx_compute_dpll(crtc, crtc_state, NULL);
9067
9068         return 0;
9069 }
9070
9071 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9072                                    struct intel_crtc_state *crtc_state)
9073 {
9074         struct drm_device *dev = crtc->base.dev;
9075         struct drm_i915_private *dev_priv = to_i915(dev);
9076         const struct intel_limit *limit;
9077         int refclk = 96000;
9078
9079         memset(&crtc_state->dpll_hw_state, 0,
9080                sizeof(crtc_state->dpll_hw_state));
9081
9082         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9083                 if (intel_panel_use_ssc(dev_priv)) {
9084                         refclk = dev_priv->vbt.lvds_ssc_freq;
9085                         drm_dbg_kms(&dev_priv->drm,
9086                                     "using SSC reference clock of %d kHz\n",
9087                                     refclk);
9088                 }
9089
9090                 limit = &intel_limits_i9xx_lvds;
9091         } else {
9092                 limit = &intel_limits_i9xx_sdvo;
9093         }
9094
9095         if (!crtc_state->clock_set &&
9096             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9097                                  refclk, NULL, &crtc_state->dpll)) {
9098                 drm_err(&dev_priv->drm,
9099                         "Couldn't find PLL settings for mode!\n");
9100                 return -EINVAL;
9101         }
9102
9103         i9xx_compute_dpll(crtc, crtc_state, NULL);
9104
9105         return 0;
9106 }
9107
9108 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9109                                   struct intel_crtc_state *crtc_state)
9110 {
9111         int refclk = 100000;
9112         const struct intel_limit *limit = &intel_limits_chv;
9113         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9114
9115         memset(&crtc_state->dpll_hw_state, 0,
9116                sizeof(crtc_state->dpll_hw_state));
9117
9118         if (!crtc_state->clock_set &&
9119             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9120                                 refclk, NULL, &crtc_state->dpll)) {
9121                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9122                 return -EINVAL;
9123         }
9124
9125         chv_compute_dpll(crtc, crtc_state);
9126
9127         return 0;
9128 }
9129
9130 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9131                                   struct intel_crtc_state *crtc_state)
9132 {
9133         int refclk = 100000;
9134         const struct intel_limit *limit = &intel_limits_vlv;
9135         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9136
9137         memset(&crtc_state->dpll_hw_state, 0,
9138                sizeof(crtc_state->dpll_hw_state));
9139
9140         if (!crtc_state->clock_set &&
9141             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9142                                 refclk, NULL, &crtc_state->dpll)) {
9143                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
9144                 return -EINVAL;
9145         }
9146
9147         vlv_compute_dpll(crtc, crtc_state);
9148
9149         return 0;
9150 }
9151
9152 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9153 {
9154         if (IS_I830(dev_priv))
9155                 return false;
9156
9157         return INTEL_GEN(dev_priv) >= 4 ||
9158                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9159 }
9160
9161 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
9162                                  struct intel_crtc_state *pipe_config)
9163 {
9164         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9165         u32 tmp;
9166
9167         if (!i9xx_has_pfit(dev_priv))
9168                 return;
9169
9170         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9171         if (!(tmp & PFIT_ENABLE))
9172                 return;
9173
9174         /* Check whether the pfit is attached to our pipe. */
9175         if (INTEL_GEN(dev_priv) < 4) {
9176                 if (crtc->pipe != PIPE_B)
9177                         return;
9178         } else {
9179                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9180                         return;
9181         }
9182
9183         pipe_config->gmch_pfit.control = tmp;
9184         pipe_config->gmch_pfit.pgm_ratios = intel_de_read(dev_priv,
9185                                                           PFIT_PGM_RATIOS);
9186 }
9187
9188 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9189                                struct intel_crtc_state *pipe_config)
9190 {
9191         struct drm_device *dev = crtc->base.dev;
9192         struct drm_i915_private *dev_priv = to_i915(dev);
9193         enum pipe pipe = crtc->pipe;
9194         struct dpll clock;
9195         u32 mdiv;
9196         int refclk = 100000;
9197
9198         /* In case of DSI, DPLL will not be used */
9199         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9200                 return;
9201
9202         vlv_dpio_get(dev_priv);
9203         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9204         vlv_dpio_put(dev_priv);
9205
9206         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9207         clock.m2 = mdiv & DPIO_M2DIV_MASK;
9208         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9209         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9210         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9211
9212         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9213 }
9214
9215 static void
9216 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9217                               struct intel_initial_plane_config *plane_config)
9218 {
9219         struct drm_device *dev = crtc->base.dev;
9220         struct drm_i915_private *dev_priv = to_i915(dev);
9221         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9222         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9223         enum pipe pipe;
9224         u32 val, base, offset;
9225         int fourcc, pixel_format;
9226         unsigned int aligned_height;
9227         struct drm_framebuffer *fb;
9228         struct intel_framebuffer *intel_fb;
9229
9230         if (!plane->get_hw_state(plane, &pipe))
9231                 return;
9232
9233         drm_WARN_ON(dev, pipe != crtc->pipe);
9234
9235         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9236         if (!intel_fb) {
9237                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9238                 return;
9239         }
9240
9241         fb = &intel_fb->base;
9242
9243         fb->dev = dev;
9244
9245         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9246
9247         if (INTEL_GEN(dev_priv) >= 4) {
9248                 if (val & DISPPLANE_TILED) {
9249                         plane_config->tiling = I915_TILING_X;
9250                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9251                 }
9252
9253                 if (val & DISPPLANE_ROTATE_180)
9254                         plane_config->rotation = DRM_MODE_ROTATE_180;
9255         }
9256
9257         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9258             val & DISPPLANE_MIRROR)
9259                 plane_config->rotation |= DRM_MODE_REFLECT_X;
9260
9261         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9262         fourcc = i9xx_format_to_fourcc(pixel_format);
9263         fb->format = drm_format_info(fourcc);
9264
9265         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9266                 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9267                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9268         } else if (INTEL_GEN(dev_priv) >= 4) {
9269                 if (plane_config->tiling)
9270                         offset = intel_de_read(dev_priv,
9271                                                DSPTILEOFF(i9xx_plane));
9272                 else
9273                         offset = intel_de_read(dev_priv,
9274                                                DSPLINOFF(i9xx_plane));
9275                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9276         } else {
9277                 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9278         }
9279         plane_config->base = base;
9280
9281         val = intel_de_read(dev_priv, PIPESRC(pipe));
9282         fb->width = ((val >> 16) & 0xfff) + 1;
9283         fb->height = ((val >> 0) & 0xfff) + 1;
9284
9285         val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9286         fb->pitches[0] = val & 0xffffffc0;
9287
9288         aligned_height = intel_fb_align_height(fb, 0, fb->height);
9289
9290         plane_config->size = fb->pitches[0] * aligned_height;
9291
9292         drm_dbg_kms(&dev_priv->drm,
9293                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9294                     crtc->base.name, plane->base.name, fb->width, fb->height,
9295                     fb->format->cpp[0] * 8, base, fb->pitches[0],
9296                     plane_config->size);
9297
9298         plane_config->fb = intel_fb;
9299 }
9300
9301 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9302                                struct intel_crtc_state *pipe_config)
9303 {
9304         struct drm_device *dev = crtc->base.dev;
9305         struct drm_i915_private *dev_priv = to_i915(dev);
9306         enum pipe pipe = crtc->pipe;
9307         enum dpio_channel port = vlv_pipe_to_channel(pipe);
9308         struct dpll clock;
9309         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9310         int refclk = 100000;
9311
9312         /* In case of DSI, DPLL will not be used */
9313         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9314                 return;
9315
9316         vlv_dpio_get(dev_priv);
9317         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9318         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9319         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9320         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9321         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9322         vlv_dpio_put(dev_priv);
9323
9324         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9325         clock.m2 = (pll_dw0 & 0xff) << 22;
9326         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9327                 clock.m2 |= pll_dw2 & 0x3fffff;
9328         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9329         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9330         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9331
9332         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9333 }
9334
9335 static enum intel_output_format
9336 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9337 {
9338         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9339         u32 tmp;
9340
9341         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9342
9343         if (tmp & PIPEMISC_YUV420_ENABLE) {
9344                 /* We support 4:2:0 in full blend mode only */
9345                 drm_WARN_ON(&dev_priv->drm,
9346                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9347
9348                 return INTEL_OUTPUT_FORMAT_YCBCR420;
9349         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9350                 return INTEL_OUTPUT_FORMAT_YCBCR444;
9351         } else {
9352                 return INTEL_OUTPUT_FORMAT_RGB;
9353         }
9354 }
9355
9356 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9357 {
9358         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9359         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9360         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9361         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9362         u32 tmp;
9363
9364         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9365
9366         if (tmp & DISPPLANE_GAMMA_ENABLE)
9367                 crtc_state->gamma_enable = true;
9368
9369         if (!HAS_GMCH(dev_priv) &&
9370             tmp & DISPPLANE_PIPE_CSC_ENABLE)
9371                 crtc_state->csc_enable = true;
9372 }
9373
9374 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9375                                  struct intel_crtc_state *pipe_config)
9376 {
9377         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9378         enum intel_display_power_domain power_domain;
9379         intel_wakeref_t wakeref;
9380         u32 tmp;
9381         bool ret;
9382
9383         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9384         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9385         if (!wakeref)
9386                 return false;
9387
9388         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9389         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9390         pipe_config->shared_dpll = NULL;
9391
9392         ret = false;
9393
9394         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9395         if (!(tmp & PIPECONF_ENABLE))
9396                 goto out;
9397
9398         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9399             IS_CHERRYVIEW(dev_priv)) {
9400                 switch (tmp & PIPECONF_BPC_MASK) {
9401                 case PIPECONF_6BPC:
9402                         pipe_config->pipe_bpp = 18;
9403                         break;
9404                 case PIPECONF_8BPC:
9405                         pipe_config->pipe_bpp = 24;
9406                         break;
9407                 case PIPECONF_10BPC:
9408                         pipe_config->pipe_bpp = 30;
9409                         break;
9410                 default:
9411                         break;
9412                 }
9413         }
9414
9415         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9416             (tmp & PIPECONF_COLOR_RANGE_SELECT))
9417                 pipe_config->limited_color_range = true;
9418
9419         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9420                 PIPECONF_GAMMA_MODE_SHIFT;
9421
9422         if (IS_CHERRYVIEW(dev_priv))
9423                 pipe_config->cgm_mode = intel_de_read(dev_priv,
9424                                                       CGM_PIPE_MODE(crtc->pipe));
9425
9426         i9xx_get_pipe_color_config(pipe_config);
9427         intel_color_get_config(pipe_config);
9428
9429         if (INTEL_GEN(dev_priv) < 4)
9430                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9431
9432         intel_get_pipe_timings(crtc, pipe_config);
9433         intel_get_pipe_src_size(crtc, pipe_config);
9434
9435         i9xx_get_pfit_config(crtc, pipe_config);
9436
9437         if (INTEL_GEN(dev_priv) >= 4) {
9438                 /* No way to read it out on pipes B and C */
9439                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9440                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
9441                 else
9442                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9443                 pipe_config->pixel_multiplier =
9444                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9445                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9446                 pipe_config->dpll_hw_state.dpll_md = tmp;
9447         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9448                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9449                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9450                 pipe_config->pixel_multiplier =
9451                         ((tmp & SDVO_MULTIPLIER_MASK)
9452                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9453         } else {
9454                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9455                  * port and will be fixed up in the encoder->get_config
9456                  * function. */
9457                 pipe_config->pixel_multiplier = 1;
9458         }
9459         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9460                                                         DPLL(crtc->pipe));
9461         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9462                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9463                                                                FP0(crtc->pipe));
9464                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9465                                                                FP1(crtc->pipe));
9466         } else {
9467                 /* Mask out read-only status bits. */
9468                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9469                                                      DPLL_PORTC_READY_MASK |
9470                                                      DPLL_PORTB_READY_MASK);
9471         }
9472
9473         if (IS_CHERRYVIEW(dev_priv))
9474                 chv_crtc_clock_get(crtc, pipe_config);
9475         else if (IS_VALLEYVIEW(dev_priv))
9476                 vlv_crtc_clock_get(crtc, pipe_config);
9477         else
9478                 i9xx_crtc_clock_get(crtc, pipe_config);
9479
9480         /*
9481          * Normally the dotclock is filled in by the encoder .get_config()
9482          * but in case the pipe is enabled w/o any ports we need a sane
9483          * default.
9484          */
9485         pipe_config->hw.adjusted_mode.crtc_clock =
9486                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9487
9488         ret = true;
9489
9490 out:
9491         intel_display_power_put(dev_priv, power_domain, wakeref);
9492
9493         return ret;
9494 }
9495
9496 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9497 {
9498         struct intel_encoder *encoder;
9499         int i;
9500         u32 val, final;
9501         bool has_lvds = false;
9502         bool has_cpu_edp = false;
9503         bool has_panel = false;
9504         bool has_ck505 = false;
9505         bool can_ssc = false;
9506         bool using_ssc_source = false;
9507
9508         /* We need to take the global config into account */
9509         for_each_intel_encoder(&dev_priv->drm, encoder) {
9510                 switch (encoder->type) {
9511                 case INTEL_OUTPUT_LVDS:
9512                         has_panel = true;
9513                         has_lvds = true;
9514                         break;
9515                 case INTEL_OUTPUT_EDP:
9516                         has_panel = true;
9517                         if (encoder->port == PORT_A)
9518                                 has_cpu_edp = true;
9519                         break;
9520                 default:
9521                         break;
9522                 }
9523         }
9524
9525         if (HAS_PCH_IBX(dev_priv)) {
9526                 has_ck505 = dev_priv->vbt.display_clock_mode;
9527                 can_ssc = has_ck505;
9528         } else {
9529                 has_ck505 = false;
9530                 can_ssc = true;
9531         }
9532
9533         /* Check if any DPLLs are using the SSC source */
9534         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9535                 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9536
9537                 if (!(temp & DPLL_VCO_ENABLE))
9538                         continue;
9539
9540                 if ((temp & PLL_REF_INPUT_MASK) ==
9541                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9542                         using_ssc_source = true;
9543                         break;
9544                 }
9545         }
9546
9547         drm_dbg_kms(&dev_priv->drm,
9548                     "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9549                     has_panel, has_lvds, has_ck505, using_ssc_source);
9550
9551         /* Ironlake: try to setup display ref clock before DPLL
9552          * enabling. This is only under driver's control after
9553          * PCH B stepping, previous chipset stepping should be
9554          * ignoring this setting.
9555          */
9556         val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9557
9558         /* As we must carefully and slowly disable/enable each source in turn,
9559          * compute the final state we want first and check if we need to
9560          * make any changes at all.
9561          */
9562         final = val;
9563         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9564         if (has_ck505)
9565                 final |= DREF_NONSPREAD_CK505_ENABLE;
9566         else
9567                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9568
9569         final &= ~DREF_SSC_SOURCE_MASK;
9570         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9571         final &= ~DREF_SSC1_ENABLE;
9572
9573         if (has_panel) {
9574                 final |= DREF_SSC_SOURCE_ENABLE;
9575
9576                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9577                         final |= DREF_SSC1_ENABLE;
9578
9579                 if (has_cpu_edp) {
9580                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9581                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9582                         else
9583                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9584                 } else
9585                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9586         } else if (using_ssc_source) {
9587                 final |= DREF_SSC_SOURCE_ENABLE;
9588                 final |= DREF_SSC1_ENABLE;
9589         }
9590
9591         if (final == val)
9592                 return;
9593
9594         /* Always enable nonspread source */
9595         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9596
9597         if (has_ck505)
9598                 val |= DREF_NONSPREAD_CK505_ENABLE;
9599         else
9600                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9601
9602         if (has_panel) {
9603                 val &= ~DREF_SSC_SOURCE_MASK;
9604                 val |= DREF_SSC_SOURCE_ENABLE;
9605
9606                 /* SSC must be turned on before enabling the CPU output  */
9607                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9608                         drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9609                         val |= DREF_SSC1_ENABLE;
9610                 } else
9611                         val &= ~DREF_SSC1_ENABLE;
9612
9613                 /* Get SSC going before enabling the outputs */
9614                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9615                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9616                 udelay(200);
9617
9618                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9619
9620                 /* Enable CPU source on CPU attached eDP */
9621                 if (has_cpu_edp) {
9622                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9623                                 drm_dbg_kms(&dev_priv->drm,
9624                                             "Using SSC on eDP\n");
9625                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9626                         } else
9627                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9628                 } else
9629                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9630
9631                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9632                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9633                 udelay(200);
9634         } else {
9635                 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9636
9637                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9638
9639                 /* Turn off CPU output */
9640                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9641
9642                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9643                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9644                 udelay(200);
9645
9646                 if (!using_ssc_source) {
9647                         drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9648
9649                         /* Turn off the SSC source */
9650                         val &= ~DREF_SSC_SOURCE_MASK;
9651                         val |= DREF_SSC_SOURCE_DISABLE;
9652
9653                         /* Turn off SSC1 */
9654                         val &= ~DREF_SSC1_ENABLE;
9655
9656                         intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9657                         intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9658                         udelay(200);
9659                 }
9660         }
9661
9662         BUG_ON(val != final);
9663 }
9664
9665 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9666 {
9667         u32 tmp;
9668
9669         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9670         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9671         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9672
9673         if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9674                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9675                 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9676
9677         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9678         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9679         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9680
9681         if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9682                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9683                 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9684 }
9685
9686 /* WaMPhyProgramming:hsw */
9687 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9688 {
9689         u32 tmp;
9690
9691         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9692         tmp &= ~(0xFF << 24);
9693         tmp |= (0x12 << 24);
9694         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9695
9696         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9697         tmp |= (1 << 11);
9698         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9699
9700         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9701         tmp |= (1 << 11);
9702         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9703
9704         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9705         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9706         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9707
9708         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9709         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9710         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9711
9712         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9713         tmp &= ~(7 << 13);
9714         tmp |= (5 << 13);
9715         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9716
9717         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9718         tmp &= ~(7 << 13);
9719         tmp |= (5 << 13);
9720         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9721
9722         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9723         tmp &= ~0xFF;
9724         tmp |= 0x1C;
9725         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9726
9727         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9728         tmp &= ~0xFF;
9729         tmp |= 0x1C;
9730         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9731
9732         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9733         tmp &= ~(0xFF << 16);
9734         tmp |= (0x1C << 16);
9735         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9736
9737         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9738         tmp &= ~(0xFF << 16);
9739         tmp |= (0x1C << 16);
9740         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9741
9742         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9743         tmp |= (1 << 27);
9744         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9745
9746         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9747         tmp |= (1 << 27);
9748         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9749
9750         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9751         tmp &= ~(0xF << 28);
9752         tmp |= (4 << 28);
9753         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9754
9755         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9756         tmp &= ~(0xF << 28);
9757         tmp |= (4 << 28);
9758         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9759 }
9760
9761 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9762  * Programming" based on the parameters passed:
9763  * - Sequence to enable CLKOUT_DP
9764  * - Sequence to enable CLKOUT_DP without spread
9765  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9766  */
9767 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9768                                  bool with_spread, bool with_fdi)
9769 {
9770         u32 reg, tmp;
9771
9772         if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9773                      "FDI requires downspread\n"))
9774                 with_spread = true;
9775         if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9776                      with_fdi, "LP PCH doesn't have FDI\n"))
9777                 with_fdi = false;
9778
9779         mutex_lock(&dev_priv->sb_lock);
9780
9781         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9782         tmp &= ~SBI_SSCCTL_DISABLE;
9783         tmp |= SBI_SSCCTL_PATHALT;
9784         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9785
9786         udelay(24);
9787
9788         if (with_spread) {
9789                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9790                 tmp &= ~SBI_SSCCTL_PATHALT;
9791                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9792
9793                 if (with_fdi) {
9794                         lpt_reset_fdi_mphy(dev_priv);
9795                         lpt_program_fdi_mphy(dev_priv);
9796                 }
9797         }
9798
9799         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9800         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9801         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9802         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9803
9804         mutex_unlock(&dev_priv->sb_lock);
9805 }
9806
9807 /* Sequence to disable CLKOUT_DP */
9808 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9809 {
9810         u32 reg, tmp;
9811
9812         mutex_lock(&dev_priv->sb_lock);
9813
9814         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9815         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9816         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9817         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9818
9819         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9820         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9821                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9822                         tmp |= SBI_SSCCTL_PATHALT;
9823                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9824                         udelay(32);
9825                 }
9826                 tmp |= SBI_SSCCTL_DISABLE;
9827                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9828         }
9829
9830         mutex_unlock(&dev_priv->sb_lock);
9831 }
9832
9833 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9834
9835 static const u16 sscdivintphase[] = {
9836         [BEND_IDX( 50)] = 0x3B23,
9837         [BEND_IDX( 45)] = 0x3B23,
9838         [BEND_IDX( 40)] = 0x3C23,
9839         [BEND_IDX( 35)] = 0x3C23,
9840         [BEND_IDX( 30)] = 0x3D23,
9841         [BEND_IDX( 25)] = 0x3D23,
9842         [BEND_IDX( 20)] = 0x3E23,
9843         [BEND_IDX( 15)] = 0x3E23,
9844         [BEND_IDX( 10)] = 0x3F23,
9845         [BEND_IDX(  5)] = 0x3F23,
9846         [BEND_IDX(  0)] = 0x0025,
9847         [BEND_IDX( -5)] = 0x0025,
9848         [BEND_IDX(-10)] = 0x0125,
9849         [BEND_IDX(-15)] = 0x0125,
9850         [BEND_IDX(-20)] = 0x0225,
9851         [BEND_IDX(-25)] = 0x0225,
9852         [BEND_IDX(-30)] = 0x0325,
9853         [BEND_IDX(-35)] = 0x0325,
9854         [BEND_IDX(-40)] = 0x0425,
9855         [BEND_IDX(-45)] = 0x0425,
9856         [BEND_IDX(-50)] = 0x0525,
9857 };
9858
9859 /*
9860  * Bend CLKOUT_DP
9861  * steps -50 to 50 inclusive, in steps of 5
9862  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9863  * change in clock period = -(steps / 10) * 5.787 ps
9864  */
9865 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9866 {
9867         u32 tmp;
9868         int idx = BEND_IDX(steps);
9869
9870         if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
9871                 return;
9872
9873         if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
9874                 return;
9875
9876         mutex_lock(&dev_priv->sb_lock);
9877
9878         if (steps % 10 != 0)
9879                 tmp = 0xAAAAAAAB;
9880         else
9881                 tmp = 0x00000000;
9882         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9883
9884         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9885         tmp &= 0xffff0000;
9886         tmp |= sscdivintphase[idx];
9887         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9888
9889         mutex_unlock(&dev_priv->sb_lock);
9890 }
9891
9892 #undef BEND_IDX
9893
9894 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9895 {
9896         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9897         u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
9898
9899         if ((ctl & SPLL_PLL_ENABLE) == 0)
9900                 return false;
9901
9902         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9903             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9904                 return true;
9905
9906         if (IS_BROADWELL(dev_priv) &&
9907             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9908                 return true;
9909
9910         return false;
9911 }
9912
9913 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9914                                enum intel_dpll_id id)
9915 {
9916         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9917         u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
9918
9919         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9920                 return false;
9921
9922         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9923                 return true;
9924
9925         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9926             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9927             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9928                 return true;
9929
9930         return false;
9931 }
9932
9933 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9934 {
9935         struct intel_encoder *encoder;
9936         bool has_fdi = false;
9937
9938         for_each_intel_encoder(&dev_priv->drm, encoder) {
9939                 switch (encoder->type) {
9940                 case INTEL_OUTPUT_ANALOG:
9941                         has_fdi = true;
9942                         break;
9943                 default:
9944                         break;
9945                 }
9946         }
9947
9948         /*
9949          * The BIOS may have decided to use the PCH SSC
9950          * reference so we must not disable it until the
9951          * relevant PLLs have stopped relying on it. We'll
9952          * just leave the PCH SSC reference enabled in case
9953          * any active PLL is using it. It will get disabled
9954          * after runtime suspend if we don't have FDI.
9955          *
9956          * TODO: Move the whole reference clock handling
9957          * to the modeset sequence proper so that we can
9958          * actually enable/disable/reconfigure these things
9959          * safely. To do that we need to introduce a real
9960          * clock hierarchy. That would also allow us to do
9961          * clock bending finally.
9962          */
9963         dev_priv->pch_ssc_use = 0;
9964
9965         if (spll_uses_pch_ssc(dev_priv)) {
9966                 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
9967                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9968         }
9969
9970         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9971                 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
9972                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9973         }
9974
9975         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9976                 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
9977                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9978         }
9979
9980         if (dev_priv->pch_ssc_use)
9981                 return;
9982
9983         if (has_fdi) {
9984                 lpt_bend_clkout_dp(dev_priv, 0);
9985                 lpt_enable_clkout_dp(dev_priv, true, true);
9986         } else {
9987                 lpt_disable_clkout_dp(dev_priv);
9988         }
9989 }
9990
9991 /*
9992  * Initialize reference clocks when the driver loads
9993  */
9994 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9995 {
9996         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9997                 ilk_init_pch_refclk(dev_priv);
9998         else if (HAS_PCH_LPT(dev_priv))
9999                 lpt_init_pch_refclk(dev_priv);
10000 }
10001
10002 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10003 {
10004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10005         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10006         enum pipe pipe = crtc->pipe;
10007         u32 val;
10008
10009         val = 0;
10010
10011         switch (crtc_state->pipe_bpp) {
10012         case 18:
10013                 val |= PIPECONF_6BPC;
10014                 break;
10015         case 24:
10016                 val |= PIPECONF_8BPC;
10017                 break;
10018         case 30:
10019                 val |= PIPECONF_10BPC;
10020                 break;
10021         case 36:
10022                 val |= PIPECONF_12BPC;
10023                 break;
10024         default:
10025                 /* Case prevented by intel_choose_pipe_bpp_dither. */
10026                 BUG();
10027         }
10028
10029         if (crtc_state->dither)
10030                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10031
10032         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10033                 val |= PIPECONF_INTERLACED_ILK;
10034         else
10035                 val |= PIPECONF_PROGRESSIVE;
10036
10037         /*
10038          * This would end up with an odd purple hue over
10039          * the entire display. Make sure we don't do it.
10040          */
10041         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10042                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10043
10044         if (crtc_state->limited_color_range)
10045                 val |= PIPECONF_COLOR_RANGE_SELECT;
10046
10047         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10048                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10049
10050         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10051
10052         val |= PIPECONF_FRAME_START_DELAY(0);
10053
10054         intel_de_write(dev_priv, PIPECONF(pipe), val);
10055         intel_de_posting_read(dev_priv, PIPECONF(pipe));
10056 }
10057
10058 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10059 {
10060         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10061         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10062         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10063         u32 val = 0;
10064
10065         if (IS_HASWELL(dev_priv) && crtc_state->dither)
10066                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10067
10068         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10069                 val |= PIPECONF_INTERLACED_ILK;
10070         else
10071                 val |= PIPECONF_PROGRESSIVE;
10072
10073         if (IS_HASWELL(dev_priv) &&
10074             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10075                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10076
10077         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10078         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10079 }
10080
10081 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10082 {
10083         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10084         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10085         u32 val = 0;
10086
10087         switch (crtc_state->pipe_bpp) {
10088         case 18:
10089                 val |= PIPEMISC_DITHER_6_BPC;
10090                 break;
10091         case 24:
10092                 val |= PIPEMISC_DITHER_8_BPC;
10093                 break;
10094         case 30:
10095                 val |= PIPEMISC_DITHER_10_BPC;
10096                 break;
10097         case 36:
10098                 val |= PIPEMISC_DITHER_12_BPC;
10099                 break;
10100         default:
10101                 MISSING_CASE(crtc_state->pipe_bpp);
10102                 break;
10103         }
10104
10105         if (crtc_state->dither)
10106                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10107
10108         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10109             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10110                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10111
10112         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10113                 val |= PIPEMISC_YUV420_ENABLE |
10114                         PIPEMISC_YUV420_MODE_FULL_BLEND;
10115
10116         if (INTEL_GEN(dev_priv) >= 11 &&
10117             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10118                                            BIT(PLANE_CURSOR))) == 0)
10119                 val |= PIPEMISC_HDR_MODE_PRECISION;
10120
10121         if (INTEL_GEN(dev_priv) >= 12)
10122                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10123
10124         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10125 }
10126
10127 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10128 {
10129         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10130         u32 tmp;
10131
10132         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10133
10134         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10135         case PIPEMISC_DITHER_6_BPC:
10136                 return 18;
10137         case PIPEMISC_DITHER_8_BPC:
10138                 return 24;
10139         case PIPEMISC_DITHER_10_BPC:
10140                 return 30;
10141         case PIPEMISC_DITHER_12_BPC:
10142                 return 36;
10143         default:
10144                 MISSING_CASE(tmp);
10145                 return 0;
10146         }
10147 }
10148
10149 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10150 {
10151         /*
10152          * Account for spread spectrum to avoid
10153          * oversubscribing the link. Max center spread
10154          * is 2.5%; use 5% for safety's sake.
10155          */
10156         u32 bps = target_clock * bpp * 21 / 20;
10157         return DIV_ROUND_UP(bps, link_bw * 8);
10158 }
10159
10160 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10161 {
10162         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10163 }
10164
10165 static void ilk_compute_dpll(struct intel_crtc *crtc,
10166                              struct intel_crtc_state *crtc_state,
10167                              struct dpll *reduced_clock)
10168 {
10169         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10170         u32 dpll, fp, fp2;
10171         int factor;
10172
10173         /* Enable autotuning of the PLL clock (if permissible) */
10174         factor = 21;
10175         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10176                 if ((intel_panel_use_ssc(dev_priv) &&
10177                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
10178                     (HAS_PCH_IBX(dev_priv) &&
10179                      intel_is_dual_link_lvds(dev_priv)))
10180                         factor = 25;
10181         } else if (crtc_state->sdvo_tv_clock) {
10182                 factor = 20;
10183         }
10184
10185         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10186
10187         if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10188                 fp |= FP_CB_TUNE;
10189
10190         if (reduced_clock) {
10191                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10192
10193                 if (reduced_clock->m < factor * reduced_clock->n)
10194                         fp2 |= FP_CB_TUNE;
10195         } else {
10196                 fp2 = fp;
10197         }
10198
10199         dpll = 0;
10200
10201         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10202                 dpll |= DPLLB_MODE_LVDS;
10203         else
10204                 dpll |= DPLLB_MODE_DAC_SERIAL;
10205
10206         dpll |= (crtc_state->pixel_multiplier - 1)
10207                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10208
10209         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10210             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10211                 dpll |= DPLL_SDVO_HIGH_SPEED;
10212
10213         if (intel_crtc_has_dp_encoder(crtc_state))
10214                 dpll |= DPLL_SDVO_HIGH_SPEED;
10215
10216         /*
10217          * The high speed IO clock is only really required for
10218          * SDVO/HDMI/DP, but we also enable it for CRT to make it
10219          * possible to share the DPLL between CRT and HDMI. Enabling
10220          * the clock needlessly does no real harm, except use up a
10221          * bit of power potentially.
10222          *
10223          * We'll limit this to IVB with 3 pipes, since it has only two
10224          * DPLLs and so DPLL sharing is the only way to get three pipes
10225          * driving PCH ports at the same time. On SNB we could do this,
10226          * and potentially avoid enabling the second DPLL, but it's not
10227          * clear if it''s a win or loss power wise. No point in doing
10228          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10229          */
10230         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10231             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10232                 dpll |= DPLL_SDVO_HIGH_SPEED;
10233
10234         /* compute bitmask from p1 value */
10235         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10236         /* also FPA1 */
10237         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10238
10239         switch (crtc_state->dpll.p2) {
10240         case 5:
10241                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10242                 break;
10243         case 7:
10244                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10245                 break;
10246         case 10:
10247                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10248                 break;
10249         case 14:
10250                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10251                 break;
10252         }
10253
10254         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10255             intel_panel_use_ssc(dev_priv))
10256                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10257         else
10258                 dpll |= PLL_REF_INPUT_DREFCLK;
10259
10260         dpll |= DPLL_VCO_ENABLE;
10261
10262         crtc_state->dpll_hw_state.dpll = dpll;
10263         crtc_state->dpll_hw_state.fp0 = fp;
10264         crtc_state->dpll_hw_state.fp1 = fp2;
10265 }
10266
10267 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10268                                   struct intel_crtc_state *crtc_state)
10269 {
10270         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10271         struct intel_atomic_state *state =
10272                 to_intel_atomic_state(crtc_state->uapi.state);
10273         const struct intel_limit *limit;
10274         int refclk = 120000;
10275
10276         memset(&crtc_state->dpll_hw_state, 0,
10277                sizeof(crtc_state->dpll_hw_state));
10278
10279         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10280         if (!crtc_state->has_pch_encoder)
10281                 return 0;
10282
10283         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10284                 if (intel_panel_use_ssc(dev_priv)) {
10285                         drm_dbg_kms(&dev_priv->drm,
10286                                     "using SSC reference clock of %d kHz\n",
10287                                     dev_priv->vbt.lvds_ssc_freq);
10288                         refclk = dev_priv->vbt.lvds_ssc_freq;
10289                 }
10290
10291                 if (intel_is_dual_link_lvds(dev_priv)) {
10292                         if (refclk == 100000)
10293                                 limit = &ilk_limits_dual_lvds_100m;
10294                         else
10295                                 limit = &ilk_limits_dual_lvds;
10296                 } else {
10297                         if (refclk == 100000)
10298                                 limit = &ilk_limits_single_lvds_100m;
10299                         else
10300                                 limit = &ilk_limits_single_lvds;
10301                 }
10302         } else {
10303                 limit = &ilk_limits_dac;
10304         }
10305
10306         if (!crtc_state->clock_set &&
10307             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10308                                 refclk, NULL, &crtc_state->dpll)) {
10309                 drm_err(&dev_priv->drm,
10310                         "Couldn't find PLL settings for mode!\n");
10311                 return -EINVAL;
10312         }
10313
10314         ilk_compute_dpll(crtc, crtc_state, NULL);
10315
10316         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10317                 drm_dbg_kms(&dev_priv->drm,
10318                             "failed to find PLL for pipe %c\n",
10319                             pipe_name(crtc->pipe));
10320                 return -EINVAL;
10321         }
10322
10323         return 0;
10324 }
10325
10326 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10327                                          struct intel_link_m_n *m_n)
10328 {
10329         struct drm_device *dev = crtc->base.dev;
10330         struct drm_i915_private *dev_priv = to_i915(dev);
10331         enum pipe pipe = crtc->pipe;
10332
10333         m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10334         m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10335         m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10336                 & ~TU_SIZE_MASK;
10337         m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10338         m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10339                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10340 }
10341
10342 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10343                                          enum transcoder transcoder,
10344                                          struct intel_link_m_n *m_n,
10345                                          struct intel_link_m_n *m2_n2)
10346 {
10347         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10348         enum pipe pipe = crtc->pipe;
10349
10350         if (INTEL_GEN(dev_priv) >= 5) {
10351                 m_n->link_m = intel_de_read(dev_priv,
10352                                             PIPE_LINK_M1(transcoder));
10353                 m_n->link_n = intel_de_read(dev_priv,
10354                                             PIPE_LINK_N1(transcoder));
10355                 m_n->gmch_m = intel_de_read(dev_priv,
10356                                             PIPE_DATA_M1(transcoder))
10357                         & ~TU_SIZE_MASK;
10358                 m_n->gmch_n = intel_de_read(dev_priv,
10359                                             PIPE_DATA_N1(transcoder));
10360                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10361                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10362
10363                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10364                         m2_n2->link_m = intel_de_read(dev_priv,
10365                                                       PIPE_LINK_M2(transcoder));
10366                         m2_n2->link_n = intel_de_read(dev_priv,
10367                                                              PIPE_LINK_N2(transcoder));
10368                         m2_n2->gmch_m = intel_de_read(dev_priv,
10369                                                              PIPE_DATA_M2(transcoder))
10370                                         & ~TU_SIZE_MASK;
10371                         m2_n2->gmch_n = intel_de_read(dev_priv,
10372                                                              PIPE_DATA_N2(transcoder));
10373                         m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10374                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10375                 }
10376         } else {
10377                 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10378                 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10379                 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10380                         & ~TU_SIZE_MASK;
10381                 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10382                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10383                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10384         }
10385 }
10386
10387 void intel_dp_get_m_n(struct intel_crtc *crtc,
10388                       struct intel_crtc_state *pipe_config)
10389 {
10390         if (pipe_config->has_pch_encoder)
10391                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10392         else
10393                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10394                                              &pipe_config->dp_m_n,
10395                                              &pipe_config->dp_m2_n2);
10396 }
10397
10398 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10399                                    struct intel_crtc_state *pipe_config)
10400 {
10401         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10402                                      &pipe_config->fdi_m_n, NULL);
10403 }
10404
10405 static void skl_get_pfit_config(struct intel_crtc *crtc,
10406                                 struct intel_crtc_state *pipe_config)
10407 {
10408         struct drm_device *dev = crtc->base.dev;
10409         struct drm_i915_private *dev_priv = to_i915(dev);
10410         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
10411         u32 ps_ctrl = 0;
10412         int id = -1;
10413         int i;
10414
10415         /* find scaler attached to this pipe */
10416         for (i = 0; i < crtc->num_scalers; i++) {
10417                 ps_ctrl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10418                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
10419                         id = i;
10420                         pipe_config->pch_pfit.enabled = true;
10421                         pipe_config->pch_pfit.pos = intel_de_read(dev_priv,
10422                                                                   SKL_PS_WIN_POS(crtc->pipe, i));
10423                         pipe_config->pch_pfit.size = intel_de_read(dev_priv,
10424                                                                    SKL_PS_WIN_SZ(crtc->pipe, i));
10425                         scaler_state->scalers[i].in_use = true;
10426                         break;
10427                 }
10428         }
10429
10430         scaler_state->scaler_id = id;
10431         if (id >= 0) {
10432                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10433         } else {
10434                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10435         }
10436 }
10437
10438 static void
10439 skl_get_initial_plane_config(struct intel_crtc *crtc,
10440                              struct intel_initial_plane_config *plane_config)
10441 {
10442         struct drm_device *dev = crtc->base.dev;
10443         struct drm_i915_private *dev_priv = to_i915(dev);
10444         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10445         enum plane_id plane_id = plane->id;
10446         enum pipe pipe;
10447         u32 val, base, offset, stride_mult, tiling, alpha;
10448         int fourcc, pixel_format;
10449         unsigned int aligned_height;
10450         struct drm_framebuffer *fb;
10451         struct intel_framebuffer *intel_fb;
10452
10453         if (!plane->get_hw_state(plane, &pipe))
10454                 return;
10455
10456         drm_WARN_ON(dev, pipe != crtc->pipe);
10457
10458         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10459         if (!intel_fb) {
10460                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10461                 return;
10462         }
10463
10464         fb = &intel_fb->base;
10465
10466         fb->dev = dev;
10467
10468         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10469
10470         if (INTEL_GEN(dev_priv) >= 11)
10471                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10472         else
10473                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10474
10475         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10476                 alpha = intel_de_read(dev_priv,
10477                                       PLANE_COLOR_CTL(pipe, plane_id));
10478                 alpha &= PLANE_COLOR_ALPHA_MASK;
10479         } else {
10480                 alpha = val & PLANE_CTL_ALPHA_MASK;
10481         }
10482
10483         fourcc = skl_format_to_fourcc(pixel_format,
10484                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10485         fb->format = drm_format_info(fourcc);
10486
10487         tiling = val & PLANE_CTL_TILED_MASK;
10488         switch (tiling) {
10489         case PLANE_CTL_TILED_LINEAR:
10490                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10491                 break;
10492         case PLANE_CTL_TILED_X:
10493                 plane_config->tiling = I915_TILING_X;
10494                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10495                 break;
10496         case PLANE_CTL_TILED_Y:
10497                 plane_config->tiling = I915_TILING_Y;
10498                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10499                         fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10500                                 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10501                                 I915_FORMAT_MOD_Y_TILED_CCS;
10502                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10503                         fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10504                 else
10505                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10506                 break;
10507         case PLANE_CTL_TILED_YF:
10508                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10509                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10510                 else
10511                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10512                 break;
10513         default:
10514                 MISSING_CASE(tiling);
10515                 goto error;
10516         }
10517
10518         /*
10519          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10520          * while i915 HW rotation is clockwise, thats why this swapping.
10521          */
10522         switch (val & PLANE_CTL_ROTATE_MASK) {
10523         case PLANE_CTL_ROTATE_0:
10524                 plane_config->rotation = DRM_MODE_ROTATE_0;
10525                 break;
10526         case PLANE_CTL_ROTATE_90:
10527                 plane_config->rotation = DRM_MODE_ROTATE_270;
10528                 break;
10529         case PLANE_CTL_ROTATE_180:
10530                 plane_config->rotation = DRM_MODE_ROTATE_180;
10531                 break;
10532         case PLANE_CTL_ROTATE_270:
10533                 plane_config->rotation = DRM_MODE_ROTATE_90;
10534                 break;
10535         }
10536
10537         if (INTEL_GEN(dev_priv) >= 10 &&
10538             val & PLANE_CTL_FLIP_HORIZONTAL)
10539                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10540
10541         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10542         plane_config->base = base;
10543
10544         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10545
10546         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10547         fb->height = ((val >> 16) & 0xffff) + 1;
10548         fb->width = ((val >> 0) & 0xffff) + 1;
10549
10550         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10551         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10552         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10553
10554         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10555
10556         plane_config->size = fb->pitches[0] * aligned_height;
10557
10558         drm_dbg_kms(&dev_priv->drm,
10559                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10560                     crtc->base.name, plane->base.name, fb->width, fb->height,
10561                     fb->format->cpp[0] * 8, base, fb->pitches[0],
10562                     plane_config->size);
10563
10564         plane_config->fb = intel_fb;
10565         return;
10566
10567 error:
10568         kfree(intel_fb);
10569 }
10570
10571 static void ilk_get_pfit_config(struct intel_crtc *crtc,
10572                                 struct intel_crtc_state *pipe_config)
10573 {
10574         struct drm_device *dev = crtc->base.dev;
10575         struct drm_i915_private *dev_priv = to_i915(dev);
10576         u32 tmp;
10577
10578         tmp = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10579
10580         if (tmp & PF_ENABLE) {
10581                 pipe_config->pch_pfit.enabled = true;
10582                 pipe_config->pch_pfit.pos = intel_de_read(dev_priv,
10583                                                           PF_WIN_POS(crtc->pipe));
10584                 pipe_config->pch_pfit.size = intel_de_read(dev_priv,
10585                                                            PF_WIN_SZ(crtc->pipe));
10586
10587                 /* We currently do not free assignements of panel fitters on
10588                  * ivb/hsw (since we don't use the higher upscaling modes which
10589                  * differentiates them) so just WARN about this case for now. */
10590                 if (IS_GEN(dev_priv, 7)) {
10591                         drm_WARN_ON(dev, (tmp & PF_PIPE_SEL_MASK_IVB) !=
10592                                     PF_PIPE_SEL_IVB(crtc->pipe));
10593                 }
10594         }
10595 }
10596
10597 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10598                                 struct intel_crtc_state *pipe_config)
10599 {
10600         struct drm_device *dev = crtc->base.dev;
10601         struct drm_i915_private *dev_priv = to_i915(dev);
10602         enum intel_display_power_domain power_domain;
10603         intel_wakeref_t wakeref;
10604         u32 tmp;
10605         bool ret;
10606
10607         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10608         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10609         if (!wakeref)
10610                 return false;
10611
10612         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10613         pipe_config->shared_dpll = NULL;
10614
10615         ret = false;
10616         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10617         if (!(tmp & PIPECONF_ENABLE))
10618                 goto out;
10619
10620         switch (tmp & PIPECONF_BPC_MASK) {
10621         case PIPECONF_6BPC:
10622                 pipe_config->pipe_bpp = 18;
10623                 break;
10624         case PIPECONF_8BPC:
10625                 pipe_config->pipe_bpp = 24;
10626                 break;
10627         case PIPECONF_10BPC:
10628                 pipe_config->pipe_bpp = 30;
10629                 break;
10630         case PIPECONF_12BPC:
10631                 pipe_config->pipe_bpp = 36;
10632                 break;
10633         default:
10634                 break;
10635         }
10636
10637         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10638                 pipe_config->limited_color_range = true;
10639
10640         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10641         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10642         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10643                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10644                 break;
10645         default:
10646                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10647                 break;
10648         }
10649
10650         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10651                 PIPECONF_GAMMA_MODE_SHIFT;
10652
10653         pipe_config->csc_mode = intel_de_read(dev_priv,
10654                                               PIPE_CSC_MODE(crtc->pipe));
10655
10656         i9xx_get_pipe_color_config(pipe_config);
10657         intel_color_get_config(pipe_config);
10658
10659         if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10660                 struct intel_shared_dpll *pll;
10661                 enum intel_dpll_id pll_id;
10662
10663                 pipe_config->has_pch_encoder = true;
10664
10665                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10666                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10667                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10668
10669                 ilk_get_fdi_m_n_config(crtc, pipe_config);
10670
10671                 if (HAS_PCH_IBX(dev_priv)) {
10672                         /*
10673                          * The pipe->pch transcoder and pch transcoder->pll
10674                          * mapping is fixed.
10675                          */
10676                         pll_id = (enum intel_dpll_id) crtc->pipe;
10677                 } else {
10678                         tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10679                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10680                                 pll_id = DPLL_ID_PCH_PLL_B;
10681                         else
10682                                 pll_id= DPLL_ID_PCH_PLL_A;
10683                 }
10684
10685                 pipe_config->shared_dpll =
10686                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10687                 pll = pipe_config->shared_dpll;
10688
10689                 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10690                                                  &pipe_config->dpll_hw_state));
10691
10692                 tmp = pipe_config->dpll_hw_state.dpll;
10693                 pipe_config->pixel_multiplier =
10694                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10695                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10696
10697                 ilk_pch_clock_get(crtc, pipe_config);
10698         } else {
10699                 pipe_config->pixel_multiplier = 1;
10700         }
10701
10702         intel_get_pipe_timings(crtc, pipe_config);
10703         intel_get_pipe_src_size(crtc, pipe_config);
10704
10705         ilk_get_pfit_config(crtc, pipe_config);
10706
10707         ret = true;
10708
10709 out:
10710         intel_display_power_put(dev_priv, power_domain, wakeref);
10711
10712         return ret;
10713 }
10714
10715 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10716                                   struct intel_crtc_state *crtc_state)
10717 {
10718         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10719         struct intel_atomic_state *state =
10720                 to_intel_atomic_state(crtc_state->uapi.state);
10721
10722         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10723             INTEL_GEN(dev_priv) >= 11) {
10724                 struct intel_encoder *encoder =
10725                         intel_get_crtc_new_encoder(state, crtc_state);
10726
10727                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10728                         drm_dbg_kms(&dev_priv->drm,
10729                                     "failed to find PLL for pipe %c\n",
10730                                     pipe_name(crtc->pipe));
10731                         return -EINVAL;
10732                 }
10733         }
10734
10735         return 0;
10736 }
10737
10738 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10739                             struct intel_crtc_state *pipe_config)
10740 {
10741         enum intel_dpll_id id;
10742         u32 temp;
10743
10744         temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10745         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10746
10747         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10748                 return;
10749
10750         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10751 }
10752
10753 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10754                             struct intel_crtc_state *pipe_config)
10755 {
10756         enum phy phy = intel_port_to_phy(dev_priv, port);
10757         enum icl_port_dpll_id port_dpll_id;
10758         enum intel_dpll_id id;
10759         u32 temp;
10760
10761         if (intel_phy_is_combo(dev_priv, phy)) {
10762                 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
10763                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10764                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10765                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10766         } else if (intel_phy_is_tc(dev_priv, phy)) {
10767                 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10768
10769                 if (clk_sel == DDI_CLK_SEL_MG) {
10770                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10771                                                                     port));
10772                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10773                 } else {
10774                         drm_WARN_ON(&dev_priv->drm,
10775                                     clk_sel < DDI_CLK_SEL_TBT_162);
10776                         id = DPLL_ID_ICL_TBTPLL;
10777                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10778                 }
10779         } else {
10780                 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10781                 return;
10782         }
10783
10784         pipe_config->icl_port_dplls[port_dpll_id].pll =
10785                 intel_get_shared_dpll_by_id(dev_priv, id);
10786
10787         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10788 }
10789
10790 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10791                                 enum port port,
10792                                 struct intel_crtc_state *pipe_config)
10793 {
10794         enum intel_dpll_id id;
10795
10796         switch (port) {
10797         case PORT_A:
10798                 id = DPLL_ID_SKL_DPLL0;
10799                 break;
10800         case PORT_B:
10801                 id = DPLL_ID_SKL_DPLL1;
10802                 break;
10803         case PORT_C:
10804                 id = DPLL_ID_SKL_DPLL2;
10805                 break;
10806         default:
10807                 drm_err(&dev_priv->drm, "Incorrect port type\n");
10808                 return;
10809         }
10810
10811         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10812 }
10813
10814 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10815                             struct intel_crtc_state *pipe_config)
10816 {
10817         enum intel_dpll_id id;
10818         u32 temp;
10819
10820         temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10821         id = temp >> (port * 3 + 1);
10822
10823         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10824                 return;
10825
10826         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10827 }
10828
10829 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10830                             struct intel_crtc_state *pipe_config)
10831 {
10832         enum intel_dpll_id id;
10833         u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
10834
10835         switch (ddi_pll_sel) {
10836         case PORT_CLK_SEL_WRPLL1:
10837                 id = DPLL_ID_WRPLL1;
10838                 break;
10839         case PORT_CLK_SEL_WRPLL2:
10840                 id = DPLL_ID_WRPLL2;
10841                 break;
10842         case PORT_CLK_SEL_SPLL:
10843                 id = DPLL_ID_SPLL;
10844                 break;
10845         case PORT_CLK_SEL_LCPLL_810:
10846                 id = DPLL_ID_LCPLL_810;
10847                 break;
10848         case PORT_CLK_SEL_LCPLL_1350:
10849                 id = DPLL_ID_LCPLL_1350;
10850                 break;
10851         case PORT_CLK_SEL_LCPLL_2700:
10852                 id = DPLL_ID_LCPLL_2700;
10853                 break;
10854         default:
10855                 MISSING_CASE(ddi_pll_sel);
10856                 /* fall through */
10857         case PORT_CLK_SEL_NONE:
10858                 return;
10859         }
10860
10861         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10862 }
10863
10864 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10865                                      struct intel_crtc_state *pipe_config,
10866                                      u64 *power_domain_mask,
10867                                      intel_wakeref_t *wakerefs)
10868 {
10869         struct drm_device *dev = crtc->base.dev;
10870         struct drm_i915_private *dev_priv = to_i915(dev);
10871         enum intel_display_power_domain power_domain;
10872         unsigned long panel_transcoder_mask = 0;
10873         unsigned long enabled_panel_transcoders = 0;
10874         enum transcoder panel_transcoder;
10875         intel_wakeref_t wf;
10876         u32 tmp;
10877
10878         if (INTEL_GEN(dev_priv) >= 11)
10879                 panel_transcoder_mask |=
10880                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10881
10882         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP))
10883                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10884
10885         /*
10886          * The pipe->transcoder mapping is fixed with the exception of the eDP
10887          * and DSI transcoders handled below.
10888          */
10889         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10890
10891         /*
10892          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10893          * consistency and less surprising code; it's in always on power).
10894          */
10895         for_each_set_bit(panel_transcoder,
10896                          &panel_transcoder_mask,
10897                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10898                 bool force_thru = false;
10899                 enum pipe trans_pipe;
10900
10901                 tmp = intel_de_read(dev_priv,
10902                                     TRANS_DDI_FUNC_CTL(panel_transcoder));
10903                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10904                         continue;
10905
10906                 /*
10907                  * Log all enabled ones, only use the first one.
10908                  *
10909                  * FIXME: This won't work for two separate DSI displays.
10910                  */
10911                 enabled_panel_transcoders |= BIT(panel_transcoder);
10912                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10913                         continue;
10914
10915                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10916                 default:
10917                         drm_WARN(dev, 1,
10918                                  "unknown pipe linked to transcoder %s\n",
10919                                  transcoder_name(panel_transcoder));
10920                         /* fall through */
10921                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10922                         force_thru = true;
10923                         /* fall through */
10924                 case TRANS_DDI_EDP_INPUT_A_ON:
10925                         trans_pipe = PIPE_A;
10926                         break;
10927                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10928                         trans_pipe = PIPE_B;
10929                         break;
10930                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10931                         trans_pipe = PIPE_C;
10932                         break;
10933                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
10934                         trans_pipe = PIPE_D;
10935                         break;
10936                 }
10937
10938                 if (trans_pipe == crtc->pipe) {
10939                         pipe_config->cpu_transcoder = panel_transcoder;
10940                         pipe_config->pch_pfit.force_thru = force_thru;
10941                 }
10942         }
10943
10944         /*
10945          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10946          */
10947         drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10948                     enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10949
10950         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10951         drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
10952
10953         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10954         if (!wf)
10955                 return false;
10956
10957         wakerefs[power_domain] = wf;
10958         *power_domain_mask |= BIT_ULL(power_domain);
10959
10960         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
10961
10962         return tmp & PIPECONF_ENABLE;
10963 }
10964
10965 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10966                                          struct intel_crtc_state *pipe_config,
10967                                          u64 *power_domain_mask,
10968                                          intel_wakeref_t *wakerefs)
10969 {
10970         struct drm_device *dev = crtc->base.dev;
10971         struct drm_i915_private *dev_priv = to_i915(dev);
10972         enum intel_display_power_domain power_domain;
10973         enum transcoder cpu_transcoder;
10974         intel_wakeref_t wf;
10975         enum port port;
10976         u32 tmp;
10977
10978         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10979                 if (port == PORT_A)
10980                         cpu_transcoder = TRANSCODER_DSI_A;
10981                 else
10982                         cpu_transcoder = TRANSCODER_DSI_C;
10983
10984                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10985                 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
10986
10987                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10988                 if (!wf)
10989                         continue;
10990
10991                 wakerefs[power_domain] = wf;
10992                 *power_domain_mask |= BIT_ULL(power_domain);
10993
10994                 /*
10995                  * The PLL needs to be enabled with a valid divider
10996                  * configuration, otherwise accessing DSI registers will hang
10997                  * the machine. See BSpec North Display Engine
10998                  * registers/MIPI[BXT]. We can break out here early, since we
10999                  * need the same DSI PLL to be enabled for both DSI ports.
11000                  */
11001                 if (!bxt_dsi_pll_is_enabled(dev_priv))
11002                         break;
11003
11004                 /* XXX: this works for video mode only */
11005                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11006                 if (!(tmp & DPI_ENABLE))
11007                         continue;
11008
11009                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11010                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11011                         continue;
11012
11013                 pipe_config->cpu_transcoder = cpu_transcoder;
11014                 break;
11015         }
11016
11017         return transcoder_is_dsi(pipe_config->cpu_transcoder);
11018 }
11019
11020 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11021                                    struct intel_crtc_state *pipe_config)
11022 {
11023         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11024         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11025         struct intel_shared_dpll *pll;
11026         enum port port;
11027         u32 tmp;
11028
11029         if (transcoder_is_dsi(cpu_transcoder)) {
11030                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11031                                                 PORT_A : PORT_B;
11032         } else {
11033                 tmp = intel_de_read(dev_priv,
11034                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
11035                 if (INTEL_GEN(dev_priv) >= 12)
11036                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11037                 else
11038                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11039         }
11040
11041         if (INTEL_GEN(dev_priv) >= 11)
11042                 icl_get_ddi_pll(dev_priv, port, pipe_config);
11043         else if (IS_CANNONLAKE(dev_priv))
11044                 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11045         else if (IS_GEN9_BC(dev_priv))
11046                 skl_get_ddi_pll(dev_priv, port, pipe_config);
11047         else if (IS_GEN9_LP(dev_priv))
11048                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11049         else
11050                 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11051
11052         pll = pipe_config->shared_dpll;
11053         if (pll) {
11054                 drm_WARN_ON(&dev_priv->drm,
11055                             !pll->info->funcs->get_hw_state(dev_priv, pll,
11056                                                 &pipe_config->dpll_hw_state));
11057         }
11058
11059         /*
11060          * Haswell has only FDI/PCH transcoder A. It is which is connected to
11061          * DDI E. So just check whether this pipe is wired to DDI E and whether
11062          * the PCH transcoder is on.
11063          */
11064         if (INTEL_GEN(dev_priv) < 9 &&
11065             (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11066                 pipe_config->has_pch_encoder = true;
11067
11068                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11069                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11070                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
11071
11072                 ilk_get_fdi_m_n_config(crtc, pipe_config);
11073         }
11074 }
11075
11076 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11077                                 struct intel_crtc_state *pipe_config)
11078 {
11079         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11080         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11081         enum intel_display_power_domain power_domain;
11082         u64 power_domain_mask;
11083         bool active;
11084         u32 tmp;
11085
11086         pipe_config->master_transcoder = INVALID_TRANSCODER;
11087
11088         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11089         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11090         if (!wf)
11091                 return false;
11092
11093         wakerefs[power_domain] = wf;
11094         power_domain_mask = BIT_ULL(power_domain);
11095
11096         pipe_config->shared_dpll = NULL;
11097
11098         active = hsw_get_transcoder_state(crtc, pipe_config,
11099                                           &power_domain_mask, wakerefs);
11100
11101         if (IS_GEN9_LP(dev_priv) &&
11102             bxt_get_dsi_transcoder_state(crtc, pipe_config,
11103                                          &power_domain_mask, wakerefs)) {
11104                 drm_WARN_ON(&dev_priv->drm, active);
11105                 active = true;
11106         }
11107
11108         if (!active)
11109                 goto out;
11110
11111         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11112             INTEL_GEN(dev_priv) >= 11) {
11113                 hsw_get_ddi_port_state(crtc, pipe_config);
11114                 intel_get_pipe_timings(crtc, pipe_config);
11115         }
11116
11117         intel_get_pipe_src_size(crtc, pipe_config);
11118
11119         if (IS_HASWELL(dev_priv)) {
11120                 u32 tmp = intel_de_read(dev_priv,
11121                                         PIPECONF(pipe_config->cpu_transcoder));
11122
11123                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11124                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11125                 else
11126                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11127         } else {
11128                 pipe_config->output_format =
11129                         bdw_get_pipemisc_output_format(crtc);
11130
11131                 /*
11132                  * Currently there is no interface defined to
11133                  * check user preference between RGB/YCBCR444
11134                  * or YCBCR420. So the only possible case for
11135                  * YCBCR444 usage is driving YCBCR420 output
11136                  * with LSPCON, when pipe is configured for
11137                  * YCBCR444 output and LSPCON takes care of
11138                  * downsampling it.
11139                  */
11140                 pipe_config->lspcon_downsampling =
11141                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
11142         }
11143
11144         pipe_config->gamma_mode = intel_de_read(dev_priv,
11145                                                 GAMMA_MODE(crtc->pipe));
11146
11147         pipe_config->csc_mode = intel_de_read(dev_priv,
11148                                               PIPE_CSC_MODE(crtc->pipe));
11149
11150         if (INTEL_GEN(dev_priv) >= 9) {
11151                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11152
11153                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11154                         pipe_config->gamma_enable = true;
11155
11156                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11157                         pipe_config->csc_enable = true;
11158         } else {
11159                 i9xx_get_pipe_color_config(pipe_config);
11160         }
11161
11162         intel_color_get_config(pipe_config);
11163
11164         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11165         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11166         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11167                 pipe_config->ips_linetime =
11168                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11169
11170         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11171         drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11172
11173         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11174         if (wf) {
11175                 wakerefs[power_domain] = wf;
11176                 power_domain_mask |= BIT_ULL(power_domain);
11177
11178                 if (INTEL_GEN(dev_priv) >= 9)
11179                         skl_get_pfit_config(crtc, pipe_config);
11180                 else
11181                         ilk_get_pfit_config(crtc, pipe_config);
11182         }
11183
11184         if (hsw_crtc_supports_ips(crtc)) {
11185                 if (IS_HASWELL(dev_priv))
11186                         pipe_config->ips_enabled = intel_de_read(dev_priv,
11187                                                                  IPS_CTL) & IPS_ENABLE;
11188                 else {
11189                         /*
11190                          * We cannot readout IPS state on broadwell, set to
11191                          * true so we can set it to a defined state on first
11192                          * commit.
11193                          */
11194                         pipe_config->ips_enabled = true;
11195                 }
11196         }
11197
11198         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11199             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11200                 pipe_config->pixel_multiplier =
11201                         intel_de_read(dev_priv,
11202                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11203         } else {
11204                 pipe_config->pixel_multiplier = 1;
11205         }
11206
11207 out:
11208         for_each_power_domain(power_domain, power_domain_mask)
11209                 intel_display_power_put(dev_priv,
11210                                         power_domain, wakerefs[power_domain]);
11211
11212         return active;
11213 }
11214
11215 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11216 {
11217         struct drm_i915_private *dev_priv =
11218                 to_i915(plane_state->uapi.plane->dev);
11219         const struct drm_framebuffer *fb = plane_state->hw.fb;
11220         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11221         u32 base;
11222
11223         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11224                 base = sg_dma_address(obj->mm.pages->sgl);
11225         else
11226                 base = intel_plane_ggtt_offset(plane_state);
11227
11228         return base + plane_state->color_plane[0].offset;
11229 }
11230
11231 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11232 {
11233         int x = plane_state->uapi.dst.x1;
11234         int y = plane_state->uapi.dst.y1;
11235         u32 pos = 0;
11236
11237         if (x < 0) {
11238                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11239                 x = -x;
11240         }
11241         pos |= x << CURSOR_X_SHIFT;
11242
11243         if (y < 0) {
11244                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11245                 y = -y;
11246         }
11247         pos |= y << CURSOR_Y_SHIFT;
11248
11249         return pos;
11250 }
11251
11252 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11253 {
11254         const struct drm_mode_config *config =
11255                 &plane_state->uapi.plane->dev->mode_config;
11256         int width = drm_rect_width(&plane_state->uapi.dst);
11257         int height = drm_rect_height(&plane_state->uapi.dst);
11258
11259         return width > 0 && width <= config->cursor_width &&
11260                 height > 0 && height <= config->cursor_height;
11261 }
11262
11263 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11264 {
11265         struct drm_i915_private *dev_priv =
11266                 to_i915(plane_state->uapi.plane->dev);
11267         unsigned int rotation = plane_state->hw.rotation;
11268         int src_x, src_y;
11269         u32 offset;
11270         int ret;
11271
11272         ret = intel_plane_compute_gtt(plane_state);
11273         if (ret)
11274                 return ret;
11275
11276         if (!plane_state->uapi.visible)
11277                 return 0;
11278
11279         src_x = plane_state->uapi.src.x1 >> 16;
11280         src_y = plane_state->uapi.src.y1 >> 16;
11281
11282         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11283         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11284                                                     plane_state, 0);
11285
11286         if (src_x != 0 || src_y != 0) {
11287                 drm_dbg_kms(&dev_priv->drm,
11288                             "Arbitrary cursor panning not supported\n");
11289                 return -EINVAL;
11290         }
11291
11292         /*
11293          * Put the final coordinates back so that the src
11294          * coordinate checks will see the right values.
11295          */
11296         drm_rect_translate_to(&plane_state->uapi.src,
11297                               src_x << 16, src_y << 16);
11298
11299         /* ILK+ do this automagically in hardware */
11300         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11301                 const struct drm_framebuffer *fb = plane_state->hw.fb;
11302                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11303                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11304
11305                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11306         }
11307
11308         plane_state->color_plane[0].offset = offset;
11309         plane_state->color_plane[0].x = src_x;
11310         plane_state->color_plane[0].y = src_y;
11311
11312         return 0;
11313 }
11314
11315 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11316                               struct intel_plane_state *plane_state)
11317 {
11318         const struct drm_framebuffer *fb = plane_state->hw.fb;
11319         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11320         int ret;
11321
11322         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11323                 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11324                 return -EINVAL;
11325         }
11326
11327         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11328                                                   &crtc_state->uapi,
11329                                                   DRM_PLANE_HELPER_NO_SCALING,
11330                                                   DRM_PLANE_HELPER_NO_SCALING,
11331                                                   true, true);
11332         if (ret)
11333                 return ret;
11334
11335         /* Use the unclipped src/dst rectangles, which we program to hw */
11336         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11337         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11338
11339         ret = intel_cursor_check_surface(plane_state);
11340         if (ret)
11341                 return ret;
11342
11343         if (!plane_state->uapi.visible)
11344                 return 0;
11345
11346         ret = intel_plane_check_src_coordinates(plane_state);
11347         if (ret)
11348                 return ret;
11349
11350         return 0;
11351 }
11352
11353 static unsigned int
11354 i845_cursor_max_stride(struct intel_plane *plane,
11355                        u32 pixel_format, u64 modifier,
11356                        unsigned int rotation)
11357 {
11358         return 2048;
11359 }
11360
11361 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11362 {
11363         u32 cntl = 0;
11364
11365         if (crtc_state->gamma_enable)
11366                 cntl |= CURSOR_GAMMA_ENABLE;
11367
11368         return cntl;
11369 }
11370
11371 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11372                            const struct intel_plane_state *plane_state)
11373 {
11374         return CURSOR_ENABLE |
11375                 CURSOR_FORMAT_ARGB |
11376                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11377 }
11378
11379 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11380 {
11381         int width = drm_rect_width(&plane_state->uapi.dst);
11382
11383         /*
11384          * 845g/865g are only limited by the width of their cursors,
11385          * the height is arbitrary up to the precision of the register.
11386          */
11387         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11388 }
11389
11390 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11391                              struct intel_plane_state *plane_state)
11392 {
11393         const struct drm_framebuffer *fb = plane_state->hw.fb;
11394         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11395         int ret;
11396
11397         ret = intel_check_cursor(crtc_state, plane_state);
11398         if (ret)
11399                 return ret;
11400
11401         /* if we want to turn off the cursor ignore width and height */
11402         if (!fb)
11403                 return 0;
11404
11405         /* Check for which cursor types we support */
11406         if (!i845_cursor_size_ok(plane_state)) {
11407                 drm_dbg_kms(&i915->drm,
11408                             "Cursor dimension %dx%d not supported\n",
11409                             drm_rect_width(&plane_state->uapi.dst),
11410                             drm_rect_height(&plane_state->uapi.dst));
11411                 return -EINVAL;
11412         }
11413
11414         drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11415                     plane_state->color_plane[0].stride != fb->pitches[0]);
11416
11417         switch (fb->pitches[0]) {
11418         case 256:
11419         case 512:
11420         case 1024:
11421         case 2048:
11422                 break;
11423         default:
11424                  drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11425                              fb->pitches[0]);
11426                 return -EINVAL;
11427         }
11428
11429         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11430
11431         return 0;
11432 }
11433
11434 static void i845_update_cursor(struct intel_plane *plane,
11435                                const struct intel_crtc_state *crtc_state,
11436                                const struct intel_plane_state *plane_state)
11437 {
11438         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11439         u32 cntl = 0, base = 0, pos = 0, size = 0;
11440         unsigned long irqflags;
11441
11442         if (plane_state && plane_state->uapi.visible) {
11443                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11444                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11445
11446                 cntl = plane_state->ctl |
11447                         i845_cursor_ctl_crtc(crtc_state);
11448
11449                 size = (height << 12) | width;
11450
11451                 base = intel_cursor_base(plane_state);
11452                 pos = intel_cursor_position(plane_state);
11453         }
11454
11455         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11456
11457         /* On these chipsets we can only modify the base/size/stride
11458          * whilst the cursor is disabled.
11459          */
11460         if (plane->cursor.base != base ||
11461             plane->cursor.size != size ||
11462             plane->cursor.cntl != cntl) {
11463                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11464                 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11465                 intel_de_write_fw(dev_priv, CURSIZE, size);
11466                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11467                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11468
11469                 plane->cursor.base = base;
11470                 plane->cursor.size = size;
11471                 plane->cursor.cntl = cntl;
11472         } else {
11473                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11474         }
11475
11476         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11477 }
11478
11479 static void i845_disable_cursor(struct intel_plane *plane,
11480                                 const struct intel_crtc_state *crtc_state)
11481 {
11482         i845_update_cursor(plane, crtc_state, NULL);
11483 }
11484
11485 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11486                                      enum pipe *pipe)
11487 {
11488         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11489         enum intel_display_power_domain power_domain;
11490         intel_wakeref_t wakeref;
11491         bool ret;
11492
11493         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11494         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11495         if (!wakeref)
11496                 return false;
11497
11498         ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11499
11500         *pipe = PIPE_A;
11501
11502         intel_display_power_put(dev_priv, power_domain, wakeref);
11503
11504         return ret;
11505 }
11506
11507 static unsigned int
11508 i9xx_cursor_max_stride(struct intel_plane *plane,
11509                        u32 pixel_format, u64 modifier,
11510                        unsigned int rotation)
11511 {
11512         return plane->base.dev->mode_config.cursor_width * 4;
11513 }
11514
11515 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11516 {
11517         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11518         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11519         u32 cntl = 0;
11520
11521         if (INTEL_GEN(dev_priv) >= 11)
11522                 return cntl;
11523
11524         if (crtc_state->gamma_enable)
11525                 cntl = MCURSOR_GAMMA_ENABLE;
11526
11527         if (crtc_state->csc_enable)
11528                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11529
11530         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11531                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11532
11533         return cntl;
11534 }
11535
11536 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11537                            const struct intel_plane_state *plane_state)
11538 {
11539         struct drm_i915_private *dev_priv =
11540                 to_i915(plane_state->uapi.plane->dev);
11541         u32 cntl = 0;
11542
11543         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11544                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11545
11546         switch (drm_rect_width(&plane_state->uapi.dst)) {
11547         case 64:
11548                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11549                 break;
11550         case 128:
11551                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11552                 break;
11553         case 256:
11554                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11555                 break;
11556         default:
11557                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11558                 return 0;
11559         }
11560
11561         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11562                 cntl |= MCURSOR_ROTATE_180;
11563
11564         return cntl;
11565 }
11566
11567 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11568 {
11569         struct drm_i915_private *dev_priv =
11570                 to_i915(plane_state->uapi.plane->dev);
11571         int width = drm_rect_width(&plane_state->uapi.dst);
11572         int height = drm_rect_height(&plane_state->uapi.dst);
11573
11574         if (!intel_cursor_size_ok(plane_state))
11575                 return false;
11576
11577         /* Cursor width is limited to a few power-of-two sizes */
11578         switch (width) {
11579         case 256:
11580         case 128:
11581         case 64:
11582                 break;
11583         default:
11584                 return false;
11585         }
11586
11587         /*
11588          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11589          * height from 8 lines up to the cursor width, when the
11590          * cursor is not rotated. Everything else requires square
11591          * cursors.
11592          */
11593         if (HAS_CUR_FBC(dev_priv) &&
11594             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11595                 if (height < 8 || height > width)
11596                         return false;
11597         } else {
11598                 if (height != width)
11599                         return false;
11600         }
11601
11602         return true;
11603 }
11604
11605 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11606                              struct intel_plane_state *plane_state)
11607 {
11608         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11609         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11610         const struct drm_framebuffer *fb = plane_state->hw.fb;
11611         enum pipe pipe = plane->pipe;
11612         int ret;
11613
11614         ret = intel_check_cursor(crtc_state, plane_state);
11615         if (ret)
11616                 return ret;
11617
11618         /* if we want to turn off the cursor ignore width and height */
11619         if (!fb)
11620                 return 0;
11621
11622         /* Check for which cursor types we support */
11623         if (!i9xx_cursor_size_ok(plane_state)) {
11624                 drm_dbg(&dev_priv->drm,
11625                         "Cursor dimension %dx%d not supported\n",
11626                         drm_rect_width(&plane_state->uapi.dst),
11627                         drm_rect_height(&plane_state->uapi.dst));
11628                 return -EINVAL;
11629         }
11630
11631         drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11632                     plane_state->color_plane[0].stride != fb->pitches[0]);
11633
11634         if (fb->pitches[0] !=
11635             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11636                 drm_dbg_kms(&dev_priv->drm,
11637                             "Invalid cursor stride (%u) (cursor width %d)\n",
11638                             fb->pitches[0],
11639                             drm_rect_width(&plane_state->uapi.dst));
11640                 return -EINVAL;
11641         }
11642
11643         /*
11644          * There's something wrong with the cursor on CHV pipe C.
11645          * If it straddles the left edge of the screen then
11646          * moving it away from the edge or disabling it often
11647          * results in a pipe underrun, and often that can lead to
11648          * dead pipe (constant underrun reported, and it scans
11649          * out just a solid color). To recover from that, the
11650          * display power well must be turned off and on again.
11651          * Refuse the put the cursor into that compromised position.
11652          */
11653         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11654             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11655                 drm_dbg_kms(&dev_priv->drm,
11656                             "CHV cursor C not allowed to straddle the left screen edge\n");
11657                 return -EINVAL;
11658         }
11659
11660         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11661
11662         return 0;
11663 }
11664
11665 static void i9xx_update_cursor(struct intel_plane *plane,
11666                                const struct intel_crtc_state *crtc_state,
11667                                const struct intel_plane_state *plane_state)
11668 {
11669         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11670         enum pipe pipe = plane->pipe;
11671         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11672         unsigned long irqflags;
11673
11674         if (plane_state && plane_state->uapi.visible) {
11675                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11676                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11677
11678                 cntl = plane_state->ctl |
11679                         i9xx_cursor_ctl_crtc(crtc_state);
11680
11681                 if (width != height)
11682                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11683
11684                 base = intel_cursor_base(plane_state);
11685                 pos = intel_cursor_position(plane_state);
11686         }
11687
11688         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11689
11690         /*
11691          * On some platforms writing CURCNTR first will also
11692          * cause CURPOS to be armed by the CURBASE write.
11693          * Without the CURCNTR write the CURPOS write would
11694          * arm itself. Thus we always update CURCNTR before
11695          * CURPOS.
11696          *
11697          * On other platforms CURPOS always requires the
11698          * CURBASE write to arm the update. Additonally
11699          * a write to any of the cursor register will cancel
11700          * an already armed cursor update. Thus leaving out
11701          * the CURBASE write after CURPOS could lead to a
11702          * cursor that doesn't appear to move, or even change
11703          * shape. Thus we always write CURBASE.
11704          *
11705          * The other registers are armed by by the CURBASE write
11706          * except when the plane is getting enabled at which time
11707          * the CURCNTR write arms the update.
11708          */
11709
11710         if (INTEL_GEN(dev_priv) >= 9)
11711                 skl_write_cursor_wm(plane, crtc_state);
11712
11713         if (plane->cursor.base != base ||
11714             plane->cursor.size != fbc_ctl ||
11715             plane->cursor.cntl != cntl) {
11716                 if (HAS_CUR_FBC(dev_priv))
11717                         intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11718                                           fbc_ctl);
11719                 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11720                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11721                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11722
11723                 plane->cursor.base = base;
11724                 plane->cursor.size = fbc_ctl;
11725                 plane->cursor.cntl = cntl;
11726         } else {
11727                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11728                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11729         }
11730
11731         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11732 }
11733
11734 static void i9xx_disable_cursor(struct intel_plane *plane,
11735                                 const struct intel_crtc_state *crtc_state)
11736 {
11737         i9xx_update_cursor(plane, crtc_state, NULL);
11738 }
11739
11740 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11741                                      enum pipe *pipe)
11742 {
11743         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11744         enum intel_display_power_domain power_domain;
11745         intel_wakeref_t wakeref;
11746         bool ret;
11747         u32 val;
11748
11749         /*
11750          * Not 100% correct for planes that can move between pipes,
11751          * but that's only the case for gen2-3 which don't have any
11752          * display power wells.
11753          */
11754         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11755         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11756         if (!wakeref)
11757                 return false;
11758
11759         val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11760
11761         ret = val & MCURSOR_MODE;
11762
11763         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11764                 *pipe = plane->pipe;
11765         else
11766                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11767                         MCURSOR_PIPE_SELECT_SHIFT;
11768
11769         intel_display_power_put(dev_priv, power_domain, wakeref);
11770
11771         return ret;
11772 }
11773
11774 /* VESA 640x480x72Hz mode to set on the pipe */
11775 static const struct drm_display_mode load_detect_mode = {
11776         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11777                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11778 };
11779
11780 struct drm_framebuffer *
11781 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11782                          struct drm_mode_fb_cmd2 *mode_cmd)
11783 {
11784         struct intel_framebuffer *intel_fb;
11785         int ret;
11786
11787         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11788         if (!intel_fb)
11789                 return ERR_PTR(-ENOMEM);
11790
11791         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11792         if (ret)
11793                 goto err;
11794
11795         return &intel_fb->base;
11796
11797 err:
11798         kfree(intel_fb);
11799         return ERR_PTR(ret);
11800 }
11801
11802 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11803                                         struct drm_crtc *crtc)
11804 {
11805         struct drm_plane *plane;
11806         struct drm_plane_state *plane_state;
11807         int ret, i;
11808
11809         ret = drm_atomic_add_affected_planes(state, crtc);
11810         if (ret)
11811                 return ret;
11812
11813         for_each_new_plane_in_state(state, plane, plane_state, i) {
11814                 if (plane_state->crtc != crtc)
11815                         continue;
11816
11817                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11818                 if (ret)
11819                         return ret;
11820
11821                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11822         }
11823
11824         return 0;
11825 }
11826
11827 int intel_get_load_detect_pipe(struct drm_connector *connector,
11828                                struct intel_load_detect_pipe *old,
11829                                struct drm_modeset_acquire_ctx *ctx)
11830 {
11831         struct intel_crtc *intel_crtc;
11832         struct intel_encoder *intel_encoder =
11833                 intel_attached_encoder(to_intel_connector(connector));
11834         struct drm_crtc *possible_crtc;
11835         struct drm_encoder *encoder = &intel_encoder->base;
11836         struct drm_crtc *crtc = NULL;
11837         struct drm_device *dev = encoder->dev;
11838         struct drm_i915_private *dev_priv = to_i915(dev);
11839         struct drm_mode_config *config = &dev->mode_config;
11840         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11841         struct drm_connector_state *connector_state;
11842         struct intel_crtc_state *crtc_state;
11843         int ret, i = -1;
11844
11845         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11846                     connector->base.id, connector->name,
11847                     encoder->base.id, encoder->name);
11848
11849         old->restore_state = NULL;
11850
11851         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
11852
11853         /*
11854          * Algorithm gets a little messy:
11855          *
11856          *   - if the connector already has an assigned crtc, use it (but make
11857          *     sure it's on first)
11858          *
11859          *   - try to find the first unused crtc that can drive this connector,
11860          *     and use that if we find one
11861          */
11862
11863         /* See if we already have a CRTC for this connector */
11864         if (connector->state->crtc) {
11865                 crtc = connector->state->crtc;
11866
11867                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11868                 if (ret)
11869                         goto fail;
11870
11871                 /* Make sure the crtc and connector are running */
11872                 goto found;
11873         }
11874
11875         /* Find an unused one (if possible) */
11876         for_each_crtc(dev, possible_crtc) {
11877                 i++;
11878                 if (!(encoder->possible_crtcs & (1 << i)))
11879                         continue;
11880
11881                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11882                 if (ret)
11883                         goto fail;
11884
11885                 if (possible_crtc->state->enable) {
11886                         drm_modeset_unlock(&possible_crtc->mutex);
11887                         continue;
11888                 }
11889
11890                 crtc = possible_crtc;
11891                 break;
11892         }
11893
11894         /*
11895          * If we didn't find an unused CRTC, don't use any.
11896          */
11897         if (!crtc) {
11898                 drm_dbg_kms(&dev_priv->drm,
11899                             "no pipe available for load-detect\n");
11900                 ret = -ENODEV;
11901                 goto fail;
11902         }
11903
11904 found:
11905         intel_crtc = to_intel_crtc(crtc);
11906
11907         state = drm_atomic_state_alloc(dev);
11908         restore_state = drm_atomic_state_alloc(dev);
11909         if (!state || !restore_state) {
11910                 ret = -ENOMEM;
11911                 goto fail;
11912         }
11913
11914         state->acquire_ctx = ctx;
11915         restore_state->acquire_ctx = ctx;
11916
11917         connector_state = drm_atomic_get_connector_state(state, connector);
11918         if (IS_ERR(connector_state)) {
11919                 ret = PTR_ERR(connector_state);
11920                 goto fail;
11921         }
11922
11923         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11924         if (ret)
11925                 goto fail;
11926
11927         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11928         if (IS_ERR(crtc_state)) {
11929                 ret = PTR_ERR(crtc_state);
11930                 goto fail;
11931         }
11932
11933         crtc_state->uapi.active = true;
11934
11935         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11936                                            &load_detect_mode);
11937         if (ret)
11938                 goto fail;
11939
11940         ret = intel_modeset_disable_planes(state, crtc);
11941         if (ret)
11942                 goto fail;
11943
11944         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11945         if (!ret)
11946                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11947         if (!ret)
11948                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11949         if (ret) {
11950                 drm_dbg_kms(&dev_priv->drm,
11951                             "Failed to create a copy of old state to restore: %i\n",
11952                             ret);
11953                 goto fail;
11954         }
11955
11956         ret = drm_atomic_commit(state);
11957         if (ret) {
11958                 drm_dbg_kms(&dev_priv->drm,
11959                             "failed to set mode on load-detect pipe\n");
11960                 goto fail;
11961         }
11962
11963         old->restore_state = restore_state;
11964         drm_atomic_state_put(state);
11965
11966         /* let the connector get through one full cycle before testing */
11967         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11968         return true;
11969
11970 fail:
11971         if (state) {
11972                 drm_atomic_state_put(state);
11973                 state = NULL;
11974         }
11975         if (restore_state) {
11976                 drm_atomic_state_put(restore_state);
11977                 restore_state = NULL;
11978         }
11979
11980         if (ret == -EDEADLK)
11981                 return ret;
11982
11983         return false;
11984 }
11985
11986 void intel_release_load_detect_pipe(struct drm_connector *connector,
11987                                     struct intel_load_detect_pipe *old,
11988                                     struct drm_modeset_acquire_ctx *ctx)
11989 {
11990         struct intel_encoder *intel_encoder =
11991                 intel_attached_encoder(to_intel_connector(connector));
11992         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
11993         struct drm_encoder *encoder = &intel_encoder->base;
11994         struct drm_atomic_state *state = old->restore_state;
11995         int ret;
11996
11997         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11998                     connector->base.id, connector->name,
11999                     encoder->base.id, encoder->name);
12000
12001         if (!state)
12002                 return;
12003
12004         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12005         if (ret)
12006                 drm_dbg_kms(&i915->drm,
12007                             "Couldn't release load detect pipe: %i\n", ret);
12008         drm_atomic_state_put(state);
12009 }
12010
12011 static int i9xx_pll_refclk(struct drm_device *dev,
12012                            const struct intel_crtc_state *pipe_config)
12013 {
12014         struct drm_i915_private *dev_priv = to_i915(dev);
12015         u32 dpll = pipe_config->dpll_hw_state.dpll;
12016
12017         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12018                 return dev_priv->vbt.lvds_ssc_freq;
12019         else if (HAS_PCH_SPLIT(dev_priv))
12020                 return 120000;
12021         else if (!IS_GEN(dev_priv, 2))
12022                 return 96000;
12023         else
12024                 return 48000;
12025 }
12026
12027 /* Returns the clock of the currently programmed mode of the given pipe. */
12028 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12029                                 struct intel_crtc_state *pipe_config)
12030 {
12031         struct drm_device *dev = crtc->base.dev;
12032         struct drm_i915_private *dev_priv = to_i915(dev);
12033         enum pipe pipe = crtc->pipe;
12034         u32 dpll = pipe_config->dpll_hw_state.dpll;
12035         u32 fp;
12036         struct dpll clock;
12037         int port_clock;
12038         int refclk = i9xx_pll_refclk(dev, pipe_config);
12039
12040         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12041                 fp = pipe_config->dpll_hw_state.fp0;
12042         else
12043                 fp = pipe_config->dpll_hw_state.fp1;
12044
12045         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12046         if (IS_PINEVIEW(dev_priv)) {
12047                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12048                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12049         } else {
12050                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12051                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12052         }
12053
12054         if (!IS_GEN(dev_priv, 2)) {
12055                 if (IS_PINEVIEW(dev_priv))
12056                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12057                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12058                 else
12059                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12060                                DPLL_FPA01_P1_POST_DIV_SHIFT);
12061
12062                 switch (dpll & DPLL_MODE_MASK) {
12063                 case DPLLB_MODE_DAC_SERIAL:
12064                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12065                                 5 : 10;
12066                         break;
12067                 case DPLLB_MODE_LVDS:
12068                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12069                                 7 : 14;
12070                         break;
12071                 default:
12072                         drm_dbg_kms(&dev_priv->drm,
12073                                     "Unknown DPLL mode %08x in programmed "
12074                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
12075                         return;
12076                 }
12077
12078                 if (IS_PINEVIEW(dev_priv))
12079                         port_clock = pnv_calc_dpll_params(refclk, &clock);
12080                 else
12081                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
12082         } else {
12083                 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12084                                                                  LVDS);
12085                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12086
12087                 if (is_lvds) {
12088                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12089                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
12090
12091                         if (lvds & LVDS_CLKB_POWER_UP)
12092                                 clock.p2 = 7;
12093                         else
12094                                 clock.p2 = 14;
12095                 } else {
12096                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
12097                                 clock.p1 = 2;
12098                         else {
12099                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12100                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12101                         }
12102                         if (dpll & PLL_P2_DIVIDE_BY_4)
12103                                 clock.p2 = 4;
12104                         else
12105                                 clock.p2 = 2;
12106                 }
12107
12108                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12109         }
12110
12111         /*
12112          * This value includes pixel_multiplier. We will use
12113          * port_clock to compute adjusted_mode.crtc_clock in the
12114          * encoder's get_config() function.
12115          */
12116         pipe_config->port_clock = port_clock;
12117 }
12118
12119 int intel_dotclock_calculate(int link_freq,
12120                              const struct intel_link_m_n *m_n)
12121 {
12122         /*
12123          * The calculation for the data clock is:
12124          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12125          * But we want to avoid losing precison if possible, so:
12126          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12127          *
12128          * and the link clock is simpler:
12129          * link_clock = (m * link_clock) / n
12130          */
12131
12132         if (!m_n->link_n)
12133                 return 0;
12134
12135         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12136 }
12137
12138 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12139                               struct intel_crtc_state *pipe_config)
12140 {
12141         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12142
12143         /* read out port_clock from the DPLL */
12144         i9xx_crtc_clock_get(crtc, pipe_config);
12145
12146         /*
12147          * In case there is an active pipe without active ports,
12148          * we may need some idea for the dotclock anyway.
12149          * Calculate one based on the FDI configuration.
12150          */
12151         pipe_config->hw.adjusted_mode.crtc_clock =
12152                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12153                                          &pipe_config->fdi_m_n);
12154 }
12155
12156 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12157                                    struct intel_crtc *crtc)
12158 {
12159         memset(crtc_state, 0, sizeof(*crtc_state));
12160
12161         __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12162
12163         crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12164         crtc_state->master_transcoder = INVALID_TRANSCODER;
12165         crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12166         crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12167         crtc_state->scaler_state.scaler_id = -1;
12168         crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12169 }
12170
12171 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12172 {
12173         struct intel_crtc_state *crtc_state;
12174
12175         crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12176
12177         if (crtc_state)
12178                 intel_crtc_state_reset(crtc_state, crtc);
12179
12180         return crtc_state;
12181 }
12182
12183 /* Returns the currently programmed mode of the given encoder. */
12184 struct drm_display_mode *
12185 intel_encoder_current_mode(struct intel_encoder *encoder)
12186 {
12187         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12188         struct intel_crtc_state *crtc_state;
12189         struct drm_display_mode *mode;
12190         struct intel_crtc *crtc;
12191         enum pipe pipe;
12192
12193         if (!encoder->get_hw_state(encoder, &pipe))
12194                 return NULL;
12195
12196         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12197
12198         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12199         if (!mode)
12200                 return NULL;
12201
12202         crtc_state = intel_crtc_state_alloc(crtc);
12203         if (!crtc_state) {
12204                 kfree(mode);
12205                 return NULL;
12206         }
12207
12208         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12209                 kfree(crtc_state);
12210                 kfree(mode);
12211                 return NULL;
12212         }
12213
12214         encoder->get_config(encoder, crtc_state);
12215
12216         intel_mode_from_pipe_config(mode, crtc_state);
12217
12218         kfree(crtc_state);
12219
12220         return mode;
12221 }
12222
12223 static void intel_crtc_destroy(struct drm_crtc *crtc)
12224 {
12225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12226
12227         drm_crtc_cleanup(crtc);
12228         kfree(intel_crtc);
12229 }
12230
12231 /**
12232  * intel_wm_need_update - Check whether watermarks need updating
12233  * @cur: current plane state
12234  * @new: new plane state
12235  *
12236  * Check current plane state versus the new one to determine whether
12237  * watermarks need to be recalculated.
12238  *
12239  * Returns true or false.
12240  */
12241 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12242                                  struct intel_plane_state *new)
12243 {
12244         /* Update watermarks on tiling or size changes. */
12245         if (new->uapi.visible != cur->uapi.visible)
12246                 return true;
12247
12248         if (!cur->hw.fb || !new->hw.fb)
12249                 return false;
12250
12251         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12252             cur->hw.rotation != new->hw.rotation ||
12253             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12254             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12255             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12256             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12257                 return true;
12258
12259         return false;
12260 }
12261
12262 static bool needs_scaling(const struct intel_plane_state *state)
12263 {
12264         int src_w = drm_rect_width(&state->uapi.src) >> 16;
12265         int src_h = drm_rect_height(&state->uapi.src) >> 16;
12266         int dst_w = drm_rect_width(&state->uapi.dst);
12267         int dst_h = drm_rect_height(&state->uapi.dst);
12268
12269         return (src_w != dst_w || src_h != dst_h);
12270 }
12271
12272 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12273                                     struct intel_crtc_state *crtc_state,
12274                                     const struct intel_plane_state *old_plane_state,
12275                                     struct intel_plane_state *plane_state)
12276 {
12277         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12278         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12279         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12280         bool mode_changed = needs_modeset(crtc_state);
12281         bool was_crtc_enabled = old_crtc_state->hw.active;
12282         bool is_crtc_enabled = crtc_state->hw.active;
12283         bool turn_off, turn_on, visible, was_visible;
12284         int ret;
12285
12286         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12287                 ret = skl_update_scaler_plane(crtc_state, plane_state);
12288                 if (ret)
12289                         return ret;
12290         }
12291
12292         was_visible = old_plane_state->uapi.visible;
12293         visible = plane_state->uapi.visible;
12294
12295         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12296                 was_visible = false;
12297
12298         /*
12299          * Visibility is calculated as if the crtc was on, but
12300          * after scaler setup everything depends on it being off
12301          * when the crtc isn't active.
12302          *
12303          * FIXME this is wrong for watermarks. Watermarks should also
12304          * be computed as if the pipe would be active. Perhaps move
12305          * per-plane wm computation to the .check_plane() hook, and
12306          * only combine the results from all planes in the current place?
12307          */
12308         if (!is_crtc_enabled) {
12309                 intel_plane_set_invisible(crtc_state, plane_state);
12310                 visible = false;
12311         }
12312
12313         if (!was_visible && !visible)
12314                 return 0;
12315
12316         turn_off = was_visible && (!visible || mode_changed);
12317         turn_on = visible && (!was_visible || mode_changed);
12318
12319         drm_dbg_atomic(&dev_priv->drm,
12320                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12321                        crtc->base.base.id, crtc->base.name,
12322                        plane->base.base.id, plane->base.name,
12323                        was_visible, visible,
12324                        turn_off, turn_on, mode_changed);
12325
12326         if (turn_on) {
12327                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12328                         crtc_state->update_wm_pre = true;
12329
12330                 /* must disable cxsr around plane enable/disable */
12331                 if (plane->id != PLANE_CURSOR)
12332                         crtc_state->disable_cxsr = true;
12333         } else if (turn_off) {
12334                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12335                         crtc_state->update_wm_post = true;
12336
12337                 /* must disable cxsr around plane enable/disable */
12338                 if (plane->id != PLANE_CURSOR)
12339                         crtc_state->disable_cxsr = true;
12340         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12341                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12342                         /* FIXME bollocks */
12343                         crtc_state->update_wm_pre = true;
12344                         crtc_state->update_wm_post = true;
12345                 }
12346         }
12347
12348         if (visible || was_visible)
12349                 crtc_state->fb_bits |= plane->frontbuffer_bit;
12350
12351         /*
12352          * ILK/SNB DVSACNTR/Sprite Enable
12353          * IVB SPR_CTL/Sprite Enable
12354          * "When in Self Refresh Big FIFO mode, a write to enable the
12355          *  plane will be internally buffered and delayed while Big FIFO
12356          *  mode is exiting."
12357          *
12358          * Which means that enabling the sprite can take an extra frame
12359          * when we start in big FIFO mode (LP1+). Thus we need to drop
12360          * down to LP0 and wait for vblank in order to make sure the
12361          * sprite gets enabled on the next vblank after the register write.
12362          * Doing otherwise would risk enabling the sprite one frame after
12363          * we've already signalled flip completion. We can resume LP1+
12364          * once the sprite has been enabled.
12365          *
12366          *
12367          * WaCxSRDisabledForSpriteScaling:ivb
12368          * IVB SPR_SCALE/Scaling Enable
12369          * "Low Power watermarks must be disabled for at least one
12370          *  frame before enabling sprite scaling, and kept disabled
12371          *  until sprite scaling is disabled."
12372          *
12373          * ILK/SNB DVSASCALE/Scaling Enable
12374          * "When in Self Refresh Big FIFO mode, scaling enable will be
12375          *  masked off while Big FIFO mode is exiting."
12376          *
12377          * Despite the w/a only being listed for IVB we assume that
12378          * the ILK/SNB note has similar ramifications, hence we apply
12379          * the w/a on all three platforms.
12380          *
12381          * With experimental results seems this is needed also for primary
12382          * plane, not only sprite plane.
12383          */
12384         if (plane->id != PLANE_CURSOR &&
12385             (IS_GEN_RANGE(dev_priv, 5, 6) ||
12386              IS_IVYBRIDGE(dev_priv)) &&
12387             (turn_on || (!needs_scaling(old_plane_state) &&
12388                          needs_scaling(plane_state))))
12389                 crtc_state->disable_lp_wm = true;
12390
12391         return 0;
12392 }
12393
12394 static bool encoders_cloneable(const struct intel_encoder *a,
12395                                const struct intel_encoder *b)
12396 {
12397         /* masks could be asymmetric, so check both ways */
12398         return a == b || (a->cloneable & (1 << b->type) &&
12399                           b->cloneable & (1 << a->type));
12400 }
12401
12402 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12403                                          struct intel_crtc *crtc,
12404                                          struct intel_encoder *encoder)
12405 {
12406         struct intel_encoder *source_encoder;
12407         struct drm_connector *connector;
12408         struct drm_connector_state *connector_state;
12409         int i;
12410
12411         for_each_new_connector_in_state(state, connector, connector_state, i) {
12412                 if (connector_state->crtc != &crtc->base)
12413                         continue;
12414
12415                 source_encoder =
12416                         to_intel_encoder(connector_state->best_encoder);
12417                 if (!encoders_cloneable(encoder, source_encoder))
12418                         return false;
12419         }
12420
12421         return true;
12422 }
12423
12424 static int icl_add_linked_planes(struct intel_atomic_state *state)
12425 {
12426         struct intel_plane *plane, *linked;
12427         struct intel_plane_state *plane_state, *linked_plane_state;
12428         int i;
12429
12430         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12431                 linked = plane_state->planar_linked_plane;
12432
12433                 if (!linked)
12434                         continue;
12435
12436                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12437                 if (IS_ERR(linked_plane_state))
12438                         return PTR_ERR(linked_plane_state);
12439
12440                 drm_WARN_ON(state->base.dev,
12441                             linked_plane_state->planar_linked_plane != plane);
12442                 drm_WARN_ON(state->base.dev,
12443                             linked_plane_state->planar_slave == plane_state->planar_slave);
12444         }
12445
12446         return 0;
12447 }
12448
12449 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12450 {
12451         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12452         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12453         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12454         struct intel_plane *plane, *linked;
12455         struct intel_plane_state *plane_state;
12456         int i;
12457
12458         if (INTEL_GEN(dev_priv) < 11)
12459                 return 0;
12460
12461         /*
12462          * Destroy all old plane links and make the slave plane invisible
12463          * in the crtc_state->active_planes mask.
12464          */
12465         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12466                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12467                         continue;
12468
12469                 plane_state->planar_linked_plane = NULL;
12470                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12471                         crtc_state->active_planes &= ~BIT(plane->id);
12472                         crtc_state->update_planes |= BIT(plane->id);
12473                 }
12474
12475                 plane_state->planar_slave = false;
12476         }
12477
12478         if (!crtc_state->nv12_planes)
12479                 return 0;
12480
12481         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12482                 struct intel_plane_state *linked_state = NULL;
12483
12484                 if (plane->pipe != crtc->pipe ||
12485                     !(crtc_state->nv12_planes & BIT(plane->id)))
12486                         continue;
12487
12488                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12489                         if (!icl_is_nv12_y_plane(linked->id))
12490                                 continue;
12491
12492                         if (crtc_state->active_planes & BIT(linked->id))
12493                                 continue;
12494
12495                         linked_state = intel_atomic_get_plane_state(state, linked);
12496                         if (IS_ERR(linked_state))
12497                                 return PTR_ERR(linked_state);
12498
12499                         break;
12500                 }
12501
12502                 if (!linked_state) {
12503                         drm_dbg_kms(&dev_priv->drm,
12504                                     "Need %d free Y planes for planar YUV\n",
12505                                     hweight8(crtc_state->nv12_planes));
12506
12507                         return -EINVAL;
12508                 }
12509
12510                 plane_state->planar_linked_plane = linked;
12511
12512                 linked_state->planar_slave = true;
12513                 linked_state->planar_linked_plane = plane;
12514                 crtc_state->active_planes |= BIT(linked->id);
12515                 crtc_state->update_planes |= BIT(linked->id);
12516                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12517                             linked->base.name, plane->base.name);
12518
12519                 /* Copy parameters to slave plane */
12520                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12521                 linked_state->color_ctl = plane_state->color_ctl;
12522                 linked_state->view = plane_state->view;
12523                 memcpy(linked_state->color_plane, plane_state->color_plane,
12524                        sizeof(linked_state->color_plane));
12525
12526                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12527                 linked_state->uapi.src = plane_state->uapi.src;
12528                 linked_state->uapi.dst = plane_state->uapi.dst;
12529
12530                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12531                         if (linked->id == PLANE_SPRITE5)
12532                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12533                         else if (linked->id == PLANE_SPRITE4)
12534                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12535                         else
12536                                 MISSING_CASE(linked->id);
12537                 }
12538         }
12539
12540         return 0;
12541 }
12542
12543 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12544 {
12545         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12546         struct intel_atomic_state *state =
12547                 to_intel_atomic_state(new_crtc_state->uapi.state);
12548         const struct intel_crtc_state *old_crtc_state =
12549                 intel_atomic_get_old_crtc_state(state, crtc);
12550
12551         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12552 }
12553
12554 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12555 {
12556         const struct drm_display_mode *adjusted_mode =
12557                 &crtc_state->hw.adjusted_mode;
12558
12559         if (!crtc_state->hw.enable)
12560                 return 0;
12561
12562         return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12563                                  adjusted_mode->crtc_clock);
12564 }
12565
12566 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12567                                const struct intel_cdclk_state *cdclk_state)
12568 {
12569         const struct drm_display_mode *adjusted_mode =
12570                 &crtc_state->hw.adjusted_mode;
12571
12572         if (!crtc_state->hw.enable)
12573                 return 0;
12574
12575         return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12576                                  cdclk_state->logical.cdclk);
12577 }
12578
12579 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12580 {
12581         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12582         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12583         const struct drm_display_mode *adjusted_mode =
12584                 &crtc_state->hw.adjusted_mode;
12585         u16 linetime_wm;
12586
12587         if (!crtc_state->hw.enable)
12588                 return 0;
12589
12590         linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12591                                    crtc_state->pixel_rate);
12592
12593         /* Display WA #1135: BXT:ALL GLK:ALL */
12594         if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12595                 linetime_wm /= 2;
12596
12597         return linetime_wm;
12598 }
12599
12600 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12601                                    struct intel_crtc *crtc)
12602 {
12603         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12604         struct intel_crtc_state *crtc_state =
12605                 intel_atomic_get_new_crtc_state(state, crtc);
12606         const struct intel_cdclk_state *cdclk_state;
12607
12608         if (INTEL_GEN(dev_priv) >= 9)
12609                 crtc_state->linetime = skl_linetime_wm(crtc_state);
12610         else
12611                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12612
12613         if (!hsw_crtc_supports_ips(crtc))
12614                 return 0;
12615
12616         cdclk_state = intel_atomic_get_cdclk_state(state);
12617         if (IS_ERR(cdclk_state))
12618                 return PTR_ERR(cdclk_state);
12619
12620         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12621                                                        cdclk_state);
12622
12623         return 0;
12624 }
12625
12626 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12627                                    struct intel_crtc *crtc)
12628 {
12629         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12630         struct intel_crtc_state *crtc_state =
12631                 intel_atomic_get_new_crtc_state(state, crtc);
12632         bool mode_changed = needs_modeset(crtc_state);
12633         int ret;
12634
12635         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12636             mode_changed && !crtc_state->hw.active)
12637                 crtc_state->update_wm_post = true;
12638
12639         if (mode_changed && crtc_state->hw.enable &&
12640             dev_priv->display.crtc_compute_clock &&
12641             !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12642                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12643                 if (ret)
12644                         return ret;
12645         }
12646
12647         /*
12648          * May need to update pipe gamma enable bits
12649          * when C8 planes are getting enabled/disabled.
12650          */
12651         if (c8_planes_changed(crtc_state))
12652                 crtc_state->uapi.color_mgmt_changed = true;
12653
12654         if (mode_changed || crtc_state->update_pipe ||
12655             crtc_state->uapi.color_mgmt_changed) {
12656                 ret = intel_color_check(crtc_state);
12657                 if (ret)
12658                         return ret;
12659         }
12660
12661         if (dev_priv->display.compute_pipe_wm) {
12662                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12663                 if (ret) {
12664                         drm_dbg_kms(&dev_priv->drm,
12665                                     "Target pipe watermarks are invalid\n");
12666                         return ret;
12667                 }
12668         }
12669
12670         if (dev_priv->display.compute_intermediate_wm) {
12671                 if (drm_WARN_ON(&dev_priv->drm,
12672                                 !dev_priv->display.compute_pipe_wm))
12673                         return 0;
12674
12675                 /*
12676                  * Calculate 'intermediate' watermarks that satisfy both the
12677                  * old state and the new state.  We can program these
12678                  * immediately.
12679                  */
12680                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12681                 if (ret) {
12682                         drm_dbg_kms(&dev_priv->drm,
12683                                     "No valid intermediate pipe watermarks are possible\n");
12684                         return ret;
12685                 }
12686         }
12687
12688         if (INTEL_GEN(dev_priv) >= 9) {
12689                 if (mode_changed || crtc_state->update_pipe) {
12690                         ret = skl_update_scaler_crtc(crtc_state);
12691                         if (ret)
12692                                 return ret;
12693                 }
12694
12695                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12696                 if (ret)
12697                         return ret;
12698         }
12699
12700         if (HAS_IPS(dev_priv)) {
12701                 ret = hsw_compute_ips_config(crtc_state);
12702                 if (ret)
12703                         return ret;
12704         }
12705
12706         if (INTEL_GEN(dev_priv) >= 9 ||
12707             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12708                 ret = hsw_compute_linetime_wm(state, crtc);
12709                 if (ret)
12710                         return ret;
12711
12712         }
12713
12714         return 0;
12715 }
12716
12717 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12718 {
12719         struct intel_connector *connector;
12720         struct drm_connector_list_iter conn_iter;
12721
12722         drm_connector_list_iter_begin(dev, &conn_iter);
12723         for_each_intel_connector_iter(connector, &conn_iter) {
12724                 if (connector->base.state->crtc)
12725                         drm_connector_put(&connector->base);
12726
12727                 if (connector->base.encoder) {
12728                         connector->base.state->best_encoder =
12729                                 connector->base.encoder;
12730                         connector->base.state->crtc =
12731                                 connector->base.encoder->crtc;
12732
12733                         drm_connector_get(&connector->base);
12734                 } else {
12735                         connector->base.state->best_encoder = NULL;
12736                         connector->base.state->crtc = NULL;
12737                 }
12738         }
12739         drm_connector_list_iter_end(&conn_iter);
12740 }
12741
12742 static int
12743 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12744                       struct intel_crtc_state *pipe_config)
12745 {
12746         struct drm_connector *connector = conn_state->connector;
12747         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12748         const struct drm_display_info *info = &connector->display_info;
12749         int bpp;
12750
12751         switch (conn_state->max_bpc) {
12752         case 6 ... 7:
12753                 bpp = 6 * 3;
12754                 break;
12755         case 8 ... 9:
12756                 bpp = 8 * 3;
12757                 break;
12758         case 10 ... 11:
12759                 bpp = 10 * 3;
12760                 break;
12761         case 12:
12762                 bpp = 12 * 3;
12763                 break;
12764         default:
12765                 return -EINVAL;
12766         }
12767
12768         if (bpp < pipe_config->pipe_bpp) {
12769                 drm_dbg_kms(&i915->drm,
12770                             "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12771                             "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12772                             connector->base.id, connector->name,
12773                             bpp, 3 * info->bpc,
12774                             3 * conn_state->max_requested_bpc,
12775                             pipe_config->pipe_bpp);
12776
12777                 pipe_config->pipe_bpp = bpp;
12778         }
12779
12780         return 0;
12781 }
12782
12783 static int
12784 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12785                           struct intel_crtc_state *pipe_config)
12786 {
12787         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12788         struct drm_atomic_state *state = pipe_config->uapi.state;
12789         struct drm_connector *connector;
12790         struct drm_connector_state *connector_state;
12791         int bpp, i;
12792
12793         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12794             IS_CHERRYVIEW(dev_priv)))
12795                 bpp = 10*3;
12796         else if (INTEL_GEN(dev_priv) >= 5)
12797                 bpp = 12*3;
12798         else
12799                 bpp = 8*3;
12800
12801         pipe_config->pipe_bpp = bpp;
12802
12803         /* Clamp display bpp to connector max bpp */
12804         for_each_new_connector_in_state(state, connector, connector_state, i) {
12805                 int ret;
12806
12807                 if (connector_state->crtc != &crtc->base)
12808                         continue;
12809
12810                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12811                 if (ret)
12812                         return ret;
12813         }
12814
12815         return 0;
12816 }
12817
12818 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
12819                                     const struct drm_display_mode *mode)
12820 {
12821         drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
12822                     "type: 0x%x flags: 0x%x\n",
12823                     mode->crtc_clock,
12824                     mode->crtc_hdisplay, mode->crtc_hsync_start,
12825                     mode->crtc_hsync_end, mode->crtc_htotal,
12826                     mode->crtc_vdisplay, mode->crtc_vsync_start,
12827                     mode->crtc_vsync_end, mode->crtc_vtotal,
12828                     mode->type, mode->flags);
12829 }
12830
12831 static void
12832 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12833                       const char *id, unsigned int lane_count,
12834                       const struct intel_link_m_n *m_n)
12835 {
12836         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12837
12838         drm_dbg_kms(&i915->drm,
12839                     "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12840                     id, lane_count,
12841                     m_n->gmch_m, m_n->gmch_n,
12842                     m_n->link_m, m_n->link_n, m_n->tu);
12843 }
12844
12845 static void
12846 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12847                      const union hdmi_infoframe *frame)
12848 {
12849         if (!drm_debug_enabled(DRM_UT_KMS))
12850                 return;
12851
12852         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12853 }
12854
12855 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12856
12857 static const char * const output_type_str[] = {
12858         OUTPUT_TYPE(UNUSED),
12859         OUTPUT_TYPE(ANALOG),
12860         OUTPUT_TYPE(DVO),
12861         OUTPUT_TYPE(SDVO),
12862         OUTPUT_TYPE(LVDS),
12863         OUTPUT_TYPE(TVOUT),
12864         OUTPUT_TYPE(HDMI),
12865         OUTPUT_TYPE(DP),
12866         OUTPUT_TYPE(EDP),
12867         OUTPUT_TYPE(DSI),
12868         OUTPUT_TYPE(DDI),
12869         OUTPUT_TYPE(DP_MST),
12870 };
12871
12872 #undef OUTPUT_TYPE
12873
12874 static void snprintf_output_types(char *buf, size_t len,
12875                                   unsigned int output_types)
12876 {
12877         char *str = buf;
12878         int i;
12879
12880         str[0] = '\0';
12881
12882         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12883                 int r;
12884
12885                 if ((output_types & BIT(i)) == 0)
12886                         continue;
12887
12888                 r = snprintf(str, len, "%s%s",
12889                              str != buf ? "," : "", output_type_str[i]);
12890                 if (r >= len)
12891                         break;
12892                 str += r;
12893                 len -= r;
12894
12895                 output_types &= ~BIT(i);
12896         }
12897
12898         WARN_ON_ONCE(output_types != 0);
12899 }
12900
12901 static const char * const output_format_str[] = {
12902         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12903         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12904         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12905         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12906 };
12907
12908 static const char *output_formats(enum intel_output_format format)
12909 {
12910         if (format >= ARRAY_SIZE(output_format_str))
12911                 format = INTEL_OUTPUT_FORMAT_INVALID;
12912         return output_format_str[format];
12913 }
12914
12915 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12916 {
12917         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12918         struct drm_i915_private *i915 = to_i915(plane->base.dev);
12919         const struct drm_framebuffer *fb = plane_state->hw.fb;
12920         struct drm_format_name_buf format_name;
12921
12922         if (!fb) {
12923                 drm_dbg_kms(&i915->drm,
12924                             "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12925                             plane->base.base.id, plane->base.name,
12926                             yesno(plane_state->uapi.visible));
12927                 return;
12928         }
12929
12930         drm_dbg_kms(&i915->drm,
12931                     "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12932                     plane->base.base.id, plane->base.name,
12933                     fb->base.id, fb->width, fb->height,
12934                     drm_get_format_name(fb->format->format, &format_name),
12935                     yesno(plane_state->uapi.visible));
12936         drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
12937                     plane_state->hw.rotation, plane_state->scaler_id);
12938         if (plane_state->uapi.visible)
12939                 drm_dbg_kms(&i915->drm,
12940                             "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12941                             DRM_RECT_FP_ARG(&plane_state->uapi.src),
12942                             DRM_RECT_ARG(&plane_state->uapi.dst));
12943 }
12944
12945 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12946                                    struct intel_atomic_state *state,
12947                                    const char *context)
12948 {
12949         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12951         const struct intel_plane_state *plane_state;
12952         struct intel_plane *plane;
12953         char buf[64];
12954         int i;
12955
12956         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
12957                     crtc->base.base.id, crtc->base.name,
12958                     yesno(pipe_config->hw.enable), context);
12959
12960         if (!pipe_config->hw.enable)
12961                 goto dump_planes;
12962
12963         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12964         drm_dbg_kms(&dev_priv->drm,
12965                     "active: %s, output_types: %s (0x%x), output format: %s\n",
12966                     yesno(pipe_config->hw.active),
12967                     buf, pipe_config->output_types,
12968                     output_formats(pipe_config->output_format));
12969
12970         drm_dbg_kms(&dev_priv->drm,
12971                     "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12972                     transcoder_name(pipe_config->cpu_transcoder),
12973                     pipe_config->pipe_bpp, pipe_config->dither);
12974
12975         drm_dbg_kms(&dev_priv->drm,
12976                     "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
12977                     transcoder_name(pipe_config->master_transcoder),
12978                     pipe_config->sync_mode_slaves_mask);
12979
12980         if (pipe_config->has_pch_encoder)
12981                 intel_dump_m_n_config(pipe_config, "fdi",
12982                                       pipe_config->fdi_lanes,
12983                                       &pipe_config->fdi_m_n);
12984
12985         if (intel_crtc_has_dp_encoder(pipe_config)) {
12986                 intel_dump_m_n_config(pipe_config, "dp m_n",
12987                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12988                 if (pipe_config->has_drrs)
12989                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12990                                               pipe_config->lane_count,
12991                                               &pipe_config->dp_m2_n2);
12992         }
12993
12994         drm_dbg_kms(&dev_priv->drm,
12995                     "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12996                     pipe_config->has_audio, pipe_config->has_infoframe,
12997                     pipe_config->infoframes.enable);
12998
12999         if (pipe_config->infoframes.enable &
13000             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13001                 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13002                             pipe_config->infoframes.gcp);
13003         if (pipe_config->infoframes.enable &
13004             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13005                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13006         if (pipe_config->infoframes.enable &
13007             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13008                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13009         if (pipe_config->infoframes.enable &
13010             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13011                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13012
13013         drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13014         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13015         drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13016         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13017         intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13018         drm_dbg_kms(&dev_priv->drm,
13019                     "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13020                     pipe_config->port_clock,
13021                     pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13022                     pipe_config->pixel_rate);
13023
13024         drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13025                     pipe_config->linetime, pipe_config->ips_linetime);
13026
13027         if (INTEL_GEN(dev_priv) >= 9)
13028                 drm_dbg_kms(&dev_priv->drm,
13029                             "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13030                             crtc->num_scalers,
13031                             pipe_config->scaler_state.scaler_users,
13032                             pipe_config->scaler_state.scaler_id);
13033
13034         if (HAS_GMCH(dev_priv))
13035                 drm_dbg_kms(&dev_priv->drm,
13036                             "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13037                             pipe_config->gmch_pfit.control,
13038                             pipe_config->gmch_pfit.pgm_ratios,
13039                             pipe_config->gmch_pfit.lvds_border_bits);
13040         else
13041                 drm_dbg_kms(&dev_priv->drm,
13042                             "pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
13043                             pipe_config->pch_pfit.pos,
13044                             pipe_config->pch_pfit.size,
13045                             enableddisabled(pipe_config->pch_pfit.enabled),
13046                             yesno(pipe_config->pch_pfit.force_thru));
13047
13048         drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13049                     pipe_config->ips_enabled, pipe_config->double_wide);
13050
13051         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13052
13053         if (IS_CHERRYVIEW(dev_priv))
13054                 drm_dbg_kms(&dev_priv->drm,
13055                             "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13056                             pipe_config->cgm_mode, pipe_config->gamma_mode,
13057                             pipe_config->gamma_enable, pipe_config->csc_enable);
13058         else
13059                 drm_dbg_kms(&dev_priv->drm,
13060                             "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13061                             pipe_config->csc_mode, pipe_config->gamma_mode,
13062                             pipe_config->gamma_enable, pipe_config->csc_enable);
13063
13064         drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13065                     transcoder_name(pipe_config->mst_master_transcoder));
13066
13067 dump_planes:
13068         if (!state)
13069                 return;
13070
13071         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13072                 if (plane->pipe == crtc->pipe)
13073                         intel_dump_plane_state(plane_state);
13074         }
13075 }
13076
13077 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13078 {
13079         struct drm_device *dev = state->base.dev;
13080         struct drm_connector *connector;
13081         struct drm_connector_list_iter conn_iter;
13082         unsigned int used_ports = 0;
13083         unsigned int used_mst_ports = 0;
13084         bool ret = true;
13085
13086         /*
13087          * We're going to peek into connector->state,
13088          * hence connection_mutex must be held.
13089          */
13090         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13091
13092         /*
13093          * Walk the connector list instead of the encoder
13094          * list to detect the problem on ddi platforms
13095          * where there's just one encoder per digital port.
13096          */
13097         drm_connector_list_iter_begin(dev, &conn_iter);
13098         drm_for_each_connector_iter(connector, &conn_iter) {
13099                 struct drm_connector_state *connector_state;
13100                 struct intel_encoder *encoder;
13101
13102                 connector_state =
13103                         drm_atomic_get_new_connector_state(&state->base,
13104                                                            connector);
13105                 if (!connector_state)
13106                         connector_state = connector->state;
13107
13108                 if (!connector_state->best_encoder)
13109                         continue;
13110
13111                 encoder = to_intel_encoder(connector_state->best_encoder);
13112
13113                 drm_WARN_ON(dev, !connector_state->crtc);
13114
13115                 switch (encoder->type) {
13116                 case INTEL_OUTPUT_DDI:
13117                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13118                                 break;
13119                         /* else, fall through */
13120                 case INTEL_OUTPUT_DP:
13121                 case INTEL_OUTPUT_HDMI:
13122                 case INTEL_OUTPUT_EDP:
13123                         /* the same port mustn't appear more than once */
13124                         if (used_ports & BIT(encoder->port))
13125                                 ret = false;
13126
13127                         used_ports |= BIT(encoder->port);
13128                         break;
13129                 case INTEL_OUTPUT_DP_MST:
13130                         used_mst_ports |=
13131                                 1 << encoder->port;
13132                         break;
13133                 default:
13134                         break;
13135                 }
13136         }
13137         drm_connector_list_iter_end(&conn_iter);
13138
13139         /* can't mix MST and SST/HDMI on the same port */
13140         if (used_ports & used_mst_ports)
13141                 return false;
13142
13143         return ret;
13144 }
13145
13146 static void
13147 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13148 {
13149         intel_crtc_copy_color_blobs(crtc_state);
13150 }
13151
13152 static void
13153 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13154 {
13155         crtc_state->hw.enable = crtc_state->uapi.enable;
13156         crtc_state->hw.active = crtc_state->uapi.active;
13157         crtc_state->hw.mode = crtc_state->uapi.mode;
13158         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13159         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13160 }
13161
13162 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13163 {
13164         crtc_state->uapi.enable = crtc_state->hw.enable;
13165         crtc_state->uapi.active = crtc_state->hw.active;
13166         drm_WARN_ON(crtc_state->uapi.crtc->dev,
13167                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13168
13169         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13170
13171         /* copy color blobs to uapi */
13172         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13173                                   crtc_state->hw.degamma_lut);
13174         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13175                                   crtc_state->hw.gamma_lut);
13176         drm_property_replace_blob(&crtc_state->uapi.ctm,
13177                                   crtc_state->hw.ctm);
13178 }
13179
13180 static int
13181 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13182 {
13183         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13184         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13185         struct intel_crtc_state *saved_state;
13186
13187         saved_state = intel_crtc_state_alloc(crtc);
13188         if (!saved_state)
13189                 return -ENOMEM;
13190
13191         /* free the old crtc_state->hw members */
13192         intel_crtc_free_hw_state(crtc_state);
13193
13194         /* FIXME: before the switch to atomic started, a new pipe_config was
13195          * kzalloc'd. Code that depends on any field being zero should be
13196          * fixed, so that the crtc_state can be safely duplicated. For now,
13197          * only fields that are know to not cause problems are preserved. */
13198
13199         saved_state->uapi = crtc_state->uapi;
13200         saved_state->scaler_state = crtc_state->scaler_state;
13201         saved_state->shared_dpll = crtc_state->shared_dpll;
13202         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13203         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13204                sizeof(saved_state->icl_port_dplls));
13205         saved_state->crc_enabled = crtc_state->crc_enabled;
13206         if (IS_G4X(dev_priv) ||
13207             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13208                 saved_state->wm = crtc_state->wm;
13209
13210         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13211         kfree(saved_state);
13212
13213         intel_crtc_copy_uapi_to_hw_state(crtc_state);
13214
13215         return 0;
13216 }
13217
13218 static int
13219 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13220 {
13221         struct drm_crtc *crtc = pipe_config->uapi.crtc;
13222         struct drm_atomic_state *state = pipe_config->uapi.state;
13223         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13224         struct drm_connector *connector;
13225         struct drm_connector_state *connector_state;
13226         int base_bpp, ret, i;
13227         bool retry = true;
13228
13229         pipe_config->cpu_transcoder =
13230                 (enum transcoder) to_intel_crtc(crtc)->pipe;
13231
13232         /*
13233          * Sanitize sync polarity flags based on requested ones. If neither
13234          * positive or negative polarity is requested, treat this as meaning
13235          * negative polarity.
13236          */
13237         if (!(pipe_config->hw.adjusted_mode.flags &
13238               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13239                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13240
13241         if (!(pipe_config->hw.adjusted_mode.flags &
13242               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13243                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13244
13245         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13246                                         pipe_config);
13247         if (ret)
13248                 return ret;
13249
13250         base_bpp = pipe_config->pipe_bpp;
13251
13252         /*
13253          * Determine the real pipe dimensions. Note that stereo modes can
13254          * increase the actual pipe size due to the frame doubling and
13255          * insertion of additional space for blanks between the frame. This
13256          * is stored in the crtc timings. We use the requested mode to do this
13257          * computation to clearly distinguish it from the adjusted mode, which
13258          * can be changed by the connectors in the below retry loop.
13259          */
13260         drm_mode_get_hv_timing(&pipe_config->hw.mode,
13261                                &pipe_config->pipe_src_w,
13262                                &pipe_config->pipe_src_h);
13263
13264         for_each_new_connector_in_state(state, connector, connector_state, i) {
13265                 struct intel_encoder *encoder =
13266                         to_intel_encoder(connector_state->best_encoder);
13267
13268                 if (connector_state->crtc != crtc)
13269                         continue;
13270
13271                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13272                         drm_dbg_kms(&i915->drm,
13273                                     "rejecting invalid cloning configuration\n");
13274                         return -EINVAL;
13275                 }
13276
13277                 /*
13278                  * Determine output_types before calling the .compute_config()
13279                  * hooks so that the hooks can use this information safely.
13280                  */
13281                 if (encoder->compute_output_type)
13282                         pipe_config->output_types |=
13283                                 BIT(encoder->compute_output_type(encoder, pipe_config,
13284                                                                  connector_state));
13285                 else
13286                         pipe_config->output_types |= BIT(encoder->type);
13287         }
13288
13289 encoder_retry:
13290         /* Ensure the port clock defaults are reset when retrying. */
13291         pipe_config->port_clock = 0;
13292         pipe_config->pixel_multiplier = 1;
13293
13294         /* Fill in default crtc timings, allow encoders to overwrite them. */
13295         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13296                               CRTC_STEREO_DOUBLE);
13297
13298         /* Pass our mode to the connectors and the CRTC to give them a chance to
13299          * adjust it according to limitations or connector properties, and also
13300          * a chance to reject the mode entirely.
13301          */
13302         for_each_new_connector_in_state(state, connector, connector_state, i) {
13303                 struct intel_encoder *encoder =
13304                         to_intel_encoder(connector_state->best_encoder);
13305
13306                 if (connector_state->crtc != crtc)
13307                         continue;
13308
13309                 ret = encoder->compute_config(encoder, pipe_config,
13310                                               connector_state);
13311                 if (ret < 0) {
13312                         if (ret != -EDEADLK)
13313                                 drm_dbg_kms(&i915->drm,
13314                                             "Encoder config failure: %d\n",
13315                                             ret);
13316                         return ret;
13317                 }
13318         }
13319
13320         /* Set default port clock if not overwritten by the encoder. Needs to be
13321          * done afterwards in case the encoder adjusts the mode. */
13322         if (!pipe_config->port_clock)
13323                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13324                         * pipe_config->pixel_multiplier;
13325
13326         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13327         if (ret == -EDEADLK)
13328                 return ret;
13329         if (ret < 0) {
13330                 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13331                 return ret;
13332         }
13333
13334         if (ret == RETRY) {
13335                 if (drm_WARN(&i915->drm, !retry,
13336                              "loop in pipe configuration computation\n"))
13337                         return -EINVAL;
13338
13339                 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13340                 retry = false;
13341                 goto encoder_retry;
13342         }
13343
13344         /* Dithering seems to not pass-through bits correctly when it should, so
13345          * only enable it on 6bpc panels and when its not a compliance
13346          * test requesting 6bpc video pattern.
13347          */
13348         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13349                 !pipe_config->dither_force_disable;
13350         drm_dbg_kms(&i915->drm,
13351                     "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13352                     base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13353
13354         /*
13355          * Make drm_calc_timestamping_constants in
13356          * drm_atomic_helper_update_legacy_modeset_state() happy
13357          */
13358         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
13359
13360         return 0;
13361 }
13362
13363 static int
13364 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13365 {
13366         struct intel_atomic_state *state =
13367                 to_intel_atomic_state(crtc_state->uapi.state);
13368         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13369         struct drm_connector_state *conn_state;
13370         struct drm_connector *connector;
13371         int i;
13372
13373         for_each_new_connector_in_state(&state->base, connector,
13374                                         conn_state, i) {
13375                 struct intel_encoder *encoder =
13376                         to_intel_encoder(conn_state->best_encoder);
13377                 int ret;
13378
13379                 if (conn_state->crtc != &crtc->base ||
13380                     !encoder->compute_config_late)
13381                         continue;
13382
13383                 ret = encoder->compute_config_late(encoder, crtc_state,
13384                                                    conn_state);
13385                 if (ret)
13386                         return ret;
13387         }
13388
13389         return 0;
13390 }
13391
13392 bool intel_fuzzy_clock_check(int clock1, int clock2)
13393 {
13394         int diff;
13395
13396         if (clock1 == clock2)
13397                 return true;
13398
13399         if (!clock1 || !clock2)
13400                 return false;
13401
13402         diff = abs(clock1 - clock2);
13403
13404         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13405                 return true;
13406
13407         return false;
13408 }
13409
13410 static bool
13411 intel_compare_m_n(unsigned int m, unsigned int n,
13412                   unsigned int m2, unsigned int n2,
13413                   bool exact)
13414 {
13415         if (m == m2 && n == n2)
13416                 return true;
13417
13418         if (exact || !m || !n || !m2 || !n2)
13419                 return false;
13420
13421         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13422
13423         if (n > n2) {
13424                 while (n > n2) {
13425                         m2 <<= 1;
13426                         n2 <<= 1;
13427                 }
13428         } else if (n < n2) {
13429                 while (n < n2) {
13430                         m <<= 1;
13431                         n <<= 1;
13432                 }
13433         }
13434
13435         if (n != n2)
13436                 return false;
13437
13438         return intel_fuzzy_clock_check(m, m2);
13439 }
13440
13441 static bool
13442 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13443                        const struct intel_link_m_n *m2_n2,
13444                        bool exact)
13445 {
13446         return m_n->tu == m2_n2->tu &&
13447                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13448                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13449                 intel_compare_m_n(m_n->link_m, m_n->link_n,
13450                                   m2_n2->link_m, m2_n2->link_n, exact);
13451 }
13452
13453 static bool
13454 intel_compare_infoframe(const union hdmi_infoframe *a,
13455                         const union hdmi_infoframe *b)
13456 {
13457         return memcmp(a, b, sizeof(*a)) == 0;
13458 }
13459
13460 static void
13461 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13462                                bool fastset, const char *name,
13463                                const union hdmi_infoframe *a,
13464                                const union hdmi_infoframe *b)
13465 {
13466         if (fastset) {
13467                 if (!drm_debug_enabled(DRM_UT_KMS))
13468                         return;
13469
13470                 drm_dbg_kms(&dev_priv->drm,
13471                             "fastset mismatch in %s infoframe\n", name);
13472                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13473                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13474                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13475                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13476         } else {
13477                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13478                 drm_err(&dev_priv->drm, "expected:\n");
13479                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13480                 drm_err(&dev_priv->drm, "found:\n");
13481                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13482         }
13483 }
13484
13485 static void __printf(4, 5)
13486 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13487                      const char *name, const char *format, ...)
13488 {
13489         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13490         struct va_format vaf;
13491         va_list args;
13492
13493         va_start(args, format);
13494         vaf.fmt = format;
13495         vaf.va = &args;
13496
13497         if (fastset)
13498                 drm_dbg_kms(&i915->drm,
13499                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13500                             crtc->base.base.id, crtc->base.name, name, &vaf);
13501         else
13502                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13503                         crtc->base.base.id, crtc->base.name, name, &vaf);
13504
13505         va_end(args);
13506 }
13507
13508 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13509 {
13510         if (i915_modparams.fastboot != -1)
13511                 return i915_modparams.fastboot;
13512
13513         /* Enable fastboot by default on Skylake and newer */
13514         if (INTEL_GEN(dev_priv) >= 9)
13515                 return true;
13516
13517         /* Enable fastboot by default on VLV and CHV */
13518         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13519                 return true;
13520
13521         /* Disabled by default on all others */
13522         return false;
13523 }
13524
13525 static bool
13526 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13527                           const struct intel_crtc_state *pipe_config,
13528                           bool fastset)
13529 {
13530         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13531         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13532         bool ret = true;
13533         u32 bp_gamma = 0;
13534         bool fixup_inherited = fastset &&
13535                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
13536                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
13537
13538         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13539                 drm_dbg_kms(&dev_priv->drm,
13540                             "initial modeset and fastboot not set\n");
13541                 ret = false;
13542         }
13543
13544 #define PIPE_CONF_CHECK_X(name) do { \
13545         if (current_config->name != pipe_config->name) { \
13546                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13547                                      "(expected 0x%08x, found 0x%08x)", \
13548                                      current_config->name, \
13549                                      pipe_config->name); \
13550                 ret = false; \
13551         } \
13552 } while (0)
13553
13554 #define PIPE_CONF_CHECK_I(name) do { \
13555         if (current_config->name != pipe_config->name) { \
13556                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13557                                      "(expected %i, found %i)", \
13558                                      current_config->name, \
13559                                      pipe_config->name); \
13560                 ret = false; \
13561         } \
13562 } while (0)
13563
13564 #define PIPE_CONF_CHECK_BOOL(name) do { \
13565         if (current_config->name != pipe_config->name) { \
13566                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13567                                      "(expected %s, found %s)", \
13568                                      yesno(current_config->name), \
13569                                      yesno(pipe_config->name)); \
13570                 ret = false; \
13571         } \
13572 } while (0)
13573
13574 /*
13575  * Checks state where we only read out the enabling, but not the entire
13576  * state itself (like full infoframes or ELD for audio). These states
13577  * require a full modeset on bootup to fix up.
13578  */
13579 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13580         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13581                 PIPE_CONF_CHECK_BOOL(name); \
13582         } else { \
13583                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13584                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13585                                      yesno(current_config->name), \
13586                                      yesno(pipe_config->name)); \
13587                 ret = false; \
13588         } \
13589 } while (0)
13590
13591 #define PIPE_CONF_CHECK_P(name) do { \
13592         if (current_config->name != pipe_config->name) { \
13593                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13594                                      "(expected %p, found %p)", \
13595                                      current_config->name, \
13596                                      pipe_config->name); \
13597                 ret = false; \
13598         } \
13599 } while (0)
13600
13601 #define PIPE_CONF_CHECK_M_N(name) do { \
13602         if (!intel_compare_link_m_n(&current_config->name, \
13603                                     &pipe_config->name,\
13604                                     !fastset)) { \
13605                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13606                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13607                                      "found tu %i, gmch %i/%i link %i/%i)", \
13608                                      current_config->name.tu, \
13609                                      current_config->name.gmch_m, \
13610                                      current_config->name.gmch_n, \
13611                                      current_config->name.link_m, \
13612                                      current_config->name.link_n, \
13613                                      pipe_config->name.tu, \
13614                                      pipe_config->name.gmch_m, \
13615                                      pipe_config->name.gmch_n, \
13616                                      pipe_config->name.link_m, \
13617                                      pipe_config->name.link_n); \
13618                 ret = false; \
13619         } \
13620 } while (0)
13621
13622 /* This is required for BDW+ where there is only one set of registers for
13623  * switching between high and low RR.
13624  * This macro can be used whenever a comparison has to be made between one
13625  * hw state and multiple sw state variables.
13626  */
13627 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13628         if (!intel_compare_link_m_n(&current_config->name, \
13629                                     &pipe_config->name, !fastset) && \
13630             !intel_compare_link_m_n(&current_config->alt_name, \
13631                                     &pipe_config->name, !fastset)) { \
13632                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13633                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13634                                      "or tu %i gmch %i/%i link %i/%i, " \
13635                                      "found tu %i, gmch %i/%i link %i/%i)", \
13636                                      current_config->name.tu, \
13637                                      current_config->name.gmch_m, \
13638                                      current_config->name.gmch_n, \
13639                                      current_config->name.link_m, \
13640                                      current_config->name.link_n, \
13641                                      current_config->alt_name.tu, \
13642                                      current_config->alt_name.gmch_m, \
13643                                      current_config->alt_name.gmch_n, \
13644                                      current_config->alt_name.link_m, \
13645                                      current_config->alt_name.link_n, \
13646                                      pipe_config->name.tu, \
13647                                      pipe_config->name.gmch_m, \
13648                                      pipe_config->name.gmch_n, \
13649                                      pipe_config->name.link_m, \
13650                                      pipe_config->name.link_n); \
13651                 ret = false; \
13652         } \
13653 } while (0)
13654
13655 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13656         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13657                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13658                                      "(%x) (expected %i, found %i)", \
13659                                      (mask), \
13660                                      current_config->name & (mask), \
13661                                      pipe_config->name & (mask)); \
13662                 ret = false; \
13663         } \
13664 } while (0)
13665
13666 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13667         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13668                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13669                                      "(expected %i, found %i)", \
13670                                      current_config->name, \
13671                                      pipe_config->name); \
13672                 ret = false; \
13673         } \
13674 } while (0)
13675
13676 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13677         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13678                                      &pipe_config->infoframes.name)) { \
13679                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13680                                                &current_config->infoframes.name, \
13681                                                &pipe_config->infoframes.name); \
13682                 ret = false; \
13683         } \
13684 } while (0)
13685
13686 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13687         if (current_config->name1 != pipe_config->name1) { \
13688                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13689                                 "(expected %i, found %i, won't compare lut values)", \
13690                                 current_config->name1, \
13691                                 pipe_config->name1); \
13692                 ret = false;\
13693         } else { \
13694                 if (!intel_color_lut_equal(current_config->name2, \
13695                                         pipe_config->name2, pipe_config->name1, \
13696                                         bit_precision)) { \
13697                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13698                                         "hw_state doesn't match sw_state"); \
13699                         ret = false; \
13700                 } \
13701         } \
13702 } while (0)
13703
13704 #define PIPE_CONF_QUIRK(quirk) \
13705         ((current_config->quirks | pipe_config->quirks) & (quirk))
13706
13707         PIPE_CONF_CHECK_I(cpu_transcoder);
13708
13709         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13710         PIPE_CONF_CHECK_I(fdi_lanes);
13711         PIPE_CONF_CHECK_M_N(fdi_m_n);
13712
13713         PIPE_CONF_CHECK_I(lane_count);
13714         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13715
13716         if (INTEL_GEN(dev_priv) < 8) {
13717                 PIPE_CONF_CHECK_M_N(dp_m_n);
13718
13719                 if (current_config->has_drrs)
13720                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13721         } else
13722                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13723
13724         PIPE_CONF_CHECK_X(output_types);
13725
13726         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13727         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13728         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13729         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13730         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13731         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13732
13733         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13734         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13735         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13736         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13737         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13738         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13739
13740         PIPE_CONF_CHECK_I(pixel_multiplier);
13741         PIPE_CONF_CHECK_I(output_format);
13742         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13743         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13744             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13745                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13746
13747         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13748         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13749         PIPE_CONF_CHECK_BOOL(has_infoframe);
13750         PIPE_CONF_CHECK_BOOL(fec_enable);
13751
13752         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13753
13754         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13755                               DRM_MODE_FLAG_INTERLACE);
13756
13757         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13758                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13759                                       DRM_MODE_FLAG_PHSYNC);
13760                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13761                                       DRM_MODE_FLAG_NHSYNC);
13762                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13763                                       DRM_MODE_FLAG_PVSYNC);
13764                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13765                                       DRM_MODE_FLAG_NVSYNC);
13766         }
13767
13768         PIPE_CONF_CHECK_X(gmch_pfit.control);
13769         /* pfit ratios are autocomputed by the hw on gen4+ */
13770         if (INTEL_GEN(dev_priv) < 4)
13771                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13772         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13773
13774         /*
13775          * Changing the EDP transcoder input mux
13776          * (A_ONOFF vs. A_ON) requires a full modeset.
13777          */
13778         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13779
13780         if (!fastset) {
13781                 PIPE_CONF_CHECK_I(pipe_src_w);
13782                 PIPE_CONF_CHECK_I(pipe_src_h);
13783
13784                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13785                 if (current_config->pch_pfit.enabled) {
13786                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13787                         PIPE_CONF_CHECK_X(pch_pfit.size);
13788                 }
13789
13790                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13791                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13792
13793                 PIPE_CONF_CHECK_X(gamma_mode);
13794                 if (IS_CHERRYVIEW(dev_priv))
13795                         PIPE_CONF_CHECK_X(cgm_mode);
13796                 else
13797                         PIPE_CONF_CHECK_X(csc_mode);
13798                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13799                 PIPE_CONF_CHECK_BOOL(csc_enable);
13800
13801                 PIPE_CONF_CHECK_I(linetime);
13802                 PIPE_CONF_CHECK_I(ips_linetime);
13803
13804                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13805                 if (bp_gamma)
13806                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13807         }
13808
13809         PIPE_CONF_CHECK_BOOL(double_wide);
13810
13811         PIPE_CONF_CHECK_P(shared_dpll);
13812         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13813         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13814         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13815         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13816         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13817         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13818         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13819         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13820         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13821         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13822         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13823         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13824         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13825         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13826         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13827         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13828         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13829         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13830         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13831         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13832         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13833         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13834         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13835         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13836         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13837         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13838         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13839         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13840         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13841         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13842         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13843
13844         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13845         PIPE_CONF_CHECK_X(dsi_pll.div);
13846
13847         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13848                 PIPE_CONF_CHECK_I(pipe_bpp);
13849
13850         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13851         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13852
13853         PIPE_CONF_CHECK_I(min_voltage_level);
13854
13855         PIPE_CONF_CHECK_X(infoframes.enable);
13856         PIPE_CONF_CHECK_X(infoframes.gcp);
13857         PIPE_CONF_CHECK_INFOFRAME(avi);
13858         PIPE_CONF_CHECK_INFOFRAME(spd);
13859         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13860         PIPE_CONF_CHECK_INFOFRAME(drm);
13861
13862         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
13863         PIPE_CONF_CHECK_I(master_transcoder);
13864
13865         PIPE_CONF_CHECK_I(dsc.compression_enable);
13866         PIPE_CONF_CHECK_I(dsc.dsc_split);
13867         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
13868
13869         PIPE_CONF_CHECK_I(mst_master_transcoder);
13870
13871 #undef PIPE_CONF_CHECK_X
13872 #undef PIPE_CONF_CHECK_I
13873 #undef PIPE_CONF_CHECK_BOOL
13874 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13875 #undef PIPE_CONF_CHECK_P
13876 #undef PIPE_CONF_CHECK_FLAGS
13877 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13878 #undef PIPE_CONF_CHECK_COLOR_LUT
13879 #undef PIPE_CONF_QUIRK
13880
13881         return ret;
13882 }
13883
13884 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13885                                            const struct intel_crtc_state *pipe_config)
13886 {
13887         if (pipe_config->has_pch_encoder) {
13888                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13889                                                             &pipe_config->fdi_m_n);
13890                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13891
13892                 /*
13893                  * FDI already provided one idea for the dotclock.
13894                  * Yell if the encoder disagrees.
13895                  */
13896                 drm_WARN(&dev_priv->drm,
13897                          !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13898                          "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13899                          fdi_dotclock, dotclock);
13900         }
13901 }
13902
13903 static void verify_wm_state(struct intel_crtc *crtc,
13904                             struct intel_crtc_state *new_crtc_state)
13905 {
13906         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13907         struct skl_hw_state {
13908                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13909                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13910                 struct skl_pipe_wm wm;
13911         } *hw;
13912         struct skl_pipe_wm *sw_wm;
13913         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13914         u8 hw_enabled_slices;
13915         const enum pipe pipe = crtc->pipe;
13916         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13917
13918         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13919                 return;
13920
13921         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13922         if (!hw)
13923                 return;
13924
13925         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13926         sw_wm = &new_crtc_state->wm.skl.optimal;
13927
13928         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13929
13930         hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
13931
13932         if (INTEL_GEN(dev_priv) >= 11 &&
13933             hw_enabled_slices != dev_priv->enabled_dbuf_slices_mask)
13934                 drm_err(&dev_priv->drm,
13935                         "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
13936                         dev_priv->enabled_dbuf_slices_mask,
13937                         hw_enabled_slices);
13938
13939         /* planes */
13940         for_each_universal_plane(dev_priv, pipe, plane) {
13941                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13942
13943                 hw_plane_wm = &hw->wm.planes[plane];
13944                 sw_plane_wm = &sw_wm->planes[plane];
13945
13946                 /* Watermarks */
13947                 for (level = 0; level <= max_level; level++) {
13948                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13949                                                 &sw_plane_wm->wm[level]))
13950                                 continue;
13951
13952                         drm_err(&dev_priv->drm,
13953                                 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13954                                 pipe_name(pipe), plane + 1, level,
13955                                 sw_plane_wm->wm[level].plane_en,
13956                                 sw_plane_wm->wm[level].plane_res_b,
13957                                 sw_plane_wm->wm[level].plane_res_l,
13958                                 hw_plane_wm->wm[level].plane_en,
13959                                 hw_plane_wm->wm[level].plane_res_b,
13960                                 hw_plane_wm->wm[level].plane_res_l);
13961                 }
13962
13963                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13964                                          &sw_plane_wm->trans_wm)) {
13965                         drm_err(&dev_priv->drm,
13966                                 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13967                                 pipe_name(pipe), plane + 1,
13968                                 sw_plane_wm->trans_wm.plane_en,
13969                                 sw_plane_wm->trans_wm.plane_res_b,
13970                                 sw_plane_wm->trans_wm.plane_res_l,
13971                                 hw_plane_wm->trans_wm.plane_en,
13972                                 hw_plane_wm->trans_wm.plane_res_b,
13973                                 hw_plane_wm->trans_wm.plane_res_l);
13974                 }
13975
13976                 /* DDB */
13977                 hw_ddb_entry = &hw->ddb_y[plane];
13978                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13979
13980                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13981                         drm_err(&dev_priv->drm,
13982                                 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13983                                 pipe_name(pipe), plane + 1,
13984                                 sw_ddb_entry->start, sw_ddb_entry->end,
13985                                 hw_ddb_entry->start, hw_ddb_entry->end);
13986                 }
13987         }
13988
13989         /*
13990          * cursor
13991          * If the cursor plane isn't active, we may not have updated it's ddb
13992          * allocation. In that case since the ddb allocation will be updated
13993          * once the plane becomes visible, we can skip this check
13994          */
13995         if (1) {
13996                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13997
13998                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13999                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14000
14001                 /* Watermarks */
14002                 for (level = 0; level <= max_level; level++) {
14003                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14004                                                 &sw_plane_wm->wm[level]))
14005                                 continue;
14006
14007                         drm_err(&dev_priv->drm,
14008                                 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14009                                 pipe_name(pipe), level,
14010                                 sw_plane_wm->wm[level].plane_en,
14011                                 sw_plane_wm->wm[level].plane_res_b,
14012                                 sw_plane_wm->wm[level].plane_res_l,
14013                                 hw_plane_wm->wm[level].plane_en,
14014                                 hw_plane_wm->wm[level].plane_res_b,
14015                                 hw_plane_wm->wm[level].plane_res_l);
14016                 }
14017
14018                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14019                                          &sw_plane_wm->trans_wm)) {
14020                         drm_err(&dev_priv->drm,
14021                                 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14022                                 pipe_name(pipe),
14023                                 sw_plane_wm->trans_wm.plane_en,
14024                                 sw_plane_wm->trans_wm.plane_res_b,
14025                                 sw_plane_wm->trans_wm.plane_res_l,
14026                                 hw_plane_wm->trans_wm.plane_en,
14027                                 hw_plane_wm->trans_wm.plane_res_b,
14028                                 hw_plane_wm->trans_wm.plane_res_l);
14029                 }
14030
14031                 /* DDB */
14032                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14033                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14034
14035                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14036                         drm_err(&dev_priv->drm,
14037                                 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14038                                 pipe_name(pipe),
14039                                 sw_ddb_entry->start, sw_ddb_entry->end,
14040                                 hw_ddb_entry->start, hw_ddb_entry->end);
14041                 }
14042         }
14043
14044         kfree(hw);
14045 }
14046
14047 static void
14048 verify_connector_state(struct intel_atomic_state *state,
14049                        struct intel_crtc *crtc)
14050 {
14051         struct drm_connector *connector;
14052         struct drm_connector_state *new_conn_state;
14053         int i;
14054
14055         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14056                 struct drm_encoder *encoder = connector->encoder;
14057                 struct intel_crtc_state *crtc_state = NULL;
14058
14059                 if (new_conn_state->crtc != &crtc->base)
14060                         continue;
14061
14062                 if (crtc)
14063                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14064
14065                 intel_connector_verify_state(crtc_state, new_conn_state);
14066
14067                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14068                      "connector's atomic encoder doesn't match legacy encoder\n");
14069         }
14070 }
14071
14072 static void
14073 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14074 {
14075         struct intel_encoder *encoder;
14076         struct drm_connector *connector;
14077         struct drm_connector_state *old_conn_state, *new_conn_state;
14078         int i;
14079
14080         for_each_intel_encoder(&dev_priv->drm, encoder) {
14081                 bool enabled = false, found = false;
14082                 enum pipe pipe;
14083
14084                 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14085                             encoder->base.base.id,
14086                             encoder->base.name);
14087
14088                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14089                                                    new_conn_state, i) {
14090                         if (old_conn_state->best_encoder == &encoder->base)
14091                                 found = true;
14092
14093                         if (new_conn_state->best_encoder != &encoder->base)
14094                                 continue;
14095                         found = enabled = true;
14096
14097                         I915_STATE_WARN(new_conn_state->crtc !=
14098                                         encoder->base.crtc,
14099                              "connector's crtc doesn't match encoder crtc\n");
14100                 }
14101
14102                 if (!found)
14103                         continue;
14104
14105                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14106                      "encoder's enabled state mismatch "
14107                      "(expected %i, found %i)\n",
14108                      !!encoder->base.crtc, enabled);
14109
14110                 if (!encoder->base.crtc) {
14111                         bool active;
14112
14113                         active = encoder->get_hw_state(encoder, &pipe);
14114                         I915_STATE_WARN(active,
14115                              "encoder detached but still enabled on pipe %c.\n",
14116                              pipe_name(pipe));
14117                 }
14118         }
14119 }
14120
14121 static void
14122 verify_crtc_state(struct intel_crtc *crtc,
14123                   struct intel_crtc_state *old_crtc_state,
14124                   struct intel_crtc_state *new_crtc_state)
14125 {
14126         struct drm_device *dev = crtc->base.dev;
14127         struct drm_i915_private *dev_priv = to_i915(dev);
14128         struct intel_encoder *encoder;
14129         struct intel_crtc_state *pipe_config = old_crtc_state;
14130         struct drm_atomic_state *state = old_crtc_state->uapi.state;
14131         bool active;
14132
14133         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14134         intel_crtc_free_hw_state(old_crtc_state);
14135         intel_crtc_state_reset(old_crtc_state, crtc);
14136         old_crtc_state->uapi.state = state;
14137
14138         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14139                     crtc->base.name);
14140
14141         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
14142
14143         /* we keep both pipes enabled on 830 */
14144         if (IS_I830(dev_priv))
14145                 active = new_crtc_state->hw.active;
14146
14147         I915_STATE_WARN(new_crtc_state->hw.active != active,
14148                         "crtc active state doesn't match with hw state "
14149                         "(expected %i, found %i)\n",
14150                         new_crtc_state->hw.active, active);
14151
14152         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14153                         "transitional active state does not match atomic hw state "
14154                         "(expected %i, found %i)\n",
14155                         new_crtc_state->hw.active, crtc->active);
14156
14157         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14158                 enum pipe pipe;
14159
14160                 active = encoder->get_hw_state(encoder, &pipe);
14161                 I915_STATE_WARN(active != new_crtc_state->hw.active,
14162                                 "[ENCODER:%i] active %i with crtc active %i\n",
14163                                 encoder->base.base.id, active,
14164                                 new_crtc_state->hw.active);
14165
14166                 I915_STATE_WARN(active && crtc->pipe != pipe,
14167                                 "Encoder connected to wrong pipe %c\n",
14168                                 pipe_name(pipe));
14169
14170                 if (active)
14171                         encoder->get_config(encoder, pipe_config);
14172         }
14173
14174         intel_crtc_compute_pixel_rate(pipe_config);
14175
14176         if (!new_crtc_state->hw.active)
14177                 return;
14178
14179         intel_pipe_config_sanity_check(dev_priv, pipe_config);
14180
14181         if (!intel_pipe_config_compare(new_crtc_state,
14182                                        pipe_config, false)) {
14183                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14184                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14185                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14186         }
14187 }
14188
14189 static void
14190 intel_verify_planes(struct intel_atomic_state *state)
14191 {
14192         struct intel_plane *plane;
14193         const struct intel_plane_state *plane_state;
14194         int i;
14195
14196         for_each_new_intel_plane_in_state(state, plane,
14197                                           plane_state, i)
14198                 assert_plane(plane, plane_state->planar_slave ||
14199                              plane_state->uapi.visible);
14200 }
14201
14202 static void
14203 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14204                          struct intel_shared_dpll *pll,
14205                          struct intel_crtc *crtc,
14206                          struct intel_crtc_state *new_crtc_state)
14207 {
14208         struct intel_dpll_hw_state dpll_hw_state;
14209         unsigned int crtc_mask;
14210         bool active;
14211
14212         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14213
14214         drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14215
14216         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14217
14218         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14219                 I915_STATE_WARN(!pll->on && pll->active_mask,
14220                      "pll in active use but not on in sw tracking\n");
14221                 I915_STATE_WARN(pll->on && !pll->active_mask,
14222                      "pll is on but not used by any active crtc\n");
14223                 I915_STATE_WARN(pll->on != active,
14224                      "pll on state mismatch (expected %i, found %i)\n",
14225                      pll->on, active);
14226         }
14227
14228         if (!crtc) {
14229                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14230                                 "more active pll users than references: %x vs %x\n",
14231                                 pll->active_mask, pll->state.crtc_mask);
14232
14233                 return;
14234         }
14235
14236         crtc_mask = drm_crtc_mask(&crtc->base);
14237
14238         if (new_crtc_state->hw.active)
14239                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14240                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14241                                 pipe_name(crtc->pipe), pll->active_mask);
14242         else
14243                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14244                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14245                                 pipe_name(crtc->pipe), pll->active_mask);
14246
14247         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14248                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14249                         crtc_mask, pll->state.crtc_mask);
14250
14251         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14252                                           &dpll_hw_state,
14253                                           sizeof(dpll_hw_state)),
14254                         "pll hw state mismatch\n");
14255 }
14256
14257 static void
14258 verify_shared_dpll_state(struct intel_crtc *crtc,
14259                          struct intel_crtc_state *old_crtc_state,
14260                          struct intel_crtc_state *new_crtc_state)
14261 {
14262         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14263
14264         if (new_crtc_state->shared_dpll)
14265                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14266
14267         if (old_crtc_state->shared_dpll &&
14268             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14269                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14270                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14271
14272                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14273                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14274                                 pipe_name(crtc->pipe));
14275                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14276                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14277                                 pipe_name(crtc->pipe));
14278         }
14279 }
14280
14281 static void
14282 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14283                           struct intel_atomic_state *state,
14284                           struct intel_crtc_state *old_crtc_state,
14285                           struct intel_crtc_state *new_crtc_state)
14286 {
14287         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14288                 return;
14289
14290         verify_wm_state(crtc, new_crtc_state);
14291         verify_connector_state(state, crtc);
14292         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14293         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14294 }
14295
14296 static void
14297 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14298 {
14299         int i;
14300
14301         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14302                 verify_single_dpll_state(dev_priv,
14303                                          &dev_priv->dpll.shared_dplls[i],
14304                                          NULL, NULL);
14305 }
14306
14307 static void
14308 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14309                               struct intel_atomic_state *state)
14310 {
14311         verify_encoder_state(dev_priv, state);
14312         verify_connector_state(state, NULL);
14313         verify_disabled_dpll_state(dev_priv);
14314 }
14315
14316 static void
14317 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14318 {
14319         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14320         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14321         const struct drm_display_mode *adjusted_mode =
14322                 &crtc_state->hw.adjusted_mode;
14323
14324         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14325
14326         /*
14327          * The scanline counter increments at the leading edge of hsync.
14328          *
14329          * On most platforms it starts counting from vtotal-1 on the
14330          * first active line. That means the scanline counter value is
14331          * always one less than what we would expect. Ie. just after
14332          * start of vblank, which also occurs at start of hsync (on the
14333          * last active line), the scanline counter will read vblank_start-1.
14334          *
14335          * On gen2 the scanline counter starts counting from 1 instead
14336          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14337          * to keep the value positive), instead of adding one.
14338          *
14339          * On HSW+ the behaviour of the scanline counter depends on the output
14340          * type. For DP ports it behaves like most other platforms, but on HDMI
14341          * there's an extra 1 line difference. So we need to add two instead of
14342          * one to the value.
14343          *
14344          * On VLV/CHV DSI the scanline counter would appear to increment
14345          * approx. 1/3 of a scanline before start of vblank. Unfortunately
14346          * that means we can't tell whether we're in vblank or not while
14347          * we're on that particular line. We must still set scanline_offset
14348          * to 1 so that the vblank timestamps come out correct when we query
14349          * the scanline counter from within the vblank interrupt handler.
14350          * However if queried just before the start of vblank we'll get an
14351          * answer that's slightly in the future.
14352          */
14353         if (IS_GEN(dev_priv, 2)) {
14354                 int vtotal;
14355
14356                 vtotal = adjusted_mode->crtc_vtotal;
14357                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14358                         vtotal /= 2;
14359
14360                 crtc->scanline_offset = vtotal - 1;
14361         } else if (HAS_DDI(dev_priv) &&
14362                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14363                 crtc->scanline_offset = 2;
14364         } else {
14365                 crtc->scanline_offset = 1;
14366         }
14367 }
14368
14369 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14370 {
14371         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14372         struct intel_crtc_state *new_crtc_state;
14373         struct intel_crtc *crtc;
14374         int i;
14375
14376         if (!dev_priv->display.crtc_compute_clock)
14377                 return;
14378
14379         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14380                 if (!needs_modeset(new_crtc_state))
14381                         continue;
14382
14383                 intel_release_shared_dplls(state, crtc);
14384         }
14385 }
14386
14387 /*
14388  * This implements the workaround described in the "notes" section of the mode
14389  * set sequence documentation. When going from no pipes or single pipe to
14390  * multiple pipes, and planes are enabled after the pipe, we need to wait at
14391  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14392  */
14393 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14394 {
14395         struct intel_crtc_state *crtc_state;
14396         struct intel_crtc *crtc;
14397         struct intel_crtc_state *first_crtc_state = NULL;
14398         struct intel_crtc_state *other_crtc_state = NULL;
14399         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14400         int i;
14401
14402         /* look at all crtc's that are going to be enabled in during modeset */
14403         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14404                 if (!crtc_state->hw.active ||
14405                     !needs_modeset(crtc_state))
14406                         continue;
14407
14408                 if (first_crtc_state) {
14409                         other_crtc_state = crtc_state;
14410                         break;
14411                 } else {
14412                         first_crtc_state = crtc_state;
14413                         first_pipe = crtc->pipe;
14414                 }
14415         }
14416
14417         /* No workaround needed? */
14418         if (!first_crtc_state)
14419                 return 0;
14420
14421         /* w/a possibly needed, check how many crtc's are already enabled. */
14422         for_each_intel_crtc(state->base.dev, crtc) {
14423                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14424                 if (IS_ERR(crtc_state))
14425                         return PTR_ERR(crtc_state);
14426
14427                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14428
14429                 if (!crtc_state->hw.active ||
14430                     needs_modeset(crtc_state))
14431                         continue;
14432
14433                 /* 2 or more enabled crtcs means no need for w/a */
14434                 if (enabled_pipe != INVALID_PIPE)
14435                         return 0;
14436
14437                 enabled_pipe = crtc->pipe;
14438         }
14439
14440         if (enabled_pipe != INVALID_PIPE)
14441                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14442         else if (other_crtc_state)
14443                 other_crtc_state->hsw_workaround_pipe = first_pipe;
14444
14445         return 0;
14446 }
14447
14448 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14449                            u8 active_pipes)
14450 {
14451         const struct intel_crtc_state *crtc_state;
14452         struct intel_crtc *crtc;
14453         int i;
14454
14455         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14456                 if (crtc_state->hw.active)
14457                         active_pipes |= BIT(crtc->pipe);
14458                 else
14459                         active_pipes &= ~BIT(crtc->pipe);
14460         }
14461
14462         return active_pipes;
14463 }
14464
14465 static int intel_modeset_checks(struct intel_atomic_state *state)
14466 {
14467         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14468         int ret;
14469
14470         state->modeset = true;
14471         state->active_pipes = intel_calc_active_pipes(state, dev_priv->active_pipes);
14472
14473         state->active_pipe_changes = state->active_pipes ^ dev_priv->active_pipes;
14474
14475         if (state->active_pipe_changes) {
14476                 ret = _intel_atomic_lock_global_state(state);
14477                 if (ret)
14478                         return ret;
14479         }
14480
14481         ret = intel_modeset_calc_cdclk(state);
14482         if (ret)
14483                 return ret;
14484
14485         intel_modeset_clear_plls(state);
14486
14487         if (IS_HASWELL(dev_priv))
14488                 return hsw_mode_set_planes_workaround(state);
14489
14490         return 0;
14491 }
14492
14493 /*
14494  * Handle calculation of various watermark data at the end of the atomic check
14495  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14496  * handlers to ensure that all derived state has been updated.
14497  */
14498 static int calc_watermark_data(struct intel_atomic_state *state)
14499 {
14500         struct drm_device *dev = state->base.dev;
14501         struct drm_i915_private *dev_priv = to_i915(dev);
14502
14503         /* Is there platform-specific watermark information to calculate? */
14504         if (dev_priv->display.compute_global_watermarks)
14505                 return dev_priv->display.compute_global_watermarks(state);
14506
14507         return 0;
14508 }
14509
14510 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14511                                      struct intel_crtc_state *new_crtc_state)
14512 {
14513         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14514                 return;
14515
14516         new_crtc_state->uapi.mode_changed = false;
14517         new_crtc_state->update_pipe = true;
14518 }
14519
14520 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14521                                     struct intel_crtc_state *new_crtc_state)
14522 {
14523         /*
14524          * If we're not doing the full modeset we want to
14525          * keep the current M/N values as they may be
14526          * sufficiently different to the computed values
14527          * to cause problems.
14528          *
14529          * FIXME: should really copy more fuzzy state here
14530          */
14531         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14532         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14533         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14534         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14535 }
14536
14537 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14538                                           struct intel_crtc *crtc,
14539                                           u8 plane_ids_mask)
14540 {
14541         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14542         struct intel_plane *plane;
14543
14544         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14545                 struct intel_plane_state *plane_state;
14546
14547                 if ((plane_ids_mask & BIT(plane->id)) == 0)
14548                         continue;
14549
14550                 plane_state = intel_atomic_get_plane_state(state, plane);
14551                 if (IS_ERR(plane_state))
14552                         return PTR_ERR(plane_state);
14553         }
14554
14555         return 0;
14556 }
14557
14558 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14559 {
14560         /* See {hsw,vlv,ivb}_plane_ratio() */
14561         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14562                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14563                 IS_IVYBRIDGE(dev_priv);
14564 }
14565
14566 static int intel_atomic_check_planes(struct intel_atomic_state *state,
14567                                      bool *need_cdclk_calc)
14568 {
14569         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14570         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14571         struct intel_plane_state *plane_state;
14572         struct intel_plane *plane;
14573         struct intel_crtc *crtc;
14574         int i, ret;
14575
14576         ret = icl_add_linked_planes(state);
14577         if (ret)
14578                 return ret;
14579
14580         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14581                 ret = intel_plane_atomic_check(state, plane);
14582                 if (ret) {
14583                         drm_dbg_atomic(&dev_priv->drm,
14584                                        "[PLANE:%d:%s] atomic driver check failed\n",
14585                                        plane->base.base.id, plane->base.name);
14586                         return ret;
14587                 }
14588         }
14589
14590         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14591                                             new_crtc_state, i) {
14592                 u8 old_active_planes, new_active_planes;
14593
14594                 ret = icl_check_nv12_planes(new_crtc_state);
14595                 if (ret)
14596                         return ret;
14597
14598                 /*
14599                  * On some platforms the number of active planes affects
14600                  * the planes' minimum cdclk calculation. Add such planes
14601                  * to the state before we compute the minimum cdclk.
14602                  */
14603                 if (!active_planes_affects_min_cdclk(dev_priv))
14604                         continue;
14605
14606                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14607                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14608
14609                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14610                         continue;
14611
14612                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14613                 if (ret)
14614                         return ret;
14615         }
14616
14617         /*
14618          * active_planes bitmask has been updated, and potentially
14619          * affected planes are part of the state. We can now
14620          * compute the minimum cdclk for each plane.
14621          */
14622         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14623                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14624                 if (ret)
14625                         return ret;
14626         }
14627
14628         return 0;
14629 }
14630
14631 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14632 {
14633         struct intel_crtc_state *crtc_state;
14634         struct intel_crtc *crtc;
14635         int i;
14636
14637         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14638                 int ret = intel_crtc_atomic_check(state, crtc);
14639                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14640                 if (ret) {
14641                         drm_dbg_atomic(&i915->drm,
14642                                        "[CRTC:%d:%s] atomic driver check failed\n",
14643                                        crtc->base.base.id, crtc->base.name);
14644                         return ret;
14645                 }
14646         }
14647
14648         return 0;
14649 }
14650
14651 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14652                                                u8 transcoders)
14653 {
14654         const struct intel_crtc_state *new_crtc_state;
14655         struct intel_crtc *crtc;
14656         int i;
14657
14658         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14659                 if (new_crtc_state->hw.enable &&
14660                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14661                     needs_modeset(new_crtc_state))
14662                         return true;
14663         }
14664
14665         return false;
14666 }
14667
14668 /**
14669  * intel_atomic_check - validate state object
14670  * @dev: drm device
14671  * @_state: state to validate
14672  */
14673 static int intel_atomic_check(struct drm_device *dev,
14674                               struct drm_atomic_state *_state)
14675 {
14676         struct drm_i915_private *dev_priv = to_i915(dev);
14677         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14678         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14679         struct intel_cdclk_state *new_cdclk_state;
14680         struct intel_crtc *crtc;
14681         int ret, i;
14682         bool any_ms = false;
14683
14684         /* Catch I915_MODE_FLAG_INHERITED */
14685         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14686                                             new_crtc_state, i) {
14687                 if (new_crtc_state->uapi.mode.private_flags !=
14688                     old_crtc_state->uapi.mode.private_flags)
14689                         new_crtc_state->uapi.mode_changed = true;
14690         }
14691
14692         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14693         if (ret)
14694                 goto fail;
14695
14696         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14697                                             new_crtc_state, i) {
14698                 if (!needs_modeset(new_crtc_state)) {
14699                         /* Light copy */
14700                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14701
14702                         continue;
14703                 }
14704
14705                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14706                 if (ret)
14707                         goto fail;
14708
14709                 if (!new_crtc_state->hw.enable)
14710                         continue;
14711
14712                 ret = intel_modeset_pipe_config(new_crtc_state);
14713                 if (ret)
14714                         goto fail;
14715         }
14716
14717         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14718                                             new_crtc_state, i) {
14719                 if (!needs_modeset(new_crtc_state))
14720                         continue;
14721
14722                 ret = intel_modeset_pipe_config_late(new_crtc_state);
14723                 if (ret)
14724                         goto fail;
14725
14726                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14727         }
14728
14729         /**
14730          * Check if fastset is allowed by external dependencies like other
14731          * pipes and transcoders.
14732          *
14733          * Right now it only forces a fullmodeset when the MST master
14734          * transcoder did not changed but the pipe of the master transcoder
14735          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
14736          * in case of port synced crtcs, if one of the synced crtcs
14737          * needs a full modeset, all other synced crtcs should be
14738          * forced a full modeset.
14739          */
14740         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14741                 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
14742                         continue;
14743
14744                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
14745                         enum transcoder master = new_crtc_state->mst_master_transcoder;
14746
14747                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
14748                                 new_crtc_state->uapi.mode_changed = true;
14749                                 new_crtc_state->update_pipe = false;
14750                         }
14751                 }
14752
14753                 if (is_trans_port_sync_mode(new_crtc_state)) {
14754                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
14755
14756                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
14757                                 trans |= BIT(new_crtc_state->master_transcoder);
14758
14759                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
14760                                 new_crtc_state->uapi.mode_changed = true;
14761                                 new_crtc_state->update_pipe = false;
14762                         }
14763                 }
14764         }
14765
14766         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14767                                             new_crtc_state, i) {
14768                 if (needs_modeset(new_crtc_state)) {
14769                         any_ms = true;
14770                         continue;
14771                 }
14772
14773                 if (!new_crtc_state->update_pipe)
14774                         continue;
14775
14776                 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
14777         }
14778
14779         if (any_ms && !check_digital_port_conflicts(state)) {
14780                 drm_dbg_kms(&dev_priv->drm,
14781                             "rejecting conflicting digital port configuration\n");
14782                 ret = EINVAL;
14783                 goto fail;
14784         }
14785
14786         ret = drm_dp_mst_atomic_check(&state->base);
14787         if (ret)
14788                 goto fail;
14789
14790         ret = intel_atomic_check_planes(state, &any_ms);
14791         if (ret)
14792                 goto fail;
14793
14794         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14795         if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
14796                 any_ms = true;
14797
14798         /*
14799          * distrust_bios_wm will force a full dbuf recomputation
14800          * but the hardware state will only get updated accordingly
14801          * if state->modeset==true. Hence distrust_bios_wm==true &&
14802          * state->modeset==false is an invalid combination which
14803          * would cause the hardware and software dbuf state to get
14804          * out of sync. We must prevent that.
14805          *
14806          * FIXME clean up this mess and introduce better
14807          * state tracking for dbuf.
14808          */
14809         if (dev_priv->wm.distrust_bios_wm)
14810                 any_ms = true;
14811
14812         if (any_ms) {
14813                 ret = intel_modeset_checks(state);
14814                 if (ret)
14815                         goto fail;
14816         }
14817
14818         ret = intel_atomic_check_crtcs(state);
14819         if (ret)
14820                 goto fail;
14821
14822         intel_fbc_choose_crtc(dev_priv, state);
14823         ret = calc_watermark_data(state);
14824         if (ret)
14825                 goto fail;
14826
14827         ret = intel_bw_atomic_check(state);
14828         if (ret)
14829                 goto fail;
14830
14831         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14832                                             new_crtc_state, i) {
14833                 if (!needs_modeset(new_crtc_state) &&
14834                     !new_crtc_state->update_pipe)
14835                         continue;
14836
14837                 intel_dump_pipe_config(new_crtc_state, state,
14838                                        needs_modeset(new_crtc_state) ?
14839                                        "[modeset]" : "[fastset]");
14840         }
14841
14842         return 0;
14843
14844  fail:
14845         if (ret == -EDEADLK)
14846                 return ret;
14847
14848         /*
14849          * FIXME would probably be nice to know which crtc specifically
14850          * caused the failure, in cases where we can pinpoint it.
14851          */
14852         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14853                                             new_crtc_state, i)
14854                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14855
14856         return ret;
14857 }
14858
14859 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14860 {
14861         return drm_atomic_helper_prepare_planes(state->base.dev,
14862                                                 &state->base);
14863 }
14864
14865 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14866 {
14867         struct drm_device *dev = crtc->base.dev;
14868         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14869
14870         if (!vblank->max_vblank_count)
14871                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14872
14873         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14874 }
14875
14876 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14877                                   struct intel_crtc_state *crtc_state)
14878 {
14879         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14880
14881         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
14882                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14883
14884         if (crtc_state->has_pch_encoder) {
14885                 enum pipe pch_transcoder =
14886                         intel_crtc_pch_transcoder(crtc);
14887
14888                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14889         }
14890 }
14891
14892 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14893                                const struct intel_crtc_state *new_crtc_state)
14894 {
14895         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14896         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14897
14898         /*
14899          * Update pipe size and adjust fitter if needed: the reason for this is
14900          * that in compute_mode_changes we check the native mode (not the pfit
14901          * mode) to see if we can flip rather than do a full mode set. In the
14902          * fastboot case, we'll flip, but if we don't update the pipesrc and
14903          * pfit state, we'll end up with a big fb scanned out into the wrong
14904          * sized surface.
14905          */
14906         intel_set_pipe_src_size(new_crtc_state);
14907
14908         /* on skylake this is done by detaching scalers */
14909         if (INTEL_GEN(dev_priv) >= 9) {
14910                 skl_detach_scalers(new_crtc_state);
14911
14912                 if (new_crtc_state->pch_pfit.enabled)
14913                         skl_pfit_enable(new_crtc_state);
14914         } else if (HAS_PCH_SPLIT(dev_priv)) {
14915                 if (new_crtc_state->pch_pfit.enabled)
14916                         ilk_pfit_enable(new_crtc_state);
14917                 else if (old_crtc_state->pch_pfit.enabled)
14918                         ilk_pfit_disable(old_crtc_state);
14919         }
14920
14921         /*
14922          * The register is supposedly single buffered so perhaps
14923          * not 100% correct to do this here. But SKL+ calculate
14924          * this based on the adjust pixel rate so pfit changes do
14925          * affect it and so it must be updated for fastsets.
14926          * HSW/BDW only really need this here for fastboot, after
14927          * that the value should not change without a full modeset.
14928          */
14929         if (INTEL_GEN(dev_priv) >= 9 ||
14930             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
14931                 hsw_set_linetime_wm(new_crtc_state);
14932
14933         if (INTEL_GEN(dev_priv) >= 11)
14934                 icl_set_pipe_chicken(crtc);
14935 }
14936
14937 static void commit_pipe_config(struct intel_atomic_state *state,
14938                                struct intel_crtc *crtc)
14939 {
14940         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14941         const struct intel_crtc_state *old_crtc_state =
14942                 intel_atomic_get_old_crtc_state(state, crtc);
14943         const struct intel_crtc_state *new_crtc_state =
14944                 intel_atomic_get_new_crtc_state(state, crtc);
14945         bool modeset = needs_modeset(new_crtc_state);
14946
14947         /*
14948          * During modesets pipe configuration was programmed as the
14949          * CRTC was enabled.
14950          */
14951         if (!modeset) {
14952                 if (new_crtc_state->uapi.color_mgmt_changed ||
14953                     new_crtc_state->update_pipe)
14954                         intel_color_commit(new_crtc_state);
14955
14956                 if (INTEL_GEN(dev_priv) >= 9)
14957                         skl_detach_scalers(new_crtc_state);
14958
14959                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14960                         bdw_set_pipemisc(new_crtc_state);
14961
14962                 if (new_crtc_state->update_pipe)
14963                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14964         }
14965
14966         if (dev_priv->display.atomic_update_watermarks)
14967                 dev_priv->display.atomic_update_watermarks(state, crtc);
14968 }
14969
14970 static void intel_enable_crtc(struct intel_atomic_state *state,
14971                               struct intel_crtc *crtc)
14972 {
14973         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14974         const struct intel_crtc_state *new_crtc_state =
14975                 intel_atomic_get_new_crtc_state(state, crtc);
14976
14977         if (!needs_modeset(new_crtc_state))
14978                 return;
14979
14980         intel_crtc_update_active_timings(new_crtc_state);
14981
14982         dev_priv->display.crtc_enable(state, crtc);
14983
14984         /* vblanks work again, re-enable pipe CRC. */
14985         intel_crtc_enable_pipe_crc(crtc);
14986 }
14987
14988 static void intel_update_crtc(struct intel_atomic_state *state,
14989                               struct intel_crtc *crtc)
14990 {
14991         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14992         const struct intel_crtc_state *old_crtc_state =
14993                 intel_atomic_get_old_crtc_state(state, crtc);
14994         struct intel_crtc_state *new_crtc_state =
14995                 intel_atomic_get_new_crtc_state(state, crtc);
14996         bool modeset = needs_modeset(new_crtc_state);
14997
14998         if (!modeset) {
14999                 if (new_crtc_state->preload_luts &&
15000                     (new_crtc_state->uapi.color_mgmt_changed ||
15001                      new_crtc_state->update_pipe))
15002                         intel_color_load_luts(new_crtc_state);
15003
15004                 intel_pre_plane_update(state, crtc);
15005
15006                 if (new_crtc_state->update_pipe)
15007                         intel_encoders_update_pipe(state, crtc);
15008         }
15009
15010         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15011                 intel_fbc_disable(crtc);
15012         else
15013                 intel_fbc_enable(state, crtc);
15014
15015         /* Perform vblank evasion around commit operation */
15016         intel_pipe_update_start(new_crtc_state);
15017
15018         commit_pipe_config(state, crtc);
15019
15020         if (INTEL_GEN(dev_priv) >= 9)
15021                 skl_update_planes_on_crtc(state, crtc);
15022         else
15023                 i9xx_update_planes_on_crtc(state, crtc);
15024
15025         intel_pipe_update_end(new_crtc_state);
15026
15027         /*
15028          * We usually enable FIFO underrun interrupts as part of the
15029          * CRTC enable sequence during modesets.  But when we inherit a
15030          * valid pipe configuration from the BIOS we need to take care
15031          * of enabling them on the CRTC's first fastset.
15032          */
15033         if (new_crtc_state->update_pipe && !modeset &&
15034             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
15035                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15036 }
15037
15038
15039 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15040                                           struct intel_crtc_state *old_crtc_state,
15041                                           struct intel_crtc_state *new_crtc_state,
15042                                           struct intel_crtc *crtc)
15043 {
15044         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15045
15046         intel_crtc_disable_planes(state, crtc);
15047
15048         /*
15049          * We need to disable pipe CRC before disabling the pipe,
15050          * or we race against vblank off.
15051          */
15052         intel_crtc_disable_pipe_crc(crtc);
15053
15054         dev_priv->display.crtc_disable(state, crtc);
15055         crtc->active = false;
15056         intel_fbc_disable(crtc);
15057         intel_disable_shared_dpll(old_crtc_state);
15058
15059         /* FIXME unify this for all platforms */
15060         if (!new_crtc_state->hw.active &&
15061             !HAS_GMCH(dev_priv) &&
15062             dev_priv->display.initial_watermarks)
15063                 dev_priv->display.initial_watermarks(state, crtc);
15064 }
15065
15066 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15067 {
15068         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15069         struct intel_crtc *crtc;
15070         u32 handled = 0;
15071         int i;
15072
15073         /* Only disable port sync and MST slaves */
15074         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15075                                             new_crtc_state, i) {
15076                 if (!needs_modeset(new_crtc_state))
15077                         continue;
15078
15079                 if (!old_crtc_state->hw.active)
15080                         continue;
15081
15082                 /* In case of Transcoder port Sync master slave CRTCs can be
15083                  * assigned in any order and we need to make sure that
15084                  * slave CRTCs are disabled first and then master CRTC since
15085                  * Slave vblanks are masked till Master Vblanks.
15086                  */
15087                 if (!is_trans_port_sync_slave(old_crtc_state) &&
15088                     !intel_dp_mst_is_slave_trans(old_crtc_state))
15089                         continue;
15090
15091                 intel_pre_plane_update(state, crtc);
15092                 intel_old_crtc_state_disables(state, old_crtc_state,
15093                                               new_crtc_state, crtc);
15094                 handled |= BIT(crtc->pipe);
15095         }
15096
15097         /* Disable everything else left on */
15098         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15099                                             new_crtc_state, i) {
15100                 if (!needs_modeset(new_crtc_state) ||
15101                     (handled & BIT(crtc->pipe)))
15102                         continue;
15103
15104                 intel_pre_plane_update(state, crtc);
15105                 if (old_crtc_state->hw.active)
15106                         intel_old_crtc_state_disables(state, old_crtc_state,
15107                                                       new_crtc_state, crtc);
15108         }
15109 }
15110
15111 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15112 {
15113         struct intel_crtc_state *new_crtc_state;
15114         struct intel_crtc *crtc;
15115         int i;
15116
15117         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15118                 if (!new_crtc_state->hw.active)
15119                         continue;
15120
15121                 intel_enable_crtc(state, crtc);
15122                 intel_update_crtc(state, crtc);
15123         }
15124 }
15125
15126 static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
15127 {
15128         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15129         u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
15130         u8 required_slices = state->enabled_dbuf_slices_mask;
15131         u8 slices_union = hw_enabled_slices | required_slices;
15132
15133         /* If 2nd DBuf slice required, enable it here */
15134         if (INTEL_GEN(dev_priv) >= 11 && slices_union != hw_enabled_slices)
15135                 icl_dbuf_slices_update(dev_priv, slices_union);
15136 }
15137
15138 static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
15139 {
15140         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15141         u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
15142         u8 required_slices = state->enabled_dbuf_slices_mask;
15143
15144         /* If 2nd DBuf slice is no more required disable it */
15145         if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
15146                 icl_dbuf_slices_update(dev_priv, required_slices);
15147 }
15148
15149 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15150 {
15151         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15152         struct intel_crtc *crtc;
15153         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15154         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15155         u8 update_pipes = 0, modeset_pipes = 0;
15156         int i;
15157
15158         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15159                 enum pipe pipe = crtc->pipe;
15160
15161                 if (!new_crtc_state->hw.active)
15162                         continue;
15163
15164                 /* ignore allocations for crtc's that have been turned off. */
15165                 if (!needs_modeset(new_crtc_state)) {
15166                         entries[pipe] = old_crtc_state->wm.skl.ddb;
15167                         update_pipes |= BIT(pipe);
15168                 } else {
15169                         modeset_pipes |= BIT(pipe);
15170                 }
15171         }
15172
15173         /*
15174          * Whenever the number of active pipes changes, we need to make sure we
15175          * update the pipes in the right order so that their ddb allocations
15176          * never overlap with each other between CRTC updates. Otherwise we'll
15177          * cause pipe underruns and other bad stuff.
15178          *
15179          * So first lets enable all pipes that do not need a fullmodeset as
15180          * those don't have any external dependency.
15181          */
15182         while (update_pipes) {
15183                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15184                                                     new_crtc_state, i) {
15185                         enum pipe pipe = crtc->pipe;
15186
15187                         if ((update_pipes & BIT(pipe)) == 0)
15188                                 continue;
15189
15190                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15191                                                         entries, I915_MAX_PIPES, pipe))
15192                                 continue;
15193
15194                         entries[pipe] = new_crtc_state->wm.skl.ddb;
15195                         update_pipes &= ~BIT(pipe);
15196
15197                         intel_update_crtc(state, crtc);
15198
15199                         /*
15200                          * If this is an already active pipe, it's DDB changed,
15201                          * and this isn't the last pipe that needs updating
15202                          * then we need to wait for a vblank to pass for the
15203                          * new ddb allocation to take effect.
15204                          */
15205                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15206                                                  &old_crtc_state->wm.skl.ddb) &&
15207                             (update_pipes | modeset_pipes))
15208                                 intel_wait_for_vblank(dev_priv, pipe);
15209                 }
15210         }
15211
15212         update_pipes = modeset_pipes;
15213
15214         /*
15215          * Enable all pipes that needs a modeset and do not depends on other
15216          * pipes
15217          */
15218         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15219                 enum pipe pipe = crtc->pipe;
15220
15221                 if ((modeset_pipes & BIT(pipe)) == 0)
15222                         continue;
15223
15224                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15225                     is_trans_port_sync_master(new_crtc_state))
15226                         continue;
15227
15228                 modeset_pipes &= ~BIT(pipe);
15229
15230                 intel_enable_crtc(state, crtc);
15231         }
15232
15233         /*
15234          * Then we enable all remaining pipes that depend on other
15235          * pipes: MST slaves and port sync masters.
15236          */
15237         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15238                 enum pipe pipe = crtc->pipe;
15239
15240                 if ((modeset_pipes & BIT(pipe)) == 0)
15241                         continue;
15242
15243                 modeset_pipes &= ~BIT(pipe);
15244
15245                 intel_enable_crtc(state, crtc);
15246         }
15247
15248         /*
15249          * Finally we do the plane updates/etc. for all pipes that got enabled.
15250          */
15251         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15252                 enum pipe pipe = crtc->pipe;
15253
15254                 if ((update_pipes & BIT(pipe)) == 0)
15255                         continue;
15256
15257                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15258                                                                         entries, I915_MAX_PIPES, pipe));
15259
15260                 entries[pipe] = new_crtc_state->wm.skl.ddb;
15261                 update_pipes &= ~BIT(pipe);
15262
15263                 intel_update_crtc(state, crtc);
15264         }
15265
15266         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15267         drm_WARN_ON(&dev_priv->drm, update_pipes);
15268 }
15269
15270 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15271 {
15272         struct intel_atomic_state *state, *next;
15273         struct llist_node *freed;
15274
15275         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15276         llist_for_each_entry_safe(state, next, freed, freed)
15277                 drm_atomic_state_put(&state->base);
15278 }
15279
15280 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15281 {
15282         struct drm_i915_private *dev_priv =
15283                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15284
15285         intel_atomic_helper_free_state(dev_priv);
15286 }
15287
15288 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15289 {
15290         struct wait_queue_entry wait_fence, wait_reset;
15291         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15292
15293         init_wait_entry(&wait_fence, 0);
15294         init_wait_entry(&wait_reset, 0);
15295         for (;;) {
15296                 prepare_to_wait(&intel_state->commit_ready.wait,
15297                                 &wait_fence, TASK_UNINTERRUPTIBLE);
15298                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15299                                               I915_RESET_MODESET),
15300                                 &wait_reset, TASK_UNINTERRUPTIBLE);
15301
15302
15303                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15304                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15305                         break;
15306
15307                 schedule();
15308         }
15309         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15310         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15311                                   I915_RESET_MODESET),
15312                     &wait_reset);
15313 }
15314
15315 static void intel_atomic_cleanup_work(struct work_struct *work)
15316 {
15317         struct drm_atomic_state *state =
15318                 container_of(work, struct drm_atomic_state, commit_work);
15319         struct drm_i915_private *i915 = to_i915(state->dev);
15320
15321         drm_atomic_helper_cleanup_planes(&i915->drm, state);
15322         drm_atomic_helper_commit_cleanup_done(state);
15323         drm_atomic_state_put(state);
15324
15325         intel_atomic_helper_free_state(i915);
15326 }
15327
15328 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15329 {
15330         struct drm_device *dev = state->base.dev;
15331         struct drm_i915_private *dev_priv = to_i915(dev);
15332         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15333         struct intel_crtc *crtc;
15334         u64 put_domains[I915_MAX_PIPES] = {};
15335         intel_wakeref_t wakeref = 0;
15336         int i;
15337
15338         intel_atomic_commit_fence_wait(state);
15339
15340         drm_atomic_helper_wait_for_dependencies(&state->base);
15341
15342         if (state->modeset)
15343                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15344
15345         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15346                                             new_crtc_state, i) {
15347                 if (needs_modeset(new_crtc_state) ||
15348                     new_crtc_state->update_pipe) {
15349
15350                         put_domains[crtc->pipe] =
15351                                 modeset_get_crtc_power_domains(new_crtc_state);
15352                 }
15353         }
15354
15355         intel_commit_modeset_disables(state);
15356
15357         /* FIXME: Eventually get rid of our crtc->config pointer */
15358         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15359                 crtc->config = new_crtc_state;
15360
15361         if (state->modeset) {
15362                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15363
15364                 intel_set_cdclk_pre_plane_update(state);
15365
15366                 intel_sagv_pre_plane_update(state);
15367
15368                 intel_modeset_verify_disabled(dev_priv, state);
15369         }
15370
15371         /* Complete the events for pipes that have now been disabled */
15372         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15373                 bool modeset = needs_modeset(new_crtc_state);
15374
15375                 /* Complete events for now disable pipes here. */
15376                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15377                         spin_lock_irq(&dev->event_lock);
15378                         drm_crtc_send_vblank_event(&crtc->base,
15379                                                    new_crtc_state->uapi.event);
15380                         spin_unlock_irq(&dev->event_lock);
15381
15382                         new_crtc_state->uapi.event = NULL;
15383                 }
15384         }
15385
15386         if (state->modeset)
15387                 intel_encoders_update_prepare(state);
15388
15389         /* Enable all new slices, we might need */
15390         if (state->modeset)
15391                 icl_dbuf_slice_pre_update(state);
15392
15393         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15394         dev_priv->display.commit_modeset_enables(state);
15395
15396         if (state->modeset) {
15397                 intel_encoders_update_complete(state);
15398
15399                 intel_set_cdclk_post_plane_update(state);
15400         }
15401
15402         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15403          * already, but still need the state for the delayed optimization. To
15404          * fix this:
15405          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15406          * - schedule that vblank worker _before_ calling hw_done
15407          * - at the start of commit_tail, cancel it _synchrously
15408          * - switch over to the vblank wait helper in the core after that since
15409          *   we don't need out special handling any more.
15410          */
15411         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15412
15413         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15414                 if (new_crtc_state->hw.active &&
15415                     !needs_modeset(new_crtc_state) &&
15416                     !new_crtc_state->preload_luts &&
15417                     (new_crtc_state->uapi.color_mgmt_changed ||
15418                      new_crtc_state->update_pipe))
15419                         intel_color_load_luts(new_crtc_state);
15420         }
15421
15422         /*
15423          * Now that the vblank has passed, we can go ahead and program the
15424          * optimal watermarks on platforms that need two-step watermark
15425          * programming.
15426          *
15427          * TODO: Move this (and other cleanup) to an async worker eventually.
15428          */
15429         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15430                                             new_crtc_state, i) {
15431                 /*
15432                  * Gen2 reports pipe underruns whenever all planes are disabled.
15433                  * So re-enable underrun reporting after some planes get enabled.
15434                  *
15435                  * We do this before .optimize_watermarks() so that we have a
15436                  * chance of catching underruns with the intermediate watermarks
15437                  * vs. the new plane configuration.
15438                  */
15439                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15440                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15441
15442                 if (dev_priv->display.optimize_watermarks)
15443                         dev_priv->display.optimize_watermarks(state, crtc);
15444         }
15445
15446         /* Disable all slices, we don't need */
15447         if (state->modeset)
15448                 icl_dbuf_slice_post_update(state);
15449
15450         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15451                 intel_post_plane_update(state, crtc);
15452
15453                 if (put_domains[i])
15454                         modeset_put_power_domains(dev_priv, put_domains[i]);
15455
15456                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15457         }
15458
15459         /* Underruns don't always raise interrupts, so check manually */
15460         intel_check_cpu_fifo_underruns(dev_priv);
15461         intel_check_pch_fifo_underruns(dev_priv);
15462
15463         if (state->modeset) {
15464                 intel_verify_planes(state);
15465
15466                 intel_sagv_post_plane_update(state);
15467         }
15468
15469         drm_atomic_helper_commit_hw_done(&state->base);
15470
15471         if (state->modeset) {
15472                 /* As one of the primary mmio accessors, KMS has a high
15473                  * likelihood of triggering bugs in unclaimed access. After we
15474                  * finish modesetting, see if an error has been flagged, and if
15475                  * so enable debugging for the next modeset - and hope we catch
15476                  * the culprit.
15477                  */
15478                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15479                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15480         }
15481         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15482
15483         /*
15484          * Defer the cleanup of the old state to a separate worker to not
15485          * impede the current task (userspace for blocking modesets) that
15486          * are executed inline. For out-of-line asynchronous modesets/flips,
15487          * deferring to a new worker seems overkill, but we would place a
15488          * schedule point (cond_resched()) here anyway to keep latencies
15489          * down.
15490          */
15491         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15492         queue_work(system_highpri_wq, &state->base.commit_work);
15493 }
15494
15495 static void intel_atomic_commit_work(struct work_struct *work)
15496 {
15497         struct intel_atomic_state *state =
15498                 container_of(work, struct intel_atomic_state, base.commit_work);
15499
15500         intel_atomic_commit_tail(state);
15501 }
15502
15503 static int __i915_sw_fence_call
15504 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15505                           enum i915_sw_fence_notify notify)
15506 {
15507         struct intel_atomic_state *state =
15508                 container_of(fence, struct intel_atomic_state, commit_ready);
15509
15510         switch (notify) {
15511         case FENCE_COMPLETE:
15512                 /* we do blocking waits in the worker, nothing to do here */
15513                 break;
15514         case FENCE_FREE:
15515                 {
15516                         struct intel_atomic_helper *helper =
15517                                 &to_i915(state->base.dev)->atomic_helper;
15518
15519                         if (llist_add(&state->freed, &helper->free_list))
15520                                 schedule_work(&helper->free_work);
15521                         break;
15522                 }
15523         }
15524
15525         return NOTIFY_DONE;
15526 }
15527
15528 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15529 {
15530         struct intel_plane_state *old_plane_state, *new_plane_state;
15531         struct intel_plane *plane;
15532         int i;
15533
15534         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15535                                              new_plane_state, i)
15536                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15537                                         to_intel_frontbuffer(new_plane_state->hw.fb),
15538                                         plane->frontbuffer_bit);
15539 }
15540
15541 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
15542 {
15543         struct intel_crtc *crtc;
15544
15545         for_each_intel_crtc(&dev_priv->drm, crtc)
15546                 drm_modeset_lock_assert_held(&crtc->base.mutex);
15547 }
15548
15549 static int intel_atomic_commit(struct drm_device *dev,
15550                                struct drm_atomic_state *_state,
15551                                bool nonblock)
15552 {
15553         struct intel_atomic_state *state = to_intel_atomic_state(_state);
15554         struct drm_i915_private *dev_priv = to_i915(dev);
15555         int ret = 0;
15556
15557         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15558
15559         drm_atomic_state_get(&state->base);
15560         i915_sw_fence_init(&state->commit_ready,
15561                            intel_atomic_commit_ready);
15562
15563         /*
15564          * The intel_legacy_cursor_update() fast path takes care
15565          * of avoiding the vblank waits for simple cursor
15566          * movement and flips. For cursor on/off and size changes,
15567          * we want to perform the vblank waits so that watermark
15568          * updates happen during the correct frames. Gen9+ have
15569          * double buffered watermarks and so shouldn't need this.
15570          *
15571          * Unset state->legacy_cursor_update before the call to
15572          * drm_atomic_helper_setup_commit() because otherwise
15573          * drm_atomic_helper_wait_for_flip_done() is a noop and
15574          * we get FIFO underruns because we didn't wait
15575          * for vblank.
15576          *
15577          * FIXME doing watermarks and fb cleanup from a vblank worker
15578          * (assuming we had any) would solve these problems.
15579          */
15580         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15581                 struct intel_crtc_state *new_crtc_state;
15582                 struct intel_crtc *crtc;
15583                 int i;
15584
15585                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15586                         if (new_crtc_state->wm.need_postvbl_update ||
15587                             new_crtc_state->update_wm_post)
15588                                 state->base.legacy_cursor_update = false;
15589         }
15590
15591         ret = intel_atomic_prepare_commit(state);
15592         if (ret) {
15593                 drm_dbg_atomic(&dev_priv->drm,
15594                                "Preparing state failed with %i\n", ret);
15595                 i915_sw_fence_commit(&state->commit_ready);
15596                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15597                 return ret;
15598         }
15599
15600         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15601         if (!ret)
15602                 ret = drm_atomic_helper_swap_state(&state->base, true);
15603         if (!ret)
15604                 intel_atomic_swap_global_state(state);
15605
15606         if (ret) {
15607                 i915_sw_fence_commit(&state->commit_ready);
15608
15609                 drm_atomic_helper_cleanup_planes(dev, &state->base);
15610                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15611                 return ret;
15612         }
15613         dev_priv->wm.distrust_bios_wm = false;
15614         intel_shared_dpll_swap_state(state);
15615         intel_atomic_track_fbs(state);
15616
15617         if (state->global_state_changed) {
15618                 assert_global_state_locked(dev_priv);
15619
15620                 dev_priv->active_pipes = state->active_pipes;
15621         }
15622
15623         drm_atomic_state_get(&state->base);
15624         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15625
15626         i915_sw_fence_commit(&state->commit_ready);
15627         if (nonblock && state->modeset) {
15628                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15629         } else if (nonblock) {
15630                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15631         } else {
15632                 if (state->modeset)
15633                         flush_workqueue(dev_priv->modeset_wq);
15634                 intel_atomic_commit_tail(state);
15635         }
15636
15637         return 0;
15638 }
15639
15640 struct wait_rps_boost {
15641         struct wait_queue_entry wait;
15642
15643         struct drm_crtc *crtc;
15644         struct i915_request *request;
15645 };
15646
15647 static int do_rps_boost(struct wait_queue_entry *_wait,
15648                         unsigned mode, int sync, void *key)
15649 {
15650         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15651         struct i915_request *rq = wait->request;
15652
15653         /*
15654          * If we missed the vblank, but the request is already running it
15655          * is reasonable to assume that it will complete before the next
15656          * vblank without our intervention, so leave RPS alone.
15657          */
15658         if (!i915_request_started(rq))
15659                 intel_rps_boost(rq);
15660         i915_request_put(rq);
15661
15662         drm_crtc_vblank_put(wait->crtc);
15663
15664         list_del(&wait->wait.entry);
15665         kfree(wait);
15666         return 1;
15667 }
15668
15669 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15670                                        struct dma_fence *fence)
15671 {
15672         struct wait_rps_boost *wait;
15673
15674         if (!dma_fence_is_i915(fence))
15675                 return;
15676
15677         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15678                 return;
15679
15680         if (drm_crtc_vblank_get(crtc))
15681                 return;
15682
15683         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15684         if (!wait) {
15685                 drm_crtc_vblank_put(crtc);
15686                 return;
15687         }
15688
15689         wait->request = to_request(dma_fence_get(fence));
15690         wait->crtc = crtc;
15691
15692         wait->wait.func = do_rps_boost;
15693         wait->wait.flags = 0;
15694
15695         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15696 }
15697
15698 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15699 {
15700         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15701         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15702         struct drm_framebuffer *fb = plane_state->hw.fb;
15703         struct i915_vma *vma;
15704
15705         if (plane->id == PLANE_CURSOR &&
15706             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15707                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15708                 const int align = intel_cursor_alignment(dev_priv);
15709                 int err;
15710
15711                 err = i915_gem_object_attach_phys(obj, align);
15712                 if (err)
15713                         return err;
15714         }
15715
15716         vma = intel_pin_and_fence_fb_obj(fb,
15717                                          &plane_state->view,
15718                                          intel_plane_uses_fence(plane_state),
15719                                          &plane_state->flags);
15720         if (IS_ERR(vma))
15721                 return PTR_ERR(vma);
15722
15723         plane_state->vma = vma;
15724
15725         return 0;
15726 }
15727
15728 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15729 {
15730         struct i915_vma *vma;
15731
15732         vma = fetch_and_zero(&old_plane_state->vma);
15733         if (vma)
15734                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15735 }
15736
15737 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15738 {
15739         struct i915_sched_attr attr = {
15740                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15741         };
15742
15743         i915_gem_object_wait_priority(obj, 0, &attr);
15744 }
15745
15746 /**
15747  * intel_prepare_plane_fb - Prepare fb for usage on plane
15748  * @_plane: drm plane to prepare for
15749  * @_new_plane_state: the plane state being prepared
15750  *
15751  * Prepares a framebuffer for usage on a display plane.  Generally this
15752  * involves pinning the underlying object and updating the frontbuffer tracking
15753  * bits.  Some older platforms need special physical address handling for
15754  * cursor planes.
15755  *
15756  * Returns 0 on success, negative error code on failure.
15757  */
15758 int
15759 intel_prepare_plane_fb(struct drm_plane *_plane,
15760                        struct drm_plane_state *_new_plane_state)
15761 {
15762         struct intel_plane *plane = to_intel_plane(_plane);
15763         struct intel_plane_state *new_plane_state =
15764                 to_intel_plane_state(_new_plane_state);
15765         struct intel_atomic_state *state =
15766                 to_intel_atomic_state(new_plane_state->uapi.state);
15767         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15768         const struct intel_plane_state *old_plane_state =
15769                 intel_atomic_get_old_plane_state(state, plane);
15770         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
15771         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
15772         int ret;
15773
15774         if (old_obj) {
15775                 const struct intel_crtc_state *crtc_state =
15776                         intel_atomic_get_new_crtc_state(state,
15777                                                         to_intel_crtc(old_plane_state->hw.crtc));
15778
15779                 /* Big Hammer, we also need to ensure that any pending
15780                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15781                  * current scanout is retired before unpinning the old
15782                  * framebuffer. Note that we rely on userspace rendering
15783                  * into the buffer attached to the pipe they are waiting
15784                  * on. If not, userspace generates a GPU hang with IPEHR
15785                  * point to the MI_WAIT_FOR_EVENT.
15786                  *
15787                  * This should only fail upon a hung GPU, in which case we
15788                  * can safely continue.
15789                  */
15790                 if (needs_modeset(crtc_state)) {
15791                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
15792                                                               old_obj->base.resv, NULL,
15793                                                               false, 0,
15794                                                               GFP_KERNEL);
15795                         if (ret < 0)
15796                                 return ret;
15797                 }
15798         }
15799
15800         if (new_plane_state->uapi.fence) { /* explicit fencing */
15801                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
15802                                                     new_plane_state->uapi.fence,
15803                                                     I915_FENCE_TIMEOUT,
15804                                                     GFP_KERNEL);
15805                 if (ret < 0)
15806                         return ret;
15807         }
15808
15809         if (!obj)
15810                 return 0;
15811
15812         ret = i915_gem_object_pin_pages(obj);
15813         if (ret)
15814                 return ret;
15815
15816         ret = intel_plane_pin_fb(new_plane_state);
15817
15818         i915_gem_object_unpin_pages(obj);
15819         if (ret)
15820                 return ret;
15821
15822         fb_obj_bump_render_priority(obj);
15823         i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
15824
15825         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15826                 struct dma_fence *fence;
15827
15828                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
15829                                                       obj->base.resv, NULL,
15830                                                       false, I915_FENCE_TIMEOUT,
15831                                                       GFP_KERNEL);
15832                 if (ret < 0)
15833                         goto unpin_fb;
15834
15835                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15836                 if (fence) {
15837                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15838                                                    fence);
15839                         dma_fence_put(fence);
15840                 }
15841         } else {
15842                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15843                                            new_plane_state->uapi.fence);
15844         }
15845
15846         /*
15847          * We declare pageflips to be interactive and so merit a small bias
15848          * towards upclocking to deliver the frame on time. By only changing
15849          * the RPS thresholds to sample more regularly and aim for higher
15850          * clocks we can hopefully deliver low power workloads (like kodi)
15851          * that are not quite steady state without resorting to forcing
15852          * maximum clocks following a vblank miss (see do_rps_boost()).
15853          */
15854         if (!state->rps_interactive) {
15855                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15856                 state->rps_interactive = true;
15857         }
15858
15859         return 0;
15860
15861 unpin_fb:
15862         intel_plane_unpin_fb(new_plane_state);
15863
15864         return ret;
15865 }
15866
15867 /**
15868  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15869  * @plane: drm plane to clean up for
15870  * @_old_plane_state: the state from the previous modeset
15871  *
15872  * Cleans up a framebuffer that has just been removed from a plane.
15873  */
15874 void
15875 intel_cleanup_plane_fb(struct drm_plane *plane,
15876                        struct drm_plane_state *_old_plane_state)
15877 {
15878         struct intel_plane_state *old_plane_state =
15879                 to_intel_plane_state(_old_plane_state);
15880         struct intel_atomic_state *state =
15881                 to_intel_atomic_state(old_plane_state->uapi.state);
15882         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15883         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
15884
15885         if (!obj)
15886                 return;
15887
15888         if (state->rps_interactive) {
15889                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15890                 state->rps_interactive = false;
15891         }
15892
15893         /* Should only be called after a successful intel_prepare_plane_fb()! */
15894         intel_plane_unpin_fb(old_plane_state);
15895 }
15896
15897 /**
15898  * intel_plane_destroy - destroy a plane
15899  * @plane: plane to destroy
15900  *
15901  * Common destruction function for all types of planes (primary, cursor,
15902  * sprite).
15903  */
15904 void intel_plane_destroy(struct drm_plane *plane)
15905 {
15906         drm_plane_cleanup(plane);
15907         kfree(to_intel_plane(plane));
15908 }
15909
15910 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15911                                             u32 format, u64 modifier)
15912 {
15913         switch (modifier) {
15914         case DRM_FORMAT_MOD_LINEAR:
15915         case I915_FORMAT_MOD_X_TILED:
15916                 break;
15917         default:
15918                 return false;
15919         }
15920
15921         switch (format) {
15922         case DRM_FORMAT_C8:
15923         case DRM_FORMAT_RGB565:
15924         case DRM_FORMAT_XRGB1555:
15925         case DRM_FORMAT_XRGB8888:
15926                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15927                         modifier == I915_FORMAT_MOD_X_TILED;
15928         default:
15929                 return false;
15930         }
15931 }
15932
15933 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15934                                             u32 format, u64 modifier)
15935 {
15936         switch (modifier) {
15937         case DRM_FORMAT_MOD_LINEAR:
15938         case I915_FORMAT_MOD_X_TILED:
15939                 break;
15940         default:
15941                 return false;
15942         }
15943
15944         switch (format) {
15945         case DRM_FORMAT_C8:
15946         case DRM_FORMAT_RGB565:
15947         case DRM_FORMAT_XRGB8888:
15948         case DRM_FORMAT_XBGR8888:
15949         case DRM_FORMAT_ARGB8888:
15950         case DRM_FORMAT_ABGR8888:
15951         case DRM_FORMAT_XRGB2101010:
15952         case DRM_FORMAT_XBGR2101010:
15953         case DRM_FORMAT_ARGB2101010:
15954         case DRM_FORMAT_ABGR2101010:
15955         case DRM_FORMAT_XBGR16161616F:
15956                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15957                         modifier == I915_FORMAT_MOD_X_TILED;
15958         default:
15959                 return false;
15960         }
15961 }
15962
15963 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15964                                               u32 format, u64 modifier)
15965 {
15966         return modifier == DRM_FORMAT_MOD_LINEAR &&
15967                 format == DRM_FORMAT_ARGB8888;
15968 }
15969
15970 static const struct drm_plane_funcs i965_plane_funcs = {
15971         .update_plane = drm_atomic_helper_update_plane,
15972         .disable_plane = drm_atomic_helper_disable_plane,
15973         .destroy = intel_plane_destroy,
15974         .atomic_duplicate_state = intel_plane_duplicate_state,
15975         .atomic_destroy_state = intel_plane_destroy_state,
15976         .format_mod_supported = i965_plane_format_mod_supported,
15977 };
15978
15979 static const struct drm_plane_funcs i8xx_plane_funcs = {
15980         .update_plane = drm_atomic_helper_update_plane,
15981         .disable_plane = drm_atomic_helper_disable_plane,
15982         .destroy = intel_plane_destroy,
15983         .atomic_duplicate_state = intel_plane_duplicate_state,
15984         .atomic_destroy_state = intel_plane_destroy_state,
15985         .format_mod_supported = i8xx_plane_format_mod_supported,
15986 };
15987
15988 static int
15989 intel_legacy_cursor_update(struct drm_plane *_plane,
15990                            struct drm_crtc *_crtc,
15991                            struct drm_framebuffer *fb,
15992                            int crtc_x, int crtc_y,
15993                            unsigned int crtc_w, unsigned int crtc_h,
15994                            u32 src_x, u32 src_y,
15995                            u32 src_w, u32 src_h,
15996                            struct drm_modeset_acquire_ctx *ctx)
15997 {
15998         struct intel_plane *plane = to_intel_plane(_plane);
15999         struct intel_crtc *crtc = to_intel_crtc(_crtc);
16000         struct intel_plane_state *old_plane_state =
16001                 to_intel_plane_state(plane->base.state);
16002         struct intel_plane_state *new_plane_state;
16003         struct intel_crtc_state *crtc_state =
16004                 to_intel_crtc_state(crtc->base.state);
16005         struct intel_crtc_state *new_crtc_state;
16006         int ret;
16007
16008         /*
16009          * When crtc is inactive or there is a modeset pending,
16010          * wait for it to complete in the slowpath
16011          */
16012         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16013             crtc_state->update_pipe)
16014                 goto slow;
16015
16016         /*
16017          * Don't do an async update if there is an outstanding commit modifying
16018          * the plane.  This prevents our async update's changes from getting
16019          * overridden by a previous synchronous update's state.
16020          */
16021         if (old_plane_state->uapi.commit &&
16022             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16023                 goto slow;
16024
16025         /*
16026          * If any parameters change that may affect watermarks,
16027          * take the slowpath. Only changing fb or position should be
16028          * in the fastpath.
16029          */
16030         if (old_plane_state->uapi.crtc != &crtc->base ||
16031             old_plane_state->uapi.src_w != src_w ||
16032             old_plane_state->uapi.src_h != src_h ||
16033             old_plane_state->uapi.crtc_w != crtc_w ||
16034             old_plane_state->uapi.crtc_h != crtc_h ||
16035             !old_plane_state->uapi.fb != !fb)
16036                 goto slow;
16037
16038         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16039         if (!new_plane_state)
16040                 return -ENOMEM;
16041
16042         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16043         if (!new_crtc_state) {
16044                 ret = -ENOMEM;
16045                 goto out_free;
16046         }
16047
16048         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16049
16050         new_plane_state->uapi.src_x = src_x;
16051         new_plane_state->uapi.src_y = src_y;
16052         new_plane_state->uapi.src_w = src_w;
16053         new_plane_state->uapi.src_h = src_h;
16054         new_plane_state->uapi.crtc_x = crtc_x;
16055         new_plane_state->uapi.crtc_y = crtc_y;
16056         new_plane_state->uapi.crtc_w = crtc_w;
16057         new_plane_state->uapi.crtc_h = crtc_h;
16058
16059         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16060
16061         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16062                                                   old_plane_state, new_plane_state);
16063         if (ret)
16064                 goto out_free;
16065
16066         ret = intel_plane_pin_fb(new_plane_state);
16067         if (ret)
16068                 goto out_free;
16069
16070         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16071                                 ORIGIN_FLIP);
16072         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16073                                 to_intel_frontbuffer(new_plane_state->hw.fb),
16074                                 plane->frontbuffer_bit);
16075
16076         /* Swap plane state */
16077         plane->base.state = &new_plane_state->uapi;
16078
16079         /*
16080          * We cannot swap crtc_state as it may be in use by an atomic commit or
16081          * page flip that's running simultaneously. If we swap crtc_state and
16082          * destroy the old state, we will cause a use-after-free there.
16083          *
16084          * Only update active_planes, which is needed for our internal
16085          * bookkeeping. Either value will do the right thing when updating
16086          * planes atomically. If the cursor was part of the atomic update then
16087          * we would have taken the slowpath.
16088          */
16089         crtc_state->active_planes = new_crtc_state->active_planes;
16090
16091         if (new_plane_state->uapi.visible)
16092                 intel_update_plane(plane, crtc_state, new_plane_state);
16093         else
16094                 intel_disable_plane(plane, crtc_state);
16095
16096         intel_plane_unpin_fb(old_plane_state);
16097
16098 out_free:
16099         if (new_crtc_state)
16100                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16101         if (ret)
16102                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16103         else
16104                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16105         return ret;
16106
16107 slow:
16108         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16109                                               crtc_x, crtc_y, crtc_w, crtc_h,
16110                                               src_x, src_y, src_w, src_h, ctx);
16111 }
16112
16113 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16114         .update_plane = intel_legacy_cursor_update,
16115         .disable_plane = drm_atomic_helper_disable_plane,
16116         .destroy = intel_plane_destroy,
16117         .atomic_duplicate_state = intel_plane_duplicate_state,
16118         .atomic_destroy_state = intel_plane_destroy_state,
16119         .format_mod_supported = intel_cursor_format_mod_supported,
16120 };
16121
16122 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16123                                enum i9xx_plane_id i9xx_plane)
16124 {
16125         if (!HAS_FBC(dev_priv))
16126                 return false;
16127
16128         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16129                 return i9xx_plane == PLANE_A; /* tied to pipe A */
16130         else if (IS_IVYBRIDGE(dev_priv))
16131                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16132                         i9xx_plane == PLANE_C;
16133         else if (INTEL_GEN(dev_priv) >= 4)
16134                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16135         else
16136                 return i9xx_plane == PLANE_A;
16137 }
16138
16139 static struct intel_plane *
16140 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16141 {
16142         struct intel_plane *plane;
16143         const struct drm_plane_funcs *plane_funcs;
16144         unsigned int supported_rotations;
16145         const u32 *formats;
16146         int num_formats;
16147         int ret, zpos;
16148
16149         if (INTEL_GEN(dev_priv) >= 9)
16150                 return skl_universal_plane_create(dev_priv, pipe,
16151                                                   PLANE_PRIMARY);
16152
16153         plane = intel_plane_alloc();
16154         if (IS_ERR(plane))
16155                 return plane;
16156
16157         plane->pipe = pipe;
16158         /*
16159          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16160          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16161          */
16162         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
16163                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16164         else
16165                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16166         plane->id = PLANE_PRIMARY;
16167         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16168
16169         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16170         if (plane->has_fbc) {
16171                 struct intel_fbc *fbc = &dev_priv->fbc;
16172
16173                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16174         }
16175
16176         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16177                 formats = vlv_primary_formats;
16178                 num_formats = ARRAY_SIZE(vlv_primary_formats);
16179         } else if (INTEL_GEN(dev_priv) >= 4) {
16180                 /*
16181                  * WaFP16GammaEnabling:ivb
16182                  * "Workaround : When using the 64-bit format, the plane
16183                  *  output on each color channel has one quarter amplitude.
16184                  *  It can be brought up to full amplitude by using pipe
16185                  *  gamma correction or pipe color space conversion to
16186                  *  multiply the plane output by four."
16187                  *
16188                  * There is no dedicated plane gamma for the primary plane,
16189                  * and using the pipe gamma/csc could conflict with other
16190                  * planes, so we choose not to expose fp16 on IVB primary
16191                  * planes. HSW primary planes no longer have this problem.
16192                  */
16193                 if (IS_IVYBRIDGE(dev_priv)) {
16194                         formats = ivb_primary_formats;
16195                         num_formats = ARRAY_SIZE(ivb_primary_formats);
16196                 } else {
16197                         formats = i965_primary_formats;
16198                         num_formats = ARRAY_SIZE(i965_primary_formats);
16199                 }
16200         } else {
16201                 formats = i8xx_primary_formats;
16202                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16203         }
16204
16205         if (INTEL_GEN(dev_priv) >= 4)
16206                 plane_funcs = &i965_plane_funcs;
16207         else
16208                 plane_funcs = &i8xx_plane_funcs;
16209
16210         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16211                 plane->min_cdclk = vlv_plane_min_cdclk;
16212         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16213                 plane->min_cdclk = hsw_plane_min_cdclk;
16214         else if (IS_IVYBRIDGE(dev_priv))
16215                 plane->min_cdclk = ivb_plane_min_cdclk;
16216         else
16217                 plane->min_cdclk = i9xx_plane_min_cdclk;
16218
16219         plane->max_stride = i9xx_plane_max_stride;
16220         plane->update_plane = i9xx_update_plane;
16221         plane->disable_plane = i9xx_disable_plane;
16222         plane->get_hw_state = i9xx_plane_get_hw_state;
16223         plane->check_plane = i9xx_plane_check;
16224
16225         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16226                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16227                                                0, plane_funcs,
16228                                                formats, num_formats,
16229                                                i9xx_format_modifiers,
16230                                                DRM_PLANE_TYPE_PRIMARY,
16231                                                "primary %c", pipe_name(pipe));
16232         else
16233                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16234                                                0, plane_funcs,
16235                                                formats, num_formats,
16236                                                i9xx_format_modifiers,
16237                                                DRM_PLANE_TYPE_PRIMARY,
16238                                                "plane %c",
16239                                                plane_name(plane->i9xx_plane));
16240         if (ret)
16241                 goto fail;
16242
16243         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16244                 supported_rotations =
16245                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16246                         DRM_MODE_REFLECT_X;
16247         } else if (INTEL_GEN(dev_priv) >= 4) {
16248                 supported_rotations =
16249                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16250         } else {
16251                 supported_rotations = DRM_MODE_ROTATE_0;
16252         }
16253
16254         if (INTEL_GEN(dev_priv) >= 4)
16255                 drm_plane_create_rotation_property(&plane->base,
16256                                                    DRM_MODE_ROTATE_0,
16257                                                    supported_rotations);
16258
16259         zpos = 0;
16260         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16261
16262         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16263
16264         return plane;
16265
16266 fail:
16267         intel_plane_free(plane);
16268
16269         return ERR_PTR(ret);
16270 }
16271
16272 static struct intel_plane *
16273 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16274                           enum pipe pipe)
16275 {
16276         struct intel_plane *cursor;
16277         int ret, zpos;
16278
16279         cursor = intel_plane_alloc();
16280         if (IS_ERR(cursor))
16281                 return cursor;
16282
16283         cursor->pipe = pipe;
16284         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16285         cursor->id = PLANE_CURSOR;
16286         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16287
16288         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16289                 cursor->max_stride = i845_cursor_max_stride;
16290                 cursor->update_plane = i845_update_cursor;
16291                 cursor->disable_plane = i845_disable_cursor;
16292                 cursor->get_hw_state = i845_cursor_get_hw_state;
16293                 cursor->check_plane = i845_check_cursor;
16294         } else {
16295                 cursor->max_stride = i9xx_cursor_max_stride;
16296                 cursor->update_plane = i9xx_update_cursor;
16297                 cursor->disable_plane = i9xx_disable_cursor;
16298                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16299                 cursor->check_plane = i9xx_check_cursor;
16300         }
16301
16302         cursor->cursor.base = ~0;
16303         cursor->cursor.cntl = ~0;
16304
16305         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16306                 cursor->cursor.size = ~0;
16307
16308         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16309                                        0, &intel_cursor_plane_funcs,
16310                                        intel_cursor_formats,
16311                                        ARRAY_SIZE(intel_cursor_formats),
16312                                        cursor_format_modifiers,
16313                                        DRM_PLANE_TYPE_CURSOR,
16314                                        "cursor %c", pipe_name(pipe));
16315         if (ret)
16316                 goto fail;
16317
16318         if (INTEL_GEN(dev_priv) >= 4)
16319                 drm_plane_create_rotation_property(&cursor->base,
16320                                                    DRM_MODE_ROTATE_0,
16321                                                    DRM_MODE_ROTATE_0 |
16322                                                    DRM_MODE_ROTATE_180);
16323
16324         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16325         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16326
16327         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16328
16329         return cursor;
16330
16331 fail:
16332         intel_plane_free(cursor);
16333
16334         return ERR_PTR(ret);
16335 }
16336
16337 #define INTEL_CRTC_FUNCS \
16338         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16339         .set_config = drm_atomic_helper_set_config, \
16340         .destroy = intel_crtc_destroy, \
16341         .page_flip = drm_atomic_helper_page_flip, \
16342         .atomic_duplicate_state = intel_crtc_duplicate_state, \
16343         .atomic_destroy_state = intel_crtc_destroy_state, \
16344         .set_crc_source = intel_crtc_set_crc_source, \
16345         .verify_crc_source = intel_crtc_verify_crc_source, \
16346         .get_crc_sources = intel_crtc_get_crc_sources
16347
16348 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16349         INTEL_CRTC_FUNCS,
16350
16351         .get_vblank_counter = g4x_get_vblank_counter,
16352         .enable_vblank = bdw_enable_vblank,
16353         .disable_vblank = bdw_disable_vblank,
16354         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16355 };
16356
16357 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16358         INTEL_CRTC_FUNCS,
16359
16360         .get_vblank_counter = g4x_get_vblank_counter,
16361         .enable_vblank = ilk_enable_vblank,
16362         .disable_vblank = ilk_disable_vblank,
16363         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16364 };
16365
16366 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16367         INTEL_CRTC_FUNCS,
16368
16369         .get_vblank_counter = g4x_get_vblank_counter,
16370         .enable_vblank = i965_enable_vblank,
16371         .disable_vblank = i965_disable_vblank,
16372         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16373 };
16374
16375 static const struct drm_crtc_funcs i965_crtc_funcs = {
16376         INTEL_CRTC_FUNCS,
16377
16378         .get_vblank_counter = i915_get_vblank_counter,
16379         .enable_vblank = i965_enable_vblank,
16380         .disable_vblank = i965_disable_vblank,
16381         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16382 };
16383
16384 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16385         INTEL_CRTC_FUNCS,
16386
16387         .get_vblank_counter = i915_get_vblank_counter,
16388         .enable_vblank = i915gm_enable_vblank,
16389         .disable_vblank = i915gm_disable_vblank,
16390         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16391 };
16392
16393 static const struct drm_crtc_funcs i915_crtc_funcs = {
16394         INTEL_CRTC_FUNCS,
16395
16396         .get_vblank_counter = i915_get_vblank_counter,
16397         .enable_vblank = i8xx_enable_vblank,
16398         .disable_vblank = i8xx_disable_vblank,
16399         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16400 };
16401
16402 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16403         INTEL_CRTC_FUNCS,
16404
16405         /* no hw vblank counter */
16406         .enable_vblank = i8xx_enable_vblank,
16407         .disable_vblank = i8xx_disable_vblank,
16408         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16409 };
16410
16411 static struct intel_crtc *intel_crtc_alloc(void)
16412 {
16413         struct intel_crtc_state *crtc_state;
16414         struct intel_crtc *crtc;
16415
16416         crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16417         if (!crtc)
16418                 return ERR_PTR(-ENOMEM);
16419
16420         crtc_state = intel_crtc_state_alloc(crtc);
16421         if (!crtc_state) {
16422                 kfree(crtc);
16423                 return ERR_PTR(-ENOMEM);
16424         }
16425
16426         crtc->base.state = &crtc_state->uapi;
16427         crtc->config = crtc_state;
16428
16429         return crtc;
16430 }
16431
16432 static void intel_crtc_free(struct intel_crtc *crtc)
16433 {
16434         intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16435         kfree(crtc);
16436 }
16437
16438 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16439 {
16440         struct intel_plane *plane;
16441
16442         for_each_intel_plane(&dev_priv->drm, plane) {
16443                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16444                                                                   plane->pipe);
16445
16446                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16447         }
16448 }
16449
16450 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16451 {
16452         struct intel_plane *primary, *cursor;
16453         const struct drm_crtc_funcs *funcs;
16454         struct intel_crtc *crtc;
16455         int sprite, ret;
16456
16457         crtc = intel_crtc_alloc();
16458         if (IS_ERR(crtc))
16459                 return PTR_ERR(crtc);
16460
16461         crtc->pipe = pipe;
16462         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16463
16464         primary = intel_primary_plane_create(dev_priv, pipe);
16465         if (IS_ERR(primary)) {
16466                 ret = PTR_ERR(primary);
16467                 goto fail;
16468         }
16469         crtc->plane_ids_mask |= BIT(primary->id);
16470
16471         for_each_sprite(dev_priv, pipe, sprite) {
16472                 struct intel_plane *plane;
16473
16474                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16475                 if (IS_ERR(plane)) {
16476                         ret = PTR_ERR(plane);
16477                         goto fail;
16478                 }
16479                 crtc->plane_ids_mask |= BIT(plane->id);
16480         }
16481
16482         cursor = intel_cursor_plane_create(dev_priv, pipe);
16483         if (IS_ERR(cursor)) {
16484                 ret = PTR_ERR(cursor);
16485                 goto fail;
16486         }
16487         crtc->plane_ids_mask |= BIT(cursor->id);
16488
16489         if (HAS_GMCH(dev_priv)) {
16490                 if (IS_CHERRYVIEW(dev_priv) ||
16491                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16492                         funcs = &g4x_crtc_funcs;
16493                 else if (IS_GEN(dev_priv, 4))
16494                         funcs = &i965_crtc_funcs;
16495                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16496                         funcs = &i915gm_crtc_funcs;
16497                 else if (IS_GEN(dev_priv, 3))
16498                         funcs = &i915_crtc_funcs;
16499                 else
16500                         funcs = &i8xx_crtc_funcs;
16501         } else {
16502                 if (INTEL_GEN(dev_priv) >= 8)
16503                         funcs = &bdw_crtc_funcs;
16504                 else
16505                         funcs = &ilk_crtc_funcs;
16506         }
16507
16508         ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16509                                         &primary->base, &cursor->base,
16510                                         funcs, "pipe %c", pipe_name(pipe));
16511         if (ret)
16512                 goto fail;
16513
16514         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16515                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16516         dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16517
16518         if (INTEL_GEN(dev_priv) < 9) {
16519                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16520
16521                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16522                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16523                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16524         }
16525
16526         intel_color_init(crtc);
16527
16528         intel_crtc_crc_init(crtc);
16529
16530         drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16531
16532         return 0;
16533
16534 fail:
16535         intel_crtc_free(crtc);
16536
16537         return ret;
16538 }
16539
16540 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16541                                       struct drm_file *file)
16542 {
16543         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16544         struct drm_crtc *drmmode_crtc;
16545         struct intel_crtc *crtc;
16546
16547         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
16548         if (!drmmode_crtc)
16549                 return -ENOENT;
16550
16551         crtc = to_intel_crtc(drmmode_crtc);
16552         pipe_from_crtc_id->pipe = crtc->pipe;
16553
16554         return 0;
16555 }
16556
16557 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
16558 {
16559         struct drm_device *dev = encoder->base.dev;
16560         struct intel_encoder *source_encoder;
16561         u32 possible_clones = 0;
16562
16563         for_each_intel_encoder(dev, source_encoder) {
16564                 if (encoders_cloneable(encoder, source_encoder))
16565                         possible_clones |= drm_encoder_mask(&source_encoder->base);
16566         }
16567
16568         return possible_clones;
16569 }
16570
16571 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16572 {
16573         struct drm_device *dev = encoder->base.dev;
16574         struct intel_crtc *crtc;
16575         u32 possible_crtcs = 0;
16576
16577         for_each_intel_crtc(dev, crtc) {
16578                 if (encoder->pipe_mask & BIT(crtc->pipe))
16579                         possible_crtcs |= drm_crtc_mask(&crtc->base);
16580         }
16581
16582         return possible_crtcs;
16583 }
16584
16585 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16586 {
16587         if (!IS_MOBILE(dev_priv))
16588                 return false;
16589
16590         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
16591                 return false;
16592
16593         if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
16594                 return false;
16595
16596         return true;
16597 }
16598
16599 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16600 {
16601         if (INTEL_GEN(dev_priv) >= 9)
16602                 return false;
16603
16604         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16605                 return false;
16606
16607         if (HAS_PCH_LPT_H(dev_priv) &&
16608             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16609                 return false;
16610
16611         /* DDI E can't be used if DDI A requires 4 lanes */
16612         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16613                 return false;
16614
16615         if (!dev_priv->vbt.int_crt_support)
16616                 return false;
16617
16618         return true;
16619 }
16620
16621 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16622 {
16623         int pps_num;
16624         int pps_idx;
16625
16626         if (HAS_DDI(dev_priv))
16627                 return;
16628         /*
16629          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16630          * everywhere where registers can be write protected.
16631          */
16632         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16633                 pps_num = 2;
16634         else
16635                 pps_num = 1;
16636
16637         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16638                 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
16639
16640                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16641                 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
16642         }
16643 }
16644
16645 static void intel_pps_init(struct drm_i915_private *dev_priv)
16646 {
16647         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16648                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16649         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16650                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16651         else
16652                 dev_priv->pps_mmio_base = PPS_BASE;
16653
16654         intel_pps_unlock_regs_wa(dev_priv);
16655 }
16656
16657 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16658 {
16659         struct intel_encoder *encoder;
16660         bool dpd_is_edp = false;
16661
16662         intel_pps_init(dev_priv);
16663
16664         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16665                 return;
16666
16667         if (INTEL_GEN(dev_priv) >= 12) {
16668                 intel_ddi_init(dev_priv, PORT_A);
16669                 intel_ddi_init(dev_priv, PORT_B);
16670                 intel_ddi_init(dev_priv, PORT_D);
16671                 intel_ddi_init(dev_priv, PORT_E);
16672                 intel_ddi_init(dev_priv, PORT_F);
16673                 intel_ddi_init(dev_priv, PORT_G);
16674                 intel_ddi_init(dev_priv, PORT_H);
16675                 intel_ddi_init(dev_priv, PORT_I);
16676                 icl_dsi_init(dev_priv);
16677         } else if (IS_ELKHARTLAKE(dev_priv)) {
16678                 intel_ddi_init(dev_priv, PORT_A);
16679                 intel_ddi_init(dev_priv, PORT_B);
16680                 intel_ddi_init(dev_priv, PORT_C);
16681                 intel_ddi_init(dev_priv, PORT_D);
16682                 icl_dsi_init(dev_priv);
16683         } else if (IS_GEN(dev_priv, 11)) {
16684                 intel_ddi_init(dev_priv, PORT_A);
16685                 intel_ddi_init(dev_priv, PORT_B);
16686                 intel_ddi_init(dev_priv, PORT_C);
16687                 intel_ddi_init(dev_priv, PORT_D);
16688                 intel_ddi_init(dev_priv, PORT_E);
16689                 /*
16690                  * On some ICL SKUs port F is not present. No strap bits for
16691                  * this, so rely on VBT.
16692                  * Work around broken VBTs on SKUs known to have no port F.
16693                  */
16694                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16695                     intel_bios_is_port_present(dev_priv, PORT_F))
16696                         intel_ddi_init(dev_priv, PORT_F);
16697
16698                 icl_dsi_init(dev_priv);
16699         } else if (IS_GEN9_LP(dev_priv)) {
16700                 /*
16701                  * FIXME: Broxton doesn't support port detection via the
16702                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16703                  * detect the ports.
16704                  */
16705                 intel_ddi_init(dev_priv, PORT_A);
16706                 intel_ddi_init(dev_priv, PORT_B);
16707                 intel_ddi_init(dev_priv, PORT_C);
16708
16709                 vlv_dsi_init(dev_priv);
16710         } else if (HAS_DDI(dev_priv)) {
16711                 int found;
16712
16713                 if (intel_ddi_crt_present(dev_priv))
16714                         intel_crt_init(dev_priv);
16715
16716                 /*
16717                  * Haswell uses DDI functions to detect digital outputs.
16718                  * On SKL pre-D0 the strap isn't connected, so we assume
16719                  * it's there.
16720                  */
16721                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16722                 /* WaIgnoreDDIAStrap: skl */
16723                 if (found || IS_GEN9_BC(dev_priv))
16724                         intel_ddi_init(dev_priv, PORT_A);
16725
16726                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16727                  * register */
16728                 found = intel_de_read(dev_priv, SFUSE_STRAP);
16729
16730                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16731                         intel_ddi_init(dev_priv, PORT_B);
16732                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16733                         intel_ddi_init(dev_priv, PORT_C);
16734                 if (found & SFUSE_STRAP_DDID_DETECTED)
16735                         intel_ddi_init(dev_priv, PORT_D);
16736                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16737                         intel_ddi_init(dev_priv, PORT_F);
16738                 /*
16739                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16740                  */
16741                 if (IS_GEN9_BC(dev_priv) &&
16742                     intel_bios_is_port_present(dev_priv, PORT_E))
16743                         intel_ddi_init(dev_priv, PORT_E);
16744
16745         } else if (HAS_PCH_SPLIT(dev_priv)) {
16746                 int found;
16747
16748                 /*
16749                  * intel_edp_init_connector() depends on this completing first,
16750                  * to prevent the registration of both eDP and LVDS and the
16751                  * incorrect sharing of the PPS.
16752                  */
16753                 intel_lvds_init(dev_priv);
16754                 intel_crt_init(dev_priv);
16755
16756                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16757
16758                 if (ilk_has_edp_a(dev_priv))
16759                         intel_dp_init(dev_priv, DP_A, PORT_A);
16760
16761                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
16762                         /* PCH SDVOB multiplex with HDMIB */
16763                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16764                         if (!found)
16765                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16766                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
16767                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16768                 }
16769
16770                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
16771                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16772
16773                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
16774                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16775
16776                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
16777                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16778
16779                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
16780                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16781         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16782                 bool has_edp, has_port;
16783
16784                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16785                         intel_crt_init(dev_priv);
16786
16787                 /*
16788                  * The DP_DETECTED bit is the latched state of the DDC
16789                  * SDA pin at boot. However since eDP doesn't require DDC
16790                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16791                  * eDP ports may have been muxed to an alternate function.
16792                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16793                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16794                  * detect eDP ports.
16795                  *
16796                  * Sadly the straps seem to be missing sometimes even for HDMI
16797                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16798                  * and VBT for the presence of the port. Additionally we can't
16799                  * trust the port type the VBT declares as we've seen at least
16800                  * HDMI ports that the VBT claim are DP or eDP.
16801                  */
16802                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16803                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16804                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
16805                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16806                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16807                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16808
16809                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16810                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16811                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
16812                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16813                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16814                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16815
16816                 if (IS_CHERRYVIEW(dev_priv)) {
16817                         /*
16818                          * eDP not supported on port D,
16819                          * so no need to worry about it
16820                          */
16821                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16822                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
16823                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16824                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
16825                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16826                 }
16827
16828                 vlv_dsi_init(dev_priv);
16829         } else if (IS_PINEVIEW(dev_priv)) {
16830                 intel_lvds_init(dev_priv);
16831                 intel_crt_init(dev_priv);
16832         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16833                 bool found = false;
16834
16835                 if (IS_MOBILE(dev_priv))
16836                         intel_lvds_init(dev_priv);
16837
16838                 intel_crt_init(dev_priv);
16839
16840                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
16841                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
16842                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16843                         if (!found && IS_G4X(dev_priv)) {
16844                                 drm_dbg_kms(&dev_priv->drm,
16845                                             "probing HDMI on SDVOB\n");
16846                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16847                         }
16848
16849                         if (!found && IS_G4X(dev_priv))
16850                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16851                 }
16852
16853                 /* Before G4X SDVOC doesn't have its own detect register */
16854
16855                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
16856                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
16857                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16858                 }
16859
16860                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
16861
16862                         if (IS_G4X(dev_priv)) {
16863                                 drm_dbg_kms(&dev_priv->drm,
16864                                             "probing HDMI on SDVOC\n");
16865                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16866                         }
16867                         if (IS_G4X(dev_priv))
16868                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16869                 }
16870
16871                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
16872                         intel_dp_init(dev_priv, DP_D, PORT_D);
16873
16874                 if (SUPPORTS_TV(dev_priv))
16875                         intel_tv_init(dev_priv);
16876         } else if (IS_GEN(dev_priv, 2)) {
16877                 if (IS_I85X(dev_priv))
16878                         intel_lvds_init(dev_priv);
16879
16880                 intel_crt_init(dev_priv);
16881                 intel_dvo_init(dev_priv);
16882         }
16883
16884         intel_psr_init(dev_priv);
16885
16886         for_each_intel_encoder(&dev_priv->drm, encoder) {
16887                 encoder->base.possible_crtcs =
16888                         intel_encoder_possible_crtcs(encoder);
16889                 encoder->base.possible_clones =
16890                         intel_encoder_possible_clones(encoder);
16891         }
16892
16893         intel_init_pch_refclk(dev_priv);
16894
16895         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16896 }
16897
16898 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16899 {
16900         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16901
16902         drm_framebuffer_cleanup(fb);
16903         intel_frontbuffer_put(intel_fb->frontbuffer);
16904
16905         kfree(intel_fb);
16906 }
16907
16908 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16909                                                 struct drm_file *file,
16910                                                 unsigned int *handle)
16911 {
16912         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16913         struct drm_i915_private *i915 = to_i915(obj->base.dev);
16914
16915         if (obj->userptr.mm) {
16916                 drm_dbg(&i915->drm,
16917                         "attempting to use a userptr for a framebuffer, denied\n");
16918                 return -EINVAL;
16919         }
16920
16921         return drm_gem_handle_create(file, &obj->base, handle);
16922 }
16923
16924 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16925                                         struct drm_file *file,
16926                                         unsigned flags, unsigned color,
16927                                         struct drm_clip_rect *clips,
16928                                         unsigned num_clips)
16929 {
16930         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16931
16932         i915_gem_object_flush_if_display(obj);
16933         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16934
16935         return 0;
16936 }
16937
16938 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16939         .destroy = intel_user_framebuffer_destroy,
16940         .create_handle = intel_user_framebuffer_create_handle,
16941         .dirty = intel_user_framebuffer_dirty,
16942 };
16943
16944 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16945                                   struct drm_i915_gem_object *obj,
16946                                   struct drm_mode_fb_cmd2 *mode_cmd)
16947 {
16948         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16949         struct drm_framebuffer *fb = &intel_fb->base;
16950         u32 max_stride;
16951         unsigned int tiling, stride;
16952         int ret = -EINVAL;
16953         int i;
16954
16955         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16956         if (!intel_fb->frontbuffer)
16957                 return -ENOMEM;
16958
16959         i915_gem_object_lock(obj);
16960         tiling = i915_gem_object_get_tiling(obj);
16961         stride = i915_gem_object_get_stride(obj);
16962         i915_gem_object_unlock(obj);
16963
16964         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16965                 /*
16966                  * If there's a fence, enforce that
16967                  * the fb modifier and tiling mode match.
16968                  */
16969                 if (tiling != I915_TILING_NONE &&
16970                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16971                         drm_dbg_kms(&dev_priv->drm,
16972                                     "tiling_mode doesn't match fb modifier\n");
16973                         goto err;
16974                 }
16975         } else {
16976                 if (tiling == I915_TILING_X) {
16977                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16978                 } else if (tiling == I915_TILING_Y) {
16979                         drm_dbg_kms(&dev_priv->drm,
16980                                     "No Y tiling for legacy addfb\n");
16981                         goto err;
16982                 }
16983         }
16984
16985         if (!drm_any_plane_has_format(&dev_priv->drm,
16986                                       mode_cmd->pixel_format,
16987                                       mode_cmd->modifier[0])) {
16988                 struct drm_format_name_buf format_name;
16989
16990                 drm_dbg_kms(&dev_priv->drm,
16991                             "unsupported pixel format %s / modifier 0x%llx\n",
16992                             drm_get_format_name(mode_cmd->pixel_format,
16993                                                 &format_name),
16994                             mode_cmd->modifier[0]);
16995                 goto err;
16996         }
16997
16998         /*
16999          * gen2/3 display engine uses the fence if present,
17000          * so the tiling mode must match the fb modifier exactly.
17001          */
17002         if (INTEL_GEN(dev_priv) < 4 &&
17003             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17004                 drm_dbg_kms(&dev_priv->drm,
17005                             "tiling_mode must match fb modifier exactly on gen2/3\n");
17006                 goto err;
17007         }
17008
17009         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17010                                          mode_cmd->modifier[0]);
17011         if (mode_cmd->pitches[0] > max_stride) {
17012                 drm_dbg_kms(&dev_priv->drm,
17013                             "%s pitch (%u) must be at most %d\n",
17014                             mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17015                             "tiled" : "linear",
17016                             mode_cmd->pitches[0], max_stride);
17017                 goto err;
17018         }
17019
17020         /*
17021          * If there's a fence, enforce that
17022          * the fb pitch and fence stride match.
17023          */
17024         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17025                 drm_dbg_kms(&dev_priv->drm,
17026                             "pitch (%d) must match tiling stride (%d)\n",
17027                             mode_cmd->pitches[0], stride);
17028                 goto err;
17029         }
17030
17031         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17032         if (mode_cmd->offsets[0] != 0) {
17033                 drm_dbg_kms(&dev_priv->drm,
17034                             "plane 0 offset (0x%08x) must be 0\n",
17035                             mode_cmd->offsets[0]);
17036                 goto err;
17037         }
17038
17039         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17040
17041         for (i = 0; i < fb->format->num_planes; i++) {
17042                 u32 stride_alignment;
17043
17044                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17045                         drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17046                                     i);
17047                         goto err;
17048                 }
17049
17050                 stride_alignment = intel_fb_stride_alignment(fb, i);
17051                 if (fb->pitches[i] & (stride_alignment - 1)) {
17052                         drm_dbg_kms(&dev_priv->drm,
17053                                     "plane %d pitch (%d) must be at least %u byte aligned\n",
17054                                     i, fb->pitches[i], stride_alignment);
17055                         goto err;
17056                 }
17057
17058                 if (is_gen12_ccs_plane(fb, i)) {
17059                         int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17060
17061                         if (fb->pitches[i] != ccs_aux_stride) {
17062                                 drm_dbg_kms(&dev_priv->drm,
17063                                             "ccs aux plane %d pitch (%d) must be %d\n",
17064                                             i,
17065                                             fb->pitches[i], ccs_aux_stride);
17066                                 goto err;
17067                         }
17068                 }
17069
17070                 fb->obj[i] = &obj->base;
17071         }
17072
17073         ret = intel_fill_fb_info(dev_priv, fb);
17074         if (ret)
17075                 goto err;
17076
17077         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17078         if (ret) {
17079                 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17080                 goto err;
17081         }
17082
17083         return 0;
17084
17085 err:
17086         intel_frontbuffer_put(intel_fb->frontbuffer);
17087         return ret;
17088 }
17089
17090 static struct drm_framebuffer *
17091 intel_user_framebuffer_create(struct drm_device *dev,
17092                               struct drm_file *filp,
17093                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
17094 {
17095         struct drm_framebuffer *fb;
17096         struct drm_i915_gem_object *obj;
17097         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17098
17099         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17100         if (!obj)
17101                 return ERR_PTR(-ENOENT);
17102
17103         fb = intel_framebuffer_create(obj, &mode_cmd);
17104         i915_gem_object_put(obj);
17105
17106         return fb;
17107 }
17108
17109 static enum drm_mode_status
17110 intel_mode_valid(struct drm_device *dev,
17111                  const struct drm_display_mode *mode)
17112 {
17113         struct drm_i915_private *dev_priv = to_i915(dev);
17114         int hdisplay_max, htotal_max;
17115         int vdisplay_max, vtotal_max;
17116
17117         /*
17118          * Can't reject DBLSCAN here because Xorg ddxen can add piles
17119          * of DBLSCAN modes to the output's mode list when they detect
17120          * the scaling mode property on the connector. And they don't
17121          * ask the kernel to validate those modes in any way until
17122          * modeset time at which point the client gets a protocol error.
17123          * So in order to not upset those clients we silently ignore the
17124          * DBLSCAN flag on such connectors. For other connectors we will
17125          * reject modes with the DBLSCAN flag in encoder->compute_config().
17126          * And we always reject DBLSCAN modes in connector->mode_valid()
17127          * as we never want such modes on the connector's mode list.
17128          */
17129
17130         if (mode->vscan > 1)
17131                 return MODE_NO_VSCAN;
17132
17133         if (mode->flags & DRM_MODE_FLAG_HSKEW)
17134                 return MODE_H_ILLEGAL;
17135
17136         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17137                            DRM_MODE_FLAG_NCSYNC |
17138                            DRM_MODE_FLAG_PCSYNC))
17139                 return MODE_HSYNC;
17140
17141         if (mode->flags & (DRM_MODE_FLAG_BCAST |
17142                            DRM_MODE_FLAG_PIXMUX |
17143                            DRM_MODE_FLAG_CLKDIV2))
17144                 return MODE_BAD;
17145
17146         /* Transcoder timing limits */
17147         if (INTEL_GEN(dev_priv) >= 11) {
17148                 hdisplay_max = 16384;
17149                 vdisplay_max = 8192;
17150                 htotal_max = 16384;
17151                 vtotal_max = 8192;
17152         } else if (INTEL_GEN(dev_priv) >= 9 ||
17153                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17154                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17155                 vdisplay_max = 4096;
17156                 htotal_max = 8192;
17157                 vtotal_max = 8192;
17158         } else if (INTEL_GEN(dev_priv) >= 3) {
17159                 hdisplay_max = 4096;
17160                 vdisplay_max = 4096;
17161                 htotal_max = 8192;
17162                 vtotal_max = 8192;
17163         } else {
17164                 hdisplay_max = 2048;
17165                 vdisplay_max = 2048;
17166                 htotal_max = 4096;
17167                 vtotal_max = 4096;
17168         }
17169
17170         if (mode->hdisplay > hdisplay_max ||
17171             mode->hsync_start > htotal_max ||
17172             mode->hsync_end > htotal_max ||
17173             mode->htotal > htotal_max)
17174                 return MODE_H_ILLEGAL;
17175
17176         if (mode->vdisplay > vdisplay_max ||
17177             mode->vsync_start > vtotal_max ||
17178             mode->vsync_end > vtotal_max ||
17179             mode->vtotal > vtotal_max)
17180                 return MODE_V_ILLEGAL;
17181
17182         if (INTEL_GEN(dev_priv) >= 5) {
17183                 if (mode->hdisplay < 64 ||
17184                     mode->htotal - mode->hdisplay < 32)
17185                         return MODE_H_ILLEGAL;
17186
17187                 if (mode->vtotal - mode->vdisplay < 5)
17188                         return MODE_V_ILLEGAL;
17189         } else {
17190                 if (mode->htotal - mode->hdisplay < 32)
17191                         return MODE_H_ILLEGAL;
17192
17193                 if (mode->vtotal - mode->vdisplay < 3)
17194                         return MODE_V_ILLEGAL;
17195         }
17196
17197         return MODE_OK;
17198 }
17199
17200 enum drm_mode_status
17201 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17202                                 const struct drm_display_mode *mode)
17203 {
17204         int plane_width_max, plane_height_max;
17205
17206         /*
17207          * intel_mode_valid() should be
17208          * sufficient on older platforms.
17209          */
17210         if (INTEL_GEN(dev_priv) < 9)
17211                 return MODE_OK;
17212
17213         /*
17214          * Most people will probably want a fullscreen
17215          * plane so let's not advertize modes that are
17216          * too big for that.
17217          */
17218         if (INTEL_GEN(dev_priv) >= 11) {
17219                 plane_width_max = 5120;
17220                 plane_height_max = 4320;
17221         } else {
17222                 plane_width_max = 5120;
17223                 plane_height_max = 4096;
17224         }
17225
17226         if (mode->hdisplay > plane_width_max)
17227                 return MODE_H_ILLEGAL;
17228
17229         if (mode->vdisplay > plane_height_max)
17230                 return MODE_V_ILLEGAL;
17231
17232         return MODE_OK;
17233 }
17234
17235 static const struct drm_mode_config_funcs intel_mode_funcs = {
17236         .fb_create = intel_user_framebuffer_create,
17237         .get_format_info = intel_get_format_info,
17238         .output_poll_changed = intel_fbdev_output_poll_changed,
17239         .mode_valid = intel_mode_valid,
17240         .atomic_check = intel_atomic_check,
17241         .atomic_commit = intel_atomic_commit,
17242         .atomic_state_alloc = intel_atomic_state_alloc,
17243         .atomic_state_clear = intel_atomic_state_clear,
17244         .atomic_state_free = intel_atomic_state_free,
17245 };
17246
17247 /**
17248  * intel_init_display_hooks - initialize the display modesetting hooks
17249  * @dev_priv: device private
17250  */
17251 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17252 {
17253         intel_init_cdclk_hooks(dev_priv);
17254
17255         if (INTEL_GEN(dev_priv) >= 9) {
17256                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17257                 dev_priv->display.get_initial_plane_config =
17258                         skl_get_initial_plane_config;
17259                 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17260                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17261                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17262         } else if (HAS_DDI(dev_priv)) {
17263                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17264                 dev_priv->display.get_initial_plane_config =
17265                         i9xx_get_initial_plane_config;
17266                 dev_priv->display.crtc_compute_clock =
17267                         hsw_crtc_compute_clock;
17268                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17269                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17270         } else if (HAS_PCH_SPLIT(dev_priv)) {
17271                 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17272                 dev_priv->display.get_initial_plane_config =
17273                         i9xx_get_initial_plane_config;
17274                 dev_priv->display.crtc_compute_clock =
17275                         ilk_crtc_compute_clock;
17276                 dev_priv->display.crtc_enable = ilk_crtc_enable;
17277                 dev_priv->display.crtc_disable = ilk_crtc_disable;
17278         } else if (IS_CHERRYVIEW(dev_priv)) {
17279                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17280                 dev_priv->display.get_initial_plane_config =
17281                         i9xx_get_initial_plane_config;
17282                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17283                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17284                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17285         } else if (IS_VALLEYVIEW(dev_priv)) {
17286                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17287                 dev_priv->display.get_initial_plane_config =
17288                         i9xx_get_initial_plane_config;
17289                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17290                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17291                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17292         } else if (IS_G4X(dev_priv)) {
17293                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17294                 dev_priv->display.get_initial_plane_config =
17295                         i9xx_get_initial_plane_config;
17296                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17297                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17298                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17299         } else if (IS_PINEVIEW(dev_priv)) {
17300                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17301                 dev_priv->display.get_initial_plane_config =
17302                         i9xx_get_initial_plane_config;
17303                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17304                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17305                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17306         } else if (!IS_GEN(dev_priv, 2)) {
17307                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17308                 dev_priv->display.get_initial_plane_config =
17309                         i9xx_get_initial_plane_config;
17310                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17311                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17312                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17313         } else {
17314                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17315                 dev_priv->display.get_initial_plane_config =
17316                         i9xx_get_initial_plane_config;
17317                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17318                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17319                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17320         }
17321
17322         if (IS_GEN(dev_priv, 5)) {
17323                 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17324         } else if (IS_GEN(dev_priv, 6)) {
17325                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17326         } else if (IS_IVYBRIDGE(dev_priv)) {
17327                 /* FIXME: detect B0+ stepping and use auto training */
17328                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17329         }
17330
17331         if (INTEL_GEN(dev_priv) >= 9)
17332                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17333         else
17334                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17335
17336 }
17337
17338 void intel_modeset_init_hw(struct drm_i915_private *i915)
17339 {
17340         struct intel_cdclk_state *cdclk_state =
17341                 to_intel_cdclk_state(i915->cdclk.obj.state);
17342
17343         intel_update_cdclk(i915);
17344         intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17345         cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17346 }
17347
17348 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17349 {
17350         struct drm_plane *plane;
17351         struct drm_crtc *crtc;
17352
17353         drm_for_each_crtc(crtc, state->dev) {
17354                 struct drm_crtc_state *crtc_state;
17355
17356                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
17357                 if (IS_ERR(crtc_state))
17358                         return PTR_ERR(crtc_state);
17359         }
17360
17361         drm_for_each_plane(plane, state->dev) {
17362                 struct drm_plane_state *plane_state;
17363
17364                 plane_state = drm_atomic_get_plane_state(state, plane);
17365                 if (IS_ERR(plane_state))
17366                         return PTR_ERR(plane_state);
17367         }
17368
17369         return 0;
17370 }
17371
17372 /*
17373  * Calculate what we think the watermarks should be for the state we've read
17374  * out of the hardware and then immediately program those watermarks so that
17375  * we ensure the hardware settings match our internal state.
17376  *
17377  * We can calculate what we think WM's should be by creating a duplicate of the
17378  * current state (which was constructed during hardware readout) and running it
17379  * through the atomic check code to calculate new watermark values in the
17380  * state object.
17381  */
17382 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17383 {
17384         struct drm_atomic_state *state;
17385         struct intel_atomic_state *intel_state;
17386         struct intel_crtc *crtc;
17387         struct intel_crtc_state *crtc_state;
17388         struct drm_modeset_acquire_ctx ctx;
17389         int ret;
17390         int i;
17391
17392         /* Only supported on platforms that use atomic watermark design */
17393         if (!dev_priv->display.optimize_watermarks)
17394                 return;
17395
17396         state = drm_atomic_state_alloc(&dev_priv->drm);
17397         if (drm_WARN_ON(&dev_priv->drm, !state))
17398                 return;
17399
17400         intel_state = to_intel_atomic_state(state);
17401
17402         drm_modeset_acquire_init(&ctx, 0);
17403
17404 retry:
17405         state->acquire_ctx = &ctx;
17406
17407         /*
17408          * Hardware readout is the only time we don't want to calculate
17409          * intermediate watermarks (since we don't trust the current
17410          * watermarks).
17411          */
17412         if (!HAS_GMCH(dev_priv))
17413                 intel_state->skip_intermediate_wm = true;
17414
17415         ret = sanitize_watermarks_add_affected(state);
17416         if (ret)
17417                 goto fail;
17418
17419         ret = intel_atomic_check(&dev_priv->drm, state);
17420         if (ret)
17421                 goto fail;
17422
17423         /* Write calculated watermark values back */
17424         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17425                 crtc_state->wm.need_postvbl_update = true;
17426                 dev_priv->display.optimize_watermarks(intel_state, crtc);
17427
17428                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17429         }
17430
17431 fail:
17432         if (ret == -EDEADLK) {
17433                 drm_atomic_state_clear(state);
17434                 drm_modeset_backoff(&ctx);
17435                 goto retry;
17436         }
17437
17438         /*
17439          * If we fail here, it means that the hardware appears to be
17440          * programmed in a way that shouldn't be possible, given our
17441          * understanding of watermark requirements.  This might mean a
17442          * mistake in the hardware readout code or a mistake in the
17443          * watermark calculations for a given platform.  Raise a WARN
17444          * so that this is noticeable.
17445          *
17446          * If this actually happens, we'll have to just leave the
17447          * BIOS-programmed watermarks untouched and hope for the best.
17448          */
17449         drm_WARN(&dev_priv->drm, ret,
17450                  "Could not determine valid watermarks for inherited state\n");
17451
17452         drm_atomic_state_put(state);
17453
17454         drm_modeset_drop_locks(&ctx);
17455         drm_modeset_acquire_fini(&ctx);
17456 }
17457
17458 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17459 {
17460         if (IS_GEN(dev_priv, 5)) {
17461                 u32 fdi_pll_clk =
17462                         intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17463
17464                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17465         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17466                 dev_priv->fdi_pll_freq = 270000;
17467         } else {
17468                 return;
17469         }
17470
17471         drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17472 }
17473
17474 static int intel_initial_commit(struct drm_device *dev)
17475 {
17476         struct drm_atomic_state *state = NULL;
17477         struct drm_modeset_acquire_ctx ctx;
17478         struct intel_crtc *crtc;
17479         int ret = 0;
17480
17481         state = drm_atomic_state_alloc(dev);
17482         if (!state)
17483                 return -ENOMEM;
17484
17485         drm_modeset_acquire_init(&ctx, 0);
17486
17487 retry:
17488         state->acquire_ctx = &ctx;
17489
17490         for_each_intel_crtc(dev, crtc) {
17491                 struct intel_crtc_state *crtc_state =
17492                         intel_atomic_get_crtc_state(state, crtc);
17493
17494                 if (IS_ERR(crtc_state)) {
17495                         ret = PTR_ERR(crtc_state);
17496                         goto out;
17497                 }
17498
17499                 if (crtc_state->hw.active) {
17500                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
17501                         if (ret)
17502                                 goto out;
17503
17504                         /*
17505                          * FIXME hack to force a LUT update to avoid the
17506                          * plane update forcing the pipe gamma on without
17507                          * having a proper LUT loaded. Remove once we
17508                          * have readout for pipe gamma enable.
17509                          */
17510                         crtc_state->uapi.color_mgmt_changed = true;
17511
17512                         /*
17513                          * FIXME hack to force full modeset when DSC is being
17514                          * used.
17515                          *
17516                          * As long as we do not have full state readout and
17517                          * config comparison of crtc_state->dsc, we have no way
17518                          * to ensure reliable fastset. Remove once we have
17519                          * readout for DSC.
17520                          */
17521                         if (crtc_state->dsc.compression_enable) {
17522                                 ret = drm_atomic_add_affected_connectors(state,
17523                                                                          &crtc->base);
17524                                 if (ret)
17525                                         goto out;
17526                                 crtc_state->uapi.mode_changed = true;
17527                                 drm_dbg_kms(dev, "Force full modeset for DSC\n");
17528                         }
17529                 }
17530         }
17531
17532         ret = drm_atomic_commit(state);
17533
17534 out:
17535         if (ret == -EDEADLK) {
17536                 drm_atomic_state_clear(state);
17537                 drm_modeset_backoff(&ctx);
17538                 goto retry;
17539         }
17540
17541         drm_atomic_state_put(state);
17542
17543         drm_modeset_drop_locks(&ctx);
17544         drm_modeset_acquire_fini(&ctx);
17545
17546         return ret;
17547 }
17548
17549 static void intel_mode_config_init(struct drm_i915_private *i915)
17550 {
17551         struct drm_mode_config *mode_config = &i915->drm.mode_config;
17552
17553         drm_mode_config_init(&i915->drm);
17554         INIT_LIST_HEAD(&i915->global_obj_list);
17555
17556         mode_config->min_width = 0;
17557         mode_config->min_height = 0;
17558
17559         mode_config->preferred_depth = 24;
17560         mode_config->prefer_shadow = 1;
17561
17562         mode_config->allow_fb_modifiers = true;
17563
17564         mode_config->funcs = &intel_mode_funcs;
17565
17566         /*
17567          * Maximum framebuffer dimensions, chosen to match
17568          * the maximum render engine surface size on gen4+.
17569          */
17570         if (INTEL_GEN(i915) >= 7) {
17571                 mode_config->max_width = 16384;
17572                 mode_config->max_height = 16384;
17573         } else if (INTEL_GEN(i915) >= 4) {
17574                 mode_config->max_width = 8192;
17575                 mode_config->max_height = 8192;
17576         } else if (IS_GEN(i915, 3)) {
17577                 mode_config->max_width = 4096;
17578                 mode_config->max_height = 4096;
17579         } else {
17580                 mode_config->max_width = 2048;
17581                 mode_config->max_height = 2048;
17582         }
17583
17584         if (IS_I845G(i915) || IS_I865G(i915)) {
17585                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
17586                 mode_config->cursor_height = 1023;
17587         } else if (IS_GEN(i915, 2)) {
17588                 mode_config->cursor_width = 64;
17589                 mode_config->cursor_height = 64;
17590         } else {
17591                 mode_config->cursor_width = 256;
17592                 mode_config->cursor_height = 256;
17593         }
17594 }
17595
17596 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
17597 {
17598         intel_atomic_global_obj_cleanup(i915);
17599         drm_mode_config_cleanup(&i915->drm);
17600 }
17601
17602 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
17603 {
17604         if (plane_config->fb) {
17605                 struct drm_framebuffer *fb = &plane_config->fb->base;
17606
17607                 /* We may only have the stub and not a full framebuffer */
17608                 if (drm_framebuffer_read_refcount(fb))
17609                         drm_framebuffer_put(fb);
17610                 else
17611                         kfree(fb);
17612         }
17613
17614         if (plane_config->vma)
17615                 i915_vma_put(plane_config->vma);
17616 }
17617
17618 /* part #1: call before irq install */
17619 int intel_modeset_init_noirq(struct drm_i915_private *i915)
17620 {
17621         int ret;
17622
17623         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
17624         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
17625                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
17626
17627         intel_mode_config_init(i915);
17628
17629         ret = intel_cdclk_init(i915);
17630         if (ret)
17631                 return ret;
17632
17633         ret = intel_bw_init(i915);
17634         if (ret)
17635                 return ret;
17636
17637         init_llist_head(&i915->atomic_helper.free_list);
17638         INIT_WORK(&i915->atomic_helper.free_work,
17639                   intel_atomic_helper_free_state_worker);
17640
17641         intel_init_quirks(i915);
17642
17643         intel_fbc_init(i915);
17644
17645         return 0;
17646 }
17647
17648 /* part #2: call after irq install */
17649 int intel_modeset_init(struct drm_i915_private *i915)
17650 {
17651         struct drm_device *dev = &i915->drm;
17652         enum pipe pipe;
17653         struct intel_crtc *crtc;
17654         int ret;
17655
17656         intel_init_pm(i915);
17657
17658         intel_panel_sanitize_ssc(i915);
17659
17660         intel_gmbus_setup(i915);
17661
17662         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
17663                     INTEL_NUM_PIPES(i915),
17664                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17665
17666         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
17667                 for_each_pipe(i915, pipe) {
17668                         ret = intel_crtc_init(i915, pipe);
17669                         if (ret) {
17670                                 intel_mode_config_cleanup(i915);
17671                                 return ret;
17672                         }
17673                 }
17674         }
17675
17676         intel_plane_possible_crtcs_init(i915);
17677         intel_shared_dpll_init(dev);
17678         intel_update_fdi_pll_freq(i915);
17679
17680         intel_update_czclk(i915);
17681         intel_modeset_init_hw(i915);
17682
17683         intel_hdcp_component_init(i915);
17684
17685         if (i915->max_cdclk_freq == 0)
17686                 intel_update_max_cdclk(i915);
17687
17688         /* Just disable it once at startup */
17689         intel_vga_disable(i915);
17690         intel_setup_outputs(i915);
17691
17692         drm_modeset_lock_all(dev);
17693         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17694         drm_modeset_unlock_all(dev);
17695
17696         for_each_intel_crtc(dev, crtc) {
17697                 struct intel_initial_plane_config plane_config = {};
17698
17699                 if (!crtc->active)
17700                         continue;
17701
17702                 /*
17703                  * Note that reserving the BIOS fb up front prevents us
17704                  * from stuffing other stolen allocations like the ring
17705                  * on top.  This prevents some ugliness at boot time, and
17706                  * can even allow for smooth boot transitions if the BIOS
17707                  * fb is large enough for the active pipe configuration.
17708                  */
17709                 i915->display.get_initial_plane_config(crtc, &plane_config);
17710
17711                 /*
17712                  * If the fb is shared between multiple heads, we'll
17713                  * just get the first one.
17714                  */
17715                 intel_find_initial_plane_obj(crtc, &plane_config);
17716
17717                 plane_config_fini(&plane_config);
17718         }
17719
17720         /*
17721          * Make sure hardware watermarks really match the state we read out.
17722          * Note that we need to do this after reconstructing the BIOS fb's
17723          * since the watermark calculation done here will use pstate->fb.
17724          */
17725         if (!HAS_GMCH(i915))
17726                 sanitize_watermarks(i915);
17727
17728         /*
17729          * Force all active planes to recompute their states. So that on
17730          * mode_setcrtc after probe, all the intel_plane_state variables
17731          * are already calculated and there is no assert_plane warnings
17732          * during bootup.
17733          */
17734         ret = intel_initial_commit(dev);
17735         if (ret)
17736                 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
17737
17738         return 0;
17739 }
17740
17741 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17742 {
17743         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17744         /* 640x480@60Hz, ~25175 kHz */
17745         struct dpll clock = {
17746                 .m1 = 18,
17747                 .m2 = 7,
17748                 .p1 = 13,
17749                 .p2 = 4,
17750                 .n = 2,
17751         };
17752         u32 dpll, fp;
17753         int i;
17754
17755         drm_WARN_ON(&dev_priv->drm,
17756                     i9xx_calc_dpll_params(48000, &clock) != 25154);
17757
17758         drm_dbg_kms(&dev_priv->drm,
17759                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17760                     pipe_name(pipe), clock.vco, clock.dot);
17761
17762         fp = i9xx_dpll_compute_fp(&clock);
17763         dpll = DPLL_DVO_2X_MODE |
17764                 DPLL_VGA_MODE_DIS |
17765                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17766                 PLL_P2_DIVIDE_BY_4 |
17767                 PLL_REF_INPUT_DREFCLK |
17768                 DPLL_VCO_ENABLE;
17769
17770         intel_de_write(dev_priv, FP0(pipe), fp);
17771         intel_de_write(dev_priv, FP1(pipe), fp);
17772
17773         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17774         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17775         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17776         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17777         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17778         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17779         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17780
17781         /*
17782          * Apparently we need to have VGA mode enabled prior to changing
17783          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17784          * dividers, even though the register value does change.
17785          */
17786         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17787         intel_de_write(dev_priv, DPLL(pipe), dpll);
17788
17789         /* Wait for the clocks to stabilize. */
17790         intel_de_posting_read(dev_priv, DPLL(pipe));
17791         udelay(150);
17792
17793         /* The pixel multiplier can only be updated once the
17794          * DPLL is enabled and the clocks are stable.
17795          *
17796          * So write it again.
17797          */
17798         intel_de_write(dev_priv, DPLL(pipe), dpll);
17799
17800         /* We do this three times for luck */
17801         for (i = 0; i < 3 ; i++) {
17802                 intel_de_write(dev_priv, DPLL(pipe), dpll);
17803                 intel_de_posting_read(dev_priv, DPLL(pipe));
17804                 udelay(150); /* wait for warmup */
17805         }
17806
17807         intel_de_write(dev_priv, PIPECONF(pipe),
17808                        PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17809         intel_de_posting_read(dev_priv, PIPECONF(pipe));
17810
17811         intel_wait_for_pipe_scanline_moving(crtc);
17812 }
17813
17814 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17815 {
17816         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17817
17818         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
17819                     pipe_name(pipe));
17820
17821         drm_WARN_ON(&dev_priv->drm,
17822                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
17823                     DISPLAY_PLANE_ENABLE);
17824         drm_WARN_ON(&dev_priv->drm,
17825                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
17826                     DISPLAY_PLANE_ENABLE);
17827         drm_WARN_ON(&dev_priv->drm,
17828                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
17829                     DISPLAY_PLANE_ENABLE);
17830         drm_WARN_ON(&dev_priv->drm,
17831                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
17832         drm_WARN_ON(&dev_priv->drm,
17833                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
17834
17835         intel_de_write(dev_priv, PIPECONF(pipe), 0);
17836         intel_de_posting_read(dev_priv, PIPECONF(pipe));
17837
17838         intel_wait_for_pipe_scanline_stopped(crtc);
17839
17840         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
17841         intel_de_posting_read(dev_priv, DPLL(pipe));
17842 }
17843
17844 static void
17845 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17846 {
17847         struct intel_crtc *crtc;
17848
17849         if (INTEL_GEN(dev_priv) >= 4)
17850                 return;
17851
17852         for_each_intel_crtc(&dev_priv->drm, crtc) {
17853                 struct intel_plane *plane =
17854                         to_intel_plane(crtc->base.primary);
17855                 struct intel_crtc *plane_crtc;
17856                 enum pipe pipe;
17857
17858                 if (!plane->get_hw_state(plane, &pipe))
17859                         continue;
17860
17861                 if (pipe == crtc->pipe)
17862                         continue;
17863
17864                 drm_dbg_kms(&dev_priv->drm,
17865                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17866                             plane->base.base.id, plane->base.name);
17867
17868                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17869                 intel_plane_disable_noatomic(plane_crtc, plane);
17870         }
17871 }
17872
17873 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17874 {
17875         struct drm_device *dev = crtc->base.dev;
17876         struct intel_encoder *encoder;
17877
17878         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17879                 return true;
17880
17881         return false;
17882 }
17883
17884 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17885 {
17886         struct drm_device *dev = encoder->base.dev;
17887         struct intel_connector *connector;
17888
17889         for_each_connector_on_encoder(dev, &encoder->base, connector)
17890                 return connector;
17891
17892         return NULL;
17893 }
17894
17895 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17896                               enum pipe pch_transcoder)
17897 {
17898         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17899                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17900 }
17901
17902 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
17903 {
17904         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
17905         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
17906         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17907
17908         if (INTEL_GEN(dev_priv) >= 9 ||
17909             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17910                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
17911                 u32 val;
17912
17913                 if (transcoder_is_dsi(cpu_transcoder))
17914                         return;
17915
17916                 val = intel_de_read(dev_priv, reg);
17917                 val &= ~HSW_FRAME_START_DELAY_MASK;
17918                 val |= HSW_FRAME_START_DELAY(0);
17919                 intel_de_write(dev_priv, reg, val);
17920         } else {
17921                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17922                 u32 val;
17923
17924                 val = intel_de_read(dev_priv, reg);
17925                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
17926                 val |= PIPECONF_FRAME_START_DELAY(0);
17927                 intel_de_write(dev_priv, reg, val);
17928         }
17929
17930         if (!crtc_state->has_pch_encoder)
17931                 return;
17932
17933         if (HAS_PCH_IBX(dev_priv)) {
17934                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
17935                 u32 val;
17936
17937                 val = intel_de_read(dev_priv, reg);
17938                 val &= ~TRANS_FRAME_START_DELAY_MASK;
17939                 val |= TRANS_FRAME_START_DELAY(0);
17940                 intel_de_write(dev_priv, reg, val);
17941         } else {
17942                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
17943                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
17944                 u32 val;
17945
17946                 val = intel_de_read(dev_priv, reg);
17947                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
17948                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
17949                 intel_de_write(dev_priv, reg, val);
17950         }
17951 }
17952
17953 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17954                                 struct drm_modeset_acquire_ctx *ctx)
17955 {
17956         struct drm_device *dev = crtc->base.dev;
17957         struct drm_i915_private *dev_priv = to_i915(dev);
17958         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17959
17960         if (crtc_state->hw.active) {
17961                 struct intel_plane *plane;
17962
17963                 /* Clear any frame start delays used for debugging left by the BIOS */
17964                 intel_sanitize_frame_start_delay(crtc_state);
17965
17966                 /* Disable everything but the primary plane */
17967                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17968                         const struct intel_plane_state *plane_state =
17969                                 to_intel_plane_state(plane->base.state);
17970
17971                         if (plane_state->uapi.visible &&
17972                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17973                                 intel_plane_disable_noatomic(crtc, plane);
17974                 }
17975
17976                 /*
17977                  * Disable any background color set by the BIOS, but enable the
17978                  * gamma and CSC to match how we program our planes.
17979                  */
17980                 if (INTEL_GEN(dev_priv) >= 9)
17981                         intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
17982                                        SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
17983         }
17984
17985         /* Adjust the state of the output pipe according to whether we
17986          * have active connectors/encoders. */
17987         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17988                 intel_crtc_disable_noatomic(crtc, ctx);
17989
17990         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17991                 /*
17992                  * We start out with underrun reporting disabled to avoid races.
17993                  * For correct bookkeeping mark this on active crtcs.
17994                  *
17995                  * Also on gmch platforms we dont have any hardware bits to
17996                  * disable the underrun reporting. Which means we need to start
17997                  * out with underrun reporting disabled also on inactive pipes,
17998                  * since otherwise we'll complain about the garbage we read when
17999                  * e.g. coming up after runtime pm.
18000                  *
18001                  * No protection against concurrent access is required - at
18002                  * worst a fifo underrun happens which also sets this to false.
18003                  */
18004                 crtc->cpu_fifo_underrun_disabled = true;
18005                 /*
18006                  * We track the PCH trancoder underrun reporting state
18007                  * within the crtc. With crtc for pipe A housing the underrun
18008                  * reporting state for PCH transcoder A, crtc for pipe B housing
18009                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18010                  * and marking underrun reporting as disabled for the non-existing
18011                  * PCH transcoders B and C would prevent enabling the south
18012                  * error interrupt (see cpt_can_enable_serr_int()).
18013                  */
18014                 if (has_pch_trancoder(dev_priv, crtc->pipe))
18015                         crtc->pch_fifo_underrun_disabled = true;
18016         }
18017 }
18018
18019 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18020 {
18021         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18022
18023         /*
18024          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18025          * the hardware when a high res displays plugged in. DPLL P
18026          * divider is zero, and the pipe timings are bonkers. We'll
18027          * try to disable everything in that case.
18028          *
18029          * FIXME would be nice to be able to sanitize this state
18030          * without several WARNs, but for now let's take the easy
18031          * road.
18032          */
18033         return IS_GEN(dev_priv, 6) &&
18034                 crtc_state->hw.active &&
18035                 crtc_state->shared_dpll &&
18036                 crtc_state->port_clock == 0;
18037 }
18038
18039 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18040 {
18041         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18042         struct intel_connector *connector;
18043         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18044         struct intel_crtc_state *crtc_state = crtc ?
18045                 to_intel_crtc_state(crtc->base.state) : NULL;
18046
18047         /* We need to check both for a crtc link (meaning that the
18048          * encoder is active and trying to read from a pipe) and the
18049          * pipe itself being active. */
18050         bool has_active_crtc = crtc_state &&
18051                 crtc_state->hw.active;
18052
18053         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18054                 drm_dbg_kms(&dev_priv->drm,
18055                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18056                             pipe_name(crtc->pipe));
18057                 has_active_crtc = false;
18058         }
18059
18060         connector = intel_encoder_find_connector(encoder);
18061         if (connector && !has_active_crtc) {
18062                 drm_dbg_kms(&dev_priv->drm,
18063                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18064                             encoder->base.base.id,
18065                             encoder->base.name);
18066
18067                 /* Connector is active, but has no active pipe. This is
18068                  * fallout from our resume register restoring. Disable
18069                  * the encoder manually again. */
18070                 if (crtc_state) {
18071                         struct drm_encoder *best_encoder;
18072
18073                         drm_dbg_kms(&dev_priv->drm,
18074                                     "[ENCODER:%d:%s] manually disabled\n",
18075                                     encoder->base.base.id,
18076                                     encoder->base.name);
18077
18078                         /* avoid oopsing in case the hooks consult best_encoder */
18079                         best_encoder = connector->base.state->best_encoder;
18080                         connector->base.state->best_encoder = &encoder->base;
18081
18082                         /* FIXME NULL atomic state passed! */
18083                         if (encoder->disable)
18084                                 encoder->disable(NULL, encoder, crtc_state,
18085                                                  connector->base.state);
18086                         if (encoder->post_disable)
18087                                 encoder->post_disable(NULL, encoder, crtc_state,
18088                                                       connector->base.state);
18089
18090                         connector->base.state->best_encoder = best_encoder;
18091                 }
18092                 encoder->base.crtc = NULL;
18093
18094                 /* Inconsistent output/port/pipe state happens presumably due to
18095                  * a bug in one of the get_hw_state functions. Or someplace else
18096                  * in our code, like the register restore mess on resume. Clamp
18097                  * things to off as a safer default. */
18098
18099                 connector->base.dpms = DRM_MODE_DPMS_OFF;
18100                 connector->base.encoder = NULL;
18101         }
18102
18103         /* notify opregion of the sanitized encoder state */
18104         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18105
18106         if (INTEL_GEN(dev_priv) >= 11)
18107                 icl_sanitize_encoder_pll_mapping(encoder);
18108 }
18109
18110 /* FIXME read out full plane state for all planes */
18111 static void readout_plane_state(struct drm_i915_private *dev_priv)
18112 {
18113         struct intel_plane *plane;
18114         struct intel_crtc *crtc;
18115
18116         for_each_intel_plane(&dev_priv->drm, plane) {
18117                 struct intel_plane_state *plane_state =
18118                         to_intel_plane_state(plane->base.state);
18119                 struct intel_crtc_state *crtc_state;
18120                 enum pipe pipe = PIPE_A;
18121                 bool visible;
18122
18123                 visible = plane->get_hw_state(plane, &pipe);
18124
18125                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18126                 crtc_state = to_intel_crtc_state(crtc->base.state);
18127
18128                 intel_set_plane_visible(crtc_state, plane_state, visible);
18129
18130                 drm_dbg_kms(&dev_priv->drm,
18131                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18132                             plane->base.base.id, plane->base.name,
18133                             enableddisabled(visible), pipe_name(pipe));
18134         }
18135
18136         for_each_intel_crtc(&dev_priv->drm, crtc) {
18137                 struct intel_crtc_state *crtc_state =
18138                         to_intel_crtc_state(crtc->base.state);
18139
18140                 fixup_active_planes(crtc_state);
18141         }
18142 }
18143
18144 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18145 {
18146         struct drm_i915_private *dev_priv = to_i915(dev);
18147         struct intel_cdclk_state *cdclk_state =
18148                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18149         enum pipe pipe;
18150         struct intel_crtc *crtc;
18151         struct intel_encoder *encoder;
18152         struct intel_connector *connector;
18153         struct drm_connector_list_iter conn_iter;
18154         u8 active_pipes = 0;
18155
18156         for_each_intel_crtc(dev, crtc) {
18157                 struct intel_crtc_state *crtc_state =
18158                         to_intel_crtc_state(crtc->base.state);
18159
18160                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18161                 intel_crtc_free_hw_state(crtc_state);
18162                 intel_crtc_state_reset(crtc_state, crtc);
18163
18164                 crtc_state->hw.active = crtc_state->hw.enable =
18165                         dev_priv->display.get_pipe_config(crtc, crtc_state);
18166
18167                 crtc->base.enabled = crtc_state->hw.enable;
18168                 crtc->active = crtc_state->hw.active;
18169
18170                 if (crtc_state->hw.active)
18171                         active_pipes |= BIT(crtc->pipe);
18172
18173                 drm_dbg_kms(&dev_priv->drm,
18174                             "[CRTC:%d:%s] hw state readout: %s\n",
18175                             crtc->base.base.id, crtc->base.name,
18176                             enableddisabled(crtc_state->hw.active));
18177         }
18178
18179         dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes;
18180
18181         readout_plane_state(dev_priv);
18182
18183         intel_dpll_readout_hw_state(dev_priv);
18184
18185         for_each_intel_encoder(dev, encoder) {
18186                 pipe = 0;
18187
18188                 if (encoder->get_hw_state(encoder, &pipe)) {
18189                         struct intel_crtc_state *crtc_state;
18190
18191                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18192                         crtc_state = to_intel_crtc_state(crtc->base.state);
18193
18194                         encoder->base.crtc = &crtc->base;
18195                         encoder->get_config(encoder, crtc_state);
18196                 } else {
18197                         encoder->base.crtc = NULL;
18198                 }
18199
18200                 drm_dbg_kms(&dev_priv->drm,
18201                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18202                             encoder->base.base.id, encoder->base.name,
18203                             enableddisabled(encoder->base.crtc),
18204                             pipe_name(pipe));
18205         }
18206
18207         drm_connector_list_iter_begin(dev, &conn_iter);
18208         for_each_intel_connector_iter(connector, &conn_iter) {
18209                 if (connector->get_hw_state(connector)) {
18210                         struct intel_crtc_state *crtc_state;
18211                         struct intel_crtc *crtc;
18212
18213                         connector->base.dpms = DRM_MODE_DPMS_ON;
18214
18215                         encoder = intel_attached_encoder(connector);
18216                         connector->base.encoder = &encoder->base;
18217
18218                         crtc = to_intel_crtc(encoder->base.crtc);
18219                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18220
18221                         if (crtc_state && crtc_state->hw.active) {
18222                                 /*
18223                                  * This has to be done during hardware readout
18224                                  * because anything calling .crtc_disable may
18225                                  * rely on the connector_mask being accurate.
18226                                  */
18227                                 crtc_state->uapi.connector_mask |=
18228                                         drm_connector_mask(&connector->base);
18229                                 crtc_state->uapi.encoder_mask |=
18230                                         drm_encoder_mask(&encoder->base);
18231                         }
18232                 } else {
18233                         connector->base.dpms = DRM_MODE_DPMS_OFF;
18234                         connector->base.encoder = NULL;
18235                 }
18236                 drm_dbg_kms(&dev_priv->drm,
18237                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
18238                             connector->base.base.id, connector->base.name,
18239                             enableddisabled(connector->base.encoder));
18240         }
18241         drm_connector_list_iter_end(&conn_iter);
18242
18243         for_each_intel_crtc(dev, crtc) {
18244                 struct intel_bw_state *bw_state =
18245                         to_intel_bw_state(dev_priv->bw_obj.state);
18246                 struct intel_crtc_state *crtc_state =
18247                         to_intel_crtc_state(crtc->base.state);
18248                 struct intel_plane *plane;
18249                 int min_cdclk = 0;
18250
18251                 if (crtc_state->hw.active) {
18252                         struct drm_display_mode *mode = &crtc_state->hw.mode;
18253
18254                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18255                                                     crtc_state);
18256
18257                         *mode = crtc_state->hw.adjusted_mode;
18258                         mode->hdisplay = crtc_state->pipe_src_w;
18259                         mode->vdisplay = crtc_state->pipe_src_h;
18260
18261                         /*
18262                          * The initial mode needs to be set in order to keep
18263                          * the atomic core happy. It wants a valid mode if the
18264                          * crtc's enabled, so we do the above call.
18265                          *
18266                          * But we don't set all the derived state fully, hence
18267                          * set a flag to indicate that a full recalculation is
18268                          * needed on the next commit.
18269                          */
18270                         mode->private_flags = I915_MODE_FLAG_INHERITED;
18271
18272                         intel_crtc_compute_pixel_rate(crtc_state);
18273
18274                         intel_crtc_update_active_timings(crtc_state);
18275
18276                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
18277                 }
18278
18279                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18280                         const struct intel_plane_state *plane_state =
18281                                 to_intel_plane_state(plane->base.state);
18282
18283                         /*
18284                          * FIXME don't have the fb yet, so can't
18285                          * use intel_plane_data_rate() :(
18286                          */
18287                         if (plane_state->uapi.visible)
18288                                 crtc_state->data_rate[plane->id] =
18289                                         4 * crtc_state->pixel_rate;
18290                         /*
18291                          * FIXME don't have the fb yet, so can't
18292                          * use plane->min_cdclk() :(
18293                          */
18294                         if (plane_state->uapi.visible && plane->min_cdclk) {
18295                                 if (crtc_state->double_wide ||
18296                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18297                                         crtc_state->min_cdclk[plane->id] =
18298                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18299                                 else
18300                                         crtc_state->min_cdclk[plane->id] =
18301                                                 crtc_state->pixel_rate;
18302                         }
18303                         drm_dbg_kms(&dev_priv->drm,
18304                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
18305                                     plane->base.base.id, plane->base.name,
18306                                     crtc_state->min_cdclk[plane->id]);
18307                 }
18308
18309                 if (crtc_state->hw.active) {
18310                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18311                         if (drm_WARN_ON(dev, min_cdclk < 0))
18312                                 min_cdclk = 0;
18313                 }
18314
18315                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18316                 cdclk_state->min_voltage_level[crtc->pipe] =
18317                         crtc_state->min_voltage_level;
18318
18319                 intel_bw_crtc_update(bw_state, crtc_state);
18320
18321                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18322         }
18323 }
18324
18325 static void
18326 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18327 {
18328         struct intel_encoder *encoder;
18329
18330         for_each_intel_encoder(&dev_priv->drm, encoder) {
18331                 struct intel_crtc_state *crtc_state;
18332
18333                 if (!encoder->get_power_domains)
18334                         continue;
18335
18336                 /*
18337                  * MST-primary and inactive encoders don't have a crtc state
18338                  * and neither of these require any power domain references.
18339                  */
18340                 if (!encoder->base.crtc)
18341                         continue;
18342
18343                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18344                 encoder->get_power_domains(encoder, crtc_state);
18345         }
18346 }
18347
18348 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18349 {
18350         /*
18351          * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18352          * Also known as Wa_14010480278.
18353          */
18354         if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18355                 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18356                                intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18357
18358         if (IS_HASWELL(dev_priv)) {
18359                 /*
18360                  * WaRsPkgCStateDisplayPMReq:hsw
18361                  * System hang if this isn't done before disabling all planes!
18362                  */
18363                 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18364                                intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18365         }
18366 }
18367
18368 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18369                                        enum port port, i915_reg_t hdmi_reg)
18370 {
18371         u32 val = intel_de_read(dev_priv, hdmi_reg);
18372
18373         if (val & SDVO_ENABLE ||
18374             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18375                 return;
18376
18377         drm_dbg_kms(&dev_priv->drm,
18378                     "Sanitizing transcoder select for HDMI %c\n",
18379                     port_name(port));
18380
18381         val &= ~SDVO_PIPE_SEL_MASK;
18382         val |= SDVO_PIPE_SEL(PIPE_A);
18383
18384         intel_de_write(dev_priv, hdmi_reg, val);
18385 }
18386
18387 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18388                                      enum port port, i915_reg_t dp_reg)
18389 {
18390         u32 val = intel_de_read(dev_priv, dp_reg);
18391
18392         if (val & DP_PORT_EN ||
18393             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18394                 return;
18395
18396         drm_dbg_kms(&dev_priv->drm,
18397                     "Sanitizing transcoder select for DP %c\n",
18398                     port_name(port));
18399
18400         val &= ~DP_PIPE_SEL_MASK;
18401         val |= DP_PIPE_SEL(PIPE_A);
18402
18403         intel_de_write(dev_priv, dp_reg, val);
18404 }
18405
18406 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18407 {
18408         /*
18409          * The BIOS may select transcoder B on some of the PCH
18410          * ports even it doesn't enable the port. This would trip
18411          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18412          * Sanitize the transcoder select bits to prevent that. We
18413          * assume that the BIOS never actually enabled the port,
18414          * because if it did we'd actually have to toggle the port
18415          * on and back off to make the transcoder A select stick
18416          * (see. intel_dp_link_down(), intel_disable_hdmi(),
18417          * intel_disable_sdvo()).
18418          */
18419         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18420         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18421         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18422
18423         /* PCH SDVOB multiplex with HDMIB */
18424         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18425         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18426         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18427 }
18428
18429 /* Scan out the current hw modeset state,
18430  * and sanitizes it to the current state
18431  */
18432 static void
18433 intel_modeset_setup_hw_state(struct drm_device *dev,
18434                              struct drm_modeset_acquire_ctx *ctx)
18435 {
18436         struct drm_i915_private *dev_priv = to_i915(dev);
18437         struct intel_encoder *encoder;
18438         struct intel_crtc *crtc;
18439         intel_wakeref_t wakeref;
18440
18441         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
18442
18443         intel_early_display_was(dev_priv);
18444         intel_modeset_readout_hw_state(dev);
18445
18446         /* HW state is read out, now we need to sanitize this mess. */
18447
18448         /* Sanitize the TypeC port mode upfront, encoders depend on this */
18449         for_each_intel_encoder(dev, encoder) {
18450                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
18451
18452                 /* We need to sanitize only the MST primary port. */
18453                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
18454                     intel_phy_is_tc(dev_priv, phy))
18455                         intel_tc_port_sanitize(enc_to_dig_port(encoder));
18456         }
18457
18458         get_encoder_power_domains(dev_priv);
18459
18460         if (HAS_PCH_IBX(dev_priv))
18461                 ibx_sanitize_pch_ports(dev_priv);
18462
18463         /*
18464          * intel_sanitize_plane_mapping() may need to do vblank
18465          * waits, so we need vblank interrupts restored beforehand.
18466          */
18467         for_each_intel_crtc(&dev_priv->drm, crtc) {
18468                 struct intel_crtc_state *crtc_state =
18469                         to_intel_crtc_state(crtc->base.state);
18470
18471                 drm_crtc_vblank_reset(&crtc->base);
18472
18473                 if (crtc_state->hw.active)
18474                         intel_crtc_vblank_on(crtc_state);
18475         }
18476
18477         intel_sanitize_plane_mapping(dev_priv);
18478
18479         for_each_intel_encoder(dev, encoder)
18480                 intel_sanitize_encoder(encoder);
18481
18482         for_each_intel_crtc(&dev_priv->drm, crtc) {
18483                 struct intel_crtc_state *crtc_state =
18484                         to_intel_crtc_state(crtc->base.state);
18485
18486                 intel_sanitize_crtc(crtc, ctx);
18487                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
18488         }
18489
18490         intel_modeset_update_connector_atomic_state(dev);
18491
18492         intel_dpll_sanitize_state(dev_priv);
18493
18494         if (IS_G4X(dev_priv)) {
18495                 g4x_wm_get_hw_state(dev_priv);
18496                 g4x_wm_sanitize(dev_priv);
18497         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
18498                 vlv_wm_get_hw_state(dev_priv);
18499                 vlv_wm_sanitize(dev_priv);
18500         } else if (INTEL_GEN(dev_priv) >= 9) {
18501                 skl_wm_get_hw_state(dev_priv);
18502         } else if (HAS_PCH_SPLIT(dev_priv)) {
18503                 ilk_wm_get_hw_state(dev_priv);
18504         }
18505
18506         for_each_intel_crtc(dev, crtc) {
18507                 struct intel_crtc_state *crtc_state =
18508                         to_intel_crtc_state(crtc->base.state);
18509                 u64 put_domains;
18510
18511                 put_domains = modeset_get_crtc_power_domains(crtc_state);
18512                 if (drm_WARN_ON(dev, put_domains))
18513                         modeset_put_power_domains(dev_priv, put_domains);
18514         }
18515
18516         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
18517 }
18518
18519 void intel_display_resume(struct drm_device *dev)
18520 {
18521         struct drm_i915_private *dev_priv = to_i915(dev);
18522         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
18523         struct drm_modeset_acquire_ctx ctx;
18524         int ret;
18525
18526         dev_priv->modeset_restore_state = NULL;
18527         if (state)
18528                 state->acquire_ctx = &ctx;
18529
18530         drm_modeset_acquire_init(&ctx, 0);
18531
18532         while (1) {
18533                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
18534                 if (ret != -EDEADLK)
18535                         break;
18536
18537                 drm_modeset_backoff(&ctx);
18538         }
18539
18540         if (!ret)
18541                 ret = __intel_display_resume(dev, state, &ctx);
18542
18543         intel_enable_ipc(dev_priv);
18544         drm_modeset_drop_locks(&ctx);
18545         drm_modeset_acquire_fini(&ctx);
18546
18547         if (ret)
18548                 drm_err(&dev_priv->drm,
18549                         "Restoring old state failed with %i\n", ret);
18550         if (state)
18551                 drm_atomic_state_put(state);
18552 }
18553
18554 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
18555 {
18556         struct intel_connector *connector;
18557         struct drm_connector_list_iter conn_iter;
18558
18559         /* Kill all the work that may have been queued by hpd. */
18560         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
18561         for_each_intel_connector_iter(connector, &conn_iter) {
18562                 if (connector->modeset_retry_work.func)
18563                         cancel_work_sync(&connector->modeset_retry_work);
18564                 if (connector->hdcp.shim) {
18565                         cancel_delayed_work_sync(&connector->hdcp.check_work);
18566                         cancel_work_sync(&connector->hdcp.prop_work);
18567                 }
18568         }
18569         drm_connector_list_iter_end(&conn_iter);
18570 }
18571
18572 /* part #1: call before irq uninstall */
18573 void intel_modeset_driver_remove(struct drm_i915_private *i915)
18574 {
18575         flush_workqueue(i915->flip_wq);
18576         flush_workqueue(i915->modeset_wq);
18577
18578         flush_work(&i915->atomic_helper.free_work);
18579         drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
18580 }
18581
18582 /* part #2: call after irq uninstall */
18583 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
18584 {
18585         /*
18586          * Due to the hpd irq storm handling the hotplug work can re-arm the
18587          * poll handlers. Hence disable polling after hpd handling is shut down.
18588          */
18589         intel_hpd_poll_fini(i915);
18590
18591         /*
18592          * MST topology needs to be suspended so we don't have any calls to
18593          * fbdev after it's finalized. MST will be destroyed later as part of
18594          * drm_mode_config_cleanup()
18595          */
18596         intel_dp_mst_suspend(i915);
18597
18598         /* poll work can call into fbdev, hence clean that up afterwards */
18599         intel_fbdev_fini(i915);
18600
18601         intel_unregister_dsm_handler();
18602
18603         intel_fbc_global_disable(i915);
18604
18605         /* flush any delayed tasks or pending work */
18606         flush_scheduled_work();
18607
18608         intel_hdcp_component_fini(i915);
18609
18610         intel_mode_config_cleanup(i915);
18611
18612         intel_overlay_cleanup(i915);
18613
18614         intel_gmbus_teardown(i915);
18615
18616         destroy_workqueue(i915->flip_wq);
18617         destroy_workqueue(i915->modeset_wq);
18618
18619         intel_fbc_cleanup_cfb(i915);
18620 }
18621
18622 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
18623
18624 struct intel_display_error_state {
18625
18626         u32 power_well_driver;
18627
18628         struct intel_cursor_error_state {
18629                 u32 control;
18630                 u32 position;
18631                 u32 base;
18632                 u32 size;
18633         } cursor[I915_MAX_PIPES];
18634
18635         struct intel_pipe_error_state {
18636                 bool power_domain_on;
18637                 u32 source;
18638                 u32 stat;
18639         } pipe[I915_MAX_PIPES];
18640
18641         struct intel_plane_error_state {
18642                 u32 control;
18643                 u32 stride;
18644                 u32 size;
18645                 u32 pos;
18646                 u32 addr;
18647                 u32 surface;
18648                 u32 tile_offset;
18649         } plane[I915_MAX_PIPES];
18650
18651         struct intel_transcoder_error_state {
18652                 bool available;
18653                 bool power_domain_on;
18654                 enum transcoder cpu_transcoder;
18655
18656                 u32 conf;
18657
18658                 u32 htotal;
18659                 u32 hblank;
18660                 u32 hsync;
18661                 u32 vtotal;
18662                 u32 vblank;
18663                 u32 vsync;
18664         } transcoder[5];
18665 };
18666
18667 struct intel_display_error_state *
18668 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18669 {
18670         struct intel_display_error_state *error;
18671         int transcoders[] = {
18672                 TRANSCODER_A,
18673                 TRANSCODER_B,
18674                 TRANSCODER_C,
18675                 TRANSCODER_D,
18676                 TRANSCODER_EDP,
18677         };
18678         int i;
18679
18680         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
18681
18682         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
18683                 return NULL;
18684
18685         error = kzalloc(sizeof(*error), GFP_ATOMIC);
18686         if (error == NULL)
18687                 return NULL;
18688
18689         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18690                 error->power_well_driver = intel_de_read(dev_priv,
18691                                                          HSW_PWR_WELL_CTL2);
18692
18693         for_each_pipe(dev_priv, i) {
18694                 error->pipe[i].power_domain_on =
18695                         __intel_display_power_is_enabled(dev_priv,
18696                                                          POWER_DOMAIN_PIPE(i));
18697                 if (!error->pipe[i].power_domain_on)
18698                         continue;
18699
18700                 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
18701                 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
18702                 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
18703
18704                 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
18705                 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
18706                 if (INTEL_GEN(dev_priv) <= 3) {
18707                         error->plane[i].size = intel_de_read(dev_priv,
18708                                                              DSPSIZE(i));
18709                         error->plane[i].pos = intel_de_read(dev_priv,
18710                                                             DSPPOS(i));
18711                 }
18712                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18713                         error->plane[i].addr = intel_de_read(dev_priv,
18714                                                              DSPADDR(i));
18715                 if (INTEL_GEN(dev_priv) >= 4) {
18716                         error->plane[i].surface = intel_de_read(dev_priv,
18717                                                                 DSPSURF(i));
18718                         error->plane[i].tile_offset = intel_de_read(dev_priv,
18719                                                                     DSPTILEOFF(i));
18720                 }
18721
18722                 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
18723
18724                 if (HAS_GMCH(dev_priv))
18725                         error->pipe[i].stat = intel_de_read(dev_priv,
18726                                                             PIPESTAT(i));
18727         }
18728
18729         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18730                 enum transcoder cpu_transcoder = transcoders[i];
18731
18732                 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
18733                         continue;
18734
18735                 error->transcoder[i].available = true;
18736                 error->transcoder[i].power_domain_on =
18737                         __intel_display_power_is_enabled(dev_priv,
18738                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18739                 if (!error->transcoder[i].power_domain_on)
18740                         continue;
18741
18742                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18743
18744                 error->transcoder[i].conf = intel_de_read(dev_priv,
18745                                                           PIPECONF(cpu_transcoder));
18746                 error->transcoder[i].htotal = intel_de_read(dev_priv,
18747                                                             HTOTAL(cpu_transcoder));
18748                 error->transcoder[i].hblank = intel_de_read(dev_priv,
18749                                                             HBLANK(cpu_transcoder));
18750                 error->transcoder[i].hsync = intel_de_read(dev_priv,
18751                                                            HSYNC(cpu_transcoder));
18752                 error->transcoder[i].vtotal = intel_de_read(dev_priv,
18753                                                             VTOTAL(cpu_transcoder));
18754                 error->transcoder[i].vblank = intel_de_read(dev_priv,
18755                                                             VBLANK(cpu_transcoder));
18756                 error->transcoder[i].vsync = intel_de_read(dev_priv,
18757                                                            VSYNC(cpu_transcoder));
18758         }
18759
18760         return error;
18761 }
18762
18763 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18764
18765 void
18766 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18767                                 struct intel_display_error_state *error)
18768 {
18769         struct drm_i915_private *dev_priv = m->i915;
18770         int i;
18771
18772         if (!error)
18773                 return;
18774
18775         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18776         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18777                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18778                            error->power_well_driver);
18779         for_each_pipe(dev_priv, i) {
18780                 err_printf(m, "Pipe [%d]:\n", i);
18781                 err_printf(m, "  Power: %s\n",
18782                            onoff(error->pipe[i].power_domain_on));
18783                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18784                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18785
18786                 err_printf(m, "Plane [%d]:\n", i);
18787                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18788                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18789                 if (INTEL_GEN(dev_priv) <= 3) {
18790                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18791                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18792                 }
18793                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18794                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18795                 if (INTEL_GEN(dev_priv) >= 4) {
18796                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18797                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18798                 }
18799
18800                 err_printf(m, "Cursor [%d]:\n", i);
18801                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18802                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18803                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18804         }
18805
18806         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18807                 if (!error->transcoder[i].available)
18808                         continue;
18809
18810                 err_printf(m, "CPU transcoder: %s\n",
18811                            transcoder_name(error->transcoder[i].cpu_transcoder));
18812                 err_printf(m, "  Power: %s\n",
18813                            onoff(error->transcoder[i].power_domain_on));
18814                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
18815                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18816                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18817                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18818                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18819                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
18820                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
18821         }
18822 }
18823
18824 #endif