drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <drm/i915_drm.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_RGB565,
  90         DRM_FORMAT_XRGB1555,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 static const u64 i9xx_format_modifiers[] = {
 116         I915_FORMAT_MOD_X_TILED,
 117         DRM_FORMAT_MOD_LINEAR,
 118         DRM_FORMAT_MOD_INVALID
 119 };
 120
 121 /* Cursor formats */
 122 static const u32 intel_cursor_formats[] = {
 123         DRM_FORMAT_ARGB8888,
 124 };
 125
 126 static const u64 cursor_format_modifiers[] = {
 127         DRM_FORMAT_MOD_LINEAR,
 128         DRM_FORMAT_MOD_INVALID
 129 };
 130
 131 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 132                                 struct intel_crtc_state *pipe_config);
 133 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 134                                    struct intel_crtc_state *pipe_config);
 135
 136 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 137                                   struct drm_i915_gem_object *obj,
 138                                   struct drm_mode_fb_cmd2 *mode_cmd);
 139 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 140 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 141 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 142                                          const struct intel_link_m_n *m_n,
 143                                          const struct intel_link_m_n *m2_n2);
 144 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 145 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 146 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 147 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 148 static void vlv_prepare_pll(struct intel_crtc *crtc,
 149                             const struct intel_crtc_state *pipe_config);
 150 static void chv_prepare_pll(struct intel_crtc *crtc,
 151                             const struct intel_crtc_state *pipe_config);
 152 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 153                                     struct intel_crtc_state *crtc_state);
 154 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 155 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 156 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 157 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 158                                          struct drm_modeset_acquire_ctx *ctx);
 159 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 160
 161 struct intel_limit {
 162         struct {
 163                 int min, max;
 164         } dot, vco, n, m, m1, m2, p, p1;
 165
 166         struct {
 167                 int dot_limit;
 168                 int p2_slow, p2_fast;
 169         } p2;
 170 };
 171
 172 /* returns HPLL frequency in kHz */
 173 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 174 {
 175         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 176
 177         /* Obtain SKU information */
 178         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 179                 CCK_FUSE_HPLL_FREQ_MASK;
 180
 181         return vco_freq[hpll_freq] * 1000;
 182 }
 183
 184 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 185                       const char *name, u32 reg, int ref_freq)
 186 {
 187         u32 val;
 188         int divider;
 189
 190         val = vlv_cck_read(dev_priv, reg);
 191         divider = val & CCK_FREQUENCY_VALUES;
 192
 193         WARN((val & CCK_FREQUENCY_STATUS) !=
 194              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 195              "%s change in progress\n", name);
 196
 197         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 198 }
 199
 200 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 201                            const char *name, u32 reg)
 202 {
 203         int hpll;
 204
 205         vlv_cck_get(dev_priv);
 206
 207         if (dev_priv->hpll_freq == 0)
 208                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 209
 210         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 211
 212         vlv_cck_put(dev_priv);
 213
 214         return hpll;
 215 }
 216
 217 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 218 {
 219         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 220                 return;
 221
 222         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 223                                                       CCK_CZ_CLOCK_CONTROL);
 224
 225         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 226 }
 227
 228 static inline u32 /* units of 100MHz */
 229 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 230                     const struct intel_crtc_state *pipe_config)
 231 {
 232         if (HAS_DDI(dev_priv))
 233                 return pipe_config->port_clock; /* SPLL */
 234         else
 235                 return dev_priv->fdi_pll_freq;
 236 }
 237
 238 static const struct intel_limit intel_limits_i8xx_dac = {
 239         .dot = { .min = 25000, .max = 350000 },
 240         .vco = { .min = 908000, .max = 1512000 },
 241         .n = { .min = 2, .max = 16 },
 242         .m = { .min = 96, .max = 140 },
 243         .m1 = { .min = 18, .max = 26 },
 244         .m2 = { .min = 6, .max = 16 },
 245         .p = { .min = 4, .max = 128 },
 246         .p1 = { .min = 2, .max = 33 },
 247         .p2 = { .dot_limit = 165000,
 248                 .p2_slow = 4, .p2_fast = 2 },
 249 };
 250
 251 static const struct intel_limit intel_limits_i8xx_dvo = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 4 },
 262 };
 263
 264 static const struct intel_limit intel_limits_i8xx_lvds = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 1, .max = 6 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 14, .p2_fast = 7 },
 275 };
 276
 277 static const struct intel_limit intel_limits_i9xx_sdvo = {
 278         .dot = { .min = 20000, .max = 400000 },
 279         .vco = { .min = 1400000, .max = 2800000 },
 280         .n = { .min = 1, .max = 6 },
 281         .m = { .min = 70, .max = 120 },
 282         .m1 = { .min = 8, .max = 18 },
 283         .m2 = { .min = 3, .max = 7 },
 284         .p = { .min = 5, .max = 80 },
 285         .p1 = { .min = 1, .max = 8 },
 286         .p2 = { .dot_limit = 200000,
 287                 .p2_slow = 10, .p2_fast = 5 },
 288 };
 289
 290 static const struct intel_limit intel_limits_i9xx_lvds = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 7, .max = 98 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 112000,
 300                 .p2_slow = 14, .p2_fast = 7 },
 301 };
 302
 303
 304 static const struct intel_limit intel_limits_g4x_sdvo = {
 305         .dot = { .min = 25000, .max = 270000 },
 306         .vco = { .min = 1750000, .max = 3500000},
 307         .n = { .min = 1, .max = 4 },
 308         .m = { .min = 104, .max = 138 },
 309         .m1 = { .min = 17, .max = 23 },
 310         .m2 = { .min = 5, .max = 11 },
 311         .p = { .min = 10, .max = 30 },
 312         .p1 = { .min = 1, .max = 3},
 313         .p2 = { .dot_limit = 270000,
 314                 .p2_slow = 10,
 315                 .p2_fast = 10
 316         },
 317 };
 318
 319 static const struct intel_limit intel_limits_g4x_hdmi = {
 320         .dot = { .min = 22000, .max = 400000 },
 321         .vco = { .min = 1750000, .max = 3500000},
 322         .n = { .min = 1, .max = 4 },
 323         .m = { .min = 104, .max = 138 },
 324         .m1 = { .min = 16, .max = 23 },
 325         .m2 = { .min = 5, .max = 11 },
 326         .p = { .min = 5, .max = 80 },
 327         .p1 = { .min = 1, .max = 8},
 328         .p2 = { .dot_limit = 165000,
 329                 .p2_slow = 10, .p2_fast = 5 },
 330 };
 331
 332 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 333         .dot = { .min = 20000, .max = 115000 },
 334         .vco = { .min = 1750000, .max = 3500000 },
 335         .n = { .min = 1, .max = 3 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 17, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 28, .max = 112 },
 340         .p1 = { .min = 2, .max = 8 },
 341         .p2 = { .dot_limit = 0,
 342                 .p2_slow = 14, .p2_fast = 14
 343         },
 344 };
 345
 346 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 347         .dot = { .min = 80000, .max = 224000 },
 348         .vco = { .min = 1750000, .max = 3500000 },
 349         .n = { .min = 1, .max = 3 },
 350         .m = { .min = 104, .max = 138 },
 351         .m1 = { .min = 17, .max = 23 },
 352         .m2 = { .min = 5, .max = 11 },
 353         .p = { .min = 14, .max = 42 },
 354         .p1 = { .min = 2, .max = 6 },
 355         .p2 = { .dot_limit = 0,
 356                 .p2_slow = 7, .p2_fast = 7
 357         },
 358 };
 359
 360 static const struct intel_limit intel_limits_pineview_sdvo = {
 361         .dot = { .min = 20000, .max = 400000},
 362         .vco = { .min = 1700000, .max = 3500000 },
 363         /* Pineview's Ncounter is a ring counter */
 364         .n = { .min = 3, .max = 6 },
 365         .m = { .min = 2, .max = 256 },
 366         /* Pineview only has one combined m divider, which we treat as m2. */
 367         .m1 = { .min = 0, .max = 0 },
 368         .m2 = { .min = 0, .max = 254 },
 369         .p = { .min = 5, .max = 80 },
 370         .p1 = { .min = 1, .max = 8 },
 371         .p2 = { .dot_limit = 200000,
 372                 .p2_slow = 10, .p2_fast = 5 },
 373 };
 374
 375 static const struct intel_limit intel_limits_pineview_lvds = {
 376         .dot = { .min = 20000, .max = 400000 },
 377         .vco = { .min = 1700000, .max = 3500000 },
 378         .n = { .min = 3, .max = 6 },
 379         .m = { .min = 2, .max = 256 },
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 7, .max = 112 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 112000,
 385                 .p2_slow = 14, .p2_fast = 14 },
 386 };
 387
 388 /* Ironlake / Sandybridge
 389  *
 390  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 391  * the range value for them is (actual_value - 2).
 392  */
 393 static const struct intel_limit intel_limits_ironlake_dac = {
 394         .dot = { .min = 25000, .max = 350000 },
 395         .vco = { .min = 1760000, .max = 3510000 },
 396         .n = { .min = 1, .max = 5 },
 397         .m = { .min = 79, .max = 127 },
 398         .m1 = { .min = 12, .max = 22 },
 399         .m2 = { .min = 5, .max = 9 },
 400         .p = { .min = 5, .max = 80 },
 401         .p1 = { .min = 1, .max = 8 },
 402         .p2 = { .dot_limit = 225000,
 403                 .p2_slow = 10, .p2_fast = 5 },
 404 };
 405
 406 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 3 },
 410         .m = { .min = 79, .max = 118 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 28, .max = 112 },
 414         .p1 = { .min = 2, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 14, .p2_fast = 14 },
 417 };
 418
 419 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 127 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 14, .max = 56 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 7, .p2_fast = 7 },
 430 };
 431
 432 /* LVDS 100mhz refclk limits. */
 433 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 434         .dot = { .min = 25000, .max = 350000 },
 435         .vco = { .min = 1760000, .max = 3510000 },
 436         .n = { .min = 1, .max = 2 },
 437         .m = { .min = 79, .max = 126 },
 438         .m1 = { .min = 12, .max = 22 },
 439         .m2 = { .min = 5, .max = 9 },
 440         .p = { .min = 28, .max = 112 },
 441         .p1 = { .min = 2, .max = 8 },
 442         .p2 = { .dot_limit = 225000,
 443                 .p2_slow = 14, .p2_fast = 14 },
 444 };
 445
 446 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 3 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 14, .max = 42 },
 454         .p1 = { .min = 2, .max = 6 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 7, .p2_fast = 7 },
 457 };
 458
 459 static const struct intel_limit intel_limits_vlv = {
 460          /*
 461           * These are the data rate limits (measured in fast clocks)
 462           * since those are the strictest limits we have. The fast
 463           * clock and actual rate limits are more relaxed, so checking
 464           * them would make no difference.
 465           */
 466         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 467         .vco = { .min = 4000000, .max = 6000000 },
 468         .n = { .min = 1, .max = 7 },
 469         .m1 = { .min = 2, .max = 3 },
 470         .m2 = { .min = 11, .max = 156 },
 471         .p1 = { .min = 2, .max = 3 },
 472         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 473 };
 474
 475 static const struct intel_limit intel_limits_chv = {
 476         /*
 477          * These are the data rate limits (measured in fast clocks)
 478          * since those are the strictest limits we have.  The fast
 479          * clock and actual rate limits are more relaxed, so checking
 480          * them would make no difference.
 481          */
 482         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 483         .vco = { .min = 4800000, .max = 6480000 },
 484         .n = { .min = 1, .max = 1 },
 485         .m1 = { .min = 2, .max = 2 },
 486         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 487         .p1 = { .min = 2, .max = 4 },
 488         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 489 };
 490
 491 static const struct intel_limit intel_limits_bxt = {
 492         /* FIXME: find real dot limits */
 493         .dot = { .min = 0, .max = INT_MAX },
 494         .vco = { .min = 4800000, .max = 6700000 },
 495         .n = { .min = 1, .max = 1 },
 496         .m1 = { .min = 2, .max = 2 },
 497         /* FIXME: find real m2 limits */
 498         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 499         .p1 = { .min = 2, .max = 4 },
 500         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 501 };
 502
 503 /* WA Display #0827: Gen9:all */
 504 static void
 505 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 506 {
 507         if (enable)
 508                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 509                            I915_READ(CLKGATE_DIS_PSL(pipe)) |
 510                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 511         else
 512                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 513                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 514                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 515 }
 516
 517 /* Wa_2006604312:icl */
 518 static void
 519 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 520                        bool enable)
 521 {
 522         if (enable)
 523                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 524                            I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 525         else
 526                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 527                            I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 528 }
 529
 530 static bool
 531 needs_modeset(const struct intel_crtc_state *state)
 532 {
 533         return drm_atomic_crtc_needs_modeset(&state->base);
 534 }
 535
 536 bool
 537 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 538 {
 539         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 540                 crtc_state->sync_mode_slaves_mask);
 541 }
 542
 543 static bool
 544 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 545 {
 546         return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
 547                 crtc_state->sync_mode_slaves_mask);
 548 }
 549
 550 /*
 551  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 552  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 553  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 554  * The helpers' return value is the rate of the clock that is fed to the
 555  * display engine's pipe which can be the above fast dot clock rate or a
 556  * divided-down version of it.
 557  */
 558 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 559 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 560 {
 561         clock->m = clock->m2 + 2;
 562         clock->p = clock->p1 * clock->p2;
 563         if (WARN_ON(clock->n == 0 || clock->p == 0))
 564                 return 0;
 565         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 566         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 567
 568         return clock->dot;
 569 }
 570
 571 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 572 {
 573         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 574 }
 575
 576 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 577 {
 578         clock->m = i9xx_dpll_compute_m(clock);
 579         clock->p = clock->p1 * clock->p2;
 580         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 581                 return 0;
 582         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 583         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 584
 585         return clock->dot;
 586 }
 587
 588 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 589 {
 590         clock->m = clock->m1 * clock->m2;
 591         clock->p = clock->p1 * clock->p2;
 592         if (WARN_ON(clock->n == 0 || clock->p == 0))
 593                 return 0;
 594         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 595         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 596
 597         return clock->dot / 5;
 598 }
 599
 600 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 601 {
 602         clock->m = clock->m1 * clock->m2;
 603         clock->p = clock->p1 * clock->p2;
 604         if (WARN_ON(clock->n == 0 || clock->p == 0))
 605                 return 0;
 606         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 607                                            clock->n << 22);
 608         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 609
 610         return clock->dot / 5;
 611 }
 612
 613 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 614
 615 /*
 616  * Returns whether the given set of divisors are valid for a given refclk with
 617  * the given connectors.
 618  */
 619 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 620                                const struct intel_limit *limit,
 621                                const struct dpll *clock)
 622 {
 623         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 624                 INTELPllInvalid("n out of range\n");
 625         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 626                 INTELPllInvalid("p1 out of range\n");
 627         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 628                 INTELPllInvalid("m2 out of range\n");
 629         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 630                 INTELPllInvalid("m1 out of range\n");
 631
 632         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 633             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 634                 if (clock->m1 <= clock->m2)
 635                         INTELPllInvalid("m1 <= m2\n");
 636
 637         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 638             !IS_GEN9_LP(dev_priv)) {
 639                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 640                         INTELPllInvalid("p out of range\n");
 641                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 642                         INTELPllInvalid("m out of range\n");
 643         }
 644
 645         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 646                 INTELPllInvalid("vco out of range\n");
 647         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 648          * connector, etc., rather than just a single range.
 649          */
 650         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 651                 INTELPllInvalid("dot out of range\n");
 652
 653         return true;
 654 }
 655
 656 static int
 657 i9xx_select_p2_div(const struct intel_limit *limit,
 658                    const struct intel_crtc_state *crtc_state,
 659                    int target)
 660 {
 661         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 662
 663         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 664                 /*
 665                  * For LVDS just rely on its current settings for dual-channel.
 666                  * We haven't figured out how to reliably set up different
 667                  * single/dual channel state, if we even can.
 668                  */
 669                 if (intel_is_dual_link_lvds(dev_priv))
 670                         return limit->p2.p2_fast;
 671                 else
 672                         return limit->p2.p2_slow;
 673         } else {
 674                 if (target < limit->p2.dot_limit)
 675                         return limit->p2.p2_slow;
 676                 else
 677                         return limit->p2.p2_fast;
 678         }
 679 }
 680
 681 /*
 682  * Returns a set of divisors for the desired target clock with the given
 683  * refclk, or FALSE.  The returned values represent the clock equation:
 684  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 685  *
 686  * Target and reference clocks are specified in kHz.
 687  *
 688  * If match_clock is provided, then best_clock P divider must match the P
 689  * divider from @match_clock used for LVDS downclocking.
 690  */
 691 static bool
 692 i9xx_find_best_dpll(const struct intel_limit *limit,
 693                     struct intel_crtc_state *crtc_state,
 694                     int target, int refclk, struct dpll *match_clock,
 695                     struct dpll *best_clock)
 696 {
 697         struct drm_device *dev = crtc_state->base.crtc->dev;
 698         struct dpll clock;
 699         int err = target;
 700
 701         memset(best_clock, 0, sizeof(*best_clock));
 702
 703         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 704
 705         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 706              clock.m1++) {
 707                 for (clock.m2 = limit->m2.min;
 708                      clock.m2 <= limit->m2.max; clock.m2++) {
 709                         if (clock.m2 >= clock.m1)
 710                                 break;
 711                         for (clock.n = limit->n.min;
 712                              clock.n <= limit->n.max; clock.n++) {
 713                                 for (clock.p1 = limit->p1.min;
 714                                         clock.p1 <= limit->p1.max; clock.p1++) {
 715                                         int this_err;
 716
 717                                         i9xx_calc_dpll_params(refclk, &clock);
 718                                         if (!intel_PLL_is_valid(to_i915(dev),
 719                                                                 limit,
 720                                                                 &clock))
 721                                                 continue;
 722                                         if (match_clock &&
 723                                             clock.p != match_clock->p)
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739 /*
 740  * Returns a set of divisors for the desired target clock with the given
 741  * refclk, or FALSE.  The returned values represent the clock equation:
 742  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 743  *
 744  * Target and reference clocks are specified in kHz.
 745  *
 746  * If match_clock is provided, then best_clock P divider must match the P
 747  * divider from @match_clock used for LVDS downclocking.
 748  */
 749 static bool
 750 pnv_find_best_dpll(const struct intel_limit *limit,
 751                    struct intel_crtc_state *crtc_state,
 752                    int target, int refclk, struct dpll *match_clock,
 753                    struct dpll *best_clock)
 754 {
 755         struct drm_device *dev = crtc_state->base.crtc->dev;
 756         struct dpll clock;
 757         int err = target;
 758
 759         memset(best_clock, 0, sizeof(*best_clock));
 760
 761         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 762
 763         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 764              clock.m1++) {
 765                 for (clock.m2 = limit->m2.min;
 766                      clock.m2 <= limit->m2.max; clock.m2++) {
 767                         for (clock.n = limit->n.min;
 768                              clock.n <= limit->n.max; clock.n++) {
 769                                 for (clock.p1 = limit->p1.min;
 770                                         clock.p1 <= limit->p1.max; clock.p1++) {
 771                                         int this_err;
 772
 773                                         pnv_calc_dpll_params(refclk, &clock);
 774                                         if (!intel_PLL_is_valid(to_i915(dev),
 775                                                                 limit,
 776                                                                 &clock))
 777                                                 continue;
 778                                         if (match_clock &&
 779                                             clock.p != match_clock->p)
 780                                                 continue;
 781
 782                                         this_err = abs(clock.dot - target);
 783                                         if (this_err < err) {
 784                                                 *best_clock = clock;
 785                                                 err = this_err;
 786                                         }
 787                                 }
 788                         }
 789                 }
 790         }
 791
 792         return (err != target);
 793 }
 794
 795 /*
 796  * Returns a set of divisors for the desired target clock with the given
 797  * refclk, or FALSE.  The returned values represent the clock equation:
 798  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 799  *
 800  * Target and reference clocks are specified in kHz.
 801  *
 802  * If match_clock is provided, then best_clock P divider must match the P
 803  * divider from @match_clock used for LVDS downclocking.
 804  */
 805 static bool
 806 g4x_find_best_dpll(const struct intel_limit *limit,
 807                    struct intel_crtc_state *crtc_state,
 808                    int target, int refclk, struct dpll *match_clock,
 809                    struct dpll *best_clock)
 810 {
 811         struct drm_device *dev = crtc_state->base.crtc->dev;
 812         struct dpll clock;
 813         int max_n;
 814         bool found = false;
 815         /* approximately equals target * 0.00585 */
 816         int err_most = (target >> 8) + (target >> 9);
 817
 818         memset(best_clock, 0, sizeof(*best_clock));
 819
 820         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 821
 822         max_n = limit->n.max;
 823         /* based on hardware requirement, prefer smaller n to precision */
 824         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 825                 /* based on hardware requirement, prefere larger m1,m2 */
 826                 for (clock.m1 = limit->m1.max;
 827                      clock.m1 >= limit->m1.min; clock.m1--) {
 828                         for (clock.m2 = limit->m2.max;
 829                              clock.m2 >= limit->m2.min; clock.m2--) {
 830                                 for (clock.p1 = limit->p1.max;
 831                                      clock.p1 >= limit->p1.min; clock.p1--) {
 832                                         int this_err;
 833
 834                                         i9xx_calc_dpll_params(refclk, &clock);
 835                                         if (!intel_PLL_is_valid(to_i915(dev),
 836                                                                 limit,
 837                                                                 &clock))
 838                                                 continue;
 839
 840                                         this_err = abs(clock.dot - target);
 841                                         if (this_err < err_most) {
 842                                                 *best_clock = clock;
 843                                                 err_most = this_err;
 844                                                 max_n = clock.n;
 845                                                 found = true;
 846                                         }
 847                                 }
 848                         }
 849                 }
 850         }
 851         return found;
 852 }
 853
 854 /*
 855  * Check if the calculated PLL configuration is more optimal compared to the
 856  * best configuration and error found so far. Return the calculated error.
 857  */
 858 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 859                                const struct dpll *calculated_clock,
 860                                const struct dpll *best_clock,
 861                                unsigned int best_error_ppm,
 862                                unsigned int *error_ppm)
 863 {
 864         /*
 865          * For CHV ignore the error and consider only the P value.
 866          * Prefer a bigger P value based on HW requirements.
 867          */
 868         if (IS_CHERRYVIEW(to_i915(dev))) {
 869                 *error_ppm = 0;
 870
 871                 return calculated_clock->p > best_clock->p;
 872         }
 873
 874         if (WARN_ON_ONCE(!target_freq))
 875                 return false;
 876
 877         *error_ppm = div_u64(1000000ULL *
 878                                 abs(target_freq - calculated_clock->dot),
 879                              target_freq);
 880         /*
 881          * Prefer a better P value over a better (smaller) error if the error
 882          * is small. Ensure this preference for future configurations too by
 883          * setting the error to 0.
 884          */
 885         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 886                 *error_ppm = 0;
 887
 888                 return true;
 889         }
 890
 891         return *error_ppm + 10 < best_error_ppm;
 892 }
 893
 894 /*
 895  * Returns a set of divisors for the desired target clock with the given
 896  * refclk, or FALSE.  The returned values represent the clock equation:
 897  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 898  */
 899 static bool
 900 vlv_find_best_dpll(const struct intel_limit *limit,
 901                    struct intel_crtc_state *crtc_state,
 902                    int target, int refclk, struct dpll *match_clock,
 903                    struct dpll *best_clock)
 904 {
 905         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 906         struct drm_device *dev = crtc->base.dev;
 907         struct dpll clock;
 908         unsigned int bestppm = 1000000;
 909         /* min update 19.2 MHz */
 910         int max_n = min(limit->n.max, refclk / 19200);
 911         bool found = false;
 912
 913         target *= 5; /* fast clock */
 914
 915         memset(best_clock, 0, sizeof(*best_clock));
 916
 917         /* based on hardware requirement, prefer smaller n to precision */
 918         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 919                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 920                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 921                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 922                                 clock.p = clock.p1 * clock.p2;
 923                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 924                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 925                                         unsigned int ppm;
 926
 927                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 928                                                                      refclk * clock.m1);
 929
 930                                         vlv_calc_dpll_params(refclk, &clock);
 931
 932                                         if (!intel_PLL_is_valid(to_i915(dev),
 933                                                                 limit,
 934                                                                 &clock))
 935                                                 continue;
 936
 937                                         if (!vlv_PLL_is_optimal(dev, target,
 938                                                                 &clock,
 939                                                                 best_clock,
 940                                                                 bestppm, &ppm))
 941                                                 continue;
 942
 943                                         *best_clock = clock;
 944                                         bestppm = ppm;
 945                                         found = true;
 946                                 }
 947                         }
 948                 }
 949         }
 950
 951         return found;
 952 }
 953
 954 /*
 955  * Returns a set of divisors for the desired target clock with the given
 956  * refclk, or FALSE.  The returned values represent the clock equation:
 957  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 958  */
 959 static bool
 960 chv_find_best_dpll(const struct intel_limit *limit,
 961                    struct intel_crtc_state *crtc_state,
 962                    int target, int refclk, struct dpll *match_clock,
 963                    struct dpll *best_clock)
 964 {
 965         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 966         struct drm_device *dev = crtc->base.dev;
 967         unsigned int best_error_ppm;
 968         struct dpll clock;
 969         u64 m2;
 970         int found = false;
 971
 972         memset(best_clock, 0, sizeof(*best_clock));
 973         best_error_ppm = 1000000;
 974
 975         /*
 976          * Based on hardware doc, the n always set to 1, and m1 always
 977          * set to 2.  If requires to support 200Mhz refclk, we need to
 978          * revisit this because n may not 1 anymore.
 979          */
 980         clock.n = 1, clock.m1 = 2;
 981         target *= 5;    /* fast clock */
 982
 983         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 984                 for (clock.p2 = limit->p2.p2_fast;
 985                                 clock.p2 >= limit->p2.p2_slow;
 986                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 987                         unsigned int error_ppm;
 988
 989                         clock.p = clock.p1 * clock.p2;
 990
 991                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
 992                                                    refclk * clock.m1);
 993
 994                         if (m2 > INT_MAX/clock.m1)
 995                                 continue;
 996
 997                         clock.m2 = m2;
 998
 999                         chv_calc_dpll_params(refclk, &clock);
1000
1001                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1002                                 continue;
1003
1004                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1005                                                 best_error_ppm, &error_ppm))
1006                                 continue;
1007
1008                         *best_clock = clock;
1009                         best_error_ppm = error_ppm;
1010                         found = true;
1011                 }
1012         }
1013
1014         return found;
1015 }
1016
1017 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1018                         struct dpll *best_clock)
1019 {
1020         int refclk = 100000;
1021         const struct intel_limit *limit = &intel_limits_bxt;
1022
1023         return chv_find_best_dpll(limit, crtc_state,
1024                                   crtc_state->port_clock, refclk,
1025                                   NULL, best_clock);
1026 }
1027
1028 bool intel_crtc_active(struct intel_crtc *crtc)
1029 {
1030         /* Be paranoid as we can arrive here with only partial
1031          * state retrieved from the hardware during setup.
1032          *
1033          * We can ditch the adjusted_mode.crtc_clock check as soon
1034          * as Haswell has gained clock readout/fastboot support.
1035          *
1036          * We can ditch the crtc->primary->state->fb check as soon as we can
1037          * properly reconstruct framebuffers.
1038          *
1039          * FIXME: The intel_crtc->active here should be switched to
1040          * crtc->state->active once we have proper CRTC states wired up
1041          * for atomic.
1042          */
1043         return crtc->active && crtc->base.primary->state->fb &&
1044                 crtc->config->base.adjusted_mode.crtc_clock;
1045 }
1046
1047 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1048                                              enum pipe pipe)
1049 {
1050         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1051
1052         return crtc->config->cpu_transcoder;
1053 }
1054
1055 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1056                                     enum pipe pipe)
1057 {
1058         i915_reg_t reg = PIPEDSL(pipe);
1059         u32 line1, line2;
1060         u32 line_mask;
1061
1062         if (IS_GEN(dev_priv, 2))
1063                 line_mask = DSL_LINEMASK_GEN2;
1064         else
1065                 line_mask = DSL_LINEMASK_GEN3;
1066
1067         line1 = I915_READ(reg) & line_mask;
1068         msleep(5);
1069         line2 = I915_READ(reg) & line_mask;
1070
1071         return line1 != line2;
1072 }
1073
1074 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1075 {
1076         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1077         enum pipe pipe = crtc->pipe;
1078
1079         /* Wait for the display line to settle/start moving */
1080         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1081                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1082                           pipe_name(pipe), onoff(state));
1083 }
1084
1085 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1086 {
1087         wait_for_pipe_scanline_moving(crtc, false);
1088 }
1089
1090 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1091 {
1092         wait_for_pipe_scanline_moving(crtc, true);
1093 }
1094
1095 static void
1096 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1097 {
1098         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1099         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1100
1101         if (INTEL_GEN(dev_priv) >= 4) {
1102                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1103                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1104
1105                 /* Wait for the Pipe State to go off */
1106                 if (intel_de_wait_for_clear(dev_priv, reg,
1107                                             I965_PIPECONF_ACTIVE, 100))
1108                         WARN(1, "pipe_off wait timed out\n");
1109         } else {
1110                 intel_wait_for_pipe_scanline_stopped(crtc);
1111         }
1112 }
1113
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116                 enum pipe pipe, bool state)
1117 {
1118         u32 val;
1119         bool cur_state;
1120
1121         val = I915_READ(DPLL(pipe));
1122         cur_state = !!(val & DPLL_VCO_ENABLE);
1123         I915_STATE_WARN(cur_state != state,
1124              "PLL state assertion failure (expected %s, current %s)\n",
1125                         onoff(state), onoff(cur_state));
1126 }
1127
1128 /* XXX: the dsi pll is shared between MIPI DSI ports */
1129 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1130 {
1131         u32 val;
1132         bool cur_state;
1133
1134         vlv_cck_get(dev_priv);
1135         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1136         vlv_cck_put(dev_priv);
1137
1138         cur_state = val & DSI_PLL_VCO_EN;
1139         I915_STATE_WARN(cur_state != state,
1140              "DSI PLL state assertion failure (expected %s, current %s)\n",
1141                         onoff(state), onoff(cur_state));
1142 }
1143
1144 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1145                           enum pipe pipe, bool state)
1146 {
1147         bool cur_state;
1148         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1149                                                                       pipe);
1150
1151         if (HAS_DDI(dev_priv)) {
1152                 /* DDI does not have a specific FDI_TX register */
1153                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1154                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1155         } else {
1156                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1157                 cur_state = !!(val & FDI_TX_ENABLE);
1158         }
1159         I915_STATE_WARN(cur_state != state,
1160              "FDI TX state assertion failure (expected %s, current %s)\n",
1161                         onoff(state), onoff(cur_state));
1162 }
1163 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1164 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1165
1166 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1167                           enum pipe pipe, bool state)
1168 {
1169         u32 val;
1170         bool cur_state;
1171
1172         val = I915_READ(FDI_RX_CTL(pipe));
1173         cur_state = !!(val & FDI_RX_ENABLE);
1174         I915_STATE_WARN(cur_state != state,
1175              "FDI RX state assertion failure (expected %s, current %s)\n",
1176                         onoff(state), onoff(cur_state));
1177 }
1178 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1179 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1180
1181 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1182                                       enum pipe pipe)
1183 {
1184         u32 val;
1185
1186         /* ILK FDI PLL is always enabled */
1187         if (IS_GEN(dev_priv, 5))
1188                 return;
1189
1190         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1191         if (HAS_DDI(dev_priv))
1192                 return;
1193
1194         val = I915_READ(FDI_TX_CTL(pipe));
1195         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1196 }
1197
1198 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1199                        enum pipe pipe, bool state)
1200 {
1201         u32 val;
1202         bool cur_state;
1203
1204         val = I915_READ(FDI_RX_CTL(pipe));
1205         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1206         I915_STATE_WARN(cur_state != state,
1207              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1208                         onoff(state), onoff(cur_state));
1209 }
1210
1211 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1212 {
1213         i915_reg_t pp_reg;
1214         u32 val;
1215         enum pipe panel_pipe = INVALID_PIPE;
1216         bool locked = true;
1217
1218         if (WARN_ON(HAS_DDI(dev_priv)))
1219                 return;
1220
1221         if (HAS_PCH_SPLIT(dev_priv)) {
1222                 u32 port_sel;
1223
1224                 pp_reg = PP_CONTROL(0);
1225                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1226
1227                 switch (port_sel) {
1228                 case PANEL_PORT_SELECT_LVDS:
1229                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1230                         break;
1231                 case PANEL_PORT_SELECT_DPA:
1232                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1233                         break;
1234                 case PANEL_PORT_SELECT_DPC:
1235                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1236                         break;
1237                 case PANEL_PORT_SELECT_DPD:
1238                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1239                         break;
1240                 default:
1241                         MISSING_CASE(port_sel);
1242                         break;
1243                 }
1244         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1245                 /* presumably write lock depends on pipe, not port select */
1246                 pp_reg = PP_CONTROL(pipe);
1247                 panel_pipe = pipe;
1248         } else {
1249                 u32 port_sel;
1250
1251                 pp_reg = PP_CONTROL(0);
1252                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1253
1254                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1255                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1256         }
1257
1258         val = I915_READ(pp_reg);
1259         if (!(val & PANEL_POWER_ON) ||
1260             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1261                 locked = false;
1262
1263         I915_STATE_WARN(panel_pipe == pipe && locked,
1264              "panel assertion failure, pipe %c regs locked\n",
1265              pipe_name(pipe));
1266 }
1267
1268 void assert_pipe(struct drm_i915_private *dev_priv,
1269                  enum pipe pipe, bool state)
1270 {
1271         bool cur_state;
1272         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1273                                                                       pipe);
1274         enum intel_display_power_domain power_domain;
1275         intel_wakeref_t wakeref;
1276
1277         /* we keep both pipes enabled on 830 */
1278         if (IS_I830(dev_priv))
1279                 state = true;
1280
1281         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1282         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1283         if (wakeref) {
1284                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1285                 cur_state = !!(val & PIPECONF_ENABLE);
1286
1287                 intel_display_power_put(dev_priv, power_domain, wakeref);
1288         } else {
1289                 cur_state = false;
1290         }
1291
1292         I915_STATE_WARN(cur_state != state,
1293              "pipe %c assertion failure (expected %s, current %s)\n",
1294                         pipe_name(pipe), onoff(state), onoff(cur_state));
1295 }
1296
1297 static void assert_plane(struct intel_plane *plane, bool state)
1298 {
1299         enum pipe pipe;
1300         bool cur_state;
1301
1302         cur_state = plane->get_hw_state(plane, &pipe);
1303
1304         I915_STATE_WARN(cur_state != state,
1305                         "%s assertion failure (expected %s, current %s)\n",
1306                         plane->base.name, onoff(state), onoff(cur_state));
1307 }
1308
1309 #define assert_plane_enabled(p) assert_plane(p, true)
1310 #define assert_plane_disabled(p) assert_plane(p, false)
1311
1312 static void assert_planes_disabled(struct intel_crtc *crtc)
1313 {
1314         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1315         struct intel_plane *plane;
1316
1317         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1318                 assert_plane_disabled(plane);
1319 }
1320
1321 static void assert_vblank_disabled(struct drm_crtc *crtc)
1322 {
1323         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1324                 drm_crtc_vblank_put(crtc);
1325 }
1326
1327 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1328                                     enum pipe pipe)
1329 {
1330         u32 val;
1331         bool enabled;
1332
1333         val = I915_READ(PCH_TRANSCONF(pipe));
1334         enabled = !!(val & TRANS_ENABLE);
1335         I915_STATE_WARN(enabled,
1336              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1337              pipe_name(pipe));
1338 }
1339
1340 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1341                                    enum pipe pipe, enum port port,
1342                                    i915_reg_t dp_reg)
1343 {
1344         enum pipe port_pipe;
1345         bool state;
1346
1347         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1348
1349         I915_STATE_WARN(state && port_pipe == pipe,
1350                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1351                         port_name(port), pipe_name(pipe));
1352
1353         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1354                         "IBX PCH DP %c still using transcoder B\n",
1355                         port_name(port));
1356 }
1357
1358 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1359                                      enum pipe pipe, enum port port,
1360                                      i915_reg_t hdmi_reg)
1361 {
1362         enum pipe port_pipe;
1363         bool state;
1364
1365         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1366
1367         I915_STATE_WARN(state && port_pipe == pipe,
1368                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1369                         port_name(port), pipe_name(pipe));
1370
1371         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1372                         "IBX PCH HDMI %c still using transcoder B\n",
1373                         port_name(port));
1374 }
1375
1376 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1377                                       enum pipe pipe)
1378 {
1379         enum pipe port_pipe;
1380
1381         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1382         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1383         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1384
1385         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1386                         port_pipe == pipe,
1387                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1388                         pipe_name(pipe));
1389
1390         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1391                         port_pipe == pipe,
1392                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1393                         pipe_name(pipe));
1394
1395         /* PCH SDVOB multiplex with HDMIB */
1396         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1397         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1398         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1399 }
1400
1401 static void _vlv_enable_pll(struct intel_crtc *crtc,
1402                             const struct intel_crtc_state *pipe_config)
1403 {
1404         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1405         enum pipe pipe = crtc->pipe;
1406
1407         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1408         POSTING_READ(DPLL(pipe));
1409         udelay(150);
1410
1411         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1412                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1413 }
1414
1415 static void vlv_enable_pll(struct intel_crtc *crtc,
1416                            const struct intel_crtc_state *pipe_config)
1417 {
1418         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1419         enum pipe pipe = crtc->pipe;
1420
1421         assert_pipe_disabled(dev_priv, pipe);
1422
1423         /* PLL is protected by panel, make sure we can write it */
1424         assert_panel_unlocked(dev_priv, pipe);
1425
1426         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1427                 _vlv_enable_pll(crtc, pipe_config);
1428
1429         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1430         POSTING_READ(DPLL_MD(pipe));
1431 }
1432
1433
1434 static void _chv_enable_pll(struct intel_crtc *crtc,
1435                             const struct intel_crtc_state *pipe_config)
1436 {
1437         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1438         enum pipe pipe = crtc->pipe;
1439         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1440         u32 tmp;
1441
1442         vlv_dpio_get(dev_priv);
1443
1444         /* Enable back the 10bit clock to display controller */
1445         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1446         tmp |= DPIO_DCLKP_EN;
1447         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1448
1449         vlv_dpio_put(dev_priv);
1450
1451         /*
1452          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1453          */
1454         udelay(1);
1455
1456         /* Enable PLL */
1457         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1458
1459         /* Check PLL is locked */
1460         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1461                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1462 }
1463
1464 static void chv_enable_pll(struct intel_crtc *crtc,
1465                            const struct intel_crtc_state *pipe_config)
1466 {
1467         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1468         enum pipe pipe = crtc->pipe;
1469
1470         assert_pipe_disabled(dev_priv, pipe);
1471
1472         /* PLL is protected by panel, make sure we can write it */
1473         assert_panel_unlocked(dev_priv, pipe);
1474
1475         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1476                 _chv_enable_pll(crtc, pipe_config);
1477
1478         if (pipe != PIPE_A) {
1479                 /*
1480                  * WaPixelRepeatModeFixForC0:chv
1481                  *
1482                  * DPLLCMD is AWOL. Use chicken bits to propagate
1483                  * the value from DPLLBMD to either pipe B or C.
1484                  */
1485                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1486                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1487                 I915_WRITE(CBR4_VLV, 0);
1488                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1489
1490                 /*
1491                  * DPLLB VGA mode also seems to cause problems.
1492                  * We should always have it disabled.
1493                  */
1494                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1495         } else {
1496                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1497                 POSTING_READ(DPLL_MD(pipe));
1498         }
1499 }
1500
1501 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1502 {
1503         if (IS_I830(dev_priv))
1504                 return false;
1505
1506         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1507 }
1508
1509 static void i9xx_enable_pll(struct intel_crtc *crtc,
1510                             const struct intel_crtc_state *crtc_state)
1511 {
1512         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1513         i915_reg_t reg = DPLL(crtc->pipe);
1514         u32 dpll = crtc_state->dpll_hw_state.dpll;
1515         int i;
1516
1517         assert_pipe_disabled(dev_priv, crtc->pipe);
1518
1519         /* PLL is protected by panel, make sure we can write it */
1520         if (i9xx_has_pps(dev_priv))
1521                 assert_panel_unlocked(dev_priv, crtc->pipe);
1522
1523         /*
1524          * Apparently we need to have VGA mode enabled prior to changing
1525          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1526          * dividers, even though the register value does change.
1527          */
1528         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1529         I915_WRITE(reg, dpll);
1530
1531         /* Wait for the clocks to stabilize. */
1532         POSTING_READ(reg);
1533         udelay(150);
1534
1535         if (INTEL_GEN(dev_priv) >= 4) {
1536                 I915_WRITE(DPLL_MD(crtc->pipe),
1537                            crtc_state->dpll_hw_state.dpll_md);
1538         } else {
1539                 /* The pixel multiplier can only be updated once the
1540                  * DPLL is enabled and the clocks are stable.
1541                  *
1542                  * So write it again.
1543                  */
1544                 I915_WRITE(reg, dpll);
1545         }
1546
1547         /* We do this three times for luck */
1548         for (i = 0; i < 3; i++) {
1549                 I915_WRITE(reg, dpll);
1550                 POSTING_READ(reg);
1551                 udelay(150); /* wait for warmup */
1552         }
1553 }
1554
1555 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1556 {
1557         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1558         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1559         enum pipe pipe = crtc->pipe;
1560
1561         /* Don't disable pipe or pipe PLLs if needed */
1562         if (IS_I830(dev_priv))
1563                 return;
1564
1565         /* Make sure the pipe isn't still relying on us */
1566         assert_pipe_disabled(dev_priv, pipe);
1567
1568         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1569         POSTING_READ(DPLL(pipe));
1570 }
1571
1572 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1573 {
1574         u32 val;
1575
1576         /* Make sure the pipe isn't still relying on us */
1577         assert_pipe_disabled(dev_priv, pipe);
1578
1579         val = DPLL_INTEGRATED_REF_CLK_VLV |
1580                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1581         if (pipe != PIPE_A)
1582                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1583
1584         I915_WRITE(DPLL(pipe), val);
1585         POSTING_READ(DPLL(pipe));
1586 }
1587
1588 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1589 {
1590         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1591         u32 val;
1592
1593         /* Make sure the pipe isn't still relying on us */
1594         assert_pipe_disabled(dev_priv, pipe);
1595
1596         val = DPLL_SSC_REF_CLK_CHV |
1597                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1598         if (pipe != PIPE_A)
1599                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1600
1601         I915_WRITE(DPLL(pipe), val);
1602         POSTING_READ(DPLL(pipe));
1603
1604         vlv_dpio_get(dev_priv);
1605
1606         /* Disable 10bit clock to display controller */
1607         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1608         val &= ~DPIO_DCLKP_EN;
1609         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1610
1611         vlv_dpio_put(dev_priv);
1612 }
1613
1614 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1615                          struct intel_digital_port *dport,
1616                          unsigned int expected_mask)
1617 {
1618         u32 port_mask;
1619         i915_reg_t dpll_reg;
1620
1621         switch (dport->base.port) {
1622         case PORT_B:
1623                 port_mask = DPLL_PORTB_READY_MASK;
1624                 dpll_reg = DPLL(0);
1625                 break;
1626         case PORT_C:
1627                 port_mask = DPLL_PORTC_READY_MASK;
1628                 dpll_reg = DPLL(0);
1629                 expected_mask <<= 4;
1630                 break;
1631         case PORT_D:
1632                 port_mask = DPLL_PORTD_READY_MASK;
1633                 dpll_reg = DPIO_PHY_STATUS;
1634                 break;
1635         default:
1636                 BUG();
1637         }
1638
1639         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1640                                        port_mask, expected_mask, 1000))
1641                 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1642                      dport->base.base.base.id, dport->base.base.name,
1643                      I915_READ(dpll_reg) & port_mask, expected_mask);
1644 }
1645
1646 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1647 {
1648         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1649         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1650         enum pipe pipe = crtc->pipe;
1651         i915_reg_t reg;
1652         u32 val, pipeconf_val;
1653
1654         /* Make sure PCH DPLL is enabled */
1655         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1656
1657         /* FDI must be feeding us bits for PCH ports */
1658         assert_fdi_tx_enabled(dev_priv, pipe);
1659         assert_fdi_rx_enabled(dev_priv, pipe);
1660
1661         if (HAS_PCH_CPT(dev_priv)) {
1662                 /* Workaround: Set the timing override bit before enabling the
1663                  * pch transcoder. */
1664                 reg = TRANS_CHICKEN2(pipe);
1665                 val = I915_READ(reg);
1666                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1667                 I915_WRITE(reg, val);
1668         }
1669
1670         reg = PCH_TRANSCONF(pipe);
1671         val = I915_READ(reg);
1672         pipeconf_val = I915_READ(PIPECONF(pipe));
1673
1674         if (HAS_PCH_IBX(dev_priv)) {
1675                 /*
1676                  * Make the BPC in transcoder be consistent with
1677                  * that in pipeconf reg. For HDMI we must use 8bpc
1678                  * here for both 8bpc and 12bpc.
1679                  */
1680                 val &= ~PIPECONF_BPC_MASK;
1681                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1682                         val |= PIPECONF_8BPC;
1683                 else
1684                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1685         }
1686
1687         val &= ~TRANS_INTERLACE_MASK;
1688         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1689                 if (HAS_PCH_IBX(dev_priv) &&
1690                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1691                         val |= TRANS_LEGACY_INTERLACED_ILK;
1692                 else
1693                         val |= TRANS_INTERLACED;
1694         } else {
1695                 val |= TRANS_PROGRESSIVE;
1696         }
1697
1698         I915_WRITE(reg, val | TRANS_ENABLE);
1699         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1701 }
1702
1703 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                       enum transcoder cpu_transcoder)
1705 {
1706         u32 val, pipeconf_val;
1707
1708         /* FDI must be feeding us bits for PCH ports */
1709         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1710         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1711
1712         /* Workaround: set timing override bit. */
1713         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1714         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1715         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1716
1717         val = TRANS_ENABLE;
1718         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1719
1720         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1721             PIPECONF_INTERLACED_ILK)
1722                 val |= TRANS_INTERLACED;
1723         else
1724                 val |= TRANS_PROGRESSIVE;
1725
1726         I915_WRITE(LPT_TRANSCONF, val);
1727         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1728                                   TRANS_STATE_ENABLE, 100))
1729                 DRM_ERROR("Failed to enable PCH transcoder\n");
1730 }
1731
1732 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1733                                             enum pipe pipe)
1734 {
1735         i915_reg_t reg;
1736         u32 val;
1737
1738         /* FDI relies on the transcoder */
1739         assert_fdi_tx_disabled(dev_priv, pipe);
1740         assert_fdi_rx_disabled(dev_priv, pipe);
1741
1742         /* Ports must be off as well */
1743         assert_pch_ports_disabled(dev_priv, pipe);
1744
1745         reg = PCH_TRANSCONF(pipe);
1746         val = I915_READ(reg);
1747         val &= ~TRANS_ENABLE;
1748         I915_WRITE(reg, val);
1749         /* wait for PCH transcoder off, transcoder state */
1750         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1751                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1752
1753         if (HAS_PCH_CPT(dev_priv)) {
1754                 /* Workaround: Clear the timing override chicken bit again. */
1755                 reg = TRANS_CHICKEN2(pipe);
1756                 val = I915_READ(reg);
1757                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1758                 I915_WRITE(reg, val);
1759         }
1760 }
1761
1762 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1763 {
1764         u32 val;
1765
1766         val = I915_READ(LPT_TRANSCONF);
1767         val &= ~TRANS_ENABLE;
1768         I915_WRITE(LPT_TRANSCONF, val);
1769         /* wait for PCH transcoder off, transcoder state */
1770         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1771                                     TRANS_STATE_ENABLE, 50))
1772                 DRM_ERROR("Failed to disable PCH transcoder\n");
1773
1774         /* Workaround: clear timing override bit. */
1775         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1776         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1777         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1778 }
1779
1780 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1781 {
1782         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1783
1784         if (HAS_PCH_LPT(dev_priv))
1785                 return PIPE_A;
1786         else
1787                 return crtc->pipe;
1788 }
1789
1790 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1791 {
1792         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1793
1794         /*
1795          * On i965gm the hardware frame counter reads
1796          * zero when the TV encoder is enabled :(
1797          */
1798         if (IS_I965GM(dev_priv) &&
1799             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1800                 return 0;
1801
1802         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1803                 return 0xffffffff; /* full 32 bit counter */
1804         else if (INTEL_GEN(dev_priv) >= 3)
1805                 return 0xffffff; /* only 24 bits of frame count */
1806         else
1807                 return 0; /* Gen2 doesn't have a hardware frame counter */
1808 }
1809
1810 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1811 {
1812         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1813
1814         drm_crtc_set_max_vblank_count(&crtc->base,
1815                                       intel_crtc_max_vblank_count(crtc_state));
1816         drm_crtc_vblank_on(&crtc->base);
1817 }
1818
1819 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1820 {
1821         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1822         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1824         enum pipe pipe = crtc->pipe;
1825         i915_reg_t reg;
1826         u32 val;
1827
1828         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1829
1830         assert_planes_disabled(crtc);
1831
1832         /*
1833          * A pipe without a PLL won't actually be able to drive bits from
1834          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1835          * need the check.
1836          */
1837         if (HAS_GMCH(dev_priv)) {
1838                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1839                         assert_dsi_pll_enabled(dev_priv);
1840                 else
1841                         assert_pll_enabled(dev_priv, pipe);
1842         } else {
1843                 if (new_crtc_state->has_pch_encoder) {
1844                         /* if driving the PCH, we need FDI enabled */
1845                         assert_fdi_rx_pll_enabled(dev_priv,
1846                                                   intel_crtc_pch_transcoder(crtc));
1847                         assert_fdi_tx_pll_enabled(dev_priv,
1848                                                   (enum pipe) cpu_transcoder);
1849                 }
1850                 /* FIXME: assert CPU port conditions for SNB+ */
1851         }
1852
1853         trace_intel_pipe_enable(crtc);
1854
1855         reg = PIPECONF(cpu_transcoder);
1856         val = I915_READ(reg);
1857         if (val & PIPECONF_ENABLE) {
1858                 /* we keep both pipes enabled on 830 */
1859                 WARN_ON(!IS_I830(dev_priv));
1860                 return;
1861         }
1862
1863         I915_WRITE(reg, val | PIPECONF_ENABLE);
1864         POSTING_READ(reg);
1865
1866         /*
1867          * Until the pipe starts PIPEDSL reads will return a stale value,
1868          * which causes an apparent vblank timestamp jump when PIPEDSL
1869          * resets to its proper value. That also messes up the frame count
1870          * when it's derived from the timestamps. So let's wait for the
1871          * pipe to start properly before we call drm_crtc_vblank_on()
1872          */
1873         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1874                 intel_wait_for_pipe_scanline_moving(crtc);
1875 }
1876
1877 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1878 {
1879         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1880         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1881         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1882         enum pipe pipe = crtc->pipe;
1883         i915_reg_t reg;
1884         u32 val;
1885
1886         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1887
1888         /*
1889          * Make sure planes won't keep trying to pump pixels to us,
1890          * or we might hang the display.
1891          */
1892         assert_planes_disabled(crtc);
1893
1894         trace_intel_pipe_disable(crtc);
1895
1896         reg = PIPECONF(cpu_transcoder);
1897         val = I915_READ(reg);
1898         if ((val & PIPECONF_ENABLE) == 0)
1899                 return;
1900
1901         /*
1902          * Double wide has implications for planes
1903          * so best keep it disabled when not needed.
1904          */
1905         if (old_crtc_state->double_wide)
1906                 val &= ~PIPECONF_DOUBLE_WIDE;
1907
1908         /* Don't disable pipe or pipe PLLs if needed */
1909         if (!IS_I830(dev_priv))
1910                 val &= ~PIPECONF_ENABLE;
1911
1912         I915_WRITE(reg, val);
1913         if ((val & PIPECONF_ENABLE) == 0)
1914                 intel_wait_for_pipe_off(old_crtc_state);
1915 }
1916
1917 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1918 {
1919         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1920 }
1921
1922 static unsigned int
1923 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1924 {
1925         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1926         unsigned int cpp = fb->format->cpp[color_plane];
1927
1928         switch (fb->modifier) {
1929         case DRM_FORMAT_MOD_LINEAR:
1930                 return intel_tile_size(dev_priv);
1931         case I915_FORMAT_MOD_X_TILED:
1932                 if (IS_GEN(dev_priv, 2))
1933                         return 128;
1934                 else
1935                         return 512;
1936         case I915_FORMAT_MOD_Y_TILED_CCS:
1937                 if (color_plane == 1)
1938                         return 128;
1939                 /* fall through */
1940         case I915_FORMAT_MOD_Y_TILED:
1941                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1942                         return 128;
1943                 else
1944                         return 512;
1945         case I915_FORMAT_MOD_Yf_TILED_CCS:
1946                 if (color_plane == 1)
1947                         return 128;
1948                 /* fall through */
1949         case I915_FORMAT_MOD_Yf_TILED:
1950                 switch (cpp) {
1951                 case 1:
1952                         return 64;
1953                 case 2:
1954                 case 4:
1955                         return 128;
1956                 case 8:
1957                 case 16:
1958                         return 256;
1959                 default:
1960                         MISSING_CASE(cpp);
1961                         return cpp;
1962                 }
1963                 break;
1964         default:
1965                 MISSING_CASE(fb->modifier);
1966                 return cpp;
1967         }
1968 }
1969
1970 static unsigned int
1971 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1972 {
1973         return intel_tile_size(to_i915(fb->dev)) /
1974                 intel_tile_width_bytes(fb, color_plane);
1975 }
1976
1977 /* Return the tile dimensions in pixel units */
1978 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1979                             unsigned int *tile_width,
1980                             unsigned int *tile_height)
1981 {
1982         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1983         unsigned int cpp = fb->format->cpp[color_plane];
1984
1985         *tile_width = tile_width_bytes / cpp;
1986         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1987 }
1988
1989 unsigned int
1990 intel_fb_align_height(const struct drm_framebuffer *fb,
1991                       int color_plane, unsigned int height)
1992 {
1993         unsigned int tile_height = intel_tile_height(fb, color_plane);
1994
1995         return ALIGN(height, tile_height);
1996 }
1997
1998 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1999 {
2000         unsigned int size = 0;
2001         int i;
2002
2003         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2004                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2005
2006         return size;
2007 }
2008
2009 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2010 {
2011         unsigned int size = 0;
2012         int i;
2013
2014         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2015                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2016
2017         return size;
2018 }
2019
2020 static void
2021 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2022                         const struct drm_framebuffer *fb,
2023                         unsigned int rotation)
2024 {
2025         view->type = I915_GGTT_VIEW_NORMAL;
2026         if (drm_rotation_90_or_270(rotation)) {
2027                 view->type = I915_GGTT_VIEW_ROTATED;
2028                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2029         }
2030 }
2031
2032 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2033 {
2034         if (IS_I830(dev_priv))
2035                 return 16 * 1024;
2036         else if (IS_I85X(dev_priv))
2037                 return 256;
2038         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2039                 return 32;
2040         else
2041                 return 4 * 1024;
2042 }
2043
2044 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2045 {
2046         if (INTEL_GEN(dev_priv) >= 9)
2047                 return 256 * 1024;
2048         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2049                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2050                 return 128 * 1024;
2051         else if (INTEL_GEN(dev_priv) >= 4)
2052                 return 4 * 1024;
2053         else
2054                 return 0;
2055 }
2056
2057 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2058                                          int color_plane)
2059 {
2060         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2061
2062         /* AUX_DIST needs only 4K alignment */
2063         if (color_plane == 1)
2064                 return 4096;
2065
2066         switch (fb->modifier) {
2067         case DRM_FORMAT_MOD_LINEAR:
2068                 return intel_linear_alignment(dev_priv);
2069         case I915_FORMAT_MOD_X_TILED:
2070                 if (INTEL_GEN(dev_priv) >= 9)
2071                         return 256 * 1024;
2072                 return 0;
2073         case I915_FORMAT_MOD_Y_TILED_CCS:
2074         case I915_FORMAT_MOD_Yf_TILED_CCS:
2075         case I915_FORMAT_MOD_Y_TILED:
2076         case I915_FORMAT_MOD_Yf_TILED:
2077                 return 1 * 1024 * 1024;
2078         default:
2079                 MISSING_CASE(fb->modifier);
2080                 return 0;
2081         }
2082 }
2083
2084 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2085 {
2086         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2087         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2088
2089         return INTEL_GEN(dev_priv) < 4 ||
2090                 (plane->has_fbc &&
2091                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2092 }
2093
2094 struct i915_vma *
2095 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2096                            const struct i915_ggtt_view *view,
2097                            bool uses_fence,
2098                            unsigned long *out_flags)
2099 {
2100         struct drm_device *dev = fb->dev;
2101         struct drm_i915_private *dev_priv = to_i915(dev);
2102         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2103         intel_wakeref_t wakeref;
2104         struct i915_vma *vma;
2105         unsigned int pinctl;
2106         u32 alignment;
2107
2108         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2109                 return ERR_PTR(-EINVAL);
2110
2111         alignment = intel_surf_alignment(fb, 0);
2112
2113         /* Note that the w/a also requires 64 PTE of padding following the
2114          * bo. We currently fill all unused PTE with the shadow page and so
2115          * we should always have valid PTE following the scanout preventing
2116          * the VT-d warning.
2117          */
2118         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2119                 alignment = 256 * 1024;
2120
2121         /*
2122          * Global gtt pte registers are special registers which actually forward
2123          * writes to a chunk of system memory. Which means that there is no risk
2124          * that the register values disappear as soon as we call
2125          * intel_runtime_pm_put(), so it is correct to wrap only the
2126          * pin/unpin/fence and not more.
2127          */
2128         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2129         i915_gem_object_lock(obj);
2130
2131         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2132
2133         pinctl = 0;
2134
2135         /* Valleyview is definitely limited to scanning out the first
2136          * 512MiB. Lets presume this behaviour was inherited from the
2137          * g4x display engine and that all earlier gen are similarly
2138          * limited. Testing suggests that it is a little more
2139          * complicated than this. For example, Cherryview appears quite
2140          * happy to scanout from anywhere within its global aperture.
2141          */
2142         if (HAS_GMCH(dev_priv))
2143                 pinctl |= PIN_MAPPABLE;
2144
2145         vma = i915_gem_object_pin_to_display_plane(obj,
2146                                                    alignment, view, pinctl);
2147         if (IS_ERR(vma))
2148                 goto err;
2149
2150         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2151                 int ret;
2152
2153                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2154                  * fence, whereas 965+ only requires a fence if using
2155                  * framebuffer compression.  For simplicity, we always, when
2156                  * possible, install a fence as the cost is not that onerous.
2157                  *
2158                  * If we fail to fence the tiled scanout, then either the
2159                  * modeset will reject the change (which is highly unlikely as
2160                  * the affected systems, all but one, do not have unmappable
2161                  * space) or we will not be able to enable full powersaving
2162                  * techniques (also likely not to apply due to various limits
2163                  * FBC and the like impose on the size of the buffer, which
2164                  * presumably we violated anyway with this unmappable buffer).
2165                  * Anyway, it is presumably better to stumble onwards with
2166                  * something and try to run the system in a "less than optimal"
2167                  * mode that matches the user configuration.
2168                  */
2169                 ret = i915_vma_pin_fence(vma);
2170                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2171                         i915_gem_object_unpin_from_display_plane(vma);
2172                         vma = ERR_PTR(ret);
2173                         goto err;
2174                 }
2175
2176                 if (ret == 0 && vma->fence)
2177                         *out_flags |= PLANE_HAS_FENCE;
2178         }
2179
2180         i915_vma_get(vma);
2181 err:
2182         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2183
2184         i915_gem_object_unlock(obj);
2185         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2186         return vma;
2187 }
2188
2189 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2190 {
2191         i915_gem_object_lock(vma->obj);
2192         if (flags & PLANE_HAS_FENCE)
2193                 i915_vma_unpin_fence(vma);
2194         i915_gem_object_unpin_from_display_plane(vma);
2195         i915_gem_object_unlock(vma->obj);
2196
2197         i915_vma_put(vma);
2198 }
2199
2200 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2201                           unsigned int rotation)
2202 {
2203         if (drm_rotation_90_or_270(rotation))
2204                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2205         else
2206                 return fb->pitches[color_plane];
2207 }
2208
2209 /*
2210  * Convert the x/y offsets into a linear offset.
2211  * Only valid with 0/180 degree rotation, which is fine since linear
2212  * offset is only used with linear buffers on pre-hsw and tiled buffers
2213  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2214  */
2215 u32 intel_fb_xy_to_linear(int x, int y,
2216                           const struct intel_plane_state *state,
2217                           int color_plane)
2218 {
2219         const struct drm_framebuffer *fb = state->base.fb;
2220         unsigned int cpp = fb->format->cpp[color_plane];
2221         unsigned int pitch = state->color_plane[color_plane].stride;
2222
2223         return y * pitch + x * cpp;
2224 }
2225
2226 /*
2227  * Add the x/y offsets derived from fb->offsets[] to the user
2228  * specified plane src x/y offsets. The resulting x/y offsets
2229  * specify the start of scanout from the beginning of the gtt mapping.
2230  */
2231 void intel_add_fb_offsets(int *x, int *y,
2232                           const struct intel_plane_state *state,
2233                           int color_plane)
2234
2235 {
2236         *x += state->color_plane[color_plane].x;
2237         *y += state->color_plane[color_plane].y;
2238 }
2239
2240 static u32 intel_adjust_tile_offset(int *x, int *y,
2241                                     unsigned int tile_width,
2242                                     unsigned int tile_height,
2243                                     unsigned int tile_size,
2244                                     unsigned int pitch_tiles,
2245                                     u32 old_offset,
2246                                     u32 new_offset)
2247 {
2248         unsigned int pitch_pixels = pitch_tiles * tile_width;
2249         unsigned int tiles;
2250
2251         WARN_ON(old_offset & (tile_size - 1));
2252         WARN_ON(new_offset & (tile_size - 1));
2253         WARN_ON(new_offset > old_offset);
2254
2255         tiles = (old_offset - new_offset) / tile_size;
2256
2257         *y += tiles / pitch_tiles * tile_height;
2258         *x += tiles % pitch_tiles * tile_width;
2259
2260         /* minimize x in case it got needlessly big */
2261         *y += *x / pitch_pixels * tile_height;
2262         *x %= pitch_pixels;
2263
2264         return new_offset;
2265 }
2266
2267 static bool is_surface_linear(u64 modifier, int color_plane)
2268 {
2269         return modifier == DRM_FORMAT_MOD_LINEAR;
2270 }
2271
2272 static u32 intel_adjust_aligned_offset(int *x, int *y,
2273                                        const struct drm_framebuffer *fb,
2274                                        int color_plane,
2275                                        unsigned int rotation,
2276                                        unsigned int pitch,
2277                                        u32 old_offset, u32 new_offset)
2278 {
2279         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2280         unsigned int cpp = fb->format->cpp[color_plane];
2281
2282         WARN_ON(new_offset > old_offset);
2283
2284         if (!is_surface_linear(fb->modifier, color_plane)) {
2285                 unsigned int tile_size, tile_width, tile_height;
2286                 unsigned int pitch_tiles;
2287
2288                 tile_size = intel_tile_size(dev_priv);
2289                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2290
2291                 if (drm_rotation_90_or_270(rotation)) {
2292                         pitch_tiles = pitch / tile_height;
2293                         swap(tile_width, tile_height);
2294                 } else {
2295                         pitch_tiles = pitch / (tile_width * cpp);
2296                 }
2297
2298                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2299                                          tile_size, pitch_tiles,
2300                                          old_offset, new_offset);
2301         } else {
2302                 old_offset += *y * pitch + *x * cpp;
2303
2304                 *y = (old_offset - new_offset) / pitch;
2305                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2306         }
2307
2308         return new_offset;
2309 }
2310
2311 /*
2312  * Adjust the tile offset by moving the difference into
2313  * the x/y offsets.
2314  */
2315 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2316                                              const struct intel_plane_state *state,
2317                                              int color_plane,
2318                                              u32 old_offset, u32 new_offset)
2319 {
2320         return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2321                                            state->base.rotation,
2322                                            state->color_plane[color_plane].stride,
2323                                            old_offset, new_offset);
2324 }
2325
2326 /*
2327  * Computes the aligned offset to the base tile and adjusts
2328  * x, y. bytes per pixel is assumed to be a power-of-two.
2329  *
2330  * In the 90/270 rotated case, x and y are assumed
2331  * to be already rotated to match the rotated GTT view, and
2332  * pitch is the tile_height aligned framebuffer height.
2333  *
2334  * This function is used when computing the derived information
2335  * under intel_framebuffer, so using any of that information
2336  * here is not allowed. Anything under drm_framebuffer can be
2337  * used. This is why the user has to pass in the pitch since it
2338  * is specified in the rotated orientation.
2339  */
2340 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2341                                         int *x, int *y,
2342                                         const struct drm_framebuffer *fb,
2343                                         int color_plane,
2344                                         unsigned int pitch,
2345                                         unsigned int rotation,
2346                                         u32 alignment)
2347 {
2348         unsigned int cpp = fb->format->cpp[color_plane];
2349         u32 offset, offset_aligned;
2350
2351         if (alignment)
2352                 alignment--;
2353
2354         if (!is_surface_linear(fb->modifier, color_plane)) {
2355                 unsigned int tile_size, tile_width, tile_height;
2356                 unsigned int tile_rows, tiles, pitch_tiles;
2357
2358                 tile_size = intel_tile_size(dev_priv);
2359                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2360
2361                 if (drm_rotation_90_or_270(rotation)) {
2362                         pitch_tiles = pitch / tile_height;
2363                         swap(tile_width, tile_height);
2364                 } else {
2365                         pitch_tiles = pitch / (tile_width * cpp);
2366                 }
2367
2368                 tile_rows = *y / tile_height;
2369                 *y %= tile_height;
2370
2371                 tiles = *x / tile_width;
2372                 *x %= tile_width;
2373
2374                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2375                 offset_aligned = offset & ~alignment;
2376
2377                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2378                                          tile_size, pitch_tiles,
2379                                          offset, offset_aligned);
2380         } else {
2381                 offset = *y * pitch + *x * cpp;
2382                 offset_aligned = offset & ~alignment;
2383
2384                 *y = (offset & alignment) / pitch;
2385                 *x = ((offset & alignment) - *y * pitch) / cpp;
2386         }
2387
2388         return offset_aligned;
2389 }
2390
2391 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2392                                               const struct intel_plane_state *state,
2393                                               int color_plane)
2394 {
2395         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2396         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2397         const struct drm_framebuffer *fb = state->base.fb;
2398         unsigned int rotation = state->base.rotation;
2399         int pitch = state->color_plane[color_plane].stride;
2400         u32 alignment;
2401
2402         if (intel_plane->id == PLANE_CURSOR)
2403                 alignment = intel_cursor_alignment(dev_priv);
2404         else
2405                 alignment = intel_surf_alignment(fb, color_plane);
2406
2407         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2408                                             pitch, rotation, alignment);
2409 }
2410
2411 /* Convert the fb->offset[] into x/y offsets */
2412 static int intel_fb_offset_to_xy(int *x, int *y,
2413                                  const struct drm_framebuffer *fb,
2414                                  int color_plane)
2415 {
2416         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2417         unsigned int height;
2418
2419         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2420             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2421                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2422                               fb->offsets[color_plane], color_plane);
2423                 return -EINVAL;
2424         }
2425
2426         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2427         height = ALIGN(height, intel_tile_height(fb, color_plane));
2428
2429         /* Catch potential overflows early */
2430         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2431                             fb->offsets[color_plane])) {
2432                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2433                               fb->offsets[color_plane], fb->pitches[color_plane],
2434                               color_plane);
2435                 return -ERANGE;
2436         }
2437
2438         *x = 0;
2439         *y = 0;
2440
2441         intel_adjust_aligned_offset(x, y,
2442                                     fb, color_plane, DRM_MODE_ROTATE_0,
2443                                     fb->pitches[color_plane],
2444                                     fb->offsets[color_plane], 0);
2445
2446         return 0;
2447 }
2448
2449 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2450 {
2451         switch (fb_modifier) {
2452         case I915_FORMAT_MOD_X_TILED:
2453                 return I915_TILING_X;
2454         case I915_FORMAT_MOD_Y_TILED:
2455         case I915_FORMAT_MOD_Y_TILED_CCS:
2456                 return I915_TILING_Y;
2457         default:
2458                 return I915_TILING_NONE;
2459         }
2460 }
2461
2462 /*
2463  * From the Sky Lake PRM:
2464  * "The Color Control Surface (CCS) contains the compression status of
2465  *  the cache-line pairs. The compression state of the cache-line pair
2466  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2467  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2468  *  cache-line-pairs. CCS is always Y tiled."
2469  *
2470  * Since cache line pairs refers to horizontally adjacent cache lines,
2471  * each cache line in the CCS corresponds to an area of 32x16 cache
2472  * lines on the main surface. Since each pixel is 4 bytes, this gives
2473  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2474  * main surface.
2475  */
2476 static const struct drm_format_info ccs_formats[] = {
2477         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2478           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2479         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2480           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2481         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2482           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2483         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2484           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2485 };
2486
2487 static const struct drm_format_info *
2488 lookup_format_info(const struct drm_format_info formats[],
2489                    int num_formats, u32 format)
2490 {
2491         int i;
2492
2493         for (i = 0; i < num_formats; i++) {
2494                 if (formats[i].format == format)
2495                         return &formats[i];
2496         }
2497
2498         return NULL;
2499 }
2500
2501 static const struct drm_format_info *
2502 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2503 {
2504         switch (cmd->modifier[0]) {
2505         case I915_FORMAT_MOD_Y_TILED_CCS:
2506         case I915_FORMAT_MOD_Yf_TILED_CCS:
2507                 return lookup_format_info(ccs_formats,
2508                                           ARRAY_SIZE(ccs_formats),
2509                                           cmd->pixel_format);
2510         default:
2511                 return NULL;
2512         }
2513 }
2514
2515 bool is_ccs_modifier(u64 modifier)
2516 {
2517         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2518                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2519 }
2520
2521 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2522                               u32 pixel_format, u64 modifier)
2523 {
2524         struct intel_crtc *crtc;
2525         struct intel_plane *plane;
2526
2527         /*
2528          * We assume the primary plane for pipe A has
2529          * the highest stride limits of them all.
2530          */
2531         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2532         if (!crtc)
2533                 return 0;
2534
2535         plane = to_intel_plane(crtc->base.primary);
2536
2537         return plane->max_stride(plane, pixel_format, modifier,
2538                                  DRM_MODE_ROTATE_0);
2539 }
2540
2541 static
2542 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2543                         u32 pixel_format, u64 modifier)
2544 {
2545         /*
2546          * Arbitrary limit for gen4+ chosen to match the
2547          * render engine max stride.
2548          *
2549          * The new CCS hash mode makes remapping impossible
2550          */
2551         if (!is_ccs_modifier(modifier)) {
2552                 if (INTEL_GEN(dev_priv) >= 7)
2553                         return 256*1024;
2554                 else if (INTEL_GEN(dev_priv) >= 4)
2555                         return 128*1024;
2556         }
2557
2558         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2559 }
2560
2561 static u32
2562 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2563 {
2564         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2565
2566         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2567                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2568                                                            fb->format->format,
2569                                                            fb->modifier);
2570
2571                 /*
2572                  * To make remapping with linear generally feasible
2573                  * we need the stride to be page aligned.
2574                  */
2575                 if (fb->pitches[color_plane] > max_stride)
2576                         return intel_tile_size(dev_priv);
2577                 else
2578                         return 64;
2579         } else {
2580                 return intel_tile_width_bytes(fb, color_plane);
2581         }
2582 }
2583
2584 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2585 {
2586         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2587         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2588         const struct drm_framebuffer *fb = plane_state->base.fb;
2589         int i;
2590
2591         /* We don't want to deal with remapping with cursors */
2592         if (plane->id == PLANE_CURSOR)
2593                 return false;
2594
2595         /*
2596          * The display engine limits already match/exceed the
2597          * render engine limits, so not much point in remapping.
2598          * Would also need to deal with the fence POT alignment
2599          * and gen2 2KiB GTT tile size.
2600          */
2601         if (INTEL_GEN(dev_priv) < 4)
2602                 return false;
2603
2604         /*
2605          * The new CCS hash mode isn't compatible with remapping as
2606          * the virtual address of the pages affects the compressed data.
2607          */
2608         if (is_ccs_modifier(fb->modifier))
2609                 return false;
2610
2611         /* Linear needs a page aligned stride for remapping */
2612         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2613                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2614
2615                 for (i = 0; i < fb->format->num_planes; i++) {
2616                         if (fb->pitches[i] & alignment)
2617                                 return false;
2618                 }
2619         }
2620
2621         return true;
2622 }
2623
2624 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2625 {
2626         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2627         const struct drm_framebuffer *fb = plane_state->base.fb;
2628         unsigned int rotation = plane_state->base.rotation;
2629         u32 stride, max_stride;
2630
2631         /*
2632          * No remapping for invisible planes since we don't have
2633          * an actual source viewport to remap.
2634          */
2635         if (!plane_state->base.visible)
2636                 return false;
2637
2638         if (!intel_plane_can_remap(plane_state))
2639                 return false;
2640
2641         /*
2642          * FIXME: aux plane limits on gen9+ are
2643          * unclear in Bspec, for now no checking.
2644          */
2645         stride = intel_fb_pitch(fb, 0, rotation);
2646         max_stride = plane->max_stride(plane, fb->format->format,
2647                                        fb->modifier, rotation);
2648
2649         return stride > max_stride;
2650 }
2651
2652 static int
2653 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2654                    struct drm_framebuffer *fb)
2655 {
2656         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2657         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2658         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2659         u32 gtt_offset_rotated = 0;
2660         unsigned int max_size = 0;
2661         int i, num_planes = fb->format->num_planes;
2662         unsigned int tile_size = intel_tile_size(dev_priv);
2663
2664         for (i = 0; i < num_planes; i++) {
2665                 unsigned int width, height;
2666                 unsigned int cpp, size;
2667                 u32 offset;
2668                 int x, y;
2669                 int ret;
2670
2671                 cpp = fb->format->cpp[i];
2672                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2673                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2674
2675                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2676                 if (ret) {
2677                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2678                                       i, fb->offsets[i]);
2679                         return ret;
2680                 }
2681
2682                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2683                         int hsub = fb->format->hsub;
2684                         int vsub = fb->format->vsub;
2685                         int tile_width, tile_height;
2686                         int main_x, main_y;
2687                         int ccs_x, ccs_y;
2688
2689                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2690                         tile_width *= hsub;
2691                         tile_height *= vsub;
2692
2693                         ccs_x = (x * hsub) % tile_width;
2694                         ccs_y = (y * vsub) % tile_height;
2695                         main_x = intel_fb->normal[0].x % tile_width;
2696                         main_y = intel_fb->normal[0].y % tile_height;
2697
2698                         /*
2699                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2700                          * x/y offsets must match between CCS and the main surface.
2701                          */
2702                         if (main_x != ccs_x || main_y != ccs_y) {
2703                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2704                                               main_x, main_y,
2705                                               ccs_x, ccs_y,
2706                                               intel_fb->normal[0].x,
2707                                               intel_fb->normal[0].y,
2708                                               x, y);
2709                                 return -EINVAL;
2710                         }
2711                 }
2712
2713                 /*
2714                  * The fence (if used) is aligned to the start of the object
2715                  * so having the framebuffer wrap around across the edge of the
2716                  * fenced region doesn't really work. We have no API to configure
2717                  * the fence start offset within the object (nor could we probably
2718                  * on gen2/3). So it's just easier if we just require that the
2719                  * fb layout agrees with the fence layout. We already check that the
2720                  * fb stride matches the fence stride elsewhere.
2721                  */
2722                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2723                     (x + width) * cpp > fb->pitches[i]) {
2724                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2725                                       i, fb->offsets[i]);
2726                         return -EINVAL;
2727                 }
2728
2729                 /*
2730                  * First pixel of the framebuffer from
2731                  * the start of the normal gtt mapping.
2732                  */
2733                 intel_fb->normal[i].x = x;
2734                 intel_fb->normal[i].y = y;
2735
2736                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2737                                                       fb->pitches[i],
2738                                                       DRM_MODE_ROTATE_0,
2739                                                       tile_size);
2740                 offset /= tile_size;
2741
2742                 if (!is_surface_linear(fb->modifier, i)) {
2743                         unsigned int tile_width, tile_height;
2744                         unsigned int pitch_tiles;
2745                         struct drm_rect r;
2746
2747                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2748
2749                         rot_info->plane[i].offset = offset;
2750                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2751                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2752                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2753
2754                         intel_fb->rotated[i].pitch =
2755                                 rot_info->plane[i].height * tile_height;
2756
2757                         /* how many tiles does this plane need */
2758                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2759                         /*
2760                          * If the plane isn't horizontally tile aligned,
2761                          * we need one more tile.
2762                          */
2763                         if (x != 0)
2764                                 size++;
2765
2766                         /* rotate the x/y offsets to match the GTT view */
2767                         drm_rect_init(&r, x, y, width, height);
2768                         drm_rect_rotate(&r,
2769                                         rot_info->plane[i].width * tile_width,
2770                                         rot_info->plane[i].height * tile_height,
2771                                         DRM_MODE_ROTATE_270);
2772                         x = r.x1;
2773                         y = r.y1;
2774
2775                         /* rotate the tile dimensions to match the GTT view */
2776                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2777                         swap(tile_width, tile_height);
2778
2779                         /*
2780                          * We only keep the x/y offsets, so push all of the
2781                          * gtt offset into the x/y offsets.
2782                          */
2783                         intel_adjust_tile_offset(&x, &y,
2784                                                  tile_width, tile_height,
2785                                                  tile_size, pitch_tiles,
2786                                                  gtt_offset_rotated * tile_size, 0);
2787
2788                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2789
2790                         /*
2791                          * First pixel of the framebuffer from
2792                          * the start of the rotated gtt mapping.
2793                          */
2794                         intel_fb->rotated[i].x = x;
2795                         intel_fb->rotated[i].y = y;
2796                 } else {
2797                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2798                                             x * cpp, tile_size);
2799                 }
2800
2801                 /* how many tiles in total needed in the bo */
2802                 max_size = max(max_size, offset + size);
2803         }
2804
2805         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2806                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2807                               mul_u32_u32(max_size, tile_size), obj->base.size);
2808                 return -EINVAL;
2809         }
2810
2811         return 0;
2812 }
2813
2814 static void
2815 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2816 {
2817         struct drm_i915_private *dev_priv =
2818                 to_i915(plane_state->base.plane->dev);
2819         struct drm_framebuffer *fb = plane_state->base.fb;
2820         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2821         struct intel_rotation_info *info = &plane_state->view.rotated;
2822         unsigned int rotation = plane_state->base.rotation;
2823         int i, num_planes = fb->format->num_planes;
2824         unsigned int tile_size = intel_tile_size(dev_priv);
2825         unsigned int src_x, src_y;
2826         unsigned int src_w, src_h;
2827         u32 gtt_offset = 0;
2828
2829         memset(&plane_state->view, 0, sizeof(plane_state->view));
2830         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2831                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2832
2833         src_x = plane_state->base.src.x1 >> 16;
2834         src_y = plane_state->base.src.y1 >> 16;
2835         src_w = drm_rect_width(&plane_state->base.src) >> 16;
2836         src_h = drm_rect_height(&plane_state->base.src) >> 16;
2837
2838         WARN_ON(is_ccs_modifier(fb->modifier));
2839
2840         /* Make src coordinates relative to the viewport */
2841         drm_rect_translate(&plane_state->base.src,
2842                            -(src_x << 16), -(src_y << 16));
2843
2844         /* Rotate src coordinates to match rotated GTT view */
2845         if (drm_rotation_90_or_270(rotation))
2846                 drm_rect_rotate(&plane_state->base.src,
2847                                 src_w << 16, src_h << 16,
2848                                 DRM_MODE_ROTATE_270);
2849
2850         for (i = 0; i < num_planes; i++) {
2851                 unsigned int hsub = i ? fb->format->hsub : 1;
2852                 unsigned int vsub = i ? fb->format->vsub : 1;
2853                 unsigned int cpp = fb->format->cpp[i];
2854                 unsigned int tile_width, tile_height;
2855                 unsigned int width, height;
2856                 unsigned int pitch_tiles;
2857                 unsigned int x, y;
2858                 u32 offset;
2859
2860                 intel_tile_dims(fb, i, &tile_width, &tile_height);
2861
2862                 x = src_x / hsub;
2863                 y = src_y / vsub;
2864                 width = src_w / hsub;
2865                 height = src_h / vsub;
2866
2867                 /*
2868                  * First pixel of the src viewport from the
2869                  * start of the normal gtt mapping.
2870                  */
2871                 x += intel_fb->normal[i].x;
2872                 y += intel_fb->normal[i].y;
2873
2874                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2875                                                       fb, i, fb->pitches[i],
2876                                                       DRM_MODE_ROTATE_0, tile_size);
2877                 offset /= tile_size;
2878
2879                 info->plane[i].offset = offset;
2880                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2881                                                      tile_width * cpp);
2882                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2883                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2884
2885                 if (drm_rotation_90_or_270(rotation)) {
2886                         struct drm_rect r;
2887
2888                         /* rotate the x/y offsets to match the GTT view */
2889                         drm_rect_init(&r, x, y, width, height);
2890                         drm_rect_rotate(&r,
2891                                         info->plane[i].width * tile_width,
2892                                         info->plane[i].height * tile_height,
2893                                         DRM_MODE_ROTATE_270);
2894                         x = r.x1;
2895                         y = r.y1;
2896
2897                         pitch_tiles = info->plane[i].height;
2898                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2899
2900                         /* rotate the tile dimensions to match the GTT view */
2901                         swap(tile_width, tile_height);
2902                 } else {
2903                         pitch_tiles = info->plane[i].width;
2904                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2905                 }
2906
2907                 /*
2908                  * We only keep the x/y offsets, so push all of the
2909                  * gtt offset into the x/y offsets.
2910                  */
2911                 intel_adjust_tile_offset(&x, &y,
2912                                          tile_width, tile_height,
2913                                          tile_size, pitch_tiles,
2914                                          gtt_offset * tile_size, 0);
2915
2916                 gtt_offset += info->plane[i].width * info->plane[i].height;
2917
2918                 plane_state->color_plane[i].offset = 0;
2919                 plane_state->color_plane[i].x = x;
2920                 plane_state->color_plane[i].y = y;
2921         }
2922 }
2923
2924 static int
2925 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2926 {
2927         const struct intel_framebuffer *fb =
2928                 to_intel_framebuffer(plane_state->base.fb);
2929         unsigned int rotation = plane_state->base.rotation;
2930         int i, num_planes;
2931
2932         if (!fb)
2933                 return 0;
2934
2935         num_planes = fb->base.format->num_planes;
2936
2937         if (intel_plane_needs_remap(plane_state)) {
2938                 intel_plane_remap_gtt(plane_state);
2939
2940                 /*
2941                  * Sometimes even remapping can't overcome
2942                  * the stride limitations :( Can happen with
2943                  * big plane sizes and suitably misaligned
2944                  * offsets.
2945                  */
2946                 return intel_plane_check_stride(plane_state);
2947         }
2948
2949         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2950
2951         for (i = 0; i < num_planes; i++) {
2952                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2953                 plane_state->color_plane[i].offset = 0;
2954
2955                 if (drm_rotation_90_or_270(rotation)) {
2956                         plane_state->color_plane[i].x = fb->rotated[i].x;
2957                         plane_state->color_plane[i].y = fb->rotated[i].y;
2958                 } else {
2959                         plane_state->color_plane[i].x = fb->normal[i].x;
2960                         plane_state->color_plane[i].y = fb->normal[i].y;
2961                 }
2962         }
2963
2964         /* Rotate src coordinates to match rotated GTT view */
2965         if (drm_rotation_90_or_270(rotation))
2966                 drm_rect_rotate(&plane_state->base.src,
2967                                 fb->base.width << 16, fb->base.height << 16,
2968                                 DRM_MODE_ROTATE_270);
2969
2970         return intel_plane_check_stride(plane_state);
2971 }
2972
2973 static int i9xx_format_to_fourcc(int format)
2974 {
2975         switch (format) {
2976         case DISPPLANE_8BPP:
2977                 return DRM_FORMAT_C8;
2978         case DISPPLANE_BGRX555:
2979                 return DRM_FORMAT_XRGB1555;
2980         case DISPPLANE_BGRX565:
2981                 return DRM_FORMAT_RGB565;
2982         default:
2983         case DISPPLANE_BGRX888:
2984                 return DRM_FORMAT_XRGB8888;
2985         case DISPPLANE_RGBX888:
2986                 return DRM_FORMAT_XBGR8888;
2987         case DISPPLANE_BGRX101010:
2988                 return DRM_FORMAT_XRGB2101010;
2989         case DISPPLANE_RGBX101010:
2990                 return DRM_FORMAT_XBGR2101010;
2991         case DISPPLANE_RGBX161616:
2992                 return DRM_FORMAT_XBGR16161616F;
2993         }
2994 }
2995
2996 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2997 {
2998         switch (format) {
2999         case PLANE_CTL_FORMAT_RGB_565:
3000                 return DRM_FORMAT_RGB565;
3001         case PLANE_CTL_FORMAT_NV12:
3002                 return DRM_FORMAT_NV12;
3003         case PLANE_CTL_FORMAT_P010:
3004                 return DRM_FORMAT_P010;
3005         case PLANE_CTL_FORMAT_P012:
3006                 return DRM_FORMAT_P012;
3007         case PLANE_CTL_FORMAT_P016:
3008                 return DRM_FORMAT_P016;
3009         case PLANE_CTL_FORMAT_Y210:
3010                 return DRM_FORMAT_Y210;
3011         case PLANE_CTL_FORMAT_Y212:
3012                 return DRM_FORMAT_Y212;
3013         case PLANE_CTL_FORMAT_Y216:
3014                 return DRM_FORMAT_Y216;
3015         case PLANE_CTL_FORMAT_Y410:
3016                 return DRM_FORMAT_XVYU2101010;
3017         case PLANE_CTL_FORMAT_Y412:
3018                 return DRM_FORMAT_XVYU12_16161616;
3019         case PLANE_CTL_FORMAT_Y416:
3020                 return DRM_FORMAT_XVYU16161616;
3021         default:
3022         case PLANE_CTL_FORMAT_XRGB_8888:
3023                 if (rgb_order) {
3024                         if (alpha)
3025                                 return DRM_FORMAT_ABGR8888;
3026                         else
3027                                 return DRM_FORMAT_XBGR8888;
3028                 } else {
3029                         if (alpha)
3030                                 return DRM_FORMAT_ARGB8888;
3031                         else
3032                                 return DRM_FORMAT_XRGB8888;
3033                 }
3034         case PLANE_CTL_FORMAT_XRGB_2101010:
3035                 if (rgb_order)
3036                         return DRM_FORMAT_XBGR2101010;
3037                 else
3038                         return DRM_FORMAT_XRGB2101010;
3039         case PLANE_CTL_FORMAT_XRGB_16161616F:
3040                 if (rgb_order) {
3041                         if (alpha)
3042                                 return DRM_FORMAT_ABGR16161616F;
3043                         else
3044                                 return DRM_FORMAT_XBGR16161616F;
3045                 } else {
3046                         if (alpha)
3047                                 return DRM_FORMAT_ARGB16161616F;
3048                         else
3049                                 return DRM_FORMAT_XRGB16161616F;
3050                 }
3051         }
3052 }
3053
3054 static bool
3055 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3056                               struct intel_initial_plane_config *plane_config)
3057 {
3058         struct drm_device *dev = crtc->base.dev;
3059         struct drm_i915_private *dev_priv = to_i915(dev);
3060         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3061         struct drm_framebuffer *fb = &plane_config->fb->base;
3062         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3063         u32 size_aligned = round_up(plane_config->base + plane_config->size,
3064                                     PAGE_SIZE);
3065         struct drm_i915_gem_object *obj;
3066         bool ret = false;
3067
3068         size_aligned -= base_aligned;
3069
3070         if (plane_config->size == 0)
3071                 return false;
3072
3073         /* If the FB is too big, just don't use it since fbdev is not very
3074          * important and we should probably use that space with FBC or other
3075          * features. */
3076         if (size_aligned * 2 > dev_priv->stolen_usable_size)
3077                 return false;
3078
3079         switch (fb->modifier) {
3080         case DRM_FORMAT_MOD_LINEAR:
3081         case I915_FORMAT_MOD_X_TILED:
3082         case I915_FORMAT_MOD_Y_TILED:
3083                 break;
3084         default:
3085                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3086                                  fb->modifier);
3087                 return false;
3088         }
3089
3090         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3091                                                              base_aligned,
3092                                                              base_aligned,
3093                                                              size_aligned);
3094         if (IS_ERR(obj))
3095                 return false;
3096
3097         switch (plane_config->tiling) {
3098         case I915_TILING_NONE:
3099                 break;
3100         case I915_TILING_X:
3101         case I915_TILING_Y:
3102                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3103                 break;
3104         default:
3105                 MISSING_CASE(plane_config->tiling);
3106                 goto out;
3107         }
3108
3109         mode_cmd.pixel_format = fb->format->format;
3110         mode_cmd.width = fb->width;
3111         mode_cmd.height = fb->height;
3112         mode_cmd.pitches[0] = fb->pitches[0];
3113         mode_cmd.modifier[0] = fb->modifier;
3114         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3115
3116         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3117                 DRM_DEBUG_KMS("intel fb init failed\n");
3118                 goto out;
3119         }
3120
3121
3122         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3123         ret = true;
3124 out:
3125         i915_gem_object_put(obj);
3126         return ret;
3127 }
3128
3129 static void
3130 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3131                         struct intel_plane_state *plane_state,
3132                         bool visible)
3133 {
3134         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3135
3136         plane_state->base.visible = visible;
3137
3138         if (visible)
3139                 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
3140         else
3141                 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
3142 }
3143
3144 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3145 {
3146         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3147         struct drm_plane *plane;
3148
3149         /*
3150          * Active_planes aliases if multiple "primary" or cursor planes
3151          * have been used on the same (or wrong) pipe. plane_mask uses
3152          * unique ids, hence we can use that to reconstruct active_planes.
3153          */
3154         crtc_state->active_planes = 0;
3155
3156         drm_for_each_plane_mask(plane, &dev_priv->drm,
3157                                 crtc_state->base.plane_mask)
3158                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3159 }
3160
3161 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3162                                          struct intel_plane *plane)
3163 {
3164         struct intel_crtc_state *crtc_state =
3165                 to_intel_crtc_state(crtc->base.state);
3166         struct intel_plane_state *plane_state =
3167                 to_intel_plane_state(plane->base.state);
3168
3169         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3170                       plane->base.base.id, plane->base.name,
3171                       crtc->base.base.id, crtc->base.name);
3172
3173         intel_set_plane_visible(crtc_state, plane_state, false);
3174         fixup_active_planes(crtc_state);
3175         crtc_state->data_rate[plane->id] = 0;
3176         crtc_state->min_cdclk[plane->id] = 0;
3177
3178         if (plane->id == PLANE_PRIMARY)
3179                 intel_pre_disable_primary_noatomic(&crtc->base);
3180
3181         intel_disable_plane(plane, crtc_state);
3182 }
3183
3184 static struct intel_frontbuffer *
3185 to_intel_frontbuffer(struct drm_framebuffer *fb)
3186 {
3187         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3188 }
3189
3190 static void
3191 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3192                              struct intel_initial_plane_config *plane_config)
3193 {
3194         struct drm_device *dev = intel_crtc->base.dev;
3195         struct drm_i915_private *dev_priv = to_i915(dev);
3196         struct drm_crtc *c;
3197         struct drm_plane *primary = intel_crtc->base.primary;
3198         struct drm_plane_state *plane_state = primary->state;
3199         struct intel_plane *intel_plane = to_intel_plane(primary);
3200         struct intel_plane_state *intel_state =
3201                 to_intel_plane_state(plane_state);
3202         struct drm_framebuffer *fb;
3203
3204         if (!plane_config->fb)
3205                 return;
3206
3207         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3208                 fb = &plane_config->fb->base;
3209                 goto valid_fb;
3210         }
3211
3212         kfree(plane_config->fb);
3213
3214         /*
3215          * Failed to alloc the obj, check to see if we should share
3216          * an fb with another CRTC instead
3217          */
3218         for_each_crtc(dev, c) {
3219                 struct intel_plane_state *state;
3220
3221                 if (c == &intel_crtc->base)
3222                         continue;
3223
3224                 if (!to_intel_crtc(c)->active)
3225                         continue;
3226
3227                 state = to_intel_plane_state(c->primary->state);
3228                 if (!state->vma)
3229                         continue;
3230
3231                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3232                         fb = state->base.fb;
3233                         drm_framebuffer_get(fb);
3234                         goto valid_fb;
3235                 }
3236         }
3237
3238         /*
3239          * We've failed to reconstruct the BIOS FB.  Current display state
3240          * indicates that the primary plane is visible, but has a NULL FB,
3241          * which will lead to problems later if we don't fix it up.  The
3242          * simplest solution is to just disable the primary plane now and
3243          * pretend the BIOS never had it enabled.
3244          */
3245         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3246
3247         return;
3248
3249 valid_fb:
3250         intel_state->base.rotation = plane_config->rotation;
3251         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3252                                 intel_state->base.rotation);
3253         intel_state->color_plane[0].stride =
3254                 intel_fb_pitch(fb, 0, intel_state->base.rotation);
3255
3256         intel_state->vma =
3257                 intel_pin_and_fence_fb_obj(fb,
3258                                            &intel_state->view,
3259                                            intel_plane_uses_fence(intel_state),
3260                                            &intel_state->flags);
3261         if (IS_ERR(intel_state->vma)) {
3262                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3263                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
3264
3265                 intel_state->vma = NULL;
3266                 drm_framebuffer_put(fb);
3267                 return;
3268         }
3269
3270         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3271
3272         plane_state->src_x = 0;
3273         plane_state->src_y = 0;
3274         plane_state->src_w = fb->width << 16;
3275         plane_state->src_h = fb->height << 16;
3276
3277         plane_state->crtc_x = 0;
3278         plane_state->crtc_y = 0;
3279         plane_state->crtc_w = fb->width;
3280         plane_state->crtc_h = fb->height;
3281
3282         intel_state->base.src = drm_plane_state_src(plane_state);
3283         intel_state->base.dst = drm_plane_state_dest(plane_state);
3284
3285         if (plane_config->tiling)
3286                 dev_priv->preserve_bios_swizzle = true;
3287
3288         plane_state->fb = fb;
3289         plane_state->crtc = &intel_crtc->base;
3290
3291         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3292                   &to_intel_frontbuffer(fb)->bits);
3293 }
3294
3295 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3296                                int color_plane,
3297                                unsigned int rotation)
3298 {
3299         int cpp = fb->format->cpp[color_plane];
3300
3301         switch (fb->modifier) {
3302         case DRM_FORMAT_MOD_LINEAR:
3303         case I915_FORMAT_MOD_X_TILED:
3304                 /*
3305                  * Validated limit is 4k, but has 5k should
3306                  * work apart from the following features:
3307                  * - Ytile (already limited to 4k)
3308                  * - FP16 (already limited to 4k)
3309                  * - render compression (already limited to 4k)
3310                  * - KVMR sprite and cursor (don't care)
3311                  * - horizontal panning (TODO verify this)
3312                  * - pipe and plane scaling (TODO verify this)
3313                  */
3314                 if (cpp == 8)
3315                         return 4096;
3316                 else
3317                         return 5120;
3318         case I915_FORMAT_MOD_Y_TILED_CCS:
3319         case I915_FORMAT_MOD_Yf_TILED_CCS:
3320                 /* FIXME AUX plane? */
3321         case I915_FORMAT_MOD_Y_TILED:
3322         case I915_FORMAT_MOD_Yf_TILED:
3323                 if (cpp == 8)
3324                         return 2048;
3325                 else
3326                         return 4096;
3327         default:
3328                 MISSING_CASE(fb->modifier);
3329                 return 2048;
3330         }
3331 }
3332
3333 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3334                                int color_plane,
3335                                unsigned int rotation)
3336 {
3337         int cpp = fb->format->cpp[color_plane];
3338
3339         switch (fb->modifier) {
3340         case DRM_FORMAT_MOD_LINEAR:
3341         case I915_FORMAT_MOD_X_TILED:
3342                 if (cpp == 8)
3343                         return 4096;
3344                 else
3345                         return 5120;
3346         case I915_FORMAT_MOD_Y_TILED_CCS:
3347         case I915_FORMAT_MOD_Yf_TILED_CCS:
3348                 /* FIXME AUX plane? */
3349         case I915_FORMAT_MOD_Y_TILED:
3350         case I915_FORMAT_MOD_Yf_TILED:
3351                 if (cpp == 8)
3352                         return 2048;
3353                 else
3354                         return 5120;
3355         default:
3356                 MISSING_CASE(fb->modifier);
3357                 return 2048;
3358         }
3359 }
3360
3361 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3362                                int color_plane,
3363                                unsigned int rotation)
3364 {
3365         return 5120;
3366 }
3367
3368 static int skl_max_plane_height(void)
3369 {
3370         return 4096;
3371 }
3372
3373 static int icl_max_plane_height(void)
3374 {
3375         return 4320;
3376 }
3377
3378 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3379                                            int main_x, int main_y, u32 main_offset)
3380 {
3381         const struct drm_framebuffer *fb = plane_state->base.fb;
3382         int hsub = fb->format->hsub;
3383         int vsub = fb->format->vsub;
3384         int aux_x = plane_state->color_plane[1].x;
3385         int aux_y = plane_state->color_plane[1].y;
3386         u32 aux_offset = plane_state->color_plane[1].offset;
3387         u32 alignment = intel_surf_alignment(fb, 1);
3388
3389         while (aux_offset >= main_offset && aux_y <= main_y) {
3390                 int x, y;
3391
3392                 if (aux_x == main_x && aux_y == main_y)
3393                         break;
3394
3395                 if (aux_offset == 0)
3396                         break;
3397
3398                 x = aux_x / hsub;
3399                 y = aux_y / vsub;
3400                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3401                                                                aux_offset, aux_offset - alignment);
3402                 aux_x = x * hsub + aux_x % hsub;
3403                 aux_y = y * vsub + aux_y % vsub;
3404         }
3405
3406         if (aux_x != main_x || aux_y != main_y)
3407                 return false;
3408
3409         plane_state->color_plane[1].offset = aux_offset;
3410         plane_state->color_plane[1].x = aux_x;
3411         plane_state->color_plane[1].y = aux_y;
3412
3413         return true;
3414 }
3415
3416 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3417 {
3418         struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
3419         const struct drm_framebuffer *fb = plane_state->base.fb;
3420         unsigned int rotation = plane_state->base.rotation;
3421         int x = plane_state->base.src.x1 >> 16;
3422         int y = plane_state->base.src.y1 >> 16;
3423         int w = drm_rect_width(&plane_state->base.src) >> 16;
3424         int h = drm_rect_height(&plane_state->base.src) >> 16;
3425         int max_width;
3426         int max_height;
3427         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3428
3429         if (INTEL_GEN(dev_priv) >= 11)
3430                 max_width = icl_max_plane_width(fb, 0, rotation);
3431         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3432                 max_width = glk_max_plane_width(fb, 0, rotation);
3433         else
3434                 max_width = skl_max_plane_width(fb, 0, rotation);
3435
3436         if (INTEL_GEN(dev_priv) >= 11)
3437                 max_height = icl_max_plane_height();
3438         else
3439                 max_height = skl_max_plane_height();
3440
3441         if (w > max_width || h > max_height) {
3442                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3443                               w, h, max_width, max_height);
3444                 return -EINVAL;
3445         }
3446
3447         intel_add_fb_offsets(&x, &y, plane_state, 0);
3448         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3449         alignment = intel_surf_alignment(fb, 0);
3450
3451         /*
3452          * AUX surface offset is specified as the distance from the
3453          * main surface offset, and it must be non-negative. Make
3454          * sure that is what we will get.
3455          */
3456         if (offset > aux_offset)
3457                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3458                                                            offset, aux_offset & ~(alignment - 1));
3459
3460         /*
3461          * When using an X-tiled surface, the plane blows up
3462          * if the x offset + width exceed the stride.
3463          *
3464          * TODO: linear and Y-tiled seem fine, Yf untested,
3465          */
3466         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3467                 int cpp = fb->format->cpp[0];
3468
3469                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3470                         if (offset == 0) {
3471                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3472                                 return -EINVAL;
3473                         }
3474
3475                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3476                                                                    offset, offset - alignment);
3477                 }
3478         }
3479
3480         /*
3481          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3482          * they match with the main surface x/y offsets.
3483          */
3484         if (is_ccs_modifier(fb->modifier)) {
3485                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3486                         if (offset == 0)
3487                                 break;
3488
3489                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3490                                                                    offset, offset - alignment);
3491                 }
3492
3493                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3494                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3495                         return -EINVAL;
3496                 }
3497         }
3498
3499         plane_state->color_plane[0].offset = offset;
3500         plane_state->color_plane[0].x = x;
3501         plane_state->color_plane[0].y = y;
3502
3503         /*
3504          * Put the final coordinates back so that the src
3505          * coordinate checks will see the right values.
3506          */
3507         drm_rect_translate_to(&plane_state->base.src,
3508                               x << 16, y << 16);
3509
3510         return 0;
3511 }
3512
3513 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3514 {
3515         const struct drm_framebuffer *fb = plane_state->base.fb;
3516         unsigned int rotation = plane_state->base.rotation;
3517         int max_width = skl_max_plane_width(fb, 1, rotation);
3518         int max_height = 4096;
3519         int x = plane_state->base.src.x1 >> 17;
3520         int y = plane_state->base.src.y1 >> 17;
3521         int w = drm_rect_width(&plane_state->base.src) >> 17;
3522         int h = drm_rect_height(&plane_state->base.src) >> 17;
3523         u32 offset;
3524
3525         intel_add_fb_offsets(&x, &y, plane_state, 1);
3526         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3527
3528         /* FIXME not quite sure how/if these apply to the chroma plane */
3529         if (w > max_width || h > max_height) {
3530                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3531                               w, h, max_width, max_height);
3532                 return -EINVAL;
3533         }
3534
3535         plane_state->color_plane[1].offset = offset;
3536         plane_state->color_plane[1].x = x;
3537         plane_state->color_plane[1].y = y;
3538
3539         return 0;
3540 }
3541
3542 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3543 {
3544         const struct drm_framebuffer *fb = plane_state->base.fb;
3545         int src_x = plane_state->base.src.x1 >> 16;
3546         int src_y = plane_state->base.src.y1 >> 16;
3547         int hsub = fb->format->hsub;
3548         int vsub = fb->format->vsub;
3549         int x = src_x / hsub;
3550         int y = src_y / vsub;
3551         u32 offset;
3552
3553         intel_add_fb_offsets(&x, &y, plane_state, 1);
3554         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3555
3556         plane_state->color_plane[1].offset = offset;
3557         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3558         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3559
3560         return 0;
3561 }
3562
3563 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3564 {
3565         const struct drm_framebuffer *fb = plane_state->base.fb;
3566         int ret;
3567
3568         ret = intel_plane_compute_gtt(plane_state);
3569         if (ret)
3570                 return ret;
3571
3572         if (!plane_state->base.visible)
3573                 return 0;
3574
3575         /*
3576          * Handle the AUX surface first since
3577          * the main surface setup depends on it.
3578          */
3579         if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3580                 ret = skl_check_nv12_aux_surface(plane_state);
3581                 if (ret)
3582                         return ret;
3583         } else if (is_ccs_modifier(fb->modifier)) {
3584                 ret = skl_check_ccs_aux_surface(plane_state);
3585                 if (ret)
3586                         return ret;
3587         } else {
3588                 plane_state->color_plane[1].offset = ~0xfff;
3589                 plane_state->color_plane[1].x = 0;
3590                 plane_state->color_plane[1].y = 0;
3591         }
3592
3593         ret = skl_check_main_surface(plane_state);
3594         if (ret)
3595                 return ret;
3596
3597         return 0;
3598 }
3599
3600 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3601                              const struct intel_plane_state *plane_state,
3602                              unsigned int *num, unsigned int *den)
3603 {
3604         const struct drm_framebuffer *fb = plane_state->base.fb;
3605         unsigned int cpp = fb->format->cpp[0];
3606
3607         /*
3608          * g4x bspec says 64bpp pixel rate can't exceed 80%
3609          * of cdclk when the sprite plane is enabled on the
3610          * same pipe. ilk/snb bspec says 64bpp pixel rate is
3611          * never allowed to exceed 80% of cdclk. Let's just go
3612          * with the ilk/snb limit always.
3613          */
3614         if (cpp == 8) {
3615                 *num = 10;
3616                 *den = 8;
3617         } else {
3618                 *num = 1;
3619                 *den = 1;
3620         }
3621 }
3622
3623 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3624                                 const struct intel_plane_state *plane_state)
3625 {
3626         unsigned int pixel_rate;
3627         unsigned int num, den;
3628
3629         /*
3630          * Note that crtc_state->pixel_rate accounts for both
3631          * horizontal and vertical panel fitter downscaling factors.
3632          * Pre-HSW bspec tells us to only consider the horizontal
3633          * downscaling factor here. We ignore that and just consider
3634          * both for simplicity.
3635          */
3636         pixel_rate = crtc_state->pixel_rate;
3637
3638         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3639
3640         /* two pixels per clock with double wide pipe */
3641         if (crtc_state->double_wide)
3642                 den *= 2;
3643
3644         return DIV_ROUND_UP(pixel_rate * num, den);
3645 }
3646
3647 unsigned int
3648 i9xx_plane_max_stride(struct intel_plane *plane,
3649                       u32 pixel_format, u64 modifier,
3650                       unsigned int rotation)
3651 {
3652         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3653
3654         if (!HAS_GMCH(dev_priv)) {
3655                 return 32*1024;
3656         } else if (INTEL_GEN(dev_priv) >= 4) {
3657                 if (modifier == I915_FORMAT_MOD_X_TILED)
3658                         return 16*1024;
3659                 else
3660                         return 32*1024;
3661         } else if (INTEL_GEN(dev_priv) >= 3) {
3662                 if (modifier == I915_FORMAT_MOD_X_TILED)
3663                         return 8*1024;
3664                 else
3665                         return 16*1024;
3666         } else {
3667                 if (plane->i9xx_plane == PLANE_C)
3668                         return 4*1024;
3669                 else
3670                         return 8*1024;
3671         }
3672 }
3673
3674 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3675 {
3676         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3677         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3678         u32 dspcntr = 0;
3679
3680         if (crtc_state->gamma_enable)
3681                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3682
3683         if (crtc_state->csc_enable)
3684                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3685
3686         if (INTEL_GEN(dev_priv) < 5)
3687                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3688
3689         return dspcntr;
3690 }
3691
3692 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3693                           const struct intel_plane_state *plane_state)
3694 {
3695         struct drm_i915_private *dev_priv =
3696                 to_i915(plane_state->base.plane->dev);
3697         const struct drm_framebuffer *fb = plane_state->base.fb;
3698         unsigned int rotation = plane_state->base.rotation;
3699         u32 dspcntr;
3700
3701         dspcntr = DISPLAY_PLANE_ENABLE;
3702
3703         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3704             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3705                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3706
3707         switch (fb->format->format) {
3708         case DRM_FORMAT_C8:
3709                 dspcntr |= DISPPLANE_8BPP;
3710                 break;
3711         case DRM_FORMAT_XRGB1555:
3712                 dspcntr |= DISPPLANE_BGRX555;
3713                 break;
3714         case DRM_FORMAT_RGB565:
3715                 dspcntr |= DISPPLANE_BGRX565;
3716                 break;
3717         case DRM_FORMAT_XRGB8888:
3718                 dspcntr |= DISPPLANE_BGRX888;
3719                 break;
3720         case DRM_FORMAT_XBGR8888:
3721                 dspcntr |= DISPPLANE_RGBX888;
3722                 break;
3723         case DRM_FORMAT_XRGB2101010:
3724                 dspcntr |= DISPPLANE_BGRX101010;
3725                 break;
3726         case DRM_FORMAT_XBGR2101010:
3727                 dspcntr |= DISPPLANE_RGBX101010;
3728                 break;
3729         case DRM_FORMAT_XBGR16161616F:
3730                 dspcntr |= DISPPLANE_RGBX161616;
3731                 break;
3732         default:
3733                 MISSING_CASE(fb->format->format);
3734                 return 0;
3735         }
3736
3737         if (INTEL_GEN(dev_priv) >= 4 &&
3738             fb->modifier == I915_FORMAT_MOD_X_TILED)
3739                 dspcntr |= DISPPLANE_TILED;
3740
3741         if (rotation & DRM_MODE_ROTATE_180)
3742                 dspcntr |= DISPPLANE_ROTATE_180;
3743
3744         if (rotation & DRM_MODE_REFLECT_X)
3745                 dspcntr |= DISPPLANE_MIRROR;
3746
3747         return dspcntr;
3748 }
3749
3750 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3751 {
3752         struct drm_i915_private *dev_priv =
3753                 to_i915(plane_state->base.plane->dev);
3754         const struct drm_framebuffer *fb = plane_state->base.fb;
3755         int src_x, src_y, src_w;
3756         u32 offset;
3757         int ret;
3758
3759         ret = intel_plane_compute_gtt(plane_state);
3760         if (ret)
3761                 return ret;
3762
3763         if (!plane_state->base.visible)
3764                 return 0;
3765
3766         src_w = drm_rect_width(&plane_state->base.src) >> 16;
3767         src_x = plane_state->base.src.x1 >> 16;
3768         src_y = plane_state->base.src.y1 >> 16;
3769
3770         /* Undocumented hardware limit on i965/g4x/vlv/chv */
3771         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3772                 return -EINVAL;
3773
3774         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3775
3776         if (INTEL_GEN(dev_priv) >= 4)
3777                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3778                                                             plane_state, 0);
3779         else
3780                 offset = 0;
3781
3782         /*
3783          * Put the final coordinates back so that the src
3784          * coordinate checks will see the right values.
3785          */
3786         drm_rect_translate_to(&plane_state->base.src,
3787                               src_x << 16, src_y << 16);
3788
3789         /* HSW/BDW do this automagically in hardware */
3790         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3791                 unsigned int rotation = plane_state->base.rotation;
3792                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3793                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3794
3795                 if (rotation & DRM_MODE_ROTATE_180) {
3796                         src_x += src_w - 1;
3797                         src_y += src_h - 1;
3798                 } else if (rotation & DRM_MODE_REFLECT_X) {
3799                         src_x += src_w - 1;
3800                 }
3801         }
3802
3803         plane_state->color_plane[0].offset = offset;
3804         plane_state->color_plane[0].x = src_x;
3805         plane_state->color_plane[0].y = src_y;
3806
3807         return 0;
3808 }
3809
3810 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3811 {
3812         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3813         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3814
3815         if (IS_CHERRYVIEW(dev_priv))
3816                 return i9xx_plane == PLANE_B;
3817         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3818                 return false;
3819         else if (IS_GEN(dev_priv, 4))
3820                 return i9xx_plane == PLANE_C;
3821         else
3822                 return i9xx_plane == PLANE_B ||
3823                         i9xx_plane == PLANE_C;
3824 }
3825
3826 static int
3827 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3828                  struct intel_plane_state *plane_state)
3829 {
3830         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3831         int ret;
3832
3833         ret = chv_plane_check_rotation(plane_state);
3834         if (ret)
3835                 return ret;
3836
3837         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
3838                                                   &crtc_state->base,
3839                                                   DRM_PLANE_HELPER_NO_SCALING,
3840                                                   DRM_PLANE_HELPER_NO_SCALING,
3841                                                   i9xx_plane_has_windowing(plane),
3842                                                   true);
3843         if (ret)
3844                 return ret;
3845
3846         ret = i9xx_check_plane_surface(plane_state);
3847         if (ret)
3848                 return ret;
3849
3850         if (!plane_state->base.visible)
3851                 return 0;
3852
3853         ret = intel_plane_check_src_coordinates(plane_state);
3854         if (ret)
3855                 return ret;
3856
3857         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3858
3859         return 0;
3860 }
3861
3862 static void i9xx_update_plane(struct intel_plane *plane,
3863                               const struct intel_crtc_state *crtc_state,
3864                               const struct intel_plane_state *plane_state)
3865 {
3866         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3867         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3868         u32 linear_offset;
3869         int x = plane_state->color_plane[0].x;
3870         int y = plane_state->color_plane[0].y;
3871         int crtc_x = plane_state->base.dst.x1;
3872         int crtc_y = plane_state->base.dst.y1;
3873         int crtc_w = drm_rect_width(&plane_state->base.dst);
3874         int crtc_h = drm_rect_height(&plane_state->base.dst);
3875         unsigned long irqflags;
3876         u32 dspaddr_offset;
3877         u32 dspcntr;
3878
3879         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3880
3881         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3882
3883         if (INTEL_GEN(dev_priv) >= 4)
3884                 dspaddr_offset = plane_state->color_plane[0].offset;
3885         else
3886                 dspaddr_offset = linear_offset;
3887
3888         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3889
3890         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3891
3892         if (INTEL_GEN(dev_priv) < 4) {
3893                 /*
3894                  * PLANE_A doesn't actually have a full window
3895                  * generator but let's assume we still need to
3896                  * program whatever is there.
3897                  */
3898                 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3899                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3900                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3901         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3902                 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3903                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3904                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3905                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3906         }
3907
3908         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3909                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3910         } else if (INTEL_GEN(dev_priv) >= 4) {
3911                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3912                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3913         }
3914
3915         /*
3916          * The control register self-arms if the plane was previously
3917          * disabled. Try to make the plane enable atomic by writing
3918          * the control register just before the surface register.
3919          */
3920         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3921         if (INTEL_GEN(dev_priv) >= 4)
3922                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3923                               intel_plane_ggtt_offset(plane_state) +
3924                               dspaddr_offset);
3925         else
3926                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3927                               intel_plane_ggtt_offset(plane_state) +
3928                               dspaddr_offset);
3929
3930         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3931 }
3932
3933 static void i9xx_disable_plane(struct intel_plane *plane,
3934                                const struct intel_crtc_state *crtc_state)
3935 {
3936         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3937         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3938         unsigned long irqflags;
3939         u32 dspcntr;
3940
3941         /*
3942          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3943          * enable on ilk+ affect the pipe bottom color as
3944          * well, so we must configure them even if the plane
3945          * is disabled.
3946          *
3947          * On pre-g4x there is no way to gamma correct the
3948          * pipe bottom color but we'll keep on doing this
3949          * anyway so that the crtc state readout works correctly.
3950          */
3951         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
3952
3953         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3954
3955         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3956         if (INTEL_GEN(dev_priv) >= 4)
3957                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3958         else
3959                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3960
3961         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3962 }
3963
3964 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3965                                     enum pipe *pipe)
3966 {
3967         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3968         enum intel_display_power_domain power_domain;
3969         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3970         intel_wakeref_t wakeref;
3971         bool ret;
3972         u32 val;
3973
3974         /*
3975          * Not 100% correct for planes that can move between pipes,
3976          * but that's only the case for gen2-4 which don't have any
3977          * display power wells.
3978          */
3979         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3980         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3981         if (!wakeref)
3982                 return false;
3983
3984         val = I915_READ(DSPCNTR(i9xx_plane));
3985
3986         ret = val & DISPLAY_PLANE_ENABLE;
3987
3988         if (INTEL_GEN(dev_priv) >= 5)
3989                 *pipe = plane->pipe;
3990         else
3991                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3992                         DISPPLANE_SEL_PIPE_SHIFT;
3993
3994         intel_display_power_put(dev_priv, power_domain, wakeref);
3995
3996         return ret;
3997 }
3998
3999 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4000 {
4001         struct drm_device *dev = intel_crtc->base.dev;
4002         struct drm_i915_private *dev_priv = to_i915(dev);
4003
4004         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4005         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4006         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4007 }
4008
4009 /*
4010  * This function detaches (aka. unbinds) unused scalers in hardware
4011  */
4012 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4013 {
4014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4015         const struct intel_crtc_scaler_state *scaler_state =
4016                 &crtc_state->scaler_state;
4017         int i;
4018
4019         /* loop through and disable scalers that aren't in use */
4020         for (i = 0; i < intel_crtc->num_scalers; i++) {
4021                 if (!scaler_state->scalers[i].in_use)
4022                         skl_detach_scaler(intel_crtc, i);
4023         }
4024 }
4025
4026 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4027                                           int color_plane, unsigned int rotation)
4028 {
4029         /*
4030          * The stride is either expressed as a multiple of 64 bytes chunks for
4031          * linear buffers or in number of tiles for tiled buffers.
4032          */
4033         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4034                 return 64;
4035         else if (drm_rotation_90_or_270(rotation))
4036                 return intel_tile_height(fb, color_plane);
4037         else
4038                 return intel_tile_width_bytes(fb, color_plane);
4039 }
4040
4041 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4042                      int color_plane)
4043 {
4044         const struct drm_framebuffer *fb = plane_state->base.fb;
4045         unsigned int rotation = plane_state->base.rotation;
4046         u32 stride = plane_state->color_plane[color_plane].stride;
4047
4048         if (color_plane >= fb->format->num_planes)
4049                 return 0;
4050
4051         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4052 }
4053
4054 static u32 skl_plane_ctl_format(u32 pixel_format)
4055 {
4056         switch (pixel_format) {
4057         case DRM_FORMAT_C8:
4058                 return PLANE_CTL_FORMAT_INDEXED;
4059         case DRM_FORMAT_RGB565:
4060                 return PLANE_CTL_FORMAT_RGB_565;
4061         case DRM_FORMAT_XBGR8888:
4062         case DRM_FORMAT_ABGR8888:
4063                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4064         case DRM_FORMAT_XRGB8888:
4065         case DRM_FORMAT_ARGB8888:
4066                 return PLANE_CTL_FORMAT_XRGB_8888;
4067         case DRM_FORMAT_XBGR2101010:
4068                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4069         case DRM_FORMAT_XRGB2101010:
4070                 return PLANE_CTL_FORMAT_XRGB_2101010;
4071         case DRM_FORMAT_XBGR16161616F:
4072         case DRM_FORMAT_ABGR16161616F:
4073                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4074         case DRM_FORMAT_XRGB16161616F:
4075         case DRM_FORMAT_ARGB16161616F:
4076                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4077         case DRM_FORMAT_YUYV:
4078                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4079         case DRM_FORMAT_YVYU:
4080                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4081         case DRM_FORMAT_UYVY:
4082                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4083         case DRM_FORMAT_VYUY:
4084                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4085         case DRM_FORMAT_NV12:
4086                 return PLANE_CTL_FORMAT_NV12;
4087         case DRM_FORMAT_P010:
4088                 return PLANE_CTL_FORMAT_P010;
4089         case DRM_FORMAT_P012:
4090                 return PLANE_CTL_FORMAT_P012;
4091         case DRM_FORMAT_P016:
4092                 return PLANE_CTL_FORMAT_P016;
4093         case DRM_FORMAT_Y210:
4094                 return PLANE_CTL_FORMAT_Y210;
4095         case DRM_FORMAT_Y212:
4096                 return PLANE_CTL_FORMAT_Y212;
4097         case DRM_FORMAT_Y216:
4098                 return PLANE_CTL_FORMAT_Y216;
4099         case DRM_FORMAT_XVYU2101010:
4100                 return PLANE_CTL_FORMAT_Y410;
4101         case DRM_FORMAT_XVYU12_16161616:
4102                 return PLANE_CTL_FORMAT_Y412;
4103         case DRM_FORMAT_XVYU16161616:
4104                 return PLANE_CTL_FORMAT_Y416;
4105         default:
4106                 MISSING_CASE(pixel_format);
4107         }
4108
4109         return 0;
4110 }
4111
4112 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4113 {
4114         if (!plane_state->base.fb->format->has_alpha)
4115                 return PLANE_CTL_ALPHA_DISABLE;
4116
4117         switch (plane_state->base.pixel_blend_mode) {
4118         case DRM_MODE_BLEND_PIXEL_NONE:
4119                 return PLANE_CTL_ALPHA_DISABLE;
4120         case DRM_MODE_BLEND_PREMULTI:
4121                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4122         case DRM_MODE_BLEND_COVERAGE:
4123                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4124         default:
4125                 MISSING_CASE(plane_state->base.pixel_blend_mode);
4126                 return PLANE_CTL_ALPHA_DISABLE;
4127         }
4128 }
4129
4130 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4131 {
4132         if (!plane_state->base.fb->format->has_alpha)
4133                 return PLANE_COLOR_ALPHA_DISABLE;
4134
4135         switch (plane_state->base.pixel_blend_mode) {
4136         case DRM_MODE_BLEND_PIXEL_NONE:
4137                 return PLANE_COLOR_ALPHA_DISABLE;
4138         case DRM_MODE_BLEND_PREMULTI:
4139                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4140         case DRM_MODE_BLEND_COVERAGE:
4141                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4142         default:
4143                 MISSING_CASE(plane_state->base.pixel_blend_mode);
4144                 return PLANE_COLOR_ALPHA_DISABLE;
4145         }
4146 }
4147
4148 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4149 {
4150         switch (fb_modifier) {
4151         case DRM_FORMAT_MOD_LINEAR:
4152                 break;
4153         case I915_FORMAT_MOD_X_TILED:
4154                 return PLANE_CTL_TILED_X;
4155         case I915_FORMAT_MOD_Y_TILED:
4156                 return PLANE_CTL_TILED_Y;
4157         case I915_FORMAT_MOD_Y_TILED_CCS:
4158                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4159         case I915_FORMAT_MOD_Yf_TILED:
4160                 return PLANE_CTL_TILED_YF;
4161         case I915_FORMAT_MOD_Yf_TILED_CCS:
4162                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4163         default:
4164                 MISSING_CASE(fb_modifier);
4165         }
4166
4167         return 0;
4168 }
4169
4170 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4171 {
4172         switch (rotate) {
4173         case DRM_MODE_ROTATE_0:
4174                 break;
4175         /*
4176          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4177          * while i915 HW rotation is clockwise, thats why this swapping.
4178          */
4179         case DRM_MODE_ROTATE_90:
4180                 return PLANE_CTL_ROTATE_270;
4181         case DRM_MODE_ROTATE_180:
4182                 return PLANE_CTL_ROTATE_180;
4183         case DRM_MODE_ROTATE_270:
4184                 return PLANE_CTL_ROTATE_90;
4185         default:
4186                 MISSING_CASE(rotate);
4187         }
4188
4189         return 0;
4190 }
4191
4192 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4193 {
4194         switch (reflect) {
4195         case 0:
4196                 break;
4197         case DRM_MODE_REFLECT_X:
4198                 return PLANE_CTL_FLIP_HORIZONTAL;
4199         case DRM_MODE_REFLECT_Y:
4200         default:
4201                 MISSING_CASE(reflect);
4202         }
4203
4204         return 0;
4205 }
4206
4207 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4208 {
4209         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4210         u32 plane_ctl = 0;
4211
4212         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4213                 return plane_ctl;
4214
4215         if (crtc_state->gamma_enable)
4216                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4217
4218         if (crtc_state->csc_enable)
4219                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4220
4221         return plane_ctl;
4222 }
4223
4224 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4225                   const struct intel_plane_state *plane_state)
4226 {
4227         struct drm_i915_private *dev_priv =
4228                 to_i915(plane_state->base.plane->dev);
4229         const struct drm_framebuffer *fb = plane_state->base.fb;
4230         unsigned int rotation = plane_state->base.rotation;
4231         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4232         u32 plane_ctl;
4233
4234         plane_ctl = PLANE_CTL_ENABLE;
4235
4236         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4237                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4238                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4239
4240                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
4241                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4242
4243                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4244                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4245         }
4246
4247         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4248         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4249         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4250
4251         if (INTEL_GEN(dev_priv) >= 10)
4252                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4253                                                 DRM_MODE_REFLECT_MASK);
4254
4255         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4256                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4257         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4258                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4259
4260         return plane_ctl;
4261 }
4262
4263 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4264 {
4265         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4266         u32 plane_color_ctl = 0;
4267
4268         if (INTEL_GEN(dev_priv) >= 11)
4269                 return plane_color_ctl;
4270
4271         if (crtc_state->gamma_enable)
4272                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4273
4274         if (crtc_state->csc_enable)
4275                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4276
4277         return plane_color_ctl;
4278 }
4279
4280 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4281                         const struct intel_plane_state *plane_state)
4282 {
4283         struct drm_i915_private *dev_priv =
4284                 to_i915(plane_state->base.plane->dev);
4285         const struct drm_framebuffer *fb = plane_state->base.fb;
4286         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
4287         u32 plane_color_ctl = 0;
4288
4289         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4290         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4291
4292         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4293                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
4294                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4295                 else
4296                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4297
4298                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4299                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4300         } else if (fb->format->is_yuv) {
4301                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4302         }
4303
4304         return plane_color_ctl;
4305 }
4306
4307 static int
4308 __intel_display_resume(struct drm_device *dev,
4309                        struct drm_atomic_state *state,
4310                        struct drm_modeset_acquire_ctx *ctx)
4311 {
4312         struct drm_crtc_state *crtc_state;
4313         struct drm_crtc *crtc;
4314         int i, ret;
4315
4316         intel_modeset_setup_hw_state(dev, ctx);
4317         intel_vga_redisable(to_i915(dev));
4318
4319         if (!state)
4320                 return 0;
4321
4322         /*
4323          * We've duplicated the state, pointers to the old state are invalid.
4324          *
4325          * Don't attempt to use the old state until we commit the duplicated state.
4326          */
4327         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4328                 /*
4329                  * Force recalculation even if we restore
4330                  * current state. With fast modeset this may not result
4331                  * in a modeset when the state is compatible.
4332                  */
4333                 crtc_state->mode_changed = true;
4334         }
4335
4336         /* ignore any reset values/BIOS leftovers in the WM registers */
4337         if (!HAS_GMCH(to_i915(dev)))
4338                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4339
4340         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4341
4342         WARN_ON(ret == -EDEADLK);
4343         return ret;
4344 }
4345
4346 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4347 {
4348         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4349                 intel_has_gpu_reset(&dev_priv->gt));
4350 }
4351
4352 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4353 {
4354         struct drm_device *dev = &dev_priv->drm;
4355         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4356         struct drm_atomic_state *state;
4357         int ret;
4358
4359         /* reset doesn't touch the display */
4360         if (!i915_modparams.force_reset_modeset_test &&
4361             !gpu_reset_clobbers_display(dev_priv))
4362                 return;
4363
4364         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4365         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4366         smp_mb__after_atomic();
4367         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4368
4369         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4370                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4371                 intel_gt_set_wedged(&dev_priv->gt);
4372         }
4373
4374         /*
4375          * Need mode_config.mutex so that we don't
4376          * trample ongoing ->detect() and whatnot.
4377          */
4378         mutex_lock(&dev->mode_config.mutex);
4379         drm_modeset_acquire_init(ctx, 0);
4380         while (1) {
4381                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4382                 if (ret != -EDEADLK)
4383                         break;
4384
4385                 drm_modeset_backoff(ctx);
4386         }
4387         /*
4388          * Disabling the crtcs gracefully seems nicer. Also the
4389          * g33 docs say we should at least disable all the planes.
4390          */
4391         state = drm_atomic_helper_duplicate_state(dev, ctx);
4392         if (IS_ERR(state)) {
4393                 ret = PTR_ERR(state);
4394                 DRM_ERROR("Duplicating state failed with %i\n", ret);
4395                 return;
4396         }
4397
4398         ret = drm_atomic_helper_disable_all(dev, ctx);
4399         if (ret) {
4400                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4401                 drm_atomic_state_put(state);
4402                 return;
4403         }
4404
4405         dev_priv->modeset_restore_state = state;
4406         state->acquire_ctx = ctx;
4407 }
4408
4409 void intel_finish_reset(struct drm_i915_private *dev_priv)
4410 {
4411         struct drm_device *dev = &dev_priv->drm;
4412         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4413         struct drm_atomic_state *state;
4414         int ret;
4415
4416         /* reset doesn't touch the display */
4417         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4418                 return;
4419
4420         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4421         if (!state)
4422                 goto unlock;
4423
4424         /* reset doesn't touch the display */
4425         if (!gpu_reset_clobbers_display(dev_priv)) {
4426                 /* for testing only restore the display */
4427                 ret = __intel_display_resume(dev, state, ctx);
4428                 if (ret)
4429                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4430         } else {
4431                 /*
4432                  * The display has been reset as well,
4433                  * so need a full re-initialization.
4434                  */
4435                 intel_pps_unlock_regs_wa(dev_priv);
4436                 intel_modeset_init_hw(dev_priv);
4437                 intel_init_clock_gating(dev_priv);
4438
4439                 spin_lock_irq(&dev_priv->irq_lock);
4440                 if (dev_priv->display.hpd_irq_setup)
4441                         dev_priv->display.hpd_irq_setup(dev_priv);
4442                 spin_unlock_irq(&dev_priv->irq_lock);
4443
4444                 ret = __intel_display_resume(dev, state, ctx);
4445                 if (ret)
4446                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4447
4448                 intel_hpd_init(dev_priv);
4449         }
4450
4451         drm_atomic_state_put(state);
4452 unlock:
4453         drm_modeset_drop_locks(ctx);
4454         drm_modeset_acquire_fini(ctx);
4455         mutex_unlock(&dev->mode_config.mutex);
4456
4457         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4458 }
4459
4460 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4461 {
4462         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4463         enum pipe pipe = crtc->pipe;
4464         u32 tmp;
4465
4466         tmp = I915_READ(PIPE_CHICKEN(pipe));
4467
4468         /*
4469          * Display WA #1153: icl
4470          * enable hardware to bypass the alpha math
4471          * and rounding for per-pixel values 00 and 0xff
4472          */
4473         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4474         /*
4475          * Display WA # 1605353570: icl
4476          * Set the pixel rounding bit to 1 for allowing
4477          * passthrough of Frame buffer pixels unmodified
4478          * across pipe
4479          */
4480         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4481         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4482 }
4483
4484 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4485 {
4486         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4487         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4488         u32 trans_ddi_func_ctl2_val;
4489         u8 master_select;
4490
4491         /*
4492          * Configure the master select and enable Transcoder Port Sync for
4493          * Slave CRTCs transcoder.
4494          */
4495         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4496                 return;
4497
4498         if (crtc_state->master_transcoder == TRANSCODER_EDP)
4499                 master_select = 0;
4500         else
4501                 master_select = crtc_state->master_transcoder + 1;
4502
4503         /* Set the master select bits for Tranascoder Port Sync */
4504         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4505                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4506                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4507         /* Enable Transcoder Port Sync */
4508         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4509
4510         I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4511                    trans_ddi_func_ctl2_val);
4512 }
4513
4514 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4515 {
4516         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4517         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4518
4519         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4520                 return;
4521
4522         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4523                       transcoder_name(old_crtc_state->cpu_transcoder));
4524
4525         I915_WRITE(TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0);
4526 }
4527
4528 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4529 {
4530         struct drm_device *dev = crtc->base.dev;
4531         struct drm_i915_private *dev_priv = to_i915(dev);
4532         enum pipe pipe = crtc->pipe;
4533         i915_reg_t reg;
4534         u32 temp;
4535
4536         /* enable normal train */
4537         reg = FDI_TX_CTL(pipe);
4538         temp = I915_READ(reg);
4539         if (IS_IVYBRIDGE(dev_priv)) {
4540                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4541                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4542         } else {
4543                 temp &= ~FDI_LINK_TRAIN_NONE;
4544                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4545         }
4546         I915_WRITE(reg, temp);
4547
4548         reg = FDI_RX_CTL(pipe);
4549         temp = I915_READ(reg);
4550         if (HAS_PCH_CPT(dev_priv)) {
4551                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4552                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4553         } else {
4554                 temp &= ~FDI_LINK_TRAIN_NONE;
4555                 temp |= FDI_LINK_TRAIN_NONE;
4556         }
4557         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4558
4559         /* wait one idle pattern time */
4560         POSTING_READ(reg);
4561         udelay(1000);
4562
4563         /* IVB wants error correction enabled */
4564         if (IS_IVYBRIDGE(dev_priv))
4565                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4566                            FDI_FE_ERRC_ENABLE);
4567 }
4568
4569 /* The FDI link training functions for ILK/Ibexpeak. */
4570 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4571                                     const struct intel_crtc_state *crtc_state)
4572 {
4573         struct drm_device *dev = crtc->base.dev;
4574         struct drm_i915_private *dev_priv = to_i915(dev);
4575         enum pipe pipe = crtc->pipe;
4576         i915_reg_t reg;
4577         u32 temp, tries;
4578
4579         /* FDI needs bits from pipe first */
4580         assert_pipe_enabled(dev_priv, pipe);
4581
4582         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4583            for train result */
4584         reg = FDI_RX_IMR(pipe);
4585         temp = I915_READ(reg);
4586         temp &= ~FDI_RX_SYMBOL_LOCK;
4587         temp &= ~FDI_RX_BIT_LOCK;
4588         I915_WRITE(reg, temp);
4589         I915_READ(reg);
4590         udelay(150);
4591
4592         /* enable CPU FDI TX and PCH FDI RX */
4593         reg = FDI_TX_CTL(pipe);
4594         temp = I915_READ(reg);
4595         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4596         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4597         temp &= ~FDI_LINK_TRAIN_NONE;
4598         temp |= FDI_LINK_TRAIN_PATTERN_1;
4599         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4600
4601         reg = FDI_RX_CTL(pipe);
4602         temp = I915_READ(reg);
4603         temp &= ~FDI_LINK_TRAIN_NONE;
4604         temp |= FDI_LINK_TRAIN_PATTERN_1;
4605         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4606
4607         POSTING_READ(reg);
4608         udelay(150);
4609
4610         /* Ironlake workaround, enable clock pointer after FDI enable*/
4611         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4612         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4613                    FDI_RX_PHASE_SYNC_POINTER_EN);
4614
4615         reg = FDI_RX_IIR(pipe);
4616         for (tries = 0; tries < 5; tries++) {
4617                 temp = I915_READ(reg);
4618                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4619
4620                 if ((temp & FDI_RX_BIT_LOCK)) {
4621                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4622                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4623                         break;
4624                 }
4625         }
4626         if (tries == 5)
4627                 DRM_ERROR("FDI train 1 fail!\n");
4628
4629         /* Train 2 */
4630         reg = FDI_TX_CTL(pipe);
4631         temp = I915_READ(reg);
4632         temp &= ~FDI_LINK_TRAIN_NONE;
4633         temp |= FDI_LINK_TRAIN_PATTERN_2;
4634         I915_WRITE(reg, temp);
4635
4636         reg = FDI_RX_CTL(pipe);
4637         temp = I915_READ(reg);
4638         temp &= ~FDI_LINK_TRAIN_NONE;
4639         temp |= FDI_LINK_TRAIN_PATTERN_2;
4640         I915_WRITE(reg, temp);
4641
4642         POSTING_READ(reg);
4643         udelay(150);
4644
4645         reg = FDI_RX_IIR(pipe);
4646         for (tries = 0; tries < 5; tries++) {
4647                 temp = I915_READ(reg);
4648                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4649
4650                 if (temp & FDI_RX_SYMBOL_LOCK) {
4651                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4652                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4653                         break;
4654                 }
4655         }
4656         if (tries == 5)
4657                 DRM_ERROR("FDI train 2 fail!\n");
4658
4659         DRM_DEBUG_KMS("FDI train done\n");
4660
4661 }
4662
4663 static const int snb_b_fdi_train_param[] = {
4664         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4665         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4666         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4667         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4668 };
4669
4670 /* The FDI link training functions for SNB/Cougarpoint. */
4671 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4672                                 const struct intel_crtc_state *crtc_state)
4673 {
4674         struct drm_device *dev = crtc->base.dev;
4675         struct drm_i915_private *dev_priv = to_i915(dev);
4676         enum pipe pipe = crtc->pipe;
4677         i915_reg_t reg;
4678         u32 temp, i, retry;
4679
4680         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4681            for train result */
4682         reg = FDI_RX_IMR(pipe);
4683         temp = I915_READ(reg);
4684         temp &= ~FDI_RX_SYMBOL_LOCK;
4685         temp &= ~FDI_RX_BIT_LOCK;
4686         I915_WRITE(reg, temp);
4687
4688         POSTING_READ(reg);
4689         udelay(150);
4690
4691         /* enable CPU FDI TX and PCH FDI RX */
4692         reg = FDI_TX_CTL(pipe);
4693         temp = I915_READ(reg);
4694         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4695         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4696         temp &= ~FDI_LINK_TRAIN_NONE;
4697         temp |= FDI_LINK_TRAIN_PATTERN_1;
4698         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4699         /* SNB-B */
4700         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4701         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4702
4703         I915_WRITE(FDI_RX_MISC(pipe),
4704                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4705
4706         reg = FDI_RX_CTL(pipe);
4707         temp = I915_READ(reg);
4708         if (HAS_PCH_CPT(dev_priv)) {
4709                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4710                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4711         } else {
4712                 temp &= ~FDI_LINK_TRAIN_NONE;
4713                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4714         }
4715         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4716
4717         POSTING_READ(reg);
4718         udelay(150);
4719
4720         for (i = 0; i < 4; i++) {
4721                 reg = FDI_TX_CTL(pipe);
4722                 temp = I915_READ(reg);
4723                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4724                 temp |= snb_b_fdi_train_param[i];
4725                 I915_WRITE(reg, temp);
4726
4727                 POSTING_READ(reg);
4728                 udelay(500);
4729
4730                 for (retry = 0; retry < 5; retry++) {
4731                         reg = FDI_RX_IIR(pipe);
4732                         temp = I915_READ(reg);
4733                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4734                         if (temp & FDI_RX_BIT_LOCK) {
4735                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4736                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4737                                 break;
4738                         }
4739                         udelay(50);
4740                 }
4741                 if (retry < 5)
4742                         break;
4743         }
4744         if (i == 4)
4745                 DRM_ERROR("FDI train 1 fail!\n");
4746
4747         /* Train 2 */
4748         reg = FDI_TX_CTL(pipe);
4749         temp = I915_READ(reg);
4750         temp &= ~FDI_LINK_TRAIN_NONE;
4751         temp |= FDI_LINK_TRAIN_PATTERN_2;
4752         if (IS_GEN(dev_priv, 6)) {
4753                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4754                 /* SNB-B */
4755                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4756         }
4757         I915_WRITE(reg, temp);
4758
4759         reg = FDI_RX_CTL(pipe);
4760         temp = I915_READ(reg);
4761         if (HAS_PCH_CPT(dev_priv)) {
4762                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4763                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4764         } else {
4765                 temp &= ~FDI_LINK_TRAIN_NONE;
4766                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4767         }
4768         I915_WRITE(reg, temp);
4769
4770         POSTING_READ(reg);
4771         udelay(150);
4772
4773         for (i = 0; i < 4; i++) {
4774                 reg = FDI_TX_CTL(pipe);
4775                 temp = I915_READ(reg);
4776                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4777                 temp |= snb_b_fdi_train_param[i];
4778                 I915_WRITE(reg, temp);
4779
4780                 POSTING_READ(reg);
4781                 udelay(500);
4782
4783                 for (retry = 0; retry < 5; retry++) {
4784                         reg = FDI_RX_IIR(pipe);
4785                         temp = I915_READ(reg);
4786                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4787                         if (temp & FDI_RX_SYMBOL_LOCK) {
4788                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4789                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4790                                 break;
4791                         }
4792                         udelay(50);
4793                 }
4794                 if (retry < 5)
4795                         break;
4796         }
4797         if (i == 4)
4798                 DRM_ERROR("FDI train 2 fail!\n");
4799
4800         DRM_DEBUG_KMS("FDI train done.\n");
4801 }
4802
4803 /* Manual link training for Ivy Bridge A0 parts */
4804 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4805                                       const struct intel_crtc_state *crtc_state)
4806 {
4807         struct drm_device *dev = crtc->base.dev;
4808         struct drm_i915_private *dev_priv = to_i915(dev);
4809         enum pipe pipe = crtc->pipe;
4810         i915_reg_t reg;
4811         u32 temp, i, j;
4812
4813         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4814            for train result */
4815         reg = FDI_RX_IMR(pipe);
4816         temp = I915_READ(reg);
4817         temp &= ~FDI_RX_SYMBOL_LOCK;
4818         temp &= ~FDI_RX_BIT_LOCK;
4819         I915_WRITE(reg, temp);
4820
4821         POSTING_READ(reg);
4822         udelay(150);
4823
4824         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4825                       I915_READ(FDI_RX_IIR(pipe)));
4826
4827         /* Try each vswing and preemphasis setting twice before moving on */
4828         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4829                 /* disable first in case we need to retry */
4830                 reg = FDI_TX_CTL(pipe);
4831                 temp = I915_READ(reg);
4832                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4833                 temp &= ~FDI_TX_ENABLE;
4834                 I915_WRITE(reg, temp);
4835
4836                 reg = FDI_RX_CTL(pipe);
4837                 temp = I915_READ(reg);
4838                 temp &= ~FDI_LINK_TRAIN_AUTO;
4839                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4840                 temp &= ~FDI_RX_ENABLE;
4841                 I915_WRITE(reg, temp);
4842
4843                 /* enable CPU FDI TX and PCH FDI RX */
4844                 reg = FDI_TX_CTL(pipe);
4845                 temp = I915_READ(reg);
4846                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4847                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4848                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4849                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4850                 temp |= snb_b_fdi_train_param[j/2];
4851                 temp |= FDI_COMPOSITE_SYNC;
4852                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4853
4854                 I915_WRITE(FDI_RX_MISC(pipe),
4855                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4856
4857                 reg = FDI_RX_CTL(pipe);
4858                 temp = I915_READ(reg);
4859                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4860                 temp |= FDI_COMPOSITE_SYNC;
4861                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4862
4863                 POSTING_READ(reg);
4864                 udelay(1); /* should be 0.5us */
4865
4866                 for (i = 0; i < 4; i++) {
4867                         reg = FDI_RX_IIR(pipe);
4868                         temp = I915_READ(reg);
4869                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4870
4871                         if (temp & FDI_RX_BIT_LOCK ||
4872                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4873                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4874                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4875                                               i);
4876                                 break;
4877                         }
4878                         udelay(1); /* should be 0.5us */
4879                 }
4880                 if (i == 4) {
4881                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4882                         continue;
4883                 }
4884
4885                 /* Train 2 */
4886                 reg = FDI_TX_CTL(pipe);
4887                 temp = I915_READ(reg);
4888                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4889                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4890                 I915_WRITE(reg, temp);
4891
4892                 reg = FDI_RX_CTL(pipe);
4893                 temp = I915_READ(reg);
4894                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4895                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4896                 I915_WRITE(reg, temp);
4897
4898                 POSTING_READ(reg);
4899                 udelay(2); /* should be 1.5us */
4900
4901                 for (i = 0; i < 4; i++) {
4902                         reg = FDI_RX_IIR(pipe);
4903                         temp = I915_READ(reg);
4904                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4905
4906                         if (temp & FDI_RX_SYMBOL_LOCK ||
4907                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4908                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4909                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4910                                               i);
4911                                 goto train_done;
4912                         }
4913                         udelay(2); /* should be 1.5us */
4914                 }
4915                 if (i == 4)
4916                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4917         }
4918
4919 train_done:
4920         DRM_DEBUG_KMS("FDI train done.\n");
4921 }
4922
4923 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4924 {
4925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4926         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4927         enum pipe pipe = intel_crtc->pipe;
4928         i915_reg_t reg;
4929         u32 temp;
4930
4931         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4932         reg = FDI_RX_CTL(pipe);
4933         temp = I915_READ(reg);
4934         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4935         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4936         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4937         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4938
4939         POSTING_READ(reg);
4940         udelay(200);
4941
4942         /* Switch from Rawclk to PCDclk */
4943         temp = I915_READ(reg);
4944         I915_WRITE(reg, temp | FDI_PCDCLK);
4945
4946         POSTING_READ(reg);
4947         udelay(200);
4948
4949         /* Enable CPU FDI TX PLL, always on for Ironlake */
4950         reg = FDI_TX_CTL(pipe);
4951         temp = I915_READ(reg);
4952         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4953                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4954
4955                 POSTING_READ(reg);
4956                 udelay(100);
4957         }
4958 }
4959
4960 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4961 {
4962         struct drm_device *dev = intel_crtc->base.dev;
4963         struct drm_i915_private *dev_priv = to_i915(dev);
4964         enum pipe pipe = intel_crtc->pipe;
4965         i915_reg_t reg;
4966         u32 temp;
4967
4968         /* Switch from PCDclk to Rawclk */
4969         reg = FDI_RX_CTL(pipe);
4970         temp = I915_READ(reg);
4971         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4972
4973         /* Disable CPU FDI TX PLL */
4974         reg = FDI_TX_CTL(pipe);
4975         temp = I915_READ(reg);
4976         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4977
4978         POSTING_READ(reg);
4979         udelay(100);
4980
4981         reg = FDI_RX_CTL(pipe);
4982         temp = I915_READ(reg);
4983         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4984
4985         /* Wait for the clocks to turn off. */
4986         POSTING_READ(reg);
4987         udelay(100);
4988 }
4989
4990 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4991 {
4992         struct drm_device *dev = crtc->dev;
4993         struct drm_i915_private *dev_priv = to_i915(dev);
4994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4995         enum pipe pipe = intel_crtc->pipe;
4996         i915_reg_t reg;
4997         u32 temp;
4998
4999         /* disable CPU FDI tx and PCH FDI rx */
5000         reg = FDI_TX_CTL(pipe);
5001         temp = I915_READ(reg);
5002         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5003         POSTING_READ(reg);
5004
5005         reg = FDI_RX_CTL(pipe);
5006         temp = I915_READ(reg);
5007         temp &= ~(0x7 << 16);
5008         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5009         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5010
5011         POSTING_READ(reg);
5012         udelay(100);
5013
5014         /* Ironlake workaround, disable clock pointer after downing FDI */
5015         if (HAS_PCH_IBX(dev_priv))
5016                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5017
5018         /* still set train pattern 1 */
5019         reg = FDI_TX_CTL(pipe);
5020         temp = I915_READ(reg);
5021         temp &= ~FDI_LINK_TRAIN_NONE;
5022         temp |= FDI_LINK_TRAIN_PATTERN_1;
5023         I915_WRITE(reg, temp);
5024
5025         reg = FDI_RX_CTL(pipe);
5026         temp = I915_READ(reg);
5027         if (HAS_PCH_CPT(dev_priv)) {
5028                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5029                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5030         } else {
5031                 temp &= ~FDI_LINK_TRAIN_NONE;
5032                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5033         }
5034         /* BPC in FDI rx is consistent with that in PIPECONF */
5035         temp &= ~(0x07 << 16);
5036         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5037         I915_WRITE(reg, temp);
5038
5039         POSTING_READ(reg);
5040         udelay(100);
5041 }
5042
5043 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5044 {
5045         struct drm_crtc *crtc;
5046         bool cleanup_done;
5047
5048         drm_for_each_crtc(crtc, &dev_priv->drm) {
5049                 struct drm_crtc_commit *commit;
5050                 spin_lock(&crtc->commit_lock);
5051                 commit = list_first_entry_or_null(&crtc->commit_list,
5052                                                   struct drm_crtc_commit, commit_entry);
5053                 cleanup_done = commit ?
5054                         try_wait_for_completion(&commit->cleanup_done) : true;
5055                 spin_unlock(&crtc->commit_lock);
5056
5057                 if (cleanup_done)
5058                         continue;
5059
5060                 drm_crtc_wait_one_vblank(crtc);
5061
5062                 return true;
5063         }
5064
5065         return false;
5066 }
5067
5068 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5069 {
5070         u32 temp;
5071
5072         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5073
5074         mutex_lock(&dev_priv->sb_lock);
5075
5076         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5077         temp |= SBI_SSCCTL_DISABLE;
5078         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5079
5080         mutex_unlock(&dev_priv->sb_lock);
5081 }
5082
5083 /* Program iCLKIP clock to the desired frequency */
5084 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5085 {
5086         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5087         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5088         int clock = crtc_state->base.adjusted_mode.crtc_clock;
5089         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5090         u32 temp;
5091
5092         lpt_disable_iclkip(dev_priv);
5093
5094         /* The iCLK virtual clock root frequency is in MHz,
5095          * but the adjusted_mode->crtc_clock in in KHz. To get the
5096          * divisors, it is necessary to divide one by another, so we
5097          * convert the virtual clock precision to KHz here for higher
5098          * precision.
5099          */
5100         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5101                 u32 iclk_virtual_root_freq = 172800 * 1000;
5102                 u32 iclk_pi_range = 64;
5103                 u32 desired_divisor;
5104
5105                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5106                                                     clock << auxdiv);
5107                 divsel = (desired_divisor / iclk_pi_range) - 2;
5108                 phaseinc = desired_divisor % iclk_pi_range;
5109
5110                 /*
5111                  * Near 20MHz is a corner case which is
5112                  * out of range for the 7-bit divisor
5113                  */
5114                 if (divsel <= 0x7f)
5115                         break;
5116         }
5117
5118         /* This should not happen with any sane values */
5119         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5120                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5121         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5122                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5123
5124         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5125                         clock,
5126                         auxdiv,
5127                         divsel,
5128                         phasedir,
5129                         phaseinc);
5130
5131         mutex_lock(&dev_priv->sb_lock);
5132
5133         /* Program SSCDIVINTPHASE6 */
5134         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5135         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5136         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5137         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5138         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5139         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5140         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5141         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5142
5143         /* Program SSCAUXDIV */
5144         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5145         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5146         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5147         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5148
5149         /* Enable modulator and associated divider */
5150         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5151         temp &= ~SBI_SSCCTL_DISABLE;
5152         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5153
5154         mutex_unlock(&dev_priv->sb_lock);
5155
5156         /* Wait for initialization time */
5157         udelay(24);
5158
5159         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5160 }
5161
5162 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5163 {
5164         u32 divsel, phaseinc, auxdiv;
5165         u32 iclk_virtual_root_freq = 172800 * 1000;
5166         u32 iclk_pi_range = 64;
5167         u32 desired_divisor;
5168         u32 temp;
5169
5170         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5171                 return 0;
5172
5173         mutex_lock(&dev_priv->sb_lock);
5174
5175         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5176         if (temp & SBI_SSCCTL_DISABLE) {
5177                 mutex_unlock(&dev_priv->sb_lock);
5178                 return 0;
5179         }
5180
5181         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5182         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5183                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5184         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5185                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5186
5187         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5188         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5189                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5190
5191         mutex_unlock(&dev_priv->sb_lock);
5192
5193         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5194
5195         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5196                                  desired_divisor << auxdiv);
5197 }
5198
5199 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5200                                                 enum pipe pch_transcoder)
5201 {
5202         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5203         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5204         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5205
5206         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5207                    I915_READ(HTOTAL(cpu_transcoder)));
5208         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5209                    I915_READ(HBLANK(cpu_transcoder)));
5210         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5211                    I915_READ(HSYNC(cpu_transcoder)));
5212
5213         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5214                    I915_READ(VTOTAL(cpu_transcoder)));
5215         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5216                    I915_READ(VBLANK(cpu_transcoder)));
5217         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5218                    I915_READ(VSYNC(cpu_transcoder)));
5219         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5220                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
5221 }
5222
5223 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5224 {
5225         u32 temp;
5226
5227         temp = I915_READ(SOUTH_CHICKEN1);
5228         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5229                 return;
5230
5231         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5232         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5233
5234         temp &= ~FDI_BC_BIFURCATION_SELECT;
5235         if (enable)
5236                 temp |= FDI_BC_BIFURCATION_SELECT;
5237
5238         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5239         I915_WRITE(SOUTH_CHICKEN1, temp);
5240         POSTING_READ(SOUTH_CHICKEN1);
5241 }
5242
5243 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5244 {
5245         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5246         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5247
5248         switch (crtc->pipe) {
5249         case PIPE_A:
5250                 break;
5251         case PIPE_B:
5252                 if (crtc_state->fdi_lanes > 2)
5253                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5254                 else
5255                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5256
5257                 break;
5258         case PIPE_C:
5259                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5260
5261                 break;
5262         default:
5263                 BUG();
5264         }
5265 }
5266
5267 /*
5268  * Finds the encoder associated with the given CRTC. This can only be
5269  * used when we know that the CRTC isn't feeding multiple encoders!
5270  */
5271 static struct intel_encoder *
5272 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5273                            const struct intel_crtc_state *crtc_state)
5274 {
5275         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5276         const struct drm_connector_state *connector_state;
5277         const struct drm_connector *connector;
5278         struct intel_encoder *encoder = NULL;
5279         int num_encoders = 0;
5280         int i;
5281
5282         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5283                 if (connector_state->crtc != &crtc->base)
5284                         continue;
5285
5286                 encoder = to_intel_encoder(connector_state->best_encoder);
5287                 num_encoders++;
5288         }
5289
5290         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5291              num_encoders, pipe_name(crtc->pipe));
5292
5293         return encoder;
5294 }
5295
5296 /*
5297  * Enable PCH resources required for PCH ports:
5298  *   - PCH PLLs
5299  *   - FDI training & RX/TX
5300  *   - update transcoder timings
5301  *   - DP transcoding bits
5302  *   - transcoder
5303  */
5304 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5305                                 const struct intel_crtc_state *crtc_state)
5306 {
5307         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5308         struct drm_device *dev = crtc->base.dev;
5309         struct drm_i915_private *dev_priv = to_i915(dev);
5310         enum pipe pipe = crtc->pipe;
5311         u32 temp;
5312
5313         assert_pch_transcoder_disabled(dev_priv, pipe);
5314
5315         if (IS_IVYBRIDGE(dev_priv))
5316                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5317
5318         /* Write the TU size bits before fdi link training, so that error
5319          * detection works. */
5320         I915_WRITE(FDI_RX_TUSIZE1(pipe),
5321                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5322
5323         /* For PCH output, training FDI link */
5324         dev_priv->display.fdi_link_train(crtc, crtc_state);
5325
5326         /* We need to program the right clock selection before writing the pixel
5327          * mutliplier into the DPLL. */
5328         if (HAS_PCH_CPT(dev_priv)) {
5329                 u32 sel;
5330
5331                 temp = I915_READ(PCH_DPLL_SEL);
5332                 temp |= TRANS_DPLL_ENABLE(pipe);
5333                 sel = TRANS_DPLLB_SEL(pipe);
5334                 if (crtc_state->shared_dpll ==
5335                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5336                         temp |= sel;
5337                 else
5338                         temp &= ~sel;
5339                 I915_WRITE(PCH_DPLL_SEL, temp);
5340         }
5341
5342         /* XXX: pch pll's can be enabled any time before we enable the PCH
5343          * transcoder, and we actually should do this to not upset any PCH
5344          * transcoder that already use the clock when we share it.
5345          *
5346          * Note that enable_shared_dpll tries to do the right thing, but
5347          * get_shared_dpll unconditionally resets the pll - we need that to have
5348          * the right LVDS enable sequence. */
5349         intel_enable_shared_dpll(crtc_state);
5350
5351         /* set transcoder timing, panel must allow it */
5352         assert_panel_unlocked(dev_priv, pipe);
5353         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5354
5355         intel_fdi_normal_train(crtc);
5356
5357         /* For PCH DP, enable TRANS_DP_CTL */
5358         if (HAS_PCH_CPT(dev_priv) &&
5359             intel_crtc_has_dp_encoder(crtc_state)) {
5360                 const struct drm_display_mode *adjusted_mode =
5361                         &crtc_state->base.adjusted_mode;
5362                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5363                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5364                 enum port port;
5365
5366                 temp = I915_READ(reg);
5367                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5368                           TRANS_DP_SYNC_MASK |
5369                           TRANS_DP_BPC_MASK);
5370                 temp |= TRANS_DP_OUTPUT_ENABLE;
5371                 temp |= bpc << 9; /* same format but at 11:9 */
5372
5373                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5374                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5375                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5376                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5377
5378                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5379                 WARN_ON(port < PORT_B || port > PORT_D);
5380                 temp |= TRANS_DP_PORT_SEL(port);
5381
5382                 I915_WRITE(reg, temp);
5383         }
5384
5385         ironlake_enable_pch_transcoder(crtc_state);
5386 }
5387
5388 static void lpt_pch_enable(const struct intel_atomic_state *state,
5389                            const struct intel_crtc_state *crtc_state)
5390 {
5391         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5392         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5393         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5394
5395         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5396
5397         lpt_program_iclkip(crtc_state);
5398
5399         /* Set transcoder timing. */
5400         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5401
5402         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5403 }
5404
5405 static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
5406 {
5407         struct drm_i915_private *dev_priv = to_i915(dev);
5408         i915_reg_t dslreg = PIPEDSL(pipe);
5409         u32 temp;
5410
5411         temp = I915_READ(dslreg);
5412         udelay(500);
5413         if (wait_for(I915_READ(dslreg) != temp, 5)) {
5414                 if (wait_for(I915_READ(dslreg) != temp, 5))
5415                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5416         }
5417 }
5418
5419 /*
5420  * The hardware phase 0.0 refers to the center of the pixel.
5421  * We want to start from the top/left edge which is phase
5422  * -0.5. That matches how the hardware calculates the scaling
5423  * factors (from top-left of the first pixel to bottom-right
5424  * of the last pixel, as opposed to the pixel centers).
5425  *
5426  * For 4:2:0 subsampled chroma planes we obviously have to
5427  * adjust that so that the chroma sample position lands in
5428  * the right spot.
5429  *
5430  * Note that for packed YCbCr 4:2:2 formats there is no way to
5431  * control chroma siting. The hardware simply replicates the
5432  * chroma samples for both of the luma samples, and thus we don't
5433  * actually get the expected MPEG2 chroma siting convention :(
5434  * The same behaviour is observed on pre-SKL platforms as well.
5435  *
5436  * Theory behind the formula (note that we ignore sub-pixel
5437  * source coordinates):
5438  * s = source sample position
5439  * d = destination sample position
5440  *
5441  * Downscaling 4:1:
5442  * -0.5
5443  * | 0.0
5444  * | |     1.5 (initial phase)
5445  * | |     |
5446  * v v     v
5447  * | s | s | s | s |
5448  * |       d       |
5449  *
5450  * Upscaling 1:4:
5451  * -0.5
5452  * | -0.375 (initial phase)
5453  * | |     0.0
5454  * | |     |
5455  * v v     v
5456  * |       s       |
5457  * | d | d | d | d |
5458  */
5459 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5460 {
5461         int phase = -0x8000;
5462         u16 trip = 0;
5463
5464         if (chroma_cosited)
5465                 phase += (sub - 1) * 0x8000 / sub;
5466
5467         phase += scale / (2 * sub);
5468
5469         /*
5470          * Hardware initial phase limited to [-0.5:1.5].
5471          * Since the max hardware scale factor is 3.0, we
5472          * should never actually excdeed 1.0 here.
5473          */
5474         WARN_ON(phase < -0x8000 || phase > 0x18000);
5475
5476         if (phase < 0)
5477                 phase = 0x10000 + phase;
5478         else
5479                 trip = PS_PHASE_TRIP;
5480
5481         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5482 }
5483
5484 #define SKL_MIN_SRC_W 8
5485 #define SKL_MAX_SRC_W 4096
5486 #define SKL_MIN_SRC_H 8
5487 #define SKL_MAX_SRC_H 4096
5488 #define SKL_MIN_DST_W 8
5489 #define SKL_MAX_DST_W 4096
5490 #define SKL_MIN_DST_H 8
5491 #define SKL_MAX_DST_H 4096
5492 #define ICL_MAX_SRC_W 5120
5493 #define ICL_MAX_SRC_H 4096
5494 #define ICL_MAX_DST_W 5120
5495 #define ICL_MAX_DST_H 4096
5496 #define SKL_MIN_YUV_420_SRC_W 16
5497 #define SKL_MIN_YUV_420_SRC_H 16
5498
5499 static int
5500 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5501                   unsigned int scaler_user, int *scaler_id,
5502                   int src_w, int src_h, int dst_w, int dst_h,
5503                   const struct drm_format_info *format, bool need_scaler)
5504 {
5505         struct intel_crtc_scaler_state *scaler_state =
5506                 &crtc_state->scaler_state;
5507         struct intel_crtc *intel_crtc =
5508                 to_intel_crtc(crtc_state->base.crtc);
5509         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5510         const struct drm_display_mode *adjusted_mode =
5511                 &crtc_state->base.adjusted_mode;
5512
5513         /*
5514          * Src coordinates are already rotated by 270 degrees for
5515          * the 90/270 degree plane rotation cases (to match the
5516          * GTT mapping), hence no need to account for rotation here.
5517          */
5518         if (src_w != dst_w || src_h != dst_h)
5519                 need_scaler = true;
5520
5521         /*
5522          * Scaling/fitting not supported in IF-ID mode in GEN9+
5523          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5524          * Once NV12 is enabled, handle it here while allocating scaler
5525          * for NV12.
5526          */
5527         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
5528             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5529                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5530                 return -EINVAL;
5531         }
5532
5533         /*
5534          * if plane is being disabled or scaler is no more required or force detach
5535          *  - free scaler binded to this plane/crtc
5536          *  - in order to do this, update crtc->scaler_usage
5537          *
5538          * Here scaler state in crtc_state is set free so that
5539          * scaler can be assigned to other user. Actual register
5540          * update to free the scaler is done in plane/panel-fit programming.
5541          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5542          */
5543         if (force_detach || !need_scaler) {
5544                 if (*scaler_id >= 0) {
5545                         scaler_state->scaler_users &= ~(1 << scaler_user);
5546                         scaler_state->scalers[*scaler_id].in_use = 0;
5547
5548                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5549                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5550                                 intel_crtc->pipe, scaler_user, *scaler_id,
5551                                 scaler_state->scaler_users);
5552                         *scaler_id = -1;
5553                 }
5554                 return 0;
5555         }
5556
5557         if (format && drm_format_info_is_yuv_semiplanar(format) &&
5558             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5559                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5560                 return -EINVAL;
5561         }
5562
5563         /* range checks */
5564         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5565             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5566             (INTEL_GEN(dev_priv) >= 11 &&
5567              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5568               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5569             (INTEL_GEN(dev_priv) < 11 &&
5570              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5571               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5572                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5573                         "size is out of scaler range\n",
5574                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5575                 return -EINVAL;
5576         }
5577
5578         /* mark this plane as a scaler user in crtc_state */
5579         scaler_state->scaler_users |= (1 << scaler_user);
5580         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5581                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5582                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5583                 scaler_state->scaler_users);
5584
5585         return 0;
5586 }
5587
5588 /**
5589  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5590  *
5591  * @state: crtc's scaler state
5592  *
5593  * Return
5594  *     0 - scaler_usage updated successfully
5595  *    error - requested scaling cannot be supported or other error condition
5596  */
5597 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5598 {
5599         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5600         bool need_scaler = false;
5601
5602         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5603                 need_scaler = true;
5604
5605         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
5606                                  &state->scaler_state.scaler_id,
5607                                  state->pipe_src_w, state->pipe_src_h,
5608                                  adjusted_mode->crtc_hdisplay,
5609                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5610 }
5611
5612 /**
5613  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5614  * @crtc_state: crtc's scaler state
5615  * @plane_state: atomic plane state to update
5616  *
5617  * Return
5618  *     0 - scaler_usage updated successfully
5619  *    error - requested scaling cannot be supported or other error condition
5620  */
5621 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5622                                    struct intel_plane_state *plane_state)
5623 {
5624         struct intel_plane *intel_plane =
5625                 to_intel_plane(plane_state->base.plane);
5626         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5627         struct drm_framebuffer *fb = plane_state->base.fb;
5628         int ret;
5629         bool force_detach = !fb || !plane_state->base.visible;
5630         bool need_scaler = false;
5631
5632         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5633         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5634             fb && drm_format_info_is_yuv_semiplanar(fb->format))
5635                 need_scaler = true;
5636
5637         ret = skl_update_scaler(crtc_state, force_detach,
5638                                 drm_plane_index(&intel_plane->base),
5639                                 &plane_state->scaler_id,
5640                                 drm_rect_width(&plane_state->base.src) >> 16,
5641                                 drm_rect_height(&plane_state->base.src) >> 16,
5642                                 drm_rect_width(&plane_state->base.dst),
5643                                 drm_rect_height(&plane_state->base.dst),
5644                                 fb ? fb->format : NULL, need_scaler);
5645
5646         if (ret || plane_state->scaler_id < 0)
5647                 return ret;
5648
5649         /* check colorkey */
5650         if (plane_state->ckey.flags) {
5651                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5652                               intel_plane->base.base.id,
5653                               intel_plane->base.name);
5654                 return -EINVAL;
5655         }
5656
5657         /* Check src format */
5658         switch (fb->format->format) {
5659         case DRM_FORMAT_RGB565:
5660         case DRM_FORMAT_XBGR8888:
5661         case DRM_FORMAT_XRGB8888:
5662         case DRM_FORMAT_ABGR8888:
5663         case DRM_FORMAT_ARGB8888:
5664         case DRM_FORMAT_XRGB2101010:
5665         case DRM_FORMAT_XBGR2101010:
5666         case DRM_FORMAT_YUYV:
5667         case DRM_FORMAT_YVYU:
5668         case DRM_FORMAT_UYVY:
5669         case DRM_FORMAT_VYUY:
5670         case DRM_FORMAT_NV12:
5671         case DRM_FORMAT_P010:
5672         case DRM_FORMAT_P012:
5673         case DRM_FORMAT_P016:
5674         case DRM_FORMAT_Y210:
5675         case DRM_FORMAT_Y212:
5676         case DRM_FORMAT_Y216:
5677         case DRM_FORMAT_XVYU2101010:
5678         case DRM_FORMAT_XVYU12_16161616:
5679         case DRM_FORMAT_XVYU16161616:
5680                 break;
5681         case DRM_FORMAT_XBGR16161616F:
5682         case DRM_FORMAT_ABGR16161616F:
5683         case DRM_FORMAT_XRGB16161616F:
5684         case DRM_FORMAT_ARGB16161616F:
5685                 if (INTEL_GEN(dev_priv) >= 11)
5686                         break;
5687                 /* fall through */
5688         default:
5689                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5690                               intel_plane->base.base.id, intel_plane->base.name,
5691                               fb->base.id, fb->format->format);
5692                 return -EINVAL;
5693         }
5694
5695         return 0;
5696 }
5697
5698 static void skylake_scaler_disable(struct intel_crtc *crtc)
5699 {
5700         int i;
5701
5702         for (i = 0; i < crtc->num_scalers; i++)
5703                 skl_detach_scaler(crtc, i);
5704 }
5705
5706 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5707 {
5708         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5709         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5710         enum pipe pipe = crtc->pipe;
5711         const struct intel_crtc_scaler_state *scaler_state =
5712                 &crtc_state->scaler_state;
5713
5714         if (crtc_state->pch_pfit.enabled) {
5715                 u16 uv_rgb_hphase, uv_rgb_vphase;
5716                 int pfit_w, pfit_h, hscale, vscale;
5717                 int id;
5718
5719                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5720                         return;
5721
5722                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5723                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5724
5725                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5726                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5727
5728                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5729                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5730
5731                 id = scaler_state->scaler_id;
5732                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5733                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5734                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5735                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5736                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5737                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5738                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5739                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5740         }
5741 }
5742
5743 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5744 {
5745         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5746         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5747         enum pipe pipe = crtc->pipe;
5748
5749         if (crtc_state->pch_pfit.enabled) {
5750                 /* Force use of hard-coded filter coefficients
5751                  * as some pre-programmed values are broken,
5752                  * e.g. x201.
5753                  */
5754                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5755                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5756                                                  PF_PIPE_SEL_IVB(pipe));
5757                 else
5758                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5759                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5760                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5761         }
5762 }
5763
5764 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5765 {
5766         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5767         struct drm_device *dev = crtc->base.dev;
5768         struct drm_i915_private *dev_priv = to_i915(dev);
5769
5770         if (!crtc_state->ips_enabled)
5771                 return;
5772
5773         /*
5774          * We can only enable IPS after we enable a plane and wait for a vblank
5775          * This function is called from post_plane_update, which is run after
5776          * a vblank wait.
5777          */
5778         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5779
5780         if (IS_BROADWELL(dev_priv)) {
5781                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5782                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5783                 /* Quoting Art Runyan: "its not safe to expect any particular
5784                  * value in IPS_CTL bit 31 after enabling IPS through the
5785                  * mailbox." Moreover, the mailbox may return a bogus state,
5786                  * so we need to just enable it and continue on.
5787                  */
5788         } else {
5789                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5790                 /* The bit only becomes 1 in the next vblank, so this wait here
5791                  * is essentially intel_wait_for_vblank. If we don't have this
5792                  * and don't wait for vblanks until the end of crtc_enable, then
5793                  * the HW state readout code will complain that the expected
5794                  * IPS_CTL value is not the one we read. */
5795                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5796                         DRM_ERROR("Timed out waiting for IPS enable\n");
5797         }
5798 }
5799
5800 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5801 {
5802         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5803         struct drm_device *dev = crtc->base.dev;
5804         struct drm_i915_private *dev_priv = to_i915(dev);
5805
5806         if (!crtc_state->ips_enabled)
5807                 return;
5808
5809         if (IS_BROADWELL(dev_priv)) {
5810                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5811                 /*
5812                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5813                  * 42ms timeout value leads to occasional timeouts so use 100ms
5814                  * instead.
5815                  */
5816                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5817                         DRM_ERROR("Timed out waiting for IPS disable\n");
5818         } else {
5819                 I915_WRITE(IPS_CTL, 0);
5820                 POSTING_READ(IPS_CTL);
5821         }
5822
5823         /* We need to wait for a vblank before we can disable the plane. */
5824         intel_wait_for_vblank(dev_priv, crtc->pipe);
5825 }
5826
5827 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5828 {
5829         if (intel_crtc->overlay)
5830                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5831
5832         /* Let userspace switch the overlay on again. In most cases userspace
5833          * has to recompute where to put it anyway.
5834          */
5835 }
5836
5837 /**
5838  * intel_post_enable_primary - Perform operations after enabling primary plane
5839  * @crtc: the CRTC whose primary plane was just enabled
5840  * @new_crtc_state: the enabling state
5841  *
5842  * Performs potentially sleeping operations that must be done after the primary
5843  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5844  * called due to an explicit primary plane update, or due to an implicit
5845  * re-enable that is caused when a sprite plane is updated to no longer
5846  * completely hide the primary plane.
5847  */
5848 static void
5849 intel_post_enable_primary(struct drm_crtc *crtc,
5850                           const struct intel_crtc_state *new_crtc_state)
5851 {
5852         struct drm_device *dev = crtc->dev;
5853         struct drm_i915_private *dev_priv = to_i915(dev);
5854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5855         enum pipe pipe = intel_crtc->pipe;
5856
5857         /*
5858          * Gen2 reports pipe underruns whenever all planes are disabled.
5859          * So don't enable underrun reporting before at least some planes
5860          * are enabled.
5861          * FIXME: Need to fix the logic to work when we turn off all planes
5862          * but leave the pipe running.
5863          */
5864         if (IS_GEN(dev_priv, 2))
5865                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5866
5867         /* Underruns don't always raise interrupts, so check manually. */
5868         intel_check_cpu_fifo_underruns(dev_priv);
5869         intel_check_pch_fifo_underruns(dev_priv);
5870 }
5871
5872 /* FIXME get rid of this and use pre_plane_update */
5873 static void
5874 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5875 {
5876         struct drm_device *dev = crtc->dev;
5877         struct drm_i915_private *dev_priv = to_i915(dev);
5878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5879         enum pipe pipe = intel_crtc->pipe;
5880
5881         /*
5882          * Gen2 reports pipe underruns whenever all planes are disabled.
5883          * So disable underrun reporting before all the planes get disabled.
5884          */
5885         if (IS_GEN(dev_priv, 2))
5886                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5887
5888         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5889
5890         /*
5891          * Vblank time updates from the shadow to live plane control register
5892          * are blocked if the memory self-refresh mode is active at that
5893          * moment. So to make sure the plane gets truly disabled, disable
5894          * first the self-refresh mode. The self-refresh enable bit in turn
5895          * will be checked/applied by the HW only at the next frame start
5896          * event which is after the vblank start event, so we need to have a
5897          * wait-for-vblank between disabling the plane and the pipe.
5898          */
5899         if (HAS_GMCH(dev_priv) &&
5900             intel_set_memory_cxsr(dev_priv, false))
5901                 intel_wait_for_vblank(dev_priv, pipe);
5902 }
5903
5904 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5905                                        const struct intel_crtc_state *new_crtc_state)
5906 {
5907         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5908         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5909
5910         if (!old_crtc_state->ips_enabled)
5911                 return false;
5912
5913         if (needs_modeset(new_crtc_state))
5914                 return true;
5915
5916         /*
5917          * Workaround : Do not read or write the pipe palette/gamma data while
5918          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5919          *
5920          * Disable IPS before we program the LUT.
5921          */
5922         if (IS_HASWELL(dev_priv) &&
5923             (new_crtc_state->base.color_mgmt_changed ||
5924              new_crtc_state->update_pipe) &&
5925             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5926                 return true;
5927
5928         return !new_crtc_state->ips_enabled;
5929 }
5930
5931 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5932                                        const struct intel_crtc_state *new_crtc_state)
5933 {
5934         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5935         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5936
5937         if (!new_crtc_state->ips_enabled)
5938                 return false;
5939
5940         if (needs_modeset(new_crtc_state))
5941                 return true;
5942
5943         /*
5944          * Workaround : Do not read or write the pipe palette/gamma data while
5945          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5946          *
5947          * Re-enable IPS after the LUT has been programmed.
5948          */
5949         if (IS_HASWELL(dev_priv) &&
5950             (new_crtc_state->base.color_mgmt_changed ||
5951              new_crtc_state->update_pipe) &&
5952             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5953                 return true;
5954
5955         /*
5956          * We can't read out IPS on broadwell, assume the worst and
5957          * forcibly enable IPS on the first fastset.
5958          */
5959         if (new_crtc_state->update_pipe &&
5960             old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5961                 return true;
5962
5963         return !old_crtc_state->ips_enabled;
5964 }
5965
5966 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5967                           const struct intel_crtc_state *crtc_state)
5968 {
5969         if (!crtc_state->nv12_planes)
5970                 return false;
5971
5972         /* WA Display #0827: Gen9:all */
5973         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5974                 return true;
5975
5976         return false;
5977 }
5978
5979 static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
5980                                const struct intel_crtc_state *crtc_state)
5981 {
5982         /* Wa_2006604312:icl */
5983         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
5984                 return true;
5985
5986         return false;
5987 }
5988
5989 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5990 {
5991         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5992         struct drm_device *dev = crtc->base.dev;
5993         struct drm_i915_private *dev_priv = to_i915(dev);
5994         struct drm_atomic_state *state = old_crtc_state->base.state;
5995         struct intel_crtc_state *pipe_config =
5996                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
5997                                                 crtc);
5998         struct drm_plane *primary = crtc->base.primary;
5999         struct drm_plane_state *old_primary_state =
6000                 drm_atomic_get_old_plane_state(state, primary);
6001
6002         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
6003
6004         if (pipe_config->update_wm_post && pipe_config->base.active)
6005                 intel_update_watermarks(crtc);
6006
6007         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
6008                 hsw_enable_ips(pipe_config);
6009
6010         if (old_primary_state) {
6011                 struct drm_plane_state *new_primary_state =
6012                         drm_atomic_get_new_plane_state(state, primary);
6013
6014                 intel_fbc_post_update(crtc);
6015
6016                 if (new_primary_state->visible &&
6017                     (needs_modeset(pipe_config) ||
6018                      !old_primary_state->visible))
6019                         intel_post_enable_primary(&crtc->base, pipe_config);
6020         }
6021
6022         if (needs_nv12_wa(dev_priv, old_crtc_state) &&
6023             !needs_nv12_wa(dev_priv, pipe_config))
6024                 skl_wa_827(dev_priv, crtc->pipe, false);
6025
6026         if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6027             !needs_scalerclk_wa(dev_priv, pipe_config))
6028                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
6029 }
6030
6031 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
6032                                    struct intel_crtc_state *pipe_config)
6033 {
6034         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6035         struct drm_device *dev = crtc->base.dev;
6036         struct drm_i915_private *dev_priv = to_i915(dev);
6037         struct drm_atomic_state *state = old_crtc_state->base.state;
6038         struct drm_plane *primary = crtc->base.primary;
6039         struct drm_plane_state *old_primary_state =
6040                 drm_atomic_get_old_plane_state(state, primary);
6041         bool modeset = needs_modeset(pipe_config);
6042         struct intel_atomic_state *intel_state =
6043                 to_intel_atomic_state(state);
6044
6045         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
6046                 hsw_disable_ips(old_crtc_state);
6047
6048         if (old_primary_state) {
6049                 struct intel_plane_state *new_primary_state =
6050                         intel_atomic_get_new_plane_state(intel_state,
6051                                                          to_intel_plane(primary));
6052
6053                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
6054                 /*
6055                  * Gen2 reports pipe underruns whenever all planes are disabled.
6056                  * So disable underrun reporting before all the planes get disabled.
6057                  */
6058                 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
6059                     (modeset || !new_primary_state->base.visible))
6060                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6061         }
6062
6063         /* Display WA 827 */
6064         if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
6065             needs_nv12_wa(dev_priv, pipe_config))
6066                 skl_wa_827(dev_priv, crtc->pipe, true);
6067
6068         /* Wa_2006604312:icl */
6069         if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
6070             needs_scalerclk_wa(dev_priv, pipe_config))
6071                 icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
6072
6073         /*
6074          * Vblank time updates from the shadow to live plane control register
6075          * are blocked if the memory self-refresh mode is active at that
6076          * moment. So to make sure the plane gets truly disabled, disable
6077          * first the self-refresh mode. The self-refresh enable bit in turn
6078          * will be checked/applied by the HW only at the next frame start
6079          * event which is after the vblank start event, so we need to have a
6080          * wait-for-vblank between disabling the plane and the pipe.
6081          */
6082         if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
6083             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6084                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6085
6086         /*
6087          * IVB workaround: must disable low power watermarks for at least
6088          * one frame before enabling scaling.  LP watermarks can be re-enabled
6089          * when scaling is disabled.
6090          *
6091          * WaCxSRDisabledForSpriteScaling:ivb
6092          */
6093         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
6094             old_crtc_state->base.active)
6095                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6096
6097         /*
6098          * If we're doing a modeset, we're done.  No need to do any pre-vblank
6099          * watermark programming here.
6100          */
6101         if (needs_modeset(pipe_config))
6102                 return;
6103
6104         /*
6105          * For platforms that support atomic watermarks, program the
6106          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6107          * will be the intermediate values that are safe for both pre- and
6108          * post- vblank; when vblank happens, the 'active' values will be set
6109          * to the final 'target' values and we'll do this again to get the
6110          * optimal watermarks.  For gen9+ platforms, the values we program here
6111          * will be the final target values which will get automatically latched
6112          * at vblank time; no further programming will be necessary.
6113          *
6114          * If a platform hasn't been transitioned to atomic watermarks yet,
6115          * we'll continue to update watermarks the old way, if flags tell
6116          * us to.
6117          */
6118         if (dev_priv->display.initial_watermarks != NULL)
6119                 dev_priv->display.initial_watermarks(intel_state,
6120                                                      pipe_config);
6121         else if (pipe_config->update_wm_pre)
6122                 intel_update_watermarks(crtc);
6123 }
6124
6125 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6126                                       struct intel_crtc *crtc)
6127 {
6128         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6129         const struct intel_crtc_state *new_crtc_state =
6130                 intel_atomic_get_new_crtc_state(state, crtc);
6131         unsigned int update_mask = new_crtc_state->update_planes;
6132         const struct intel_plane_state *old_plane_state;
6133         struct intel_plane *plane;
6134         unsigned fb_bits = 0;
6135         int i;
6136
6137         intel_crtc_dpms_overlay_disable(crtc);
6138
6139         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6140                 if (crtc->pipe != plane->pipe ||
6141                     !(update_mask & BIT(plane->id)))
6142                         continue;
6143
6144                 intel_disable_plane(plane, new_crtc_state);
6145
6146                 if (old_plane_state->base.visible)
6147                         fb_bits |= plane->frontbuffer_bit;
6148         }
6149
6150         intel_frontbuffer_flip(dev_priv, fb_bits);
6151 }
6152
6153 /*
6154  * intel_connector_primary_encoder - get the primary encoder for a connector
6155  * @connector: connector for which to return the encoder
6156  *
6157  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6158  * all connectors to their encoder, except for DP-MST connectors which have
6159  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6160  * pointed to by as many DP-MST connectors as there are pipes.
6161  */
6162 static struct intel_encoder *
6163 intel_connector_primary_encoder(struct intel_connector *connector)
6164 {
6165         struct intel_encoder *encoder;
6166
6167         if (connector->mst_port)
6168                 return &dp_to_dig_port(connector->mst_port)->base;
6169
6170         encoder = intel_attached_encoder(&connector->base);
6171         WARN_ON(!encoder);
6172
6173         return encoder;
6174 }
6175
6176 static bool
6177 intel_connector_needs_modeset(struct intel_atomic_state *state,
6178                               const struct drm_connector_state *old_conn_state,
6179                               const struct drm_connector_state *new_conn_state)
6180 {
6181         struct intel_crtc *old_crtc = old_conn_state->crtc ?
6182                                       to_intel_crtc(old_conn_state->crtc) : NULL;
6183         struct intel_crtc *new_crtc = new_conn_state->crtc ?
6184                                       to_intel_crtc(new_conn_state->crtc) : NULL;
6185
6186         return new_crtc != old_crtc ||
6187                (new_crtc &&
6188                 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6189 }
6190
6191 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6192 {
6193         struct drm_connector_state *old_conn_state;
6194         struct drm_connector_state *new_conn_state;
6195         struct drm_connector *conn;
6196         int i;
6197
6198         for_each_oldnew_connector_in_state(&state->base, conn,
6199                                            old_conn_state, new_conn_state, i) {
6200                 struct intel_encoder *encoder;
6201                 struct intel_crtc *crtc;
6202
6203                 if (!intel_connector_needs_modeset(state,
6204                                                    old_conn_state,
6205                                                    new_conn_state))
6206                         continue;
6207
6208                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6209                 if (!encoder->update_prepare)
6210                         continue;
6211
6212                 crtc = new_conn_state->crtc ?
6213                         to_intel_crtc(new_conn_state->crtc) : NULL;
6214                 encoder->update_prepare(state, encoder, crtc);
6215         }
6216 }
6217
6218 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6219 {
6220         struct drm_connector_state *old_conn_state;
6221         struct drm_connector_state *new_conn_state;
6222         struct drm_connector *conn;
6223         int i;
6224
6225         for_each_oldnew_connector_in_state(&state->base, conn,
6226                                            old_conn_state, new_conn_state, i) {
6227                 struct intel_encoder *encoder;
6228                 struct intel_crtc *crtc;
6229
6230                 if (!intel_connector_needs_modeset(state,
6231                                                    old_conn_state,
6232                                                    new_conn_state))
6233                         continue;
6234
6235                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6236                 if (!encoder->update_complete)
6237                         continue;
6238
6239                 crtc = new_conn_state->crtc ?
6240                         to_intel_crtc(new_conn_state->crtc) : NULL;
6241                 encoder->update_complete(state, encoder, crtc);
6242         }
6243 }
6244
6245 static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
6246                                           struct intel_crtc_state *crtc_state,
6247                                           struct intel_atomic_state *state)
6248 {
6249         struct drm_connector_state *conn_state;
6250         struct drm_connector *conn;
6251         int i;
6252
6253         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6254                 struct intel_encoder *encoder =
6255                         to_intel_encoder(conn_state->best_encoder);
6256
6257                 if (conn_state->crtc != &crtc->base)
6258                         continue;
6259
6260                 if (encoder->pre_pll_enable)
6261                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6262         }
6263 }
6264
6265 static void intel_encoders_pre_enable(struct intel_crtc *crtc,
6266                                       struct intel_crtc_state *crtc_state,
6267                                       struct intel_atomic_state *state)
6268 {
6269         struct drm_connector_state *conn_state;
6270         struct drm_connector *conn;
6271         int i;
6272
6273         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6274                 struct intel_encoder *encoder =
6275                         to_intel_encoder(conn_state->best_encoder);
6276
6277                 if (conn_state->crtc != &crtc->base)
6278                         continue;
6279
6280                 if (encoder->pre_enable)
6281                         encoder->pre_enable(encoder, crtc_state, conn_state);
6282         }
6283 }
6284
6285 static void intel_encoders_enable(struct intel_crtc *crtc,
6286                                   struct intel_crtc_state *crtc_state,
6287                                   struct intel_atomic_state *state)
6288 {
6289         struct drm_connector_state *conn_state;
6290         struct drm_connector *conn;
6291         int i;
6292
6293         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6294                 struct intel_encoder *encoder =
6295                         to_intel_encoder(conn_state->best_encoder);
6296
6297                 if (conn_state->crtc != &crtc->base)
6298                         continue;
6299
6300                 if (encoder->enable)
6301                         encoder->enable(encoder, crtc_state, conn_state);
6302                 intel_opregion_notify_encoder(encoder, true);
6303         }
6304 }
6305
6306 static void intel_encoders_disable(struct intel_crtc *crtc,
6307                                    struct intel_crtc_state *old_crtc_state,
6308                                    struct intel_atomic_state *state)
6309 {
6310         struct drm_connector_state *old_conn_state;
6311         struct drm_connector *conn;
6312         int i;
6313
6314         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6315                 struct intel_encoder *encoder =
6316                         to_intel_encoder(old_conn_state->best_encoder);
6317
6318                 if (old_conn_state->crtc != &crtc->base)
6319                         continue;
6320
6321                 intel_opregion_notify_encoder(encoder, false);
6322                 if (encoder->disable)
6323                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6324         }
6325 }
6326
6327 static void intel_encoders_post_disable(struct intel_crtc *crtc,
6328                                         struct intel_crtc_state *old_crtc_state,
6329                                         struct intel_atomic_state *state)
6330 {
6331         struct drm_connector_state *old_conn_state;
6332         struct drm_connector *conn;
6333         int i;
6334
6335         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6336                 struct intel_encoder *encoder =
6337                         to_intel_encoder(old_conn_state->best_encoder);
6338
6339                 if (old_conn_state->crtc != &crtc->base)
6340                         continue;
6341
6342                 if (encoder->post_disable)
6343                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6344         }
6345 }
6346
6347 static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
6348                                             struct intel_crtc_state *old_crtc_state,
6349                                             struct intel_atomic_state *state)
6350 {
6351         struct drm_connector_state *old_conn_state;
6352         struct drm_connector *conn;
6353         int i;
6354
6355         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6356                 struct intel_encoder *encoder =
6357                         to_intel_encoder(old_conn_state->best_encoder);
6358
6359                 if (old_conn_state->crtc != &crtc->base)
6360                         continue;
6361
6362                 if (encoder->post_pll_disable)
6363                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6364         }
6365 }
6366
6367 static void intel_encoders_update_pipe(struct intel_crtc *crtc,
6368                                        struct intel_crtc_state *crtc_state,
6369                                        struct intel_atomic_state *state)
6370 {
6371         struct drm_connector_state *conn_state;
6372         struct drm_connector *conn;
6373         int i;
6374
6375         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6376                 struct intel_encoder *encoder =
6377                         to_intel_encoder(conn_state->best_encoder);
6378
6379                 if (conn_state->crtc != &crtc->base)
6380                         continue;
6381
6382                 if (encoder->update_pipe)
6383                         encoder->update_pipe(encoder, crtc_state, conn_state);
6384         }
6385 }
6386
6387 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6388 {
6389         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6390         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6391
6392         plane->disable_plane(plane, crtc_state);
6393 }
6394
6395 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
6396                                  struct intel_atomic_state *state)
6397 {
6398         struct drm_crtc *crtc = pipe_config->base.crtc;
6399         struct drm_device *dev = crtc->dev;
6400         struct drm_i915_private *dev_priv = to_i915(dev);
6401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402         enum pipe pipe = intel_crtc->pipe;
6403
6404         if (WARN_ON(intel_crtc->active))
6405                 return;
6406
6407         /*
6408          * Sometimes spurious CPU pipe underruns happen during FDI
6409          * training, at least with VGA+HDMI cloning. Suppress them.
6410          *
6411          * On ILK we get an occasional spurious CPU pipe underruns
6412          * between eDP port A enable and vdd enable. Also PCH port
6413          * enable seems to result in the occasional CPU pipe underrun.
6414          *
6415          * Spurious PCH underruns also occur during PCH enabling.
6416          */
6417         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6418         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6419
6420         if (pipe_config->has_pch_encoder)
6421                 intel_prepare_shared_dpll(pipe_config);
6422
6423         if (intel_crtc_has_dp_encoder(pipe_config))
6424                 intel_dp_set_m_n(pipe_config, M1_N1);
6425
6426         intel_set_pipe_timings(pipe_config);
6427         intel_set_pipe_src_size(pipe_config);
6428
6429         if (pipe_config->has_pch_encoder) {
6430                 intel_cpu_transcoder_set_m_n(pipe_config,
6431                                              &pipe_config->fdi_m_n, NULL);
6432         }
6433
6434         ironlake_set_pipeconf(pipe_config);
6435
6436         intel_crtc->active = true;
6437
6438         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6439
6440         if (pipe_config->has_pch_encoder) {
6441                 /* Note: FDI PLL enabling _must_ be done before we enable the
6442                  * cpu pipes, hence this is separate from all the other fdi/pch
6443                  * enabling. */
6444                 ironlake_fdi_pll_enable(pipe_config);
6445         } else {
6446                 assert_fdi_tx_disabled(dev_priv, pipe);
6447                 assert_fdi_rx_disabled(dev_priv, pipe);
6448         }
6449
6450         ironlake_pfit_enable(pipe_config);
6451
6452         /*
6453          * On ILK+ LUT must be loaded before the pipe is running but with
6454          * clocks enabled
6455          */
6456         intel_color_load_luts(pipe_config);
6457         intel_color_commit(pipe_config);
6458         /* update DSPCNTR to configure gamma for pipe bottom color */
6459         intel_disable_primary_plane(pipe_config);
6460
6461         if (dev_priv->display.initial_watermarks != NULL)
6462                 dev_priv->display.initial_watermarks(state, pipe_config);
6463         intel_enable_pipe(pipe_config);
6464
6465         if (pipe_config->has_pch_encoder)
6466                 ironlake_pch_enable(state, pipe_config);
6467
6468         assert_vblank_disabled(crtc);
6469         intel_crtc_vblank_on(pipe_config);
6470
6471         intel_encoders_enable(intel_crtc, pipe_config, state);
6472
6473         if (HAS_PCH_CPT(dev_priv))
6474                 cpt_verify_modeset(dev, intel_crtc->pipe);
6475
6476         /*
6477          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6478          * And a second vblank wait is needed at least on ILK with
6479          * some interlaced HDMI modes. Let's do the double wait always
6480          * in case there are more corner cases we don't know about.
6481          */
6482         if (pipe_config->has_pch_encoder) {
6483                 intel_wait_for_vblank(dev_priv, pipe);
6484                 intel_wait_for_vblank(dev_priv, pipe);
6485         }
6486         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6487         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6488 }
6489
6490 /* IPS only exists on ULT machines and is tied to pipe A. */
6491 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6492 {
6493         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6494 }
6495
6496 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6497                                             enum pipe pipe, bool apply)
6498 {
6499         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6500         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6501
6502         if (apply)
6503                 val |= mask;
6504         else
6505                 val &= ~mask;
6506
6507         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6508 }
6509
6510 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6511 {
6512         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6513         enum pipe pipe = crtc->pipe;
6514         u32 val;
6515
6516         val = MBUS_DBOX_A_CREDIT(2);
6517
6518         if (INTEL_GEN(dev_priv) >= 12) {
6519                 val |= MBUS_DBOX_BW_CREDIT(2);
6520                 val |= MBUS_DBOX_B_CREDIT(12);
6521         } else {
6522                 val |= MBUS_DBOX_BW_CREDIT(1);
6523                 val |= MBUS_DBOX_B_CREDIT(8);
6524         }
6525
6526         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6527 }
6528
6529 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
6530                                 struct intel_atomic_state *state)
6531 {
6532         struct drm_crtc *crtc = pipe_config->base.crtc;
6533         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6535         enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
6536         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6537         bool psl_clkgate_wa;
6538
6539         if (WARN_ON(intel_crtc->active))
6540                 return;
6541
6542         intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6543
6544         if (pipe_config->shared_dpll)
6545                 intel_enable_shared_dpll(pipe_config);
6546
6547         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6548
6549         if (intel_crtc_has_dp_encoder(pipe_config))
6550                 intel_dp_set_m_n(pipe_config, M1_N1);
6551
6552         if (!transcoder_is_dsi(cpu_transcoder))
6553                 intel_set_pipe_timings(pipe_config);
6554
6555         if (INTEL_GEN(dev_priv) >= 11)
6556                 icl_enable_trans_port_sync(pipe_config);
6557
6558         intel_set_pipe_src_size(pipe_config);
6559
6560         if (cpu_transcoder != TRANSCODER_EDP &&
6561             !transcoder_is_dsi(cpu_transcoder)) {
6562                 I915_WRITE(PIPE_MULT(cpu_transcoder),
6563                            pipe_config->pixel_multiplier - 1);
6564         }
6565
6566         if (pipe_config->has_pch_encoder) {
6567                 intel_cpu_transcoder_set_m_n(pipe_config,
6568                                              &pipe_config->fdi_m_n, NULL);
6569         }
6570
6571         if (!transcoder_is_dsi(cpu_transcoder))
6572                 haswell_set_pipeconf(pipe_config);
6573
6574         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6575                 bdw_set_pipemisc(pipe_config);
6576
6577         intel_crtc->active = true;
6578
6579         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6580         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6581                          pipe_config->pch_pfit.enabled;
6582         if (psl_clkgate_wa)
6583                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6584
6585         if (INTEL_GEN(dev_priv) >= 9)
6586                 skylake_pfit_enable(pipe_config);
6587         else
6588                 ironlake_pfit_enable(pipe_config);
6589
6590         /*
6591          * On ILK+ LUT must be loaded before the pipe is running but with
6592          * clocks enabled
6593          */
6594         intel_color_load_luts(pipe_config);
6595         intel_color_commit(pipe_config);
6596         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6597         if (INTEL_GEN(dev_priv) < 9)
6598                 intel_disable_primary_plane(pipe_config);
6599
6600         if (INTEL_GEN(dev_priv) >= 11)
6601                 icl_set_pipe_chicken(intel_crtc);
6602
6603         if (!transcoder_is_dsi(cpu_transcoder))
6604                 intel_ddi_enable_transcoder_func(pipe_config);
6605
6606         if (dev_priv->display.initial_watermarks != NULL)
6607                 dev_priv->display.initial_watermarks(state, pipe_config);
6608
6609         if (INTEL_GEN(dev_priv) >= 11)
6610                 icl_pipe_mbus_enable(intel_crtc);
6611
6612         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6613         if (!transcoder_is_dsi(cpu_transcoder))
6614                 intel_enable_pipe(pipe_config);
6615
6616         if (pipe_config->has_pch_encoder)
6617                 lpt_pch_enable(state, pipe_config);
6618
6619         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6620                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
6621
6622         assert_vblank_disabled(crtc);
6623         intel_crtc_vblank_on(pipe_config);
6624
6625         intel_encoders_enable(intel_crtc, pipe_config, state);
6626
6627         if (psl_clkgate_wa) {
6628                 intel_wait_for_vblank(dev_priv, pipe);
6629                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6630         }
6631
6632         /* If we change the relative order between pipe/planes enabling, we need
6633          * to change the workaround. */
6634         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6635         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6636                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6637                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6638         }
6639 }
6640
6641 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6642 {
6643         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6644         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6645         enum pipe pipe = crtc->pipe;
6646
6647         /* To avoid upsetting the power well on haswell only disable the pfit if
6648          * it's in use. The hw state code will make sure we get this right. */
6649         if (old_crtc_state->pch_pfit.enabled) {
6650                 I915_WRITE(PF_CTL(pipe), 0);
6651                 I915_WRITE(PF_WIN_POS(pipe), 0);
6652                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6653         }
6654 }
6655
6656 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6657                                   struct intel_atomic_state *state)
6658 {
6659         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6660         struct drm_device *dev = crtc->dev;
6661         struct drm_i915_private *dev_priv = to_i915(dev);
6662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663         enum pipe pipe = intel_crtc->pipe;
6664
6665         /*
6666          * Sometimes spurious CPU pipe underruns happen when the
6667          * pipe is already disabled, but FDI RX/TX is still enabled.
6668          * Happens at least with VGA+HDMI cloning. Suppress them.
6669          */
6670         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6671         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6672
6673         intel_encoders_disable(intel_crtc, old_crtc_state, state);
6674
6675         drm_crtc_vblank_off(crtc);
6676         assert_vblank_disabled(crtc);
6677
6678         intel_disable_pipe(old_crtc_state);
6679
6680         ironlake_pfit_disable(old_crtc_state);
6681
6682         if (old_crtc_state->has_pch_encoder)
6683                 ironlake_fdi_disable(crtc);
6684
6685         intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6686
6687         if (old_crtc_state->has_pch_encoder) {
6688                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6689
6690                 if (HAS_PCH_CPT(dev_priv)) {
6691                         i915_reg_t reg;
6692                         u32 temp;
6693
6694                         /* disable TRANS_DP_CTL */
6695                         reg = TRANS_DP_CTL(pipe);
6696                         temp = I915_READ(reg);
6697                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6698                                   TRANS_DP_PORT_SEL_MASK);
6699                         temp |= TRANS_DP_PORT_SEL_NONE;
6700                         I915_WRITE(reg, temp);
6701
6702                         /* disable DPLL_SEL */
6703                         temp = I915_READ(PCH_DPLL_SEL);
6704                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6705                         I915_WRITE(PCH_DPLL_SEL, temp);
6706                 }
6707
6708                 ironlake_fdi_pll_disable(intel_crtc);
6709         }
6710
6711         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6712         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6713 }
6714
6715 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6716                                  struct intel_atomic_state *state)
6717 {
6718         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6719         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6721         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6722
6723         intel_encoders_disable(intel_crtc, old_crtc_state, state);
6724
6725         drm_crtc_vblank_off(crtc);
6726         assert_vblank_disabled(crtc);
6727
6728         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6729         if (!transcoder_is_dsi(cpu_transcoder))
6730                 intel_disable_pipe(old_crtc_state);
6731
6732         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
6733                 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
6734
6735         if (INTEL_GEN(dev_priv) >= 11)
6736                 icl_disable_transcoder_port_sync(old_crtc_state);
6737
6738         if (!transcoder_is_dsi(cpu_transcoder))
6739                 intel_ddi_disable_transcoder_func(old_crtc_state);
6740
6741         intel_dsc_disable(old_crtc_state);
6742
6743         if (INTEL_GEN(dev_priv) >= 9)
6744                 skylake_scaler_disable(intel_crtc);
6745         else
6746                 ironlake_pfit_disable(old_crtc_state);
6747
6748         intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6749
6750         intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
6751 }
6752
6753 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6754 {
6755         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6756         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6757
6758         if (!crtc_state->gmch_pfit.control)
6759                 return;
6760
6761         /*
6762          * The panel fitter should only be adjusted whilst the pipe is disabled,
6763          * according to register description and PRM.
6764          */
6765         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6766         assert_pipe_disabled(dev_priv, crtc->pipe);
6767
6768         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6769         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6770
6771         /* Border color in case we don't scale up to the full screen. Black by
6772          * default, change to something else for debugging. */
6773         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6774 }
6775
6776 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6777 {
6778         if (phy == PHY_NONE)
6779                 return false;
6780
6781         if (IS_ELKHARTLAKE(dev_priv))
6782                 return phy <= PHY_C;
6783
6784         if (INTEL_GEN(dev_priv) >= 11)
6785                 return phy <= PHY_B;
6786
6787         return false;
6788 }
6789
6790 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6791 {
6792         if (INTEL_GEN(dev_priv) >= 12)
6793                 return phy >= PHY_D && phy <= PHY_I;
6794
6795         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6796                 return phy >= PHY_C && phy <= PHY_F;
6797
6798         return false;
6799 }
6800
6801 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6802 {
6803         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6804                 return PHY_A;
6805
6806         return (enum phy)port;
6807 }
6808
6809 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6810 {
6811         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6812                 return PORT_TC_NONE;
6813
6814         if (INTEL_GEN(dev_priv) >= 12)
6815                 return port - PORT_D;
6816
6817         return port - PORT_C;
6818 }
6819
6820 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6821 {
6822         switch (port) {
6823         case PORT_A:
6824                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6825         case PORT_B:
6826                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6827         case PORT_C:
6828                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6829         case PORT_D:
6830                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6831         case PORT_E:
6832                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6833         case PORT_F:
6834                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6835         case PORT_G:
6836                 return POWER_DOMAIN_PORT_DDI_G_LANES;
6837         default:
6838                 MISSING_CASE(port);
6839                 return POWER_DOMAIN_PORT_OTHER;
6840         }
6841 }
6842
6843 enum intel_display_power_domain
6844 intel_aux_power_domain(struct intel_digital_port *dig_port)
6845 {
6846         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6847         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6848
6849         if (intel_phy_is_tc(dev_priv, phy) &&
6850             dig_port->tc_mode == TC_PORT_TBT_ALT) {
6851                 switch (dig_port->aux_ch) {
6852                 case AUX_CH_C:
6853                         return POWER_DOMAIN_AUX_C_TBT;
6854                 case AUX_CH_D:
6855                         return POWER_DOMAIN_AUX_D_TBT;
6856                 case AUX_CH_E:
6857                         return POWER_DOMAIN_AUX_E_TBT;
6858                 case AUX_CH_F:
6859                         return POWER_DOMAIN_AUX_F_TBT;
6860                 case AUX_CH_G:
6861                         return POWER_DOMAIN_AUX_G_TBT;
6862                 default:
6863                         MISSING_CASE(dig_port->aux_ch);
6864                         return POWER_DOMAIN_AUX_C_TBT;
6865                 }
6866         }
6867
6868         switch (dig_port->aux_ch) {
6869         case AUX_CH_A:
6870                 return POWER_DOMAIN_AUX_A;
6871         case AUX_CH_B:
6872                 return POWER_DOMAIN_AUX_B;
6873         case AUX_CH_C:
6874                 return POWER_DOMAIN_AUX_C;
6875         case AUX_CH_D:
6876                 return POWER_DOMAIN_AUX_D;
6877         case AUX_CH_E:
6878                 return POWER_DOMAIN_AUX_E;
6879         case AUX_CH_F:
6880                 return POWER_DOMAIN_AUX_F;
6881         case AUX_CH_G:
6882                 return POWER_DOMAIN_AUX_G;
6883         default:
6884                 MISSING_CASE(dig_port->aux_ch);
6885                 return POWER_DOMAIN_AUX_A;
6886         }
6887 }
6888
6889 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6890 {
6891         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6892         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6893         struct drm_encoder *encoder;
6894         enum pipe pipe = crtc->pipe;
6895         u64 mask;
6896         enum transcoder transcoder = crtc_state->cpu_transcoder;
6897
6898         if (!crtc_state->base.active)
6899                 return 0;
6900
6901         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6902         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6903         if (crtc_state->pch_pfit.enabled ||
6904             crtc_state->pch_pfit.force_thru)
6905                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6906
6907         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6908                                   crtc_state->base.encoder_mask) {
6909                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6910
6911                 mask |= BIT_ULL(intel_encoder->power_domain);
6912         }
6913
6914         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6915                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6916
6917         if (crtc_state->shared_dpll)
6918                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6919
6920         return mask;
6921 }
6922
6923 static u64
6924 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6925 {
6926         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6927         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6928         enum intel_display_power_domain domain;
6929         u64 domains, new_domains, old_domains;
6930
6931         old_domains = crtc->enabled_power_domains;
6932         crtc->enabled_power_domains = new_domains =
6933                 get_crtc_power_domains(crtc_state);
6934
6935         domains = new_domains & ~old_domains;
6936
6937         for_each_power_domain(domain, domains)
6938                 intel_display_power_get(dev_priv, domain);
6939
6940         return old_domains & ~new_domains;
6941 }
6942
6943 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6944                                       u64 domains)
6945 {
6946         enum intel_display_power_domain domain;
6947
6948         for_each_power_domain(domain, domains)
6949                 intel_display_power_put_unchecked(dev_priv, domain);
6950 }
6951
6952 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6953                                    struct intel_atomic_state *state)
6954 {
6955         struct drm_crtc *crtc = pipe_config->base.crtc;
6956         struct drm_device *dev = crtc->dev;
6957         struct drm_i915_private *dev_priv = to_i915(dev);
6958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6959         enum pipe pipe = intel_crtc->pipe;
6960
6961         if (WARN_ON(intel_crtc->active))
6962                 return;
6963
6964         if (intel_crtc_has_dp_encoder(pipe_config))
6965                 intel_dp_set_m_n(pipe_config, M1_N1);
6966
6967         intel_set_pipe_timings(pipe_config);
6968         intel_set_pipe_src_size(pipe_config);
6969
6970         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6971                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6972                 I915_WRITE(CHV_CANVAS(pipe), 0);
6973         }
6974
6975         i9xx_set_pipeconf(pipe_config);
6976
6977         intel_crtc->active = true;
6978
6979         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6980
6981         intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6982
6983         if (IS_CHERRYVIEW(dev_priv)) {
6984                 chv_prepare_pll(intel_crtc, pipe_config);
6985                 chv_enable_pll(intel_crtc, pipe_config);
6986         } else {
6987                 vlv_prepare_pll(intel_crtc, pipe_config);
6988                 vlv_enable_pll(intel_crtc, pipe_config);
6989         }
6990
6991         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6992
6993         i9xx_pfit_enable(pipe_config);
6994
6995         intel_color_load_luts(pipe_config);
6996         intel_color_commit(pipe_config);
6997         /* update DSPCNTR to configure gamma for pipe bottom color */
6998         intel_disable_primary_plane(pipe_config);
6999
7000         dev_priv->display.initial_watermarks(state, pipe_config);
7001         intel_enable_pipe(pipe_config);
7002
7003         assert_vblank_disabled(crtc);
7004         intel_crtc_vblank_on(pipe_config);
7005
7006         intel_encoders_enable(intel_crtc, pipe_config, state);
7007 }
7008
7009 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7010 {
7011         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7013
7014         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7015         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7016 }
7017
7018 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
7019                              struct intel_atomic_state *state)
7020 {
7021         struct drm_crtc *crtc = pipe_config->base.crtc;
7022         struct drm_device *dev = crtc->dev;
7023         struct drm_i915_private *dev_priv = to_i915(dev);
7024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7025         enum pipe pipe = intel_crtc->pipe;
7026
7027         if (WARN_ON(intel_crtc->active))
7028                 return;
7029
7030         i9xx_set_pll_dividers(pipe_config);
7031
7032         if (intel_crtc_has_dp_encoder(pipe_config))
7033                 intel_dp_set_m_n(pipe_config, M1_N1);
7034
7035         intel_set_pipe_timings(pipe_config);
7036         intel_set_pipe_src_size(pipe_config);
7037
7038         i9xx_set_pipeconf(pipe_config);
7039
7040         intel_crtc->active = true;
7041
7042         if (!IS_GEN(dev_priv, 2))
7043                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7044
7045         intel_encoders_pre_enable(intel_crtc, pipe_config, state);
7046
7047         i9xx_enable_pll(intel_crtc, pipe_config);
7048
7049         i9xx_pfit_enable(pipe_config);
7050
7051         intel_color_load_luts(pipe_config);
7052         intel_color_commit(pipe_config);
7053         /* update DSPCNTR to configure gamma for pipe bottom color */
7054         intel_disable_primary_plane(pipe_config);
7055
7056         if (dev_priv->display.initial_watermarks != NULL)
7057                 dev_priv->display.initial_watermarks(state,
7058                                                      pipe_config);
7059         else
7060                 intel_update_watermarks(intel_crtc);
7061         intel_enable_pipe(pipe_config);
7062
7063         assert_vblank_disabled(crtc);
7064         intel_crtc_vblank_on(pipe_config);
7065
7066         intel_encoders_enable(intel_crtc, pipe_config, state);
7067 }
7068
7069 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7070 {
7071         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
7072         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7073
7074         if (!old_crtc_state->gmch_pfit.control)
7075                 return;
7076
7077         assert_pipe_disabled(dev_priv, crtc->pipe);
7078
7079         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7080                       I915_READ(PFIT_CONTROL));
7081         I915_WRITE(PFIT_CONTROL, 0);
7082 }
7083
7084 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
7085                               struct intel_atomic_state *state)
7086 {
7087         struct drm_crtc *crtc = old_crtc_state->base.crtc;
7088         struct drm_device *dev = crtc->dev;
7089         struct drm_i915_private *dev_priv = to_i915(dev);
7090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091         enum pipe pipe = intel_crtc->pipe;
7092
7093         /*
7094          * On gen2 planes are double buffered but the pipe isn't, so we must
7095          * wait for planes to fully turn off before disabling the pipe.
7096          */
7097         if (IS_GEN(dev_priv, 2))
7098                 intel_wait_for_vblank(dev_priv, pipe);
7099
7100         intel_encoders_disable(intel_crtc, old_crtc_state, state);
7101
7102         drm_crtc_vblank_off(crtc);
7103         assert_vblank_disabled(crtc);
7104
7105         intel_disable_pipe(old_crtc_state);
7106
7107         i9xx_pfit_disable(old_crtc_state);
7108
7109         intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
7110
7111         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7112                 if (IS_CHERRYVIEW(dev_priv))
7113                         chv_disable_pll(dev_priv, pipe);
7114                 else if (IS_VALLEYVIEW(dev_priv))
7115                         vlv_disable_pll(dev_priv, pipe);
7116                 else
7117                         i9xx_disable_pll(old_crtc_state);
7118         }
7119
7120         intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
7121
7122         if (!IS_GEN(dev_priv, 2))
7123                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7124
7125         if (!dev_priv->display.initial_watermarks)
7126                 intel_update_watermarks(intel_crtc);
7127
7128         /* clock the pipe down to 640x480@60 to potentially save power */
7129         if (IS_I830(dev_priv))
7130                 i830_enable_pipe(dev_priv, pipe);
7131 }
7132
7133 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
7134                                         struct drm_modeset_acquire_ctx *ctx)
7135 {
7136         struct intel_encoder *encoder;
7137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7139         struct intel_bw_state *bw_state =
7140                 to_intel_bw_state(dev_priv->bw_obj.state);
7141         enum intel_display_power_domain domain;
7142         struct intel_plane *plane;
7143         u64 domains;
7144         struct drm_atomic_state *state;
7145         struct intel_crtc_state *crtc_state;
7146         int ret;
7147
7148         if (!intel_crtc->active)
7149                 return;
7150
7151         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
7152                 const struct intel_plane_state *plane_state =
7153                         to_intel_plane_state(plane->base.state);
7154
7155                 if (plane_state->base.visible)
7156                         intel_plane_disable_noatomic(intel_crtc, plane);
7157         }
7158
7159         state = drm_atomic_state_alloc(crtc->dev);
7160         if (!state) {
7161                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7162                               crtc->base.id, crtc->name);
7163                 return;
7164         }
7165
7166         state->acquire_ctx = ctx;
7167
7168         /* Everything's already locked, -EDEADLK can't happen. */
7169         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
7170         ret = drm_atomic_add_affected_connectors(state, crtc);
7171
7172         WARN_ON(IS_ERR(crtc_state) || ret);
7173
7174         dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state));
7175
7176         drm_atomic_state_put(state);
7177
7178         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7179                       crtc->base.id, crtc->name);
7180
7181         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
7182         crtc->state->active = false;
7183         intel_crtc->active = false;
7184         crtc->enabled = false;
7185         crtc->state->connector_mask = 0;
7186         crtc->state->encoder_mask = 0;
7187
7188         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
7189                 encoder->base.crtc = NULL;
7190
7191         intel_fbc_disable(intel_crtc);
7192         intel_update_watermarks(intel_crtc);
7193         intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
7194
7195         domains = intel_crtc->enabled_power_domains;
7196         for_each_power_domain(domain, domains)
7197                 intel_display_power_put_unchecked(dev_priv, domain);
7198         intel_crtc->enabled_power_domains = 0;
7199
7200         dev_priv->active_pipes &= ~BIT(intel_crtc->pipe);
7201         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
7202         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
7203
7204         bw_state->data_rate[intel_crtc->pipe] = 0;
7205         bw_state->num_active_planes[intel_crtc->pipe] = 0;
7206 }
7207
7208 /*
7209  * turn all crtc's off, but do not adjust state
7210  * This has to be paired with a call to intel_modeset_setup_hw_state.
7211  */
7212 int intel_display_suspend(struct drm_device *dev)
7213 {
7214         struct drm_i915_private *dev_priv = to_i915(dev);
7215         struct drm_atomic_state *state;
7216         int ret;
7217
7218         state = drm_atomic_helper_suspend(dev);
7219         ret = PTR_ERR_OR_ZERO(state);
7220         if (ret)
7221                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7222         else
7223                 dev_priv->modeset_restore_state = state;
7224         return ret;
7225 }
7226
7227 void intel_encoder_destroy(struct drm_encoder *encoder)
7228 {
7229         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7230
7231         drm_encoder_cleanup(encoder);
7232         kfree(intel_encoder);
7233 }
7234
7235 /* Cross check the actual hw state with our own modeset state tracking (and it's
7236  * internal consistency). */
7237 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7238                                          struct drm_connector_state *conn_state)
7239 {
7240         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7241
7242         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7243                       connector->base.base.id,
7244                       connector->base.name);
7245
7246         if (connector->get_hw_state(connector)) {
7247                 struct intel_encoder *encoder = connector->encoder;
7248
7249                 I915_STATE_WARN(!crtc_state,
7250                          "connector enabled without attached crtc\n");
7251
7252                 if (!crtc_state)
7253                         return;
7254
7255                 I915_STATE_WARN(!crtc_state->base.active,
7256                       "connector is active, but attached crtc isn't\n");
7257
7258                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7259                         return;
7260
7261                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7262                         "atomic encoder doesn't match attached encoder\n");
7263
7264                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7265                         "attached encoder crtc differs from connector crtc\n");
7266         } else {
7267                 I915_STATE_WARN(crtc_state && crtc_state->base.active,
7268                         "attached crtc is active, but connector isn't\n");
7269                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7270                         "best encoder set without crtc!\n");
7271         }
7272 }
7273
7274 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7275 {
7276         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7277                 return crtc_state->fdi_lanes;
7278
7279         return 0;
7280 }
7281
7282 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7283                                      struct intel_crtc_state *pipe_config)
7284 {
7285         struct drm_i915_private *dev_priv = to_i915(dev);
7286         struct drm_atomic_state *state = pipe_config->base.state;
7287         struct intel_crtc *other_crtc;
7288         struct intel_crtc_state *other_crtc_state;
7289
7290         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7291                       pipe_name(pipe), pipe_config->fdi_lanes);
7292         if (pipe_config->fdi_lanes > 4) {
7293                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7294                               pipe_name(pipe), pipe_config->fdi_lanes);
7295                 return -EINVAL;
7296         }
7297
7298         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7299                 if (pipe_config->fdi_lanes > 2) {
7300                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7301                                       pipe_config->fdi_lanes);
7302                         return -EINVAL;
7303                 } else {
7304                         return 0;
7305                 }
7306         }
7307
7308         if (INTEL_NUM_PIPES(dev_priv) == 2)
7309                 return 0;
7310
7311         /* Ivybridge 3 pipe is really complicated */
7312         switch (pipe) {
7313         case PIPE_A:
7314                 return 0;
7315         case PIPE_B:
7316                 if (pipe_config->fdi_lanes <= 2)
7317                         return 0;
7318
7319                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7320                 other_crtc_state =
7321                         intel_atomic_get_crtc_state(state, other_crtc);
7322                 if (IS_ERR(other_crtc_state))
7323                         return PTR_ERR(other_crtc_state);
7324
7325                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7326                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7327                                       pipe_name(pipe), pipe_config->fdi_lanes);
7328                         return -EINVAL;
7329                 }
7330                 return 0;
7331         case PIPE_C:
7332                 if (pipe_config->fdi_lanes > 2) {
7333                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7334                                       pipe_name(pipe), pipe_config->fdi_lanes);
7335                         return -EINVAL;
7336                 }
7337
7338                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7339                 other_crtc_state =
7340                         intel_atomic_get_crtc_state(state, other_crtc);
7341                 if (IS_ERR(other_crtc_state))
7342                         return PTR_ERR(other_crtc_state);
7343
7344                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7345                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7346                         return -EINVAL;
7347                 }
7348                 return 0;
7349         default:
7350                 BUG();
7351         }
7352 }
7353
7354 #define RETRY 1
7355 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7356                                        struct intel_crtc_state *pipe_config)
7357 {
7358         struct drm_device *dev = intel_crtc->base.dev;
7359         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7360         int lane, link_bw, fdi_dotclock, ret;
7361         bool needs_recompute = false;
7362
7363 retry:
7364         /* FDI is a binary signal running at ~2.7GHz, encoding
7365          * each output octet as 10 bits. The actual frequency
7366          * is stored as a divider into a 100MHz clock, and the
7367          * mode pixel clock is stored in units of 1KHz.
7368          * Hence the bw of each lane in terms of the mode signal
7369          * is:
7370          */
7371         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7372
7373         fdi_dotclock = adjusted_mode->crtc_clock;
7374
7375         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7376                                            pipe_config->pipe_bpp);
7377
7378         pipe_config->fdi_lanes = lane;
7379
7380         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7381                                link_bw, &pipe_config->fdi_m_n, false, false);
7382
7383         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7384         if (ret == -EDEADLK)
7385                 return ret;
7386
7387         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7388                 pipe_config->pipe_bpp -= 2*3;
7389                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7390                               pipe_config->pipe_bpp);
7391                 needs_recompute = true;
7392                 pipe_config->bw_constrained = true;
7393
7394                 goto retry;
7395         }
7396
7397         if (needs_recompute)
7398                 return RETRY;
7399
7400         return ret;
7401 }
7402
7403 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7404 {
7405         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7406         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7407
7408         /* IPS only exists on ULT machines and is tied to pipe A. */
7409         if (!hsw_crtc_supports_ips(crtc))
7410                 return false;
7411
7412         if (!i915_modparams.enable_ips)
7413                 return false;
7414
7415         if (crtc_state->pipe_bpp > 24)
7416                 return false;
7417
7418         /*
7419          * We compare against max which means we must take
7420          * the increased cdclk requirement into account when
7421          * calculating the new cdclk.
7422          *
7423          * Should measure whether using a lower cdclk w/o IPS
7424          */
7425         if (IS_BROADWELL(dev_priv) &&
7426             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7427                 return false;
7428
7429         return true;
7430 }
7431
7432 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7433 {
7434         struct drm_i915_private *dev_priv =
7435                 to_i915(crtc_state->base.crtc->dev);
7436         struct intel_atomic_state *intel_state =
7437                 to_intel_atomic_state(crtc_state->base.state);
7438
7439         if (!hsw_crtc_state_ips_capable(crtc_state))
7440                 return false;
7441
7442         /*
7443          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7444          * enabled and disabled dynamically based on package C states,
7445          * user space can't make reliable use of the CRCs, so let's just
7446          * completely disable it.
7447          */
7448         if (crtc_state->crc_enabled)
7449                 return false;
7450
7451         /* IPS should be fine as long as at least one plane is enabled. */
7452         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7453                 return false;
7454
7455         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7456         if (IS_BROADWELL(dev_priv) &&
7457             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7458                 return false;
7459
7460         return true;
7461 }
7462
7463 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7464 {
7465         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7466
7467         /* GDG double wide on either pipe, otherwise pipe A only */
7468         return INTEL_GEN(dev_priv) < 4 &&
7469                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7470 }
7471
7472 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7473 {
7474         u32 pixel_rate;
7475
7476         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
7477
7478         /*
7479          * We only use IF-ID interlacing. If we ever use
7480          * PF-ID we'll need to adjust the pixel_rate here.
7481          */
7482
7483         if (pipe_config->pch_pfit.enabled) {
7484                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7485                 u32 pfit_size = pipe_config->pch_pfit.size;
7486
7487                 pipe_w = pipe_config->pipe_src_w;
7488                 pipe_h = pipe_config->pipe_src_h;
7489
7490                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7491                 pfit_h = pfit_size & 0xFFFF;
7492                 if (pipe_w < pfit_w)
7493                         pipe_w = pfit_w;
7494                 if (pipe_h < pfit_h)
7495                         pipe_h = pfit_h;
7496
7497                 if (WARN_ON(!pfit_w || !pfit_h))
7498                         return pixel_rate;
7499
7500                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7501                                      pfit_w * pfit_h);
7502         }
7503
7504         return pixel_rate;
7505 }
7506
7507 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7508 {
7509         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
7510
7511         if (HAS_GMCH(dev_priv))
7512                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7513                 crtc_state->pixel_rate =
7514                         crtc_state->base.adjusted_mode.crtc_clock;
7515         else
7516                 crtc_state->pixel_rate =
7517                         ilk_pipe_pixel_rate(crtc_state);
7518 }
7519
7520 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7521                                      struct intel_crtc_state *pipe_config)
7522 {
7523         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7524         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7525         int clock_limit = dev_priv->max_dotclk_freq;
7526
7527         if (INTEL_GEN(dev_priv) < 4) {
7528                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7529
7530                 /*
7531                  * Enable double wide mode when the dot clock
7532                  * is > 90% of the (display) core speed.
7533                  */
7534                 if (intel_crtc_supports_double_wide(crtc) &&
7535                     adjusted_mode->crtc_clock > clock_limit) {
7536                         clock_limit = dev_priv->max_dotclk_freq;
7537                         pipe_config->double_wide = true;
7538                 }
7539         }
7540
7541         if (adjusted_mode->crtc_clock > clock_limit) {
7542                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7543                               adjusted_mode->crtc_clock, clock_limit,
7544                               yesno(pipe_config->double_wide));
7545                 return -EINVAL;
7546         }
7547
7548         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7549              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7550              pipe_config->base.ctm) {
7551                 /*
7552                  * There is only one pipe CSC unit per pipe, and we need that
7553                  * for output conversion from RGB->YCBCR. So if CTM is already
7554                  * applied we can't support YCBCR420 output.
7555                  */
7556                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7557                 return -EINVAL;
7558         }
7559
7560         /*
7561          * Pipe horizontal size must be even in:
7562          * - DVO ganged mode
7563          * - LVDS dual channel mode
7564          * - Double wide pipe
7565          */
7566         if (pipe_config->pipe_src_w & 1) {
7567                 if (pipe_config->double_wide) {
7568                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7569                         return -EINVAL;
7570                 }
7571
7572                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7573                     intel_is_dual_link_lvds(dev_priv)) {
7574                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7575                         return -EINVAL;
7576                 }
7577         }
7578
7579         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7580          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7581          */
7582         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7583                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7584                 return -EINVAL;
7585
7586         intel_crtc_compute_pixel_rate(pipe_config);
7587
7588         if (pipe_config->has_pch_encoder)
7589                 return ironlake_fdi_compute_config(crtc, pipe_config);
7590
7591         return 0;
7592 }
7593
7594 static void
7595 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7596 {
7597         while (*num > DATA_LINK_M_N_MASK ||
7598                *den > DATA_LINK_M_N_MASK) {
7599                 *num >>= 1;
7600                 *den >>= 1;
7601         }
7602 }
7603
7604 static void compute_m_n(unsigned int m, unsigned int n,
7605                         u32 *ret_m, u32 *ret_n,
7606                         bool constant_n)
7607 {
7608         /*
7609          * Several DP dongles in particular seem to be fussy about
7610          * too large link M/N values. Give N value as 0x8000 that
7611          * should be acceptable by specific devices. 0x8000 is the
7612          * specified fixed N value for asynchronous clock mode,
7613          * which the devices expect also in synchronous clock mode.
7614          */
7615         if (constant_n)
7616                 *ret_n = 0x8000;
7617         else
7618                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7619
7620         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7621         intel_reduce_m_n_ratio(ret_m, ret_n);
7622 }
7623
7624 void
7625 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7626                        int pixel_clock, int link_clock,
7627                        struct intel_link_m_n *m_n,
7628                        bool constant_n, bool fec_enable)
7629 {
7630         u32 data_clock = bits_per_pixel * pixel_clock;
7631
7632         if (fec_enable)
7633                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7634
7635         m_n->tu = 64;
7636         compute_m_n(data_clock,
7637                     link_clock * nlanes * 8,
7638                     &m_n->gmch_m, &m_n->gmch_n,
7639                     constant_n);
7640
7641         compute_m_n(pixel_clock, link_clock,
7642                     &m_n->link_m, &m_n->link_n,
7643                     constant_n);
7644 }
7645
7646 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7647 {
7648         /*
7649          * There may be no VBT; and if the BIOS enabled SSC we can
7650          * just keep using it to avoid unnecessary flicker.  Whereas if the
7651          * BIOS isn't using it, don't assume it will work even if the VBT
7652          * indicates as much.
7653          */
7654         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7655                 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7656                         DREF_SSC1_ENABLE;
7657
7658                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7659                         DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7660                                       enableddisabled(bios_lvds_use_ssc),
7661                                       enableddisabled(dev_priv->vbt.lvds_use_ssc));
7662                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7663                 }
7664         }
7665 }
7666
7667 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7668 {
7669         if (i915_modparams.panel_use_ssc >= 0)
7670                 return i915_modparams.panel_use_ssc != 0;
7671         return dev_priv->vbt.lvds_use_ssc
7672                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7673 }
7674
7675 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7676 {
7677         return (1 << dpll->n) << 16 | dpll->m2;
7678 }
7679
7680 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7681 {
7682         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7683 }
7684
7685 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7686                                      struct intel_crtc_state *crtc_state,
7687                                      struct dpll *reduced_clock)
7688 {
7689         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7690         u32 fp, fp2 = 0;
7691
7692         if (IS_PINEVIEW(dev_priv)) {
7693                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7694                 if (reduced_clock)
7695                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7696         } else {
7697                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7698                 if (reduced_clock)
7699                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7700         }
7701
7702         crtc_state->dpll_hw_state.fp0 = fp;
7703
7704         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7705             reduced_clock) {
7706                 crtc_state->dpll_hw_state.fp1 = fp2;
7707         } else {
7708                 crtc_state->dpll_hw_state.fp1 = fp;
7709         }
7710 }
7711
7712 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7713                 pipe)
7714 {
7715         u32 reg_val;
7716
7717         /*
7718          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7719          * and set it to a reasonable value instead.
7720          */
7721         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7722         reg_val &= 0xffffff00;
7723         reg_val |= 0x00000030;
7724         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7725
7726         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7727         reg_val &= 0x00ffffff;
7728         reg_val |= 0x8c000000;
7729         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7730
7731         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7732         reg_val &= 0xffffff00;
7733         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7734
7735         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7736         reg_val &= 0x00ffffff;
7737         reg_val |= 0xb0000000;
7738         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7739 }
7740
7741 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7742                                          const struct intel_link_m_n *m_n)
7743 {
7744         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7745         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7746         enum pipe pipe = crtc->pipe;
7747
7748         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7749         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7750         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7751         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7752 }
7753
7754 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7755                                  enum transcoder transcoder)
7756 {
7757         if (IS_HASWELL(dev_priv))
7758                 return transcoder == TRANSCODER_EDP;
7759
7760         /*
7761          * Strictly speaking some registers are available before
7762          * gen7, but we only support DRRS on gen7+
7763          */
7764         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7765 }
7766
7767 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7768                                          const struct intel_link_m_n *m_n,
7769                                          const struct intel_link_m_n *m2_n2)
7770 {
7771         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7772         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7773         enum pipe pipe = crtc->pipe;
7774         enum transcoder transcoder = crtc_state->cpu_transcoder;
7775
7776         if (INTEL_GEN(dev_priv) >= 5) {
7777                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7778                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7779                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7780                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7781                 /*
7782                  *  M2_N2 registers are set only if DRRS is supported
7783                  * (to make sure the registers are not unnecessarily accessed).
7784                  */
7785                 if (m2_n2 && crtc_state->has_drrs &&
7786                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7787                         I915_WRITE(PIPE_DATA_M2(transcoder),
7788                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7789                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7790                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7791                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7792                 }
7793         } else {
7794                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7795                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7796                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7797                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7798         }
7799 }
7800
7801 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7802 {
7803         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7804
7805         if (m_n == M1_N1) {
7806                 dp_m_n = &crtc_state->dp_m_n;
7807                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7808         } else if (m_n == M2_N2) {
7809
7810                 /*
7811                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7812                  * needs to be programmed into M1_N1.
7813                  */
7814                 dp_m_n = &crtc_state->dp_m2_n2;
7815         } else {
7816                 DRM_ERROR("Unsupported divider value\n");
7817                 return;
7818         }
7819
7820         if (crtc_state->has_pch_encoder)
7821                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7822         else
7823                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7824 }
7825
7826 static void vlv_compute_dpll(struct intel_crtc *crtc,
7827                              struct intel_crtc_state *pipe_config)
7828 {
7829         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7830                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7831         if (crtc->pipe != PIPE_A)
7832                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7833
7834         /* DPLL not used with DSI, but still need the rest set up */
7835         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7836                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7837                         DPLL_EXT_BUFFER_ENABLE_VLV;
7838
7839         pipe_config->dpll_hw_state.dpll_md =
7840                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7841 }
7842
7843 static void chv_compute_dpll(struct intel_crtc *crtc,
7844                              struct intel_crtc_state *pipe_config)
7845 {
7846         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7847                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7848         if (crtc->pipe != PIPE_A)
7849                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7850
7851         /* DPLL not used with DSI, but still need the rest set up */
7852         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7853                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7854
7855         pipe_config->dpll_hw_state.dpll_md =
7856                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7857 }
7858
7859 static void vlv_prepare_pll(struct intel_crtc *crtc,
7860                             const struct intel_crtc_state *pipe_config)
7861 {
7862         struct drm_device *dev = crtc->base.dev;
7863         struct drm_i915_private *dev_priv = to_i915(dev);
7864         enum pipe pipe = crtc->pipe;
7865         u32 mdiv;
7866         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7867         u32 coreclk, reg_val;
7868
7869         /* Enable Refclk */
7870         I915_WRITE(DPLL(pipe),
7871                    pipe_config->dpll_hw_state.dpll &
7872                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7873
7874         /* No need to actually set up the DPLL with DSI */
7875         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7876                 return;
7877
7878         vlv_dpio_get(dev_priv);
7879
7880         bestn = pipe_config->dpll.n;
7881         bestm1 = pipe_config->dpll.m1;
7882         bestm2 = pipe_config->dpll.m2;
7883         bestp1 = pipe_config->dpll.p1;
7884         bestp2 = pipe_config->dpll.p2;
7885
7886         /* See eDP HDMI DPIO driver vbios notes doc */
7887
7888         /* PLL B needs special handling */
7889         if (pipe == PIPE_B)
7890                 vlv_pllb_recal_opamp(dev_priv, pipe);
7891
7892         /* Set up Tx target for periodic Rcomp update */
7893         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7894
7895         /* Disable target IRef on PLL */
7896         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7897         reg_val &= 0x00ffffff;
7898         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7899
7900         /* Disable fast lock */
7901         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7902
7903         /* Set idtafcrecal before PLL is enabled */
7904         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7905         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7906         mdiv |= ((bestn << DPIO_N_SHIFT));
7907         mdiv |= (1 << DPIO_K_SHIFT);
7908
7909         /*
7910          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7911          * but we don't support that).
7912          * Note: don't use the DAC post divider as it seems unstable.
7913          */
7914         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7915         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7916
7917         mdiv |= DPIO_ENABLE_CALIBRATION;
7918         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7919
7920         /* Set HBR and RBR LPF coefficients */
7921         if (pipe_config->port_clock == 162000 ||
7922             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7923             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7924                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7925                                  0x009f0003);
7926         else
7927                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7928                                  0x00d0000f);
7929
7930         if (intel_crtc_has_dp_encoder(pipe_config)) {
7931                 /* Use SSC source */
7932                 if (pipe == PIPE_A)
7933                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7934                                          0x0df40000);
7935                 else
7936                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7937                                          0x0df70000);
7938         } else { /* HDMI or VGA */
7939                 /* Use bend source */
7940                 if (pipe == PIPE_A)
7941                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7942                                          0x0df70000);
7943                 else
7944                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7945                                          0x0df40000);
7946         }
7947
7948         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7949         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7950         if (intel_crtc_has_dp_encoder(pipe_config))
7951                 coreclk |= 0x01000000;
7952         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7953
7954         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7955
7956         vlv_dpio_put(dev_priv);
7957 }
7958
7959 static void chv_prepare_pll(struct intel_crtc *crtc,
7960                             const struct intel_crtc_state *pipe_config)
7961 {
7962         struct drm_device *dev = crtc->base.dev;
7963         struct drm_i915_private *dev_priv = to_i915(dev);
7964         enum pipe pipe = crtc->pipe;
7965         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7966         u32 loopfilter, tribuf_calcntr;
7967         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7968         u32 dpio_val;
7969         int vco;
7970
7971         /* Enable Refclk and SSC */
7972         I915_WRITE(DPLL(pipe),
7973                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7974
7975         /* No need to actually set up the DPLL with DSI */
7976         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7977                 return;
7978
7979         bestn = pipe_config->dpll.n;
7980         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7981         bestm1 = pipe_config->dpll.m1;
7982         bestm2 = pipe_config->dpll.m2 >> 22;
7983         bestp1 = pipe_config->dpll.p1;
7984         bestp2 = pipe_config->dpll.p2;
7985         vco = pipe_config->dpll.vco;
7986         dpio_val = 0;
7987         loopfilter = 0;
7988
7989         vlv_dpio_get(dev_priv);
7990
7991         /* p1 and p2 divider */
7992         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7993                         5 << DPIO_CHV_S1_DIV_SHIFT |
7994                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7995                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7996                         1 << DPIO_CHV_K_DIV_SHIFT);
7997
7998         /* Feedback post-divider - m2 */
7999         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8000
8001         /* Feedback refclk divider - n and m1 */
8002         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8003                         DPIO_CHV_M1_DIV_BY_2 |
8004                         1 << DPIO_CHV_N_DIV_SHIFT);
8005
8006         /* M2 fraction division */
8007         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8008
8009         /* M2 fraction division enable */
8010         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8011         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8012         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8013         if (bestm2_frac)
8014                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8015         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8016
8017         /* Program digital lock detect threshold */
8018         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8019         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8020                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8021         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8022         if (!bestm2_frac)
8023                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8024         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8025
8026         /* Loop filter */
8027         if (vco == 5400000) {
8028                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8029                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8030                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8031                 tribuf_calcntr = 0x9;
8032         } else if (vco <= 6200000) {
8033                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8034                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8035                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8036                 tribuf_calcntr = 0x9;
8037         } else if (vco <= 6480000) {
8038                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8039                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8040                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8041                 tribuf_calcntr = 0x8;
8042         } else {
8043                 /* Not supported. Apply the same limits as in the max case */
8044                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8045                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8046                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8047                 tribuf_calcntr = 0;
8048         }
8049         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8050
8051         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8052         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8053         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8054         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8055
8056         /* AFC Recal */
8057         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8058                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8059                         DPIO_AFC_RECAL);
8060
8061         vlv_dpio_put(dev_priv);
8062 }
8063
8064 /**
8065  * vlv_force_pll_on - forcibly enable just the PLL
8066  * @dev_priv: i915 private structure
8067  * @pipe: pipe PLL to enable
8068  * @dpll: PLL configuration
8069  *
8070  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8071  * in cases where we need the PLL enabled even when @pipe is not going to
8072  * be enabled.
8073  */
8074 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8075                      const struct dpll *dpll)
8076 {
8077         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8078         struct intel_crtc_state *pipe_config;
8079
8080         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8081         if (!pipe_config)
8082                 return -ENOMEM;
8083
8084         pipe_config->base.crtc = &crtc->base;
8085         pipe_config->pixel_multiplier = 1;
8086         pipe_config->dpll = *dpll;
8087
8088         if (IS_CHERRYVIEW(dev_priv)) {
8089                 chv_compute_dpll(crtc, pipe_config);
8090                 chv_prepare_pll(crtc, pipe_config);
8091                 chv_enable_pll(crtc, pipe_config);
8092         } else {
8093                 vlv_compute_dpll(crtc, pipe_config);
8094                 vlv_prepare_pll(crtc, pipe_config);
8095                 vlv_enable_pll(crtc, pipe_config);
8096         }
8097
8098         kfree(pipe_config);
8099
8100         return 0;
8101 }
8102
8103 /**
8104  * vlv_force_pll_off - forcibly disable just the PLL
8105  * @dev_priv: i915 private structure
8106  * @pipe: pipe PLL to disable
8107  *
8108  * Disable the PLL for @pipe. To be used in cases where we need
8109  * the PLL enabled even when @pipe is not going to be enabled.
8110  */
8111 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8112 {
8113         if (IS_CHERRYVIEW(dev_priv))
8114                 chv_disable_pll(dev_priv, pipe);
8115         else
8116                 vlv_disable_pll(dev_priv, pipe);
8117 }
8118
8119 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8120                               struct intel_crtc_state *crtc_state,
8121                               struct dpll *reduced_clock)
8122 {
8123         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8124         u32 dpll;
8125         struct dpll *clock = &crtc_state->dpll;
8126
8127         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8128
8129         dpll = DPLL_VGA_MODE_DIS;
8130
8131         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8132                 dpll |= DPLLB_MODE_LVDS;
8133         else
8134                 dpll |= DPLLB_MODE_DAC_SERIAL;
8135
8136         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8137             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8138                 dpll |= (crtc_state->pixel_multiplier - 1)
8139                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8140         }
8141
8142         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8143             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8144                 dpll |= DPLL_SDVO_HIGH_SPEED;
8145
8146         if (intel_crtc_has_dp_encoder(crtc_state))
8147                 dpll |= DPLL_SDVO_HIGH_SPEED;
8148
8149         /* compute bitmask from p1 value */
8150         if (IS_PINEVIEW(dev_priv))
8151                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8152         else {
8153                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8154                 if (IS_G4X(dev_priv) && reduced_clock)
8155                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8156         }
8157         switch (clock->p2) {
8158         case 5:
8159                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8160                 break;
8161         case 7:
8162                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8163                 break;
8164         case 10:
8165                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8166                 break;
8167         case 14:
8168                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8169                 break;
8170         }
8171         if (INTEL_GEN(dev_priv) >= 4)
8172                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8173
8174         if (crtc_state->sdvo_tv_clock)
8175                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8176         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8177                  intel_panel_use_ssc(dev_priv))
8178                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8179         else
8180                 dpll |= PLL_REF_INPUT_DREFCLK;
8181
8182         dpll |= DPLL_VCO_ENABLE;
8183         crtc_state->dpll_hw_state.dpll = dpll;
8184
8185         if (INTEL_GEN(dev_priv) >= 4) {
8186                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8187                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8188                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8189         }
8190 }
8191
8192 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8193                               struct intel_crtc_state *crtc_state,
8194                               struct dpll *reduced_clock)
8195 {
8196         struct drm_device *dev = crtc->base.dev;
8197         struct drm_i915_private *dev_priv = to_i915(dev);
8198         u32 dpll;
8199         struct dpll *clock = &crtc_state->dpll;
8200
8201         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8202
8203         dpll = DPLL_VGA_MODE_DIS;
8204
8205         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8206                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8207         } else {
8208                 if (clock->p1 == 2)
8209                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8210                 else
8211                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8212                 if (clock->p2 == 4)
8213                         dpll |= PLL_P2_DIVIDE_BY_4;
8214         }
8215
8216         /*
8217          * Bspec:
8218          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8219          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8220          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8221          *  Enable) must be set to “1” in both the DPLL A Control Register
8222          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8223          *
8224          * For simplicity We simply keep both bits always enabled in
8225          * both DPLLS. The spec says we should disable the DVO 2X clock
8226          * when not needed, but this seems to work fine in practice.
8227          */
8228         if (IS_I830(dev_priv) ||
8229             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8230                 dpll |= DPLL_DVO_2X_MODE;
8231
8232         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8233             intel_panel_use_ssc(dev_priv))
8234                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8235         else
8236                 dpll |= PLL_REF_INPUT_DREFCLK;
8237
8238         dpll |= DPLL_VCO_ENABLE;
8239         crtc_state->dpll_hw_state.dpll = dpll;
8240 }
8241
8242 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8243 {
8244         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8245         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8246         enum pipe pipe = crtc->pipe;
8247         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8248         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
8249         u32 crtc_vtotal, crtc_vblank_end;
8250         int vsyncshift = 0;
8251
8252         /* We need to be careful not to changed the adjusted mode, for otherwise
8253          * the hw state checker will get angry at the mismatch. */
8254         crtc_vtotal = adjusted_mode->crtc_vtotal;
8255         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8256
8257         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8258                 /* the chip adds 2 halflines automatically */
8259                 crtc_vtotal -= 1;
8260                 crtc_vblank_end -= 1;
8261
8262                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8263                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8264                 else
8265                         vsyncshift = adjusted_mode->crtc_hsync_start -
8266                                 adjusted_mode->crtc_htotal / 2;
8267                 if (vsyncshift < 0)
8268                         vsyncshift += adjusted_mode->crtc_htotal;
8269         }
8270
8271         if (INTEL_GEN(dev_priv) > 3)
8272                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8273
8274         I915_WRITE(HTOTAL(cpu_transcoder),
8275                    (adjusted_mode->crtc_hdisplay - 1) |
8276                    ((adjusted_mode->crtc_htotal - 1) << 16));
8277         I915_WRITE(HBLANK(cpu_transcoder),
8278                    (adjusted_mode->crtc_hblank_start - 1) |
8279                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8280         I915_WRITE(HSYNC(cpu_transcoder),
8281                    (adjusted_mode->crtc_hsync_start - 1) |
8282                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8283
8284         I915_WRITE(VTOTAL(cpu_transcoder),
8285                    (adjusted_mode->crtc_vdisplay - 1) |
8286                    ((crtc_vtotal - 1) << 16));
8287         I915_WRITE(VBLANK(cpu_transcoder),
8288                    (adjusted_mode->crtc_vblank_start - 1) |
8289                    ((crtc_vblank_end - 1) << 16));
8290         I915_WRITE(VSYNC(cpu_transcoder),
8291                    (adjusted_mode->crtc_vsync_start - 1) |
8292                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8293
8294         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8295          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8296          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8297          * bits. */
8298         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8299             (pipe == PIPE_B || pipe == PIPE_C))
8300                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8301
8302 }
8303
8304 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8305 {
8306         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8307         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8308         enum pipe pipe = crtc->pipe;
8309
8310         /* pipesrc controls the size that is scaled from, which should
8311          * always be the user's requested size.
8312          */
8313         I915_WRITE(PIPESRC(pipe),
8314                    ((crtc_state->pipe_src_w - 1) << 16) |
8315                    (crtc_state->pipe_src_h - 1));
8316 }
8317
8318 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8319 {
8320         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
8321         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8322
8323         if (IS_GEN(dev_priv, 2))
8324                 return false;
8325
8326         if (INTEL_GEN(dev_priv) >= 9 ||
8327             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8328                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8329         else
8330                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8331 }
8332
8333 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8334                                    struct intel_crtc_state *pipe_config)
8335 {
8336         struct drm_device *dev = crtc->base.dev;
8337         struct drm_i915_private *dev_priv = to_i915(dev);
8338         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8339         u32 tmp;
8340
8341         tmp = I915_READ(HTOTAL(cpu_transcoder));
8342         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8343         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8344
8345         if (!transcoder_is_dsi(cpu_transcoder)) {
8346                 tmp = I915_READ(HBLANK(cpu_transcoder));
8347                 pipe_config->base.adjusted_mode.crtc_hblank_start =
8348                                                         (tmp & 0xffff) + 1;
8349                 pipe_config->base.adjusted_mode.crtc_hblank_end =
8350                                                 ((tmp >> 16) & 0xffff) + 1;
8351         }
8352         tmp = I915_READ(HSYNC(cpu_transcoder));
8353         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8354         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8355
8356         tmp = I915_READ(VTOTAL(cpu_transcoder));
8357         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8358         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8359
8360         if (!transcoder_is_dsi(cpu_transcoder)) {
8361                 tmp = I915_READ(VBLANK(cpu_transcoder));
8362                 pipe_config->base.adjusted_mode.crtc_vblank_start =
8363                                                         (tmp & 0xffff) + 1;
8364                 pipe_config->base.adjusted_mode.crtc_vblank_end =
8365                                                 ((tmp >> 16) & 0xffff) + 1;
8366         }
8367         tmp = I915_READ(VSYNC(cpu_transcoder));
8368         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8369         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8370
8371         if (intel_pipe_is_interlaced(pipe_config)) {
8372                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8373                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8374                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8375         }
8376 }
8377
8378 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8379                                     struct intel_crtc_state *pipe_config)
8380 {
8381         struct drm_device *dev = crtc->base.dev;
8382         struct drm_i915_private *dev_priv = to_i915(dev);
8383         u32 tmp;
8384
8385         tmp = I915_READ(PIPESRC(crtc->pipe));
8386         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8387         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8388
8389         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8390         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8391 }
8392
8393 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8394                                  struct intel_crtc_state *pipe_config)
8395 {
8396         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8397         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8398         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8399         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8400
8401         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8402         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8403         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8404         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8405
8406         mode->flags = pipe_config->base.adjusted_mode.flags;
8407         mode->type = DRM_MODE_TYPE_DRIVER;
8408
8409         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8410
8411         mode->hsync = drm_mode_hsync(mode);
8412         mode->vrefresh = drm_mode_vrefresh(mode);
8413         drm_mode_set_name(mode);
8414 }
8415
8416 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8417 {
8418         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8419         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8420         u32 pipeconf;
8421
8422         pipeconf = 0;
8423
8424         /* we keep both pipes enabled on 830 */
8425         if (IS_I830(dev_priv))
8426                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8427
8428         if (crtc_state->double_wide)
8429                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8430
8431         /* only g4x and later have fancy bpc/dither controls */
8432         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8433             IS_CHERRYVIEW(dev_priv)) {
8434                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8435                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8436                         pipeconf |= PIPECONF_DITHER_EN |
8437                                     PIPECONF_DITHER_TYPE_SP;
8438
8439                 switch (crtc_state->pipe_bpp) {
8440                 case 18:
8441                         pipeconf |= PIPECONF_6BPC;
8442                         break;
8443                 case 24:
8444                         pipeconf |= PIPECONF_8BPC;
8445                         break;
8446                 case 30:
8447                         pipeconf |= PIPECONF_10BPC;
8448                         break;
8449                 default:
8450                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8451                         BUG();
8452                 }
8453         }
8454
8455         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8456                 if (INTEL_GEN(dev_priv) < 4 ||
8457                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8458                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8459                 else
8460                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8461         } else {
8462                 pipeconf |= PIPECONF_PROGRESSIVE;
8463         }
8464
8465         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8466              crtc_state->limited_color_range)
8467                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8468
8469         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8470
8471         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8472         POSTING_READ(PIPECONF(crtc->pipe));
8473 }
8474
8475 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8476                                    struct intel_crtc_state *crtc_state)
8477 {
8478         struct drm_device *dev = crtc->base.dev;
8479         struct drm_i915_private *dev_priv = to_i915(dev);
8480         const struct intel_limit *limit;
8481         int refclk = 48000;
8482
8483         memset(&crtc_state->dpll_hw_state, 0,
8484                sizeof(crtc_state->dpll_hw_state));
8485
8486         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8487                 if (intel_panel_use_ssc(dev_priv)) {
8488                         refclk = dev_priv->vbt.lvds_ssc_freq;
8489                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8490                 }
8491
8492                 limit = &intel_limits_i8xx_lvds;
8493         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8494                 limit = &intel_limits_i8xx_dvo;
8495         } else {
8496                 limit = &intel_limits_i8xx_dac;
8497         }
8498
8499         if (!crtc_state->clock_set &&
8500             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8501                                  refclk, NULL, &crtc_state->dpll)) {
8502                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8503                 return -EINVAL;
8504         }
8505
8506         i8xx_compute_dpll(crtc, crtc_state, NULL);
8507
8508         return 0;
8509 }
8510
8511 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8512                                   struct intel_crtc_state *crtc_state)
8513 {
8514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8515         const struct intel_limit *limit;
8516         int refclk = 96000;
8517
8518         memset(&crtc_state->dpll_hw_state, 0,
8519                sizeof(crtc_state->dpll_hw_state));
8520
8521         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8522                 if (intel_panel_use_ssc(dev_priv)) {
8523                         refclk = dev_priv->vbt.lvds_ssc_freq;
8524                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8525                 }
8526
8527                 if (intel_is_dual_link_lvds(dev_priv))
8528                         limit = &intel_limits_g4x_dual_channel_lvds;
8529                 else
8530                         limit = &intel_limits_g4x_single_channel_lvds;
8531         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8532                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8533                 limit = &intel_limits_g4x_hdmi;
8534         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8535                 limit = &intel_limits_g4x_sdvo;
8536         } else {
8537                 /* The option is for other outputs */
8538                 limit = &intel_limits_i9xx_sdvo;
8539         }
8540
8541         if (!crtc_state->clock_set &&
8542             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8543                                 refclk, NULL, &crtc_state->dpll)) {
8544                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8545                 return -EINVAL;
8546         }
8547
8548         i9xx_compute_dpll(crtc, crtc_state, NULL);
8549
8550         return 0;
8551 }
8552
8553 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8554                                   struct intel_crtc_state *crtc_state)
8555 {
8556         struct drm_device *dev = crtc->base.dev;
8557         struct drm_i915_private *dev_priv = to_i915(dev);
8558         const struct intel_limit *limit;
8559         int refclk = 96000;
8560
8561         memset(&crtc_state->dpll_hw_state, 0,
8562                sizeof(crtc_state->dpll_hw_state));
8563
8564         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8565                 if (intel_panel_use_ssc(dev_priv)) {
8566                         refclk = dev_priv->vbt.lvds_ssc_freq;
8567                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8568                 }
8569
8570                 limit = &intel_limits_pineview_lvds;
8571         } else {
8572                 limit = &intel_limits_pineview_sdvo;
8573         }
8574
8575         if (!crtc_state->clock_set &&
8576             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8577                                 refclk, NULL, &crtc_state->dpll)) {
8578                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8579                 return -EINVAL;
8580         }
8581
8582         i9xx_compute_dpll(crtc, crtc_state, NULL);
8583
8584         return 0;
8585 }
8586
8587 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8588                                    struct intel_crtc_state *crtc_state)
8589 {
8590         struct drm_device *dev = crtc->base.dev;
8591         struct drm_i915_private *dev_priv = to_i915(dev);
8592         const struct intel_limit *limit;
8593         int refclk = 96000;
8594
8595         memset(&crtc_state->dpll_hw_state, 0,
8596                sizeof(crtc_state->dpll_hw_state));
8597
8598         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8599                 if (intel_panel_use_ssc(dev_priv)) {
8600                         refclk = dev_priv->vbt.lvds_ssc_freq;
8601                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8602                 }
8603
8604                 limit = &intel_limits_i9xx_lvds;
8605         } else {
8606                 limit = &intel_limits_i9xx_sdvo;
8607         }
8608
8609         if (!crtc_state->clock_set &&
8610             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8611                                  refclk, NULL, &crtc_state->dpll)) {
8612                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8613                 return -EINVAL;
8614         }
8615
8616         i9xx_compute_dpll(crtc, crtc_state, NULL);
8617
8618         return 0;
8619 }
8620
8621 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8622                                   struct intel_crtc_state *crtc_state)
8623 {
8624         int refclk = 100000;
8625         const struct intel_limit *limit = &intel_limits_chv;
8626
8627         memset(&crtc_state->dpll_hw_state, 0,
8628                sizeof(crtc_state->dpll_hw_state));
8629
8630         if (!crtc_state->clock_set &&
8631             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8632                                 refclk, NULL, &crtc_state->dpll)) {
8633                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8634                 return -EINVAL;
8635         }
8636
8637         chv_compute_dpll(crtc, crtc_state);
8638
8639         return 0;
8640 }
8641
8642 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8643                                   struct intel_crtc_state *crtc_state)
8644 {
8645         int refclk = 100000;
8646         const struct intel_limit *limit = &intel_limits_vlv;
8647
8648         memset(&crtc_state->dpll_hw_state, 0,
8649                sizeof(crtc_state->dpll_hw_state));
8650
8651         if (!crtc_state->clock_set &&
8652             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8653                                 refclk, NULL, &crtc_state->dpll)) {
8654                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8655                 return -EINVAL;
8656         }
8657
8658         vlv_compute_dpll(crtc, crtc_state);
8659
8660         return 0;
8661 }
8662
8663 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8664 {
8665         if (IS_I830(dev_priv))
8666                 return false;
8667
8668         return INTEL_GEN(dev_priv) >= 4 ||
8669                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8670 }
8671
8672 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8673                                  struct intel_crtc_state *pipe_config)
8674 {
8675         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8676         u32 tmp;
8677
8678         if (!i9xx_has_pfit(dev_priv))
8679                 return;
8680
8681         tmp = I915_READ(PFIT_CONTROL);
8682         if (!(tmp & PFIT_ENABLE))
8683                 return;
8684
8685         /* Check whether the pfit is attached to our pipe. */
8686         if (INTEL_GEN(dev_priv) < 4) {
8687                 if (crtc->pipe != PIPE_B)
8688                         return;
8689         } else {
8690                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8691                         return;
8692         }
8693
8694         pipe_config->gmch_pfit.control = tmp;
8695         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8696 }
8697
8698 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8699                                struct intel_crtc_state *pipe_config)
8700 {
8701         struct drm_device *dev = crtc->base.dev;
8702         struct drm_i915_private *dev_priv = to_i915(dev);
8703         enum pipe pipe = crtc->pipe;
8704         struct dpll clock;
8705         u32 mdiv;
8706         int refclk = 100000;
8707
8708         /* In case of DSI, DPLL will not be used */
8709         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8710                 return;
8711
8712         vlv_dpio_get(dev_priv);
8713         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8714         vlv_dpio_put(dev_priv);
8715
8716         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8717         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8718         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8719         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8720         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8721
8722         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8723 }
8724
8725 static void
8726 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8727                               struct intel_initial_plane_config *plane_config)
8728 {
8729         struct drm_device *dev = crtc->base.dev;
8730         struct drm_i915_private *dev_priv = to_i915(dev);
8731         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8732         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8733         enum pipe pipe;
8734         u32 val, base, offset;
8735         int fourcc, pixel_format;
8736         unsigned int aligned_height;
8737         struct drm_framebuffer *fb;
8738         struct intel_framebuffer *intel_fb;
8739
8740         if (!plane->get_hw_state(plane, &pipe))
8741                 return;
8742
8743         WARN_ON(pipe != crtc->pipe);
8744
8745         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8746         if (!intel_fb) {
8747                 DRM_DEBUG_KMS("failed to alloc fb\n");
8748                 return;
8749         }
8750
8751         fb = &intel_fb->base;
8752
8753         fb->dev = dev;
8754
8755         val = I915_READ(DSPCNTR(i9xx_plane));
8756
8757         if (INTEL_GEN(dev_priv) >= 4) {
8758                 if (val & DISPPLANE_TILED) {
8759                         plane_config->tiling = I915_TILING_X;
8760                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8761                 }
8762
8763                 if (val & DISPPLANE_ROTATE_180)
8764                         plane_config->rotation = DRM_MODE_ROTATE_180;
8765         }
8766
8767         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8768             val & DISPPLANE_MIRROR)
8769                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8770
8771         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8772         fourcc = i9xx_format_to_fourcc(pixel_format);
8773         fb->format = drm_format_info(fourcc);
8774
8775         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8776                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8777                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8778         } else if (INTEL_GEN(dev_priv) >= 4) {
8779                 if (plane_config->tiling)
8780                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8781                 else
8782                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8783                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8784         } else {
8785                 base = I915_READ(DSPADDR(i9xx_plane));
8786         }
8787         plane_config->base = base;
8788
8789         val = I915_READ(PIPESRC(pipe));
8790         fb->width = ((val >> 16) & 0xfff) + 1;
8791         fb->height = ((val >> 0) & 0xfff) + 1;
8792
8793         val = I915_READ(DSPSTRIDE(i9xx_plane));
8794         fb->pitches[0] = val & 0xffffffc0;
8795
8796         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8797
8798         plane_config->size = fb->pitches[0] * aligned_height;
8799
8800         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8801                       crtc->base.name, plane->base.name, fb->width, fb->height,
8802                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8803                       plane_config->size);
8804
8805         plane_config->fb = intel_fb;
8806 }
8807
8808 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8809                                struct intel_crtc_state *pipe_config)
8810 {
8811         struct drm_device *dev = crtc->base.dev;
8812         struct drm_i915_private *dev_priv = to_i915(dev);
8813         enum pipe pipe = crtc->pipe;
8814         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8815         struct dpll clock;
8816         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8817         int refclk = 100000;
8818
8819         /* In case of DSI, DPLL will not be used */
8820         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8821                 return;
8822
8823         vlv_dpio_get(dev_priv);
8824         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8825         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8826         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8827         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8828         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8829         vlv_dpio_put(dev_priv);
8830
8831         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8832         clock.m2 = (pll_dw0 & 0xff) << 22;
8833         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8834                 clock.m2 |= pll_dw2 & 0x3fffff;
8835         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8836         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8837         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8838
8839         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8840 }
8841
8842 static enum intel_output_format
8843 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8844 {
8845         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8846         u32 tmp;
8847
8848         tmp = I915_READ(PIPEMISC(crtc->pipe));
8849
8850         if (tmp & PIPEMISC_YUV420_ENABLE) {
8851                 /* We support 4:2:0 in full blend mode only */
8852                 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8853
8854                 return INTEL_OUTPUT_FORMAT_YCBCR420;
8855         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8856                 return INTEL_OUTPUT_FORMAT_YCBCR444;
8857         } else {
8858                 return INTEL_OUTPUT_FORMAT_RGB;
8859         }
8860 }
8861
8862 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8863 {
8864         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8865         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8866         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8867         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8868         u32 tmp;
8869
8870         tmp = I915_READ(DSPCNTR(i9xx_plane));
8871
8872         if (tmp & DISPPLANE_GAMMA_ENABLE)
8873                 crtc_state->gamma_enable = true;
8874
8875         if (!HAS_GMCH(dev_priv) &&
8876             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8877                 crtc_state->csc_enable = true;
8878 }
8879
8880 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8881                                  struct intel_crtc_state *pipe_config)
8882 {
8883         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8884         enum intel_display_power_domain power_domain;
8885         intel_wakeref_t wakeref;
8886         u32 tmp;
8887         bool ret;
8888
8889         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8890         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8891         if (!wakeref)
8892                 return false;
8893
8894         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8895         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8896         pipe_config->shared_dpll = NULL;
8897         pipe_config->master_transcoder = INVALID_TRANSCODER;
8898
8899         ret = false;
8900
8901         tmp = I915_READ(PIPECONF(crtc->pipe));
8902         if (!(tmp & PIPECONF_ENABLE))
8903                 goto out;
8904
8905         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8906             IS_CHERRYVIEW(dev_priv)) {
8907                 switch (tmp & PIPECONF_BPC_MASK) {
8908                 case PIPECONF_6BPC:
8909                         pipe_config->pipe_bpp = 18;
8910                         break;
8911                 case PIPECONF_8BPC:
8912                         pipe_config->pipe_bpp = 24;
8913                         break;
8914                 case PIPECONF_10BPC:
8915                         pipe_config->pipe_bpp = 30;
8916                         break;
8917                 default:
8918                         break;
8919                 }
8920         }
8921
8922         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8923             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8924                 pipe_config->limited_color_range = true;
8925
8926         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8927                 PIPECONF_GAMMA_MODE_SHIFT;
8928
8929         if (IS_CHERRYVIEW(dev_priv))
8930                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8931
8932         i9xx_get_pipe_color_config(pipe_config);
8933         intel_color_get_config(pipe_config);
8934
8935         if (INTEL_GEN(dev_priv) < 4)
8936                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8937
8938         intel_get_pipe_timings(crtc, pipe_config);
8939         intel_get_pipe_src_size(crtc, pipe_config);
8940
8941         i9xx_get_pfit_config(crtc, pipe_config);
8942
8943         if (INTEL_GEN(dev_priv) >= 4) {
8944                 /* No way to read it out on pipes B and C */
8945                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8946                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8947                 else
8948                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8949                 pipe_config->pixel_multiplier =
8950                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8951                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8952                 pipe_config->dpll_hw_state.dpll_md = tmp;
8953         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8954                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8955                 tmp = I915_READ(DPLL(crtc->pipe));
8956                 pipe_config->pixel_multiplier =
8957                         ((tmp & SDVO_MULTIPLIER_MASK)
8958                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8959         } else {
8960                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8961                  * port and will be fixed up in the encoder->get_config
8962                  * function. */
8963                 pipe_config->pixel_multiplier = 1;
8964         }
8965         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8966         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8967                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8968                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8969         } else {
8970                 /* Mask out read-only status bits. */
8971                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8972                                                      DPLL_PORTC_READY_MASK |
8973                                                      DPLL_PORTB_READY_MASK);
8974         }
8975
8976         if (IS_CHERRYVIEW(dev_priv))
8977                 chv_crtc_clock_get(crtc, pipe_config);
8978         else if (IS_VALLEYVIEW(dev_priv))
8979                 vlv_crtc_clock_get(crtc, pipe_config);
8980         else
8981                 i9xx_crtc_clock_get(crtc, pipe_config);
8982
8983         /*
8984          * Normally the dotclock is filled in by the encoder .get_config()
8985          * but in case the pipe is enabled w/o any ports we need a sane
8986          * default.
8987          */
8988         pipe_config->base.adjusted_mode.crtc_clock =
8989                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8990
8991         ret = true;
8992
8993 out:
8994         intel_display_power_put(dev_priv, power_domain, wakeref);
8995
8996         return ret;
8997 }
8998
8999 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9000 {
9001         struct intel_encoder *encoder;
9002         int i;
9003         u32 val, final;
9004         bool has_lvds = false;
9005         bool has_cpu_edp = false;
9006         bool has_panel = false;
9007         bool has_ck505 = false;
9008         bool can_ssc = false;
9009         bool using_ssc_source = false;
9010
9011         /* We need to take the global config into account */
9012         for_each_intel_encoder(&dev_priv->drm, encoder) {
9013                 switch (encoder->type) {
9014                 case INTEL_OUTPUT_LVDS:
9015                         has_panel = true;
9016                         has_lvds = true;
9017                         break;
9018                 case INTEL_OUTPUT_EDP:
9019                         has_panel = true;
9020                         if (encoder->port == PORT_A)
9021                                 has_cpu_edp = true;
9022                         break;
9023                 default:
9024                         break;
9025                 }
9026         }
9027
9028         if (HAS_PCH_IBX(dev_priv)) {
9029                 has_ck505 = dev_priv->vbt.display_clock_mode;
9030                 can_ssc = has_ck505;
9031         } else {
9032                 has_ck505 = false;
9033                 can_ssc = true;
9034         }
9035
9036         /* Check if any DPLLs are using the SSC source */
9037         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9038                 u32 temp = I915_READ(PCH_DPLL(i));
9039
9040                 if (!(temp & DPLL_VCO_ENABLE))
9041                         continue;
9042
9043                 if ((temp & PLL_REF_INPUT_MASK) ==
9044                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9045                         using_ssc_source = true;
9046                         break;
9047                 }
9048         }
9049
9050         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9051                       has_panel, has_lvds, has_ck505, using_ssc_source);
9052
9053         /* Ironlake: try to setup display ref clock before DPLL
9054          * enabling. This is only under driver's control after
9055          * PCH B stepping, previous chipset stepping should be
9056          * ignoring this setting.
9057          */
9058         val = I915_READ(PCH_DREF_CONTROL);
9059
9060         /* As we must carefully and slowly disable/enable each source in turn,
9061          * compute the final state we want first and check if we need to
9062          * make any changes at all.
9063          */
9064         final = val;
9065         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9066         if (has_ck505)
9067                 final |= DREF_NONSPREAD_CK505_ENABLE;
9068         else
9069                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9070
9071         final &= ~DREF_SSC_SOURCE_MASK;
9072         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9073         final &= ~DREF_SSC1_ENABLE;
9074
9075         if (has_panel) {
9076                 final |= DREF_SSC_SOURCE_ENABLE;
9077
9078                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9079                         final |= DREF_SSC1_ENABLE;
9080
9081                 if (has_cpu_edp) {
9082                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9083                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9084                         else
9085                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9086                 } else
9087                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9088         } else if (using_ssc_source) {
9089                 final |= DREF_SSC_SOURCE_ENABLE;
9090                 final |= DREF_SSC1_ENABLE;
9091         }
9092
9093         if (final == val)
9094                 return;
9095
9096         /* Always enable nonspread source */
9097         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9098
9099         if (has_ck505)
9100                 val |= DREF_NONSPREAD_CK505_ENABLE;
9101         else
9102                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9103
9104         if (has_panel) {
9105                 val &= ~DREF_SSC_SOURCE_MASK;
9106                 val |= DREF_SSC_SOURCE_ENABLE;
9107
9108                 /* SSC must be turned on before enabling the CPU output  */
9109                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9110                         DRM_DEBUG_KMS("Using SSC on panel\n");
9111                         val |= DREF_SSC1_ENABLE;
9112                 } else
9113                         val &= ~DREF_SSC1_ENABLE;
9114
9115                 /* Get SSC going before enabling the outputs */
9116                 I915_WRITE(PCH_DREF_CONTROL, val);
9117                 POSTING_READ(PCH_DREF_CONTROL);
9118                 udelay(200);
9119
9120                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9121
9122                 /* Enable CPU source on CPU attached eDP */
9123                 if (has_cpu_edp) {
9124                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9125                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9126                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9127                         } else
9128                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9129                 } else
9130                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9131
9132                 I915_WRITE(PCH_DREF_CONTROL, val);
9133                 POSTING_READ(PCH_DREF_CONTROL);
9134                 udelay(200);
9135         } else {
9136                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9137
9138                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9139
9140                 /* Turn off CPU output */
9141                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9142
9143                 I915_WRITE(PCH_DREF_CONTROL, val);
9144                 POSTING_READ(PCH_DREF_CONTROL);
9145                 udelay(200);
9146
9147                 if (!using_ssc_source) {
9148                         DRM_DEBUG_KMS("Disabling SSC source\n");
9149
9150                         /* Turn off the SSC source */
9151                         val &= ~DREF_SSC_SOURCE_MASK;
9152                         val |= DREF_SSC_SOURCE_DISABLE;
9153
9154                         /* Turn off SSC1 */
9155                         val &= ~DREF_SSC1_ENABLE;
9156
9157                         I915_WRITE(PCH_DREF_CONTROL, val);
9158                         POSTING_READ(PCH_DREF_CONTROL);
9159                         udelay(200);
9160                 }
9161         }
9162
9163         BUG_ON(val != final);
9164 }
9165
9166 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9167 {
9168         u32 tmp;
9169
9170         tmp = I915_READ(SOUTH_CHICKEN2);
9171         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9172         I915_WRITE(SOUTH_CHICKEN2, tmp);
9173
9174         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9175                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9176                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9177
9178         tmp = I915_READ(SOUTH_CHICKEN2);
9179         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9180         I915_WRITE(SOUTH_CHICKEN2, tmp);
9181
9182         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9183                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9184                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9185 }
9186
9187 /* WaMPhyProgramming:hsw */
9188 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9189 {
9190         u32 tmp;
9191
9192         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9193         tmp &= ~(0xFF << 24);
9194         tmp |= (0x12 << 24);
9195         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9196
9197         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9198         tmp |= (1 << 11);
9199         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9200
9201         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9202         tmp |= (1 << 11);
9203         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9204
9205         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9206         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9207         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9208
9209         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9210         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9211         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9212
9213         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9214         tmp &= ~(7 << 13);
9215         tmp |= (5 << 13);
9216         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9217
9218         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9219         tmp &= ~(7 << 13);
9220         tmp |= (5 << 13);
9221         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9222
9223         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9224         tmp &= ~0xFF;
9225         tmp |= 0x1C;
9226         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9227
9228         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9229         tmp &= ~0xFF;
9230         tmp |= 0x1C;
9231         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9232
9233         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9234         tmp &= ~(0xFF << 16);
9235         tmp |= (0x1C << 16);
9236         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9237
9238         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9239         tmp &= ~(0xFF << 16);
9240         tmp |= (0x1C << 16);
9241         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9242
9243         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9244         tmp |= (1 << 27);
9245         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9246
9247         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9248         tmp |= (1 << 27);
9249         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9250
9251         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9252         tmp &= ~(0xF << 28);
9253         tmp |= (4 << 28);
9254         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9255
9256         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9257         tmp &= ~(0xF << 28);
9258         tmp |= (4 << 28);
9259         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9260 }
9261
9262 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9263  * Programming" based on the parameters passed:
9264  * - Sequence to enable CLKOUT_DP
9265  * - Sequence to enable CLKOUT_DP without spread
9266  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9267  */
9268 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9269                                  bool with_spread, bool with_fdi)
9270 {
9271         u32 reg, tmp;
9272
9273         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9274                 with_spread = true;
9275         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9276             with_fdi, "LP PCH doesn't have FDI\n"))
9277                 with_fdi = false;
9278
9279         mutex_lock(&dev_priv->sb_lock);
9280
9281         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9282         tmp &= ~SBI_SSCCTL_DISABLE;
9283         tmp |= SBI_SSCCTL_PATHALT;
9284         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9285
9286         udelay(24);
9287
9288         if (with_spread) {
9289                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9290                 tmp &= ~SBI_SSCCTL_PATHALT;
9291                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9292
9293                 if (with_fdi) {
9294                         lpt_reset_fdi_mphy(dev_priv);
9295                         lpt_program_fdi_mphy(dev_priv);
9296                 }
9297         }
9298
9299         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9300         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9301         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9302         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9303
9304         mutex_unlock(&dev_priv->sb_lock);
9305 }
9306
9307 /* Sequence to disable CLKOUT_DP */
9308 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9309 {
9310         u32 reg, tmp;
9311
9312         mutex_lock(&dev_priv->sb_lock);
9313
9314         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9315         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9316         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9317         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9318
9319         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9320         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9321                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9322                         tmp |= SBI_SSCCTL_PATHALT;
9323                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9324                         udelay(32);
9325                 }
9326                 tmp |= SBI_SSCCTL_DISABLE;
9327                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9328         }
9329
9330         mutex_unlock(&dev_priv->sb_lock);
9331 }
9332
9333 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9334
9335 static const u16 sscdivintphase[] = {
9336         [BEND_IDX( 50)] = 0x3B23,
9337         [BEND_IDX( 45)] = 0x3B23,
9338         [BEND_IDX( 40)] = 0x3C23,
9339         [BEND_IDX( 35)] = 0x3C23,
9340         [BEND_IDX( 30)] = 0x3D23,
9341         [BEND_IDX( 25)] = 0x3D23,
9342         [BEND_IDX( 20)] = 0x3E23,
9343         [BEND_IDX( 15)] = 0x3E23,
9344         [BEND_IDX( 10)] = 0x3F23,
9345         [BEND_IDX(  5)] = 0x3F23,
9346         [BEND_IDX(  0)] = 0x0025,
9347         [BEND_IDX( -5)] = 0x0025,
9348         [BEND_IDX(-10)] = 0x0125,
9349         [BEND_IDX(-15)] = 0x0125,
9350         [BEND_IDX(-20)] = 0x0225,
9351         [BEND_IDX(-25)] = 0x0225,
9352         [BEND_IDX(-30)] = 0x0325,
9353         [BEND_IDX(-35)] = 0x0325,
9354         [BEND_IDX(-40)] = 0x0425,
9355         [BEND_IDX(-45)] = 0x0425,
9356         [BEND_IDX(-50)] = 0x0525,
9357 };
9358
9359 /*
9360  * Bend CLKOUT_DP
9361  * steps -50 to 50 inclusive, in steps of 5
9362  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9363  * change in clock period = -(steps / 10) * 5.787 ps
9364  */
9365 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9366 {
9367         u32 tmp;
9368         int idx = BEND_IDX(steps);
9369
9370         if (WARN_ON(steps % 5 != 0))
9371                 return;
9372
9373         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9374                 return;
9375
9376         mutex_lock(&dev_priv->sb_lock);
9377
9378         if (steps % 10 != 0)
9379                 tmp = 0xAAAAAAAB;
9380         else
9381                 tmp = 0x00000000;
9382         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9383
9384         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9385         tmp &= 0xffff0000;
9386         tmp |= sscdivintphase[idx];
9387         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9388
9389         mutex_unlock(&dev_priv->sb_lock);
9390 }
9391
9392 #undef BEND_IDX
9393
9394 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9395 {
9396         u32 fuse_strap = I915_READ(FUSE_STRAP);
9397         u32 ctl = I915_READ(SPLL_CTL);
9398
9399         if ((ctl & SPLL_PLL_ENABLE) == 0)
9400                 return false;
9401
9402         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9403             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9404                 return true;
9405
9406         if (IS_BROADWELL(dev_priv) &&
9407             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9408                 return true;
9409
9410         return false;
9411 }
9412
9413 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9414                                enum intel_dpll_id id)
9415 {
9416         u32 fuse_strap = I915_READ(FUSE_STRAP);
9417         u32 ctl = I915_READ(WRPLL_CTL(id));
9418
9419         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9420                 return false;
9421
9422         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9423                 return true;
9424
9425         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9426             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9427             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9428                 return true;
9429
9430         return false;
9431 }
9432
9433 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9434 {
9435         struct intel_encoder *encoder;
9436         bool has_fdi = false;
9437
9438         for_each_intel_encoder(&dev_priv->drm, encoder) {
9439                 switch (encoder->type) {
9440                 case INTEL_OUTPUT_ANALOG:
9441                         has_fdi = true;
9442                         break;
9443                 default:
9444                         break;
9445                 }
9446         }
9447
9448         /*
9449          * The BIOS may have decided to use the PCH SSC
9450          * reference so we must not disable it until the
9451          * relevant PLLs have stopped relying on it. We'll
9452          * just leave the PCH SSC reference enabled in case
9453          * any active PLL is using it. It will get disabled
9454          * after runtime suspend if we don't have FDI.
9455          *
9456          * TODO: Move the whole reference clock handling
9457          * to the modeset sequence proper so that we can
9458          * actually enable/disable/reconfigure these things
9459          * safely. To do that we need to introduce a real
9460          * clock hierarchy. That would also allow us to do
9461          * clock bending finally.
9462          */
9463         dev_priv->pch_ssc_use = 0;
9464
9465         if (spll_uses_pch_ssc(dev_priv)) {
9466                 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9467                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9468         }
9469
9470         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9471                 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9472                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9473         }
9474
9475         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9476                 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9477                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9478         }
9479
9480         if (dev_priv->pch_ssc_use)
9481                 return;
9482
9483         if (has_fdi) {
9484                 lpt_bend_clkout_dp(dev_priv, 0);
9485                 lpt_enable_clkout_dp(dev_priv, true, true);
9486         } else {
9487                 lpt_disable_clkout_dp(dev_priv);
9488         }
9489 }
9490
9491 /*
9492  * Initialize reference clocks when the driver loads
9493  */
9494 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9495 {
9496         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9497                 ironlake_init_pch_refclk(dev_priv);
9498         else if (HAS_PCH_LPT(dev_priv))
9499                 lpt_init_pch_refclk(dev_priv);
9500 }
9501
9502 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9503 {
9504         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9505         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9506         enum pipe pipe = crtc->pipe;
9507         u32 val;
9508
9509         val = 0;
9510
9511         switch (crtc_state->pipe_bpp) {
9512         case 18:
9513                 val |= PIPECONF_6BPC;
9514                 break;
9515         case 24:
9516                 val |= PIPECONF_8BPC;
9517                 break;
9518         case 30:
9519                 val |= PIPECONF_10BPC;
9520                 break;
9521         case 36:
9522                 val |= PIPECONF_12BPC;
9523                 break;
9524         default:
9525                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9526                 BUG();
9527         }
9528
9529         if (crtc_state->dither)
9530                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9531
9532         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9533                 val |= PIPECONF_INTERLACED_ILK;
9534         else
9535                 val |= PIPECONF_PROGRESSIVE;
9536
9537         /*
9538          * This would end up with an odd purple hue over
9539          * the entire display. Make sure we don't do it.
9540          */
9541         WARN_ON(crtc_state->limited_color_range &&
9542                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9543
9544         if (crtc_state->limited_color_range)
9545                 val |= PIPECONF_COLOR_RANGE_SELECT;
9546
9547         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9548                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9549
9550         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9551
9552         I915_WRITE(PIPECONF(pipe), val);
9553         POSTING_READ(PIPECONF(pipe));
9554 }
9555
9556 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9557 {
9558         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9559         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9560         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9561         u32 val = 0;
9562
9563         if (IS_HASWELL(dev_priv) && crtc_state->dither)
9564                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9565
9566         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9567                 val |= PIPECONF_INTERLACED_ILK;
9568         else
9569                 val |= PIPECONF_PROGRESSIVE;
9570
9571         if (IS_HASWELL(dev_priv) &&
9572             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9573                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9574
9575         I915_WRITE(PIPECONF(cpu_transcoder), val);
9576         POSTING_READ(PIPECONF(cpu_transcoder));
9577 }
9578
9579 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9580 {
9581         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9582         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9583         u32 val = 0;
9584
9585         switch (crtc_state->pipe_bpp) {
9586         case 18:
9587                 val |= PIPEMISC_DITHER_6_BPC;
9588                 break;
9589         case 24:
9590                 val |= PIPEMISC_DITHER_8_BPC;
9591                 break;
9592         case 30:
9593                 val |= PIPEMISC_DITHER_10_BPC;
9594                 break;
9595         case 36:
9596                 val |= PIPEMISC_DITHER_12_BPC;
9597                 break;
9598         default:
9599                 MISSING_CASE(crtc_state->pipe_bpp);
9600                 break;
9601         }
9602
9603         if (crtc_state->dither)
9604                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9605
9606         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9607             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9608                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9609
9610         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9611                 val |= PIPEMISC_YUV420_ENABLE |
9612                         PIPEMISC_YUV420_MODE_FULL_BLEND;
9613
9614         if (INTEL_GEN(dev_priv) >= 11 &&
9615             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9616                                            BIT(PLANE_CURSOR))) == 0)
9617                 val |= PIPEMISC_HDR_MODE_PRECISION;
9618
9619         I915_WRITE(PIPEMISC(crtc->pipe), val);
9620 }
9621
9622 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9623 {
9624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9625         u32 tmp;
9626
9627         tmp = I915_READ(PIPEMISC(crtc->pipe));
9628
9629         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9630         case PIPEMISC_DITHER_6_BPC:
9631                 return 18;
9632         case PIPEMISC_DITHER_8_BPC:
9633                 return 24;
9634         case PIPEMISC_DITHER_10_BPC:
9635                 return 30;
9636         case PIPEMISC_DITHER_12_BPC:
9637                 return 36;
9638         default:
9639                 MISSING_CASE(tmp);
9640                 return 0;
9641         }
9642 }
9643
9644 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9645 {
9646         /*
9647          * Account for spread spectrum to avoid
9648          * oversubscribing the link. Max center spread
9649          * is 2.5%; use 5% for safety's sake.
9650          */
9651         u32 bps = target_clock * bpp * 21 / 20;
9652         return DIV_ROUND_UP(bps, link_bw * 8);
9653 }
9654
9655 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9656 {
9657         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9658 }
9659
9660 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9661                                   struct intel_crtc_state *crtc_state,
9662                                   struct dpll *reduced_clock)
9663 {
9664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9665         u32 dpll, fp, fp2;
9666         int factor;
9667
9668         /* Enable autotuning of the PLL clock (if permissible) */
9669         factor = 21;
9670         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9671                 if ((intel_panel_use_ssc(dev_priv) &&
9672                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9673                     (HAS_PCH_IBX(dev_priv) &&
9674                      intel_is_dual_link_lvds(dev_priv)))
9675                         factor = 25;
9676         } else if (crtc_state->sdvo_tv_clock) {
9677                 factor = 20;
9678         }
9679
9680         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9681
9682         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9683                 fp |= FP_CB_TUNE;
9684
9685         if (reduced_clock) {
9686                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9687
9688                 if (reduced_clock->m < factor * reduced_clock->n)
9689                         fp2 |= FP_CB_TUNE;
9690         } else {
9691                 fp2 = fp;
9692         }
9693
9694         dpll = 0;
9695
9696         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9697                 dpll |= DPLLB_MODE_LVDS;
9698         else
9699                 dpll |= DPLLB_MODE_DAC_SERIAL;
9700
9701         dpll |= (crtc_state->pixel_multiplier - 1)
9702                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9703
9704         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9705             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9706                 dpll |= DPLL_SDVO_HIGH_SPEED;
9707
9708         if (intel_crtc_has_dp_encoder(crtc_state))
9709                 dpll |= DPLL_SDVO_HIGH_SPEED;
9710
9711         /*
9712          * The high speed IO clock is only really required for
9713          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9714          * possible to share the DPLL between CRT and HDMI. Enabling
9715          * the clock needlessly does no real harm, except use up a
9716          * bit of power potentially.
9717          *
9718          * We'll limit this to IVB with 3 pipes, since it has only two
9719          * DPLLs and so DPLL sharing is the only way to get three pipes
9720          * driving PCH ports at the same time. On SNB we could do this,
9721          * and potentially avoid enabling the second DPLL, but it's not
9722          * clear if it''s a win or loss power wise. No point in doing
9723          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9724          */
9725         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9726             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9727                 dpll |= DPLL_SDVO_HIGH_SPEED;
9728
9729         /* compute bitmask from p1 value */
9730         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9731         /* also FPA1 */
9732         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9733
9734         switch (crtc_state->dpll.p2) {
9735         case 5:
9736                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9737                 break;
9738         case 7:
9739                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9740                 break;
9741         case 10:
9742                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9743                 break;
9744         case 14:
9745                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9746                 break;
9747         }
9748
9749         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9750             intel_panel_use_ssc(dev_priv))
9751                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9752         else
9753                 dpll |= PLL_REF_INPUT_DREFCLK;
9754
9755         dpll |= DPLL_VCO_ENABLE;
9756
9757         crtc_state->dpll_hw_state.dpll = dpll;
9758         crtc_state->dpll_hw_state.fp0 = fp;
9759         crtc_state->dpll_hw_state.fp1 = fp2;
9760 }
9761
9762 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9763                                        struct intel_crtc_state *crtc_state)
9764 {
9765         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9766         struct intel_atomic_state *state =
9767                 to_intel_atomic_state(crtc_state->base.state);
9768         const struct intel_limit *limit;
9769         int refclk = 120000;
9770
9771         memset(&crtc_state->dpll_hw_state, 0,
9772                sizeof(crtc_state->dpll_hw_state));
9773
9774         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9775         if (!crtc_state->has_pch_encoder)
9776                 return 0;
9777
9778         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9779                 if (intel_panel_use_ssc(dev_priv)) {
9780                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9781                                       dev_priv->vbt.lvds_ssc_freq);
9782                         refclk = dev_priv->vbt.lvds_ssc_freq;
9783                 }
9784
9785                 if (intel_is_dual_link_lvds(dev_priv)) {
9786                         if (refclk == 100000)
9787                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9788                         else
9789                                 limit = &intel_limits_ironlake_dual_lvds;
9790                 } else {
9791                         if (refclk == 100000)
9792                                 limit = &intel_limits_ironlake_single_lvds_100m;
9793                         else
9794                                 limit = &intel_limits_ironlake_single_lvds;
9795                 }
9796         } else {
9797                 limit = &intel_limits_ironlake_dac;
9798         }
9799
9800         if (!crtc_state->clock_set &&
9801             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9802                                 refclk, NULL, &crtc_state->dpll)) {
9803                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9804                 return -EINVAL;
9805         }
9806
9807         ironlake_compute_dpll(crtc, crtc_state, NULL);
9808
9809         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9810                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9811                               pipe_name(crtc->pipe));
9812                 return -EINVAL;
9813         }
9814
9815         return 0;
9816 }
9817
9818 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9819                                          struct intel_link_m_n *m_n)
9820 {
9821         struct drm_device *dev = crtc->base.dev;
9822         struct drm_i915_private *dev_priv = to_i915(dev);
9823         enum pipe pipe = crtc->pipe;
9824
9825         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9826         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9827         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9828                 & ~TU_SIZE_MASK;
9829         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9830         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9831                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9832 }
9833
9834 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9835                                          enum transcoder transcoder,
9836                                          struct intel_link_m_n *m_n,
9837                                          struct intel_link_m_n *m2_n2)
9838 {
9839         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9840         enum pipe pipe = crtc->pipe;
9841
9842         if (INTEL_GEN(dev_priv) >= 5) {
9843                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9844                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9845                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9846                         & ~TU_SIZE_MASK;
9847                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9848                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9849                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9850
9851                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9852                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9853                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9854                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9855                                         & ~TU_SIZE_MASK;
9856                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9857                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9858                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9859                 }
9860         } else {
9861                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9862                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9863                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9864                         & ~TU_SIZE_MASK;
9865                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9866                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9867                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9868         }
9869 }
9870
9871 void intel_dp_get_m_n(struct intel_crtc *crtc,
9872                       struct intel_crtc_state *pipe_config)
9873 {
9874         if (pipe_config->has_pch_encoder)
9875                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9876         else
9877                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9878                                              &pipe_config->dp_m_n,
9879                                              &pipe_config->dp_m2_n2);
9880 }
9881
9882 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9883                                         struct intel_crtc_state *pipe_config)
9884 {
9885         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9886                                      &pipe_config->fdi_m_n, NULL);
9887 }
9888
9889 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9890                                     struct intel_crtc_state *pipe_config)
9891 {
9892         struct drm_device *dev = crtc->base.dev;
9893         struct drm_i915_private *dev_priv = to_i915(dev);
9894         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9895         u32 ps_ctrl = 0;
9896         int id = -1;
9897         int i;
9898
9899         /* find scaler attached to this pipe */
9900         for (i = 0; i < crtc->num_scalers; i++) {
9901                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9902                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9903                         id = i;
9904                         pipe_config->pch_pfit.enabled = true;
9905                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9906                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9907                         scaler_state->scalers[i].in_use = true;
9908                         break;
9909                 }
9910         }
9911
9912         scaler_state->scaler_id = id;
9913         if (id >= 0) {
9914                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9915         } else {
9916                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9917         }
9918 }
9919
9920 static void
9921 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9922                                  struct intel_initial_plane_config *plane_config)
9923 {
9924         struct drm_device *dev = crtc->base.dev;
9925         struct drm_i915_private *dev_priv = to_i915(dev);
9926         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9927         enum plane_id plane_id = plane->id;
9928         enum pipe pipe;
9929         u32 val, base, offset, stride_mult, tiling, alpha;
9930         int fourcc, pixel_format;
9931         unsigned int aligned_height;
9932         struct drm_framebuffer *fb;
9933         struct intel_framebuffer *intel_fb;
9934
9935         if (!plane->get_hw_state(plane, &pipe))
9936                 return;
9937
9938         WARN_ON(pipe != crtc->pipe);
9939
9940         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9941         if (!intel_fb) {
9942                 DRM_DEBUG_KMS("failed to alloc fb\n");
9943                 return;
9944         }
9945
9946         fb = &intel_fb->base;
9947
9948         fb->dev = dev;
9949
9950         val = I915_READ(PLANE_CTL(pipe, plane_id));
9951
9952         if (INTEL_GEN(dev_priv) >= 11)
9953                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9954         else
9955                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9956
9957         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9958                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9959                 alpha &= PLANE_COLOR_ALPHA_MASK;
9960         } else {
9961                 alpha = val & PLANE_CTL_ALPHA_MASK;
9962         }
9963
9964         fourcc = skl_format_to_fourcc(pixel_format,
9965                                       val & PLANE_CTL_ORDER_RGBX, alpha);
9966         fb->format = drm_format_info(fourcc);
9967
9968         tiling = val & PLANE_CTL_TILED_MASK;
9969         switch (tiling) {
9970         case PLANE_CTL_TILED_LINEAR:
9971                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9972                 break;
9973         case PLANE_CTL_TILED_X:
9974                 plane_config->tiling = I915_TILING_X;
9975                 fb->modifier = I915_FORMAT_MOD_X_TILED;
9976                 break;
9977         case PLANE_CTL_TILED_Y:
9978                 plane_config->tiling = I915_TILING_Y;
9979                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9980                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
9981                 else
9982                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
9983                 break;
9984         case PLANE_CTL_TILED_YF:
9985                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9986                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
9987                 else
9988                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9989                 break;
9990         default:
9991                 MISSING_CASE(tiling);
9992                 goto error;
9993         }
9994
9995         /*
9996          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9997          * while i915 HW rotation is clockwise, thats why this swapping.
9998          */
9999         switch (val & PLANE_CTL_ROTATE_MASK) {
10000         case PLANE_CTL_ROTATE_0:
10001                 plane_config->rotation = DRM_MODE_ROTATE_0;
10002                 break;
10003         case PLANE_CTL_ROTATE_90:
10004                 plane_config->rotation = DRM_MODE_ROTATE_270;
10005                 break;
10006         case PLANE_CTL_ROTATE_180:
10007                 plane_config->rotation = DRM_MODE_ROTATE_180;
10008                 break;
10009         case PLANE_CTL_ROTATE_270:
10010                 plane_config->rotation = DRM_MODE_ROTATE_90;
10011                 break;
10012         }
10013
10014         if (INTEL_GEN(dev_priv) >= 10 &&
10015             val & PLANE_CTL_FLIP_HORIZONTAL)
10016                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10017
10018         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10019         plane_config->base = base;
10020
10021         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10022
10023         val = I915_READ(PLANE_SIZE(pipe, plane_id));
10024         fb->height = ((val >> 16) & 0xffff) + 1;
10025         fb->width = ((val >> 0) & 0xffff) + 1;
10026
10027         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10028         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10029         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10030
10031         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10032
10033         plane_config->size = fb->pitches[0] * aligned_height;
10034
10035         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10036                       crtc->base.name, plane->base.name, fb->width, fb->height,
10037                       fb->format->cpp[0] * 8, base, fb->pitches[0],
10038                       plane_config->size);
10039
10040         plane_config->fb = intel_fb;
10041         return;
10042
10043 error:
10044         kfree(intel_fb);
10045 }
10046
10047 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10048                                      struct intel_crtc_state *pipe_config)
10049 {
10050         struct drm_device *dev = crtc->base.dev;
10051         struct drm_i915_private *dev_priv = to_i915(dev);
10052         u32 tmp;
10053
10054         tmp = I915_READ(PF_CTL(crtc->pipe));
10055
10056         if (tmp & PF_ENABLE) {
10057                 pipe_config->pch_pfit.enabled = true;
10058                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10059                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10060
10061                 /* We currently do not free assignements of panel fitters on
10062                  * ivb/hsw (since we don't use the higher upscaling modes which
10063                  * differentiates them) so just WARN about this case for now. */
10064                 if (IS_GEN(dev_priv, 7)) {
10065                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10066                                 PF_PIPE_SEL_IVB(crtc->pipe));
10067                 }
10068         }
10069 }
10070
10071 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10072                                      struct intel_crtc_state *pipe_config)
10073 {
10074         struct drm_device *dev = crtc->base.dev;
10075         struct drm_i915_private *dev_priv = to_i915(dev);
10076         enum intel_display_power_domain power_domain;
10077         intel_wakeref_t wakeref;
10078         u32 tmp;
10079         bool ret;
10080
10081         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10082         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10083         if (!wakeref)
10084                 return false;
10085
10086         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10087         pipe_config->shared_dpll = NULL;
10088         pipe_config->master_transcoder = INVALID_TRANSCODER;
10089
10090         ret = false;
10091         tmp = I915_READ(PIPECONF(crtc->pipe));
10092         if (!(tmp & PIPECONF_ENABLE))
10093                 goto out;
10094
10095         switch (tmp & PIPECONF_BPC_MASK) {
10096         case PIPECONF_6BPC:
10097                 pipe_config->pipe_bpp = 18;
10098                 break;
10099         case PIPECONF_8BPC:
10100                 pipe_config->pipe_bpp = 24;
10101                 break;
10102         case PIPECONF_10BPC:
10103                 pipe_config->pipe_bpp = 30;
10104                 break;
10105         case PIPECONF_12BPC:
10106                 pipe_config->pipe_bpp = 36;
10107                 break;
10108         default:
10109                 break;
10110         }
10111
10112         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10113                 pipe_config->limited_color_range = true;
10114
10115         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10116         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10117         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10118                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10119                 break;
10120         default:
10121                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10122                 break;
10123         }
10124
10125         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10126                 PIPECONF_GAMMA_MODE_SHIFT;
10127
10128         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10129
10130         i9xx_get_pipe_color_config(pipe_config);
10131         intel_color_get_config(pipe_config);
10132
10133         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10134                 struct intel_shared_dpll *pll;
10135                 enum intel_dpll_id pll_id;
10136
10137                 pipe_config->has_pch_encoder = true;
10138
10139                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10140                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10141                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10142
10143                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10144
10145                 if (HAS_PCH_IBX(dev_priv)) {
10146                         /*
10147                          * The pipe->pch transcoder and pch transcoder->pll
10148                          * mapping is fixed.
10149                          */
10150                         pll_id = (enum intel_dpll_id) crtc->pipe;
10151                 } else {
10152                         tmp = I915_READ(PCH_DPLL_SEL);
10153                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10154                                 pll_id = DPLL_ID_PCH_PLL_B;
10155                         else
10156                                 pll_id= DPLL_ID_PCH_PLL_A;
10157                 }
10158
10159                 pipe_config->shared_dpll =
10160                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10161                 pll = pipe_config->shared_dpll;
10162
10163                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10164                                                 &pipe_config->dpll_hw_state));
10165
10166                 tmp = pipe_config->dpll_hw_state.dpll;
10167                 pipe_config->pixel_multiplier =
10168                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10169                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10170
10171                 ironlake_pch_clock_get(crtc, pipe_config);
10172         } else {
10173                 pipe_config->pixel_multiplier = 1;
10174         }
10175
10176         intel_get_pipe_timings(crtc, pipe_config);
10177         intel_get_pipe_src_size(crtc, pipe_config);
10178
10179         ironlake_get_pfit_config(crtc, pipe_config);
10180
10181         ret = true;
10182
10183 out:
10184         intel_display_power_put(dev_priv, power_domain, wakeref);
10185
10186         return ret;
10187 }
10188 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10189                                       struct intel_crtc_state *crtc_state)
10190 {
10191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10192         struct intel_atomic_state *state =
10193                 to_intel_atomic_state(crtc_state->base.state);
10194
10195         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10196             INTEL_GEN(dev_priv) >= 11) {
10197                 struct intel_encoder *encoder =
10198                         intel_get_crtc_new_encoder(state, crtc_state);
10199
10200                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10201                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10202                                       pipe_name(crtc->pipe));
10203                         return -EINVAL;
10204                 }
10205         }
10206
10207         return 0;
10208 }
10209
10210 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10211                                    enum port port,
10212                                    struct intel_crtc_state *pipe_config)
10213 {
10214         enum intel_dpll_id id;
10215         u32 temp;
10216
10217         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10218         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10219
10220         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10221                 return;
10222
10223         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10224 }
10225
10226 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10227                                 enum port port,
10228                                 struct intel_crtc_state *pipe_config)
10229 {
10230         enum phy phy = intel_port_to_phy(dev_priv, port);
10231         enum icl_port_dpll_id port_dpll_id;
10232         enum intel_dpll_id id;
10233         u32 temp;
10234
10235         if (intel_phy_is_combo(dev_priv, phy)) {
10236                 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10237                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10238                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10239                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10240         } else if (intel_phy_is_tc(dev_priv, phy)) {
10241                 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10242
10243                 if (clk_sel == DDI_CLK_SEL_MG) {
10244                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10245                                                                     port));
10246                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10247                 } else {
10248                         WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10249                         id = DPLL_ID_ICL_TBTPLL;
10250                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10251                 }
10252         } else {
10253                 WARN(1, "Invalid port %x\n", port);
10254                 return;
10255         }
10256
10257         pipe_config->icl_port_dplls[port_dpll_id].pll =
10258                 intel_get_shared_dpll_by_id(dev_priv, id);
10259
10260         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10261 }
10262
10263 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10264                                 enum port port,
10265                                 struct intel_crtc_state *pipe_config)
10266 {
10267         enum intel_dpll_id id;
10268
10269         switch (port) {
10270         case PORT_A:
10271                 id = DPLL_ID_SKL_DPLL0;
10272                 break;
10273         case PORT_B:
10274                 id = DPLL_ID_SKL_DPLL1;
10275                 break;
10276         case PORT_C:
10277                 id = DPLL_ID_SKL_DPLL2;
10278                 break;
10279         default:
10280                 DRM_ERROR("Incorrect port type\n");
10281                 return;
10282         }
10283
10284         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10285 }
10286
10287 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10288                                 enum port port,
10289                                 struct intel_crtc_state *pipe_config)
10290 {
10291         enum intel_dpll_id id;
10292         u32 temp;
10293
10294         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10295         id = temp >> (port * 3 + 1);
10296
10297         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10298                 return;
10299
10300         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10301 }
10302
10303 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10304                                 enum port port,
10305                                 struct intel_crtc_state *pipe_config)
10306 {
10307         enum intel_dpll_id id;
10308         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10309
10310         switch (ddi_pll_sel) {
10311         case PORT_CLK_SEL_WRPLL1:
10312                 id = DPLL_ID_WRPLL1;
10313                 break;
10314         case PORT_CLK_SEL_WRPLL2:
10315                 id = DPLL_ID_WRPLL2;
10316                 break;
10317         case PORT_CLK_SEL_SPLL:
10318                 id = DPLL_ID_SPLL;
10319                 break;
10320         case PORT_CLK_SEL_LCPLL_810:
10321                 id = DPLL_ID_LCPLL_810;
10322                 break;
10323         case PORT_CLK_SEL_LCPLL_1350:
10324                 id = DPLL_ID_LCPLL_1350;
10325                 break;
10326         case PORT_CLK_SEL_LCPLL_2700:
10327                 id = DPLL_ID_LCPLL_2700;
10328                 break;
10329         default:
10330                 MISSING_CASE(ddi_pll_sel);
10331                 /* fall through */
10332         case PORT_CLK_SEL_NONE:
10333                 return;
10334         }
10335
10336         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10337 }
10338
10339 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10340                                      struct intel_crtc_state *pipe_config,
10341                                      u64 *power_domain_mask,
10342                                      intel_wakeref_t *wakerefs)
10343 {
10344         struct drm_device *dev = crtc->base.dev;
10345         struct drm_i915_private *dev_priv = to_i915(dev);
10346         enum intel_display_power_domain power_domain;
10347         unsigned long panel_transcoder_mask = 0;
10348         unsigned long enabled_panel_transcoders = 0;
10349         enum transcoder panel_transcoder;
10350         intel_wakeref_t wf;
10351         u32 tmp;
10352
10353         if (INTEL_GEN(dev_priv) >= 11)
10354                 panel_transcoder_mask |=
10355                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10356
10357         if (HAS_TRANSCODER_EDP(dev_priv))
10358                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10359
10360         /*
10361          * The pipe->transcoder mapping is fixed with the exception of the eDP
10362          * and DSI transcoders handled below.
10363          */
10364         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10365
10366         /*
10367          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10368          * consistency and less surprising code; it's in always on power).
10369          */
10370         for_each_set_bit(panel_transcoder,
10371                          &panel_transcoder_mask,
10372                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10373                 bool force_thru = false;
10374                 enum pipe trans_pipe;
10375
10376                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10377                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10378                         continue;
10379
10380                 /*
10381                  * Log all enabled ones, only use the first one.
10382                  *
10383                  * FIXME: This won't work for two separate DSI displays.
10384                  */
10385                 enabled_panel_transcoders |= BIT(panel_transcoder);
10386                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10387                         continue;
10388
10389                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10390                 default:
10391                         WARN(1, "unknown pipe linked to transcoder %s\n",
10392                              transcoder_name(panel_transcoder));
10393                         /* fall through */
10394                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10395                         force_thru = true;
10396                         /* fall through */
10397                 case TRANS_DDI_EDP_INPUT_A_ON:
10398                         trans_pipe = PIPE_A;
10399                         break;
10400                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10401                         trans_pipe = PIPE_B;
10402                         break;
10403                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10404                         trans_pipe = PIPE_C;
10405                         break;
10406                 }
10407
10408                 if (trans_pipe == crtc->pipe) {
10409                         pipe_config->cpu_transcoder = panel_transcoder;
10410                         pipe_config->pch_pfit.force_thru = force_thru;
10411                 }
10412         }
10413
10414         /*
10415          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10416          */
10417         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10418                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10419
10420         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10421         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10422
10423         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10424         if (!wf)
10425                 return false;
10426
10427         wakerefs[power_domain] = wf;
10428         *power_domain_mask |= BIT_ULL(power_domain);
10429
10430         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10431
10432         return tmp & PIPECONF_ENABLE;
10433 }
10434
10435 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10436                                          struct intel_crtc_state *pipe_config,
10437                                          u64 *power_domain_mask,
10438                                          intel_wakeref_t *wakerefs)
10439 {
10440         struct drm_device *dev = crtc->base.dev;
10441         struct drm_i915_private *dev_priv = to_i915(dev);
10442         enum intel_display_power_domain power_domain;
10443         enum transcoder cpu_transcoder;
10444         intel_wakeref_t wf;
10445         enum port port;
10446         u32 tmp;
10447
10448         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10449                 if (port == PORT_A)
10450                         cpu_transcoder = TRANSCODER_DSI_A;
10451                 else
10452                         cpu_transcoder = TRANSCODER_DSI_C;
10453
10454                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10455                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10456
10457                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10458                 if (!wf)
10459                         continue;
10460
10461                 wakerefs[power_domain] = wf;
10462                 *power_domain_mask |= BIT_ULL(power_domain);
10463
10464                 /*
10465                  * The PLL needs to be enabled with a valid divider
10466                  * configuration, otherwise accessing DSI registers will hang
10467                  * the machine. See BSpec North Display Engine
10468                  * registers/MIPI[BXT]. We can break out here early, since we
10469                  * need the same DSI PLL to be enabled for both DSI ports.
10470                  */
10471                 if (!bxt_dsi_pll_is_enabled(dev_priv))
10472                         break;
10473
10474                 /* XXX: this works for video mode only */
10475                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10476                 if (!(tmp & DPI_ENABLE))
10477                         continue;
10478
10479                 tmp = I915_READ(MIPI_CTRL(port));
10480                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10481                         continue;
10482
10483                 pipe_config->cpu_transcoder = cpu_transcoder;
10484                 break;
10485         }
10486
10487         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10488 }
10489
10490 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10491                                        struct intel_crtc_state *pipe_config)
10492 {
10493         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10494         struct intel_shared_dpll *pll;
10495         enum port port;
10496         u32 tmp;
10497
10498         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10499
10500         if (INTEL_GEN(dev_priv) >= 12)
10501                 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10502         else
10503                 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10504
10505         if (INTEL_GEN(dev_priv) >= 11)
10506                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10507         else if (IS_CANNONLAKE(dev_priv))
10508                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10509         else if (IS_GEN9_BC(dev_priv))
10510                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10511         else if (IS_GEN9_LP(dev_priv))
10512                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10513         else
10514                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10515
10516         pll = pipe_config->shared_dpll;
10517         if (pll) {
10518                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10519                                                 &pipe_config->dpll_hw_state));
10520         }
10521
10522         /*
10523          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10524          * DDI E. So just check whether this pipe is wired to DDI E and whether
10525          * the PCH transcoder is on.
10526          */
10527         if (INTEL_GEN(dev_priv) < 9 &&
10528             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10529                 pipe_config->has_pch_encoder = true;
10530
10531                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10532                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10533                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10534
10535                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10536         }
10537 }
10538
10539 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10540                                                  enum transcoder cpu_transcoder)
10541 {
10542         u32 trans_port_sync, master_select;
10543
10544         trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10545
10546         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10547                 return INVALID_TRANSCODER;
10548
10549         master_select = trans_port_sync &
10550                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
10551         if (master_select == 0)
10552                 return TRANSCODER_EDP;
10553         else
10554                 return master_select - 1;
10555 }
10556
10557 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10558 {
10559         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10560         u32 transcoders;
10561         enum transcoder cpu_transcoder;
10562
10563         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10564                                                                   crtc_state->cpu_transcoder);
10565
10566         transcoders = BIT(TRANSCODER_A) |
10567                 BIT(TRANSCODER_B) |
10568                 BIT(TRANSCODER_C) |
10569                 BIT(TRANSCODER_D);
10570         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10571                 enum intel_display_power_domain power_domain;
10572                 intel_wakeref_t trans_wakeref;
10573
10574                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10575                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10576                                                                    power_domain);
10577
10578                 if (!trans_wakeref)
10579                         continue;
10580
10581                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10582                     crtc_state->cpu_transcoder)
10583                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10584
10585                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10586         }
10587
10588         WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10589                 crtc_state->sync_mode_slaves_mask);
10590 }
10591
10592 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10593                                     struct intel_crtc_state *pipe_config)
10594 {
10595         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10596         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10597         enum intel_display_power_domain power_domain;
10598         u64 power_domain_mask;
10599         bool active;
10600
10601         intel_crtc_init_scalers(crtc, pipe_config);
10602
10603         pipe_config->master_transcoder = INVALID_TRANSCODER;
10604
10605         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10606         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10607         if (!wf)
10608                 return false;
10609
10610         wakerefs[power_domain] = wf;
10611         power_domain_mask = BIT_ULL(power_domain);
10612
10613         pipe_config->shared_dpll = NULL;
10614
10615         active = hsw_get_transcoder_state(crtc, pipe_config,
10616                                           &power_domain_mask, wakerefs);
10617
10618         if (IS_GEN9_LP(dev_priv) &&
10619             bxt_get_dsi_transcoder_state(crtc, pipe_config,
10620                                          &power_domain_mask, wakerefs)) {
10621                 WARN_ON(active);
10622                 active = true;
10623         }
10624
10625         if (!active)
10626                 goto out;
10627
10628         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10629             INTEL_GEN(dev_priv) >= 11) {
10630                 haswell_get_ddi_port_state(crtc, pipe_config);
10631                 intel_get_pipe_timings(crtc, pipe_config);
10632         }
10633
10634         intel_get_pipe_src_size(crtc, pipe_config);
10635
10636         if (IS_HASWELL(dev_priv)) {
10637                 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10638
10639                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10640                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10641                 else
10642                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10643         } else {
10644                 pipe_config->output_format =
10645                         bdw_get_pipemisc_output_format(crtc);
10646
10647                 /*
10648                  * Currently there is no interface defined to
10649                  * check user preference between RGB/YCBCR444
10650                  * or YCBCR420. So the only possible case for
10651                  * YCBCR444 usage is driving YCBCR420 output
10652                  * with LSPCON, when pipe is configured for
10653                  * YCBCR444 output and LSPCON takes care of
10654                  * downsampling it.
10655                  */
10656                 pipe_config->lspcon_downsampling =
10657                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10658         }
10659
10660         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10661
10662         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10663
10664         if (INTEL_GEN(dev_priv) >= 9) {
10665                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10666
10667                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10668                         pipe_config->gamma_enable = true;
10669
10670                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10671                         pipe_config->csc_enable = true;
10672         } else {
10673                 i9xx_get_pipe_color_config(pipe_config);
10674         }
10675
10676         intel_color_get_config(pipe_config);
10677
10678         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10679         WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10680
10681         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10682         if (wf) {
10683                 wakerefs[power_domain] = wf;
10684                 power_domain_mask |= BIT_ULL(power_domain);
10685
10686                 if (INTEL_GEN(dev_priv) >= 9)
10687                         skylake_get_pfit_config(crtc, pipe_config);
10688                 else
10689                         ironlake_get_pfit_config(crtc, pipe_config);
10690         }
10691
10692         if (hsw_crtc_supports_ips(crtc)) {
10693                 if (IS_HASWELL(dev_priv))
10694                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10695                 else {
10696                         /*
10697                          * We cannot readout IPS state on broadwell, set to
10698                          * true so we can set it to a defined state on first
10699                          * commit.
10700                          */
10701                         pipe_config->ips_enabled = true;
10702                 }
10703         }
10704
10705         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10706             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10707                 pipe_config->pixel_multiplier =
10708                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10709         } else {
10710                 pipe_config->pixel_multiplier = 1;
10711         }
10712
10713         if (INTEL_GEN(dev_priv) >= 11 &&
10714             !transcoder_is_dsi(pipe_config->cpu_transcoder))
10715                 icelake_get_trans_port_sync_config(pipe_config);
10716
10717 out:
10718         for_each_power_domain(power_domain, power_domain_mask)
10719                 intel_display_power_put(dev_priv,
10720                                         power_domain, wakerefs[power_domain]);
10721
10722         return active;
10723 }
10724
10725 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10726 {
10727         struct drm_i915_private *dev_priv =
10728                 to_i915(plane_state->base.plane->dev);
10729         const struct drm_framebuffer *fb = plane_state->base.fb;
10730         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10731         u32 base;
10732
10733         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10734                 base = obj->phys_handle->busaddr;
10735         else
10736                 base = intel_plane_ggtt_offset(plane_state);
10737
10738         return base + plane_state->color_plane[0].offset;
10739 }
10740
10741 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10742 {
10743         int x = plane_state->base.dst.x1;
10744         int y = plane_state->base.dst.y1;
10745         u32 pos = 0;
10746
10747         if (x < 0) {
10748                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10749                 x = -x;
10750         }
10751         pos |= x << CURSOR_X_SHIFT;
10752
10753         if (y < 0) {
10754                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10755                 y = -y;
10756         }
10757         pos |= y << CURSOR_Y_SHIFT;
10758
10759         return pos;
10760 }
10761
10762 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10763 {
10764         const struct drm_mode_config *config =
10765                 &plane_state->base.plane->dev->mode_config;
10766         int width = drm_rect_width(&plane_state->base.dst);
10767         int height = drm_rect_height(&plane_state->base.dst);
10768
10769         return width > 0 && width <= config->cursor_width &&
10770                 height > 0 && height <= config->cursor_height;
10771 }
10772
10773 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10774 {
10775         struct drm_i915_private *dev_priv =
10776                 to_i915(plane_state->base.plane->dev);
10777         unsigned int rotation = plane_state->base.rotation;
10778         int src_x, src_y;
10779         u32 offset;
10780         int ret;
10781
10782         ret = intel_plane_compute_gtt(plane_state);
10783         if (ret)
10784                 return ret;
10785
10786         if (!plane_state->base.visible)
10787                 return 0;
10788
10789         src_x = plane_state->base.src.x1 >> 16;
10790         src_y = plane_state->base.src.y1 >> 16;
10791
10792         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10793         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10794                                                     plane_state, 0);
10795
10796         if (src_x != 0 || src_y != 0) {
10797                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10798                 return -EINVAL;
10799         }
10800
10801         /*
10802          * Put the final coordinates back so that the src
10803          * coordinate checks will see the right values.
10804          */
10805         drm_rect_translate_to(&plane_state->base.src,
10806                               src_x << 16, src_y << 16);
10807
10808         /* ILK+ do this automagically in hardware */
10809         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10810                 const struct drm_framebuffer *fb = plane_state->base.fb;
10811                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
10812                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
10813
10814                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10815         }
10816
10817         plane_state->color_plane[0].offset = offset;
10818         plane_state->color_plane[0].x = src_x;
10819         plane_state->color_plane[0].y = src_y;
10820
10821         return 0;
10822 }
10823
10824 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10825                               struct intel_plane_state *plane_state)
10826 {
10827         const struct drm_framebuffer *fb = plane_state->base.fb;
10828         int ret;
10829
10830         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10831                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10832                 return -EINVAL;
10833         }
10834
10835         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
10836                                                   &crtc_state->base,
10837                                                   DRM_PLANE_HELPER_NO_SCALING,
10838                                                   DRM_PLANE_HELPER_NO_SCALING,
10839                                                   true, true);
10840         if (ret)
10841                 return ret;
10842
10843         /* Use the unclipped src/dst rectangles, which we program to hw */
10844         plane_state->base.src = drm_plane_state_src(&plane_state->base);
10845         plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
10846
10847         ret = intel_cursor_check_surface(plane_state);
10848         if (ret)
10849                 return ret;
10850
10851         if (!plane_state->base.visible)
10852                 return 0;
10853
10854         ret = intel_plane_check_src_coordinates(plane_state);
10855         if (ret)
10856                 return ret;
10857
10858         return 0;
10859 }
10860
10861 static unsigned int
10862 i845_cursor_max_stride(struct intel_plane *plane,
10863                        u32 pixel_format, u64 modifier,
10864                        unsigned int rotation)
10865 {
10866         return 2048;
10867 }
10868
10869 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10870 {
10871         u32 cntl = 0;
10872
10873         if (crtc_state->gamma_enable)
10874                 cntl |= CURSOR_GAMMA_ENABLE;
10875
10876         return cntl;
10877 }
10878
10879 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10880                            const struct intel_plane_state *plane_state)
10881 {
10882         return CURSOR_ENABLE |
10883                 CURSOR_FORMAT_ARGB |
10884                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10885 }
10886
10887 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10888 {
10889         int width = drm_rect_width(&plane_state->base.dst);
10890
10891         /*
10892          * 845g/865g are only limited by the width of their cursors,
10893          * the height is arbitrary up to the precision of the register.
10894          */
10895         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10896 }
10897
10898 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10899                              struct intel_plane_state *plane_state)
10900 {
10901         const struct drm_framebuffer *fb = plane_state->base.fb;
10902         int ret;
10903
10904         ret = intel_check_cursor(crtc_state, plane_state);
10905         if (ret)
10906                 return ret;
10907
10908         /* if we want to turn off the cursor ignore width and height */
10909         if (!fb)
10910                 return 0;
10911
10912         /* Check for which cursor types we support */
10913         if (!i845_cursor_size_ok(plane_state)) {
10914                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10915                           drm_rect_width(&plane_state->base.dst),
10916                           drm_rect_height(&plane_state->base.dst));
10917                 return -EINVAL;
10918         }
10919
10920         WARN_ON(plane_state->base.visible &&
10921                 plane_state->color_plane[0].stride != fb->pitches[0]);
10922
10923         switch (fb->pitches[0]) {
10924         case 256:
10925         case 512:
10926         case 1024:
10927         case 2048:
10928                 break;
10929         default:
10930                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10931                               fb->pitches[0]);
10932                 return -EINVAL;
10933         }
10934
10935         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10936
10937         return 0;
10938 }
10939
10940 static void i845_update_cursor(struct intel_plane *plane,
10941                                const struct intel_crtc_state *crtc_state,
10942                                const struct intel_plane_state *plane_state)
10943 {
10944         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10945         u32 cntl = 0, base = 0, pos = 0, size = 0;
10946         unsigned long irqflags;
10947
10948         if (plane_state && plane_state->base.visible) {
10949                 unsigned int width = drm_rect_width(&plane_state->base.dst);
10950                 unsigned int height = drm_rect_height(&plane_state->base.dst);
10951
10952                 cntl = plane_state->ctl |
10953                         i845_cursor_ctl_crtc(crtc_state);
10954
10955                 size = (height << 12) | width;
10956
10957                 base = intel_cursor_base(plane_state);
10958                 pos = intel_cursor_position(plane_state);
10959         }
10960
10961         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10962
10963         /* On these chipsets we can only modify the base/size/stride
10964          * whilst the cursor is disabled.
10965          */
10966         if (plane->cursor.base != base ||
10967             plane->cursor.size != size ||
10968             plane->cursor.cntl != cntl) {
10969                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10970                 I915_WRITE_FW(CURBASE(PIPE_A), base);
10971                 I915_WRITE_FW(CURSIZE, size);
10972                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10973                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
10974
10975                 plane->cursor.base = base;
10976                 plane->cursor.size = size;
10977                 plane->cursor.cntl = cntl;
10978         } else {
10979                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10980         }
10981
10982         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10983 }
10984
10985 static void i845_disable_cursor(struct intel_plane *plane,
10986                                 const struct intel_crtc_state *crtc_state)
10987 {
10988         i845_update_cursor(plane, crtc_state, NULL);
10989 }
10990
10991 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
10992                                      enum pipe *pipe)
10993 {
10994         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10995         enum intel_display_power_domain power_domain;
10996         intel_wakeref_t wakeref;
10997         bool ret;
10998
10999         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11000         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11001         if (!wakeref)
11002                 return false;
11003
11004         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11005
11006         *pipe = PIPE_A;
11007
11008         intel_display_power_put(dev_priv, power_domain, wakeref);
11009
11010         return ret;
11011 }
11012
11013 static unsigned int
11014 i9xx_cursor_max_stride(struct intel_plane *plane,
11015                        u32 pixel_format, u64 modifier,
11016                        unsigned int rotation)
11017 {
11018         return plane->base.dev->mode_config.cursor_width * 4;
11019 }
11020
11021 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11022 {
11023         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11024         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11025         u32 cntl = 0;
11026
11027         if (INTEL_GEN(dev_priv) >= 11)
11028                 return cntl;
11029
11030         if (crtc_state->gamma_enable)
11031                 cntl = MCURSOR_GAMMA_ENABLE;
11032
11033         if (crtc_state->csc_enable)
11034                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11035
11036         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11037                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11038
11039         return cntl;
11040 }
11041
11042 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11043                            const struct intel_plane_state *plane_state)
11044 {
11045         struct drm_i915_private *dev_priv =
11046                 to_i915(plane_state->base.plane->dev);
11047         u32 cntl = 0;
11048
11049         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11050                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11051
11052         switch (drm_rect_width(&plane_state->base.dst)) {
11053         case 64:
11054                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11055                 break;
11056         case 128:
11057                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11058                 break;
11059         case 256:
11060                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11061                 break;
11062         default:
11063                 MISSING_CASE(drm_rect_width(&plane_state->base.dst));
11064                 return 0;
11065         }
11066
11067         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
11068                 cntl |= MCURSOR_ROTATE_180;
11069
11070         return cntl;
11071 }
11072
11073 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11074 {
11075         struct drm_i915_private *dev_priv =
11076                 to_i915(plane_state->base.plane->dev);
11077         int width = drm_rect_width(&plane_state->base.dst);
11078         int height = drm_rect_height(&plane_state->base.dst);
11079
11080         if (!intel_cursor_size_ok(plane_state))
11081                 return false;
11082
11083         /* Cursor width is limited to a few power-of-two sizes */
11084         switch (width) {
11085         case 256:
11086         case 128:
11087         case 64:
11088                 break;
11089         default:
11090                 return false;
11091         }
11092
11093         /*
11094          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11095          * height from 8 lines up to the cursor width, when the
11096          * cursor is not rotated. Everything else requires square
11097          * cursors.
11098          */
11099         if (HAS_CUR_FBC(dev_priv) &&
11100             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
11101                 if (height < 8 || height > width)
11102                         return false;
11103         } else {
11104                 if (height != width)
11105                         return false;
11106         }
11107
11108         return true;
11109 }
11110
11111 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11112                              struct intel_plane_state *plane_state)
11113 {
11114         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
11115         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11116         const struct drm_framebuffer *fb = plane_state->base.fb;
11117         enum pipe pipe = plane->pipe;
11118         int ret;
11119
11120         ret = intel_check_cursor(crtc_state, plane_state);
11121         if (ret)
11122                 return ret;
11123
11124         /* if we want to turn off the cursor ignore width and height */
11125         if (!fb)
11126                 return 0;
11127
11128         /* Check for which cursor types we support */
11129         if (!i9xx_cursor_size_ok(plane_state)) {
11130                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11131                           drm_rect_width(&plane_state->base.dst),
11132                           drm_rect_height(&plane_state->base.dst));
11133                 return -EINVAL;
11134         }
11135
11136         WARN_ON(plane_state->base.visible &&
11137                 plane_state->color_plane[0].stride != fb->pitches[0]);
11138
11139         if (fb->pitches[0] !=
11140             drm_rect_width(&plane_state->base.dst) * fb->format->cpp[0]) {
11141                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11142                               fb->pitches[0],
11143                               drm_rect_width(&plane_state->base.dst));
11144                 return -EINVAL;
11145         }
11146
11147         /*
11148          * There's something wrong with the cursor on CHV pipe C.
11149          * If it straddles the left edge of the screen then
11150          * moving it away from the edge or disabling it often
11151          * results in a pipe underrun, and often that can lead to
11152          * dead pipe (constant underrun reported, and it scans
11153          * out just a solid color). To recover from that, the
11154          * display power well must be turned off and on again.
11155          * Refuse the put the cursor into that compromised position.
11156          */
11157         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11158             plane_state->base.visible && plane_state->base.dst.x1 < 0) {
11159                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11160                 return -EINVAL;
11161         }
11162
11163         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11164
11165         return 0;
11166 }
11167
11168 static void i9xx_update_cursor(struct intel_plane *plane,
11169                                const struct intel_crtc_state *crtc_state,
11170                                const struct intel_plane_state *plane_state)
11171 {
11172         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11173         enum pipe pipe = plane->pipe;
11174         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11175         unsigned long irqflags;
11176
11177         if (plane_state && plane_state->base.visible) {
11178                 unsigned width = drm_rect_width(&plane_state->base.dst);
11179                 unsigned height = drm_rect_height(&plane_state->base.dst);
11180
11181                 cntl = plane_state->ctl |
11182                         i9xx_cursor_ctl_crtc(crtc_state);
11183
11184                 if (width != height)
11185                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11186
11187                 base = intel_cursor_base(plane_state);
11188                 pos = intel_cursor_position(plane_state);
11189         }
11190
11191         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11192
11193         /*
11194          * On some platforms writing CURCNTR first will also
11195          * cause CURPOS to be armed by the CURBASE write.
11196          * Without the CURCNTR write the CURPOS write would
11197          * arm itself. Thus we always update CURCNTR before
11198          * CURPOS.
11199          *
11200          * On other platforms CURPOS always requires the
11201          * CURBASE write to arm the update. Additonally
11202          * a write to any of the cursor register will cancel
11203          * an already armed cursor update. Thus leaving out
11204          * the CURBASE write after CURPOS could lead to a
11205          * cursor that doesn't appear to move, or even change
11206          * shape. Thus we always write CURBASE.
11207          *
11208          * The other registers are armed by by the CURBASE write
11209          * except when the plane is getting enabled at which time
11210          * the CURCNTR write arms the update.
11211          */
11212
11213         if (INTEL_GEN(dev_priv) >= 9)
11214                 skl_write_cursor_wm(plane, crtc_state);
11215
11216         if (plane->cursor.base != base ||
11217             plane->cursor.size != fbc_ctl ||
11218             plane->cursor.cntl != cntl) {
11219                 if (HAS_CUR_FBC(dev_priv))
11220                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11221                 I915_WRITE_FW(CURCNTR(pipe), cntl);
11222                 I915_WRITE_FW(CURPOS(pipe), pos);
11223                 I915_WRITE_FW(CURBASE(pipe), base);
11224
11225                 plane->cursor.base = base;
11226                 plane->cursor.size = fbc_ctl;
11227                 plane->cursor.cntl = cntl;
11228         } else {
11229                 I915_WRITE_FW(CURPOS(pipe), pos);
11230                 I915_WRITE_FW(CURBASE(pipe), base);
11231         }
11232
11233         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11234 }
11235
11236 static void i9xx_disable_cursor(struct intel_plane *plane,
11237                                 const struct intel_crtc_state *crtc_state)
11238 {
11239         i9xx_update_cursor(plane, crtc_state, NULL);
11240 }
11241
11242 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11243                                      enum pipe *pipe)
11244 {
11245         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11246         enum intel_display_power_domain power_domain;
11247         intel_wakeref_t wakeref;
11248         bool ret;
11249         u32 val;
11250
11251         /*
11252          * Not 100% correct for planes that can move between pipes,
11253          * but that's only the case for gen2-3 which don't have any
11254          * display power wells.
11255          */
11256         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11257         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11258         if (!wakeref)
11259                 return false;
11260
11261         val = I915_READ(CURCNTR(plane->pipe));
11262
11263         ret = val & MCURSOR_MODE;
11264
11265         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11266                 *pipe = plane->pipe;
11267         else
11268                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11269                         MCURSOR_PIPE_SELECT_SHIFT;
11270
11271         intel_display_power_put(dev_priv, power_domain, wakeref);
11272
11273         return ret;
11274 }
11275
11276 /* VESA 640x480x72Hz mode to set on the pipe */
11277 static const struct drm_display_mode load_detect_mode = {
11278         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11279                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11280 };
11281
11282 struct drm_framebuffer *
11283 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11284                          struct drm_mode_fb_cmd2 *mode_cmd)
11285 {
11286         struct intel_framebuffer *intel_fb;
11287         int ret;
11288
11289         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11290         if (!intel_fb)
11291                 return ERR_PTR(-ENOMEM);
11292
11293         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11294         if (ret)
11295                 goto err;
11296
11297         return &intel_fb->base;
11298
11299 err:
11300         kfree(intel_fb);
11301         return ERR_PTR(ret);
11302 }
11303
11304 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11305                                         struct drm_crtc *crtc)
11306 {
11307         struct drm_plane *plane;
11308         struct drm_plane_state *plane_state;
11309         int ret, i;
11310
11311         ret = drm_atomic_add_affected_planes(state, crtc);
11312         if (ret)
11313                 return ret;
11314
11315         for_each_new_plane_in_state(state, plane, plane_state, i) {
11316                 if (plane_state->crtc != crtc)
11317                         continue;
11318
11319                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11320                 if (ret)
11321                         return ret;
11322
11323                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11324         }
11325
11326         return 0;
11327 }
11328
11329 int intel_get_load_detect_pipe(struct drm_connector *connector,
11330                                struct intel_load_detect_pipe *old,
11331                                struct drm_modeset_acquire_ctx *ctx)
11332 {
11333         struct intel_crtc *intel_crtc;
11334         struct intel_encoder *intel_encoder =
11335                 intel_attached_encoder(connector);
11336         struct drm_crtc *possible_crtc;
11337         struct drm_encoder *encoder = &intel_encoder->base;
11338         struct drm_crtc *crtc = NULL;
11339         struct drm_device *dev = encoder->dev;
11340         struct drm_i915_private *dev_priv = to_i915(dev);
11341         struct drm_mode_config *config = &dev->mode_config;
11342         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11343         struct drm_connector_state *connector_state;
11344         struct intel_crtc_state *crtc_state;
11345         int ret, i = -1;
11346
11347         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11348                       connector->base.id, connector->name,
11349                       encoder->base.id, encoder->name);
11350
11351         old->restore_state = NULL;
11352
11353         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11354
11355         /*
11356          * Algorithm gets a little messy:
11357          *
11358          *   - if the connector already has an assigned crtc, use it (but make
11359          *     sure it's on first)
11360          *
11361          *   - try to find the first unused crtc that can drive this connector,
11362          *     and use that if we find one
11363          */
11364
11365         /* See if we already have a CRTC for this connector */
11366         if (connector->state->crtc) {
11367                 crtc = connector->state->crtc;
11368
11369                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11370                 if (ret)
11371                         goto fail;
11372
11373                 /* Make sure the crtc and connector are running */
11374                 goto found;
11375         }
11376
11377         /* Find an unused one (if possible) */
11378         for_each_crtc(dev, possible_crtc) {
11379                 i++;
11380                 if (!(encoder->possible_crtcs & (1 << i)))
11381                         continue;
11382
11383                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11384                 if (ret)
11385                         goto fail;
11386
11387                 if (possible_crtc->state->enable) {
11388                         drm_modeset_unlock(&possible_crtc->mutex);
11389                         continue;
11390                 }
11391
11392                 crtc = possible_crtc;
11393                 break;
11394         }
11395
11396         /*
11397          * If we didn't find an unused CRTC, don't use any.
11398          */
11399         if (!crtc) {
11400                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11401                 ret = -ENODEV;
11402                 goto fail;
11403         }
11404
11405 found:
11406         intel_crtc = to_intel_crtc(crtc);
11407
11408         state = drm_atomic_state_alloc(dev);
11409         restore_state = drm_atomic_state_alloc(dev);
11410         if (!state || !restore_state) {
11411                 ret = -ENOMEM;
11412                 goto fail;
11413         }
11414
11415         state->acquire_ctx = ctx;
11416         restore_state->acquire_ctx = ctx;
11417
11418         connector_state = drm_atomic_get_connector_state(state, connector);
11419         if (IS_ERR(connector_state)) {
11420                 ret = PTR_ERR(connector_state);
11421                 goto fail;
11422         }
11423
11424         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11425         if (ret)
11426                 goto fail;
11427
11428         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11429         if (IS_ERR(crtc_state)) {
11430                 ret = PTR_ERR(crtc_state);
11431                 goto fail;
11432         }
11433
11434         crtc_state->base.active = crtc_state->base.enable = true;
11435
11436         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base,
11437                                            &load_detect_mode);
11438         if (ret)
11439                 goto fail;
11440
11441         ret = intel_modeset_disable_planes(state, crtc);
11442         if (ret)
11443                 goto fail;
11444
11445         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11446         if (!ret)
11447                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11448         if (!ret)
11449                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11450         if (ret) {
11451                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11452                 goto fail;
11453         }
11454
11455         ret = drm_atomic_commit(state);
11456         if (ret) {
11457                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11458                 goto fail;
11459         }
11460
11461         old->restore_state = restore_state;
11462         drm_atomic_state_put(state);
11463
11464         /* let the connector get through one full cycle before testing */
11465         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11466         return true;
11467
11468 fail:
11469         if (state) {
11470                 drm_atomic_state_put(state);
11471                 state = NULL;
11472         }
11473         if (restore_state) {
11474                 drm_atomic_state_put(restore_state);
11475                 restore_state = NULL;
11476         }
11477
11478         if (ret == -EDEADLK)
11479                 return ret;
11480
11481         return false;
11482 }
11483
11484 void intel_release_load_detect_pipe(struct drm_connector *connector,
11485                                     struct intel_load_detect_pipe *old,
11486                                     struct drm_modeset_acquire_ctx *ctx)
11487 {
11488         struct intel_encoder *intel_encoder =
11489                 intel_attached_encoder(connector);
11490         struct drm_encoder *encoder = &intel_encoder->base;
11491         struct drm_atomic_state *state = old->restore_state;
11492         int ret;
11493
11494         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11495                       connector->base.id, connector->name,
11496                       encoder->base.id, encoder->name);
11497
11498         if (!state)
11499                 return;
11500
11501         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11502         if (ret)
11503                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11504         drm_atomic_state_put(state);
11505 }
11506
11507 static int i9xx_pll_refclk(struct drm_device *dev,
11508                            const struct intel_crtc_state *pipe_config)
11509 {
11510         struct drm_i915_private *dev_priv = to_i915(dev);
11511         u32 dpll = pipe_config->dpll_hw_state.dpll;
11512
11513         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11514                 return dev_priv->vbt.lvds_ssc_freq;
11515         else if (HAS_PCH_SPLIT(dev_priv))
11516                 return 120000;
11517         else if (!IS_GEN(dev_priv, 2))
11518                 return 96000;
11519         else
11520                 return 48000;
11521 }
11522
11523 /* Returns the clock of the currently programmed mode of the given pipe. */
11524 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11525                                 struct intel_crtc_state *pipe_config)
11526 {
11527         struct drm_device *dev = crtc->base.dev;
11528         struct drm_i915_private *dev_priv = to_i915(dev);
11529         enum pipe pipe = crtc->pipe;
11530         u32 dpll = pipe_config->dpll_hw_state.dpll;
11531         u32 fp;
11532         struct dpll clock;
11533         int port_clock;
11534         int refclk = i9xx_pll_refclk(dev, pipe_config);
11535
11536         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11537                 fp = pipe_config->dpll_hw_state.fp0;
11538         else
11539                 fp = pipe_config->dpll_hw_state.fp1;
11540
11541         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11542         if (IS_PINEVIEW(dev_priv)) {
11543                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11544                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11545         } else {
11546                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11547                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11548         }
11549
11550         if (!IS_GEN(dev_priv, 2)) {
11551                 if (IS_PINEVIEW(dev_priv))
11552                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11553                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11554                 else
11555                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11556                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11557
11558                 switch (dpll & DPLL_MODE_MASK) {
11559                 case DPLLB_MODE_DAC_SERIAL:
11560                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11561                                 5 : 10;
11562                         break;
11563                 case DPLLB_MODE_LVDS:
11564                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11565                                 7 : 14;
11566                         break;
11567                 default:
11568                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11569                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11570                         return;
11571                 }
11572
11573                 if (IS_PINEVIEW(dev_priv))
11574                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11575                 else
11576                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11577         } else {
11578                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11579                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11580
11581                 if (is_lvds) {
11582                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11583                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11584
11585                         if (lvds & LVDS_CLKB_POWER_UP)
11586                                 clock.p2 = 7;
11587                         else
11588                                 clock.p2 = 14;
11589                 } else {
11590                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11591                                 clock.p1 = 2;
11592                         else {
11593                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11594                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11595                         }
11596                         if (dpll & PLL_P2_DIVIDE_BY_4)
11597                                 clock.p2 = 4;
11598                         else
11599                                 clock.p2 = 2;
11600                 }
11601
11602                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11603         }
11604
11605         /*
11606          * This value includes pixel_multiplier. We will use
11607          * port_clock to compute adjusted_mode.crtc_clock in the
11608          * encoder's get_config() function.
11609          */
11610         pipe_config->port_clock = port_clock;
11611 }
11612
11613 int intel_dotclock_calculate(int link_freq,
11614                              const struct intel_link_m_n *m_n)
11615 {
11616         /*
11617          * The calculation for the data clock is:
11618          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11619          * But we want to avoid losing precison if possible, so:
11620          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11621          *
11622          * and the link clock is simpler:
11623          * link_clock = (m * link_clock) / n
11624          */
11625
11626         if (!m_n->link_n)
11627                 return 0;
11628
11629         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11630 }
11631
11632 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11633                                    struct intel_crtc_state *pipe_config)
11634 {
11635         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11636
11637         /* read out port_clock from the DPLL */
11638         i9xx_crtc_clock_get(crtc, pipe_config);
11639
11640         /*
11641          * In case there is an active pipe without active ports,
11642          * we may need some idea for the dotclock anyway.
11643          * Calculate one based on the FDI configuration.
11644          */
11645         pipe_config->base.adjusted_mode.crtc_clock =
11646                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11647                                          &pipe_config->fdi_m_n);
11648 }
11649
11650 /* Returns the currently programmed mode of the given encoder. */
11651 struct drm_display_mode *
11652 intel_encoder_current_mode(struct intel_encoder *encoder)
11653 {
11654         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11655         struct intel_crtc_state *crtc_state;
11656         struct drm_display_mode *mode;
11657         struct intel_crtc *crtc;
11658         enum pipe pipe;
11659
11660         if (!encoder->get_hw_state(encoder, &pipe))
11661                 return NULL;
11662
11663         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11664
11665         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11666         if (!mode)
11667                 return NULL;
11668
11669         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11670         if (!crtc_state) {
11671                 kfree(mode);
11672                 return NULL;
11673         }
11674
11675         crtc_state->base.crtc = &crtc->base;
11676
11677         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11678                 kfree(crtc_state);
11679                 kfree(mode);
11680                 return NULL;
11681         }
11682
11683         encoder->get_config(encoder, crtc_state);
11684
11685         intel_mode_from_pipe_config(mode, crtc_state);
11686
11687         kfree(crtc_state);
11688
11689         return mode;
11690 }
11691
11692 static void intel_crtc_destroy(struct drm_crtc *crtc)
11693 {
11694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11695
11696         drm_crtc_cleanup(crtc);
11697         kfree(intel_crtc);
11698 }
11699
11700 /**
11701  * intel_wm_need_update - Check whether watermarks need updating
11702  * @cur: current plane state
11703  * @new: new plane state
11704  *
11705  * Check current plane state versus the new one to determine whether
11706  * watermarks need to be recalculated.
11707  *
11708  * Returns true or false.
11709  */
11710 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11711                                  struct intel_plane_state *new)
11712 {
11713         /* Update watermarks on tiling or size changes. */
11714         if (new->base.visible != cur->base.visible)
11715                 return true;
11716
11717         if (!cur->base.fb || !new->base.fb)
11718                 return false;
11719
11720         if (cur->base.fb->modifier != new->base.fb->modifier ||
11721             cur->base.rotation != new->base.rotation ||
11722             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
11723             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
11724             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
11725             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
11726                 return true;
11727
11728         return false;
11729 }
11730
11731 static bool needs_scaling(const struct intel_plane_state *state)
11732 {
11733         int src_w = drm_rect_width(&state->base.src) >> 16;
11734         int src_h = drm_rect_height(&state->base.src) >> 16;
11735         int dst_w = drm_rect_width(&state->base.dst);
11736         int dst_h = drm_rect_height(&state->base.dst);
11737
11738         return (src_w != dst_w || src_h != dst_h);
11739 }
11740
11741 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11742                                     struct intel_crtc_state *crtc_state,
11743                                     const struct intel_plane_state *old_plane_state,
11744                                     struct intel_plane_state *plane_state)
11745 {
11746         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11747         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
11748         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11749         bool mode_changed = needs_modeset(crtc_state);
11750         bool was_crtc_enabled = old_crtc_state->base.active;
11751         bool is_crtc_enabled = crtc_state->base.active;
11752         bool turn_off, turn_on, visible, was_visible;
11753         int ret;
11754
11755         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11756                 ret = skl_update_scaler_plane(crtc_state, plane_state);
11757                 if (ret)
11758                         return ret;
11759         }
11760
11761         was_visible = old_plane_state->base.visible;
11762         visible = plane_state->base.visible;
11763
11764         if (!was_crtc_enabled && WARN_ON(was_visible))
11765                 was_visible = false;
11766
11767         /*
11768          * Visibility is calculated as if the crtc was on, but
11769          * after scaler setup everything depends on it being off
11770          * when the crtc isn't active.
11771          *
11772          * FIXME this is wrong for watermarks. Watermarks should also
11773          * be computed as if the pipe would be active. Perhaps move
11774          * per-plane wm computation to the .check_plane() hook, and
11775          * only combine the results from all planes in the current place?
11776          */
11777         if (!is_crtc_enabled) {
11778                 plane_state->base.visible = visible = false;
11779                 crtc_state->active_planes &= ~BIT(plane->id);
11780                 crtc_state->data_rate[plane->id] = 0;
11781                 crtc_state->min_cdclk[plane->id] = 0;
11782         }
11783
11784         if (!was_visible && !visible)
11785                 return 0;
11786
11787         turn_off = was_visible && (!visible || mode_changed);
11788         turn_on = visible && (!was_visible || mode_changed);
11789
11790         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11791                          crtc->base.base.id, crtc->base.name,
11792                          plane->base.base.id, plane->base.name,
11793                          was_visible, visible,
11794                          turn_off, turn_on, mode_changed);
11795
11796         if (turn_on) {
11797                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11798                         crtc_state->update_wm_pre = true;
11799
11800                 /* must disable cxsr around plane enable/disable */
11801                 if (plane->id != PLANE_CURSOR)
11802                         crtc_state->disable_cxsr = true;
11803         } else if (turn_off) {
11804                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11805                         crtc_state->update_wm_post = true;
11806
11807                 /* must disable cxsr around plane enable/disable */
11808                 if (plane->id != PLANE_CURSOR)
11809                         crtc_state->disable_cxsr = true;
11810         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11811                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11812                         /* FIXME bollocks */
11813                         crtc_state->update_wm_pre = true;
11814                         crtc_state->update_wm_post = true;
11815                 }
11816         }
11817
11818         if (visible || was_visible)
11819                 crtc_state->fb_bits |= plane->frontbuffer_bit;
11820
11821         /*
11822          * ILK/SNB DVSACNTR/Sprite Enable
11823          * IVB SPR_CTL/Sprite Enable
11824          * "When in Self Refresh Big FIFO mode, a write to enable the
11825          *  plane will be internally buffered and delayed while Big FIFO
11826          *  mode is exiting."
11827          *
11828          * Which means that enabling the sprite can take an extra frame
11829          * when we start in big FIFO mode (LP1+). Thus we need to drop
11830          * down to LP0 and wait for vblank in order to make sure the
11831          * sprite gets enabled on the next vblank after the register write.
11832          * Doing otherwise would risk enabling the sprite one frame after
11833          * we've already signalled flip completion. We can resume LP1+
11834          * once the sprite has been enabled.
11835          *
11836          *
11837          * WaCxSRDisabledForSpriteScaling:ivb
11838          * IVB SPR_SCALE/Scaling Enable
11839          * "Low Power watermarks must be disabled for at least one
11840          *  frame before enabling sprite scaling, and kept disabled
11841          *  until sprite scaling is disabled."
11842          *
11843          * ILK/SNB DVSASCALE/Scaling Enable
11844          * "When in Self Refresh Big FIFO mode, scaling enable will be
11845          *  masked off while Big FIFO mode is exiting."
11846          *
11847          * Despite the w/a only being listed for IVB we assume that
11848          * the ILK/SNB note has similar ramifications, hence we apply
11849          * the w/a on all three platforms.
11850          *
11851          * With experimental results seems this is needed also for primary
11852          * plane, not only sprite plane.
11853          */
11854         if (plane->id != PLANE_CURSOR &&
11855             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11856              IS_IVYBRIDGE(dev_priv)) &&
11857             (turn_on || (!needs_scaling(old_plane_state) &&
11858                          needs_scaling(plane_state))))
11859                 crtc_state->disable_lp_wm = true;
11860
11861         return 0;
11862 }
11863
11864 static bool encoders_cloneable(const struct intel_encoder *a,
11865                                const struct intel_encoder *b)
11866 {
11867         /* masks could be asymmetric, so check both ways */
11868         return a == b || (a->cloneable & (1 << b->type) &&
11869                           b->cloneable & (1 << a->type));
11870 }
11871
11872 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11873                                          struct intel_crtc *crtc,
11874                                          struct intel_encoder *encoder)
11875 {
11876         struct intel_encoder *source_encoder;
11877         struct drm_connector *connector;
11878         struct drm_connector_state *connector_state;
11879         int i;
11880
11881         for_each_new_connector_in_state(state, connector, connector_state, i) {
11882                 if (connector_state->crtc != &crtc->base)
11883                         continue;
11884
11885                 source_encoder =
11886                         to_intel_encoder(connector_state->best_encoder);
11887                 if (!encoders_cloneable(encoder, source_encoder))
11888                         return false;
11889         }
11890
11891         return true;
11892 }
11893
11894 static int icl_add_linked_planes(struct intel_atomic_state *state)
11895 {
11896         struct intel_plane *plane, *linked;
11897         struct intel_plane_state *plane_state, *linked_plane_state;
11898         int i;
11899
11900         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11901                 linked = plane_state->planar_linked_plane;
11902
11903                 if (!linked)
11904                         continue;
11905
11906                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11907                 if (IS_ERR(linked_plane_state))
11908                         return PTR_ERR(linked_plane_state);
11909
11910                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
11911                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
11912         }
11913
11914         return 0;
11915 }
11916
11917 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11918 {
11919         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11920         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11921         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
11922         struct intel_plane *plane, *linked;
11923         struct intel_plane_state *plane_state;
11924         int i;
11925
11926         if (INTEL_GEN(dev_priv) < 11)
11927                 return 0;
11928
11929         /*
11930          * Destroy all old plane links and make the slave plane invisible
11931          * in the crtc_state->active_planes mask.
11932          */
11933         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11934                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
11935                         continue;
11936
11937                 plane_state->planar_linked_plane = NULL;
11938                 if (plane_state->planar_slave && !plane_state->base.visible) {
11939                         crtc_state->active_planes &= ~BIT(plane->id);
11940                         crtc_state->update_planes |= BIT(plane->id);
11941                 }
11942
11943                 plane_state->planar_slave = false;
11944         }
11945
11946         if (!crtc_state->nv12_planes)
11947                 return 0;
11948
11949         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11950                 struct intel_plane_state *linked_state = NULL;
11951
11952                 if (plane->pipe != crtc->pipe ||
11953                     !(crtc_state->nv12_planes & BIT(plane->id)))
11954                         continue;
11955
11956                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11957                         if (!icl_is_nv12_y_plane(linked->id))
11958                                 continue;
11959
11960                         if (crtc_state->active_planes & BIT(linked->id))
11961                                 continue;
11962
11963                         linked_state = intel_atomic_get_plane_state(state, linked);
11964                         if (IS_ERR(linked_state))
11965                                 return PTR_ERR(linked_state);
11966
11967                         break;
11968                 }
11969
11970                 if (!linked_state) {
11971                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11972                                       hweight8(crtc_state->nv12_planes));
11973
11974                         return -EINVAL;
11975                 }
11976
11977                 plane_state->planar_linked_plane = linked;
11978
11979                 linked_state->planar_slave = true;
11980                 linked_state->planar_linked_plane = plane;
11981                 crtc_state->active_planes |= BIT(linked->id);
11982                 crtc_state->update_planes |= BIT(linked->id);
11983                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
11984         }
11985
11986         return 0;
11987 }
11988
11989 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
11990 {
11991         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
11992         struct intel_atomic_state *state =
11993                 to_intel_atomic_state(new_crtc_state->base.state);
11994         const struct intel_crtc_state *old_crtc_state =
11995                 intel_atomic_get_old_crtc_state(state, crtc);
11996
11997         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
11998 }
11999
12000 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12001 {
12002         struct drm_crtc *crtc = crtc_state->base.crtc;
12003         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
12004         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
12005         struct drm_connector *master_connector, *connector;
12006         struct drm_connector_state *connector_state;
12007         struct drm_connector_list_iter conn_iter;
12008         struct drm_crtc *master_crtc = NULL;
12009         struct drm_crtc_state *master_crtc_state;
12010         struct intel_crtc_state *master_pipe_config;
12011         int i, tile_group_id;
12012
12013         if (INTEL_GEN(dev_priv) < 11)
12014                 return 0;
12015
12016         /*
12017          * In case of tiled displays there could be one or more slaves but there is
12018          * only one master. Lets make the CRTC used by the connector corresponding
12019          * to the last horizonal and last vertical tile a master/genlock CRTC.
12020          * All the other CRTCs corresponding to other tiles of the same Tile group
12021          * are the slave CRTCs and hold a pointer to their genlock CRTC.
12022          */
12023         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12024                 if (connector_state->crtc != crtc)
12025                         continue;
12026                 if (!connector->has_tile)
12027                         continue;
12028                 if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
12029                     crtc_state->base.mode.vdisplay != connector->tile_v_size)
12030                         return 0;
12031                 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12032                     connector->tile_v_loc == connector->num_v_tile - 1)
12033                         continue;
12034                 crtc_state->sync_mode_slaves_mask = 0;
12035                 tile_group_id = connector->tile_group->id;
12036                 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12037                 drm_for_each_connector_iter(master_connector, &conn_iter) {
12038                         struct drm_connector_state *master_conn_state = NULL;
12039
12040                         if (!master_connector->has_tile)
12041                                 continue;
12042                         if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12043                             master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12044                                 continue;
12045                         if (master_connector->tile_group->id != tile_group_id)
12046                                 continue;
12047
12048                         master_conn_state = drm_atomic_get_connector_state(&state->base,
12049                                                                            master_connector);
12050                         if (IS_ERR(master_conn_state)) {
12051                                 drm_connector_list_iter_end(&conn_iter);
12052                                 return PTR_ERR(master_conn_state);
12053                         }
12054                         if (master_conn_state->crtc) {
12055                                 master_crtc = master_conn_state->crtc;
12056                                 break;
12057                         }
12058                 }
12059                 drm_connector_list_iter_end(&conn_iter);
12060
12061                 if (!master_crtc) {
12062                         DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12063                                       connector_state->crtc->base.id);
12064                         return -EINVAL;
12065                 }
12066
12067                 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12068                                                               master_crtc);
12069                 if (IS_ERR(master_crtc_state))
12070                         return PTR_ERR(master_crtc_state);
12071
12072                 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12073                 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12074                 master_pipe_config->sync_mode_slaves_mask |=
12075                         BIT(crtc_state->cpu_transcoder);
12076                 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12077                               transcoder_name(crtc_state->master_transcoder),
12078                               crtc_state->base.crtc->base.id,
12079                               master_pipe_config->sync_mode_slaves_mask);
12080         }
12081
12082         return 0;
12083 }
12084
12085 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12086                                    struct intel_crtc *crtc)
12087 {
12088         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12089         struct intel_crtc_state *crtc_state =
12090                 intel_atomic_get_new_crtc_state(state, crtc);
12091         bool mode_changed = needs_modeset(crtc_state);
12092         int ret;
12093
12094         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12095             mode_changed && !crtc_state->base.active)
12096                 crtc_state->update_wm_post = true;
12097
12098         if (mode_changed && crtc_state->base.enable &&
12099             dev_priv->display.crtc_compute_clock &&
12100             !WARN_ON(crtc_state->shared_dpll)) {
12101                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12102                 if (ret)
12103                         return ret;
12104         }
12105
12106         /*
12107          * May need to update pipe gamma enable bits
12108          * when C8 planes are getting enabled/disabled.
12109          */
12110         if (c8_planes_changed(crtc_state))
12111                 crtc_state->base.color_mgmt_changed = true;
12112
12113         if (mode_changed || crtc_state->update_pipe ||
12114             crtc_state->base.color_mgmt_changed) {
12115                 ret = intel_color_check(crtc_state);
12116                 if (ret)
12117                         return ret;
12118         }
12119
12120         ret = 0;
12121         if (dev_priv->display.compute_pipe_wm) {
12122                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12123                 if (ret) {
12124                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12125                         return ret;
12126                 }
12127         }
12128
12129         if (dev_priv->display.compute_intermediate_wm) {
12130                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12131                         return 0;
12132
12133                 /*
12134                  * Calculate 'intermediate' watermarks that satisfy both the
12135                  * old state and the new state.  We can program these
12136                  * immediately.
12137                  */
12138                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12139                 if (ret) {
12140                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12141                         return ret;
12142                 }
12143         }
12144
12145         if (INTEL_GEN(dev_priv) >= 9) {
12146                 if (mode_changed || crtc_state->update_pipe)
12147                         ret = skl_update_scaler_crtc(crtc_state);
12148                 if (!ret)
12149                         ret = intel_atomic_setup_scalers(dev_priv, crtc,
12150                                                          crtc_state);
12151         }
12152
12153         if (HAS_IPS(dev_priv))
12154                 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12155
12156         return ret;
12157 }
12158
12159 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12160 {
12161         struct intel_connector *connector;
12162         struct drm_connector_list_iter conn_iter;
12163
12164         drm_connector_list_iter_begin(dev, &conn_iter);
12165         for_each_intel_connector_iter(connector, &conn_iter) {
12166                 if (connector->base.state->crtc)
12167                         drm_connector_put(&connector->base);
12168
12169                 if (connector->base.encoder) {
12170                         connector->base.state->best_encoder =
12171                                 connector->base.encoder;
12172                         connector->base.state->crtc =
12173                                 connector->base.encoder->crtc;
12174
12175                         drm_connector_get(&connector->base);
12176                 } else {
12177                         connector->base.state->best_encoder = NULL;
12178                         connector->base.state->crtc = NULL;
12179                 }
12180         }
12181         drm_connector_list_iter_end(&conn_iter);
12182 }
12183
12184 static int
12185 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12186                       struct intel_crtc_state *pipe_config)
12187 {
12188         struct drm_connector *connector = conn_state->connector;
12189         const struct drm_display_info *info = &connector->display_info;
12190         int bpp;
12191
12192         switch (conn_state->max_bpc) {
12193         case 6 ... 7:
12194                 bpp = 6 * 3;
12195                 break;
12196         case 8 ... 9:
12197                 bpp = 8 * 3;
12198                 break;
12199         case 10 ... 11:
12200                 bpp = 10 * 3;
12201                 break;
12202         case 12:
12203                 bpp = 12 * 3;
12204                 break;
12205         default:
12206                 return -EINVAL;
12207         }
12208
12209         if (bpp < pipe_config->pipe_bpp) {
12210                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12211                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12212                               connector->base.id, connector->name,
12213                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12214                               pipe_config->pipe_bpp);
12215
12216                 pipe_config->pipe_bpp = bpp;
12217         }
12218
12219         return 0;
12220 }
12221
12222 static int
12223 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12224                           struct intel_crtc_state *pipe_config)
12225 {
12226         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12227         struct drm_atomic_state *state = pipe_config->base.state;
12228         struct drm_connector *connector;
12229         struct drm_connector_state *connector_state;
12230         int bpp, i;
12231
12232         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12233             IS_CHERRYVIEW(dev_priv)))
12234                 bpp = 10*3;
12235         else if (INTEL_GEN(dev_priv) >= 5)
12236                 bpp = 12*3;
12237         else
12238                 bpp = 8*3;
12239
12240         pipe_config->pipe_bpp = bpp;
12241
12242         /* Clamp display bpp to connector max bpp */
12243         for_each_new_connector_in_state(state, connector, connector_state, i) {
12244                 int ret;
12245
12246                 if (connector_state->crtc != &crtc->base)
12247                         continue;
12248
12249                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12250                 if (ret)
12251                         return ret;
12252         }
12253
12254         return 0;
12255 }
12256
12257 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12258 {
12259         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12260                       "type: 0x%x flags: 0x%x\n",
12261                       mode->crtc_clock,
12262                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12263                       mode->crtc_hsync_end, mode->crtc_htotal,
12264                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12265                       mode->crtc_vsync_end, mode->crtc_vtotal,
12266                       mode->type, mode->flags);
12267 }
12268
12269 static inline void
12270 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12271                       const char *id, unsigned int lane_count,
12272                       const struct intel_link_m_n *m_n)
12273 {
12274         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12275                       id, lane_count,
12276                       m_n->gmch_m, m_n->gmch_n,
12277                       m_n->link_m, m_n->link_n, m_n->tu);
12278 }
12279
12280 static void
12281 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12282                      const union hdmi_infoframe *frame)
12283 {
12284         if ((drm_debug & DRM_UT_KMS) == 0)
12285                 return;
12286
12287         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12288 }
12289
12290 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12291
12292 static const char * const output_type_str[] = {
12293         OUTPUT_TYPE(UNUSED),
12294         OUTPUT_TYPE(ANALOG),
12295         OUTPUT_TYPE(DVO),
12296         OUTPUT_TYPE(SDVO),
12297         OUTPUT_TYPE(LVDS),
12298         OUTPUT_TYPE(TVOUT),
12299         OUTPUT_TYPE(HDMI),
12300         OUTPUT_TYPE(DP),
12301         OUTPUT_TYPE(EDP),
12302         OUTPUT_TYPE(DSI),
12303         OUTPUT_TYPE(DDI),
12304         OUTPUT_TYPE(DP_MST),
12305 };
12306
12307 #undef OUTPUT_TYPE
12308
12309 static void snprintf_output_types(char *buf, size_t len,
12310                                   unsigned int output_types)
12311 {
12312         char *str = buf;
12313         int i;
12314
12315         str[0] = '\0';
12316
12317         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12318                 int r;
12319
12320                 if ((output_types & BIT(i)) == 0)
12321                         continue;
12322
12323                 r = snprintf(str, len, "%s%s",
12324                              str != buf ? "," : "", output_type_str[i]);
12325                 if (r >= len)
12326                         break;
12327                 str += r;
12328                 len -= r;
12329
12330                 output_types &= ~BIT(i);
12331         }
12332
12333         WARN_ON_ONCE(output_types != 0);
12334 }
12335
12336 static const char * const output_format_str[] = {
12337         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12338         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12339         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12340         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12341 };
12342
12343 static const char *output_formats(enum intel_output_format format)
12344 {
12345         if (format >= ARRAY_SIZE(output_format_str))
12346                 format = INTEL_OUTPUT_FORMAT_INVALID;
12347         return output_format_str[format];
12348 }
12349
12350 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12351 {
12352         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12353         const struct drm_framebuffer *fb = plane_state->base.fb;
12354         struct drm_format_name_buf format_name;
12355
12356         if (!fb) {
12357                 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12358                               plane->base.base.id, plane->base.name,
12359                               yesno(plane_state->base.visible));
12360                 return;
12361         }
12362
12363         DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12364                       plane->base.base.id, plane->base.name,
12365                       fb->base.id, fb->width, fb->height,
12366                       drm_get_format_name(fb->format->format, &format_name),
12367                       yesno(plane_state->base.visible));
12368         DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12369                       plane_state->base.rotation, plane_state->scaler_id);
12370         if (plane_state->base.visible)
12371                 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12372                               DRM_RECT_FP_ARG(&plane_state->base.src),
12373                               DRM_RECT_ARG(&plane_state->base.dst));
12374 }
12375
12376 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12377                                    struct intel_atomic_state *state,
12378                                    const char *context)
12379 {
12380         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
12381         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12382         const struct intel_plane_state *plane_state;
12383         struct intel_plane *plane;
12384         char buf[64];
12385         int i;
12386
12387         DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12388                       crtc->base.base.id, crtc->base.name,
12389                       yesno(pipe_config->base.enable), context);
12390
12391         if (!pipe_config->base.enable)
12392                 goto dump_planes;
12393
12394         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12395         DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12396                       yesno(pipe_config->base.active),
12397                       buf, pipe_config->output_types,
12398                       output_formats(pipe_config->output_format));
12399
12400         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12401                       transcoder_name(pipe_config->cpu_transcoder),
12402                       pipe_config->pipe_bpp, pipe_config->dither);
12403
12404         if (pipe_config->has_pch_encoder)
12405                 intel_dump_m_n_config(pipe_config, "fdi",
12406                                       pipe_config->fdi_lanes,
12407                                       &pipe_config->fdi_m_n);
12408
12409         if (intel_crtc_has_dp_encoder(pipe_config)) {
12410                 intel_dump_m_n_config(pipe_config, "dp m_n",
12411                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12412                 if (pipe_config->has_drrs)
12413                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12414                                               pipe_config->lane_count,
12415                                               &pipe_config->dp_m2_n2);
12416         }
12417
12418         DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12419                       pipe_config->has_audio, pipe_config->has_infoframe,
12420                       pipe_config->infoframes.enable);
12421
12422         if (pipe_config->infoframes.enable &
12423             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12424                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12425         if (pipe_config->infoframes.enable &
12426             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12427                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12428         if (pipe_config->infoframes.enable &
12429             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12430                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12431         if (pipe_config->infoframes.enable &
12432             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12433                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12434
12435         DRM_DEBUG_KMS("requested mode:\n");
12436         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12437         DRM_DEBUG_KMS("adjusted mode:\n");
12438         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12439         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12440         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12441                       pipe_config->port_clock,
12442                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12443                       pipe_config->pixel_rate);
12444
12445         if (INTEL_GEN(dev_priv) >= 9)
12446                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12447                               crtc->num_scalers,
12448                               pipe_config->scaler_state.scaler_users,
12449                               pipe_config->scaler_state.scaler_id);
12450
12451         if (HAS_GMCH(dev_priv))
12452                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12453                               pipe_config->gmch_pfit.control,
12454                               pipe_config->gmch_pfit.pgm_ratios,
12455                               pipe_config->gmch_pfit.lvds_border_bits);
12456         else
12457                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12458                               pipe_config->pch_pfit.pos,
12459                               pipe_config->pch_pfit.size,
12460                               enableddisabled(pipe_config->pch_pfit.enabled),
12461                               yesno(pipe_config->pch_pfit.force_thru));
12462
12463         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12464                       pipe_config->ips_enabled, pipe_config->double_wide);
12465
12466         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12467
12468         if (IS_CHERRYVIEW(dev_priv))
12469                 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12470                               pipe_config->cgm_mode, pipe_config->gamma_mode,
12471                               pipe_config->gamma_enable, pipe_config->csc_enable);
12472         else
12473                 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12474                               pipe_config->csc_mode, pipe_config->gamma_mode,
12475                               pipe_config->gamma_enable, pipe_config->csc_enable);
12476
12477 dump_planes:
12478         if (!state)
12479                 return;
12480
12481         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12482                 if (plane->pipe == crtc->pipe)
12483                         intel_dump_plane_state(plane_state);
12484         }
12485 }
12486
12487 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12488 {
12489         struct drm_device *dev = state->base.dev;
12490         struct drm_connector *connector;
12491         struct drm_connector_list_iter conn_iter;
12492         unsigned int used_ports = 0;
12493         unsigned int used_mst_ports = 0;
12494         bool ret = true;
12495
12496         /*
12497          * We're going to peek into connector->state,
12498          * hence connection_mutex must be held.
12499          */
12500         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12501
12502         /*
12503          * Walk the connector list instead of the encoder
12504          * list to detect the problem on ddi platforms
12505          * where there's just one encoder per digital port.
12506          */
12507         drm_connector_list_iter_begin(dev, &conn_iter);
12508         drm_for_each_connector_iter(connector, &conn_iter) {
12509                 struct drm_connector_state *connector_state;
12510                 struct intel_encoder *encoder;
12511
12512                 connector_state =
12513                         drm_atomic_get_new_connector_state(&state->base,
12514                                                            connector);
12515                 if (!connector_state)
12516                         connector_state = connector->state;
12517
12518                 if (!connector_state->best_encoder)
12519                         continue;
12520
12521                 encoder = to_intel_encoder(connector_state->best_encoder);
12522
12523                 WARN_ON(!connector_state->crtc);
12524
12525                 switch (encoder->type) {
12526                         unsigned int port_mask;
12527                 case INTEL_OUTPUT_DDI:
12528                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12529                                 break;
12530                         /* else, fall through */
12531                 case INTEL_OUTPUT_DP:
12532                 case INTEL_OUTPUT_HDMI:
12533                 case INTEL_OUTPUT_EDP:
12534                         port_mask = 1 << encoder->port;
12535
12536                         /* the same port mustn't appear more than once */
12537                         if (used_ports & port_mask)
12538                                 ret = false;
12539
12540                         used_ports |= port_mask;
12541                         break;
12542                 case INTEL_OUTPUT_DP_MST:
12543                         used_mst_ports |=
12544                                 1 << encoder->port;
12545                         break;
12546                 default:
12547                         break;
12548                 }
12549         }
12550         drm_connector_list_iter_end(&conn_iter);
12551
12552         /* can't mix MST and SST/HDMI on the same port */
12553         if (used_ports & used_mst_ports)
12554                 return false;
12555
12556         return ret;
12557 }
12558
12559 static int
12560 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12561 {
12562         struct drm_i915_private *dev_priv =
12563                 to_i915(crtc_state->base.crtc->dev);
12564         struct intel_crtc_state *saved_state;
12565
12566         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12567         if (!saved_state)
12568                 return -ENOMEM;
12569
12570         /* FIXME: before the switch to atomic started, a new pipe_config was
12571          * kzalloc'd. Code that depends on any field being zero should be
12572          * fixed, so that the crtc_state can be safely duplicated. For now,
12573          * only fields that are know to not cause problems are preserved. */
12574
12575         saved_state->scaler_state = crtc_state->scaler_state;
12576         saved_state->shared_dpll = crtc_state->shared_dpll;
12577         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12578         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12579                sizeof(saved_state->icl_port_dplls));
12580         saved_state->crc_enabled = crtc_state->crc_enabled;
12581         if (IS_G4X(dev_priv) ||
12582             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12583                 saved_state->wm = crtc_state->wm;
12584         /*
12585          * Save the slave bitmask which gets filled for master crtc state during
12586          * slave atomic check call.
12587          */
12588         if (is_trans_port_sync_master(crtc_state))
12589                 saved_state->sync_mode_slaves_mask =
12590                         crtc_state->sync_mode_slaves_mask;
12591
12592         /* Keep base drm_crtc_state intact, only clear our extended struct */
12593         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
12594         memcpy(&crtc_state->base + 1, &saved_state->base + 1,
12595                sizeof(*crtc_state) - sizeof(crtc_state->base));
12596
12597         kfree(saved_state);
12598         return 0;
12599 }
12600
12601 static int
12602 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12603 {
12604         struct drm_crtc *crtc = pipe_config->base.crtc;
12605         struct drm_atomic_state *state = pipe_config->base.state;
12606         struct intel_encoder *encoder;
12607         struct drm_connector *connector;
12608         struct drm_connector_state *connector_state;
12609         int base_bpp, ret;
12610         int i;
12611         bool retry = true;
12612
12613         ret = clear_intel_crtc_state(pipe_config);
12614         if (ret)
12615                 return ret;
12616
12617         pipe_config->cpu_transcoder =
12618                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12619
12620         /*
12621          * Sanitize sync polarity flags based on requested ones. If neither
12622          * positive or negative polarity is requested, treat this as meaning
12623          * negative polarity.
12624          */
12625         if (!(pipe_config->base.adjusted_mode.flags &
12626               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12627                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12628
12629         if (!(pipe_config->base.adjusted_mode.flags &
12630               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12631                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12632
12633         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12634                                         pipe_config);
12635         if (ret)
12636                 return ret;
12637
12638         base_bpp = pipe_config->pipe_bpp;
12639
12640         /*
12641          * Determine the real pipe dimensions. Note that stereo modes can
12642          * increase the actual pipe size due to the frame doubling and
12643          * insertion of additional space for blanks between the frame. This
12644          * is stored in the crtc timings. We use the requested mode to do this
12645          * computation to clearly distinguish it from the adjusted mode, which
12646          * can be changed by the connectors in the below retry loop.
12647          */
12648         drm_mode_get_hv_timing(&pipe_config->base.mode,
12649                                &pipe_config->pipe_src_w,
12650                                &pipe_config->pipe_src_h);
12651
12652         for_each_new_connector_in_state(state, connector, connector_state, i) {
12653                 if (connector_state->crtc != crtc)
12654                         continue;
12655
12656                 encoder = to_intel_encoder(connector_state->best_encoder);
12657
12658                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12659                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12660                         return -EINVAL;
12661                 }
12662
12663                 /*
12664                  * Determine output_types before calling the .compute_config()
12665                  * hooks so that the hooks can use this information safely.
12666                  */
12667                 if (encoder->compute_output_type)
12668                         pipe_config->output_types |=
12669                                 BIT(encoder->compute_output_type(encoder, pipe_config,
12670                                                                  connector_state));
12671                 else
12672                         pipe_config->output_types |= BIT(encoder->type);
12673         }
12674
12675 encoder_retry:
12676         /* Ensure the port clock defaults are reset when retrying. */
12677         pipe_config->port_clock = 0;
12678         pipe_config->pixel_multiplier = 1;
12679
12680         /* Fill in default crtc timings, allow encoders to overwrite them. */
12681         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12682                               CRTC_STEREO_DOUBLE);
12683
12684         /* Set the crtc_state defaults for trans_port_sync */
12685         pipe_config->master_transcoder = INVALID_TRANSCODER;
12686         ret = icl_add_sync_mode_crtcs(pipe_config);
12687         if (ret) {
12688                 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12689                               ret);
12690                 return ret;
12691         }
12692
12693         /* Pass our mode to the connectors and the CRTC to give them a chance to
12694          * adjust it according to limitations or connector properties, and also
12695          * a chance to reject the mode entirely.
12696          */
12697         for_each_new_connector_in_state(state, connector, connector_state, i) {
12698                 if (connector_state->crtc != crtc)
12699                         continue;
12700
12701                 encoder = to_intel_encoder(connector_state->best_encoder);
12702                 ret = encoder->compute_config(encoder, pipe_config,
12703                                               connector_state);
12704                 if (ret < 0) {
12705                         if (ret != -EDEADLK)
12706                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12707                                               ret);
12708                         return ret;
12709                 }
12710         }
12711
12712         /* Set default port clock if not overwritten by the encoder. Needs to be
12713          * done afterwards in case the encoder adjusts the mode. */
12714         if (!pipe_config->port_clock)
12715                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12716                         * pipe_config->pixel_multiplier;
12717
12718         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12719         if (ret == -EDEADLK)
12720                 return ret;
12721         if (ret < 0) {
12722                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12723                 return ret;
12724         }
12725
12726         if (ret == RETRY) {
12727                 if (WARN(!retry, "loop in pipe configuration computation\n"))
12728                         return -EINVAL;
12729
12730                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12731                 retry = false;
12732                 goto encoder_retry;
12733         }
12734
12735         /* Dithering seems to not pass-through bits correctly when it should, so
12736          * only enable it on 6bpc panels and when its not a compliance
12737          * test requesting 6bpc video pattern.
12738          */
12739         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12740                 !pipe_config->dither_force_disable;
12741         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12742                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12743
12744         return 0;
12745 }
12746
12747 bool intel_fuzzy_clock_check(int clock1, int clock2)
12748 {
12749         int diff;
12750
12751         if (clock1 == clock2)
12752                 return true;
12753
12754         if (!clock1 || !clock2)
12755                 return false;
12756
12757         diff = abs(clock1 - clock2);
12758
12759         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12760                 return true;
12761
12762         return false;
12763 }
12764
12765 static bool
12766 intel_compare_m_n(unsigned int m, unsigned int n,
12767                   unsigned int m2, unsigned int n2,
12768                   bool exact)
12769 {
12770         if (m == m2 && n == n2)
12771                 return true;
12772
12773         if (exact || !m || !n || !m2 || !n2)
12774                 return false;
12775
12776         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12777
12778         if (n > n2) {
12779                 while (n > n2) {
12780                         m2 <<= 1;
12781                         n2 <<= 1;
12782                 }
12783         } else if (n < n2) {
12784                 while (n < n2) {
12785                         m <<= 1;
12786                         n <<= 1;
12787                 }
12788         }
12789
12790         if (n != n2)
12791                 return false;
12792
12793         return intel_fuzzy_clock_check(m, m2);
12794 }
12795
12796 static bool
12797 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12798                        const struct intel_link_m_n *m2_n2,
12799                        bool exact)
12800 {
12801         return m_n->tu == m2_n2->tu &&
12802                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12803                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12804                 intel_compare_m_n(m_n->link_m, m_n->link_n,
12805                                   m2_n2->link_m, m2_n2->link_n, exact);
12806 }
12807
12808 static bool
12809 intel_compare_infoframe(const union hdmi_infoframe *a,
12810                         const union hdmi_infoframe *b)
12811 {
12812         return memcmp(a, b, sizeof(*a)) == 0;
12813 }
12814
12815 static void
12816 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12817                                bool fastset, const char *name,
12818                                const union hdmi_infoframe *a,
12819                                const union hdmi_infoframe *b)
12820 {
12821         if (fastset) {
12822                 if ((drm_debug & DRM_UT_KMS) == 0)
12823                         return;
12824
12825                 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12826                 DRM_DEBUG_KMS("expected:\n");
12827                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12828                 DRM_DEBUG_KMS("found:\n");
12829                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12830         } else {
12831                 DRM_ERROR("mismatch in %s infoframe\n", name);
12832                 DRM_ERROR("expected:\n");
12833                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12834                 DRM_ERROR("found:\n");
12835                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12836         }
12837 }
12838
12839 static void __printf(4, 5)
12840 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12841                      const char *name, const char *format, ...)
12842 {
12843         struct va_format vaf;
12844         va_list args;
12845
12846         va_start(args, format);
12847         vaf.fmt = format;
12848         vaf.va = &args;
12849
12850         if (fastset)
12851                 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12852                               crtc->base.base.id, crtc->base.name, name, &vaf);
12853         else
12854                 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
12855                           crtc->base.base.id, crtc->base.name, name, &vaf);
12856
12857         va_end(args);
12858 }
12859
12860 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12861 {
12862         if (i915_modparams.fastboot != -1)
12863                 return i915_modparams.fastboot;
12864
12865         /* Enable fastboot by default on Skylake and newer */
12866         if (INTEL_GEN(dev_priv) >= 9)
12867                 return true;
12868
12869         /* Enable fastboot by default on VLV and CHV */
12870         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12871                 return true;
12872
12873         /* Disabled by default on all others */
12874         return false;
12875 }
12876
12877 static bool
12878 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
12879                           const struct intel_crtc_state *pipe_config,
12880                           bool fastset)
12881 {
12882         struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
12883         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
12884         bool ret = true;
12885         u32 bp_gamma = 0;
12886         bool fixup_inherited = fastset &&
12887                 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12888                 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
12889
12890         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12891                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12892                 ret = false;
12893         }
12894
12895 #define PIPE_CONF_CHECK_X(name) do { \
12896         if (current_config->name != pipe_config->name) { \
12897                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12898                                      "(expected 0x%08x, found 0x%08x)", \
12899                                      current_config->name, \
12900                                      pipe_config->name); \
12901                 ret = false; \
12902         } \
12903 } while (0)
12904
12905 #define PIPE_CONF_CHECK_I(name) do { \
12906         if (current_config->name != pipe_config->name) { \
12907                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12908                                      "(expected %i, found %i)", \
12909                                      current_config->name, \
12910                                      pipe_config->name); \
12911                 ret = false; \
12912         } \
12913 } while (0)
12914
12915 #define PIPE_CONF_CHECK_BOOL(name) do { \
12916         if (current_config->name != pipe_config->name) { \
12917                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
12918                                      "(expected %s, found %s)", \
12919                                      yesno(current_config->name), \
12920                                      yesno(pipe_config->name)); \
12921                 ret = false; \
12922         } \
12923 } while (0)
12924
12925 /*
12926  * Checks state where we only read out the enabling, but not the entire
12927  * state itself (like full infoframes or ELD for audio). These states
12928  * require a full modeset on bootup to fix up.
12929  */
12930 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12931         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12932                 PIPE_CONF_CHECK_BOOL(name); \
12933         } else { \
12934                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12935                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
12936                                      yesno(current_config->name), \
12937                                      yesno(pipe_config->name)); \
12938                 ret = false; \
12939         } \
12940 } while (0)
12941
12942 #define PIPE_CONF_CHECK_P(name) do { \
12943         if (current_config->name != pipe_config->name) { \
12944                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12945                                      "(expected %p, found %p)", \
12946                                      current_config->name, \
12947                                      pipe_config->name); \
12948                 ret = false; \
12949         } \
12950 } while (0)
12951
12952 #define PIPE_CONF_CHECK_M_N(name) do { \
12953         if (!intel_compare_link_m_n(&current_config->name, \
12954                                     &pipe_config->name,\
12955                                     !fastset)) { \
12956                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12957                                      "(expected tu %i gmch %i/%i link %i/%i, " \
12958                                      "found tu %i, gmch %i/%i link %i/%i)", \
12959                                      current_config->name.tu, \
12960                                      current_config->name.gmch_m, \
12961                                      current_config->name.gmch_n, \
12962                                      current_config->name.link_m, \
12963                                      current_config->name.link_n, \
12964                                      pipe_config->name.tu, \
12965                                      pipe_config->name.gmch_m, \
12966                                      pipe_config->name.gmch_n, \
12967                                      pipe_config->name.link_m, \
12968                                      pipe_config->name.link_n); \
12969                 ret = false; \
12970         } \
12971 } while (0)
12972
12973 /* This is required for BDW+ where there is only one set of registers for
12974  * switching between high and low RR.
12975  * This macro can be used whenever a comparison has to be made between one
12976  * hw state and multiple sw state variables.
12977  */
12978 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12979         if (!intel_compare_link_m_n(&current_config->name, \
12980                                     &pipe_config->name, !fastset) && \
12981             !intel_compare_link_m_n(&current_config->alt_name, \
12982                                     &pipe_config->name, !fastset)) { \
12983                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12984                                      "(expected tu %i gmch %i/%i link %i/%i, " \
12985                                      "or tu %i gmch %i/%i link %i/%i, " \
12986                                      "found tu %i, gmch %i/%i link %i/%i)", \
12987                                      current_config->name.tu, \
12988                                      current_config->name.gmch_m, \
12989                                      current_config->name.gmch_n, \
12990                                      current_config->name.link_m, \
12991                                      current_config->name.link_n, \
12992                                      current_config->alt_name.tu, \
12993                                      current_config->alt_name.gmch_m, \
12994                                      current_config->alt_name.gmch_n, \
12995                                      current_config->alt_name.link_m, \
12996                                      current_config->alt_name.link_n, \
12997                                      pipe_config->name.tu, \
12998                                      pipe_config->name.gmch_m, \
12999                                      pipe_config->name.gmch_n, \
13000                                      pipe_config->name.link_m, \
13001                                      pipe_config->name.link_n); \
13002                 ret = false; \
13003         } \
13004 } while (0)
13005
13006 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13007         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13008                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13009                                      "(%x) (expected %i, found %i)", \
13010                                      (mask), \
13011                                      current_config->name & (mask), \
13012                                      pipe_config->name & (mask)); \
13013                 ret = false; \
13014         } \
13015 } while (0)
13016
13017 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13018         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13019                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13020                                      "(expected %i, found %i)", \
13021                                      current_config->name, \
13022                                      pipe_config->name); \
13023                 ret = false; \
13024         } \
13025 } while (0)
13026
13027 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13028         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13029                                      &pipe_config->infoframes.name)) { \
13030                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13031                                                &current_config->infoframes.name, \
13032                                                &pipe_config->infoframes.name); \
13033                 ret = false; \
13034         } \
13035 } while (0)
13036
13037 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13038         if (current_config->name1 != pipe_config->name1) { \
13039                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13040                                 "(expected %i, found %i, won't compare lut values)", \
13041                                 current_config->name1, \
13042                                 pipe_config->name1); \
13043                 ret = false;\
13044         } else { \
13045                 if (!intel_color_lut_equal(current_config->name2, \
13046                                         pipe_config->name2, pipe_config->name1, \
13047                                         bit_precision)) { \
13048                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13049                                         "hw_state doesn't match sw_state"); \
13050                         ret = false; \
13051                 } \
13052         } \
13053 } while (0)
13054
13055 #define PIPE_CONF_QUIRK(quirk) \
13056         ((current_config->quirks | pipe_config->quirks) & (quirk))
13057
13058         PIPE_CONF_CHECK_I(cpu_transcoder);
13059
13060         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13061         PIPE_CONF_CHECK_I(fdi_lanes);
13062         PIPE_CONF_CHECK_M_N(fdi_m_n);
13063
13064         PIPE_CONF_CHECK_I(lane_count);
13065         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13066
13067         if (INTEL_GEN(dev_priv) < 8) {
13068                 PIPE_CONF_CHECK_M_N(dp_m_n);
13069
13070                 if (current_config->has_drrs)
13071                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13072         } else
13073                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13074
13075         PIPE_CONF_CHECK_X(output_types);
13076
13077         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13078         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13079         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13080         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13081         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13082         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13083
13084         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13085         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13086         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13087         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13088         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13089         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13090
13091         PIPE_CONF_CHECK_I(pixel_multiplier);
13092         PIPE_CONF_CHECK_I(output_format);
13093         PIPE_CONF_CHECK_I(dc3co_exitline);
13094         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13095         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13096             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13097                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13098
13099         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13100         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13101         PIPE_CONF_CHECK_BOOL(has_infoframe);
13102         PIPE_CONF_CHECK_BOOL(fec_enable);
13103
13104         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13105
13106         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13107                               DRM_MODE_FLAG_INTERLACE);
13108
13109         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13110                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13111                                       DRM_MODE_FLAG_PHSYNC);
13112                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13113                                       DRM_MODE_FLAG_NHSYNC);
13114                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13115                                       DRM_MODE_FLAG_PVSYNC);
13116                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13117                                       DRM_MODE_FLAG_NVSYNC);
13118         }
13119
13120         PIPE_CONF_CHECK_X(gmch_pfit.control);
13121         /* pfit ratios are autocomputed by the hw on gen4+ */
13122         if (INTEL_GEN(dev_priv) < 4)
13123                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13124         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13125
13126         /*
13127          * Changing the EDP transcoder input mux
13128          * (A_ONOFF vs. A_ON) requires a full modeset.
13129          */
13130         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13131
13132         if (!fastset) {
13133                 PIPE_CONF_CHECK_I(pipe_src_w);
13134                 PIPE_CONF_CHECK_I(pipe_src_h);
13135
13136                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13137                 if (current_config->pch_pfit.enabled) {
13138                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13139                         PIPE_CONF_CHECK_X(pch_pfit.size);
13140                 }
13141
13142                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13143                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13144
13145                 PIPE_CONF_CHECK_X(gamma_mode);
13146                 if (IS_CHERRYVIEW(dev_priv))
13147                         PIPE_CONF_CHECK_X(cgm_mode);
13148                 else
13149                         PIPE_CONF_CHECK_X(csc_mode);
13150                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13151                 PIPE_CONF_CHECK_BOOL(csc_enable);
13152
13153                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13154                 if (bp_gamma)
13155                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
13156
13157         }
13158
13159         PIPE_CONF_CHECK_BOOL(double_wide);
13160
13161         PIPE_CONF_CHECK_P(shared_dpll);
13162         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13163         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13164         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13165         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13166         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13167         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13168         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13169         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13170         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13171         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13172         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13173         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13174         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13175         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13176         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13177         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13178         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13179         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13180         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13181         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13182         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13183         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13184         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13185         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13186         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13187         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13188         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13189         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13190         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13191         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13192         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13193
13194         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13195         PIPE_CONF_CHECK_X(dsi_pll.div);
13196
13197         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13198                 PIPE_CONF_CHECK_I(pipe_bpp);
13199
13200         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13201         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13202
13203         PIPE_CONF_CHECK_I(min_voltage_level);
13204
13205         PIPE_CONF_CHECK_X(infoframes.enable);
13206         PIPE_CONF_CHECK_X(infoframes.gcp);
13207         PIPE_CONF_CHECK_INFOFRAME(avi);
13208         PIPE_CONF_CHECK_INFOFRAME(spd);
13209         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13210         PIPE_CONF_CHECK_INFOFRAME(drm);
13211
13212         PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13213         PIPE_CONF_CHECK_I(master_transcoder);
13214
13215 #undef PIPE_CONF_CHECK_X
13216 #undef PIPE_CONF_CHECK_I
13217 #undef PIPE_CONF_CHECK_BOOL
13218 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13219 #undef PIPE_CONF_CHECK_P
13220 #undef PIPE_CONF_CHECK_FLAGS
13221 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13222 #undef PIPE_CONF_CHECK_COLOR_LUT
13223 #undef PIPE_CONF_QUIRK
13224
13225         return ret;
13226 }
13227
13228 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13229                                            const struct intel_crtc_state *pipe_config)
13230 {
13231         if (pipe_config->has_pch_encoder) {
13232                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13233                                                             &pipe_config->fdi_m_n);
13234                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13235
13236                 /*
13237                  * FDI already provided one idea for the dotclock.
13238                  * Yell if the encoder disagrees.
13239                  */
13240                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13241                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13242                      fdi_dotclock, dotclock);
13243         }
13244 }
13245
13246 static void verify_wm_state(struct intel_crtc *crtc,
13247                             struct intel_crtc_state *new_crtc_state)
13248 {
13249         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13250         struct skl_hw_state {
13251                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13252                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13253                 struct skl_ddb_allocation ddb;
13254                 struct skl_pipe_wm wm;
13255         } *hw;
13256         struct skl_ddb_allocation *sw_ddb;
13257         struct skl_pipe_wm *sw_wm;
13258         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13259         const enum pipe pipe = crtc->pipe;
13260         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13261
13262         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
13263                 return;
13264
13265         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13266         if (!hw)
13267                 return;
13268
13269         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13270         sw_wm = &new_crtc_state->wm.skl.optimal;
13271
13272         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13273
13274         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13275         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13276
13277         if (INTEL_GEN(dev_priv) >= 11 &&
13278             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13279                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13280                           sw_ddb->enabled_slices,
13281                           hw->ddb.enabled_slices);
13282
13283         /* planes */
13284         for_each_universal_plane(dev_priv, pipe, plane) {
13285                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13286
13287                 hw_plane_wm = &hw->wm.planes[plane];
13288                 sw_plane_wm = &sw_wm->planes[plane];
13289
13290                 /* Watermarks */
13291                 for (level = 0; level <= max_level; level++) {
13292                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13293                                                 &sw_plane_wm->wm[level]))
13294                                 continue;
13295
13296                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13297                                   pipe_name(pipe), plane + 1, level,
13298                                   sw_plane_wm->wm[level].plane_en,
13299                                   sw_plane_wm->wm[level].plane_res_b,
13300                                   sw_plane_wm->wm[level].plane_res_l,
13301                                   hw_plane_wm->wm[level].plane_en,
13302                                   hw_plane_wm->wm[level].plane_res_b,
13303                                   hw_plane_wm->wm[level].plane_res_l);
13304                 }
13305
13306                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13307                                          &sw_plane_wm->trans_wm)) {
13308                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13309                                   pipe_name(pipe), plane + 1,
13310                                   sw_plane_wm->trans_wm.plane_en,
13311                                   sw_plane_wm->trans_wm.plane_res_b,
13312                                   sw_plane_wm->trans_wm.plane_res_l,
13313                                   hw_plane_wm->trans_wm.plane_en,
13314                                   hw_plane_wm->trans_wm.plane_res_b,
13315                                   hw_plane_wm->trans_wm.plane_res_l);
13316                 }
13317
13318                 /* DDB */
13319                 hw_ddb_entry = &hw->ddb_y[plane];
13320                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13321
13322                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13323                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13324                                   pipe_name(pipe), plane + 1,
13325                                   sw_ddb_entry->start, sw_ddb_entry->end,
13326                                   hw_ddb_entry->start, hw_ddb_entry->end);
13327                 }
13328         }
13329
13330         /*
13331          * cursor
13332          * If the cursor plane isn't active, we may not have updated it's ddb
13333          * allocation. In that case since the ddb allocation will be updated
13334          * once the plane becomes visible, we can skip this check
13335          */
13336         if (1) {
13337                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13338
13339                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13340                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13341
13342                 /* Watermarks */
13343                 for (level = 0; level <= max_level; level++) {
13344                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13345                                                 &sw_plane_wm->wm[level]))
13346                                 continue;
13347
13348                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13349                                   pipe_name(pipe), level,
13350                                   sw_plane_wm->wm[level].plane_en,
13351                                   sw_plane_wm->wm[level].plane_res_b,
13352                                   sw_plane_wm->wm[level].plane_res_l,
13353                                   hw_plane_wm->wm[level].plane_en,
13354                                   hw_plane_wm->wm[level].plane_res_b,
13355                                   hw_plane_wm->wm[level].plane_res_l);
13356                 }
13357
13358                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13359                                          &sw_plane_wm->trans_wm)) {
13360                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13361                                   pipe_name(pipe),
13362                                   sw_plane_wm->trans_wm.plane_en,
13363                                   sw_plane_wm->trans_wm.plane_res_b,
13364                                   sw_plane_wm->trans_wm.plane_res_l,
13365                                   hw_plane_wm->trans_wm.plane_en,
13366                                   hw_plane_wm->trans_wm.plane_res_b,
13367                                   hw_plane_wm->trans_wm.plane_res_l);
13368                 }
13369
13370                 /* DDB */
13371                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13372                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13373
13374                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13375                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13376                                   pipe_name(pipe),
13377                                   sw_ddb_entry->start, sw_ddb_entry->end,
13378                                   hw_ddb_entry->start, hw_ddb_entry->end);
13379                 }
13380         }
13381
13382         kfree(hw);
13383 }
13384
13385 static void
13386 verify_connector_state(struct intel_atomic_state *state,
13387                        struct intel_crtc *crtc)
13388 {
13389         struct drm_connector *connector;
13390         struct drm_connector_state *new_conn_state;
13391         int i;
13392
13393         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13394                 struct drm_encoder *encoder = connector->encoder;
13395                 struct intel_crtc_state *crtc_state = NULL;
13396
13397                 if (new_conn_state->crtc != &crtc->base)
13398                         continue;
13399
13400                 if (crtc)
13401                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13402
13403                 intel_connector_verify_state(crtc_state, new_conn_state);
13404
13405                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13406                      "connector's atomic encoder doesn't match legacy encoder\n");
13407         }
13408 }
13409
13410 static void
13411 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13412 {
13413         struct intel_encoder *encoder;
13414         struct drm_connector *connector;
13415         struct drm_connector_state *old_conn_state, *new_conn_state;
13416         int i;
13417
13418         for_each_intel_encoder(&dev_priv->drm, encoder) {
13419                 bool enabled = false, found = false;
13420                 enum pipe pipe;
13421
13422                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13423                               encoder->base.base.id,
13424                               encoder->base.name);
13425
13426                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13427                                                    new_conn_state, i) {
13428                         if (old_conn_state->best_encoder == &encoder->base)
13429                                 found = true;
13430
13431                         if (new_conn_state->best_encoder != &encoder->base)
13432                                 continue;
13433                         found = enabled = true;
13434
13435                         I915_STATE_WARN(new_conn_state->crtc !=
13436                                         encoder->base.crtc,
13437                              "connector's crtc doesn't match encoder crtc\n");
13438                 }
13439
13440                 if (!found)
13441                         continue;
13442
13443                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13444                      "encoder's enabled state mismatch "
13445                      "(expected %i, found %i)\n",
13446                      !!encoder->base.crtc, enabled);
13447
13448                 if (!encoder->base.crtc) {
13449                         bool active;
13450
13451                         active = encoder->get_hw_state(encoder, &pipe);
13452                         I915_STATE_WARN(active,
13453                              "encoder detached but still enabled on pipe %c.\n",
13454                              pipe_name(pipe));
13455                 }
13456         }
13457 }
13458
13459 static void
13460 verify_crtc_state(struct intel_crtc *crtc,
13461                   struct intel_crtc_state *old_crtc_state,
13462                   struct intel_crtc_state *new_crtc_state)
13463 {
13464         struct drm_device *dev = crtc->base.dev;
13465         struct drm_i915_private *dev_priv = to_i915(dev);
13466         struct intel_encoder *encoder;
13467         struct intel_crtc_state *pipe_config;
13468         struct drm_atomic_state *state;
13469         bool active;
13470
13471         state = old_crtc_state->base.state;
13472         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
13473         pipe_config = old_crtc_state;
13474         memset(pipe_config, 0, sizeof(*pipe_config));
13475         pipe_config->base.crtc = &crtc->base;
13476         pipe_config->base.state = state;
13477
13478         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13479
13480         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13481
13482         /* we keep both pipes enabled on 830 */
13483         if (IS_I830(dev_priv))
13484                 active = new_crtc_state->base.active;
13485
13486         I915_STATE_WARN(new_crtc_state->base.active != active,
13487              "crtc active state doesn't match with hw state "
13488              "(expected %i, found %i)\n", new_crtc_state->base.active, active);
13489
13490         I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
13491              "transitional active state does not match atomic hw state "
13492              "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
13493
13494         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13495                 enum pipe pipe;
13496
13497                 active = encoder->get_hw_state(encoder, &pipe);
13498                 I915_STATE_WARN(active != new_crtc_state->base.active,
13499                         "[ENCODER:%i] active %i with crtc active %i\n",
13500                         encoder->base.base.id, active, new_crtc_state->base.active);
13501
13502                 I915_STATE_WARN(active && crtc->pipe != pipe,
13503                                 "Encoder connected to wrong pipe %c\n",
13504                                 pipe_name(pipe));
13505
13506                 if (active)
13507                         encoder->get_config(encoder, pipe_config);
13508         }
13509
13510         intel_crtc_compute_pixel_rate(pipe_config);
13511
13512         if (!new_crtc_state->base.active)
13513                 return;
13514
13515         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13516
13517         if (!intel_pipe_config_compare(new_crtc_state,
13518                                        pipe_config, false)) {
13519                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13520                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13521                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13522         }
13523 }
13524
13525 static void
13526 intel_verify_planes(struct intel_atomic_state *state)
13527 {
13528         struct intel_plane *plane;
13529         const struct intel_plane_state *plane_state;
13530         int i;
13531
13532         for_each_new_intel_plane_in_state(state, plane,
13533                                           plane_state, i)
13534                 assert_plane(plane, plane_state->planar_slave ||
13535                              plane_state->base.visible);
13536 }
13537
13538 static void
13539 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13540                          struct intel_shared_dpll *pll,
13541                          struct intel_crtc *crtc,
13542                          struct intel_crtc_state *new_crtc_state)
13543 {
13544         struct intel_dpll_hw_state dpll_hw_state;
13545         unsigned int crtc_mask;
13546         bool active;
13547
13548         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13549
13550         DRM_DEBUG_KMS("%s\n", pll->info->name);
13551
13552         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13553
13554         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13555                 I915_STATE_WARN(!pll->on && pll->active_mask,
13556                      "pll in active use but not on in sw tracking\n");
13557                 I915_STATE_WARN(pll->on && !pll->active_mask,
13558                      "pll is on but not used by any active crtc\n");
13559                 I915_STATE_WARN(pll->on != active,
13560                      "pll on state mismatch (expected %i, found %i)\n",
13561                      pll->on, active);
13562         }
13563
13564         if (!crtc) {
13565                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13566                                 "more active pll users than references: %x vs %x\n",
13567                                 pll->active_mask, pll->state.crtc_mask);
13568
13569                 return;
13570         }
13571
13572         crtc_mask = drm_crtc_mask(&crtc->base);
13573
13574         if (new_crtc_state->base.active)
13575                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13576                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13577                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13578         else
13579                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13580                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13581                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13582
13583         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13584                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13585                         crtc_mask, pll->state.crtc_mask);
13586
13587         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13588                                           &dpll_hw_state,
13589                                           sizeof(dpll_hw_state)),
13590                         "pll hw state mismatch\n");
13591 }
13592
13593 static void
13594 verify_shared_dpll_state(struct intel_crtc *crtc,
13595                          struct intel_crtc_state *old_crtc_state,
13596                          struct intel_crtc_state *new_crtc_state)
13597 {
13598         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13599
13600         if (new_crtc_state->shared_dpll)
13601                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13602
13603         if (old_crtc_state->shared_dpll &&
13604             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13605                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13606                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13607
13608                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13609                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13610                                 pipe_name(drm_crtc_index(&crtc->base)));
13611                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13612                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13613                                 pipe_name(drm_crtc_index(&crtc->base)));
13614         }
13615 }
13616
13617 static void
13618 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13619                           struct intel_atomic_state *state,
13620                           struct intel_crtc_state *old_crtc_state,
13621                           struct intel_crtc_state *new_crtc_state)
13622 {
13623         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13624                 return;
13625
13626         verify_wm_state(crtc, new_crtc_state);
13627         verify_connector_state(state, crtc);
13628         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13629         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13630 }
13631
13632 static void
13633 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13634 {
13635         int i;
13636
13637         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13638                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13639 }
13640
13641 static void
13642 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13643                               struct intel_atomic_state *state)
13644 {
13645         verify_encoder_state(dev_priv, state);
13646         verify_connector_state(state, NULL);
13647         verify_disabled_dpll_state(dev_priv);
13648 }
13649
13650 static void
13651 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13652 {
13653         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
13654         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13655         const struct drm_display_mode *adjusted_mode =
13656                 &crtc_state->base.adjusted_mode;
13657
13658         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13659
13660         /*
13661          * The scanline counter increments at the leading edge of hsync.
13662          *
13663          * On most platforms it starts counting from vtotal-1 on the
13664          * first active line. That means the scanline counter value is
13665          * always one less than what we would expect. Ie. just after
13666          * start of vblank, which also occurs at start of hsync (on the
13667          * last active line), the scanline counter will read vblank_start-1.
13668          *
13669          * On gen2 the scanline counter starts counting from 1 instead
13670          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13671          * to keep the value positive), instead of adding one.
13672          *
13673          * On HSW+ the behaviour of the scanline counter depends on the output
13674          * type. For DP ports it behaves like most other platforms, but on HDMI
13675          * there's an extra 1 line difference. So we need to add two instead of
13676          * one to the value.
13677          *
13678          * On VLV/CHV DSI the scanline counter would appear to increment
13679          * approx. 1/3 of a scanline before start of vblank. Unfortunately
13680          * that means we can't tell whether we're in vblank or not while
13681          * we're on that particular line. We must still set scanline_offset
13682          * to 1 so that the vblank timestamps come out correct when we query
13683          * the scanline counter from within the vblank interrupt handler.
13684          * However if queried just before the start of vblank we'll get an
13685          * answer that's slightly in the future.
13686          */
13687         if (IS_GEN(dev_priv, 2)) {
13688                 int vtotal;
13689
13690                 vtotal = adjusted_mode->crtc_vtotal;
13691                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13692                         vtotal /= 2;
13693
13694                 crtc->scanline_offset = vtotal - 1;
13695         } else if (HAS_DDI(dev_priv) &&
13696                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13697                 crtc->scanline_offset = 2;
13698         } else {
13699                 crtc->scanline_offset = 1;
13700         }
13701 }
13702
13703 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13704 {
13705         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13706         struct intel_crtc_state *new_crtc_state;
13707         struct intel_crtc *crtc;
13708         int i;
13709
13710         if (!dev_priv->display.crtc_compute_clock)
13711                 return;
13712
13713         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13714                 if (!needs_modeset(new_crtc_state))
13715                         continue;
13716
13717                 intel_release_shared_dplls(state, crtc);
13718         }
13719 }
13720
13721 /*
13722  * This implements the workaround described in the "notes" section of the mode
13723  * set sequence documentation. When going from no pipes or single pipe to
13724  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13725  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13726  */
13727 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13728 {
13729         struct intel_crtc_state *crtc_state;
13730         struct intel_crtc *crtc;
13731         struct intel_crtc_state *first_crtc_state = NULL;
13732         struct intel_crtc_state *other_crtc_state = NULL;
13733         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13734         int i;
13735
13736         /* look at all crtc's that are going to be enabled in during modeset */
13737         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13738                 if (!crtc_state->base.active ||
13739                     !needs_modeset(crtc_state))
13740                         continue;
13741
13742                 if (first_crtc_state) {
13743                         other_crtc_state = crtc_state;
13744                         break;
13745                 } else {
13746                         first_crtc_state = crtc_state;
13747                         first_pipe = crtc->pipe;
13748                 }
13749         }
13750
13751         /* No workaround needed? */
13752         if (!first_crtc_state)
13753                 return 0;
13754
13755         /* w/a possibly needed, check how many crtc's are already enabled. */
13756         for_each_intel_crtc(state->base.dev, crtc) {
13757                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13758                 if (IS_ERR(crtc_state))
13759                         return PTR_ERR(crtc_state);
13760
13761                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13762
13763                 if (!crtc_state->base.active ||
13764                     needs_modeset(crtc_state))
13765                         continue;
13766
13767                 /* 2 or more enabled crtcs means no need for w/a */
13768                 if (enabled_pipe != INVALID_PIPE)
13769                         return 0;
13770
13771                 enabled_pipe = crtc->pipe;
13772         }
13773
13774         if (enabled_pipe != INVALID_PIPE)
13775                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13776         else if (other_crtc_state)
13777                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13778
13779         return 0;
13780 }
13781
13782 static int intel_modeset_checks(struct intel_atomic_state *state)
13783 {
13784         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13785         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13786         struct intel_crtc *crtc;
13787         int ret, i;
13788
13789         /* keep the current setting */
13790         if (!state->cdclk.force_min_cdclk_changed)
13791                 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13792
13793         state->modeset = true;
13794         state->active_pipes = dev_priv->active_pipes;
13795         state->cdclk.logical = dev_priv->cdclk.logical;
13796         state->cdclk.actual = dev_priv->cdclk.actual;
13797
13798         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13799                                             new_crtc_state, i) {
13800                 if (new_crtc_state->base.active)
13801                         state->active_pipes |= BIT(crtc->pipe);
13802                 else
13803                         state->active_pipes &= ~BIT(crtc->pipe);
13804
13805                 if (old_crtc_state->base.active != new_crtc_state->base.active)
13806                         state->active_pipe_changes |= BIT(crtc->pipe);
13807         }
13808
13809         if (state->active_pipe_changes) {
13810                 ret = intel_atomic_lock_global_state(state);
13811                 if (ret)
13812                         return ret;
13813         }
13814
13815         ret = intel_modeset_calc_cdclk(state);
13816         if (ret)
13817                 return ret;
13818
13819         intel_modeset_clear_plls(state);
13820
13821         if (IS_HASWELL(dev_priv))
13822                 return haswell_mode_set_planes_workaround(state);
13823
13824         return 0;
13825 }
13826
13827 /*
13828  * Handle calculation of various watermark data at the end of the atomic check
13829  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13830  * handlers to ensure that all derived state has been updated.
13831  */
13832 static int calc_watermark_data(struct intel_atomic_state *state)
13833 {
13834         struct drm_device *dev = state->base.dev;
13835         struct drm_i915_private *dev_priv = to_i915(dev);
13836
13837         /* Is there platform-specific watermark information to calculate? */
13838         if (dev_priv->display.compute_global_watermarks)
13839                 return dev_priv->display.compute_global_watermarks(state);
13840
13841         return 0;
13842 }
13843
13844 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13845                                      struct intel_crtc_state *new_crtc_state)
13846 {
13847         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13848                 return;
13849
13850         new_crtc_state->base.mode_changed = false;
13851         new_crtc_state->update_pipe = true;
13852
13853         /*
13854          * If we're not doing the full modeset we want to
13855          * keep the current M/N values as they may be
13856          * sufficiently different to the computed values
13857          * to cause problems.
13858          *
13859          * FIXME: should really copy more fuzzy state here
13860          */
13861         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
13862         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
13863         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
13864         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
13865 }
13866
13867 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
13868                                           struct intel_crtc *crtc,
13869                                           u8 plane_ids_mask)
13870 {
13871         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13872         struct intel_plane *plane;
13873
13874         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13875                 struct intel_plane_state *plane_state;
13876
13877                 if ((plane_ids_mask & BIT(plane->id)) == 0)
13878                         continue;
13879
13880                 plane_state = intel_atomic_get_plane_state(state, plane);
13881                 if (IS_ERR(plane_state))
13882                         return PTR_ERR(plane_state);
13883         }
13884
13885         return 0;
13886 }
13887
13888 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
13889 {
13890         /* See {hsw,vlv,ivb}_plane_ratio() */
13891         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
13892                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
13893                 IS_IVYBRIDGE(dev_priv);
13894 }
13895
13896 static int intel_atomic_check_planes(struct intel_atomic_state *state,
13897                                      bool *need_modeset)
13898 {
13899         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13900         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13901         struct intel_plane_state *plane_state;
13902         struct intel_plane *plane;
13903         struct intel_crtc *crtc;
13904         int i, ret;
13905
13906         ret = icl_add_linked_planes(state);
13907         if (ret)
13908                 return ret;
13909
13910         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13911                 ret = intel_plane_atomic_check(state, plane);
13912                 if (ret) {
13913                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
13914                                          plane->base.base.id, plane->base.name);
13915                         return ret;
13916                 }
13917         }
13918
13919         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13920                                             new_crtc_state, i) {
13921                 u8 old_active_planes, new_active_planes;
13922
13923                 ret = icl_check_nv12_planes(new_crtc_state);
13924                 if (ret)
13925                         return ret;
13926
13927                 /*
13928                  * On some platforms the number of active planes affects
13929                  * the planes' minimum cdclk calculation. Add such planes
13930                  * to the state before we compute the minimum cdclk.
13931                  */
13932                 if (!active_planes_affects_min_cdclk(dev_priv))
13933                         continue;
13934
13935                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
13936                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
13937
13938                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
13939                         continue;
13940
13941                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
13942                 if (ret)
13943                         return ret;
13944         }
13945
13946         /*
13947          * active_planes bitmask has been updated, and potentially
13948          * affected planes are part of the state. We can now
13949          * compute the minimum cdclk for each plane.
13950          */
13951         for_each_new_intel_plane_in_state(state, plane, plane_state, i)
13952                 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
13953
13954         return 0;
13955 }
13956
13957 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
13958 {
13959         struct intel_crtc_state *crtc_state;
13960         struct intel_crtc *crtc;
13961         int i;
13962
13963         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13964                 int ret = intel_crtc_atomic_check(state, crtc);
13965                 if (ret) {
13966                         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
13967                                          crtc->base.base.id, crtc->base.name);
13968                         return ret;
13969                 }
13970         }
13971
13972         return 0;
13973 }
13974
13975 /**
13976  * intel_atomic_check - validate state object
13977  * @dev: drm device
13978  * @_state: state to validate
13979  */
13980 static int intel_atomic_check(struct drm_device *dev,
13981                               struct drm_atomic_state *_state)
13982 {
13983         struct drm_i915_private *dev_priv = to_i915(dev);
13984         struct intel_atomic_state *state = to_intel_atomic_state(_state);
13985         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13986         struct intel_crtc *crtc;
13987         int ret, i;
13988         bool any_ms = false;
13989
13990         /* Catch I915_MODE_FLAG_INHERITED */
13991         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13992                                             new_crtc_state, i) {
13993                 if (new_crtc_state->base.mode.private_flags !=
13994                     old_crtc_state->base.mode.private_flags)
13995                         new_crtc_state->base.mode_changed = true;
13996         }
13997
13998         ret = drm_atomic_helper_check_modeset(dev, &state->base);
13999         if (ret)
14000                 goto fail;
14001
14002         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14003                                             new_crtc_state, i) {
14004                 if (!needs_modeset(new_crtc_state))
14005                         continue;
14006
14007                 if (!new_crtc_state->base.enable) {
14008                         any_ms = true;
14009                         continue;
14010                 }
14011
14012                 ret = intel_modeset_pipe_config(new_crtc_state);
14013                 if (ret)
14014                         goto fail;
14015
14016                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14017
14018                 if (needs_modeset(new_crtc_state))
14019                         any_ms = true;
14020         }
14021
14022         if (any_ms && !check_digital_port_conflicts(state)) {
14023                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14024                 ret = EINVAL;
14025                 goto fail;
14026         }
14027
14028         ret = drm_dp_mst_atomic_check(&state->base);
14029         if (ret)
14030                 goto fail;
14031
14032         any_ms |= state->cdclk.force_min_cdclk_changed;
14033
14034         ret = intel_atomic_check_planes(state, &any_ms);
14035         if (ret)
14036                 goto fail;
14037
14038         if (any_ms) {
14039                 ret = intel_modeset_checks(state);
14040                 if (ret)
14041                         goto fail;
14042         } else {
14043                 state->cdclk.logical = dev_priv->cdclk.logical;
14044         }
14045
14046         ret = intel_atomic_check_crtcs(state);
14047         if (ret)
14048                 goto fail;
14049
14050         intel_fbc_choose_crtc(dev_priv, state);
14051         ret = calc_watermark_data(state);
14052         if (ret)
14053                 goto fail;
14054
14055         ret = intel_bw_atomic_check(state);
14056         if (ret)
14057                 goto fail;
14058
14059         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14060                                             new_crtc_state, i) {
14061                 if (!needs_modeset(new_crtc_state) &&
14062                     !new_crtc_state->update_pipe)
14063                         continue;
14064
14065                 intel_dump_pipe_config(new_crtc_state, state,
14066                                        needs_modeset(new_crtc_state) ?
14067                                        "[modeset]" : "[fastset]");
14068         }
14069
14070         return 0;
14071
14072  fail:
14073         if (ret == -EDEADLK)
14074                 return ret;
14075
14076         /*
14077          * FIXME would probably be nice to know which crtc specifically
14078          * caused the failure, in cases where we can pinpoint it.
14079          */
14080         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14081                                             new_crtc_state, i)
14082                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14083
14084         return ret;
14085 }
14086
14087 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14088 {
14089         return drm_atomic_helper_prepare_planes(state->base.dev,
14090                                                 &state->base);
14091 }
14092
14093 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14094 {
14095         struct drm_device *dev = crtc->base.dev;
14096         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14097
14098         if (!vblank->max_vblank_count)
14099                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14100
14101         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14102 }
14103
14104 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14105                                   struct intel_crtc_state *crtc_state)
14106 {
14107         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14108
14109         if (!IS_GEN(dev_priv, 2))
14110                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14111
14112         if (crtc_state->has_pch_encoder) {
14113                 enum pipe pch_transcoder =
14114                         intel_crtc_pch_transcoder(crtc);
14115
14116                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14117         }
14118 }
14119
14120 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14121                                const struct intel_crtc_state *new_crtc_state)
14122 {
14123         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
14124         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14125
14126         /*
14127          * Update pipe size and adjust fitter if needed: the reason for this is
14128          * that in compute_mode_changes we check the native mode (not the pfit
14129          * mode) to see if we can flip rather than do a full mode set. In the
14130          * fastboot case, we'll flip, but if we don't update the pipesrc and
14131          * pfit state, we'll end up with a big fb scanned out into the wrong
14132          * sized surface.
14133          */
14134         intel_set_pipe_src_size(new_crtc_state);
14135
14136         /* on skylake this is done by detaching scalers */
14137         if (INTEL_GEN(dev_priv) >= 9) {
14138                 skl_detach_scalers(new_crtc_state);
14139
14140                 if (new_crtc_state->pch_pfit.enabled)
14141                         skylake_pfit_enable(new_crtc_state);
14142         } else if (HAS_PCH_SPLIT(dev_priv)) {
14143                 if (new_crtc_state->pch_pfit.enabled)
14144                         ironlake_pfit_enable(new_crtc_state);
14145                 else if (old_crtc_state->pch_pfit.enabled)
14146                         ironlake_pfit_disable(old_crtc_state);
14147         }
14148
14149         if (INTEL_GEN(dev_priv) >= 11)
14150                 icl_set_pipe_chicken(crtc);
14151 }
14152
14153 static void commit_pipe_config(struct intel_atomic_state *state,
14154                                struct intel_crtc_state *old_crtc_state,
14155                                struct intel_crtc_state *new_crtc_state)
14156 {
14157         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14158         bool modeset = needs_modeset(new_crtc_state);
14159
14160         /*
14161          * During modesets pipe configuration was programmed as the
14162          * CRTC was enabled.
14163          */
14164         if (!modeset) {
14165                 if (new_crtc_state->base.color_mgmt_changed ||
14166                     new_crtc_state->update_pipe)
14167                         intel_color_commit(new_crtc_state);
14168
14169                 if (INTEL_GEN(dev_priv) >= 9)
14170                         skl_detach_scalers(new_crtc_state);
14171
14172                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14173                         bdw_set_pipemisc(new_crtc_state);
14174
14175                 if (new_crtc_state->update_pipe)
14176                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14177         }
14178
14179         if (dev_priv->display.atomic_update_watermarks)
14180                 dev_priv->display.atomic_update_watermarks(state,
14181                                                            new_crtc_state);
14182 }
14183
14184 static void intel_update_crtc(struct intel_crtc *crtc,
14185                               struct intel_atomic_state *state,
14186                               struct intel_crtc_state *old_crtc_state,
14187                               struct intel_crtc_state *new_crtc_state)
14188 {
14189         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14190         bool modeset = needs_modeset(new_crtc_state);
14191         struct intel_plane_state *new_plane_state =
14192                 intel_atomic_get_new_plane_state(state,
14193                                                  to_intel_plane(crtc->base.primary));
14194
14195         if (modeset) {
14196                 intel_crtc_update_active_timings(new_crtc_state);
14197
14198                 dev_priv->display.crtc_enable(new_crtc_state, state);
14199
14200                 /* vblanks work again, re-enable pipe CRC. */
14201                 intel_crtc_enable_pipe_crc(crtc);
14202         } else {
14203                 if (new_crtc_state->preload_luts &&
14204                     (new_crtc_state->base.color_mgmt_changed ||
14205                      new_crtc_state->update_pipe))
14206                         intel_color_load_luts(new_crtc_state);
14207
14208                 intel_pre_plane_update(old_crtc_state, new_crtc_state);
14209
14210                 if (new_crtc_state->update_pipe)
14211                         intel_encoders_update_pipe(crtc, new_crtc_state, state);
14212         }
14213
14214         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14215                 intel_fbc_disable(crtc);
14216         else if (new_plane_state)
14217                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14218
14219         /* Perform vblank evasion around commit operation */
14220         intel_pipe_update_start(new_crtc_state);
14221
14222         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14223
14224         if (INTEL_GEN(dev_priv) >= 9)
14225                 skl_update_planes_on_crtc(state, crtc);
14226         else
14227                 i9xx_update_planes_on_crtc(state, crtc);
14228
14229         intel_pipe_update_end(new_crtc_state);
14230
14231         /*
14232          * We usually enable FIFO underrun interrupts as part of the
14233          * CRTC enable sequence during modesets.  But when we inherit a
14234          * valid pipe configuration from the BIOS we need to take care
14235          * of enabling them on the CRTC's first fastset.
14236          */
14237         if (new_crtc_state->update_pipe && !modeset &&
14238             old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
14239                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14240 }
14241
14242 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14243 {
14244         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->base.crtc->dev);
14245         enum transcoder slave_transcoder;
14246
14247         WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14248
14249         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14250         return intel_get_crtc_for_pipe(dev_priv,
14251                                        (enum pipe)slave_transcoder);
14252 }
14253
14254 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14255                                           struct intel_crtc_state *old_crtc_state,
14256                                           struct intel_crtc_state *new_crtc_state,
14257                                           struct intel_crtc *crtc)
14258 {
14259         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14260
14261         intel_crtc_disable_planes(state, crtc);
14262
14263         /*
14264          * We need to disable pipe CRC before disabling the pipe,
14265          * or we race against vblank off.
14266          */
14267         intel_crtc_disable_pipe_crc(crtc);
14268
14269         dev_priv->display.crtc_disable(old_crtc_state, state);
14270         crtc->active = false;
14271         intel_fbc_disable(crtc);
14272         intel_disable_shared_dpll(old_crtc_state);
14273
14274         /*
14275          * Underruns don't always raise interrupts,
14276          * so check manually.
14277          */
14278         intel_check_cpu_fifo_underruns(dev_priv);
14279         intel_check_pch_fifo_underruns(dev_priv);
14280
14281         /* FIXME unify this for all platforms */
14282         if (!new_crtc_state->base.active &&
14283             !HAS_GMCH(dev_priv) &&
14284             dev_priv->display.initial_watermarks)
14285                 dev_priv->display.initial_watermarks(state,
14286                                                      new_crtc_state);
14287 }
14288
14289 static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
14290                                                    struct intel_crtc *crtc,
14291                                                    struct intel_crtc_state *old_crtc_state,
14292                                                    struct intel_crtc_state *new_crtc_state)
14293 {
14294         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14295         struct intel_crtc_state *new_slave_crtc_state =
14296                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14297         struct intel_crtc_state *old_slave_crtc_state =
14298                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14299
14300         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14301                 !old_slave_crtc_state);
14302
14303         /* Disable Slave first */
14304         intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
14305         if (old_slave_crtc_state->base.active)
14306                 intel_old_crtc_state_disables(state,
14307                                               old_slave_crtc_state,
14308                                               new_slave_crtc_state,
14309                                               slave_crtc);
14310
14311         /* Disable Master */
14312         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14313         if (old_crtc_state->base.active)
14314                 intel_old_crtc_state_disables(state,
14315                                               old_crtc_state,
14316                                               new_crtc_state,
14317                                               crtc);
14318 }
14319
14320 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14321 {
14322         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14323         struct intel_crtc *crtc;
14324         int i;
14325
14326         /*
14327          * Disable CRTC/pipes in reverse order because some features(MST in
14328          * TGL+) requires master and slave relationship between pipes, so it
14329          * should always pick the lowest pipe as master as it will be enabled
14330          * first and disable in the reverse order so the master will be the
14331          * last one to be disabled.
14332          */
14333         for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
14334                                                     new_crtc_state, i) {
14335                 if (!needs_modeset(new_crtc_state))
14336                         continue;
14337
14338                 /* In case of Transcoder port Sync master slave CRTCs can be
14339                  * assigned in any order and we need to make sure that
14340                  * slave CRTCs are disabled first and then master CRTC since
14341                  * Slave vblanks are masked till Master Vblanks.
14342                  */
14343                 if (is_trans_port_sync_mode(new_crtc_state)) {
14344                         if (is_trans_port_sync_master(new_crtc_state))
14345                                 intel_trans_port_sync_modeset_disables(state,
14346                                                                        crtc,
14347                                                                        old_crtc_state,
14348                                                                        new_crtc_state);
14349                         else
14350                                 continue;
14351                 } else {
14352                         intel_pre_plane_update(old_crtc_state, new_crtc_state);
14353
14354                         if (old_crtc_state->base.active)
14355                                 intel_old_crtc_state_disables(state,
14356                                                               old_crtc_state,
14357                                                               new_crtc_state,
14358                                                               crtc);
14359                 }
14360         }
14361 }
14362
14363 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14364 {
14365         struct intel_crtc *crtc;
14366         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14367         int i;
14368
14369         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14370                 if (!new_crtc_state->base.active)
14371                         continue;
14372
14373                 intel_update_crtc(crtc, state, old_crtc_state,
14374                                   new_crtc_state);
14375         }
14376 }
14377
14378 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14379                                               struct intel_atomic_state *state,
14380                                               struct intel_crtc_state *new_crtc_state)
14381 {
14382         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14383
14384         intel_crtc_update_active_timings(new_crtc_state);
14385         dev_priv->display.crtc_enable(new_crtc_state, state);
14386         intel_crtc_enable_pipe_crc(crtc);
14387 }
14388
14389 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14390                                        struct intel_atomic_state *state)
14391 {
14392         struct drm_connector *uninitialized_var(conn);
14393         struct drm_connector_state *conn_state;
14394         struct intel_dp *intel_dp;
14395         int i;
14396
14397         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14398                 if (conn_state->crtc == &crtc->base)
14399                         break;
14400         }
14401         intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14402         intel_dp_stop_link_train(intel_dp);
14403 }
14404
14405 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14406                                            struct intel_atomic_state *state)
14407 {
14408         struct intel_crtc_state *new_crtc_state =
14409                 intel_atomic_get_new_crtc_state(state, crtc);
14410         struct intel_crtc_state *old_crtc_state =
14411                 intel_atomic_get_old_crtc_state(state, crtc);
14412         struct intel_plane_state *new_plane_state =
14413                 intel_atomic_get_new_plane_state(state,
14414                                                  to_intel_plane(crtc->base.primary));
14415         bool modeset = needs_modeset(new_crtc_state);
14416
14417         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14418                 intel_fbc_disable(crtc);
14419         else if (new_plane_state)
14420                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14421
14422         /* Perform vblank evasion around commit operation */
14423         intel_pipe_update_start(new_crtc_state);
14424         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14425         skl_update_planes_on_crtc(state, crtc);
14426         intel_pipe_update_end(new_crtc_state);
14427
14428         /*
14429          * We usually enable FIFO underrun interrupts as part of the
14430          * CRTC enable sequence during modesets.  But when we inherit a
14431          * valid pipe configuration from the BIOS we need to take care
14432          * of enabling them on the CRTC's first fastset.
14433          */
14434         if (new_crtc_state->update_pipe && !modeset &&
14435             old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
14436                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14437 }
14438
14439 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14440                                                struct intel_atomic_state *state,
14441                                                struct intel_crtc_state *old_crtc_state,
14442                                                struct intel_crtc_state *new_crtc_state)
14443 {
14444         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14445         struct intel_crtc_state *new_slave_crtc_state =
14446                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14447         struct intel_crtc_state *old_slave_crtc_state =
14448                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14449
14450         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14451                 !old_slave_crtc_state);
14452
14453         DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14454                       crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14455                       slave_crtc->base.name);
14456
14457         /* Enable seq for slave with with DP_TP_CTL left Idle until the
14458          * master is ready
14459          */
14460         intel_crtc_enable_trans_port_sync(slave_crtc,
14461                                           state,
14462                                           new_slave_crtc_state);
14463
14464         /* Enable seq for master with with DP_TP_CTL left Idle */
14465         intel_crtc_enable_trans_port_sync(crtc,
14466                                           state,
14467                                           new_crtc_state);
14468
14469         /* Set Slave's DP_TP_CTL to Normal */
14470         intel_set_dp_tp_ctl_normal(slave_crtc,
14471                                    state);
14472
14473         /* Set Master's DP_TP_CTL To Normal */
14474         usleep_range(200, 400);
14475         intel_set_dp_tp_ctl_normal(crtc,
14476                                    state);
14477
14478         /* Now do the post crtc enable for all master and slaves */
14479         intel_post_crtc_enable_updates(slave_crtc,
14480                                        state);
14481         intel_post_crtc_enable_updates(crtc,
14482                                        state);
14483 }
14484
14485 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14486 {
14487         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14488         struct intel_crtc *crtc;
14489         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14490         unsigned int updated = 0;
14491         bool progress;
14492         int i;
14493         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14494         u8 required_slices = state->wm_results.ddb.enabled_slices;
14495         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14496
14497         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
14498                 /* ignore allocations for crtc's that have been turned off. */
14499                 if (new_crtc_state->base.active)
14500                         entries[i] = old_crtc_state->wm.skl.ddb;
14501
14502         /* If 2nd DBuf slice required, enable it here */
14503         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14504                 icl_dbuf_slices_update(dev_priv, required_slices);
14505
14506         /*
14507          * Whenever the number of active pipes changes, we need to make sure we
14508          * update the pipes in the right order so that their ddb allocations
14509          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14510          * cause pipe underruns and other bad stuff.
14511          */
14512         do {
14513                 progress = false;
14514
14515                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14516                         enum pipe pipe = crtc->pipe;
14517                         bool vbl_wait = false;
14518                         bool modeset = needs_modeset(new_crtc_state);
14519
14520                         if (updated & BIT(crtc->pipe) || !new_crtc_state->base.active)
14521                                 continue;
14522
14523                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14524                                                         entries,
14525                                                         INTEL_NUM_PIPES(dev_priv), i))
14526                                 continue;
14527
14528                         updated |= BIT(pipe);
14529                         entries[i] = new_crtc_state->wm.skl.ddb;
14530
14531                         /*
14532                          * If this is an already active pipe, it's DDB changed,
14533                          * and this isn't the last pipe that needs updating
14534                          * then we need to wait for a vblank to pass for the
14535                          * new ddb allocation to take effect.
14536                          */
14537                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14538                                                  &old_crtc_state->wm.skl.ddb) &&
14539                             !modeset &&
14540                             state->wm_results.dirty_pipes != updated)
14541                                 vbl_wait = true;
14542
14543                         if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14544                                 if (is_trans_port_sync_master(new_crtc_state))
14545                                         intel_update_trans_port_sync_crtcs(crtc,
14546                                                                            state,
14547                                                                            old_crtc_state,
14548                                                                            new_crtc_state);
14549                                 else
14550                                         continue;
14551                         } else {
14552                                 intel_update_crtc(crtc, state, old_crtc_state,
14553                                                   new_crtc_state);
14554                         }
14555
14556                         if (vbl_wait)
14557                                 intel_wait_for_vblank(dev_priv, pipe);
14558
14559                         progress = true;
14560                 }
14561         } while (progress);
14562
14563         /* If 2nd DBuf slice is no more required disable it */
14564         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14565                 icl_dbuf_slices_update(dev_priv, required_slices);
14566 }
14567
14568 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14569 {
14570         struct intel_atomic_state *state, *next;
14571         struct llist_node *freed;
14572
14573         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14574         llist_for_each_entry_safe(state, next, freed, freed)
14575                 drm_atomic_state_put(&state->base);
14576 }
14577
14578 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14579 {
14580         struct drm_i915_private *dev_priv =
14581                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14582
14583         intel_atomic_helper_free_state(dev_priv);
14584 }
14585
14586 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14587 {
14588         struct wait_queue_entry wait_fence, wait_reset;
14589         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14590
14591         init_wait_entry(&wait_fence, 0);
14592         init_wait_entry(&wait_reset, 0);
14593         for (;;) {
14594                 prepare_to_wait(&intel_state->commit_ready.wait,
14595                                 &wait_fence, TASK_UNINTERRUPTIBLE);
14596                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14597                                               I915_RESET_MODESET),
14598                                 &wait_reset, TASK_UNINTERRUPTIBLE);
14599
14600
14601                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14602                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14603                         break;
14604
14605                 schedule();
14606         }
14607         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14608         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14609                                   I915_RESET_MODESET),
14610                     &wait_reset);
14611 }
14612
14613 static void intel_atomic_cleanup_work(struct work_struct *work)
14614 {
14615         struct drm_atomic_state *state =
14616                 container_of(work, struct drm_atomic_state, commit_work);
14617         struct drm_i915_private *i915 = to_i915(state->dev);
14618
14619         drm_atomic_helper_cleanup_planes(&i915->drm, state);
14620         drm_atomic_helper_commit_cleanup_done(state);
14621         drm_atomic_state_put(state);
14622
14623         intel_atomic_helper_free_state(i915);
14624 }
14625
14626 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14627 {
14628         struct drm_device *dev = state->base.dev;
14629         struct drm_i915_private *dev_priv = to_i915(dev);
14630         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14631         struct intel_crtc *crtc;
14632         u64 put_domains[I915_MAX_PIPES] = {};
14633         intel_wakeref_t wakeref = 0;
14634         int i;
14635
14636         intel_atomic_commit_fence_wait(state);
14637
14638         drm_atomic_helper_wait_for_dependencies(&state->base);
14639
14640         if (state->modeset)
14641                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14642
14643         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14644                                             new_crtc_state, i) {
14645                 if (needs_modeset(new_crtc_state) ||
14646                     new_crtc_state->update_pipe) {
14647
14648                         put_domains[crtc->pipe] =
14649                                 modeset_get_crtc_power_domains(new_crtc_state);
14650                 }
14651         }
14652
14653         intel_commit_modeset_disables(state);
14654
14655         /* FIXME: Eventually get rid of our crtc->config pointer */
14656         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14657                 crtc->config = new_crtc_state;
14658
14659         if (state->modeset) {
14660                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14661
14662                 intel_set_cdclk_pre_plane_update(dev_priv,
14663                                                  &state->cdclk.actual,
14664                                                  &dev_priv->cdclk.actual,
14665                                                  state->cdclk.pipe);
14666
14667                 /*
14668                  * SKL workaround: bspec recommends we disable the SAGV when we
14669                  * have more then one pipe enabled
14670                  */
14671                 if (!intel_can_enable_sagv(state))
14672                         intel_disable_sagv(dev_priv);
14673
14674                 intel_modeset_verify_disabled(dev_priv, state);
14675         }
14676
14677         /* Complete the events for pipes that have now been disabled */
14678         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14679                 bool modeset = needs_modeset(new_crtc_state);
14680
14681                 /* Complete events for now disable pipes here. */
14682                 if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
14683                         spin_lock_irq(&dev->event_lock);
14684                         drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
14685                         spin_unlock_irq(&dev->event_lock);
14686
14687                         new_crtc_state->base.event = NULL;
14688                 }
14689         }
14690
14691         if (state->modeset)
14692                 intel_encoders_update_prepare(state);
14693
14694         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14695         dev_priv->display.commit_modeset_enables(state);
14696
14697         if (state->modeset) {
14698                 intel_encoders_update_complete(state);
14699
14700                 intel_set_cdclk_post_plane_update(dev_priv,
14701                                                   &state->cdclk.actual,
14702                                                   &dev_priv->cdclk.actual,
14703                                                   state->cdclk.pipe);
14704         }
14705
14706         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14707          * already, but still need the state for the delayed optimization. To
14708          * fix this:
14709          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14710          * - schedule that vblank worker _before_ calling hw_done
14711          * - at the start of commit_tail, cancel it _synchrously
14712          * - switch over to the vblank wait helper in the core after that since
14713          *   we don't need out special handling any more.
14714          */
14715         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14716
14717         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14718                 if (new_crtc_state->base.active &&
14719                     !needs_modeset(new_crtc_state) &&
14720                     !new_crtc_state->preload_luts &&
14721                     (new_crtc_state->base.color_mgmt_changed ||
14722                      new_crtc_state->update_pipe))
14723                         intel_color_load_luts(new_crtc_state);
14724         }
14725
14726         /*
14727          * Now that the vblank has passed, we can go ahead and program the
14728          * optimal watermarks on platforms that need two-step watermark
14729          * programming.
14730          *
14731          * TODO: Move this (and other cleanup) to an async worker eventually.
14732          */
14733         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14734                 if (dev_priv->display.optimize_watermarks)
14735                         dev_priv->display.optimize_watermarks(state,
14736                                                               new_crtc_state);
14737         }
14738
14739         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14740                 intel_post_plane_update(old_crtc_state);
14741
14742                 if (put_domains[i])
14743                         modeset_put_power_domains(dev_priv, put_domains[i]);
14744
14745                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14746         }
14747
14748         if (state->modeset)
14749                 intel_verify_planes(state);
14750
14751         if (state->modeset && intel_can_enable_sagv(state))
14752                 intel_enable_sagv(dev_priv);
14753
14754         drm_atomic_helper_commit_hw_done(&state->base);
14755
14756         if (state->modeset) {
14757                 /* As one of the primary mmio accessors, KMS has a high
14758                  * likelihood of triggering bugs in unclaimed access. After we
14759                  * finish modesetting, see if an error has been flagged, and if
14760                  * so enable debugging for the next modeset - and hope we catch
14761                  * the culprit.
14762                  */
14763                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14764                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14765         }
14766         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14767
14768         /*
14769          * Defer the cleanup of the old state to a separate worker to not
14770          * impede the current task (userspace for blocking modesets) that
14771          * are executed inline. For out-of-line asynchronous modesets/flips,
14772          * deferring to a new worker seems overkill, but we would place a
14773          * schedule point (cond_resched()) here anyway to keep latencies
14774          * down.
14775          */
14776         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14777         queue_work(system_highpri_wq, &state->base.commit_work);
14778 }
14779
14780 static void intel_atomic_commit_work(struct work_struct *work)
14781 {
14782         struct intel_atomic_state *state =
14783                 container_of(work, struct intel_atomic_state, base.commit_work);
14784
14785         intel_atomic_commit_tail(state);
14786 }
14787
14788 static int __i915_sw_fence_call
14789 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14790                           enum i915_sw_fence_notify notify)
14791 {
14792         struct intel_atomic_state *state =
14793                 container_of(fence, struct intel_atomic_state, commit_ready);
14794
14795         switch (notify) {
14796         case FENCE_COMPLETE:
14797                 /* we do blocking waits in the worker, nothing to do here */
14798                 break;
14799         case FENCE_FREE:
14800                 {
14801                         struct intel_atomic_helper *helper =
14802                                 &to_i915(state->base.dev)->atomic_helper;
14803
14804                         if (llist_add(&state->freed, &helper->free_list))
14805                                 schedule_work(&helper->free_work);
14806                         break;
14807                 }
14808         }
14809
14810         return NOTIFY_DONE;
14811 }
14812
14813 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14814 {
14815         struct intel_plane_state *old_plane_state, *new_plane_state;
14816         struct intel_plane *plane;
14817         int i;
14818
14819         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14820                                              new_plane_state, i)
14821                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
14822                                         to_intel_frontbuffer(new_plane_state->base.fb),
14823                                         plane->frontbuffer_bit);
14824 }
14825
14826 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14827 {
14828         struct intel_crtc *crtc;
14829
14830         for_each_intel_crtc(&dev_priv->drm, crtc)
14831                 drm_modeset_lock_assert_held(&crtc->base.mutex);
14832 }
14833
14834 static int intel_atomic_commit(struct drm_device *dev,
14835                                struct drm_atomic_state *_state,
14836                                bool nonblock)
14837 {
14838         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14839         struct drm_i915_private *dev_priv = to_i915(dev);
14840         int ret = 0;
14841
14842         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14843
14844         drm_atomic_state_get(&state->base);
14845         i915_sw_fence_init(&state->commit_ready,
14846                            intel_atomic_commit_ready);
14847
14848         /*
14849          * The intel_legacy_cursor_update() fast path takes care
14850          * of avoiding the vblank waits for simple cursor
14851          * movement and flips. For cursor on/off and size changes,
14852          * we want to perform the vblank waits so that watermark
14853          * updates happen during the correct frames. Gen9+ have
14854          * double buffered watermarks and so shouldn't need this.
14855          *
14856          * Unset state->legacy_cursor_update before the call to
14857          * drm_atomic_helper_setup_commit() because otherwise
14858          * drm_atomic_helper_wait_for_flip_done() is a noop and
14859          * we get FIFO underruns because we didn't wait
14860          * for vblank.
14861          *
14862          * FIXME doing watermarks and fb cleanup from a vblank worker
14863          * (assuming we had any) would solve these problems.
14864          */
14865         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
14866                 struct intel_crtc_state *new_crtc_state;
14867                 struct intel_crtc *crtc;
14868                 int i;
14869
14870                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14871                         if (new_crtc_state->wm.need_postvbl_update ||
14872                             new_crtc_state->update_wm_post)
14873                                 state->base.legacy_cursor_update = false;
14874         }
14875
14876         ret = intel_atomic_prepare_commit(state);
14877         if (ret) {
14878                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14879                 i915_sw_fence_commit(&state->commit_ready);
14880                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14881                 return ret;
14882         }
14883
14884         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
14885         if (!ret)
14886                 ret = drm_atomic_helper_swap_state(&state->base, true);
14887
14888         if (ret) {
14889                 i915_sw_fence_commit(&state->commit_ready);
14890
14891                 drm_atomic_helper_cleanup_planes(dev, &state->base);
14892                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14893                 return ret;
14894         }
14895         dev_priv->wm.distrust_bios_wm = false;
14896         intel_shared_dpll_swap_state(state);
14897         intel_atomic_track_fbs(state);
14898
14899         if (state->global_state_changed) {
14900                 assert_global_state_locked(dev_priv);
14901
14902                 memcpy(dev_priv->min_cdclk, state->min_cdclk,
14903                        sizeof(state->min_cdclk));
14904                 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
14905                        sizeof(state->min_voltage_level));
14906                 dev_priv->active_pipes = state->active_pipes;
14907                 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
14908
14909                 intel_cdclk_swap_state(state);
14910         }
14911
14912         drm_atomic_state_get(&state->base);
14913         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
14914
14915         i915_sw_fence_commit(&state->commit_ready);
14916         if (nonblock && state->modeset) {
14917                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
14918         } else if (nonblock) {
14919                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
14920         } else {
14921                 if (state->modeset)
14922                         flush_workqueue(dev_priv->modeset_wq);
14923                 intel_atomic_commit_tail(state);
14924         }
14925
14926         return 0;
14927 }
14928
14929 struct wait_rps_boost {
14930         struct wait_queue_entry wait;
14931
14932         struct drm_crtc *crtc;
14933         struct i915_request *request;
14934 };
14935
14936 static int do_rps_boost(struct wait_queue_entry *_wait,
14937                         unsigned mode, int sync, void *key)
14938 {
14939         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
14940         struct i915_request *rq = wait->request;
14941
14942         /*
14943          * If we missed the vblank, but the request is already running it
14944          * is reasonable to assume that it will complete before the next
14945          * vblank without our intervention, so leave RPS alone.
14946          */
14947         if (!i915_request_started(rq))
14948                 intel_rps_boost(rq);
14949         i915_request_put(rq);
14950
14951         drm_crtc_vblank_put(wait->crtc);
14952
14953         list_del(&wait->wait.entry);
14954         kfree(wait);
14955         return 1;
14956 }
14957
14958 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
14959                                        struct dma_fence *fence)
14960 {
14961         struct wait_rps_boost *wait;
14962
14963         if (!dma_fence_is_i915(fence))
14964                 return;
14965
14966         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
14967                 return;
14968
14969         if (drm_crtc_vblank_get(crtc))
14970                 return;
14971
14972         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
14973         if (!wait) {
14974                 drm_crtc_vblank_put(crtc);
14975                 return;
14976         }
14977
14978         wait->request = to_request(dma_fence_get(fence));
14979         wait->crtc = crtc;
14980
14981         wait->wait.func = do_rps_boost;
14982         wait->wait.flags = 0;
14983
14984         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
14985 }
14986
14987 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
14988 {
14989         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
14990         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14991         struct drm_framebuffer *fb = plane_state->base.fb;
14992         struct i915_vma *vma;
14993
14994         if (plane->id == PLANE_CURSOR &&
14995             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
14996                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14997                 const int align = intel_cursor_alignment(dev_priv);
14998                 int err;
14999
15000                 err = i915_gem_object_attach_phys(obj, align);
15001                 if (err)
15002                         return err;
15003         }
15004
15005         vma = intel_pin_and_fence_fb_obj(fb,
15006                                          &plane_state->view,
15007                                          intel_plane_uses_fence(plane_state),
15008                                          &plane_state->flags);
15009         if (IS_ERR(vma))
15010                 return PTR_ERR(vma);
15011
15012         plane_state->vma = vma;
15013
15014         return 0;
15015 }
15016
15017 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15018 {
15019         struct i915_vma *vma;
15020
15021         vma = fetch_and_zero(&old_plane_state->vma);
15022         if (vma)
15023                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15024 }
15025
15026 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15027 {
15028         struct i915_sched_attr attr = {
15029                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15030         };
15031
15032         i915_gem_object_wait_priority(obj, 0, &attr);
15033 }
15034
15035 /**
15036  * intel_prepare_plane_fb - Prepare fb for usage on plane
15037  * @plane: drm plane to prepare for
15038  * @_new_plane_state: the plane state being prepared
15039  *
15040  * Prepares a framebuffer for usage on a display plane.  Generally this
15041  * involves pinning the underlying object and updating the frontbuffer tracking
15042  * bits.  Some older platforms need special physical address handling for
15043  * cursor planes.
15044  *
15045  * Returns 0 on success, negative error code on failure.
15046  */
15047 int
15048 intel_prepare_plane_fb(struct drm_plane *plane,
15049                        struct drm_plane_state *_new_plane_state)
15050 {
15051         struct intel_plane_state *new_plane_state =
15052                 to_intel_plane_state(_new_plane_state);
15053         struct intel_atomic_state *intel_state =
15054                 to_intel_atomic_state(new_plane_state->base.state);
15055         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15056         struct drm_framebuffer *fb = new_plane_state->base.fb;
15057         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15058         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15059         int ret;
15060
15061         if (old_obj) {
15062                 struct intel_crtc_state *crtc_state =
15063                         intel_atomic_get_new_crtc_state(intel_state,
15064                                                         to_intel_crtc(plane->state->crtc));
15065
15066                 /* Big Hammer, we also need to ensure that any pending
15067                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15068                  * current scanout is retired before unpinning the old
15069                  * framebuffer. Note that we rely on userspace rendering
15070                  * into the buffer attached to the pipe they are waiting
15071                  * on. If not, userspace generates a GPU hang with IPEHR
15072                  * point to the MI_WAIT_FOR_EVENT.
15073                  *
15074                  * This should only fail upon a hung GPU, in which case we
15075                  * can safely continue.
15076                  */
15077                 if (needs_modeset(crtc_state)) {
15078                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15079                                                               old_obj->base.resv, NULL,
15080                                                               false, 0,
15081                                                               GFP_KERNEL);
15082                         if (ret < 0)
15083                                 return ret;
15084                 }
15085         }
15086
15087         if (new_plane_state->base.fence) { /* explicit fencing */
15088                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15089                                                     new_plane_state->base.fence,
15090                                                     I915_FENCE_TIMEOUT,
15091                                                     GFP_KERNEL);
15092                 if (ret < 0)
15093                         return ret;
15094         }
15095
15096         if (!obj)
15097                 return 0;
15098
15099         ret = i915_gem_object_pin_pages(obj);
15100         if (ret)
15101                 return ret;
15102
15103         ret = intel_plane_pin_fb(new_plane_state);
15104
15105         i915_gem_object_unpin_pages(obj);
15106         if (ret)
15107                 return ret;
15108
15109         fb_obj_bump_render_priority(obj);
15110         i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
15111
15112         if (!new_plane_state->base.fence) { /* implicit fencing */
15113                 struct dma_fence *fence;
15114
15115                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15116                                                       obj->base.resv, NULL,
15117                                                       false, I915_FENCE_TIMEOUT,
15118                                                       GFP_KERNEL);
15119                 if (ret < 0)
15120                         return ret;
15121
15122                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15123                 if (fence) {
15124                         add_rps_boost_after_vblank(new_plane_state->base.crtc,
15125                                                    fence);
15126                         dma_fence_put(fence);
15127                 }
15128         } else {
15129                 add_rps_boost_after_vblank(new_plane_state->base.crtc,
15130                                            new_plane_state->base.fence);
15131         }
15132
15133         /*
15134          * We declare pageflips to be interactive and so merit a small bias
15135          * towards upclocking to deliver the frame on time. By only changing
15136          * the RPS thresholds to sample more regularly and aim for higher
15137          * clocks we can hopefully deliver low power workloads (like kodi)
15138          * that are not quite steady state without resorting to forcing
15139          * maximum clocks following a vblank miss (see do_rps_boost()).
15140          */
15141         if (!intel_state->rps_interactive) {
15142                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15143                 intel_state->rps_interactive = true;
15144         }
15145
15146         return 0;
15147 }
15148
15149 /**
15150  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15151  * @plane: drm plane to clean up for
15152  * @_old_plane_state: the state from the previous modeset
15153  *
15154  * Cleans up a framebuffer that has just been removed from a plane.
15155  */
15156 void
15157 intel_cleanup_plane_fb(struct drm_plane *plane,
15158                        struct drm_plane_state *_old_plane_state)
15159 {
15160         struct intel_plane_state *old_plane_state =
15161                 to_intel_plane_state(_old_plane_state);
15162         struct intel_atomic_state *intel_state =
15163                 to_intel_atomic_state(old_plane_state->base.state);
15164         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15165
15166         if (intel_state->rps_interactive) {
15167                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15168                 intel_state->rps_interactive = false;
15169         }
15170
15171         /* Should only be called after a successful intel_prepare_plane_fb()! */
15172         intel_plane_unpin_fb(old_plane_state);
15173 }
15174
15175 /**
15176  * intel_plane_destroy - destroy a plane
15177  * @plane: plane to destroy
15178  *
15179  * Common destruction function for all types of planes (primary, cursor,
15180  * sprite).
15181  */
15182 void intel_plane_destroy(struct drm_plane *plane)
15183 {
15184         drm_plane_cleanup(plane);
15185         kfree(to_intel_plane(plane));
15186 }
15187
15188 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15189                                             u32 format, u64 modifier)
15190 {
15191         switch (modifier) {
15192         case DRM_FORMAT_MOD_LINEAR:
15193         case I915_FORMAT_MOD_X_TILED:
15194                 break;
15195         default:
15196                 return false;
15197         }
15198
15199         switch (format) {
15200         case DRM_FORMAT_C8:
15201         case DRM_FORMAT_RGB565:
15202         case DRM_FORMAT_XRGB1555:
15203         case DRM_FORMAT_XRGB8888:
15204                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15205                         modifier == I915_FORMAT_MOD_X_TILED;
15206         default:
15207                 return false;
15208         }
15209 }
15210
15211 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15212                                             u32 format, u64 modifier)
15213 {
15214         switch (modifier) {
15215         case DRM_FORMAT_MOD_LINEAR:
15216         case I915_FORMAT_MOD_X_TILED:
15217                 break;
15218         default:
15219                 return false;
15220         }
15221
15222         switch (format) {
15223         case DRM_FORMAT_C8:
15224         case DRM_FORMAT_RGB565:
15225         case DRM_FORMAT_XRGB8888:
15226         case DRM_FORMAT_XBGR8888:
15227         case DRM_FORMAT_XRGB2101010:
15228         case DRM_FORMAT_XBGR2101010:
15229         case DRM_FORMAT_XBGR16161616F:
15230                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15231                         modifier == I915_FORMAT_MOD_X_TILED;
15232         default:
15233                 return false;
15234         }
15235 }
15236
15237 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15238                                               u32 format, u64 modifier)
15239 {
15240         return modifier == DRM_FORMAT_MOD_LINEAR &&
15241                 format == DRM_FORMAT_ARGB8888;
15242 }
15243
15244 static const struct drm_plane_funcs i965_plane_funcs = {
15245         .update_plane = drm_atomic_helper_update_plane,
15246         .disable_plane = drm_atomic_helper_disable_plane,
15247         .destroy = intel_plane_destroy,
15248         .atomic_duplicate_state = intel_plane_duplicate_state,
15249         .atomic_destroy_state = intel_plane_destroy_state,
15250         .format_mod_supported = i965_plane_format_mod_supported,
15251 };
15252
15253 static const struct drm_plane_funcs i8xx_plane_funcs = {
15254         .update_plane = drm_atomic_helper_update_plane,
15255         .disable_plane = drm_atomic_helper_disable_plane,
15256         .destroy = intel_plane_destroy,
15257         .atomic_duplicate_state = intel_plane_duplicate_state,
15258         .atomic_destroy_state = intel_plane_destroy_state,
15259         .format_mod_supported = i8xx_plane_format_mod_supported,
15260 };
15261
15262 static int
15263 intel_legacy_cursor_update(struct drm_plane *_plane,
15264                            struct drm_crtc *_crtc,
15265                            struct drm_framebuffer *fb,
15266                            int crtc_x, int crtc_y,
15267                            unsigned int crtc_w, unsigned int crtc_h,
15268                            u32 src_x, u32 src_y,
15269                            u32 src_w, u32 src_h,
15270                            struct drm_modeset_acquire_ctx *ctx)
15271 {
15272         struct intel_plane *plane = to_intel_plane(_plane);
15273         struct intel_crtc *crtc = to_intel_crtc(_crtc);
15274         struct intel_plane_state *old_plane_state =
15275                 to_intel_plane_state(plane->base.state);
15276         struct intel_plane_state *new_plane_state;
15277         struct intel_crtc_state *crtc_state =
15278                 to_intel_crtc_state(crtc->base.state);
15279         struct intel_crtc_state *new_crtc_state;
15280         int ret;
15281
15282         /*
15283          * When crtc is inactive or there is a modeset pending,
15284          * wait for it to complete in the slowpath
15285          */
15286         if (!crtc_state->base.active || needs_modeset(crtc_state) ||
15287             crtc_state->update_pipe)
15288                 goto slow;
15289
15290         /*
15291          * Don't do an async update if there is an outstanding commit modifying
15292          * the plane.  This prevents our async update's changes from getting
15293          * overridden by a previous synchronous update's state.
15294          */
15295         if (old_plane_state->base.commit &&
15296             !try_wait_for_completion(&old_plane_state->base.commit->hw_done))
15297                 goto slow;
15298
15299         /*
15300          * If any parameters change that may affect watermarks,
15301          * take the slowpath. Only changing fb or position should be
15302          * in the fastpath.
15303          */
15304         if (old_plane_state->base.crtc != &crtc->base ||
15305             old_plane_state->base.src_w != src_w ||
15306             old_plane_state->base.src_h != src_h ||
15307             old_plane_state->base.crtc_w != crtc_w ||
15308             old_plane_state->base.crtc_h != crtc_h ||
15309             !old_plane_state->base.fb != !fb)
15310                 goto slow;
15311
15312         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15313         if (!new_plane_state)
15314                 return -ENOMEM;
15315
15316         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15317         if (!new_crtc_state) {
15318                 ret = -ENOMEM;
15319                 goto out_free;
15320         }
15321
15322         drm_atomic_set_fb_for_plane(&new_plane_state->base, fb);
15323
15324         new_plane_state->base.src_x = src_x;
15325         new_plane_state->base.src_y = src_y;
15326         new_plane_state->base.src_w = src_w;
15327         new_plane_state->base.src_h = src_h;
15328         new_plane_state->base.crtc_x = crtc_x;
15329         new_plane_state->base.crtc_y = crtc_y;
15330         new_plane_state->base.crtc_w = crtc_w;
15331         new_plane_state->base.crtc_h = crtc_h;
15332
15333         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15334                                                   old_plane_state, new_plane_state);
15335         if (ret)
15336                 goto out_free;
15337
15338         ret = intel_plane_pin_fb(new_plane_state);
15339         if (ret)
15340                 goto out_free;
15341
15342         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->base.fb), ORIGIN_FLIP);
15343         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
15344                                 to_intel_frontbuffer(new_plane_state->base.fb),
15345                                 plane->frontbuffer_bit);
15346
15347         /* Swap plane state */
15348         plane->base.state = &new_plane_state->base;
15349
15350         /*
15351          * We cannot swap crtc_state as it may be in use by an atomic commit or
15352          * page flip that's running simultaneously. If we swap crtc_state and
15353          * destroy the old state, we will cause a use-after-free there.
15354          *
15355          * Only update active_planes, which is needed for our internal
15356          * bookkeeping. Either value will do the right thing when updating
15357          * planes atomically. If the cursor was part of the atomic update then
15358          * we would have taken the slowpath.
15359          */
15360         crtc_state->active_planes = new_crtc_state->active_planes;
15361
15362         if (new_plane_state->base.visible)
15363                 intel_update_plane(plane, crtc_state, new_plane_state);
15364         else
15365                 intel_disable_plane(plane, crtc_state);
15366
15367         intel_plane_unpin_fb(old_plane_state);
15368
15369 out_free:
15370         if (new_crtc_state)
15371                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->base);
15372         if (ret)
15373                 intel_plane_destroy_state(&plane->base, &new_plane_state->base);
15374         else
15375                 intel_plane_destroy_state(&plane->base, &old_plane_state->base);
15376         return ret;
15377
15378 slow:
15379         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15380                                               crtc_x, crtc_y, crtc_w, crtc_h,
15381                                               src_x, src_y, src_w, src_h, ctx);
15382 }
15383
15384 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15385         .update_plane = intel_legacy_cursor_update,
15386         .disable_plane = drm_atomic_helper_disable_plane,
15387         .destroy = intel_plane_destroy,
15388         .atomic_duplicate_state = intel_plane_duplicate_state,
15389         .atomic_destroy_state = intel_plane_destroy_state,
15390         .format_mod_supported = intel_cursor_format_mod_supported,
15391 };
15392
15393 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15394                                enum i9xx_plane_id i9xx_plane)
15395 {
15396         if (!HAS_FBC(dev_priv))
15397                 return false;
15398
15399         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15400                 return i9xx_plane == PLANE_A; /* tied to pipe A */
15401         else if (IS_IVYBRIDGE(dev_priv))
15402                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15403                         i9xx_plane == PLANE_C;
15404         else if (INTEL_GEN(dev_priv) >= 4)
15405                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15406         else
15407                 return i9xx_plane == PLANE_A;
15408 }
15409
15410 static struct intel_plane *
15411 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15412 {
15413         struct intel_plane *plane;
15414         const struct drm_plane_funcs *plane_funcs;
15415         unsigned int supported_rotations;
15416         unsigned int possible_crtcs;
15417         const u64 *modifiers;
15418         const u32 *formats;
15419         int num_formats;
15420         int ret, zpos;
15421
15422         if (INTEL_GEN(dev_priv) >= 9)
15423                 return skl_universal_plane_create(dev_priv, pipe,
15424                                                   PLANE_PRIMARY);
15425
15426         plane = intel_plane_alloc();
15427         if (IS_ERR(plane))
15428                 return plane;
15429
15430         plane->pipe = pipe;
15431         /*
15432          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15433          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15434          */
15435         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15436                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15437         else
15438                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15439         plane->id = PLANE_PRIMARY;
15440         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15441
15442         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15443         if (plane->has_fbc) {
15444                 struct intel_fbc *fbc = &dev_priv->fbc;
15445
15446                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15447         }
15448
15449         if (INTEL_GEN(dev_priv) >= 4) {
15450                 /*
15451                  * WaFP16GammaEnabling:ivb
15452                  * "Workaround : When using the 64-bit format, the plane
15453                  *  output on each color channel has one quarter amplitude.
15454                  *  It can be brought up to full amplitude by using pipe
15455                  *  gamma correction or pipe color space conversion to
15456                  *  multiply the plane output by four."
15457                  *
15458                  * There is no dedicated plane gamma for the primary plane,
15459                  * and using the pipe gamma/csc could conflict with other
15460                  * planes, so we choose not to expose fp16 on IVB primary
15461                  * planes. HSW primary planes no longer have this problem.
15462                  */
15463                 if (IS_IVYBRIDGE(dev_priv)) {
15464                         formats = ivb_primary_formats;
15465                         num_formats = ARRAY_SIZE(ivb_primary_formats);
15466                 } else {
15467                         formats = i965_primary_formats;
15468                         num_formats = ARRAY_SIZE(i965_primary_formats);
15469                 }
15470                 modifiers = i9xx_format_modifiers;
15471
15472                 plane->max_stride = i9xx_plane_max_stride;
15473                 plane->update_plane = i9xx_update_plane;
15474                 plane->disable_plane = i9xx_disable_plane;
15475                 plane->get_hw_state = i9xx_plane_get_hw_state;
15476                 plane->check_plane = i9xx_plane_check;
15477
15478                 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15479                         plane->min_cdclk = hsw_plane_min_cdclk;
15480                 else if (IS_IVYBRIDGE(dev_priv))
15481                         plane->min_cdclk = ivb_plane_min_cdclk;
15482                 else if (IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv))
15483                         plane->min_cdclk = vlv_plane_min_cdclk;
15484                 else
15485                         plane->min_cdclk = i9xx_plane_min_cdclk;
15486
15487                 plane_funcs = &i965_plane_funcs;
15488         } else {
15489                 formats = i8xx_primary_formats;
15490                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15491                 modifiers = i9xx_format_modifiers;
15492
15493                 plane->max_stride = i9xx_plane_max_stride;
15494                 plane->update_plane = i9xx_update_plane;
15495                 plane->disable_plane = i9xx_disable_plane;
15496                 plane->get_hw_state = i9xx_plane_get_hw_state;
15497                 plane->check_plane = i9xx_plane_check;
15498                 plane->min_cdclk = i9xx_plane_min_cdclk;
15499
15500                 plane_funcs = &i8xx_plane_funcs;
15501         }
15502
15503         possible_crtcs = BIT(pipe);
15504
15505         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15506                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15507                                                possible_crtcs, plane_funcs,
15508                                                formats, num_formats, modifiers,
15509                                                DRM_PLANE_TYPE_PRIMARY,
15510                                                "primary %c", pipe_name(pipe));
15511         else
15512                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15513                                                possible_crtcs, plane_funcs,
15514                                                formats, num_formats, modifiers,
15515                                                DRM_PLANE_TYPE_PRIMARY,
15516                                                "plane %c",
15517                                                plane_name(plane->i9xx_plane));
15518         if (ret)
15519                 goto fail;
15520
15521         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15522                 supported_rotations =
15523                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15524                         DRM_MODE_REFLECT_X;
15525         } else if (INTEL_GEN(dev_priv) >= 4) {
15526                 supported_rotations =
15527                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15528         } else {
15529                 supported_rotations = DRM_MODE_ROTATE_0;
15530         }
15531
15532         if (INTEL_GEN(dev_priv) >= 4)
15533                 drm_plane_create_rotation_property(&plane->base,
15534                                                    DRM_MODE_ROTATE_0,
15535                                                    supported_rotations);
15536
15537         zpos = 0;
15538         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15539
15540         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15541
15542         return plane;
15543
15544 fail:
15545         intel_plane_free(plane);
15546
15547         return ERR_PTR(ret);
15548 }
15549
15550 static struct intel_plane *
15551 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15552                           enum pipe pipe)
15553 {
15554         unsigned int possible_crtcs;
15555         struct intel_plane *cursor;
15556         int ret, zpos;
15557
15558         cursor = intel_plane_alloc();
15559         if (IS_ERR(cursor))
15560                 return cursor;
15561
15562         cursor->pipe = pipe;
15563         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15564         cursor->id = PLANE_CURSOR;
15565         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15566
15567         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15568                 cursor->max_stride = i845_cursor_max_stride;
15569                 cursor->update_plane = i845_update_cursor;
15570                 cursor->disable_plane = i845_disable_cursor;
15571                 cursor->get_hw_state = i845_cursor_get_hw_state;
15572                 cursor->check_plane = i845_check_cursor;
15573         } else {
15574                 cursor->max_stride = i9xx_cursor_max_stride;
15575                 cursor->update_plane = i9xx_update_cursor;
15576                 cursor->disable_plane = i9xx_disable_cursor;
15577                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15578                 cursor->check_plane = i9xx_check_cursor;
15579         }
15580
15581         cursor->cursor.base = ~0;
15582         cursor->cursor.cntl = ~0;
15583
15584         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15585                 cursor->cursor.size = ~0;
15586
15587         possible_crtcs = BIT(pipe);
15588
15589         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15590                                        possible_crtcs, &intel_cursor_plane_funcs,
15591                                        intel_cursor_formats,
15592                                        ARRAY_SIZE(intel_cursor_formats),
15593                                        cursor_format_modifiers,
15594                                        DRM_PLANE_TYPE_CURSOR,
15595                                        "cursor %c", pipe_name(pipe));
15596         if (ret)
15597                 goto fail;
15598
15599         if (INTEL_GEN(dev_priv) >= 4)
15600                 drm_plane_create_rotation_property(&cursor->base,
15601                                                    DRM_MODE_ROTATE_0,
15602                                                    DRM_MODE_ROTATE_0 |
15603                                                    DRM_MODE_ROTATE_180);
15604
15605         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15606         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15607
15608         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15609
15610         return cursor;
15611
15612 fail:
15613         intel_plane_free(cursor);
15614
15615         return ERR_PTR(ret);
15616 }
15617
15618 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15619                                     struct intel_crtc_state *crtc_state)
15620 {
15621         struct intel_crtc_scaler_state *scaler_state =
15622                 &crtc_state->scaler_state;
15623         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15624         int i;
15625
15626         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15627         if (!crtc->num_scalers)
15628                 return;
15629
15630         for (i = 0; i < crtc->num_scalers; i++) {
15631                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15632
15633                 scaler->in_use = 0;
15634                 scaler->mode = 0;
15635         }
15636
15637         scaler_state->scaler_id = -1;
15638 }
15639
15640 #define INTEL_CRTC_FUNCS \
15641         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15642         .set_config = drm_atomic_helper_set_config, \
15643         .destroy = intel_crtc_destroy, \
15644         .page_flip = drm_atomic_helper_page_flip, \
15645         .atomic_duplicate_state = intel_crtc_duplicate_state, \
15646         .atomic_destroy_state = intel_crtc_destroy_state, \
15647         .set_crc_source = intel_crtc_set_crc_source, \
15648         .verify_crc_source = intel_crtc_verify_crc_source, \
15649         .get_crc_sources = intel_crtc_get_crc_sources
15650
15651 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15652         INTEL_CRTC_FUNCS,
15653
15654         .get_vblank_counter = g4x_get_vblank_counter,
15655         .enable_vblank = bdw_enable_vblank,
15656         .disable_vblank = bdw_disable_vblank,
15657 };
15658
15659 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15660         INTEL_CRTC_FUNCS,
15661
15662         .get_vblank_counter = g4x_get_vblank_counter,
15663         .enable_vblank = ilk_enable_vblank,
15664         .disable_vblank = ilk_disable_vblank,
15665 };
15666
15667 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15668         INTEL_CRTC_FUNCS,
15669
15670         .get_vblank_counter = g4x_get_vblank_counter,
15671         .enable_vblank = i965_enable_vblank,
15672         .disable_vblank = i965_disable_vblank,
15673 };
15674
15675 static const struct drm_crtc_funcs i965_crtc_funcs = {
15676         INTEL_CRTC_FUNCS,
15677
15678         .get_vblank_counter = i915_get_vblank_counter,
15679         .enable_vblank = i965_enable_vblank,
15680         .disable_vblank = i965_disable_vblank,
15681 };
15682
15683 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15684         INTEL_CRTC_FUNCS,
15685
15686         .get_vblank_counter = i915_get_vblank_counter,
15687         .enable_vblank = i915gm_enable_vblank,
15688         .disable_vblank = i915gm_disable_vblank,
15689 };
15690
15691 static const struct drm_crtc_funcs i915_crtc_funcs = {
15692         INTEL_CRTC_FUNCS,
15693
15694         .get_vblank_counter = i915_get_vblank_counter,
15695         .enable_vblank = i8xx_enable_vblank,
15696         .disable_vblank = i8xx_disable_vblank,
15697 };
15698
15699 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15700         INTEL_CRTC_FUNCS,
15701
15702         /* no hw vblank counter */
15703         .enable_vblank = i8xx_enable_vblank,
15704         .disable_vblank = i8xx_disable_vblank,
15705 };
15706
15707 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15708 {
15709         const struct drm_crtc_funcs *funcs;
15710         struct intel_crtc *intel_crtc;
15711         struct intel_crtc_state *crtc_state = NULL;
15712         struct intel_plane *primary = NULL;
15713         struct intel_plane *cursor = NULL;
15714         int sprite, ret;
15715
15716         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15717         if (!intel_crtc)
15718                 return -ENOMEM;
15719
15720         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15721         if (!crtc_state) {
15722                 ret = -ENOMEM;
15723                 goto fail;
15724         }
15725         __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
15726         intel_crtc->config = crtc_state;
15727
15728         primary = intel_primary_plane_create(dev_priv, pipe);
15729         if (IS_ERR(primary)) {
15730                 ret = PTR_ERR(primary);
15731                 goto fail;
15732         }
15733         intel_crtc->plane_ids_mask |= BIT(primary->id);
15734
15735         for_each_sprite(dev_priv, pipe, sprite) {
15736                 struct intel_plane *plane;
15737
15738                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15739                 if (IS_ERR(plane)) {
15740                         ret = PTR_ERR(plane);
15741                         goto fail;
15742                 }
15743                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15744         }
15745
15746         cursor = intel_cursor_plane_create(dev_priv, pipe);
15747         if (IS_ERR(cursor)) {
15748                 ret = PTR_ERR(cursor);
15749                 goto fail;
15750         }
15751         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15752
15753         if (HAS_GMCH(dev_priv)) {
15754                 if (IS_CHERRYVIEW(dev_priv) ||
15755                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15756                         funcs = &g4x_crtc_funcs;
15757                 else if (IS_GEN(dev_priv, 4))
15758                         funcs = &i965_crtc_funcs;
15759                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15760                         funcs = &i915gm_crtc_funcs;
15761                 else if (IS_GEN(dev_priv, 3))
15762                         funcs = &i915_crtc_funcs;
15763                 else
15764                         funcs = &i8xx_crtc_funcs;
15765         } else {
15766                 if (INTEL_GEN(dev_priv) >= 8)
15767                         funcs = &bdw_crtc_funcs;
15768                 else
15769                         funcs = &ilk_crtc_funcs;
15770         }
15771
15772         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15773                                         &primary->base, &cursor->base,
15774                                         funcs, "pipe %c", pipe_name(pipe));
15775         if (ret)
15776                 goto fail;
15777
15778         intel_crtc->pipe = pipe;
15779
15780         /* initialize shared scalers */
15781         intel_crtc_init_scalers(intel_crtc, crtc_state);
15782
15783         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15784                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15785         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15786
15787         if (INTEL_GEN(dev_priv) < 9) {
15788                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15789
15790                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15791                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15792                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15793         }
15794
15795         intel_color_init(intel_crtc);
15796
15797         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15798
15799         return 0;
15800
15801 fail:
15802         /*
15803          * drm_mode_config_cleanup() will free up any
15804          * crtcs/planes already initialized.
15805          */
15806         kfree(crtc_state);
15807         kfree(intel_crtc);
15808
15809         return ret;
15810 }
15811
15812 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15813                                       struct drm_file *file)
15814 {
15815         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15816         struct drm_crtc *drmmode_crtc;
15817         struct intel_crtc *crtc;
15818
15819         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15820         if (!drmmode_crtc)
15821                 return -ENOENT;
15822
15823         crtc = to_intel_crtc(drmmode_crtc);
15824         pipe_from_crtc_id->pipe = crtc->pipe;
15825
15826         return 0;
15827 }
15828
15829 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15830 {
15831         struct drm_device *dev = encoder->base.dev;
15832         struct intel_encoder *source_encoder;
15833         u32 possible_clones = 0;
15834
15835         for_each_intel_encoder(dev, source_encoder) {
15836                 if (encoders_cloneable(encoder, source_encoder))
15837                         possible_clones |= drm_encoder_mask(&source_encoder->base);
15838         }
15839
15840         return possible_clones;
15841 }
15842
15843 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
15844 {
15845         struct drm_device *dev = encoder->base.dev;
15846         struct intel_crtc *crtc;
15847         u32 possible_crtcs = 0;
15848
15849         for_each_intel_crtc(dev, crtc) {
15850                 if (encoder->pipe_mask & BIT(crtc->pipe))
15851                         possible_crtcs |= drm_crtc_mask(&crtc->base);
15852         }
15853
15854         return possible_crtcs;
15855 }
15856
15857 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
15858 {
15859         if (!IS_MOBILE(dev_priv))
15860                 return false;
15861
15862         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15863                 return false;
15864
15865         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15866                 return false;
15867
15868         return true;
15869 }
15870
15871 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
15872 {
15873         if (INTEL_GEN(dev_priv) >= 9)
15874                 return false;
15875
15876         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15877                 return false;
15878
15879         if (HAS_PCH_LPT_H(dev_priv) &&
15880             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15881                 return false;
15882
15883         /* DDI E can't be used if DDI A requires 4 lanes */
15884         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15885                 return false;
15886
15887         if (!dev_priv->vbt.int_crt_support)
15888                 return false;
15889
15890         return true;
15891 }
15892
15893 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15894 {
15895         int pps_num;
15896         int pps_idx;
15897
15898         if (HAS_DDI(dev_priv))
15899                 return;
15900         /*
15901          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15902          * everywhere where registers can be write protected.
15903          */
15904         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15905                 pps_num = 2;
15906         else
15907                 pps_num = 1;
15908
15909         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15910                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15911
15912                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15913                 I915_WRITE(PP_CONTROL(pps_idx), val);
15914         }
15915 }
15916
15917 static void intel_pps_init(struct drm_i915_private *dev_priv)
15918 {
15919         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15920                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15921         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15922                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15923         else
15924                 dev_priv->pps_mmio_base = PPS_BASE;
15925
15926         intel_pps_unlock_regs_wa(dev_priv);
15927 }
15928
15929 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
15930 {
15931         struct intel_encoder *encoder;
15932         bool dpd_is_edp = false;
15933
15934         intel_pps_init(dev_priv);
15935
15936         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
15937                 return;
15938
15939         if (INTEL_GEN(dev_priv) >= 12) {
15940                 intel_ddi_init(dev_priv, PORT_A);
15941                 intel_ddi_init(dev_priv, PORT_B);
15942                 intel_ddi_init(dev_priv, PORT_D);
15943                 intel_ddi_init(dev_priv, PORT_E);
15944                 intel_ddi_init(dev_priv, PORT_F);
15945                 intel_ddi_init(dev_priv, PORT_G);
15946                 intel_ddi_init(dev_priv, PORT_H);
15947                 intel_ddi_init(dev_priv, PORT_I);
15948                 icl_dsi_init(dev_priv);
15949         } else if (IS_ELKHARTLAKE(dev_priv)) {
15950                 intel_ddi_init(dev_priv, PORT_A);
15951                 intel_ddi_init(dev_priv, PORT_B);
15952                 intel_ddi_init(dev_priv, PORT_C);
15953                 intel_ddi_init(dev_priv, PORT_D);
15954                 icl_dsi_init(dev_priv);
15955         } else if (IS_GEN(dev_priv, 11)) {
15956                 intel_ddi_init(dev_priv, PORT_A);
15957                 intel_ddi_init(dev_priv, PORT_B);
15958                 intel_ddi_init(dev_priv, PORT_C);
15959                 intel_ddi_init(dev_priv, PORT_D);
15960                 intel_ddi_init(dev_priv, PORT_E);
15961                 /*
15962                  * On some ICL SKUs port F is not present. No strap bits for
15963                  * this, so rely on VBT.
15964                  * Work around broken VBTs on SKUs known to have no port F.
15965                  */
15966                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
15967                     intel_bios_is_port_present(dev_priv, PORT_F))
15968                         intel_ddi_init(dev_priv, PORT_F);
15969
15970                 icl_dsi_init(dev_priv);
15971         } else if (IS_GEN9_LP(dev_priv)) {
15972                 /*
15973                  * FIXME: Broxton doesn't support port detection via the
15974                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15975                  * detect the ports.
15976                  */
15977                 intel_ddi_init(dev_priv, PORT_A);
15978                 intel_ddi_init(dev_priv, PORT_B);
15979                 intel_ddi_init(dev_priv, PORT_C);
15980
15981                 vlv_dsi_init(dev_priv);
15982         } else if (HAS_DDI(dev_priv)) {
15983                 int found;
15984
15985                 if (intel_ddi_crt_present(dev_priv))
15986                         intel_crt_init(dev_priv);
15987
15988                 /*
15989                  * Haswell uses DDI functions to detect digital outputs.
15990                  * On SKL pre-D0 the strap isn't connected, so we assume
15991                  * it's there.
15992                  */
15993                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15994                 /* WaIgnoreDDIAStrap: skl */
15995                 if (found || IS_GEN9_BC(dev_priv))
15996                         intel_ddi_init(dev_priv, PORT_A);
15997
15998                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
15999                  * register */
16000                 found = I915_READ(SFUSE_STRAP);
16001
16002                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16003                         intel_ddi_init(dev_priv, PORT_B);
16004                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16005                         intel_ddi_init(dev_priv, PORT_C);
16006                 if (found & SFUSE_STRAP_DDID_DETECTED)
16007                         intel_ddi_init(dev_priv, PORT_D);
16008                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16009                         intel_ddi_init(dev_priv, PORT_F);
16010                 /*
16011                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16012                  */
16013                 if (IS_GEN9_BC(dev_priv) &&
16014                     intel_bios_is_port_present(dev_priv, PORT_E))
16015                         intel_ddi_init(dev_priv, PORT_E);
16016
16017         } else if (HAS_PCH_SPLIT(dev_priv)) {
16018                 int found;
16019
16020                 /*
16021                  * intel_edp_init_connector() depends on this completing first,
16022                  * to prevent the registration of both eDP and LVDS and the
16023                  * incorrect sharing of the PPS.
16024                  */
16025                 intel_lvds_init(dev_priv);
16026                 intel_crt_init(dev_priv);
16027
16028                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16029
16030                 if (ilk_has_edp_a(dev_priv))
16031                         intel_dp_init(dev_priv, DP_A, PORT_A);
16032
16033                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16034                         /* PCH SDVOB multiplex with HDMIB */
16035                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16036                         if (!found)
16037                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16038                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16039                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16040                 }
16041
16042                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16043                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16044
16045                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16046                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16047
16048                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16049                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16050
16051                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16052                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16053         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16054                 bool has_edp, has_port;
16055
16056                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16057                         intel_crt_init(dev_priv);
16058
16059                 /*
16060                  * The DP_DETECTED bit is the latched state of the DDC
16061                  * SDA pin at boot. However since eDP doesn't require DDC
16062                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16063                  * eDP ports may have been muxed to an alternate function.
16064                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16065                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16066                  * detect eDP ports.
16067                  *
16068                  * Sadly the straps seem to be missing sometimes even for HDMI
16069                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16070                  * and VBT for the presence of the port. Additionally we can't
16071                  * trust the port type the VBT declares as we've seen at least
16072                  * HDMI ports that the VBT claim are DP or eDP.
16073                  */
16074                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16075                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16076                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16077                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16078                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16079                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16080
16081                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16082                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16083                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16084                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16085                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16086                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16087
16088                 if (IS_CHERRYVIEW(dev_priv)) {
16089                         /*
16090                          * eDP not supported on port D,
16091                          * so no need to worry about it
16092                          */
16093                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16094                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16095                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16096                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16097                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16098                 }
16099
16100                 vlv_dsi_init(dev_priv);
16101         } else if (IS_PINEVIEW(dev_priv)) {
16102                 intel_lvds_init(dev_priv);
16103                 intel_crt_init(dev_priv);
16104         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16105                 bool found = false;
16106
16107                 if (IS_MOBILE(dev_priv))
16108                         intel_lvds_init(dev_priv);
16109
16110                 intel_crt_init(dev_priv);
16111
16112                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16113                         DRM_DEBUG_KMS("probing SDVOB\n");
16114                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16115                         if (!found && IS_G4X(dev_priv)) {
16116                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16117                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16118                         }
16119
16120                         if (!found && IS_G4X(dev_priv))
16121                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16122                 }
16123
16124                 /* Before G4X SDVOC doesn't have its own detect register */
16125
16126                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16127                         DRM_DEBUG_KMS("probing SDVOC\n");
16128                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16129                 }
16130
16131                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16132
16133                         if (IS_G4X(dev_priv)) {
16134                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16135                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16136                         }
16137                         if (IS_G4X(dev_priv))
16138                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16139                 }
16140
16141                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16142                         intel_dp_init(dev_priv, DP_D, PORT_D);
16143
16144                 if (SUPPORTS_TV(dev_priv))
16145                         intel_tv_init(dev_priv);
16146         } else if (IS_GEN(dev_priv, 2)) {
16147                 if (IS_I85X(dev_priv))
16148                         intel_lvds_init(dev_priv);
16149
16150                 intel_crt_init(dev_priv);
16151                 intel_dvo_init(dev_priv);
16152         }
16153
16154         intel_psr_init(dev_priv);
16155
16156         for_each_intel_encoder(&dev_priv->drm, encoder) {
16157                 encoder->base.possible_crtcs =
16158                         intel_encoder_possible_crtcs(encoder);
16159                 encoder->base.possible_clones =
16160                         intel_encoder_possible_clones(encoder);
16161         }
16162
16163         intel_init_pch_refclk(dev_priv);
16164
16165         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16166 }
16167
16168 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16169 {
16170         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16171
16172         drm_framebuffer_cleanup(fb);
16173         intel_frontbuffer_put(intel_fb->frontbuffer);
16174
16175         kfree(intel_fb);
16176 }
16177
16178 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16179                                                 struct drm_file *file,
16180                                                 unsigned int *handle)
16181 {
16182         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16183
16184         if (obj->userptr.mm) {
16185                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16186                 return -EINVAL;
16187         }
16188
16189         return drm_gem_handle_create(file, &obj->base, handle);
16190 }
16191
16192 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16193                                         struct drm_file *file,
16194                                         unsigned flags, unsigned color,
16195                                         struct drm_clip_rect *clips,
16196                                         unsigned num_clips)
16197 {
16198         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16199
16200         i915_gem_object_flush_if_display(obj);
16201         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16202
16203         return 0;
16204 }
16205
16206 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16207         .destroy = intel_user_framebuffer_destroy,
16208         .create_handle = intel_user_framebuffer_create_handle,
16209         .dirty = intel_user_framebuffer_dirty,
16210 };
16211
16212 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16213                                   struct drm_i915_gem_object *obj,
16214                                   struct drm_mode_fb_cmd2 *mode_cmd)
16215 {
16216         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16217         struct drm_framebuffer *fb = &intel_fb->base;
16218         u32 max_stride;
16219         unsigned int tiling, stride;
16220         int ret = -EINVAL;
16221         int i;
16222
16223         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16224         if (!intel_fb->frontbuffer)
16225                 return -ENOMEM;
16226
16227         i915_gem_object_lock(obj);
16228         tiling = i915_gem_object_get_tiling(obj);
16229         stride = i915_gem_object_get_stride(obj);
16230         i915_gem_object_unlock(obj);
16231
16232         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16233                 /*
16234                  * If there's a fence, enforce that
16235                  * the fb modifier and tiling mode match.
16236                  */
16237                 if (tiling != I915_TILING_NONE &&
16238                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16239                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16240                         goto err;
16241                 }
16242         } else {
16243                 if (tiling == I915_TILING_X) {
16244                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16245                 } else if (tiling == I915_TILING_Y) {
16246                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16247                         goto err;
16248                 }
16249         }
16250
16251         if (!drm_any_plane_has_format(&dev_priv->drm,
16252                                       mode_cmd->pixel_format,
16253                                       mode_cmd->modifier[0])) {
16254                 struct drm_format_name_buf format_name;
16255
16256                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16257                               drm_get_format_name(mode_cmd->pixel_format,
16258                                                   &format_name),
16259                               mode_cmd->modifier[0]);
16260                 goto err;
16261         }
16262
16263         /*
16264          * gen2/3 display engine uses the fence if present,
16265          * so the tiling mode must match the fb modifier exactly.
16266          */
16267         if (INTEL_GEN(dev_priv) < 4 &&
16268             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16269                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16270                 goto err;
16271         }
16272
16273         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16274                                          mode_cmd->modifier[0]);
16275         if (mode_cmd->pitches[0] > max_stride) {
16276                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16277                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16278                               "tiled" : "linear",
16279                               mode_cmd->pitches[0], max_stride);
16280                 goto err;
16281         }
16282
16283         /*
16284          * If there's a fence, enforce that
16285          * the fb pitch and fence stride match.
16286          */
16287         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16288                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16289                               mode_cmd->pitches[0], stride);
16290                 goto err;
16291         }
16292
16293         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16294         if (mode_cmd->offsets[0] != 0)
16295                 goto err;
16296
16297         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16298
16299         for (i = 0; i < fb->format->num_planes; i++) {
16300                 u32 stride_alignment;
16301
16302                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16303                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
16304                         goto err;
16305                 }
16306
16307                 stride_alignment = intel_fb_stride_alignment(fb, i);
16308
16309                 /*
16310                  * Display WA #0531: skl,bxt,kbl,glk
16311                  *
16312                  * Render decompression and plane width > 3840
16313                  * combined with horizontal panning requires the
16314                  * plane stride to be a multiple of 4. We'll just
16315                  * require the entire fb to accommodate that to avoid
16316                  * potential runtime errors at plane configuration time.
16317                  */
16318                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16319                     is_ccs_modifier(fb->modifier))
16320                         stride_alignment *= 4;
16321
16322                 if (fb->pitches[i] & (stride_alignment - 1)) {
16323                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16324                                       i, fb->pitches[i], stride_alignment);
16325                         goto err;
16326                 }
16327
16328                 fb->obj[i] = &obj->base;
16329         }
16330
16331         ret = intel_fill_fb_info(dev_priv, fb);
16332         if (ret)
16333                 goto err;
16334
16335         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16336         if (ret) {
16337                 DRM_ERROR("framebuffer init failed %d\n", ret);
16338                 goto err;
16339         }
16340
16341         return 0;
16342
16343 err:
16344         intel_frontbuffer_put(intel_fb->frontbuffer);
16345         return ret;
16346 }
16347
16348 static struct drm_framebuffer *
16349 intel_user_framebuffer_create(struct drm_device *dev,
16350                               struct drm_file *filp,
16351                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16352 {
16353         struct drm_framebuffer *fb;
16354         struct drm_i915_gem_object *obj;
16355         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16356
16357         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16358         if (!obj)
16359                 return ERR_PTR(-ENOENT);
16360
16361         fb = intel_framebuffer_create(obj, &mode_cmd);
16362         i915_gem_object_put(obj);
16363
16364         return fb;
16365 }
16366
16367 static void intel_atomic_state_free(struct drm_atomic_state *state)
16368 {
16369         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16370
16371         drm_atomic_state_default_release(state);
16372
16373         i915_sw_fence_fini(&intel_state->commit_ready);
16374
16375         kfree(state);
16376 }
16377
16378 static enum drm_mode_status
16379 intel_mode_valid(struct drm_device *dev,
16380                  const struct drm_display_mode *mode)
16381 {
16382         struct drm_i915_private *dev_priv = to_i915(dev);
16383         int hdisplay_max, htotal_max;
16384         int vdisplay_max, vtotal_max;
16385
16386         /*
16387          * Can't reject DBLSCAN here because Xorg ddxen can add piles
16388          * of DBLSCAN modes to the output's mode list when they detect
16389          * the scaling mode property on the connector. And they don't
16390          * ask the kernel to validate those modes in any way until
16391          * modeset time at which point the client gets a protocol error.
16392          * So in order to not upset those clients we silently ignore the
16393          * DBLSCAN flag on such connectors. For other connectors we will
16394          * reject modes with the DBLSCAN flag in encoder->compute_config().
16395          * And we always reject DBLSCAN modes in connector->mode_valid()
16396          * as we never want such modes on the connector's mode list.
16397          */
16398
16399         if (mode->vscan > 1)
16400                 return MODE_NO_VSCAN;
16401
16402         if (mode->flags & DRM_MODE_FLAG_HSKEW)
16403                 return MODE_H_ILLEGAL;
16404
16405         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16406                            DRM_MODE_FLAG_NCSYNC |
16407                            DRM_MODE_FLAG_PCSYNC))
16408                 return MODE_HSYNC;
16409
16410         if (mode->flags & (DRM_MODE_FLAG_BCAST |
16411                            DRM_MODE_FLAG_PIXMUX |
16412                            DRM_MODE_FLAG_CLKDIV2))
16413                 return MODE_BAD;
16414
16415         /* Transcoder timing limits */
16416         if (INTEL_GEN(dev_priv) >= 11) {
16417                 hdisplay_max = 16384;
16418                 vdisplay_max = 8192;
16419                 htotal_max = 16384;
16420                 vtotal_max = 8192;
16421         } else if (INTEL_GEN(dev_priv) >= 9 ||
16422                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16423                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16424                 vdisplay_max = 4096;
16425                 htotal_max = 8192;
16426                 vtotal_max = 8192;
16427         } else if (INTEL_GEN(dev_priv) >= 3) {
16428                 hdisplay_max = 4096;
16429                 vdisplay_max = 4096;
16430                 htotal_max = 8192;
16431                 vtotal_max = 8192;
16432         } else {
16433                 hdisplay_max = 2048;
16434                 vdisplay_max = 2048;
16435                 htotal_max = 4096;
16436                 vtotal_max = 4096;
16437         }
16438
16439         if (mode->hdisplay > hdisplay_max ||
16440             mode->hsync_start > htotal_max ||
16441             mode->hsync_end > htotal_max ||
16442             mode->htotal > htotal_max)
16443                 return MODE_H_ILLEGAL;
16444
16445         if (mode->vdisplay > vdisplay_max ||
16446             mode->vsync_start > vtotal_max ||
16447             mode->vsync_end > vtotal_max ||
16448             mode->vtotal > vtotal_max)
16449                 return MODE_V_ILLEGAL;
16450
16451         if (INTEL_GEN(dev_priv) >= 5) {
16452                 if (mode->hdisplay < 64 ||
16453                     mode->htotal - mode->hdisplay < 32)
16454                         return MODE_H_ILLEGAL;
16455
16456                 if (mode->vtotal - mode->vdisplay < 5)
16457                         return MODE_V_ILLEGAL;
16458         } else {
16459                 if (mode->htotal - mode->hdisplay < 32)
16460                         return MODE_H_ILLEGAL;
16461
16462                 if (mode->vtotal - mode->vdisplay < 3)
16463                         return MODE_V_ILLEGAL;
16464         }
16465
16466         return MODE_OK;
16467 }
16468
16469 enum drm_mode_status
16470 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16471                                 const struct drm_display_mode *mode)
16472 {
16473         int plane_width_max, plane_height_max;
16474
16475         /*
16476          * intel_mode_valid() should be
16477          * sufficient on older platforms.
16478          */
16479         if (INTEL_GEN(dev_priv) < 9)
16480                 return MODE_OK;
16481
16482         /*
16483          * Most people will probably want a fullscreen
16484          * plane so let's not advertize modes that are
16485          * too big for that.
16486          */
16487         if (INTEL_GEN(dev_priv) >= 11) {
16488                 plane_width_max = 5120;
16489                 plane_height_max = 4320;
16490         } else {
16491                 plane_width_max = 5120;
16492                 plane_height_max = 4096;
16493         }
16494
16495         if (mode->hdisplay > plane_width_max)
16496                 return MODE_H_ILLEGAL;
16497
16498         if (mode->vdisplay > plane_height_max)
16499                 return MODE_V_ILLEGAL;
16500
16501         return MODE_OK;
16502 }
16503
16504 static const struct drm_mode_config_funcs intel_mode_funcs = {
16505         .fb_create = intel_user_framebuffer_create,
16506         .get_format_info = intel_get_format_info,
16507         .output_poll_changed = intel_fbdev_output_poll_changed,
16508         .mode_valid = intel_mode_valid,
16509         .atomic_check = intel_atomic_check,
16510         .atomic_commit = intel_atomic_commit,
16511         .atomic_state_alloc = intel_atomic_state_alloc,
16512         .atomic_state_clear = intel_atomic_state_clear,
16513         .atomic_state_free = intel_atomic_state_free,
16514 };
16515
16516 /**
16517  * intel_init_display_hooks - initialize the display modesetting hooks
16518  * @dev_priv: device private
16519  */
16520 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16521 {
16522         intel_init_cdclk_hooks(dev_priv);
16523
16524         if (INTEL_GEN(dev_priv) >= 9) {
16525                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16526                 dev_priv->display.get_initial_plane_config =
16527                         skylake_get_initial_plane_config;
16528                 dev_priv->display.crtc_compute_clock =
16529                         haswell_crtc_compute_clock;
16530                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16531                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16532         } else if (HAS_DDI(dev_priv)) {
16533                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16534                 dev_priv->display.get_initial_plane_config =
16535                         i9xx_get_initial_plane_config;
16536                 dev_priv->display.crtc_compute_clock =
16537                         haswell_crtc_compute_clock;
16538                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16539                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16540         } else if (HAS_PCH_SPLIT(dev_priv)) {
16541                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16542                 dev_priv->display.get_initial_plane_config =
16543                         i9xx_get_initial_plane_config;
16544                 dev_priv->display.crtc_compute_clock =
16545                         ironlake_crtc_compute_clock;
16546                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16547                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16548         } else if (IS_CHERRYVIEW(dev_priv)) {
16549                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16550                 dev_priv->display.get_initial_plane_config =
16551                         i9xx_get_initial_plane_config;
16552                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16553                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16554                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16555         } else if (IS_VALLEYVIEW(dev_priv)) {
16556                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16557                 dev_priv->display.get_initial_plane_config =
16558                         i9xx_get_initial_plane_config;
16559                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16560                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16561                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16562         } else if (IS_G4X(dev_priv)) {
16563                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16564                 dev_priv->display.get_initial_plane_config =
16565                         i9xx_get_initial_plane_config;
16566                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16567                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16568                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16569         } else if (IS_PINEVIEW(dev_priv)) {
16570                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16571                 dev_priv->display.get_initial_plane_config =
16572                         i9xx_get_initial_plane_config;
16573                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16574                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16575                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16576         } else if (!IS_GEN(dev_priv, 2)) {
16577                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16578                 dev_priv->display.get_initial_plane_config =
16579                         i9xx_get_initial_plane_config;
16580                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16581                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16582                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16583         } else {
16584                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16585                 dev_priv->display.get_initial_plane_config =
16586                         i9xx_get_initial_plane_config;
16587                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16588                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16589                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16590         }
16591
16592         if (IS_GEN(dev_priv, 5)) {
16593                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16594         } else if (IS_GEN(dev_priv, 6)) {
16595                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16596         } else if (IS_IVYBRIDGE(dev_priv)) {
16597                 /* FIXME: detect B0+ stepping and use auto training */
16598                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16599         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16600                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16601         }
16602
16603         if (INTEL_GEN(dev_priv) >= 9)
16604                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16605         else
16606                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16607
16608 }
16609
16610 void intel_modeset_init_hw(struct drm_i915_private *i915)
16611 {
16612         intel_update_cdclk(i915);
16613         intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16614         i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16615 }
16616
16617 /*
16618  * Calculate what we think the watermarks should be for the state we've read
16619  * out of the hardware and then immediately program those watermarks so that
16620  * we ensure the hardware settings match our internal state.
16621  *
16622  * We can calculate what we think WM's should be by creating a duplicate of the
16623  * current state (which was constructed during hardware readout) and running it
16624  * through the atomic check code to calculate new watermark values in the
16625  * state object.
16626  */
16627 static void sanitize_watermarks(struct drm_device *dev)
16628 {
16629         struct drm_i915_private *dev_priv = to_i915(dev);
16630         struct drm_atomic_state *state;
16631         struct intel_atomic_state *intel_state;
16632         struct intel_crtc *crtc;
16633         struct intel_crtc_state *crtc_state;
16634         struct drm_modeset_acquire_ctx ctx;
16635         int ret;
16636         int i;
16637
16638         /* Only supported on platforms that use atomic watermark design */
16639         if (!dev_priv->display.optimize_watermarks)
16640                 return;
16641
16642         /*
16643          * We need to hold connection_mutex before calling duplicate_state so
16644          * that the connector loop is protected.
16645          */
16646         drm_modeset_acquire_init(&ctx, 0);
16647 retry:
16648         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16649         if (ret == -EDEADLK) {
16650                 drm_modeset_backoff(&ctx);
16651                 goto retry;
16652         } else if (WARN_ON(ret)) {
16653                 goto fail;
16654         }
16655
16656         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16657         if (WARN_ON(IS_ERR(state)))
16658                 goto fail;
16659
16660         intel_state = to_intel_atomic_state(state);
16661
16662         /*
16663          * Hardware readout is the only time we don't want to calculate
16664          * intermediate watermarks (since we don't trust the current
16665          * watermarks).
16666          */
16667         if (!HAS_GMCH(dev_priv))
16668                 intel_state->skip_intermediate_wm = true;
16669
16670         ret = intel_atomic_check(dev, state);
16671         if (ret) {
16672                 /*
16673                  * If we fail here, it means that the hardware appears to be
16674                  * programmed in a way that shouldn't be possible, given our
16675                  * understanding of watermark requirements.  This might mean a
16676                  * mistake in the hardware readout code or a mistake in the
16677                  * watermark calculations for a given platform.  Raise a WARN
16678                  * so that this is noticeable.
16679                  *
16680                  * If this actually happens, we'll have to just leave the
16681                  * BIOS-programmed watermarks untouched and hope for the best.
16682                  */
16683                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16684                 goto put_state;
16685         }
16686
16687         /* Write calculated watermark values back */
16688         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16689                 crtc_state->wm.need_postvbl_update = true;
16690                 dev_priv->display.optimize_watermarks(intel_state, crtc_state);
16691
16692                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16693         }
16694
16695 put_state:
16696         drm_atomic_state_put(state);
16697 fail:
16698         drm_modeset_drop_locks(&ctx);
16699         drm_modeset_acquire_fini(&ctx);
16700 }
16701
16702 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16703 {
16704         if (IS_GEN(dev_priv, 5)) {
16705                 u32 fdi_pll_clk =
16706                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16707
16708                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16709         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16710                 dev_priv->fdi_pll_freq = 270000;
16711         } else {
16712                 return;
16713         }
16714
16715         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16716 }
16717
16718 static int intel_initial_commit(struct drm_device *dev)
16719 {
16720         struct drm_atomic_state *state = NULL;
16721         struct drm_modeset_acquire_ctx ctx;
16722         struct drm_crtc *crtc;
16723         struct drm_crtc_state *crtc_state;
16724         int ret = 0;
16725
16726         state = drm_atomic_state_alloc(dev);
16727         if (!state)
16728                 return -ENOMEM;
16729
16730         drm_modeset_acquire_init(&ctx, 0);
16731
16732 retry:
16733         state->acquire_ctx = &ctx;
16734
16735         drm_for_each_crtc(crtc, dev) {
16736                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
16737                 if (IS_ERR(crtc_state)) {
16738                         ret = PTR_ERR(crtc_state);
16739                         goto out;
16740                 }
16741
16742                 if (crtc_state->active) {
16743                         ret = drm_atomic_add_affected_planes(state, crtc);
16744                         if (ret)
16745                                 goto out;
16746
16747                         /*
16748                          * FIXME hack to force a LUT update to avoid the
16749                          * plane update forcing the pipe gamma on without
16750                          * having a proper LUT loaded. Remove once we
16751                          * have readout for pipe gamma enable.
16752                          */
16753                         crtc_state->color_mgmt_changed = true;
16754                 }
16755         }
16756
16757         ret = drm_atomic_commit(state);
16758
16759 out:
16760         if (ret == -EDEADLK) {
16761                 drm_atomic_state_clear(state);
16762                 drm_modeset_backoff(&ctx);
16763                 goto retry;
16764         }
16765
16766         drm_atomic_state_put(state);
16767
16768         drm_modeset_drop_locks(&ctx);
16769         drm_modeset_acquire_fini(&ctx);
16770
16771         return ret;
16772 }
16773
16774 static void intel_mode_config_init(struct drm_i915_private *i915)
16775 {
16776         struct drm_mode_config *mode_config = &i915->drm.mode_config;
16777
16778         drm_mode_config_init(&i915->drm);
16779
16780         mode_config->min_width = 0;
16781         mode_config->min_height = 0;
16782
16783         mode_config->preferred_depth = 24;
16784         mode_config->prefer_shadow = 1;
16785
16786         mode_config->allow_fb_modifiers = true;
16787
16788         mode_config->funcs = &intel_mode_funcs;
16789
16790         /*
16791          * Maximum framebuffer dimensions, chosen to match
16792          * the maximum render engine surface size on gen4+.
16793          */
16794         if (INTEL_GEN(i915) >= 7) {
16795                 mode_config->max_width = 16384;
16796                 mode_config->max_height = 16384;
16797         } else if (INTEL_GEN(i915) >= 4) {
16798                 mode_config->max_width = 8192;
16799                 mode_config->max_height = 8192;
16800         } else if (IS_GEN(i915, 3)) {
16801                 mode_config->max_width = 4096;
16802                 mode_config->max_height = 4096;
16803         } else {
16804                 mode_config->max_width = 2048;
16805                 mode_config->max_height = 2048;
16806         }
16807
16808         if (IS_I845G(i915) || IS_I865G(i915)) {
16809                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16810                 mode_config->cursor_height = 1023;
16811         } else if (IS_GEN(i915, 2)) {
16812                 mode_config->cursor_width = 64;
16813                 mode_config->cursor_height = 64;
16814         } else {
16815                 mode_config->cursor_width = 256;
16816                 mode_config->cursor_height = 256;
16817         }
16818 }
16819
16820 int intel_modeset_init(struct drm_i915_private *i915)
16821 {
16822         struct drm_device *dev = &i915->drm;
16823         enum pipe pipe;
16824         struct intel_crtc *crtc;
16825         int ret;
16826
16827         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16828         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16829                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16830
16831         intel_mode_config_init(i915);
16832
16833         ret = intel_bw_init(i915);
16834         if (ret)
16835                 return ret;
16836
16837         init_llist_head(&i915->atomic_helper.free_list);
16838         INIT_WORK(&i915->atomic_helper.free_work,
16839                   intel_atomic_helper_free_state_worker);
16840
16841         intel_init_quirks(i915);
16842
16843         intel_fbc_init(i915);
16844
16845         intel_init_pm(i915);
16846
16847         intel_panel_sanitize_ssc(i915);
16848
16849         intel_gmbus_setup(i915);
16850
16851         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16852                       INTEL_NUM_PIPES(i915),
16853                       INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
16854
16855         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
16856                 for_each_pipe(i915, pipe) {
16857                         ret = intel_crtc_init(i915, pipe);
16858                         if (ret) {
16859                                 drm_mode_config_cleanup(dev);
16860                                 return ret;
16861                         }
16862                 }
16863         }
16864
16865         intel_shared_dpll_init(dev);
16866         intel_update_fdi_pll_freq(i915);
16867
16868         intel_update_czclk(i915);
16869         intel_modeset_init_hw(i915);
16870
16871         intel_hdcp_component_init(i915);
16872
16873         if (i915->max_cdclk_freq == 0)
16874                 intel_update_max_cdclk(i915);
16875
16876         /* Just disable it once at startup */
16877         intel_vga_disable(i915);
16878         intel_setup_outputs(i915);
16879
16880         drm_modeset_lock_all(dev);
16881         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
16882         drm_modeset_unlock_all(dev);
16883
16884         for_each_intel_crtc(dev, crtc) {
16885                 struct intel_initial_plane_config plane_config = {};
16886
16887                 if (!crtc->active)
16888                         continue;
16889
16890                 /*
16891                  * Note that reserving the BIOS fb up front prevents us
16892                  * from stuffing other stolen allocations like the ring
16893                  * on top.  This prevents some ugliness at boot time, and
16894                  * can even allow for smooth boot transitions if the BIOS
16895                  * fb is large enough for the active pipe configuration.
16896                  */
16897                 i915->display.get_initial_plane_config(crtc, &plane_config);
16898
16899                 /*
16900                  * If the fb is shared between multiple heads, we'll
16901                  * just get the first one.
16902                  */
16903                 intel_find_initial_plane_obj(crtc, &plane_config);
16904         }
16905
16906         /*
16907          * Make sure hardware watermarks really match the state we read out.
16908          * Note that we need to do this after reconstructing the BIOS fb's
16909          * since the watermark calculation done here will use pstate->fb.
16910          */
16911         if (!HAS_GMCH(i915))
16912                 sanitize_watermarks(dev);
16913
16914         /*
16915          * Force all active planes to recompute their states. So that on
16916          * mode_setcrtc after probe, all the intel_plane_state variables
16917          * are already calculated and there is no assert_plane warnings
16918          * during bootup.
16919          */
16920         ret = intel_initial_commit(dev);
16921         if (ret)
16922                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
16923
16924         return 0;
16925 }
16926
16927 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
16928 {
16929         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16930         /* 640x480@60Hz, ~25175 kHz */
16931         struct dpll clock = {
16932                 .m1 = 18,
16933                 .m2 = 7,
16934                 .p1 = 13,
16935                 .p2 = 4,
16936                 .n = 2,
16937         };
16938         u32 dpll, fp;
16939         int i;
16940
16941         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
16942
16943         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
16944                       pipe_name(pipe), clock.vco, clock.dot);
16945
16946         fp = i9xx_dpll_compute_fp(&clock);
16947         dpll = DPLL_DVO_2X_MODE |
16948                 DPLL_VGA_MODE_DIS |
16949                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
16950                 PLL_P2_DIVIDE_BY_4 |
16951                 PLL_REF_INPUT_DREFCLK |
16952                 DPLL_VCO_ENABLE;
16953
16954         I915_WRITE(FP0(pipe), fp);
16955         I915_WRITE(FP1(pipe), fp);
16956
16957         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
16958         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
16959         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
16960         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
16961         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
16962         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
16963         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
16964
16965         /*
16966          * Apparently we need to have VGA mode enabled prior to changing
16967          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
16968          * dividers, even though the register value does change.
16969          */
16970         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
16971         I915_WRITE(DPLL(pipe), dpll);
16972
16973         /* Wait for the clocks to stabilize. */
16974         POSTING_READ(DPLL(pipe));
16975         udelay(150);
16976
16977         /* The pixel multiplier can only be updated once the
16978          * DPLL is enabled and the clocks are stable.
16979          *
16980          * So write it again.
16981          */
16982         I915_WRITE(DPLL(pipe), dpll);
16983
16984         /* We do this three times for luck */
16985         for (i = 0; i < 3 ; i++) {
16986                 I915_WRITE(DPLL(pipe), dpll);
16987                 POSTING_READ(DPLL(pipe));
16988                 udelay(150); /* wait for warmup */
16989         }
16990
16991         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
16992         POSTING_READ(PIPECONF(pipe));
16993
16994         intel_wait_for_pipe_scanline_moving(crtc);
16995 }
16996
16997 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
16998 {
16999         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17000
17001         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17002                       pipe_name(pipe));
17003
17004         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17005         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17006         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17007         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17008         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17009
17010         I915_WRITE(PIPECONF(pipe), 0);
17011         POSTING_READ(PIPECONF(pipe));
17012
17013         intel_wait_for_pipe_scanline_stopped(crtc);
17014
17015         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17016         POSTING_READ(DPLL(pipe));
17017 }
17018
17019 static void
17020 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17021 {
17022         struct intel_crtc *crtc;
17023
17024         if (INTEL_GEN(dev_priv) >= 4)
17025                 return;
17026
17027         for_each_intel_crtc(&dev_priv->drm, crtc) {
17028                 struct intel_plane *plane =
17029                         to_intel_plane(crtc->base.primary);
17030                 struct intel_crtc *plane_crtc;
17031                 enum pipe pipe;
17032
17033                 if (!plane->get_hw_state(plane, &pipe))
17034                         continue;
17035
17036                 if (pipe == crtc->pipe)
17037                         continue;
17038
17039                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17040                               plane->base.base.id, plane->base.name);
17041
17042                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17043                 intel_plane_disable_noatomic(plane_crtc, plane);
17044         }
17045 }
17046
17047 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17048 {
17049         struct drm_device *dev = crtc->base.dev;
17050         struct intel_encoder *encoder;
17051
17052         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17053                 return true;
17054
17055         return false;
17056 }
17057
17058 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17059 {
17060         struct drm_device *dev = encoder->base.dev;
17061         struct intel_connector *connector;
17062
17063         for_each_connector_on_encoder(dev, &encoder->base, connector)
17064                 return connector;
17065
17066         return NULL;
17067 }
17068
17069 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17070                               enum pipe pch_transcoder)
17071 {
17072         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17073                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17074 }
17075
17076 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17077                                 struct drm_modeset_acquire_ctx *ctx)
17078 {
17079         struct drm_device *dev = crtc->base.dev;
17080         struct drm_i915_private *dev_priv = to_i915(dev);
17081         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17082         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17083
17084         /* Clear any frame start delays used for debugging left by the BIOS */
17085         if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
17086                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17087
17088                 I915_WRITE(reg,
17089                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
17090         }
17091
17092         if (crtc_state->base.active) {
17093                 struct intel_plane *plane;
17094
17095                 /* Disable everything but the primary plane */
17096                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17097                         const struct intel_plane_state *plane_state =
17098                                 to_intel_plane_state(plane->base.state);
17099
17100                         if (plane_state->base.visible &&
17101                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17102                                 intel_plane_disable_noatomic(crtc, plane);
17103                 }
17104
17105                 /*
17106                  * Disable any background color set by the BIOS, but enable the
17107                  * gamma and CSC to match how we program our planes.
17108                  */
17109                 if (INTEL_GEN(dev_priv) >= 9)
17110                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17111                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17112                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
17113         }
17114
17115         /* Adjust the state of the output pipe according to whether we
17116          * have active connectors/encoders. */
17117         if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
17118                 intel_crtc_disable_noatomic(&crtc->base, ctx);
17119
17120         if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
17121                 /*
17122                  * We start out with underrun reporting disabled to avoid races.
17123                  * For correct bookkeeping mark this on active crtcs.
17124                  *
17125                  * Also on gmch platforms we dont have any hardware bits to
17126                  * disable the underrun reporting. Which means we need to start
17127                  * out with underrun reporting disabled also on inactive pipes,
17128                  * since otherwise we'll complain about the garbage we read when
17129                  * e.g. coming up after runtime pm.
17130                  *
17131                  * No protection against concurrent access is required - at
17132                  * worst a fifo underrun happens which also sets this to false.
17133                  */
17134                 crtc->cpu_fifo_underrun_disabled = true;
17135                 /*
17136                  * We track the PCH trancoder underrun reporting state
17137                  * within the crtc. With crtc for pipe A housing the underrun
17138                  * reporting state for PCH transcoder A, crtc for pipe B housing
17139                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17140                  * and marking underrun reporting as disabled for the non-existing
17141                  * PCH transcoders B and C would prevent enabling the south
17142                  * error interrupt (see cpt_can_enable_serr_int()).
17143                  */
17144                 if (has_pch_trancoder(dev_priv, crtc->pipe))
17145                         crtc->pch_fifo_underrun_disabled = true;
17146         }
17147 }
17148
17149 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17150 {
17151         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
17152
17153         /*
17154          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17155          * the hardware when a high res displays plugged in. DPLL P
17156          * divider is zero, and the pipe timings are bonkers. We'll
17157          * try to disable everything in that case.
17158          *
17159          * FIXME would be nice to be able to sanitize this state
17160          * without several WARNs, but for now let's take the easy
17161          * road.
17162          */
17163         return IS_GEN(dev_priv, 6) &&
17164                 crtc_state->base.active &&
17165                 crtc_state->shared_dpll &&
17166                 crtc_state->port_clock == 0;
17167 }
17168
17169 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17170 {
17171         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17172         struct intel_connector *connector;
17173         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17174         struct intel_crtc_state *crtc_state = crtc ?
17175                 to_intel_crtc_state(crtc->base.state) : NULL;
17176
17177         /* We need to check both for a crtc link (meaning that the
17178          * encoder is active and trying to read from a pipe) and the
17179          * pipe itself being active. */
17180         bool has_active_crtc = crtc_state &&
17181                 crtc_state->base.active;
17182
17183         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17184                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17185                               pipe_name(crtc->pipe));
17186                 has_active_crtc = false;
17187         }
17188
17189         connector = intel_encoder_find_connector(encoder);
17190         if (connector && !has_active_crtc) {
17191                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17192                               encoder->base.base.id,
17193                               encoder->base.name);
17194
17195                 /* Connector is active, but has no active pipe. This is
17196                  * fallout from our resume register restoring. Disable
17197                  * the encoder manually again. */
17198                 if (crtc_state) {
17199                         struct drm_encoder *best_encoder;
17200
17201                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17202                                       encoder->base.base.id,
17203                                       encoder->base.name);
17204
17205                         /* avoid oopsing in case the hooks consult best_encoder */
17206                         best_encoder = connector->base.state->best_encoder;
17207                         connector->base.state->best_encoder = &encoder->base;
17208
17209                         if (encoder->disable)
17210                                 encoder->disable(encoder, crtc_state,
17211                                                  connector->base.state);
17212                         if (encoder->post_disable)
17213                                 encoder->post_disable(encoder, crtc_state,
17214                                                       connector->base.state);
17215
17216                         connector->base.state->best_encoder = best_encoder;
17217                 }
17218                 encoder->base.crtc = NULL;
17219
17220                 /* Inconsistent output/port/pipe state happens presumably due to
17221                  * a bug in one of the get_hw_state functions. Or someplace else
17222                  * in our code, like the register restore mess on resume. Clamp
17223                  * things to off as a safer default. */
17224
17225                 connector->base.dpms = DRM_MODE_DPMS_OFF;
17226                 connector->base.encoder = NULL;
17227         }
17228
17229         /* notify opregion of the sanitized encoder state */
17230         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17231
17232         if (INTEL_GEN(dev_priv) >= 11)
17233                 icl_sanitize_encoder_pll_mapping(encoder);
17234 }
17235
17236 /* FIXME read out full plane state for all planes */
17237 static void readout_plane_state(struct drm_i915_private *dev_priv)
17238 {
17239         struct intel_plane *plane;
17240         struct intel_crtc *crtc;
17241
17242         for_each_intel_plane(&dev_priv->drm, plane) {
17243                 struct intel_plane_state *plane_state =
17244                         to_intel_plane_state(plane->base.state);
17245                 struct intel_crtc_state *crtc_state;
17246                 enum pipe pipe = PIPE_A;
17247                 bool visible;
17248
17249                 visible = plane->get_hw_state(plane, &pipe);
17250
17251                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17252                 crtc_state = to_intel_crtc_state(crtc->base.state);
17253
17254                 intel_set_plane_visible(crtc_state, plane_state, visible);
17255
17256                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17257                               plane->base.base.id, plane->base.name,
17258                               enableddisabled(visible), pipe_name(pipe));
17259         }
17260
17261         for_each_intel_crtc(&dev_priv->drm, crtc) {
17262                 struct intel_crtc_state *crtc_state =
17263                         to_intel_crtc_state(crtc->base.state);
17264
17265                 fixup_active_planes(crtc_state);
17266         }
17267 }
17268
17269 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17270 {
17271         struct drm_i915_private *dev_priv = to_i915(dev);
17272         enum pipe pipe;
17273         struct intel_crtc *crtc;
17274         struct intel_encoder *encoder;
17275         struct intel_connector *connector;
17276         struct drm_connector_list_iter conn_iter;
17277         int i;
17278
17279         dev_priv->active_pipes = 0;
17280
17281         for_each_intel_crtc(dev, crtc) {
17282                 struct intel_crtc_state *crtc_state =
17283                         to_intel_crtc_state(crtc->base.state);
17284
17285                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
17286                 memset(crtc_state, 0, sizeof(*crtc_state));
17287                 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
17288
17289                 crtc_state->base.active = crtc_state->base.enable =
17290                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17291
17292                 crtc->base.enabled = crtc_state->base.enable;
17293                 crtc->active = crtc_state->base.active;
17294
17295                 if (crtc_state->base.active)
17296                         dev_priv->active_pipes |= BIT(crtc->pipe);
17297
17298                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17299                               crtc->base.base.id, crtc->base.name,
17300                               enableddisabled(crtc_state->base.active));
17301         }
17302
17303         readout_plane_state(dev_priv);
17304
17305         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17306                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17307
17308                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17309                                                         &pll->state.hw_state);
17310
17311                 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17312                     pll->info->id == DPLL_ID_EHL_DPLL4) {
17313                         pll->wakeref = intel_display_power_get(dev_priv,
17314                                                                POWER_DOMAIN_DPLL_DC_OFF);
17315                 }
17316
17317                 pll->state.crtc_mask = 0;
17318                 for_each_intel_crtc(dev, crtc) {
17319                         struct intel_crtc_state *crtc_state =
17320                                 to_intel_crtc_state(crtc->base.state);
17321
17322                         if (crtc_state->base.active &&
17323                             crtc_state->shared_dpll == pll)
17324                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17325                 }
17326                 pll->active_mask = pll->state.crtc_mask;
17327
17328                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17329                               pll->info->name, pll->state.crtc_mask, pll->on);
17330         }
17331
17332         for_each_intel_encoder(dev, encoder) {
17333                 pipe = 0;
17334
17335                 if (encoder->get_hw_state(encoder, &pipe)) {
17336                         struct intel_crtc_state *crtc_state;
17337
17338                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17339                         crtc_state = to_intel_crtc_state(crtc->base.state);
17340
17341                         encoder->base.crtc = &crtc->base;
17342                         encoder->get_config(encoder, crtc_state);
17343                 } else {
17344                         encoder->base.crtc = NULL;
17345                 }
17346
17347                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17348                               encoder->base.base.id, encoder->base.name,
17349                               enableddisabled(encoder->base.crtc),
17350                               pipe_name(pipe));
17351         }
17352
17353         drm_connector_list_iter_begin(dev, &conn_iter);
17354         for_each_intel_connector_iter(connector, &conn_iter) {
17355                 if (connector->get_hw_state(connector)) {
17356                         struct intel_crtc_state *crtc_state;
17357                         struct intel_crtc *crtc;
17358
17359                         connector->base.dpms = DRM_MODE_DPMS_ON;
17360
17361                         encoder = connector->encoder;
17362                         connector->base.encoder = &encoder->base;
17363
17364                         crtc = to_intel_crtc(encoder->base.crtc);
17365                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17366
17367                         if (crtc_state && crtc_state->base.active) {
17368                                 /*
17369                                  * This has to be done during hardware readout
17370                                  * because anything calling .crtc_disable may
17371                                  * rely on the connector_mask being accurate.
17372                                  */
17373                                 crtc_state->base.connector_mask |=
17374                                         drm_connector_mask(&connector->base);
17375                                 crtc_state->base.encoder_mask |=
17376                                         drm_encoder_mask(&encoder->base);
17377                         }
17378                 } else {
17379                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17380                         connector->base.encoder = NULL;
17381                 }
17382                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17383                               connector->base.base.id, connector->base.name,
17384                               enableddisabled(connector->base.encoder));
17385         }
17386         drm_connector_list_iter_end(&conn_iter);
17387
17388         for_each_intel_crtc(dev, crtc) {
17389                 struct intel_bw_state *bw_state =
17390                         to_intel_bw_state(dev_priv->bw_obj.state);
17391                 struct intel_crtc_state *crtc_state =
17392                         to_intel_crtc_state(crtc->base.state);
17393                 struct intel_plane *plane;
17394                 int min_cdclk = 0;
17395
17396                 if (crtc_state->base.active) {
17397                         struct drm_display_mode mode;
17398
17399                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode,
17400                                                     crtc_state);
17401
17402                         mode = crtc_state->base.adjusted_mode;
17403                         mode.hdisplay = crtc_state->pipe_src_w;
17404                         mode.vdisplay = crtc_state->pipe_src_h;
17405                         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->base, &mode));
17406
17407                         /*
17408                          * The initial mode needs to be set in order to keep
17409                          * the atomic core happy. It wants a valid mode if the
17410                          * crtc's enabled, so we do the above call.
17411                          *
17412                          * But we don't set all the derived state fully, hence
17413                          * set a flag to indicate that a full recalculation is
17414                          * needed on the next commit.
17415                          */
17416                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
17417
17418                         intel_crtc_compute_pixel_rate(crtc_state);
17419
17420                         intel_crtc_update_active_timings(crtc_state);
17421                 }
17422
17423                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17424                         const struct intel_plane_state *plane_state =
17425                                 to_intel_plane_state(plane->base.state);
17426
17427                         /*
17428                          * FIXME don't have the fb yet, so can't
17429                          * use intel_plane_data_rate() :(
17430                          */
17431                         if (plane_state->base.visible)
17432                                 crtc_state->data_rate[plane->id] =
17433                                         4 * crtc_state->pixel_rate;
17434                         /*
17435                          * FIXME don't have the fb yet, so can't
17436                          * use plane->min_cdclk() :(
17437                          */
17438                         if (plane_state->base.visible && plane->min_cdclk) {
17439                                 if (crtc_state->double_wide ||
17440                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17441                                         crtc_state->min_cdclk[plane->id] =
17442                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17443                                 else
17444                                         crtc_state->min_cdclk[plane->id] =
17445                                                 crtc_state->pixel_rate;
17446                         }
17447                         DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17448                                       plane->base.base.id, plane->base.name,
17449                                       crtc_state->min_cdclk[plane->id]);
17450                 }
17451
17452                 if (crtc_state->base.active) {
17453                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17454                         if (WARN_ON(min_cdclk < 0))
17455                                 min_cdclk = 0;
17456                 }
17457
17458                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17459                 dev_priv->min_voltage_level[crtc->pipe] =
17460                         crtc_state->min_voltage_level;
17461
17462                 intel_bw_crtc_update(bw_state, crtc_state);
17463
17464                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17465         }
17466 }
17467
17468 static void
17469 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17470 {
17471         struct intel_encoder *encoder;
17472
17473         for_each_intel_encoder(&dev_priv->drm, encoder) {
17474                 struct intel_crtc_state *crtc_state;
17475
17476                 if (!encoder->get_power_domains)
17477                         continue;
17478
17479                 /*
17480                  * MST-primary and inactive encoders don't have a crtc state
17481                  * and neither of these require any power domain references.
17482                  */
17483                 if (!encoder->base.crtc)
17484                         continue;
17485
17486                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17487                 encoder->get_power_domains(encoder, crtc_state);
17488         }
17489 }
17490
17491 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17492 {
17493         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17494         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17495                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17496                            DARBF_GATING_DIS);
17497
17498         if (IS_HASWELL(dev_priv)) {
17499                 /*
17500                  * WaRsPkgCStateDisplayPMReq:hsw
17501                  * System hang if this isn't done before disabling all planes!
17502                  */
17503                 I915_WRITE(CHICKEN_PAR1_1,
17504                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17505         }
17506 }
17507
17508 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17509                                        enum port port, i915_reg_t hdmi_reg)
17510 {
17511         u32 val = I915_READ(hdmi_reg);
17512
17513         if (val & SDVO_ENABLE ||
17514             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17515                 return;
17516
17517         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17518                       port_name(port));
17519
17520         val &= ~SDVO_PIPE_SEL_MASK;
17521         val |= SDVO_PIPE_SEL(PIPE_A);
17522
17523         I915_WRITE(hdmi_reg, val);
17524 }
17525
17526 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17527                                      enum port port, i915_reg_t dp_reg)
17528 {
17529         u32 val = I915_READ(dp_reg);
17530
17531         if (val & DP_PORT_EN ||
17532             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17533                 return;
17534
17535         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17536                       port_name(port));
17537
17538         val &= ~DP_PIPE_SEL_MASK;
17539         val |= DP_PIPE_SEL(PIPE_A);
17540
17541         I915_WRITE(dp_reg, val);
17542 }
17543
17544 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17545 {
17546         /*
17547          * The BIOS may select transcoder B on some of the PCH
17548          * ports even it doesn't enable the port. This would trip
17549          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17550          * Sanitize the transcoder select bits to prevent that. We
17551          * assume that the BIOS never actually enabled the port,
17552          * because if it did we'd actually have to toggle the port
17553          * on and back off to make the transcoder A select stick
17554          * (see. intel_dp_link_down(), intel_disable_hdmi(),
17555          * intel_disable_sdvo()).
17556          */
17557         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17558         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17559         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17560
17561         /* PCH SDVOB multiplex with HDMIB */
17562         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17563         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17564         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17565 }
17566
17567 /* Scan out the current hw modeset state,
17568  * and sanitizes it to the current state
17569  */
17570 static void
17571 intel_modeset_setup_hw_state(struct drm_device *dev,
17572                              struct drm_modeset_acquire_ctx *ctx)
17573 {
17574         struct drm_i915_private *dev_priv = to_i915(dev);
17575         struct intel_crtc_state *crtc_state;
17576         struct intel_encoder *encoder;
17577         struct intel_crtc *crtc;
17578         intel_wakeref_t wakeref;
17579         int i;
17580
17581         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17582
17583         intel_early_display_was(dev_priv);
17584         intel_modeset_readout_hw_state(dev);
17585
17586         /* HW state is read out, now we need to sanitize this mess. */
17587
17588         /* Sanitize the TypeC port mode upfront, encoders depend on this */
17589         for_each_intel_encoder(dev, encoder) {
17590                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17591
17592                 /* We need to sanitize only the MST primary port. */
17593                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17594                     intel_phy_is_tc(dev_priv, phy))
17595                         intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17596         }
17597
17598         get_encoder_power_domains(dev_priv);
17599
17600         if (HAS_PCH_IBX(dev_priv))
17601                 ibx_sanitize_pch_ports(dev_priv);
17602
17603         /*
17604          * intel_sanitize_plane_mapping() may need to do vblank
17605          * waits, so we need vblank interrupts restored beforehand.
17606          */
17607         for_each_intel_crtc(&dev_priv->drm, crtc) {
17608                 crtc_state = to_intel_crtc_state(crtc->base.state);
17609
17610                 drm_crtc_vblank_reset(&crtc->base);
17611
17612                 if (crtc_state->base.active)
17613                         intel_crtc_vblank_on(crtc_state);
17614         }
17615
17616         intel_sanitize_plane_mapping(dev_priv);
17617
17618         for_each_intel_encoder(dev, encoder)
17619                 intel_sanitize_encoder(encoder);
17620
17621         for_each_intel_crtc(&dev_priv->drm, crtc) {
17622                 crtc_state = to_intel_crtc_state(crtc->base.state);
17623                 intel_sanitize_crtc(crtc, ctx);
17624                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17625         }
17626
17627         intel_modeset_update_connector_atomic_state(dev);
17628
17629         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17630                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17631
17632                 if (!pll->on || pll->active_mask)
17633                         continue;
17634
17635                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17636                               pll->info->name);
17637
17638                 pll->info->funcs->disable(dev_priv, pll);
17639                 pll->on = false;
17640         }
17641
17642         if (IS_G4X(dev_priv)) {
17643                 g4x_wm_get_hw_state(dev_priv);
17644                 g4x_wm_sanitize(dev_priv);
17645         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17646                 vlv_wm_get_hw_state(dev_priv);
17647                 vlv_wm_sanitize(dev_priv);
17648         } else if (INTEL_GEN(dev_priv) >= 9) {
17649                 skl_wm_get_hw_state(dev_priv);
17650         } else if (HAS_PCH_SPLIT(dev_priv)) {
17651                 ilk_wm_get_hw_state(dev_priv);
17652         }
17653
17654         for_each_intel_crtc(dev, crtc) {
17655                 u64 put_domains;
17656
17657                 crtc_state = to_intel_crtc_state(crtc->base.state);
17658                 put_domains = modeset_get_crtc_power_domains(crtc_state);
17659                 if (WARN_ON(put_domains))
17660                         modeset_put_power_domains(dev_priv, put_domains);
17661         }
17662
17663         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17664
17665         intel_fbc_init_pipe_state(dev_priv);
17666 }
17667
17668 void intel_display_resume(struct drm_device *dev)
17669 {
17670         struct drm_i915_private *dev_priv = to_i915(dev);
17671         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17672         struct drm_modeset_acquire_ctx ctx;
17673         int ret;
17674
17675         dev_priv->modeset_restore_state = NULL;
17676         if (state)
17677                 state->acquire_ctx = &ctx;
17678
17679         drm_modeset_acquire_init(&ctx, 0);
17680
17681         while (1) {
17682                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17683                 if (ret != -EDEADLK)
17684                         break;
17685
17686                 drm_modeset_backoff(&ctx);
17687         }
17688
17689         if (!ret)
17690                 ret = __intel_display_resume(dev, state, &ctx);
17691
17692         intel_enable_ipc(dev_priv);
17693         drm_modeset_drop_locks(&ctx);
17694         drm_modeset_acquire_fini(&ctx);
17695
17696         if (ret)
17697                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17698         if (state)
17699                 drm_atomic_state_put(state);
17700 }
17701
17702 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17703 {
17704         struct intel_connector *connector;
17705         struct drm_connector_list_iter conn_iter;
17706
17707         /* Kill all the work that may have been queued by hpd. */
17708         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17709         for_each_intel_connector_iter(connector, &conn_iter) {
17710                 if (connector->modeset_retry_work.func)
17711                         cancel_work_sync(&connector->modeset_retry_work);
17712                 if (connector->hdcp.shim) {
17713                         cancel_delayed_work_sync(&connector->hdcp.check_work);
17714                         cancel_work_sync(&connector->hdcp.prop_work);
17715                 }
17716         }
17717         drm_connector_list_iter_end(&conn_iter);
17718 }
17719
17720 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17721 {
17722         flush_workqueue(i915->flip_wq);
17723         flush_workqueue(i915->modeset_wq);
17724
17725         flush_work(&i915->atomic_helper.free_work);
17726         WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17727
17728         /*
17729          * Interrupts and polling as the first thing to avoid creating havoc.
17730          * Too much stuff here (turning of connectors, ...) would
17731          * experience fancy races otherwise.
17732          */
17733         intel_irq_uninstall(i915);
17734
17735         /*
17736          * Due to the hpd irq storm handling the hotplug work can re-arm the
17737          * poll handlers. Hence disable polling after hpd handling is shut down.
17738          */
17739         intel_hpd_poll_fini(i915);
17740
17741         /* poll work can call into fbdev, hence clean that up afterwards */
17742         intel_fbdev_fini(i915);
17743
17744         intel_unregister_dsm_handler();
17745
17746         intel_fbc_global_disable(i915);
17747
17748         /* flush any delayed tasks or pending work */
17749         flush_scheduled_work();
17750
17751         intel_hdcp_component_fini(i915);
17752
17753         drm_mode_config_cleanup(&i915->drm);
17754
17755         intel_overlay_cleanup(i915);
17756
17757         intel_gmbus_teardown(i915);
17758
17759         destroy_workqueue(i915->flip_wq);
17760         destroy_workqueue(i915->modeset_wq);
17761
17762         intel_fbc_cleanup_cfb(i915);
17763 }
17764
17765 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17766
17767 struct intel_display_error_state {
17768
17769         u32 power_well_driver;
17770
17771         struct intel_cursor_error_state {
17772                 u32 control;
17773                 u32 position;
17774                 u32 base;
17775                 u32 size;
17776         } cursor[I915_MAX_PIPES];
17777
17778         struct intel_pipe_error_state {
17779                 bool power_domain_on;
17780                 u32 source;
17781                 u32 stat;
17782         } pipe[I915_MAX_PIPES];
17783
17784         struct intel_plane_error_state {
17785                 u32 control;
17786                 u32 stride;
17787                 u32 size;
17788                 u32 pos;
17789                 u32 addr;
17790                 u32 surface;
17791                 u32 tile_offset;
17792         } plane[I915_MAX_PIPES];
17793
17794         struct intel_transcoder_error_state {
17795                 bool available;
17796                 bool power_domain_on;
17797                 enum transcoder cpu_transcoder;
17798
17799                 u32 conf;
17800
17801                 u32 htotal;
17802                 u32 hblank;
17803                 u32 hsync;
17804                 u32 vtotal;
17805                 u32 vblank;
17806                 u32 vsync;
17807         } transcoder[5];
17808 };
17809
17810 struct intel_display_error_state *
17811 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17812 {
17813         struct intel_display_error_state *error;
17814         int transcoders[] = {
17815                 TRANSCODER_A,
17816                 TRANSCODER_B,
17817                 TRANSCODER_C,
17818                 TRANSCODER_D,
17819                 TRANSCODER_EDP,
17820         };
17821         int i;
17822
17823         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
17824
17825         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
17826                 return NULL;
17827
17828         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17829         if (error == NULL)
17830                 return NULL;
17831
17832         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17833                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
17834
17835         for_each_pipe(dev_priv, i) {
17836                 error->pipe[i].power_domain_on =
17837                         __intel_display_power_is_enabled(dev_priv,
17838                                                          POWER_DOMAIN_PIPE(i));
17839                 if (!error->pipe[i].power_domain_on)
17840                         continue;
17841
17842                 error->cursor[i].control = I915_READ(CURCNTR(i));
17843                 error->cursor[i].position = I915_READ(CURPOS(i));
17844                 error->cursor[i].base = I915_READ(CURBASE(i));
17845
17846                 error->plane[i].control = I915_READ(DSPCNTR(i));
17847                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17848                 if (INTEL_GEN(dev_priv) <= 3) {
17849                         error->plane[i].size = I915_READ(DSPSIZE(i));
17850                         error->plane[i].pos = I915_READ(DSPPOS(i));
17851                 }
17852                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17853                         error->plane[i].addr = I915_READ(DSPADDR(i));
17854                 if (INTEL_GEN(dev_priv) >= 4) {
17855                         error->plane[i].surface = I915_READ(DSPSURF(i));
17856                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17857                 }
17858
17859                 error->pipe[i].source = I915_READ(PIPESRC(i));
17860
17861                 if (HAS_GMCH(dev_priv))
17862                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17863         }
17864
17865         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17866                 enum transcoder cpu_transcoder = transcoders[i];
17867
17868                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
17869                         continue;
17870
17871                 error->transcoder[i].available = true;
17872                 error->transcoder[i].power_domain_on =
17873                         __intel_display_power_is_enabled(dev_priv,
17874                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17875                 if (!error->transcoder[i].power_domain_on)
17876                         continue;
17877
17878                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17879
17880                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17881                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17882                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17883                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17884                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17885                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17886                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17887         }
17888
17889         return error;
17890 }
17891
17892 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17893
17894 void
17895 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17896                                 struct intel_display_error_state *error)
17897 {
17898         struct drm_i915_private *dev_priv = m->i915;
17899         int i;
17900
17901         if (!error)
17902                 return;
17903
17904         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
17905         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17906                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17907                            error->power_well_driver);
17908         for_each_pipe(dev_priv, i) {
17909                 err_printf(m, "Pipe [%d]:\n", i);
17910                 err_printf(m, "  Power: %s\n",
17911                            onoff(error->pipe[i].power_domain_on));
17912                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17913                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17914
17915                 err_printf(m, "Plane [%d]:\n", i);
17916                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17917                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17918                 if (INTEL_GEN(dev_priv) <= 3) {
17919                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17920                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17921                 }
17922                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17923                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17924                 if (INTEL_GEN(dev_priv) >= 4) {
17925                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17926                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17927                 }
17928
17929                 err_printf(m, "Cursor [%d]:\n", i);
17930                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17931                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17932                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17933         }
17934
17935         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17936                 if (!error->transcoder[i].available)
17937                         continue;
17938
17939                 err_printf(m, "CPU transcoder: %s\n",
17940                            transcoder_name(error->transcoder[i].cpu_transcoder));
17941                 err_printf(m, "  Power: %s\n",
17942                            onoff(error->transcoder[i].power_domain_on));
17943                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17944                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17945                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17946                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17947                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17948                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17949                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17950         }
17951 }
17952
17953 #endif