drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "display/intel_crt.h"
  46 #include "display/intel_ddi.h"
  47 #include "display/intel_dp.h"
  48 #include "display/intel_dp_mst.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ilk_pch_clock_get(struct intel_crtc *crtc,
 149                               struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
 168 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 169 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 170                                          struct drm_modeset_acquire_ctx *ctx);
 171 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
 172
 173 struct intel_limit {
 174         struct {
 175                 int min, max;
 176         } dot, vco, n, m, m1, m2, p, p1;
 177
 178         struct {
 179                 int dot_limit;
 180                 int p2_slow, p2_fast;
 181         } p2;
 182 };
 183
 184 /* returns HPLL frequency in kHz */
 185 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 186 {
 187         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 188
 189         /* Obtain SKU information */
 190         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 191                 CCK_FUSE_HPLL_FREQ_MASK;
 192
 193         return vco_freq[hpll_freq] * 1000;
 194 }
 195
 196 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 197                       const char *name, u32 reg, int ref_freq)
 198 {
 199         u32 val;
 200         int divider;
 201
 202         val = vlv_cck_read(dev_priv, reg);
 203         divider = val & CCK_FREQUENCY_VALUES;
 204
 205         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 206                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 207                  "%s change in progress\n", name);
 208
 209         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 210 }
 211
 212 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 213                            const char *name, u32 reg)
 214 {
 215         int hpll;
 216
 217         vlv_cck_get(dev_priv);
 218
 219         if (dev_priv->hpll_freq == 0)
 220                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 221
 222         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 223
 224         vlv_cck_put(dev_priv);
 225
 226         return hpll;
 227 }
 228
 229 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 230 {
 231         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 232                 return;
 233
 234         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 235                                                       CCK_CZ_CLOCK_CONTROL);
 236
 237         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 238                 dev_priv->czclk_freq);
 239 }
 240
 241 /* units of 100MHz */
 242 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 243                                const struct intel_crtc_state *pipe_config)
 244 {
 245         if (HAS_DDI(dev_priv))
 246                 return pipe_config->port_clock; /* SPLL */
 247         else
 248                 return dev_priv->fdi_pll_freq;
 249 }
 250
 251 static const struct intel_limit intel_limits_i8xx_dac = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 2 },
 262 };
 263
 264 static const struct intel_limit intel_limits_i8xx_dvo = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 4 },
 275 };
 276
 277 static const struct intel_limit intel_limits_i8xx_lvds = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 1, .max = 6 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 14, .p2_fast = 7 },
 288 };
 289
 290 static const struct intel_limit intel_limits_i9xx_sdvo = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 200000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301 };
 302
 303 static const struct intel_limit intel_limits_i9xx_lvds = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 7, .max = 98 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 112000,
 313                 .p2_slow = 14, .p2_fast = 7 },
 314 };
 315
 316
 317 static const struct intel_limit intel_limits_g4x_sdvo = {
 318         .dot = { .min = 25000, .max = 270000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 17, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 10, .max = 30 },
 325         .p1 = { .min = 1, .max = 3},
 326         .p2 = { .dot_limit = 270000,
 327                 .p2_slow = 10,
 328                 .p2_fast = 10
 329         },
 330 };
 331
 332 static const struct intel_limit intel_limits_g4x_hdmi = {
 333         .dot = { .min = 22000, .max = 400000 },
 334         .vco = { .min = 1750000, .max = 3500000},
 335         .n = { .min = 1, .max = 4 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 16, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 5, .max = 80 },
 340         .p1 = { .min = 1, .max = 8},
 341         .p2 = { .dot_limit = 165000,
 342                 .p2_slow = 10, .p2_fast = 5 },
 343 };
 344
 345 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 346         .dot = { .min = 20000, .max = 115000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 14, .p2_fast = 14
 356         },
 357 };
 358
 359 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 360         .dot = { .min = 80000, .max = 224000 },
 361         .vco = { .min = 1750000, .max = 3500000 },
 362         .n = { .min = 1, .max = 3 },
 363         .m = { .min = 104, .max = 138 },
 364         .m1 = { .min = 17, .max = 23 },
 365         .m2 = { .min = 5, .max = 11 },
 366         .p = { .min = 14, .max = 42 },
 367         .p1 = { .min = 2, .max = 6 },
 368         .p2 = { .dot_limit = 0,
 369                 .p2_slow = 7, .p2_fast = 7
 370         },
 371 };
 372
 373 static const struct intel_limit pnv_limits_sdvo = {
 374         .dot = { .min = 20000, .max = 400000},
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         /* Pineview's Ncounter is a ring counter */
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         /* Pineview only has one combined m divider, which we treat as m2. */
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 5, .max = 80 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 200000,
 385                 .p2_slow = 10, .p2_fast = 5 },
 386 };
 387
 388 static const struct intel_limit pnv_limits_lvds = {
 389         .dot = { .min = 20000, .max = 400000 },
 390         .vco = { .min = 1700000, .max = 3500000 },
 391         .n = { .min = 3, .max = 6 },
 392         .m = { .min = 2, .max = 256 },
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 7, .max = 112 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 112000,
 398                 .p2_slow = 14, .p2_fast = 14 },
 399 };
 400
 401 /* Ironlake / Sandybridge
 402  *
 403  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 404  * the range value for them is (actual_value - 2).
 405  */
 406 static const struct intel_limit ilk_limits_dac = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 5 },
 410         .m = { .min = 79, .max = 127 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 5, .max = 80 },
 414         .p1 = { .min = 1, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 10, .p2_fast = 5 },
 417 };
 418
 419 static const struct intel_limit ilk_limits_single_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 118 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 28, .max = 112 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 14, .p2_fast = 14 },
 430 };
 431
 432 static const struct intel_limit ilk_limits_dual_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 127 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 14, .max = 56 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 7, .p2_fast = 7 },
 443 };
 444
 445 /* LVDS 100mhz refclk limits. */
 446 static const struct intel_limit ilk_limits_single_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 2 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 28, .max = 112 },
 454         .p1 = { .min = 2, .max = 8 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 14, .p2_fast = 14 },
 457 };
 458
 459 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 3 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 14, .max = 42 },
 467         .p1 = { .min = 2, .max = 6 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 7, .p2_fast = 7 },
 470 };
 471
 472 static const struct intel_limit intel_limits_vlv = {
 473          /*
 474           * These are the data rate limits (measured in fast clocks)
 475           * since those are the strictest limits we have. The fast
 476           * clock and actual rate limits are more relaxed, so checking
 477           * them would make no difference.
 478           */
 479         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 480         .vco = { .min = 4000000, .max = 6000000 },
 481         .n = { .min = 1, .max = 7 },
 482         .m1 = { .min = 2, .max = 3 },
 483         .m2 = { .min = 11, .max = 156 },
 484         .p1 = { .min = 2, .max = 3 },
 485         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 486 };
 487
 488 static const struct intel_limit intel_limits_chv = {
 489         /*
 490          * These are the data rate limits (measured in fast clocks)
 491          * since those are the strictest limits we have.  The fast
 492          * clock and actual rate limits are more relaxed, so checking
 493          * them would make no difference.
 494          */
 495         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 496         .vco = { .min = 4800000, .max = 6480000 },
 497         .n = { .min = 1, .max = 1 },
 498         .m1 = { .min = 2, .max = 2 },
 499         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 500         .p1 = { .min = 2, .max = 4 },
 501         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 502 };
 503
 504 static const struct intel_limit intel_limits_bxt = {
 505         /* FIXME: find real dot limits */
 506         .dot = { .min = 0, .max = INT_MAX },
 507         .vco = { .min = 4800000, .max = 6700000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         /* FIXME: find real m2 limits */
 511         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 514 };
 515
 516 /* WA Display #0827: Gen9:all */
 517 static void
 518 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 519 {
 520         if (enable)
 521                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 522                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 523         else
 524                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 525                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 526 }
 527
 528 /* Wa_2006604312:icl,ehl */
 529 static void
 530 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 531                        bool enable)
 532 {
 533         if (enable)
 534                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 535                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 536         else
 537                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 538                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 539 }
 540
 541 static bool
 542 needs_modeset(const struct intel_crtc_state *state)
 543 {
 544         return drm_atomic_crtc_needs_modeset(&state->uapi);
 545 }
 546
 547 static bool
 548 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 549 {
 550         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 551 }
 552
 553 static bool
 554 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 555 {
 556         return crtc_state->sync_mode_slaves_mask != 0;
 557 }
 558
 559 bool
 560 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 561 {
 562         return is_trans_port_sync_master(crtc_state) ||
 563                 is_trans_port_sync_slave(crtc_state);
 564 }
 565
 566 /*
 567  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 568  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 569  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 570  * The helpers' return value is the rate of the clock that is fed to the
 571  * display engine's pipe which can be the above fast dot clock rate or a
 572  * divided-down version of it.
 573  */
 574 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 575 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 576 {
 577         clock->m = clock->m2 + 2;
 578         clock->p = clock->p1 * clock->p2;
 579         if (WARN_ON(clock->n == 0 || clock->p == 0))
 580                 return 0;
 581         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 582         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 583
 584         return clock->dot;
 585 }
 586
 587 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 588 {
 589         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 590 }
 591
 592 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 593 {
 594         clock->m = i9xx_dpll_compute_m(clock);
 595         clock->p = clock->p1 * clock->p2;
 596         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 597                 return 0;
 598         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 599         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 600
 601         return clock->dot;
 602 }
 603
 604 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 605 {
 606         clock->m = clock->m1 * clock->m2;
 607         clock->p = clock->p1 * clock->p2;
 608         if (WARN_ON(clock->n == 0 || clock->p == 0))
 609                 return 0;
 610         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 611         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 612
 613         return clock->dot / 5;
 614 }
 615
 616 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 617 {
 618         clock->m = clock->m1 * clock->m2;
 619         clock->p = clock->p1 * clock->p2;
 620         if (WARN_ON(clock->n == 0 || clock->p == 0))
 621                 return 0;
 622         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 623                                            clock->n << 22);
 624         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 625
 626         return clock->dot / 5;
 627 }
 628
 629 /*
 630  * Returns whether the given set of divisors are valid for a given refclk with
 631  * the given connectors.
 632  */
 633 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 634                                const struct intel_limit *limit,
 635                                const struct dpll *clock)
 636 {
 637         if (clock->n < limit->n.min || limit->n.max < clock->n)
 638                 return false;
 639         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 640                 return false;
 641         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 642                 return false;
 643         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 644                 return false;
 645
 646         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 647             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 648                 if (clock->m1 <= clock->m2)
 649                         return false;
 650
 651         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 652             !IS_GEN9_LP(dev_priv)) {
 653                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 654                         return false;
 655                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 656                         return false;
 657         }
 658
 659         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 660                 return false;
 661         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 662          * connector, etc., rather than just a single range.
 663          */
 664         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 665                 return false;
 666
 667         return true;
 668 }
 669
 670 static int
 671 i9xx_select_p2_div(const struct intel_limit *limit,
 672                    const struct intel_crtc_state *crtc_state,
 673                    int target)
 674 {
 675         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 676
 677         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 678                 /*
 679                  * For LVDS just rely on its current settings for dual-channel.
 680                  * We haven't figured out how to reliably set up different
 681                  * single/dual channel state, if we even can.
 682                  */
 683                 if (intel_is_dual_link_lvds(dev_priv))
 684                         return limit->p2.p2_fast;
 685                 else
 686                         return limit->p2.p2_slow;
 687         } else {
 688                 if (target < limit->p2.dot_limit)
 689                         return limit->p2.p2_slow;
 690                 else
 691                         return limit->p2.p2_fast;
 692         }
 693 }
 694
 695 /*
 696  * Returns a set of divisors for the desired target clock with the given
 697  * refclk, or FALSE.  The returned values represent the clock equation:
 698  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 699  *
 700  * Target and reference clocks are specified in kHz.
 701  *
 702  * If match_clock is provided, then best_clock P divider must match the P
 703  * divider from @match_clock used for LVDS downclocking.
 704  */
 705 static bool
 706 i9xx_find_best_dpll(const struct intel_limit *limit,
 707                     struct intel_crtc_state *crtc_state,
 708                     int target, int refclk, struct dpll *match_clock,
 709                     struct dpll *best_clock)
 710 {
 711         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 712         struct dpll clock;
 713         int err = target;
 714
 715         memset(best_clock, 0, sizeof(*best_clock));
 716
 717         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 718
 719         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 720              clock.m1++) {
 721                 for (clock.m2 = limit->m2.min;
 722                      clock.m2 <= limit->m2.max; clock.m2++) {
 723                         if (clock.m2 >= clock.m1)
 724                                 break;
 725                         for (clock.n = limit->n.min;
 726                              clock.n <= limit->n.max; clock.n++) {
 727                                 for (clock.p1 = limit->p1.min;
 728                                         clock.p1 <= limit->p1.max; clock.p1++) {
 729                                         int this_err;
 730
 731                                         i9xx_calc_dpll_params(refclk, &clock);
 732                                         if (!intel_pll_is_valid(to_i915(dev),
 733                                                                 limit,
 734                                                                 &clock))
 735                                                 continue;
 736                                         if (match_clock &&
 737                                             clock.p != match_clock->p)
 738                                                 continue;
 739
 740                                         this_err = abs(clock.dot - target);
 741                                         if (this_err < err) {
 742                                                 *best_clock = clock;
 743                                                 err = this_err;
 744                                         }
 745                                 }
 746                         }
 747                 }
 748         }
 749
 750         return (err != target);
 751 }
 752
 753 /*
 754  * Returns a set of divisors for the desired target clock with the given
 755  * refclk, or FALSE.  The returned values represent the clock equation:
 756  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 757  *
 758  * Target and reference clocks are specified in kHz.
 759  *
 760  * If match_clock is provided, then best_clock P divider must match the P
 761  * divider from @match_clock used for LVDS downclocking.
 762  */
 763 static bool
 764 pnv_find_best_dpll(const struct intel_limit *limit,
 765                    struct intel_crtc_state *crtc_state,
 766                    int target, int refclk, struct dpll *match_clock,
 767                    struct dpll *best_clock)
 768 {
 769         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 770         struct dpll clock;
 771         int err = target;
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774
 775         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 776
 777         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 778              clock.m1++) {
 779                 for (clock.m2 = limit->m2.min;
 780                      clock.m2 <= limit->m2.max; clock.m2++) {
 781                         for (clock.n = limit->n.min;
 782                              clock.n <= limit->n.max; clock.n++) {
 783                                 for (clock.p1 = limit->p1.min;
 784                                         clock.p1 <= limit->p1.max; clock.p1++) {
 785                                         int this_err;
 786
 787                                         pnv_calc_dpll_params(refclk, &clock);
 788                                         if (!intel_pll_is_valid(to_i915(dev),
 789                                                                 limit,
 790                                                                 &clock))
 791                                                 continue;
 792                                         if (match_clock &&
 793                                             clock.p != match_clock->p)
 794                                                 continue;
 795
 796                                         this_err = abs(clock.dot - target);
 797                                         if (this_err < err) {
 798                                                 *best_clock = clock;
 799                                                 err = this_err;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805
 806         return (err != target);
 807 }
 808
 809 /*
 810  * Returns a set of divisors for the desired target clock with the given
 811  * refclk, or FALSE.  The returned values represent the clock equation:
 812  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 813  *
 814  * Target and reference clocks are specified in kHz.
 815  *
 816  * If match_clock is provided, then best_clock P divider must match the P
 817  * divider from @match_clock used for LVDS downclocking.
 818  */
 819 static bool
 820 g4x_find_best_dpll(const struct intel_limit *limit,
 821                    struct intel_crtc_state *crtc_state,
 822                    int target, int refclk, struct dpll *match_clock,
 823                    struct dpll *best_clock)
 824 {
 825         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 826         struct dpll clock;
 827         int max_n;
 828         bool found = false;
 829         /* approximately equals target * 0.00585 */
 830         int err_most = (target >> 8) + (target >> 9);
 831
 832         memset(best_clock, 0, sizeof(*best_clock));
 833
 834         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 835
 836         max_n = limit->n.max;
 837         /* based on hardware requirement, prefer smaller n to precision */
 838         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 839                 /* based on hardware requirement, prefere larger m1,m2 */
 840                 for (clock.m1 = limit->m1.max;
 841                      clock.m1 >= limit->m1.min; clock.m1--) {
 842                         for (clock.m2 = limit->m2.max;
 843                              clock.m2 >= limit->m2.min; clock.m2--) {
 844                                 for (clock.p1 = limit->p1.max;
 845                                      clock.p1 >= limit->p1.min; clock.p1--) {
 846                                         int this_err;
 847
 848                                         i9xx_calc_dpll_params(refclk, &clock);
 849                                         if (!intel_pll_is_valid(to_i915(dev),
 850                                                                 limit,
 851                                                                 &clock))
 852                                                 continue;
 853
 854                                         this_err = abs(clock.dot - target);
 855                                         if (this_err < err_most) {
 856                                                 *best_clock = clock;
 857                                                 err_most = this_err;
 858                                                 max_n = clock.n;
 859                                                 found = true;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865         return found;
 866 }
 867
 868 /*
 869  * Check if the calculated PLL configuration is more optimal compared to the
 870  * best configuration and error found so far. Return the calculated error.
 871  */
 872 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 873                                const struct dpll *calculated_clock,
 874                                const struct dpll *best_clock,
 875                                unsigned int best_error_ppm,
 876                                unsigned int *error_ppm)
 877 {
 878         /*
 879          * For CHV ignore the error and consider only the P value.
 880          * Prefer a bigger P value based on HW requirements.
 881          */
 882         if (IS_CHERRYVIEW(to_i915(dev))) {
 883                 *error_ppm = 0;
 884
 885                 return calculated_clock->p > best_clock->p;
 886         }
 887
 888         if (drm_WARN_ON_ONCE(dev, !target_freq))
 889                 return false;
 890
 891         *error_ppm = div_u64(1000000ULL *
 892                                 abs(target_freq - calculated_clock->dot),
 893                              target_freq);
 894         /*
 895          * Prefer a better P value over a better (smaller) error if the error
 896          * is small. Ensure this preference for future configurations too by
 897          * setting the error to 0.
 898          */
 899         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 900                 *error_ppm = 0;
 901
 902                 return true;
 903         }
 904
 905         return *error_ppm + 10 < best_error_ppm;
 906 }
 907
 908 /*
 909  * Returns a set of divisors for the desired target clock with the given
 910  * refclk, or FALSE.  The returned values represent the clock equation:
 911  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 912  */
 913 static bool
 914 vlv_find_best_dpll(const struct intel_limit *limit,
 915                    struct intel_crtc_state *crtc_state,
 916                    int target, int refclk, struct dpll *match_clock,
 917                    struct dpll *best_clock)
 918 {
 919         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 920         struct drm_device *dev = crtc->base.dev;
 921         struct dpll clock;
 922         unsigned int bestppm = 1000000;
 923         /* min update 19.2 MHz */
 924         int max_n = min(limit->n.max, refclk / 19200);
 925         bool found = false;
 926
 927         target *= 5; /* fast clock */
 928
 929         memset(best_clock, 0, sizeof(*best_clock));
 930
 931         /* based on hardware requirement, prefer smaller n to precision */
 932         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 933                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 934                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 935                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 936                                 clock.p = clock.p1 * clock.p2;
 937                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 938                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 939                                         unsigned int ppm;
 940
 941                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 942                                                                      refclk * clock.m1);
 943
 944                                         vlv_calc_dpll_params(refclk, &clock);
 945
 946                                         if (!intel_pll_is_valid(to_i915(dev),
 947                                                                 limit,
 948                                                                 &clock))
 949                                                 continue;
 950
 951                                         if (!vlv_PLL_is_optimal(dev, target,
 952                                                                 &clock,
 953                                                                 best_clock,
 954                                                                 bestppm, &ppm))
 955                                                 continue;
 956
 957                                         *best_clock = clock;
 958                                         bestppm = ppm;
 959                                         found = true;
 960                                 }
 961                         }
 962                 }
 963         }
 964
 965         return found;
 966 }
 967
 968 /*
 969  * Returns a set of divisors for the desired target clock with the given
 970  * refclk, or FALSE.  The returned values represent the clock equation:
 971  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 972  */
 973 static bool
 974 chv_find_best_dpll(const struct intel_limit *limit,
 975                    struct intel_crtc_state *crtc_state,
 976                    int target, int refclk, struct dpll *match_clock,
 977                    struct dpll *best_clock)
 978 {
 979         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 980         struct drm_device *dev = crtc->base.dev;
 981         unsigned int best_error_ppm;
 982         struct dpll clock;
 983         u64 m2;
 984         int found = false;
 985
 986         memset(best_clock, 0, sizeof(*best_clock));
 987         best_error_ppm = 1000000;
 988
 989         /*
 990          * Based on hardware doc, the n always set to 1, and m1 always
 991          * set to 2.  If requires to support 200Mhz refclk, we need to
 992          * revisit this because n may not 1 anymore.
 993          */
 994         clock.n = 1, clock.m1 = 2;
 995         target *= 5;    /* fast clock */
 996
 997         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 998                 for (clock.p2 = limit->p2.p2_fast;
 999                                 clock.p2 >= limit->p2.p2_slow;
1000                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1001                         unsigned int error_ppm;
1002
1003                         clock.p = clock.p1 * clock.p2;
1004
1005                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1006                                                    refclk * clock.m1);
1007
1008                         if (m2 > INT_MAX/clock.m1)
1009                                 continue;
1010
1011                         clock.m2 = m2;
1012
1013                         chv_calc_dpll_params(refclk, &clock);
1014
1015                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1016                                 continue;
1017
1018                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1019                                                 best_error_ppm, &error_ppm))
1020                                 continue;
1021
1022                         *best_clock = clock;
1023                         best_error_ppm = error_ppm;
1024                         found = true;
1025                 }
1026         }
1027
1028         return found;
1029 }
1030
1031 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1032                         struct dpll *best_clock)
1033 {
1034         int refclk = 100000;
1035         const struct intel_limit *limit = &intel_limits_bxt;
1036
1037         return chv_find_best_dpll(limit, crtc_state,
1038                                   crtc_state->port_clock, refclk,
1039                                   NULL, best_clock);
1040 }
1041
1042 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1043                                     enum pipe pipe)
1044 {
1045         i915_reg_t reg = PIPEDSL(pipe);
1046         u32 line1, line2;
1047         u32 line_mask;
1048
1049         if (IS_GEN(dev_priv, 2))
1050                 line_mask = DSL_LINEMASK_GEN2;
1051         else
1052                 line_mask = DSL_LINEMASK_GEN3;
1053
1054         line1 = intel_de_read(dev_priv, reg) & line_mask;
1055         msleep(5);
1056         line2 = intel_de_read(dev_priv, reg) & line_mask;
1057
1058         return line1 != line2;
1059 }
1060
1061 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1062 {
1063         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1064         enum pipe pipe = crtc->pipe;
1065
1066         /* Wait for the display line to settle/start moving */
1067         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1068                 drm_err(&dev_priv->drm,
1069                         "pipe %c scanline %s wait timed out\n",
1070                         pipe_name(pipe), onoff(state));
1071 }
1072
1073 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1074 {
1075         wait_for_pipe_scanline_moving(crtc, false);
1076 }
1077
1078 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1079 {
1080         wait_for_pipe_scanline_moving(crtc, true);
1081 }
1082
1083 static void
1084 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1085 {
1086         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1087         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1088
1089         if (INTEL_GEN(dev_priv) >= 4) {
1090                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1091                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1092
1093                 /* Wait for the Pipe State to go off */
1094                 if (intel_de_wait_for_clear(dev_priv, reg,
1095                                             I965_PIPECONF_ACTIVE, 100))
1096                         drm_WARN(&dev_priv->drm, 1,
1097                                  "pipe_off wait timed out\n");
1098         } else {
1099                 intel_wait_for_pipe_scanline_stopped(crtc);
1100         }
1101 }
1102
1103 /* Only for pre-ILK configs */
1104 void assert_pll(struct drm_i915_private *dev_priv,
1105                 enum pipe pipe, bool state)
1106 {
1107         u32 val;
1108         bool cur_state;
1109
1110         val = intel_de_read(dev_priv, DPLL(pipe));
1111         cur_state = !!(val & DPLL_VCO_ENABLE);
1112         I915_STATE_WARN(cur_state != state,
1113              "PLL state assertion failure (expected %s, current %s)\n",
1114                         onoff(state), onoff(cur_state));
1115 }
1116
1117 /* XXX: the dsi pll is shared between MIPI DSI ports */
1118 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         vlv_cck_get(dev_priv);
1124         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1125         vlv_cck_put(dev_priv);
1126
1127         cur_state = val & DSI_PLL_VCO_EN;
1128         I915_STATE_WARN(cur_state != state,
1129              "DSI PLL state assertion failure (expected %s, current %s)\n",
1130                         onoff(state), onoff(cur_state));
1131 }
1132
1133 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1134                           enum pipe pipe, bool state)
1135 {
1136         bool cur_state;
1137
1138         if (HAS_DDI(dev_priv)) {
1139                 /*
1140                  * DDI does not have a specific FDI_TX register.
1141                  *
1142                  * FDI is never fed from EDP transcoder
1143                  * so pipe->transcoder cast is fine here.
1144                  */
1145                 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1146                 u32 val = intel_de_read(dev_priv,
1147                                         TRANS_DDI_FUNC_CTL(cpu_transcoder));
1148                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1149         } else {
1150                 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1151                 cur_state = !!(val & FDI_TX_ENABLE);
1152         }
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI TX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1158 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1159
1160 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1161                           enum pipe pipe, bool state)
1162 {
1163         u32 val;
1164         bool cur_state;
1165
1166         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1167         cur_state = !!(val & FDI_RX_ENABLE);
1168         I915_STATE_WARN(cur_state != state,
1169              "FDI RX state assertion failure (expected %s, current %s)\n",
1170                         onoff(state), onoff(cur_state));
1171 }
1172 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1173 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1174
1175 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1176                                       enum pipe pipe)
1177 {
1178         u32 val;
1179
1180         /* ILK FDI PLL is always enabled */
1181         if (IS_GEN(dev_priv, 5))
1182                 return;
1183
1184         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1185         if (HAS_DDI(dev_priv))
1186                 return;
1187
1188         val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1189         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1193                        enum pipe pipe, bool state)
1194 {
1195         u32 val;
1196         bool cur_state;
1197
1198         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1199         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1200         I915_STATE_WARN(cur_state != state,
1201              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1202                         onoff(state), onoff(cur_state));
1203 }
1204
1205 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1206 {
1207         i915_reg_t pp_reg;
1208         u32 val;
1209         enum pipe panel_pipe = INVALID_PIPE;
1210         bool locked = true;
1211
1212         if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1213                 return;
1214
1215         if (HAS_PCH_SPLIT(dev_priv)) {
1216                 u32 port_sel;
1217
1218                 pp_reg = PP_CONTROL(0);
1219                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1220
1221                 switch (port_sel) {
1222                 case PANEL_PORT_SELECT_LVDS:
1223                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1224                         break;
1225                 case PANEL_PORT_SELECT_DPA:
1226                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1227                         break;
1228                 case PANEL_PORT_SELECT_DPC:
1229                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1230                         break;
1231                 case PANEL_PORT_SELECT_DPD:
1232                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1233                         break;
1234                 default:
1235                         MISSING_CASE(port_sel);
1236                         break;
1237                 }
1238         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1239                 /* presumably write lock depends on pipe, not port select */
1240                 pp_reg = PP_CONTROL(pipe);
1241                 panel_pipe = pipe;
1242         } else {
1243                 u32 port_sel;
1244
1245                 pp_reg = PP_CONTROL(0);
1246                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1247
1248                 drm_WARN_ON(&dev_priv->drm,
1249                             port_sel != PANEL_PORT_SELECT_LVDS);
1250                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1251         }
1252
1253         val = intel_de_read(dev_priv, pp_reg);
1254         if (!(val & PANEL_POWER_ON) ||
1255             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1256                 locked = false;
1257
1258         I915_STATE_WARN(panel_pipe == pipe && locked,
1259              "panel assertion failure, pipe %c regs locked\n",
1260              pipe_name(pipe));
1261 }
1262
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264                  enum transcoder cpu_transcoder, bool state)
1265 {
1266         bool cur_state;
1267         enum intel_display_power_domain power_domain;
1268         intel_wakeref_t wakeref;
1269
1270         /* we keep both pipes enabled on 830 */
1271         if (IS_I830(dev_priv))
1272                 state = true;
1273
1274         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1275         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1276         if (wakeref) {
1277                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1278                 cur_state = !!(val & PIPECONF_ENABLE);
1279
1280                 intel_display_power_put(dev_priv, power_domain, wakeref);
1281         } else {
1282                 cur_state = false;
1283         }
1284
1285         I915_STATE_WARN(cur_state != state,
1286                         "transcoder %s assertion failure (expected %s, current %s)\n",
1287                         transcoder_name(cpu_transcoder),
1288                         onoff(state), onoff(cur_state));
1289 }
1290
1291 static void assert_plane(struct intel_plane *plane, bool state)
1292 {
1293         enum pipe pipe;
1294         bool cur_state;
1295
1296         cur_state = plane->get_hw_state(plane, &pipe);
1297
1298         I915_STATE_WARN(cur_state != state,
1299                         "%s assertion failure (expected %s, current %s)\n",
1300                         plane->base.name, onoff(state), onoff(cur_state));
1301 }
1302
1303 #define assert_plane_enabled(p) assert_plane(p, true)
1304 #define assert_plane_disabled(p) assert_plane(p, false)
1305
1306 static void assert_planes_disabled(struct intel_crtc *crtc)
1307 {
1308         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1309         struct intel_plane *plane;
1310
1311         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1312                 assert_plane_disabled(plane);
1313 }
1314
1315 static void assert_vblank_disabled(struct drm_crtc *crtc)
1316 {
1317         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1318                 drm_crtc_vblank_put(crtc);
1319 }
1320
1321 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322                                     enum pipe pipe)
1323 {
1324         u32 val;
1325         bool enabled;
1326
1327         val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1328         enabled = !!(val & TRANS_ENABLE);
1329         I915_STATE_WARN(enabled,
1330              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331              pipe_name(pipe));
1332 }
1333
1334 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1335                                    enum pipe pipe, enum port port,
1336                                    i915_reg_t dp_reg)
1337 {
1338         enum pipe port_pipe;
1339         bool state;
1340
1341         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1342
1343         I915_STATE_WARN(state && port_pipe == pipe,
1344                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1345                         port_name(port), pipe_name(pipe));
1346
1347         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1348                         "IBX PCH DP %c still using transcoder B\n",
1349                         port_name(port));
1350 }
1351
1352 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1353                                      enum pipe pipe, enum port port,
1354                                      i915_reg_t hdmi_reg)
1355 {
1356         enum pipe port_pipe;
1357         bool state;
1358
1359         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1360
1361         I915_STATE_WARN(state && port_pipe == pipe,
1362                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1363                         port_name(port), pipe_name(pipe));
1364
1365         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1366                         "IBX PCH HDMI %c still using transcoder B\n",
1367                         port_name(port));
1368 }
1369
1370 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1371                                       enum pipe pipe)
1372 {
1373         enum pipe port_pipe;
1374
1375         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1376         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1377         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1378
1379         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1380                         port_pipe == pipe,
1381                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1382                         pipe_name(pipe));
1383
1384         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1385                         port_pipe == pipe,
1386                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1387                         pipe_name(pipe));
1388
1389         /* PCH SDVOB multiplex with HDMIB */
1390         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1391         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1392         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1393 }
1394
1395 static void _vlv_enable_pll(struct intel_crtc *crtc,
1396                             const struct intel_crtc_state *pipe_config)
1397 {
1398         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1399         enum pipe pipe = crtc->pipe;
1400
1401         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1402         intel_de_posting_read(dev_priv, DPLL(pipe));
1403         udelay(150);
1404
1405         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1406                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1407 }
1408
1409 static void vlv_enable_pll(struct intel_crtc *crtc,
1410                            const struct intel_crtc_state *pipe_config)
1411 {
1412         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1413         enum pipe pipe = crtc->pipe;
1414
1415         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1416
1417         /* PLL is protected by panel, make sure we can write it */
1418         assert_panel_unlocked(dev_priv, pipe);
1419
1420         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1421                 _vlv_enable_pll(crtc, pipe_config);
1422
1423         intel_de_write(dev_priv, DPLL_MD(pipe),
1424                        pipe_config->dpll_hw_state.dpll_md);
1425         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1426 }
1427
1428
1429 static void _chv_enable_pll(struct intel_crtc *crtc,
1430                             const struct intel_crtc_state *pipe_config)
1431 {
1432         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1433         enum pipe pipe = crtc->pipe;
1434         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1435         u32 tmp;
1436
1437         vlv_dpio_get(dev_priv);
1438
1439         /* Enable back the 10bit clock to display controller */
1440         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1441         tmp |= DPIO_DCLKP_EN;
1442         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1443
1444         vlv_dpio_put(dev_priv);
1445
1446         /*
1447          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1448          */
1449         udelay(1);
1450
1451         /* Enable PLL */
1452         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1453
1454         /* Check PLL is locked */
1455         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1456                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1457 }
1458
1459 static void chv_enable_pll(struct intel_crtc *crtc,
1460                            const struct intel_crtc_state *pipe_config)
1461 {
1462         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1463         enum pipe pipe = crtc->pipe;
1464
1465         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1466
1467         /* PLL is protected by panel, make sure we can write it */
1468         assert_panel_unlocked(dev_priv, pipe);
1469
1470         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1471                 _chv_enable_pll(crtc, pipe_config);
1472
1473         if (pipe != PIPE_A) {
1474                 /*
1475                  * WaPixelRepeatModeFixForC0:chv
1476                  *
1477                  * DPLLCMD is AWOL. Use chicken bits to propagate
1478                  * the value from DPLLBMD to either pipe B or C.
1479                  */
1480                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1481                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1482                                pipe_config->dpll_hw_state.dpll_md);
1483                 intel_de_write(dev_priv, CBR4_VLV, 0);
1484                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1485
1486                 /*
1487                  * DPLLB VGA mode also seems to cause problems.
1488                  * We should always have it disabled.
1489                  */
1490                 drm_WARN_ON(&dev_priv->drm,
1491                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1492                              DPLL_VGA_MODE_DIS) == 0);
1493         } else {
1494                 intel_de_write(dev_priv, DPLL_MD(pipe),
1495                                pipe_config->dpll_hw_state.dpll_md);
1496                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1497         }
1498 }
1499
1500 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1501 {
1502         if (IS_I830(dev_priv))
1503                 return false;
1504
1505         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1506 }
1507
1508 static void i9xx_enable_pll(struct intel_crtc *crtc,
1509                             const struct intel_crtc_state *crtc_state)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1512         i915_reg_t reg = DPLL(crtc->pipe);
1513         u32 dpll = crtc_state->dpll_hw_state.dpll;
1514         int i;
1515
1516         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         if (i9xx_has_pps(dev_priv))
1520                 assert_panel_unlocked(dev_priv, crtc->pipe);
1521
1522         /*
1523          * Apparently we need to have VGA mode enabled prior to changing
1524          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1525          * dividers, even though the register value does change.
1526          */
1527         intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1528         intel_de_write(dev_priv, reg, dpll);
1529
1530         /* Wait for the clocks to stabilize. */
1531         intel_de_posting_read(dev_priv, reg);
1532         udelay(150);
1533
1534         if (INTEL_GEN(dev_priv) >= 4) {
1535                 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1536                                crtc_state->dpll_hw_state.dpll_md);
1537         } else {
1538                 /* The pixel multiplier can only be updated once the
1539                  * DPLL is enabled and the clocks are stable.
1540                  *
1541                  * So write it again.
1542                  */
1543                 intel_de_write(dev_priv, reg, dpll);
1544         }
1545
1546         /* We do this three times for luck */
1547         for (i = 0; i < 3; i++) {
1548                 intel_de_write(dev_priv, reg, dpll);
1549                 intel_de_posting_read(dev_priv, reg);
1550                 udelay(150); /* wait for warmup */
1551         }
1552 }
1553
1554 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1555 {
1556         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1558         enum pipe pipe = crtc->pipe;
1559
1560         /* Don't disable pipe or pipe PLLs if needed */
1561         if (IS_I830(dev_priv))
1562                 return;
1563
1564         /* Make sure the pipe isn't still relying on us */
1565         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1566
1567         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1568         intel_de_posting_read(dev_priv, DPLL(pipe));
1569 }
1570
1571 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1572 {
1573         u32 val;
1574
1575         /* Make sure the pipe isn't still relying on us */
1576         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1577
1578         val = DPLL_INTEGRATED_REF_CLK_VLV |
1579                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1580         if (pipe != PIPE_A)
1581                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1582
1583         intel_de_write(dev_priv, DPLL(pipe), val);
1584         intel_de_posting_read(dev_priv, DPLL(pipe));
1585 }
1586
1587 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1588 {
1589         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1590         u32 val;
1591
1592         /* Make sure the pipe isn't still relying on us */
1593         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1594
1595         val = DPLL_SSC_REF_CLK_CHV |
1596                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1597         if (pipe != PIPE_A)
1598                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1599
1600         intel_de_write(dev_priv, DPLL(pipe), val);
1601         intel_de_posting_read(dev_priv, DPLL(pipe));
1602
1603         vlv_dpio_get(dev_priv);
1604
1605         /* Disable 10bit clock to display controller */
1606         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1607         val &= ~DPIO_DCLKP_EN;
1608         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1609
1610         vlv_dpio_put(dev_priv);
1611 }
1612
1613 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1614                          struct intel_digital_port *dport,
1615                          unsigned int expected_mask)
1616 {
1617         u32 port_mask;
1618         i915_reg_t dpll_reg;
1619
1620         switch (dport->base.port) {
1621         case PORT_B:
1622                 port_mask = DPLL_PORTB_READY_MASK;
1623                 dpll_reg = DPLL(0);
1624                 break;
1625         case PORT_C:
1626                 port_mask = DPLL_PORTC_READY_MASK;
1627                 dpll_reg = DPLL(0);
1628                 expected_mask <<= 4;
1629                 break;
1630         case PORT_D:
1631                 port_mask = DPLL_PORTD_READY_MASK;
1632                 dpll_reg = DPIO_PHY_STATUS;
1633                 break;
1634         default:
1635                 BUG();
1636         }
1637
1638         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1639                                        port_mask, expected_mask, 1000))
1640                 drm_WARN(&dev_priv->drm, 1,
1641                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1642                          dport->base.base.base.id, dport->base.base.name,
1643                          intel_de_read(dev_priv, dpll_reg) & port_mask,
1644                          expected_mask);
1645 }
1646
1647 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1648 {
1649         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1650         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1651         enum pipe pipe = crtc->pipe;
1652         i915_reg_t reg;
1653         u32 val, pipeconf_val;
1654
1655         /* Make sure PCH DPLL is enabled */
1656         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1657
1658         /* FDI must be feeding us bits for PCH ports */
1659         assert_fdi_tx_enabled(dev_priv, pipe);
1660         assert_fdi_rx_enabled(dev_priv, pipe);
1661
1662         if (HAS_PCH_CPT(dev_priv)) {
1663                 reg = TRANS_CHICKEN2(pipe);
1664                 val = intel_de_read(dev_priv, reg);
1665                 /*
1666                  * Workaround: Set the timing override bit
1667                  * before enabling the pch transcoder.
1668                  */
1669                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1670                 /* Configure frame start delay to match the CPU */
1671                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1672                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1673                 intel_de_write(dev_priv, reg, val);
1674         }
1675
1676         reg = PCH_TRANSCONF(pipe);
1677         val = intel_de_read(dev_priv, reg);
1678         pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1679
1680         if (HAS_PCH_IBX(dev_priv)) {
1681                 /* Configure frame start delay to match the CPU */
1682                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1683                 val |= TRANS_FRAME_START_DELAY(0);
1684
1685                 /*
1686                  * Make the BPC in transcoder be consistent with
1687                  * that in pipeconf reg. For HDMI we must use 8bpc
1688                  * here for both 8bpc and 12bpc.
1689                  */
1690                 val &= ~PIPECONF_BPC_MASK;
1691                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1692                         val |= PIPECONF_8BPC;
1693                 else
1694                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1695         }
1696
1697         val &= ~TRANS_INTERLACE_MASK;
1698         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1699                 if (HAS_PCH_IBX(dev_priv) &&
1700                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1701                         val |= TRANS_LEGACY_INTERLACED_ILK;
1702                 else
1703                         val |= TRANS_INTERLACED;
1704         } else {
1705                 val |= TRANS_PROGRESSIVE;
1706         }
1707
1708         intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1709         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1710                 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1711                         pipe_name(pipe));
1712 }
1713
1714 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1715                                       enum transcoder cpu_transcoder)
1716 {
1717         u32 val, pipeconf_val;
1718
1719         /* FDI must be feeding us bits for PCH ports */
1720         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1721         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1722
1723         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1724         /* Workaround: set timing override bit. */
1725         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1726         /* Configure frame start delay to match the CPU */
1727         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1728         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1729         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1730
1731         val = TRANS_ENABLE;
1732         pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1733
1734         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1735             PIPECONF_INTERLACED_ILK)
1736                 val |= TRANS_INTERLACED;
1737         else
1738                 val |= TRANS_PROGRESSIVE;
1739
1740         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1741         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1742                                   TRANS_STATE_ENABLE, 100))
1743                 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1744 }
1745
1746 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1747                                        enum pipe pipe)
1748 {
1749         i915_reg_t reg;
1750         u32 val;
1751
1752         /* FDI relies on the transcoder */
1753         assert_fdi_tx_disabled(dev_priv, pipe);
1754         assert_fdi_rx_disabled(dev_priv, pipe);
1755
1756         /* Ports must be off as well */
1757         assert_pch_ports_disabled(dev_priv, pipe);
1758
1759         reg = PCH_TRANSCONF(pipe);
1760         val = intel_de_read(dev_priv, reg);
1761         val &= ~TRANS_ENABLE;
1762         intel_de_write(dev_priv, reg, val);
1763         /* wait for PCH transcoder off, transcoder state */
1764         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1765                 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1766                         pipe_name(pipe));
1767
1768         if (HAS_PCH_CPT(dev_priv)) {
1769                 /* Workaround: Clear the timing override chicken bit again. */
1770                 reg = TRANS_CHICKEN2(pipe);
1771                 val = intel_de_read(dev_priv, reg);
1772                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1773                 intel_de_write(dev_priv, reg, val);
1774         }
1775 }
1776
1777 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1778 {
1779         u32 val;
1780
1781         val = intel_de_read(dev_priv, LPT_TRANSCONF);
1782         val &= ~TRANS_ENABLE;
1783         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1784         /* wait for PCH transcoder off, transcoder state */
1785         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1786                                     TRANS_STATE_ENABLE, 50))
1787                 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1788
1789         /* Workaround: clear timing override bit. */
1790         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1791         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1792         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1793 }
1794
1795 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1796 {
1797         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1798
1799         if (HAS_PCH_LPT(dev_priv))
1800                 return PIPE_A;
1801         else
1802                 return crtc->pipe;
1803 }
1804
1805 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1806 {
1807         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1808
1809         /*
1810          * On i965gm the hardware frame counter reads
1811          * zero when the TV encoder is enabled :(
1812          */
1813         if (IS_I965GM(dev_priv) &&
1814             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1815                 return 0;
1816
1817         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1818                 return 0xffffffff; /* full 32 bit counter */
1819         else if (INTEL_GEN(dev_priv) >= 3)
1820                 return 0xffffff; /* only 24 bits of frame count */
1821         else
1822                 return 0; /* Gen2 doesn't have a hardware frame counter */
1823 }
1824
1825 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1826 {
1827         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1828
1829         assert_vblank_disabled(&crtc->base);
1830         drm_crtc_set_max_vblank_count(&crtc->base,
1831                                       intel_crtc_max_vblank_count(crtc_state));
1832         drm_crtc_vblank_on(&crtc->base);
1833 }
1834
1835 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1836 {
1837         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1838
1839         drm_crtc_vblank_off(&crtc->base);
1840         assert_vblank_disabled(&crtc->base);
1841 }
1842
1843 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1844 {
1845         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1847         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1848         enum pipe pipe = crtc->pipe;
1849         i915_reg_t reg;
1850         u32 val;
1851
1852         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1853
1854         assert_planes_disabled(crtc);
1855
1856         /*
1857          * A pipe without a PLL won't actually be able to drive bits from
1858          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1859          * need the check.
1860          */
1861         if (HAS_GMCH(dev_priv)) {
1862                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1863                         assert_dsi_pll_enabled(dev_priv);
1864                 else
1865                         assert_pll_enabled(dev_priv, pipe);
1866         } else {
1867                 if (new_crtc_state->has_pch_encoder) {
1868                         /* if driving the PCH, we need FDI enabled */
1869                         assert_fdi_rx_pll_enabled(dev_priv,
1870                                                   intel_crtc_pch_transcoder(crtc));
1871                         assert_fdi_tx_pll_enabled(dev_priv,
1872                                                   (enum pipe) cpu_transcoder);
1873                 }
1874                 /* FIXME: assert CPU port conditions for SNB+ */
1875         }
1876
1877         trace_intel_pipe_enable(crtc);
1878
1879         reg = PIPECONF(cpu_transcoder);
1880         val = intel_de_read(dev_priv, reg);
1881         if (val & PIPECONF_ENABLE) {
1882                 /* we keep both pipes enabled on 830 */
1883                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1884                 return;
1885         }
1886
1887         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1888         intel_de_posting_read(dev_priv, reg);
1889
1890         /*
1891          * Until the pipe starts PIPEDSL reads will return a stale value,
1892          * which causes an apparent vblank timestamp jump when PIPEDSL
1893          * resets to its proper value. That also messes up the frame count
1894          * when it's derived from the timestamps. So let's wait for the
1895          * pipe to start properly before we call drm_crtc_vblank_on()
1896          */
1897         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1898                 intel_wait_for_pipe_scanline_moving(crtc);
1899 }
1900
1901 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1902 {
1903         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1904         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1905         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1906         enum pipe pipe = crtc->pipe;
1907         i915_reg_t reg;
1908         u32 val;
1909
1910         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1911
1912         /*
1913          * Make sure planes won't keep trying to pump pixels to us,
1914          * or we might hang the display.
1915          */
1916         assert_planes_disabled(crtc);
1917
1918         trace_intel_pipe_disable(crtc);
1919
1920         reg = PIPECONF(cpu_transcoder);
1921         val = intel_de_read(dev_priv, reg);
1922         if ((val & PIPECONF_ENABLE) == 0)
1923                 return;
1924
1925         /*
1926          * Double wide has implications for planes
1927          * so best keep it disabled when not needed.
1928          */
1929         if (old_crtc_state->double_wide)
1930                 val &= ~PIPECONF_DOUBLE_WIDE;
1931
1932         /* Don't disable pipe or pipe PLLs if needed */
1933         if (!IS_I830(dev_priv))
1934                 val &= ~PIPECONF_ENABLE;
1935
1936         intel_de_write(dev_priv, reg, val);
1937         if ((val & PIPECONF_ENABLE) == 0)
1938                 intel_wait_for_pipe_off(old_crtc_state);
1939 }
1940
1941 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1942 {
1943         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1944 }
1945
1946 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1947 {
1948         if (!is_ccs_modifier(fb->modifier))
1949                 return false;
1950
1951         return plane >= fb->format->num_planes / 2;
1952 }
1953
1954 static bool is_gen12_ccs_modifier(u64 modifier)
1955 {
1956         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1957                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1958
1959 }
1960
1961 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1962 {
1963         return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1964 }
1965
1966 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1967 {
1968         if (is_ccs_modifier(fb->modifier))
1969                 return is_ccs_plane(fb, plane);
1970
1971         return plane == 1;
1972 }
1973
1974 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1975 {
1976         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1977                     (main_plane && main_plane >= fb->format->num_planes / 2));
1978
1979         return fb->format->num_planes / 2 + main_plane;
1980 }
1981
1982 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1983 {
1984         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1985                     ccs_plane < fb->format->num_planes / 2);
1986
1987         return ccs_plane - fb->format->num_planes / 2;
1988 }
1989
1990 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1991 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1992 {
1993         if (is_ccs_modifier(fb->modifier))
1994                 return main_to_ccs_plane(fb, main_plane);
1995
1996         return 1;
1997 }
1998
1999 bool
2000 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2001                                     uint64_t modifier)
2002 {
2003         return info->is_yuv &&
2004                info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2005 }
2006
2007 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2008                                    int color_plane)
2009 {
2010         return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2011                color_plane == 1;
2012 }
2013
2014 static unsigned int
2015 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2016 {
2017         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2018         unsigned int cpp = fb->format->cpp[color_plane];
2019
2020         switch (fb->modifier) {
2021         case DRM_FORMAT_MOD_LINEAR:
2022                 return intel_tile_size(dev_priv);
2023         case I915_FORMAT_MOD_X_TILED:
2024                 if (IS_GEN(dev_priv, 2))
2025                         return 128;
2026                 else
2027                         return 512;
2028         case I915_FORMAT_MOD_Y_TILED_CCS:
2029                 if (is_ccs_plane(fb, color_plane))
2030                         return 128;
2031                 /* fall through */
2032         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2033         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2034                 if (is_ccs_plane(fb, color_plane))
2035                         return 64;
2036                 /* fall through */
2037         case I915_FORMAT_MOD_Y_TILED:
2038                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2039                         return 128;
2040                 else
2041                         return 512;
2042         case I915_FORMAT_MOD_Yf_TILED_CCS:
2043                 if (is_ccs_plane(fb, color_plane))
2044                         return 128;
2045                 /* fall through */
2046         case I915_FORMAT_MOD_Yf_TILED:
2047                 switch (cpp) {
2048                 case 1:
2049                         return 64;
2050                 case 2:
2051                 case 4:
2052                         return 128;
2053                 case 8:
2054                 case 16:
2055                         return 256;
2056                 default:
2057                         MISSING_CASE(cpp);
2058                         return cpp;
2059                 }
2060                 break;
2061         default:
2062                 MISSING_CASE(fb->modifier);
2063                 return cpp;
2064         }
2065 }
2066
2067 static unsigned int
2068 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2069 {
2070         if (is_gen12_ccs_plane(fb, color_plane))
2071                 return 1;
2072
2073         return intel_tile_size(to_i915(fb->dev)) /
2074                 intel_tile_width_bytes(fb, color_plane);
2075 }
2076
2077 /* Return the tile dimensions in pixel units */
2078 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2079                             unsigned int *tile_width,
2080                             unsigned int *tile_height)
2081 {
2082         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2083         unsigned int cpp = fb->format->cpp[color_plane];
2084
2085         *tile_width = tile_width_bytes / cpp;
2086         *tile_height = intel_tile_height(fb, color_plane);
2087 }
2088
2089 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2090                                         int color_plane)
2091 {
2092         unsigned int tile_width, tile_height;
2093
2094         intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2095
2096         return fb->pitches[color_plane] * tile_height;
2097 }
2098
2099 unsigned int
2100 intel_fb_align_height(const struct drm_framebuffer *fb,
2101                       int color_plane, unsigned int height)
2102 {
2103         unsigned int tile_height = intel_tile_height(fb, color_plane);
2104
2105         return ALIGN(height, tile_height);
2106 }
2107
2108 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2109 {
2110         unsigned int size = 0;
2111         int i;
2112
2113         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2114                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2115
2116         return size;
2117 }
2118
2119 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2120 {
2121         unsigned int size = 0;
2122         int i;
2123
2124         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2125                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2126
2127         return size;
2128 }
2129
2130 static void
2131 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2132                         const struct drm_framebuffer *fb,
2133                         unsigned int rotation)
2134 {
2135         view->type = I915_GGTT_VIEW_NORMAL;
2136         if (drm_rotation_90_or_270(rotation)) {
2137                 view->type = I915_GGTT_VIEW_ROTATED;
2138                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2139         }
2140 }
2141
2142 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2143 {
2144         if (IS_I830(dev_priv))
2145                 return 16 * 1024;
2146         else if (IS_I85X(dev_priv))
2147                 return 256;
2148         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2149                 return 32;
2150         else
2151                 return 4 * 1024;
2152 }
2153
2154 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2155 {
2156         if (INTEL_GEN(dev_priv) >= 9)
2157                 return 256 * 1024;
2158         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2159                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2160                 return 128 * 1024;
2161         else if (INTEL_GEN(dev_priv) >= 4)
2162                 return 4 * 1024;
2163         else
2164                 return 0;
2165 }
2166
2167 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2168                                          int color_plane)
2169 {
2170         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2171
2172         /* AUX_DIST needs only 4K alignment */
2173         if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2174             is_ccs_plane(fb, color_plane))
2175                 return 4096;
2176
2177         switch (fb->modifier) {
2178         case DRM_FORMAT_MOD_LINEAR:
2179                 return intel_linear_alignment(dev_priv);
2180         case I915_FORMAT_MOD_X_TILED:
2181                 if (INTEL_GEN(dev_priv) >= 9)
2182                         return 256 * 1024;
2183                 return 0;
2184         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2185                 if (is_semiplanar_uv_plane(fb, color_plane))
2186                         return intel_tile_row_size(fb, color_plane);
2187                 /* Fall-through */
2188         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2189                 return 16 * 1024;
2190         case I915_FORMAT_MOD_Y_TILED_CCS:
2191         case I915_FORMAT_MOD_Yf_TILED_CCS:
2192         case I915_FORMAT_MOD_Y_TILED:
2193                 if (INTEL_GEN(dev_priv) >= 12 &&
2194                     is_semiplanar_uv_plane(fb, color_plane))
2195                         return intel_tile_row_size(fb, color_plane);
2196                 /* Fall-through */
2197         case I915_FORMAT_MOD_Yf_TILED:
2198                 return 1 * 1024 * 1024;
2199         default:
2200                 MISSING_CASE(fb->modifier);
2201                 return 0;
2202         }
2203 }
2204
2205 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2206 {
2207         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2208         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2209
2210         return INTEL_GEN(dev_priv) < 4 ||
2211                 (plane->has_fbc &&
2212                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2213 }
2214
2215 struct i915_vma *
2216 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2217                            const struct i915_ggtt_view *view,
2218                            bool uses_fence,
2219                            unsigned long *out_flags)
2220 {
2221         struct drm_device *dev = fb->dev;
2222         struct drm_i915_private *dev_priv = to_i915(dev);
2223         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2224         intel_wakeref_t wakeref;
2225         struct i915_vma *vma;
2226         unsigned int pinctl;
2227         u32 alignment;
2228
2229         if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2230                 return ERR_PTR(-EINVAL);
2231
2232         alignment = intel_surf_alignment(fb, 0);
2233         if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2234                 return ERR_PTR(-EINVAL);
2235
2236         /* Note that the w/a also requires 64 PTE of padding following the
2237          * bo. We currently fill all unused PTE with the shadow page and so
2238          * we should always have valid PTE following the scanout preventing
2239          * the VT-d warning.
2240          */
2241         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2242                 alignment = 256 * 1024;
2243
2244         /*
2245          * Global gtt pte registers are special registers which actually forward
2246          * writes to a chunk of system memory. Which means that there is no risk
2247          * that the register values disappear as soon as we call
2248          * intel_runtime_pm_put(), so it is correct to wrap only the
2249          * pin/unpin/fence and not more.
2250          */
2251         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2252
2253         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2254
2255         /*
2256          * Valleyview is definitely limited to scanning out the first
2257          * 512MiB. Lets presume this behaviour was inherited from the
2258          * g4x display engine and that all earlier gen are similarly
2259          * limited. Testing suggests that it is a little more
2260          * complicated than this. For example, Cherryview appears quite
2261          * happy to scanout from anywhere within its global aperture.
2262          */
2263         pinctl = 0;
2264         if (HAS_GMCH(dev_priv))
2265                 pinctl |= PIN_MAPPABLE;
2266
2267         vma = i915_gem_object_pin_to_display_plane(obj,
2268                                                    alignment, view, pinctl);
2269         if (IS_ERR(vma))
2270                 goto err;
2271
2272         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2273                 int ret;
2274
2275                 /*
2276                  * Install a fence for tiled scan-out. Pre-i965 always needs a
2277                  * fence, whereas 965+ only requires a fence if using
2278                  * framebuffer compression.  For simplicity, we always, when
2279                  * possible, install a fence as the cost is not that onerous.
2280                  *
2281                  * If we fail to fence the tiled scanout, then either the
2282                  * modeset will reject the change (which is highly unlikely as
2283                  * the affected systems, all but one, do not have unmappable
2284                  * space) or we will not be able to enable full powersaving
2285                  * techniques (also likely not to apply due to various limits
2286                  * FBC and the like impose on the size of the buffer, which
2287                  * presumably we violated anyway with this unmappable buffer).
2288                  * Anyway, it is presumably better to stumble onwards with
2289                  * something and try to run the system in a "less than optimal"
2290                  * mode that matches the user configuration.
2291                  */
2292                 ret = i915_vma_pin_fence(vma);
2293                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2294                         i915_gem_object_unpin_from_display_plane(vma);
2295                         vma = ERR_PTR(ret);
2296                         goto err;
2297                 }
2298
2299                 if (ret == 0 && vma->fence)
2300                         *out_flags |= PLANE_HAS_FENCE;
2301         }
2302
2303         i915_vma_get(vma);
2304 err:
2305         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2306         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2307         return vma;
2308 }
2309
2310 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2311 {
2312         i915_gem_object_lock(vma->obj);
2313         if (flags & PLANE_HAS_FENCE)
2314                 i915_vma_unpin_fence(vma);
2315         i915_gem_object_unpin_from_display_plane(vma);
2316         i915_gem_object_unlock(vma->obj);
2317
2318         i915_vma_put(vma);
2319 }
2320
2321 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2322                           unsigned int rotation)
2323 {
2324         if (drm_rotation_90_or_270(rotation))
2325                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2326         else
2327                 return fb->pitches[color_plane];
2328 }
2329
2330 /*
2331  * Convert the x/y offsets into a linear offset.
2332  * Only valid with 0/180 degree rotation, which is fine since linear
2333  * offset is only used with linear buffers on pre-hsw and tiled buffers
2334  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2335  */
2336 u32 intel_fb_xy_to_linear(int x, int y,
2337                           const struct intel_plane_state *state,
2338                           int color_plane)
2339 {
2340         const struct drm_framebuffer *fb = state->hw.fb;
2341         unsigned int cpp = fb->format->cpp[color_plane];
2342         unsigned int pitch = state->color_plane[color_plane].stride;
2343
2344         return y * pitch + x * cpp;
2345 }
2346
2347 /*
2348  * Add the x/y offsets derived from fb->offsets[] to the user
2349  * specified plane src x/y offsets. The resulting x/y offsets
2350  * specify the start of scanout from the beginning of the gtt mapping.
2351  */
2352 void intel_add_fb_offsets(int *x, int *y,
2353                           const struct intel_plane_state *state,
2354                           int color_plane)
2355
2356 {
2357         *x += state->color_plane[color_plane].x;
2358         *y += state->color_plane[color_plane].y;
2359 }
2360
2361 static u32 intel_adjust_tile_offset(int *x, int *y,
2362                                     unsigned int tile_width,
2363                                     unsigned int tile_height,
2364                                     unsigned int tile_size,
2365                                     unsigned int pitch_tiles,
2366                                     u32 old_offset,
2367                                     u32 new_offset)
2368 {
2369         unsigned int pitch_pixels = pitch_tiles * tile_width;
2370         unsigned int tiles;
2371
2372         WARN_ON(old_offset & (tile_size - 1));
2373         WARN_ON(new_offset & (tile_size - 1));
2374         WARN_ON(new_offset > old_offset);
2375
2376         tiles = (old_offset - new_offset) / tile_size;
2377
2378         *y += tiles / pitch_tiles * tile_height;
2379         *x += tiles % pitch_tiles * tile_width;
2380
2381         /* minimize x in case it got needlessly big */
2382         *y += *x / pitch_pixels * tile_height;
2383         *x %= pitch_pixels;
2384
2385         return new_offset;
2386 }
2387
2388 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2389 {
2390         return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2391                is_gen12_ccs_plane(fb, color_plane);
2392 }
2393
2394 static u32 intel_adjust_aligned_offset(int *x, int *y,
2395                                        const struct drm_framebuffer *fb,
2396                                        int color_plane,
2397                                        unsigned int rotation,
2398                                        unsigned int pitch,
2399                                        u32 old_offset, u32 new_offset)
2400 {
2401         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2402         unsigned int cpp = fb->format->cpp[color_plane];
2403
2404         drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2405
2406         if (!is_surface_linear(fb, color_plane)) {
2407                 unsigned int tile_size, tile_width, tile_height;
2408                 unsigned int pitch_tiles;
2409
2410                 tile_size = intel_tile_size(dev_priv);
2411                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2412
2413                 if (drm_rotation_90_or_270(rotation)) {
2414                         pitch_tiles = pitch / tile_height;
2415                         swap(tile_width, tile_height);
2416                 } else {
2417                         pitch_tiles = pitch / (tile_width * cpp);
2418                 }
2419
2420                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2421                                          tile_size, pitch_tiles,
2422                                          old_offset, new_offset);
2423         } else {
2424                 old_offset += *y * pitch + *x * cpp;
2425
2426                 *y = (old_offset - new_offset) / pitch;
2427                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2428         }
2429
2430         return new_offset;
2431 }
2432
2433 /*
2434  * Adjust the tile offset by moving the difference into
2435  * the x/y offsets.
2436  */
2437 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2438                                              const struct intel_plane_state *state,
2439                                              int color_plane,
2440                                              u32 old_offset, u32 new_offset)
2441 {
2442         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2443                                            state->hw.rotation,
2444                                            state->color_plane[color_plane].stride,
2445                                            old_offset, new_offset);
2446 }
2447
2448 /*
2449  * Computes the aligned offset to the base tile and adjusts
2450  * x, y. bytes per pixel is assumed to be a power-of-two.
2451  *
2452  * In the 90/270 rotated case, x and y are assumed
2453  * to be already rotated to match the rotated GTT view, and
2454  * pitch is the tile_height aligned framebuffer height.
2455  *
2456  * This function is used when computing the derived information
2457  * under intel_framebuffer, so using any of that information
2458  * here is not allowed. Anything under drm_framebuffer can be
2459  * used. This is why the user has to pass in the pitch since it
2460  * is specified in the rotated orientation.
2461  */
2462 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2463                                         int *x, int *y,
2464                                         const struct drm_framebuffer *fb,
2465                                         int color_plane,
2466                                         unsigned int pitch,
2467                                         unsigned int rotation,
2468                                         u32 alignment)
2469 {
2470         unsigned int cpp = fb->format->cpp[color_plane];
2471         u32 offset, offset_aligned;
2472
2473         if (!is_surface_linear(fb, color_plane)) {
2474                 unsigned int tile_size, tile_width, tile_height;
2475                 unsigned int tile_rows, tiles, pitch_tiles;
2476
2477                 tile_size = intel_tile_size(dev_priv);
2478                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2479
2480                 if (drm_rotation_90_or_270(rotation)) {
2481                         pitch_tiles = pitch / tile_height;
2482                         swap(tile_width, tile_height);
2483                 } else {
2484                         pitch_tiles = pitch / (tile_width * cpp);
2485                 }
2486
2487                 tile_rows = *y / tile_height;
2488                 *y %= tile_height;
2489
2490                 tiles = *x / tile_width;
2491                 *x %= tile_width;
2492
2493                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2494
2495                 offset_aligned = offset;
2496                 if (alignment)
2497                         offset_aligned = rounddown(offset_aligned, alignment);
2498
2499                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2500                                          tile_size, pitch_tiles,
2501                                          offset, offset_aligned);
2502         } else {
2503                 offset = *y * pitch + *x * cpp;
2504                 offset_aligned = offset;
2505                 if (alignment) {
2506                         offset_aligned = rounddown(offset_aligned, alignment);
2507                         *y = (offset % alignment) / pitch;
2508                         *x = ((offset % alignment) - *y * pitch) / cpp;
2509                 } else {
2510                         *y = *x = 0;
2511                 }
2512         }
2513
2514         return offset_aligned;
2515 }
2516
2517 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2518                                               const struct intel_plane_state *state,
2519                                               int color_plane)
2520 {
2521         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2522         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2523         const struct drm_framebuffer *fb = state->hw.fb;
2524         unsigned int rotation = state->hw.rotation;
2525         int pitch = state->color_plane[color_plane].stride;
2526         u32 alignment;
2527
2528         if (intel_plane->id == PLANE_CURSOR)
2529                 alignment = intel_cursor_alignment(dev_priv);
2530         else
2531                 alignment = intel_surf_alignment(fb, color_plane);
2532
2533         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2534                                             pitch, rotation, alignment);
2535 }
2536
2537 /* Convert the fb->offset[] into x/y offsets */
2538 static int intel_fb_offset_to_xy(int *x, int *y,
2539                                  const struct drm_framebuffer *fb,
2540                                  int color_plane)
2541 {
2542         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2543         unsigned int height;
2544         u32 alignment;
2545
2546         if (INTEL_GEN(dev_priv) >= 12 &&
2547             is_semiplanar_uv_plane(fb, color_plane))
2548                 alignment = intel_tile_row_size(fb, color_plane);
2549         else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2550                 alignment = intel_tile_size(dev_priv);
2551         else
2552                 alignment = 0;
2553
2554         if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2555                 drm_dbg_kms(&dev_priv->drm,
2556                             "Misaligned offset 0x%08x for color plane %d\n",
2557                             fb->offsets[color_plane], color_plane);
2558                 return -EINVAL;
2559         }
2560
2561         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2562         height = ALIGN(height, intel_tile_height(fb, color_plane));
2563
2564         /* Catch potential overflows early */
2565         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2566                             fb->offsets[color_plane])) {
2567                 drm_dbg_kms(&dev_priv->drm,
2568                             "Bad offset 0x%08x or pitch %d for color plane %d\n",
2569                             fb->offsets[color_plane], fb->pitches[color_plane],
2570                             color_plane);
2571                 return -ERANGE;
2572         }
2573
2574         *x = 0;
2575         *y = 0;
2576
2577         intel_adjust_aligned_offset(x, y,
2578                                     fb, color_plane, DRM_MODE_ROTATE_0,
2579                                     fb->pitches[color_plane],
2580                                     fb->offsets[color_plane], 0);
2581
2582         return 0;
2583 }
2584
2585 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2586 {
2587         switch (fb_modifier) {
2588         case I915_FORMAT_MOD_X_TILED:
2589                 return I915_TILING_X;
2590         case I915_FORMAT_MOD_Y_TILED:
2591         case I915_FORMAT_MOD_Y_TILED_CCS:
2592         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2593         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2594                 return I915_TILING_Y;
2595         default:
2596                 return I915_TILING_NONE;
2597         }
2598 }
2599
2600 /*
2601  * From the Sky Lake PRM:
2602  * "The Color Control Surface (CCS) contains the compression status of
2603  *  the cache-line pairs. The compression state of the cache-line pair
2604  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2605  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2606  *  cache-line-pairs. CCS is always Y tiled."
2607  *
2608  * Since cache line pairs refers to horizontally adjacent cache lines,
2609  * each cache line in the CCS corresponds to an area of 32x16 cache
2610  * lines on the main surface. Since each pixel is 4 bytes, this gives
2611  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2612  * main surface.
2613  */
2614 static const struct drm_format_info skl_ccs_formats[] = {
2615         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2616           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2617         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2618           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2619         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2620           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2621         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2622           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2623 };
2624
2625 /*
2626  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2627  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2628  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2629  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2630  * the main surface.
2631  */
2632 static const struct drm_format_info gen12_ccs_formats[] = {
2633         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2634           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2635           .hsub = 1, .vsub = 1, },
2636         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2637           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2638           .hsub = 1, .vsub = 1, },
2639         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2640           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2641           .hsub = 1, .vsub = 1, .has_alpha = true },
2642         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2643           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2644           .hsub = 1, .vsub = 1, .has_alpha = true },
2645         { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2646           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2647           .hsub = 2, .vsub = 1, .is_yuv = true },
2648         { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2649           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2650           .hsub = 2, .vsub = 1, .is_yuv = true },
2651         { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2652           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653           .hsub = 2, .vsub = 1, .is_yuv = true },
2654         { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2655           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656           .hsub = 2, .vsub = 1, .is_yuv = true },
2657         { .format = DRM_FORMAT_NV12, .num_planes = 4,
2658           .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2659           .hsub = 2, .vsub = 2, .is_yuv = true },
2660         { .format = DRM_FORMAT_P010, .num_planes = 4,
2661           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2662           .hsub = 2, .vsub = 2, .is_yuv = true },
2663         { .format = DRM_FORMAT_P012, .num_planes = 4,
2664           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2665           .hsub = 2, .vsub = 2, .is_yuv = true },
2666         { .format = DRM_FORMAT_P016, .num_planes = 4,
2667           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2668           .hsub = 2, .vsub = 2, .is_yuv = true },
2669 };
2670
2671 static const struct drm_format_info *
2672 lookup_format_info(const struct drm_format_info formats[],
2673                    int num_formats, u32 format)
2674 {
2675         int i;
2676
2677         for (i = 0; i < num_formats; i++) {
2678                 if (formats[i].format == format)
2679                         return &formats[i];
2680         }
2681
2682         return NULL;
2683 }
2684
2685 static const struct drm_format_info *
2686 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2687 {
2688         switch (cmd->modifier[0]) {
2689         case I915_FORMAT_MOD_Y_TILED_CCS:
2690         case I915_FORMAT_MOD_Yf_TILED_CCS:
2691                 return lookup_format_info(skl_ccs_formats,
2692                                           ARRAY_SIZE(skl_ccs_formats),
2693                                           cmd->pixel_format);
2694         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2695         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2696                 return lookup_format_info(gen12_ccs_formats,
2697                                           ARRAY_SIZE(gen12_ccs_formats),
2698                                           cmd->pixel_format);
2699         default:
2700                 return NULL;
2701         }
2702 }
2703
2704 bool is_ccs_modifier(u64 modifier)
2705 {
2706         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2707                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2708                modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2709                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2710 }
2711
2712 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2713 {
2714         return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2715                             512) * 64;
2716 }
2717
2718 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2719                               u32 pixel_format, u64 modifier)
2720 {
2721         struct intel_crtc *crtc;
2722         struct intel_plane *plane;
2723
2724         /*
2725          * We assume the primary plane for pipe A has
2726          * the highest stride limits of them all,
2727          * if in case pipe A is disabled, use the first pipe from pipe_mask.
2728          */
2729         crtc = intel_get_first_crtc(dev_priv);
2730         if (!crtc)
2731                 return 0;
2732
2733         plane = to_intel_plane(crtc->base.primary);
2734
2735         return plane->max_stride(plane, pixel_format, modifier,
2736                                  DRM_MODE_ROTATE_0);
2737 }
2738
2739 static
2740 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2741                         u32 pixel_format, u64 modifier)
2742 {
2743         /*
2744          * Arbitrary limit for gen4+ chosen to match the
2745          * render engine max stride.
2746          *
2747          * The new CCS hash mode makes remapping impossible
2748          */
2749         if (!is_ccs_modifier(modifier)) {
2750                 if (INTEL_GEN(dev_priv) >= 7)
2751                         return 256*1024;
2752                 else if (INTEL_GEN(dev_priv) >= 4)
2753                         return 128*1024;
2754         }
2755
2756         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2757 }
2758
2759 static u32
2760 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2761 {
2762         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2763         u32 tile_width;
2764
2765         if (is_surface_linear(fb, color_plane)) {
2766                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2767                                                            fb->format->format,
2768                                                            fb->modifier);
2769
2770                 /*
2771                  * To make remapping with linear generally feasible
2772                  * we need the stride to be page aligned.
2773                  */
2774                 if (fb->pitches[color_plane] > max_stride &&
2775                     !is_ccs_modifier(fb->modifier))
2776                         return intel_tile_size(dev_priv);
2777                 else
2778                         return 64;
2779         }
2780
2781         tile_width = intel_tile_width_bytes(fb, color_plane);
2782         if (is_ccs_modifier(fb->modifier)) {
2783                 /*
2784                  * Display WA #0531: skl,bxt,kbl,glk
2785                  *
2786                  * Render decompression and plane width > 3840
2787                  * combined with horizontal panning requires the
2788                  * plane stride to be a multiple of 4. We'll just
2789                  * require the entire fb to accommodate that to avoid
2790                  * potential runtime errors at plane configuration time.
2791                  */
2792                 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2793                         tile_width *= 4;
2794                 /*
2795                  * The main surface pitch must be padded to a multiple of four
2796                  * tile widths.
2797                  */
2798                 else if (INTEL_GEN(dev_priv) >= 12)
2799                         tile_width *= 4;
2800         }
2801         return tile_width;
2802 }
2803
2804 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2805 {
2806         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2807         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2808         const struct drm_framebuffer *fb = plane_state->hw.fb;
2809         int i;
2810
2811         /* We don't want to deal with remapping with cursors */
2812         if (plane->id == PLANE_CURSOR)
2813                 return false;
2814
2815         /*
2816          * The display engine limits already match/exceed the
2817          * render engine limits, so not much point in remapping.
2818          * Would also need to deal with the fence POT alignment
2819          * and gen2 2KiB GTT tile size.
2820          */
2821         if (INTEL_GEN(dev_priv) < 4)
2822                 return false;
2823
2824         /*
2825          * The new CCS hash mode isn't compatible with remapping as
2826          * the virtual address of the pages affects the compressed data.
2827          */
2828         if (is_ccs_modifier(fb->modifier))
2829                 return false;
2830
2831         /* Linear needs a page aligned stride for remapping */
2832         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2833                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2834
2835                 for (i = 0; i < fb->format->num_planes; i++) {
2836                         if (fb->pitches[i] & alignment)
2837                                 return false;
2838                 }
2839         }
2840
2841         return true;
2842 }
2843
2844 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2845 {
2846         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2847         const struct drm_framebuffer *fb = plane_state->hw.fb;
2848         unsigned int rotation = plane_state->hw.rotation;
2849         u32 stride, max_stride;
2850
2851         /*
2852          * No remapping for invisible planes since we don't have
2853          * an actual source viewport to remap.
2854          */
2855         if (!plane_state->uapi.visible)
2856                 return false;
2857
2858         if (!intel_plane_can_remap(plane_state))
2859                 return false;
2860
2861         /*
2862          * FIXME: aux plane limits on gen9+ are
2863          * unclear in Bspec, for now no checking.
2864          */
2865         stride = intel_fb_pitch(fb, 0, rotation);
2866         max_stride = plane->max_stride(plane, fb->format->format,
2867                                        fb->modifier, rotation);
2868
2869         return stride > max_stride;
2870 }
2871
2872 static void
2873 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2874                                const struct drm_framebuffer *fb,
2875                                int color_plane)
2876 {
2877         int main_plane;
2878
2879         if (color_plane == 0) {
2880                 *hsub = 1;
2881                 *vsub = 1;
2882
2883                 return;
2884         }
2885
2886         /*
2887          * TODO: Deduct the subsampling from the char block for all CCS
2888          * formats and planes.
2889          */
2890         if (!is_gen12_ccs_plane(fb, color_plane)) {
2891                 *hsub = fb->format->hsub;
2892                 *vsub = fb->format->vsub;
2893
2894                 return;
2895         }
2896
2897         main_plane = ccs_to_main_plane(fb, color_plane);
2898         *hsub = drm_format_info_block_width(fb->format, color_plane) /
2899                 drm_format_info_block_width(fb->format, main_plane);
2900
2901         /*
2902          * The min stride check in the core framebuffer_check() function
2903          * assumes that format->hsub applies to every plane except for the
2904          * first plane. That's incorrect for the CCS AUX plane of the first
2905          * plane, but for the above check to pass we must define the block
2906          * width with that subsampling applied to it. Adjust the width here
2907          * accordingly, so we can calculate the actual subsampling factor.
2908          */
2909         if (main_plane == 0)
2910                 *hsub *= fb->format->hsub;
2911
2912         *vsub = 32;
2913 }
2914 static int
2915 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2916 {
2917         struct drm_i915_private *i915 = to_i915(fb->dev);
2918         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2919         int main_plane;
2920         int hsub, vsub;
2921         int tile_width, tile_height;
2922         int ccs_x, ccs_y;
2923         int main_x, main_y;
2924
2925         if (!is_ccs_plane(fb, ccs_plane))
2926                 return 0;
2927
2928         intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2929         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2930
2931         tile_width *= hsub;
2932         tile_height *= vsub;
2933
2934         ccs_x = (x * hsub) % tile_width;
2935         ccs_y = (y * vsub) % tile_height;
2936
2937         main_plane = ccs_to_main_plane(fb, ccs_plane);
2938         main_x = intel_fb->normal[main_plane].x % tile_width;
2939         main_y = intel_fb->normal[main_plane].y % tile_height;
2940
2941         /*
2942          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2943          * x/y offsets must match between CCS and the main surface.
2944          */
2945         if (main_x != ccs_x || main_y != ccs_y) {
2946                 drm_dbg_kms(&i915->drm,
2947                               "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2948                               main_x, main_y,
2949                               ccs_x, ccs_y,
2950                               intel_fb->normal[main_plane].x,
2951                               intel_fb->normal[main_plane].y,
2952                               x, y);
2953                 return -EINVAL;
2954         }
2955
2956         return 0;
2957 }
2958
2959 static void
2960 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2961 {
2962         int main_plane = is_ccs_plane(fb, color_plane) ?
2963                          ccs_to_main_plane(fb, color_plane) : 0;
2964         int main_hsub, main_vsub;
2965         int hsub, vsub;
2966
2967         intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2968         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2969         *w = fb->width / main_hsub / hsub;
2970         *h = fb->height / main_vsub / vsub;
2971 }
2972
2973 /*
2974  * Setup the rotated view for an FB plane and return the size the GTT mapping
2975  * requires for this view.
2976  */
2977 static u32
2978 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2979                   u32 gtt_offset_rotated, int x, int y,
2980                   unsigned int width, unsigned int height,
2981                   unsigned int tile_size,
2982                   unsigned int tile_width, unsigned int tile_height,
2983                   struct drm_framebuffer *fb)
2984 {
2985         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2986         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2987         unsigned int pitch_tiles;
2988         struct drm_rect r;
2989
2990         /* Y or Yf modifiers required for 90/270 rotation */
2991         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2992             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
2993                 return 0;
2994
2995         if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
2996                 return 0;
2997
2998         rot_info->plane[plane] = *plane_info;
2999
3000         intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3001
3002         /* rotate the x/y offsets to match the GTT view */
3003         drm_rect_init(&r, x, y, width, height);
3004         drm_rect_rotate(&r,
3005                         plane_info->width * tile_width,
3006                         plane_info->height * tile_height,
3007                         DRM_MODE_ROTATE_270);
3008         x = r.x1;
3009         y = r.y1;
3010
3011         /* rotate the tile dimensions to match the GTT view */
3012         pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3013         swap(tile_width, tile_height);
3014
3015         /*
3016          * We only keep the x/y offsets, so push all of the
3017          * gtt offset into the x/y offsets.
3018          */
3019         intel_adjust_tile_offset(&x, &y,
3020                                  tile_width, tile_height,
3021                                  tile_size, pitch_tiles,
3022                                  gtt_offset_rotated * tile_size, 0);
3023
3024         /*
3025          * First pixel of the framebuffer from
3026          * the start of the rotated gtt mapping.
3027          */
3028         intel_fb->rotated[plane].x = x;
3029         intel_fb->rotated[plane].y = y;
3030
3031         return plane_info->width * plane_info->height;
3032 }
3033
3034 static int
3035 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3036                    struct drm_framebuffer *fb)
3037 {
3038         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3039         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3040         u32 gtt_offset_rotated = 0;
3041         unsigned int max_size = 0;
3042         int i, num_planes = fb->format->num_planes;
3043         unsigned int tile_size = intel_tile_size(dev_priv);
3044
3045         for (i = 0; i < num_planes; i++) {
3046                 unsigned int width, height;
3047                 unsigned int cpp, size;
3048                 u32 offset;
3049                 int x, y;
3050                 int ret;
3051
3052                 cpp = fb->format->cpp[i];
3053                 intel_fb_plane_dims(&width, &height, fb, i);
3054
3055                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3056                 if (ret) {
3057                         drm_dbg_kms(&dev_priv->drm,
3058                                     "bad fb plane %d offset: 0x%x\n",
3059                                     i, fb->offsets[i]);
3060                         return ret;
3061                 }
3062
3063                 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3064                 if (ret)
3065                         return ret;
3066
3067                 /*
3068                  * The fence (if used) is aligned to the start of the object
3069                  * so having the framebuffer wrap around across the edge of the
3070                  * fenced region doesn't really work. We have no API to configure
3071                  * the fence start offset within the object (nor could we probably
3072                  * on gen2/3). So it's just easier if we just require that the
3073                  * fb layout agrees with the fence layout. We already check that the
3074                  * fb stride matches the fence stride elsewhere.
3075                  */
3076                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3077                     (x + width) * cpp > fb->pitches[i]) {
3078                         drm_dbg_kms(&dev_priv->drm,
3079                                     "bad fb plane %d offset: 0x%x\n",
3080                                      i, fb->offsets[i]);
3081                         return -EINVAL;
3082                 }
3083
3084                 /*
3085                  * First pixel of the framebuffer from
3086                  * the start of the normal gtt mapping.
3087                  */
3088                 intel_fb->normal[i].x = x;
3089                 intel_fb->normal[i].y = y;
3090
3091                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3092                                                       fb->pitches[i],
3093                                                       DRM_MODE_ROTATE_0,
3094                                                       tile_size);
3095                 offset /= tile_size;
3096
3097                 if (!is_surface_linear(fb, i)) {
3098                         struct intel_remapped_plane_info plane_info;
3099                         unsigned int tile_width, tile_height;
3100
3101                         intel_tile_dims(fb, i, &tile_width, &tile_height);
3102
3103                         plane_info.offset = offset;
3104                         plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3105                                                          tile_width * cpp);
3106                         plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3107                         plane_info.height = DIV_ROUND_UP(y + height,
3108                                                          tile_height);
3109
3110                         /* how many tiles does this plane need */
3111                         size = plane_info.stride * plane_info.height;
3112                         /*
3113                          * If the plane isn't horizontally tile aligned,
3114                          * we need one more tile.
3115                          */
3116                         if (x != 0)
3117                                 size++;
3118
3119                         gtt_offset_rotated +=
3120                                 setup_fb_rotation(i, &plane_info,
3121                                                   gtt_offset_rotated,
3122                                                   x, y, width, height,
3123                                                   tile_size,
3124                                                   tile_width, tile_height,
3125                                                   fb);
3126                 } else {
3127                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3128                                             x * cpp, tile_size);
3129                 }
3130
3131                 /* how many tiles in total needed in the bo */
3132                 max_size = max(max_size, offset + size);
3133         }
3134
3135         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3136                 drm_dbg_kms(&dev_priv->drm,
3137                             "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3138                             mul_u32_u32(max_size, tile_size), obj->base.size);
3139                 return -EINVAL;
3140         }
3141
3142         return 0;
3143 }
3144
3145 static void
3146 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3147 {
3148         struct drm_i915_private *dev_priv =
3149                 to_i915(plane_state->uapi.plane->dev);
3150         struct drm_framebuffer *fb = plane_state->hw.fb;
3151         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3152         struct intel_rotation_info *info = &plane_state->view.rotated;
3153         unsigned int rotation = plane_state->hw.rotation;
3154         int i, num_planes = fb->format->num_planes;
3155         unsigned int tile_size = intel_tile_size(dev_priv);
3156         unsigned int src_x, src_y;
3157         unsigned int src_w, src_h;
3158         u32 gtt_offset = 0;
3159
3160         memset(&plane_state->view, 0, sizeof(plane_state->view));
3161         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3162                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3163
3164         src_x = plane_state->uapi.src.x1 >> 16;
3165         src_y = plane_state->uapi.src.y1 >> 16;
3166         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3167         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3168
3169         drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3170
3171         /* Make src coordinates relative to the viewport */
3172         drm_rect_translate(&plane_state->uapi.src,
3173                            -(src_x << 16), -(src_y << 16));
3174
3175         /* Rotate src coordinates to match rotated GTT view */
3176         if (drm_rotation_90_or_270(rotation))
3177                 drm_rect_rotate(&plane_state->uapi.src,
3178                                 src_w << 16, src_h << 16,
3179                                 DRM_MODE_ROTATE_270);
3180
3181         for (i = 0; i < num_planes; i++) {
3182                 unsigned int hsub = i ? fb->format->hsub : 1;
3183                 unsigned int vsub = i ? fb->format->vsub : 1;
3184                 unsigned int cpp = fb->format->cpp[i];
3185                 unsigned int tile_width, tile_height;
3186                 unsigned int width, height;
3187                 unsigned int pitch_tiles;
3188                 unsigned int x, y;
3189                 u32 offset;
3190
3191                 intel_tile_dims(fb, i, &tile_width, &tile_height);
3192
3193                 x = src_x / hsub;
3194                 y = src_y / vsub;
3195                 width = src_w / hsub;
3196                 height = src_h / vsub;
3197
3198                 /*
3199                  * First pixel of the src viewport from the
3200                  * start of the normal gtt mapping.
3201                  */
3202                 x += intel_fb->normal[i].x;
3203                 y += intel_fb->normal[i].y;
3204
3205                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3206                                                       fb, i, fb->pitches[i],
3207                                                       DRM_MODE_ROTATE_0, tile_size);
3208                 offset /= tile_size;
3209
3210                 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3211                 info->plane[i].offset = offset;
3212                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3213                                                      tile_width * cpp);
3214                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3215                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3216
3217                 if (drm_rotation_90_or_270(rotation)) {
3218                         struct drm_rect r;
3219
3220                         /* rotate the x/y offsets to match the GTT view */
3221                         drm_rect_init(&r, x, y, width, height);
3222                         drm_rect_rotate(&r,
3223                                         info->plane[i].width * tile_width,
3224                                         info->plane[i].height * tile_height,
3225                                         DRM_MODE_ROTATE_270);
3226                         x = r.x1;
3227                         y = r.y1;
3228
3229                         pitch_tiles = info->plane[i].height;
3230                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3231
3232                         /* rotate the tile dimensions to match the GTT view */
3233                         swap(tile_width, tile_height);
3234                 } else {
3235                         pitch_tiles = info->plane[i].width;
3236                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3237                 }
3238
3239                 /*
3240                  * We only keep the x/y offsets, so push all of the
3241                  * gtt offset into the x/y offsets.
3242                  */
3243                 intel_adjust_tile_offset(&x, &y,
3244                                          tile_width, tile_height,
3245                                          tile_size, pitch_tiles,
3246                                          gtt_offset * tile_size, 0);
3247
3248                 gtt_offset += info->plane[i].width * info->plane[i].height;
3249
3250                 plane_state->color_plane[i].offset = 0;
3251                 plane_state->color_plane[i].x = x;
3252                 plane_state->color_plane[i].y = y;
3253         }
3254 }
3255
3256 static int
3257 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3258 {
3259         const struct intel_framebuffer *fb =
3260                 to_intel_framebuffer(plane_state->hw.fb);
3261         unsigned int rotation = plane_state->hw.rotation;
3262         int i, num_planes;
3263
3264         if (!fb)
3265                 return 0;
3266
3267         num_planes = fb->base.format->num_planes;
3268
3269         if (intel_plane_needs_remap(plane_state)) {
3270                 intel_plane_remap_gtt(plane_state);
3271
3272                 /*
3273                  * Sometimes even remapping can't overcome
3274                  * the stride limitations :( Can happen with
3275                  * big plane sizes and suitably misaligned
3276                  * offsets.
3277                  */
3278                 return intel_plane_check_stride(plane_state);
3279         }
3280
3281         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3282
3283         for (i = 0; i < num_planes; i++) {
3284                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3285                 plane_state->color_plane[i].offset = 0;
3286
3287                 if (drm_rotation_90_or_270(rotation)) {
3288                         plane_state->color_plane[i].x = fb->rotated[i].x;
3289                         plane_state->color_plane[i].y = fb->rotated[i].y;
3290                 } else {
3291                         plane_state->color_plane[i].x = fb->normal[i].x;
3292                         plane_state->color_plane[i].y = fb->normal[i].y;
3293                 }
3294         }
3295
3296         /* Rotate src coordinates to match rotated GTT view */
3297         if (drm_rotation_90_or_270(rotation))
3298                 drm_rect_rotate(&plane_state->uapi.src,
3299                                 fb->base.width << 16, fb->base.height << 16,
3300                                 DRM_MODE_ROTATE_270);
3301
3302         return intel_plane_check_stride(plane_state);
3303 }
3304
3305 static int i9xx_format_to_fourcc(int format)
3306 {
3307         switch (format) {
3308         case DISPPLANE_8BPP:
3309                 return DRM_FORMAT_C8;
3310         case DISPPLANE_BGRA555:
3311                 return DRM_FORMAT_ARGB1555;
3312         case DISPPLANE_BGRX555:
3313                 return DRM_FORMAT_XRGB1555;
3314         case DISPPLANE_BGRX565:
3315                 return DRM_FORMAT_RGB565;
3316         default:
3317         case DISPPLANE_BGRX888:
3318                 return DRM_FORMAT_XRGB8888;
3319         case DISPPLANE_RGBX888:
3320                 return DRM_FORMAT_XBGR8888;
3321         case DISPPLANE_BGRA888:
3322                 return DRM_FORMAT_ARGB8888;
3323         case DISPPLANE_RGBA888:
3324                 return DRM_FORMAT_ABGR8888;
3325         case DISPPLANE_BGRX101010:
3326                 return DRM_FORMAT_XRGB2101010;
3327         case DISPPLANE_RGBX101010:
3328                 return DRM_FORMAT_XBGR2101010;
3329         case DISPPLANE_BGRA101010:
3330                 return DRM_FORMAT_ARGB2101010;
3331         case DISPPLANE_RGBA101010:
3332                 return DRM_FORMAT_ABGR2101010;
3333         case DISPPLANE_RGBX161616:
3334                 return DRM_FORMAT_XBGR16161616F;
3335         }
3336 }
3337
3338 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3339 {
3340         switch (format) {
3341         case PLANE_CTL_FORMAT_RGB_565:
3342                 return DRM_FORMAT_RGB565;
3343         case PLANE_CTL_FORMAT_NV12:
3344                 return DRM_FORMAT_NV12;
3345         case PLANE_CTL_FORMAT_XYUV:
3346                 return DRM_FORMAT_XYUV8888;
3347         case PLANE_CTL_FORMAT_P010:
3348                 return DRM_FORMAT_P010;
3349         case PLANE_CTL_FORMAT_P012:
3350                 return DRM_FORMAT_P012;
3351         case PLANE_CTL_FORMAT_P016:
3352                 return DRM_FORMAT_P016;
3353         case PLANE_CTL_FORMAT_Y210:
3354                 return DRM_FORMAT_Y210;
3355         case PLANE_CTL_FORMAT_Y212:
3356                 return DRM_FORMAT_Y212;
3357         case PLANE_CTL_FORMAT_Y216:
3358                 return DRM_FORMAT_Y216;
3359         case PLANE_CTL_FORMAT_Y410:
3360                 return DRM_FORMAT_XVYU2101010;
3361         case PLANE_CTL_FORMAT_Y412:
3362                 return DRM_FORMAT_XVYU12_16161616;
3363         case PLANE_CTL_FORMAT_Y416:
3364                 return DRM_FORMAT_XVYU16161616;
3365         default:
3366         case PLANE_CTL_FORMAT_XRGB_8888:
3367                 if (rgb_order) {
3368                         if (alpha)
3369                                 return DRM_FORMAT_ABGR8888;
3370                         else
3371                                 return DRM_FORMAT_XBGR8888;
3372                 } else {
3373                         if (alpha)
3374                                 return DRM_FORMAT_ARGB8888;
3375                         else
3376                                 return DRM_FORMAT_XRGB8888;
3377                 }
3378         case PLANE_CTL_FORMAT_XRGB_2101010:
3379                 if (rgb_order) {
3380                         if (alpha)
3381                                 return DRM_FORMAT_ABGR2101010;
3382                         else
3383                                 return DRM_FORMAT_XBGR2101010;
3384                 } else {
3385                         if (alpha)
3386                                 return DRM_FORMAT_ARGB2101010;
3387                         else
3388                                 return DRM_FORMAT_XRGB2101010;
3389                 }
3390         case PLANE_CTL_FORMAT_XRGB_16161616F:
3391                 if (rgb_order) {
3392                         if (alpha)
3393                                 return DRM_FORMAT_ABGR16161616F;
3394                         else
3395                                 return DRM_FORMAT_XBGR16161616F;
3396                 } else {
3397                         if (alpha)
3398                                 return DRM_FORMAT_ARGB16161616F;
3399                         else
3400                                 return DRM_FORMAT_XRGB16161616F;
3401                 }
3402         }
3403 }
3404
3405 static struct i915_vma *
3406 initial_plane_vma(struct drm_i915_private *i915,
3407                   struct intel_initial_plane_config *plane_config)
3408 {
3409         struct drm_i915_gem_object *obj;
3410         struct i915_vma *vma;
3411         u32 base, size;
3412
3413         if (plane_config->size == 0)
3414                 return NULL;
3415
3416         base = round_down(plane_config->base,
3417                           I915_GTT_MIN_ALIGNMENT);
3418         size = round_up(plane_config->base + plane_config->size,
3419                         I915_GTT_MIN_ALIGNMENT);
3420         size -= base;
3421
3422         /*
3423          * If the FB is too big, just don't use it since fbdev is not very
3424          * important and we should probably use that space with FBC or other
3425          * features.
3426          */
3427         if (size * 2 > i915->stolen_usable_size)
3428                 return NULL;
3429
3430         obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3431         if (IS_ERR(obj))
3432                 return NULL;
3433
3434         switch (plane_config->tiling) {
3435         case I915_TILING_NONE:
3436                 break;
3437         case I915_TILING_X:
3438         case I915_TILING_Y:
3439                 obj->tiling_and_stride =
3440                         plane_config->fb->base.pitches[0] |
3441                         plane_config->tiling;
3442                 break;
3443         default:
3444                 MISSING_CASE(plane_config->tiling);
3445                 goto err_obj;
3446         }
3447
3448         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3449         if (IS_ERR(vma))
3450                 goto err_obj;
3451
3452         if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3453                 goto err_obj;
3454
3455         if (i915_gem_object_is_tiled(obj) &&
3456             !i915_vma_is_map_and_fenceable(vma))
3457                 goto err_obj;
3458
3459         return vma;
3460
3461 err_obj:
3462         i915_gem_object_put(obj);
3463         return NULL;
3464 }
3465
3466 static bool
3467 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3468                               struct intel_initial_plane_config *plane_config)
3469 {
3470         struct drm_device *dev = crtc->base.dev;
3471         struct drm_i915_private *dev_priv = to_i915(dev);
3472         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3473         struct drm_framebuffer *fb = &plane_config->fb->base;
3474         struct i915_vma *vma;
3475
3476         switch (fb->modifier) {
3477         case DRM_FORMAT_MOD_LINEAR:
3478         case I915_FORMAT_MOD_X_TILED:
3479         case I915_FORMAT_MOD_Y_TILED:
3480                 break;
3481         default:
3482                 drm_dbg(&dev_priv->drm,
3483                         "Unsupported modifier for initial FB: 0x%llx\n",
3484                         fb->modifier);
3485                 return false;
3486         }
3487
3488         vma = initial_plane_vma(dev_priv, plane_config);
3489         if (!vma)
3490                 return false;
3491
3492         mode_cmd.pixel_format = fb->format->format;
3493         mode_cmd.width = fb->width;
3494         mode_cmd.height = fb->height;
3495         mode_cmd.pitches[0] = fb->pitches[0];
3496         mode_cmd.modifier[0] = fb->modifier;
3497         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3498
3499         if (intel_framebuffer_init(to_intel_framebuffer(fb),
3500                                    vma->obj, &mode_cmd)) {
3501                 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3502                 goto err_vma;
3503         }
3504
3505         plane_config->vma = vma;
3506         return true;
3507
3508 err_vma:
3509         i915_vma_put(vma);
3510         return false;
3511 }
3512
3513 static void
3514 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3515                         struct intel_plane_state *plane_state,
3516                         bool visible)
3517 {
3518         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3519
3520         plane_state->uapi.visible = visible;
3521
3522         if (visible)
3523                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3524         else
3525                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3526 }
3527
3528 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3529 {
3530         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3531         struct drm_plane *plane;
3532
3533         /*
3534          * Active_planes aliases if multiple "primary" or cursor planes
3535          * have been used on the same (or wrong) pipe. plane_mask uses
3536          * unique ids, hence we can use that to reconstruct active_planes.
3537          */
3538         crtc_state->active_planes = 0;
3539
3540         drm_for_each_plane_mask(plane, &dev_priv->drm,
3541                                 crtc_state->uapi.plane_mask)
3542                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3543 }
3544
3545 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3546                                          struct intel_plane *plane)
3547 {
3548         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3549         struct intel_crtc_state *crtc_state =
3550                 to_intel_crtc_state(crtc->base.state);
3551         struct intel_plane_state *plane_state =
3552                 to_intel_plane_state(plane->base.state);
3553
3554         drm_dbg_kms(&dev_priv->drm,
3555                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3556                     plane->base.base.id, plane->base.name,
3557                     crtc->base.base.id, crtc->base.name);
3558
3559         intel_set_plane_visible(crtc_state, plane_state, false);
3560         fixup_active_planes(crtc_state);
3561         crtc_state->data_rate[plane->id] = 0;
3562         crtc_state->min_cdclk[plane->id] = 0;
3563
3564         if (plane->id == PLANE_PRIMARY)
3565                 hsw_disable_ips(crtc_state);
3566
3567         /*
3568          * Vblank time updates from the shadow to live plane control register
3569          * are blocked if the memory self-refresh mode is active at that
3570          * moment. So to make sure the plane gets truly disabled, disable
3571          * first the self-refresh mode. The self-refresh enable bit in turn
3572          * will be checked/applied by the HW only at the next frame start
3573          * event which is after the vblank start event, so we need to have a
3574          * wait-for-vblank between disabling the plane and the pipe.
3575          */
3576         if (HAS_GMCH(dev_priv) &&
3577             intel_set_memory_cxsr(dev_priv, false))
3578                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3579
3580         /*
3581          * Gen2 reports pipe underruns whenever all planes are disabled.
3582          * So disable underrun reporting before all the planes get disabled.
3583          */
3584         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3585                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3586
3587         intel_disable_plane(plane, crtc_state);
3588 }
3589
3590 static struct intel_frontbuffer *
3591 to_intel_frontbuffer(struct drm_framebuffer *fb)
3592 {
3593         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3594 }
3595
3596 static void
3597 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3598                              struct intel_initial_plane_config *plane_config)
3599 {
3600         struct drm_device *dev = intel_crtc->base.dev;
3601         struct drm_i915_private *dev_priv = to_i915(dev);
3602         struct drm_crtc *c;
3603         struct drm_plane *primary = intel_crtc->base.primary;
3604         struct drm_plane_state *plane_state = primary->state;
3605         struct intel_plane *intel_plane = to_intel_plane(primary);
3606         struct intel_plane_state *intel_state =
3607                 to_intel_plane_state(plane_state);
3608         struct drm_framebuffer *fb;
3609         struct i915_vma *vma;
3610
3611         if (!plane_config->fb)
3612                 return;
3613
3614         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3615                 fb = &plane_config->fb->base;
3616                 vma = plane_config->vma;
3617                 goto valid_fb;
3618         }
3619
3620         /*
3621          * Failed to alloc the obj, check to see if we should share
3622          * an fb with another CRTC instead
3623          */
3624         for_each_crtc(dev, c) {
3625                 struct intel_plane_state *state;
3626
3627                 if (c == &intel_crtc->base)
3628                         continue;
3629
3630                 if (!to_intel_crtc(c)->active)
3631                         continue;
3632
3633                 state = to_intel_plane_state(c->primary->state);
3634                 if (!state->vma)
3635                         continue;
3636
3637                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3638                         fb = state->hw.fb;
3639                         vma = state->vma;
3640                         goto valid_fb;
3641                 }
3642         }
3643
3644         /*
3645          * We've failed to reconstruct the BIOS FB.  Current display state
3646          * indicates that the primary plane is visible, but has a NULL FB,
3647          * which will lead to problems later if we don't fix it up.  The
3648          * simplest solution is to just disable the primary plane now and
3649          * pretend the BIOS never had it enabled.
3650          */
3651         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3652
3653         return;
3654
3655 valid_fb:
3656         intel_state->hw.rotation = plane_config->rotation;
3657         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3658                                 intel_state->hw.rotation);
3659         intel_state->color_plane[0].stride =
3660                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3661
3662         __i915_vma_pin(vma);
3663         intel_state->vma = i915_vma_get(vma);
3664         if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3665                 if (vma->fence)
3666                         intel_state->flags |= PLANE_HAS_FENCE;
3667
3668         plane_state->src_x = 0;
3669         plane_state->src_y = 0;
3670         plane_state->src_w = fb->width << 16;
3671         plane_state->src_h = fb->height << 16;
3672
3673         plane_state->crtc_x = 0;
3674         plane_state->crtc_y = 0;
3675         plane_state->crtc_w = fb->width;
3676         plane_state->crtc_h = fb->height;
3677
3678         intel_state->uapi.src = drm_plane_state_src(plane_state);
3679         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3680
3681         if (plane_config->tiling)
3682                 dev_priv->preserve_bios_swizzle = true;
3683
3684         plane_state->fb = fb;
3685         drm_framebuffer_get(fb);
3686
3687         plane_state->crtc = &intel_crtc->base;
3688         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3689
3690         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3691
3692         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3693                   &to_intel_frontbuffer(fb)->bits);
3694 }
3695
3696 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3697                                int color_plane,
3698                                unsigned int rotation)
3699 {
3700         int cpp = fb->format->cpp[color_plane];
3701
3702         switch (fb->modifier) {
3703         case DRM_FORMAT_MOD_LINEAR:
3704         case I915_FORMAT_MOD_X_TILED:
3705                 /*
3706                  * Validated limit is 4k, but has 5k should
3707                  * work apart from the following features:
3708                  * - Ytile (already limited to 4k)
3709                  * - FP16 (already limited to 4k)
3710                  * - render compression (already limited to 4k)
3711                  * - KVMR sprite and cursor (don't care)
3712                  * - horizontal panning (TODO verify this)
3713                  * - pipe and plane scaling (TODO verify this)
3714                  */
3715                 if (cpp == 8)
3716                         return 4096;
3717                 else
3718                         return 5120;
3719         case I915_FORMAT_MOD_Y_TILED_CCS:
3720         case I915_FORMAT_MOD_Yf_TILED_CCS:
3721         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3722                 /* FIXME AUX plane? */
3723         case I915_FORMAT_MOD_Y_TILED:
3724         case I915_FORMAT_MOD_Yf_TILED:
3725                 if (cpp == 8)
3726                         return 2048;
3727                 else
3728                         return 4096;
3729         default:
3730                 MISSING_CASE(fb->modifier);
3731                 return 2048;
3732         }
3733 }
3734
3735 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3736                                int color_plane,
3737                                unsigned int rotation)
3738 {
3739         int cpp = fb->format->cpp[color_plane];
3740
3741         switch (fb->modifier) {
3742         case DRM_FORMAT_MOD_LINEAR:
3743         case I915_FORMAT_MOD_X_TILED:
3744                 if (cpp == 8)
3745                         return 4096;
3746                 else
3747                         return 5120;
3748         case I915_FORMAT_MOD_Y_TILED_CCS:
3749         case I915_FORMAT_MOD_Yf_TILED_CCS:
3750                 /* FIXME AUX plane? */
3751         case I915_FORMAT_MOD_Y_TILED:
3752         case I915_FORMAT_MOD_Yf_TILED:
3753                 if (cpp == 8)
3754                         return 2048;
3755                 else
3756                         return 5120;
3757         default:
3758                 MISSING_CASE(fb->modifier);
3759                 return 2048;
3760         }
3761 }
3762
3763 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3764                                int color_plane,
3765                                unsigned int rotation)
3766 {
3767         return 5120;
3768 }
3769
3770 static int skl_max_plane_height(void)
3771 {
3772         return 4096;
3773 }
3774
3775 static int icl_max_plane_height(void)
3776 {
3777         return 4320;
3778 }
3779
3780 static bool
3781 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3782                                int main_x, int main_y, u32 main_offset,
3783                                int ccs_plane)
3784 {
3785         const struct drm_framebuffer *fb = plane_state->hw.fb;
3786         int aux_x = plane_state->color_plane[ccs_plane].x;
3787         int aux_y = plane_state->color_plane[ccs_plane].y;
3788         u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3789         u32 alignment = intel_surf_alignment(fb, ccs_plane);
3790         int hsub;
3791         int vsub;
3792
3793         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3794         while (aux_offset >= main_offset && aux_y <= main_y) {
3795                 int x, y;
3796
3797                 if (aux_x == main_x && aux_y == main_y)
3798                         break;
3799
3800                 if (aux_offset == 0)
3801                         break;
3802
3803                 x = aux_x / hsub;
3804                 y = aux_y / vsub;
3805                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3806                                                                plane_state,
3807                                                                ccs_plane,
3808                                                                aux_offset,
3809                                                                aux_offset -
3810                                                                 alignment);
3811                 aux_x = x * hsub + aux_x % hsub;
3812                 aux_y = y * vsub + aux_y % vsub;
3813         }
3814
3815         if (aux_x != main_x || aux_y != main_y)
3816                 return false;
3817
3818         plane_state->color_plane[ccs_plane].offset = aux_offset;
3819         plane_state->color_plane[ccs_plane].x = aux_x;
3820         plane_state->color_plane[ccs_plane].y = aux_y;
3821
3822         return true;
3823 }
3824
3825 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3826 {
3827         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3828         const struct drm_framebuffer *fb = plane_state->hw.fb;
3829         unsigned int rotation = plane_state->hw.rotation;
3830         int x = plane_state->uapi.src.x1 >> 16;
3831         int y = plane_state->uapi.src.y1 >> 16;
3832         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3833         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3834         int max_width;
3835         int max_height;
3836         u32 alignment;
3837         u32 offset;
3838         int aux_plane = intel_main_to_aux_plane(fb, 0);
3839         u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3840
3841         if (INTEL_GEN(dev_priv) >= 11)
3842                 max_width = icl_max_plane_width(fb, 0, rotation);
3843         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3844                 max_width = glk_max_plane_width(fb, 0, rotation);
3845         else
3846                 max_width = skl_max_plane_width(fb, 0, rotation);
3847
3848         if (INTEL_GEN(dev_priv) >= 11)
3849                 max_height = icl_max_plane_height();
3850         else
3851                 max_height = skl_max_plane_height();
3852
3853         if (w > max_width || h > max_height) {
3854                 drm_dbg_kms(&dev_priv->drm,
3855                             "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3856                             w, h, max_width, max_height);
3857                 return -EINVAL;
3858         }
3859
3860         intel_add_fb_offsets(&x, &y, plane_state, 0);
3861         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3862         alignment = intel_surf_alignment(fb, 0);
3863         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3864                 return -EINVAL;
3865
3866         /*
3867          * AUX surface offset is specified as the distance from the
3868          * main surface offset, and it must be non-negative. Make
3869          * sure that is what we will get.
3870          */
3871         if (offset > aux_offset)
3872                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3873                                                            offset, aux_offset & ~(alignment - 1));
3874
3875         /*
3876          * When using an X-tiled surface, the plane blows up
3877          * if the x offset + width exceed the stride.
3878          *
3879          * TODO: linear and Y-tiled seem fine, Yf untested,
3880          */
3881         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3882                 int cpp = fb->format->cpp[0];
3883
3884                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3885                         if (offset == 0) {
3886                                 drm_dbg_kms(&dev_priv->drm,
3887                                             "Unable to find suitable display surface offset due to X-tiling\n");
3888                                 return -EINVAL;
3889                         }
3890
3891                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3892                                                                    offset, offset - alignment);
3893                 }
3894         }
3895
3896         /*
3897          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3898          * they match with the main surface x/y offsets.
3899          */
3900         if (is_ccs_modifier(fb->modifier)) {
3901                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3902                                                        offset, aux_plane)) {
3903                         if (offset == 0)
3904                                 break;
3905
3906                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3907                                                                    offset, offset - alignment);
3908                 }
3909
3910                 if (x != plane_state->color_plane[aux_plane].x ||
3911                     y != plane_state->color_plane[aux_plane].y) {
3912                         drm_dbg_kms(&dev_priv->drm,
3913                                     "Unable to find suitable display surface offset due to CCS\n");
3914                         return -EINVAL;
3915                 }
3916         }
3917
3918         plane_state->color_plane[0].offset = offset;
3919         plane_state->color_plane[0].x = x;
3920         plane_state->color_plane[0].y = y;
3921
3922         /*
3923          * Put the final coordinates back so that the src
3924          * coordinate checks will see the right values.
3925          */
3926         drm_rect_translate_to(&plane_state->uapi.src,
3927                               x << 16, y << 16);
3928
3929         return 0;
3930 }
3931
3932 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3933 {
3934         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
3935         const struct drm_framebuffer *fb = plane_state->hw.fb;
3936         unsigned int rotation = plane_state->hw.rotation;
3937         int uv_plane = 1;
3938         int max_width = skl_max_plane_width(fb, uv_plane, rotation);
3939         int max_height = 4096;
3940         int x = plane_state->uapi.src.x1 >> 17;
3941         int y = plane_state->uapi.src.y1 >> 17;
3942         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3943         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3944         u32 offset;
3945
3946         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
3947         offset = intel_plane_compute_aligned_offset(&x, &y,
3948                                                     plane_state, uv_plane);
3949
3950         /* FIXME not quite sure how/if these apply to the chroma plane */
3951         if (w > max_width || h > max_height) {
3952                 drm_dbg_kms(&i915->drm,
3953                             "CbCr source size %dx%d too big (limit %dx%d)\n",
3954                             w, h, max_width, max_height);
3955                 return -EINVAL;
3956         }
3957
3958         if (is_ccs_modifier(fb->modifier)) {
3959                 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
3960                 int aux_offset = plane_state->color_plane[ccs_plane].offset;
3961                 int alignment = intel_surf_alignment(fb, uv_plane);
3962
3963                 if (offset > aux_offset)
3964                         offset = intel_plane_adjust_aligned_offset(&x, &y,
3965                                                                    plane_state,
3966                                                                    uv_plane,
3967                                                                    offset,
3968                                                                    aux_offset & ~(alignment - 1));
3969
3970                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3971                                                        offset, ccs_plane)) {
3972                         if (offset == 0)
3973                                 break;
3974
3975                         offset = intel_plane_adjust_aligned_offset(&x, &y,
3976                                                                    plane_state,
3977                                                                    uv_plane,
3978                                                                    offset, offset - alignment);
3979                 }
3980
3981                 if (x != plane_state->color_plane[ccs_plane].x ||
3982                     y != plane_state->color_plane[ccs_plane].y) {
3983                         drm_dbg_kms(&i915->drm,
3984                                     "Unable to find suitable display surface offset due to CCS\n");
3985                         return -EINVAL;
3986                 }
3987         }
3988
3989         plane_state->color_plane[uv_plane].offset = offset;
3990         plane_state->color_plane[uv_plane].x = x;
3991         plane_state->color_plane[uv_plane].y = y;
3992
3993         return 0;
3994 }
3995
3996 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3997 {
3998         const struct drm_framebuffer *fb = plane_state->hw.fb;
3999         int src_x = plane_state->uapi.src.x1 >> 16;
4000         int src_y = plane_state->uapi.src.y1 >> 16;
4001         u32 offset;
4002         int ccs_plane;
4003
4004         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4005                 int main_hsub, main_vsub;
4006                 int hsub, vsub;
4007                 int x, y;
4008
4009                 if (!is_ccs_plane(fb, ccs_plane))
4010                         continue;
4011
4012                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4013                                                ccs_to_main_plane(fb, ccs_plane));
4014                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4015
4016                 hsub *= main_hsub;
4017                 vsub *= main_vsub;
4018                 x = src_x / hsub;
4019                 y = src_y / vsub;
4020
4021                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4022
4023                 offset = intel_plane_compute_aligned_offset(&x, &y,
4024                                                             plane_state,
4025                                                             ccs_plane);
4026
4027                 plane_state->color_plane[ccs_plane].offset = offset;
4028                 plane_state->color_plane[ccs_plane].x = (x * hsub +
4029                                                          src_x % hsub) /
4030                                                         main_hsub;
4031                 plane_state->color_plane[ccs_plane].y = (y * vsub +
4032                                                          src_y % vsub) /
4033                                                         main_vsub;
4034         }
4035
4036         return 0;
4037 }
4038
4039 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4040 {
4041         const struct drm_framebuffer *fb = plane_state->hw.fb;
4042         int ret;
4043         bool needs_aux = false;
4044
4045         ret = intel_plane_compute_gtt(plane_state);
4046         if (ret)
4047                 return ret;
4048
4049         if (!plane_state->uapi.visible)
4050                 return 0;
4051
4052         /*
4053          * Handle the AUX surface first since the main surface setup depends on
4054          * it.
4055          */
4056         if (is_ccs_modifier(fb->modifier)) {
4057                 needs_aux = true;
4058                 ret = skl_check_ccs_aux_surface(plane_state);
4059                 if (ret)
4060                         return ret;
4061         }
4062
4063         if (intel_format_info_is_yuv_semiplanar(fb->format,
4064                                                 fb->modifier)) {
4065                 needs_aux = true;
4066                 ret = skl_check_nv12_aux_surface(plane_state);
4067                 if (ret)
4068                         return ret;
4069         }
4070
4071         if (!needs_aux) {
4072                 int i;
4073
4074                 for (i = 1; i < fb->format->num_planes; i++) {
4075                         plane_state->color_plane[i].offset = ~0xfff;
4076                         plane_state->color_plane[i].x = 0;
4077                         plane_state->color_plane[i].y = 0;
4078                 }
4079         }
4080
4081         ret = skl_check_main_surface(plane_state);
4082         if (ret)
4083                 return ret;
4084
4085         return 0;
4086 }
4087
4088 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4089                              const struct intel_plane_state *plane_state,
4090                              unsigned int *num, unsigned int *den)
4091 {
4092         const struct drm_framebuffer *fb = plane_state->hw.fb;
4093         unsigned int cpp = fb->format->cpp[0];
4094
4095         /*
4096          * g4x bspec says 64bpp pixel rate can't exceed 80%
4097          * of cdclk when the sprite plane is enabled on the
4098          * same pipe. ilk/snb bspec says 64bpp pixel rate is
4099          * never allowed to exceed 80% of cdclk. Let's just go
4100          * with the ilk/snb limit always.
4101          */
4102         if (cpp == 8) {
4103                 *num = 10;
4104                 *den = 8;
4105         } else {
4106                 *num = 1;
4107                 *den = 1;
4108         }
4109 }
4110
4111 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4112                                 const struct intel_plane_state *plane_state)
4113 {
4114         unsigned int pixel_rate;
4115         unsigned int num, den;
4116
4117         /*
4118          * Note that crtc_state->pixel_rate accounts for both
4119          * horizontal and vertical panel fitter downscaling factors.
4120          * Pre-HSW bspec tells us to only consider the horizontal
4121          * downscaling factor here. We ignore that and just consider
4122          * both for simplicity.
4123          */
4124         pixel_rate = crtc_state->pixel_rate;
4125
4126         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4127
4128         /* two pixels per clock with double wide pipe */
4129         if (crtc_state->double_wide)
4130                 den *= 2;
4131
4132         return DIV_ROUND_UP(pixel_rate * num, den);
4133 }
4134
4135 unsigned int
4136 i9xx_plane_max_stride(struct intel_plane *plane,
4137                       u32 pixel_format, u64 modifier,
4138                       unsigned int rotation)
4139 {
4140         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4141
4142         if (!HAS_GMCH(dev_priv)) {
4143                 return 32*1024;
4144         } else if (INTEL_GEN(dev_priv) >= 4) {
4145                 if (modifier == I915_FORMAT_MOD_X_TILED)
4146                         return 16*1024;
4147                 else
4148                         return 32*1024;
4149         } else if (INTEL_GEN(dev_priv) >= 3) {
4150                 if (modifier == I915_FORMAT_MOD_X_TILED)
4151                         return 8*1024;
4152                 else
4153                         return 16*1024;
4154         } else {
4155                 if (plane->i9xx_plane == PLANE_C)
4156                         return 4*1024;
4157                 else
4158                         return 8*1024;
4159         }
4160 }
4161
4162 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4163 {
4164         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4165         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4166         u32 dspcntr = 0;
4167
4168         if (crtc_state->gamma_enable)
4169                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4170
4171         if (crtc_state->csc_enable)
4172                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4173
4174         if (INTEL_GEN(dev_priv) < 5)
4175                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4176
4177         return dspcntr;
4178 }
4179
4180 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4181                           const struct intel_plane_state *plane_state)
4182 {
4183         struct drm_i915_private *dev_priv =
4184                 to_i915(plane_state->uapi.plane->dev);
4185         const struct drm_framebuffer *fb = plane_state->hw.fb;
4186         unsigned int rotation = plane_state->hw.rotation;
4187         u32 dspcntr;
4188
4189         dspcntr = DISPLAY_PLANE_ENABLE;
4190
4191         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4192             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4193                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4194
4195         switch (fb->format->format) {
4196         case DRM_FORMAT_C8:
4197                 dspcntr |= DISPPLANE_8BPP;
4198                 break;
4199         case DRM_FORMAT_XRGB1555:
4200                 dspcntr |= DISPPLANE_BGRX555;
4201                 break;
4202         case DRM_FORMAT_ARGB1555:
4203                 dspcntr |= DISPPLANE_BGRA555;
4204                 break;
4205         case DRM_FORMAT_RGB565:
4206                 dspcntr |= DISPPLANE_BGRX565;
4207                 break;
4208         case DRM_FORMAT_XRGB8888:
4209                 dspcntr |= DISPPLANE_BGRX888;
4210                 break;
4211         case DRM_FORMAT_XBGR8888:
4212                 dspcntr |= DISPPLANE_RGBX888;
4213                 break;
4214         case DRM_FORMAT_ARGB8888:
4215                 dspcntr |= DISPPLANE_BGRA888;
4216                 break;
4217         case DRM_FORMAT_ABGR8888:
4218                 dspcntr |= DISPPLANE_RGBA888;
4219                 break;
4220         case DRM_FORMAT_XRGB2101010:
4221                 dspcntr |= DISPPLANE_BGRX101010;
4222                 break;
4223         case DRM_FORMAT_XBGR2101010:
4224                 dspcntr |= DISPPLANE_RGBX101010;
4225                 break;
4226         case DRM_FORMAT_ARGB2101010:
4227                 dspcntr |= DISPPLANE_BGRA101010;
4228                 break;
4229         case DRM_FORMAT_ABGR2101010:
4230                 dspcntr |= DISPPLANE_RGBA101010;
4231                 break;
4232         case DRM_FORMAT_XBGR16161616F:
4233                 dspcntr |= DISPPLANE_RGBX161616;
4234                 break;
4235         default:
4236                 MISSING_CASE(fb->format->format);
4237                 return 0;
4238         }
4239
4240         if (INTEL_GEN(dev_priv) >= 4 &&
4241             fb->modifier == I915_FORMAT_MOD_X_TILED)
4242                 dspcntr |= DISPPLANE_TILED;
4243
4244         if (rotation & DRM_MODE_ROTATE_180)
4245                 dspcntr |= DISPPLANE_ROTATE_180;
4246
4247         if (rotation & DRM_MODE_REFLECT_X)
4248                 dspcntr |= DISPPLANE_MIRROR;
4249
4250         return dspcntr;
4251 }
4252
4253 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4254 {
4255         struct drm_i915_private *dev_priv =
4256                 to_i915(plane_state->uapi.plane->dev);
4257         const struct drm_framebuffer *fb = plane_state->hw.fb;
4258         int src_x, src_y, src_w;
4259         u32 offset;
4260         int ret;
4261
4262         ret = intel_plane_compute_gtt(plane_state);
4263         if (ret)
4264                 return ret;
4265
4266         if (!plane_state->uapi.visible)
4267                 return 0;
4268
4269         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4270         src_x = plane_state->uapi.src.x1 >> 16;
4271         src_y = plane_state->uapi.src.y1 >> 16;
4272
4273         /* Undocumented hardware limit on i965/g4x/vlv/chv */
4274         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4275                 return -EINVAL;
4276
4277         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4278
4279         if (INTEL_GEN(dev_priv) >= 4)
4280                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4281                                                             plane_state, 0);
4282         else
4283                 offset = 0;
4284
4285         /*
4286          * Put the final coordinates back so that the src
4287          * coordinate checks will see the right values.
4288          */
4289         drm_rect_translate_to(&plane_state->uapi.src,
4290                               src_x << 16, src_y << 16);
4291
4292         /* HSW/BDW do this automagically in hardware */
4293         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4294                 unsigned int rotation = plane_state->hw.rotation;
4295                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4296                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4297
4298                 if (rotation & DRM_MODE_ROTATE_180) {
4299                         src_x += src_w - 1;
4300                         src_y += src_h - 1;
4301                 } else if (rotation & DRM_MODE_REFLECT_X) {
4302                         src_x += src_w - 1;
4303                 }
4304         }
4305
4306         plane_state->color_plane[0].offset = offset;
4307         plane_state->color_plane[0].x = src_x;
4308         plane_state->color_plane[0].y = src_y;
4309
4310         return 0;
4311 }
4312
4313 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4314 {
4315         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4316         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4317
4318         if (IS_CHERRYVIEW(dev_priv))
4319                 return i9xx_plane == PLANE_B;
4320         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4321                 return false;
4322         else if (IS_GEN(dev_priv, 4))
4323                 return i9xx_plane == PLANE_C;
4324         else
4325                 return i9xx_plane == PLANE_B ||
4326                         i9xx_plane == PLANE_C;
4327 }
4328
4329 static int
4330 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4331                  struct intel_plane_state *plane_state)
4332 {
4333         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4334         int ret;
4335
4336         ret = chv_plane_check_rotation(plane_state);
4337         if (ret)
4338                 return ret;
4339
4340         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4341                                                   &crtc_state->uapi,
4342                                                   DRM_PLANE_HELPER_NO_SCALING,
4343                                                   DRM_PLANE_HELPER_NO_SCALING,
4344                                                   i9xx_plane_has_windowing(plane),
4345                                                   true);
4346         if (ret)
4347                 return ret;
4348
4349         ret = i9xx_check_plane_surface(plane_state);
4350         if (ret)
4351                 return ret;
4352
4353         if (!plane_state->uapi.visible)
4354                 return 0;
4355
4356         ret = intel_plane_check_src_coordinates(plane_state);
4357         if (ret)
4358                 return ret;
4359
4360         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4361
4362         return 0;
4363 }
4364
4365 static void i9xx_update_plane(struct intel_plane *plane,
4366                               const struct intel_crtc_state *crtc_state,
4367                               const struct intel_plane_state *plane_state)
4368 {
4369         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4370         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4371         u32 linear_offset;
4372         int x = plane_state->color_plane[0].x;
4373         int y = plane_state->color_plane[0].y;
4374         int crtc_x = plane_state->uapi.dst.x1;
4375         int crtc_y = plane_state->uapi.dst.y1;
4376         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4377         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4378         unsigned long irqflags;
4379         u32 dspaddr_offset;
4380         u32 dspcntr;
4381
4382         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4383
4384         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4385
4386         if (INTEL_GEN(dev_priv) >= 4)
4387                 dspaddr_offset = plane_state->color_plane[0].offset;
4388         else
4389                 dspaddr_offset = linear_offset;
4390
4391         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4392
4393         intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4394                           plane_state->color_plane[0].stride);
4395
4396         if (INTEL_GEN(dev_priv) < 4) {
4397                 /*
4398                  * PLANE_A doesn't actually have a full window
4399                  * generator but let's assume we still need to
4400                  * program whatever is there.
4401                  */
4402                 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4403                                   (crtc_y << 16) | crtc_x);
4404                 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4405                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4406         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4407                 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4408                                   (crtc_y << 16) | crtc_x);
4409                 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4410                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4411                 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4412         }
4413
4414         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4415                 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4416                                   (y << 16) | x);
4417         } else if (INTEL_GEN(dev_priv) >= 4) {
4418                 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4419                                   linear_offset);
4420                 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4421                                   (y << 16) | x);
4422         }
4423
4424         /*
4425          * The control register self-arms if the plane was previously
4426          * disabled. Try to make the plane enable atomic by writing
4427          * the control register just before the surface register.
4428          */
4429         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4430         if (INTEL_GEN(dev_priv) >= 4)
4431                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4432                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4433         else
4434                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4435                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4436
4437         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4438 }
4439
4440 static void i9xx_disable_plane(struct intel_plane *plane,
4441                                const struct intel_crtc_state *crtc_state)
4442 {
4443         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4444         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4445         unsigned long irqflags;
4446         u32 dspcntr;
4447
4448         /*
4449          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4450          * enable on ilk+ affect the pipe bottom color as
4451          * well, so we must configure them even if the plane
4452          * is disabled.
4453          *
4454          * On pre-g4x there is no way to gamma correct the
4455          * pipe bottom color but we'll keep on doing this
4456          * anyway so that the crtc state readout works correctly.
4457          */
4458         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4459
4460         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4461
4462         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4463         if (INTEL_GEN(dev_priv) >= 4)
4464                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4465         else
4466                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4467
4468         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4469 }
4470
4471 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4472                                     enum pipe *pipe)
4473 {
4474         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4475         enum intel_display_power_domain power_domain;
4476         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4477         intel_wakeref_t wakeref;
4478         bool ret;
4479         u32 val;
4480
4481         /*
4482          * Not 100% correct for planes that can move between pipes,
4483          * but that's only the case for gen2-4 which don't have any
4484          * display power wells.
4485          */
4486         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4487         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4488         if (!wakeref)
4489                 return false;
4490
4491         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4492
4493         ret = val & DISPLAY_PLANE_ENABLE;
4494
4495         if (INTEL_GEN(dev_priv) >= 5)
4496                 *pipe = plane->pipe;
4497         else
4498                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4499                         DISPPLANE_SEL_PIPE_SHIFT;
4500
4501         intel_display_power_put(dev_priv, power_domain, wakeref);
4502
4503         return ret;
4504 }
4505
4506 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4507 {
4508         struct drm_device *dev = intel_crtc->base.dev;
4509         struct drm_i915_private *dev_priv = to_i915(dev);
4510         unsigned long irqflags;
4511
4512         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4513
4514         intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4515         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4516         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4517
4518         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4519 }
4520
4521 /*
4522  * This function detaches (aka. unbinds) unused scalers in hardware
4523  */
4524 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4525 {
4526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4527         const struct intel_crtc_scaler_state *scaler_state =
4528                 &crtc_state->scaler_state;
4529         int i;
4530
4531         /* loop through and disable scalers that aren't in use */
4532         for (i = 0; i < intel_crtc->num_scalers; i++) {
4533                 if (!scaler_state->scalers[i].in_use)
4534                         skl_detach_scaler(intel_crtc, i);
4535         }
4536 }
4537
4538 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4539                                           int color_plane, unsigned int rotation)
4540 {
4541         /*
4542          * The stride is either expressed as a multiple of 64 bytes chunks for
4543          * linear buffers or in number of tiles for tiled buffers.
4544          */
4545         if (is_surface_linear(fb, color_plane))
4546                 return 64;
4547         else if (drm_rotation_90_or_270(rotation))
4548                 return intel_tile_height(fb, color_plane);
4549         else
4550                 return intel_tile_width_bytes(fb, color_plane);
4551 }
4552
4553 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4554                      int color_plane)
4555 {
4556         const struct drm_framebuffer *fb = plane_state->hw.fb;
4557         unsigned int rotation = plane_state->hw.rotation;
4558         u32 stride = plane_state->color_plane[color_plane].stride;
4559
4560         if (color_plane >= fb->format->num_planes)
4561                 return 0;
4562
4563         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4564 }
4565
4566 static u32 skl_plane_ctl_format(u32 pixel_format)
4567 {
4568         switch (pixel_format) {
4569         case DRM_FORMAT_C8:
4570                 return PLANE_CTL_FORMAT_INDEXED;
4571         case DRM_FORMAT_RGB565:
4572                 return PLANE_CTL_FORMAT_RGB_565;
4573         case DRM_FORMAT_XBGR8888:
4574         case DRM_FORMAT_ABGR8888:
4575                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4576         case DRM_FORMAT_XRGB8888:
4577         case DRM_FORMAT_ARGB8888:
4578                 return PLANE_CTL_FORMAT_XRGB_8888;
4579         case DRM_FORMAT_XBGR2101010:
4580         case DRM_FORMAT_ABGR2101010:
4581                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4582         case DRM_FORMAT_XRGB2101010:
4583         case DRM_FORMAT_ARGB2101010:
4584                 return PLANE_CTL_FORMAT_XRGB_2101010;
4585         case DRM_FORMAT_XBGR16161616F:
4586         case DRM_FORMAT_ABGR16161616F:
4587                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4588         case DRM_FORMAT_XRGB16161616F:
4589         case DRM_FORMAT_ARGB16161616F:
4590                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4591         case DRM_FORMAT_XYUV8888:
4592                 return PLANE_CTL_FORMAT_XYUV;
4593         case DRM_FORMAT_YUYV:
4594                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4595         case DRM_FORMAT_YVYU:
4596                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4597         case DRM_FORMAT_UYVY:
4598                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4599         case DRM_FORMAT_VYUY:
4600                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4601         case DRM_FORMAT_NV12:
4602                 return PLANE_CTL_FORMAT_NV12;
4603         case DRM_FORMAT_P010:
4604                 return PLANE_CTL_FORMAT_P010;
4605         case DRM_FORMAT_P012:
4606                 return PLANE_CTL_FORMAT_P012;
4607         case DRM_FORMAT_P016:
4608                 return PLANE_CTL_FORMAT_P016;
4609         case DRM_FORMAT_Y210:
4610                 return PLANE_CTL_FORMAT_Y210;
4611         case DRM_FORMAT_Y212:
4612                 return PLANE_CTL_FORMAT_Y212;
4613         case DRM_FORMAT_Y216:
4614                 return PLANE_CTL_FORMAT_Y216;
4615         case DRM_FORMAT_XVYU2101010:
4616                 return PLANE_CTL_FORMAT_Y410;
4617         case DRM_FORMAT_XVYU12_16161616:
4618                 return PLANE_CTL_FORMAT_Y412;
4619         case DRM_FORMAT_XVYU16161616:
4620                 return PLANE_CTL_FORMAT_Y416;
4621         default:
4622                 MISSING_CASE(pixel_format);
4623         }
4624
4625         return 0;
4626 }
4627
4628 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4629 {
4630         if (!plane_state->hw.fb->format->has_alpha)
4631                 return PLANE_CTL_ALPHA_DISABLE;
4632
4633         switch (plane_state->hw.pixel_blend_mode) {
4634         case DRM_MODE_BLEND_PIXEL_NONE:
4635                 return PLANE_CTL_ALPHA_DISABLE;
4636         case DRM_MODE_BLEND_PREMULTI:
4637                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4638         case DRM_MODE_BLEND_COVERAGE:
4639                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4640         default:
4641                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4642                 return PLANE_CTL_ALPHA_DISABLE;
4643         }
4644 }
4645
4646 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4647 {
4648         if (!plane_state->hw.fb->format->has_alpha)
4649                 return PLANE_COLOR_ALPHA_DISABLE;
4650
4651         switch (plane_state->hw.pixel_blend_mode) {
4652         case DRM_MODE_BLEND_PIXEL_NONE:
4653                 return PLANE_COLOR_ALPHA_DISABLE;
4654         case DRM_MODE_BLEND_PREMULTI:
4655                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4656         case DRM_MODE_BLEND_COVERAGE:
4657                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4658         default:
4659                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4660                 return PLANE_COLOR_ALPHA_DISABLE;
4661         }
4662 }
4663
4664 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4665 {
4666         switch (fb_modifier) {
4667         case DRM_FORMAT_MOD_LINEAR:
4668                 break;
4669         case I915_FORMAT_MOD_X_TILED:
4670                 return PLANE_CTL_TILED_X;
4671         case I915_FORMAT_MOD_Y_TILED:
4672                 return PLANE_CTL_TILED_Y;
4673         case I915_FORMAT_MOD_Y_TILED_CCS:
4674                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4675         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4676                 return PLANE_CTL_TILED_Y |
4677                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4678                        PLANE_CTL_CLEAR_COLOR_DISABLE;
4679         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4680                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4681         case I915_FORMAT_MOD_Yf_TILED:
4682                 return PLANE_CTL_TILED_YF;
4683         case I915_FORMAT_MOD_Yf_TILED_CCS:
4684                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4685         default:
4686                 MISSING_CASE(fb_modifier);
4687         }
4688
4689         return 0;
4690 }
4691
4692 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4693 {
4694         switch (rotate) {
4695         case DRM_MODE_ROTATE_0:
4696                 break;
4697         /*
4698          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4699          * while i915 HW rotation is clockwise, thats why this swapping.
4700          */
4701         case DRM_MODE_ROTATE_90:
4702                 return PLANE_CTL_ROTATE_270;
4703         case DRM_MODE_ROTATE_180:
4704                 return PLANE_CTL_ROTATE_180;
4705         case DRM_MODE_ROTATE_270:
4706                 return PLANE_CTL_ROTATE_90;
4707         default:
4708                 MISSING_CASE(rotate);
4709         }
4710
4711         return 0;
4712 }
4713
4714 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4715 {
4716         switch (reflect) {
4717         case 0:
4718                 break;
4719         case DRM_MODE_REFLECT_X:
4720                 return PLANE_CTL_FLIP_HORIZONTAL;
4721         case DRM_MODE_REFLECT_Y:
4722         default:
4723                 MISSING_CASE(reflect);
4724         }
4725
4726         return 0;
4727 }
4728
4729 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4730 {
4731         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4732         u32 plane_ctl = 0;
4733
4734         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4735                 return plane_ctl;
4736
4737         if (crtc_state->gamma_enable)
4738                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4739
4740         if (crtc_state->csc_enable)
4741                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4742
4743         return plane_ctl;
4744 }
4745
4746 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4747                   const struct intel_plane_state *plane_state)
4748 {
4749         struct drm_i915_private *dev_priv =
4750                 to_i915(plane_state->uapi.plane->dev);
4751         const struct drm_framebuffer *fb = plane_state->hw.fb;
4752         unsigned int rotation = plane_state->hw.rotation;
4753         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4754         u32 plane_ctl;
4755
4756         plane_ctl = PLANE_CTL_ENABLE;
4757
4758         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4759                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4760                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4761
4762                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4763                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4764
4765                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4766                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4767         }
4768
4769         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4770         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4771         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4772
4773         if (INTEL_GEN(dev_priv) >= 10)
4774                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4775                                                 DRM_MODE_REFLECT_MASK);
4776
4777         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4778                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4779         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4780                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4781
4782         return plane_ctl;
4783 }
4784
4785 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4786 {
4787         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4788         u32 plane_color_ctl = 0;
4789
4790         if (INTEL_GEN(dev_priv) >= 11)
4791                 return plane_color_ctl;
4792
4793         if (crtc_state->gamma_enable)
4794                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4795
4796         if (crtc_state->csc_enable)
4797                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4798
4799         return plane_color_ctl;
4800 }
4801
4802 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4803                         const struct intel_plane_state *plane_state)
4804 {
4805         struct drm_i915_private *dev_priv =
4806                 to_i915(plane_state->uapi.plane->dev);
4807         const struct drm_framebuffer *fb = plane_state->hw.fb;
4808         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4809         u32 plane_color_ctl = 0;
4810
4811         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4812         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4813
4814         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4815                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4816                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4817                 else
4818                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4819
4820                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4821                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4822         } else if (fb->format->is_yuv) {
4823                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4824         }
4825
4826         return plane_color_ctl;
4827 }
4828
4829 static int
4830 __intel_display_resume(struct drm_device *dev,
4831                        struct drm_atomic_state *state,
4832                        struct drm_modeset_acquire_ctx *ctx)
4833 {
4834         struct drm_crtc_state *crtc_state;
4835         struct drm_crtc *crtc;
4836         int i, ret;
4837
4838         intel_modeset_setup_hw_state(dev, ctx);
4839         intel_vga_redisable(to_i915(dev));
4840
4841         if (!state)
4842                 return 0;
4843
4844         /*
4845          * We've duplicated the state, pointers to the old state are invalid.
4846          *
4847          * Don't attempt to use the old state until we commit the duplicated state.
4848          */
4849         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4850                 /*
4851                  * Force recalculation even if we restore
4852                  * current state. With fast modeset this may not result
4853                  * in a modeset when the state is compatible.
4854                  */
4855                 crtc_state->mode_changed = true;
4856         }
4857
4858         /* ignore any reset values/BIOS leftovers in the WM registers */
4859         if (!HAS_GMCH(to_i915(dev)))
4860                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4861
4862         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4863
4864         drm_WARN_ON(dev, ret == -EDEADLK);
4865         return ret;
4866 }
4867
4868 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4869 {
4870         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4871                 intel_has_gpu_reset(&dev_priv->gt));
4872 }
4873
4874 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4875 {
4876         struct drm_device *dev = &dev_priv->drm;
4877         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4878         struct drm_atomic_state *state;
4879         int ret;
4880
4881         /* reset doesn't touch the display */
4882         if (!i915_modparams.force_reset_modeset_test &&
4883             !gpu_reset_clobbers_display(dev_priv))
4884                 return;
4885
4886         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4887         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4888         smp_mb__after_atomic();
4889         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4890
4891         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4892                 drm_dbg_kms(&dev_priv->drm,
4893                             "Modeset potentially stuck, unbreaking through wedging\n");
4894                 intel_gt_set_wedged(&dev_priv->gt);
4895         }
4896
4897         /*
4898          * Need mode_config.mutex so that we don't
4899          * trample ongoing ->detect() and whatnot.
4900          */
4901         mutex_lock(&dev->mode_config.mutex);
4902         drm_modeset_acquire_init(ctx, 0);
4903         while (1) {
4904                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4905                 if (ret != -EDEADLK)
4906                         break;
4907
4908                 drm_modeset_backoff(ctx);
4909         }
4910         /*
4911          * Disabling the crtcs gracefully seems nicer. Also the
4912          * g33 docs say we should at least disable all the planes.
4913          */
4914         state = drm_atomic_helper_duplicate_state(dev, ctx);
4915         if (IS_ERR(state)) {
4916                 ret = PTR_ERR(state);
4917                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
4918                         ret);
4919                 return;
4920         }
4921
4922         ret = drm_atomic_helper_disable_all(dev, ctx);
4923         if (ret) {
4924                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4925                         ret);
4926                 drm_atomic_state_put(state);
4927                 return;
4928         }
4929
4930         dev_priv->modeset_restore_state = state;
4931         state->acquire_ctx = ctx;
4932 }
4933
4934 void intel_finish_reset(struct drm_i915_private *dev_priv)
4935 {
4936         struct drm_device *dev = &dev_priv->drm;
4937         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4938         struct drm_atomic_state *state;
4939         int ret;
4940
4941         /* reset doesn't touch the display */
4942         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4943                 return;
4944
4945         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4946         if (!state)
4947                 goto unlock;
4948
4949         /* reset doesn't touch the display */
4950         if (!gpu_reset_clobbers_display(dev_priv)) {
4951                 /* for testing only restore the display */
4952                 ret = __intel_display_resume(dev, state, ctx);
4953                 if (ret)
4954                         drm_err(&dev_priv->drm,
4955                                 "Restoring old state failed with %i\n", ret);
4956         } else {
4957                 /*
4958                  * The display has been reset as well,
4959                  * so need a full re-initialization.
4960                  */
4961                 intel_pps_unlock_regs_wa(dev_priv);
4962                 intel_modeset_init_hw(dev_priv);
4963                 intel_init_clock_gating(dev_priv);
4964
4965                 spin_lock_irq(&dev_priv->irq_lock);
4966                 if (dev_priv->display.hpd_irq_setup)
4967                         dev_priv->display.hpd_irq_setup(dev_priv);
4968                 spin_unlock_irq(&dev_priv->irq_lock);
4969
4970                 ret = __intel_display_resume(dev, state, ctx);
4971                 if (ret)
4972                         drm_err(&dev_priv->drm,
4973                                 "Restoring old state failed with %i\n", ret);
4974
4975                 intel_hpd_init(dev_priv);
4976         }
4977
4978         drm_atomic_state_put(state);
4979 unlock:
4980         drm_modeset_drop_locks(ctx);
4981         drm_modeset_acquire_fini(ctx);
4982         mutex_unlock(&dev->mode_config.mutex);
4983
4984         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4985 }
4986
4987 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4988 {
4989         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4990         enum pipe pipe = crtc->pipe;
4991         u32 tmp;
4992
4993         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
4994
4995         /*
4996          * Display WA #1153: icl
4997          * enable hardware to bypass the alpha math
4998          * and rounding for per-pixel values 00 and 0xff
4999          */
5000         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5001         /*
5002          * Display WA # 1605353570: icl
5003          * Set the pixel rounding bit to 1 for allowing
5004          * passthrough of Frame buffer pixels unmodified
5005          * across pipe
5006          */
5007         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5008         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5009 }
5010
5011 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5012 {
5013         struct drm_device *dev = crtc->base.dev;
5014         struct drm_i915_private *dev_priv = to_i915(dev);
5015         enum pipe pipe = crtc->pipe;
5016         i915_reg_t reg;
5017         u32 temp;
5018
5019         /* enable normal train */
5020         reg = FDI_TX_CTL(pipe);
5021         temp = intel_de_read(dev_priv, reg);
5022         if (IS_IVYBRIDGE(dev_priv)) {
5023                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5024                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5025         } else {
5026                 temp &= ~FDI_LINK_TRAIN_NONE;
5027                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5028         }
5029         intel_de_write(dev_priv, reg, temp);
5030
5031         reg = FDI_RX_CTL(pipe);
5032         temp = intel_de_read(dev_priv, reg);
5033         if (HAS_PCH_CPT(dev_priv)) {
5034                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5035                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5036         } else {
5037                 temp &= ~FDI_LINK_TRAIN_NONE;
5038                 temp |= FDI_LINK_TRAIN_NONE;
5039         }
5040         intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5041
5042         /* wait one idle pattern time */
5043         intel_de_posting_read(dev_priv, reg);
5044         udelay(1000);
5045
5046         /* IVB wants error correction enabled */
5047         if (IS_IVYBRIDGE(dev_priv))
5048                 intel_de_write(dev_priv, reg,
5049                                intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5050 }
5051
5052 /* The FDI link training functions for ILK/Ibexpeak. */
5053 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5054                                const struct intel_crtc_state *crtc_state)
5055 {
5056         struct drm_device *dev = crtc->base.dev;
5057         struct drm_i915_private *dev_priv = to_i915(dev);
5058         enum pipe pipe = crtc->pipe;
5059         i915_reg_t reg;
5060         u32 temp, tries;
5061
5062         /* FDI needs bits from pipe first */
5063         assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5064
5065         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5066            for train result */
5067         reg = FDI_RX_IMR(pipe);
5068         temp = intel_de_read(dev_priv, reg);
5069         temp &= ~FDI_RX_SYMBOL_LOCK;
5070         temp &= ~FDI_RX_BIT_LOCK;
5071         intel_de_write(dev_priv, reg, temp);
5072         intel_de_read(dev_priv, reg);
5073         udelay(150);
5074
5075         /* enable CPU FDI TX and PCH FDI RX */
5076         reg = FDI_TX_CTL(pipe);
5077         temp = intel_de_read(dev_priv, reg);
5078         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5079         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5080         temp &= ~FDI_LINK_TRAIN_NONE;
5081         temp |= FDI_LINK_TRAIN_PATTERN_1;
5082         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5083
5084         reg = FDI_RX_CTL(pipe);
5085         temp = intel_de_read(dev_priv, reg);
5086         temp &= ~FDI_LINK_TRAIN_NONE;
5087         temp |= FDI_LINK_TRAIN_PATTERN_1;
5088         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5089
5090         intel_de_posting_read(dev_priv, reg);
5091         udelay(150);
5092
5093         /* Ironlake workaround, enable clock pointer after FDI enable*/
5094         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5095                        FDI_RX_PHASE_SYNC_POINTER_OVR);
5096         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5097                        FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5098
5099         reg = FDI_RX_IIR(pipe);
5100         for (tries = 0; tries < 5; tries++) {
5101                 temp = intel_de_read(dev_priv, reg);
5102                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5103
5104                 if ((temp & FDI_RX_BIT_LOCK)) {
5105                         drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5106                         intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5107                         break;
5108                 }
5109         }
5110         if (tries == 5)
5111                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5112
5113         /* Train 2 */
5114         reg = FDI_TX_CTL(pipe);
5115         temp = intel_de_read(dev_priv, reg);
5116         temp &= ~FDI_LINK_TRAIN_NONE;
5117         temp |= FDI_LINK_TRAIN_PATTERN_2;
5118         intel_de_write(dev_priv, reg, temp);
5119
5120         reg = FDI_RX_CTL(pipe);
5121         temp = intel_de_read(dev_priv, reg);
5122         temp &= ~FDI_LINK_TRAIN_NONE;
5123         temp |= FDI_LINK_TRAIN_PATTERN_2;
5124         intel_de_write(dev_priv, reg, temp);
5125
5126         intel_de_posting_read(dev_priv, reg);
5127         udelay(150);
5128
5129         reg = FDI_RX_IIR(pipe);
5130         for (tries = 0; tries < 5; tries++) {
5131                 temp = intel_de_read(dev_priv, reg);
5132                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5133
5134                 if (temp & FDI_RX_SYMBOL_LOCK) {
5135                         intel_de_write(dev_priv, reg,
5136                                        temp | FDI_RX_SYMBOL_LOCK);
5137                         drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5138                         break;
5139                 }
5140         }
5141         if (tries == 5)
5142                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5143
5144         drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5145
5146 }
5147
5148 static const int snb_b_fdi_train_param[] = {
5149         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5150         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5151         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5152         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5153 };
5154
5155 /* The FDI link training functions for SNB/Cougarpoint. */
5156 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5157                                 const struct intel_crtc_state *crtc_state)
5158 {
5159         struct drm_device *dev = crtc->base.dev;
5160         struct drm_i915_private *dev_priv = to_i915(dev);
5161         enum pipe pipe = crtc->pipe;
5162         i915_reg_t reg;
5163         u32 temp, i, retry;
5164
5165         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5166            for train result */
5167         reg = FDI_RX_IMR(pipe);
5168         temp = intel_de_read(dev_priv, reg);
5169         temp &= ~FDI_RX_SYMBOL_LOCK;
5170         temp &= ~FDI_RX_BIT_LOCK;
5171         intel_de_write(dev_priv, reg, temp);
5172
5173         intel_de_posting_read(dev_priv, reg);
5174         udelay(150);
5175
5176         /* enable CPU FDI TX and PCH FDI RX */
5177         reg = FDI_TX_CTL(pipe);
5178         temp = intel_de_read(dev_priv, reg);
5179         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5180         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5181         temp &= ~FDI_LINK_TRAIN_NONE;
5182         temp |= FDI_LINK_TRAIN_PATTERN_1;
5183         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5184         /* SNB-B */
5185         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5186         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5187
5188         intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5189                        FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5190
5191         reg = FDI_RX_CTL(pipe);
5192         temp = intel_de_read(dev_priv, reg);
5193         if (HAS_PCH_CPT(dev_priv)) {
5194                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5195                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5196         } else {
5197                 temp &= ~FDI_LINK_TRAIN_NONE;
5198                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5199         }
5200         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5201
5202         intel_de_posting_read(dev_priv, reg);
5203         udelay(150);
5204
5205         for (i = 0; i < 4; i++) {
5206                 reg = FDI_TX_CTL(pipe);
5207                 temp = intel_de_read(dev_priv, reg);
5208                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5209                 temp |= snb_b_fdi_train_param[i];
5210                 intel_de_write(dev_priv, reg, temp);
5211
5212                 intel_de_posting_read(dev_priv, reg);
5213                 udelay(500);
5214
5215                 for (retry = 0; retry < 5; retry++) {
5216                         reg = FDI_RX_IIR(pipe);
5217                         temp = intel_de_read(dev_priv, reg);
5218                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5219                         if (temp & FDI_RX_BIT_LOCK) {
5220                                 intel_de_write(dev_priv, reg,
5221                                                temp | FDI_RX_BIT_LOCK);
5222                                 drm_dbg_kms(&dev_priv->drm,
5223                                             "FDI train 1 done.\n");
5224                                 break;
5225                         }
5226                         udelay(50);
5227                 }
5228                 if (retry < 5)
5229                         break;
5230         }
5231         if (i == 4)
5232                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5233
5234         /* Train 2 */
5235         reg = FDI_TX_CTL(pipe);
5236         temp = intel_de_read(dev_priv, reg);
5237         temp &= ~FDI_LINK_TRAIN_NONE;
5238         temp |= FDI_LINK_TRAIN_PATTERN_2;
5239         if (IS_GEN(dev_priv, 6)) {
5240                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5241                 /* SNB-B */
5242                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5243         }
5244         intel_de_write(dev_priv, reg, temp);
5245
5246         reg = FDI_RX_CTL(pipe);
5247         temp = intel_de_read(dev_priv, reg);
5248         if (HAS_PCH_CPT(dev_priv)) {
5249                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5250                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5251         } else {
5252                 temp &= ~FDI_LINK_TRAIN_NONE;
5253                 temp |= FDI_LINK_TRAIN_PATTERN_2;
5254         }
5255         intel_de_write(dev_priv, reg, temp);
5256
5257         intel_de_posting_read(dev_priv, reg);
5258         udelay(150);
5259
5260         for (i = 0; i < 4; i++) {
5261                 reg = FDI_TX_CTL(pipe);
5262                 temp = intel_de_read(dev_priv, reg);
5263                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5264                 temp |= snb_b_fdi_train_param[i];
5265                 intel_de_write(dev_priv, reg, temp);
5266
5267                 intel_de_posting_read(dev_priv, reg);
5268                 udelay(500);
5269
5270                 for (retry = 0; retry < 5; retry++) {
5271                         reg = FDI_RX_IIR(pipe);
5272                         temp = intel_de_read(dev_priv, reg);
5273                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5274                         if (temp & FDI_RX_SYMBOL_LOCK) {
5275                                 intel_de_write(dev_priv, reg,
5276                                                temp | FDI_RX_SYMBOL_LOCK);
5277                                 drm_dbg_kms(&dev_priv->drm,
5278                                             "FDI train 2 done.\n");
5279                                 break;
5280                         }
5281                         udelay(50);
5282                 }
5283                 if (retry < 5)
5284                         break;
5285         }
5286         if (i == 4)
5287                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5288
5289         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5290 }
5291
5292 /* Manual link training for Ivy Bridge A0 parts */
5293 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5294                                       const struct intel_crtc_state *crtc_state)
5295 {
5296         struct drm_device *dev = crtc->base.dev;
5297         struct drm_i915_private *dev_priv = to_i915(dev);
5298         enum pipe pipe = crtc->pipe;
5299         i915_reg_t reg;
5300         u32 temp, i, j;
5301
5302         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5303            for train result */
5304         reg = FDI_RX_IMR(pipe);
5305         temp = intel_de_read(dev_priv, reg);
5306         temp &= ~FDI_RX_SYMBOL_LOCK;
5307         temp &= ~FDI_RX_BIT_LOCK;
5308         intel_de_write(dev_priv, reg, temp);
5309
5310         intel_de_posting_read(dev_priv, reg);
5311         udelay(150);
5312
5313         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5314                     intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5315
5316         /* Try each vswing and preemphasis setting twice before moving on */
5317         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5318                 /* disable first in case we need to retry */
5319                 reg = FDI_TX_CTL(pipe);
5320                 temp = intel_de_read(dev_priv, reg);
5321                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5322                 temp &= ~FDI_TX_ENABLE;
5323                 intel_de_write(dev_priv, reg, temp);
5324
5325                 reg = FDI_RX_CTL(pipe);
5326                 temp = intel_de_read(dev_priv, reg);
5327                 temp &= ~FDI_LINK_TRAIN_AUTO;
5328                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5329                 temp &= ~FDI_RX_ENABLE;
5330                 intel_de_write(dev_priv, reg, temp);
5331
5332                 /* enable CPU FDI TX and PCH FDI RX */
5333                 reg = FDI_TX_CTL(pipe);
5334                 temp = intel_de_read(dev_priv, reg);
5335                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5336                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5337                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5338                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5339                 temp |= snb_b_fdi_train_param[j/2];
5340                 temp |= FDI_COMPOSITE_SYNC;
5341                 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5342
5343                 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5344                                FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5345
5346                 reg = FDI_RX_CTL(pipe);
5347                 temp = intel_de_read(dev_priv, reg);
5348                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5349                 temp |= FDI_COMPOSITE_SYNC;
5350                 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5351
5352                 intel_de_posting_read(dev_priv, reg);
5353                 udelay(1); /* should be 0.5us */
5354
5355                 for (i = 0; i < 4; i++) {
5356                         reg = FDI_RX_IIR(pipe);
5357                         temp = intel_de_read(dev_priv, reg);
5358                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5359
5360                         if (temp & FDI_RX_BIT_LOCK ||
5361                             (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5362                                 intel_de_write(dev_priv, reg,
5363                                                temp | FDI_RX_BIT_LOCK);
5364                                 drm_dbg_kms(&dev_priv->drm,
5365                                             "FDI train 1 done, level %i.\n",
5366                                             i);
5367                                 break;
5368                         }
5369                         udelay(1); /* should be 0.5us */
5370                 }
5371                 if (i == 4) {
5372                         drm_dbg_kms(&dev_priv->drm,
5373                                     "FDI train 1 fail on vswing %d\n", j / 2);
5374                         continue;
5375                 }
5376
5377                 /* Train 2 */
5378                 reg = FDI_TX_CTL(pipe);
5379                 temp = intel_de_read(dev_priv, reg);
5380                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5381                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5382                 intel_de_write(dev_priv, reg, temp);
5383
5384                 reg = FDI_RX_CTL(pipe);
5385                 temp = intel_de_read(dev_priv, reg);
5386                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5387                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5388                 intel_de_write(dev_priv, reg, temp);
5389
5390                 intel_de_posting_read(dev_priv, reg);
5391                 udelay(2); /* should be 1.5us */
5392
5393                 for (i = 0; i < 4; i++) {
5394                         reg = FDI_RX_IIR(pipe);
5395                         temp = intel_de_read(dev_priv, reg);
5396                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5397
5398                         if (temp & FDI_RX_SYMBOL_LOCK ||
5399                             (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5400                                 intel_de_write(dev_priv, reg,
5401                                                temp | FDI_RX_SYMBOL_LOCK);
5402                                 drm_dbg_kms(&dev_priv->drm,
5403                                             "FDI train 2 done, level %i.\n",
5404                                             i);
5405                                 goto train_done;
5406                         }
5407                         udelay(2); /* should be 1.5us */
5408                 }
5409                 if (i == 4)
5410                         drm_dbg_kms(&dev_priv->drm,
5411                                     "FDI train 2 fail on vswing %d\n", j / 2);
5412         }
5413
5414 train_done:
5415         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5416 }
5417
5418 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5419 {
5420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5421         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5422         enum pipe pipe = intel_crtc->pipe;
5423         i915_reg_t reg;
5424         u32 temp;
5425
5426         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5427         reg = FDI_RX_CTL(pipe);
5428         temp = intel_de_read(dev_priv, reg);
5429         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5430         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5431         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5432         intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5433
5434         intel_de_posting_read(dev_priv, reg);
5435         udelay(200);
5436
5437         /* Switch from Rawclk to PCDclk */
5438         temp = intel_de_read(dev_priv, reg);
5439         intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5440
5441         intel_de_posting_read(dev_priv, reg);
5442         udelay(200);
5443
5444         /* Enable CPU FDI TX PLL, always on for Ironlake */
5445         reg = FDI_TX_CTL(pipe);
5446         temp = intel_de_read(dev_priv, reg);
5447         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5448                 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5449
5450                 intel_de_posting_read(dev_priv, reg);
5451                 udelay(100);
5452         }
5453 }
5454
5455 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5456 {
5457         struct drm_device *dev = intel_crtc->base.dev;
5458         struct drm_i915_private *dev_priv = to_i915(dev);
5459         enum pipe pipe = intel_crtc->pipe;
5460         i915_reg_t reg;
5461         u32 temp;
5462
5463         /* Switch from PCDclk to Rawclk */
5464         reg = FDI_RX_CTL(pipe);
5465         temp = intel_de_read(dev_priv, reg);
5466         intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5467
5468         /* Disable CPU FDI TX PLL */
5469         reg = FDI_TX_CTL(pipe);
5470         temp = intel_de_read(dev_priv, reg);
5471         intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5472
5473         intel_de_posting_read(dev_priv, reg);
5474         udelay(100);
5475
5476         reg = FDI_RX_CTL(pipe);
5477         temp = intel_de_read(dev_priv, reg);
5478         intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5479
5480         /* Wait for the clocks to turn off. */
5481         intel_de_posting_read(dev_priv, reg);
5482         udelay(100);
5483 }
5484
5485 static void ilk_fdi_disable(struct intel_crtc *crtc)
5486 {
5487         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5488         enum pipe pipe = crtc->pipe;
5489         i915_reg_t reg;
5490         u32 temp;
5491
5492         /* disable CPU FDI tx and PCH FDI rx */
5493         reg = FDI_TX_CTL(pipe);
5494         temp = intel_de_read(dev_priv, reg);
5495         intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5496         intel_de_posting_read(dev_priv, reg);
5497
5498         reg = FDI_RX_CTL(pipe);
5499         temp = intel_de_read(dev_priv, reg);
5500         temp &= ~(0x7 << 16);
5501         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5502         intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5503
5504         intel_de_posting_read(dev_priv, reg);
5505         udelay(100);
5506
5507         /* Ironlake workaround, disable clock pointer after downing FDI */
5508         if (HAS_PCH_IBX(dev_priv))
5509                 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5510                                FDI_RX_PHASE_SYNC_POINTER_OVR);
5511
5512         /* still set train pattern 1 */
5513         reg = FDI_TX_CTL(pipe);
5514         temp = intel_de_read(dev_priv, reg);
5515         temp &= ~FDI_LINK_TRAIN_NONE;
5516         temp |= FDI_LINK_TRAIN_PATTERN_1;
5517         intel_de_write(dev_priv, reg, temp);
5518
5519         reg = FDI_RX_CTL(pipe);
5520         temp = intel_de_read(dev_priv, reg);
5521         if (HAS_PCH_CPT(dev_priv)) {
5522                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5523                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5524         } else {
5525                 temp &= ~FDI_LINK_TRAIN_NONE;
5526                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5527         }
5528         /* BPC in FDI rx is consistent with that in PIPECONF */
5529         temp &= ~(0x07 << 16);
5530         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5531         intel_de_write(dev_priv, reg, temp);
5532
5533         intel_de_posting_read(dev_priv, reg);
5534         udelay(100);
5535 }
5536
5537 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5538 {
5539         struct drm_crtc *crtc;
5540         bool cleanup_done;
5541
5542         drm_for_each_crtc(crtc, &dev_priv->drm) {
5543                 struct drm_crtc_commit *commit;
5544                 spin_lock(&crtc->commit_lock);
5545                 commit = list_first_entry_or_null(&crtc->commit_list,
5546                                                   struct drm_crtc_commit, commit_entry);
5547                 cleanup_done = commit ?
5548                         try_wait_for_completion(&commit->cleanup_done) : true;
5549                 spin_unlock(&crtc->commit_lock);
5550
5551                 if (cleanup_done)
5552                         continue;
5553
5554                 drm_crtc_wait_one_vblank(crtc);
5555
5556                 return true;
5557         }
5558
5559         return false;
5560 }
5561
5562 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5563 {
5564         u32 temp;
5565
5566         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5567
5568         mutex_lock(&dev_priv->sb_lock);
5569
5570         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5571         temp |= SBI_SSCCTL_DISABLE;
5572         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5573
5574         mutex_unlock(&dev_priv->sb_lock);
5575 }
5576
5577 /* Program iCLKIP clock to the desired frequency */
5578 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5579 {
5580         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5581         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5582         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5583         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5584         u32 temp;
5585
5586         lpt_disable_iclkip(dev_priv);
5587
5588         /* The iCLK virtual clock root frequency is in MHz,
5589          * but the adjusted_mode->crtc_clock in in KHz. To get the
5590          * divisors, it is necessary to divide one by another, so we
5591          * convert the virtual clock precision to KHz here for higher
5592          * precision.
5593          */
5594         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5595                 u32 iclk_virtual_root_freq = 172800 * 1000;
5596                 u32 iclk_pi_range = 64;
5597                 u32 desired_divisor;
5598
5599                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5600                                                     clock << auxdiv);
5601                 divsel = (desired_divisor / iclk_pi_range) - 2;
5602                 phaseinc = desired_divisor % iclk_pi_range;
5603
5604                 /*
5605                  * Near 20MHz is a corner case which is
5606                  * out of range for the 7-bit divisor
5607                  */
5608                 if (divsel <= 0x7f)
5609                         break;
5610         }
5611
5612         /* This should not happen with any sane values */
5613         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5614                     ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5615         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5616                     ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5617
5618         drm_dbg_kms(&dev_priv->drm,
5619                     "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5620                     clock, auxdiv, divsel, phasedir, phaseinc);
5621
5622         mutex_lock(&dev_priv->sb_lock);
5623
5624         /* Program SSCDIVINTPHASE6 */
5625         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5626         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5627         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5628         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5629         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5630         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5631         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5632         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5633
5634         /* Program SSCAUXDIV */
5635         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5636         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5637         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5638         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5639
5640         /* Enable modulator and associated divider */
5641         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5642         temp &= ~SBI_SSCCTL_DISABLE;
5643         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5644
5645         mutex_unlock(&dev_priv->sb_lock);
5646
5647         /* Wait for initialization time */
5648         udelay(24);
5649
5650         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5651 }
5652
5653 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5654 {
5655         u32 divsel, phaseinc, auxdiv;
5656         u32 iclk_virtual_root_freq = 172800 * 1000;
5657         u32 iclk_pi_range = 64;
5658         u32 desired_divisor;
5659         u32 temp;
5660
5661         if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5662                 return 0;
5663
5664         mutex_lock(&dev_priv->sb_lock);
5665
5666         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5667         if (temp & SBI_SSCCTL_DISABLE) {
5668                 mutex_unlock(&dev_priv->sb_lock);
5669                 return 0;
5670         }
5671
5672         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5673         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5674                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5675         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5676                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5677
5678         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5679         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5680                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5681
5682         mutex_unlock(&dev_priv->sb_lock);
5683
5684         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5685
5686         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5687                                  desired_divisor << auxdiv);
5688 }
5689
5690 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5691                                            enum pipe pch_transcoder)
5692 {
5693         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5694         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5695         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5696
5697         intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5698                        intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5699         intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5700                        intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5701         intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5702                        intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5703
5704         intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5705                        intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5706         intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5707                        intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5708         intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5709                        intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5710         intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5711                        intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5712 }
5713
5714 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5715 {
5716         u32 temp;
5717
5718         temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5719         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5720                 return;
5721
5722         drm_WARN_ON(&dev_priv->drm,
5723                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5724                     FDI_RX_ENABLE);
5725         drm_WARN_ON(&dev_priv->drm,
5726                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5727                     FDI_RX_ENABLE);
5728
5729         temp &= ~FDI_BC_BIFURCATION_SELECT;
5730         if (enable)
5731                 temp |= FDI_BC_BIFURCATION_SELECT;
5732
5733         drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5734                     enable ? "en" : "dis");
5735         intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5736         intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5737 }
5738
5739 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5740 {
5741         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5742         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5743
5744         switch (crtc->pipe) {
5745         case PIPE_A:
5746                 break;
5747         case PIPE_B:
5748                 if (crtc_state->fdi_lanes > 2)
5749                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5750                 else
5751                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5752
5753                 break;
5754         case PIPE_C:
5755                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5756
5757                 break;
5758         default:
5759                 BUG();
5760         }
5761 }
5762
5763 /*
5764  * Finds the encoder associated with the given CRTC. This can only be
5765  * used when we know that the CRTC isn't feeding multiple encoders!
5766  */
5767 static struct intel_encoder *
5768 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5769                            const struct intel_crtc_state *crtc_state)
5770 {
5771         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5772         const struct drm_connector_state *connector_state;
5773         const struct drm_connector *connector;
5774         struct intel_encoder *encoder = NULL;
5775         int num_encoders = 0;
5776         int i;
5777
5778         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5779                 if (connector_state->crtc != &crtc->base)
5780                         continue;
5781
5782                 encoder = to_intel_encoder(connector_state->best_encoder);
5783                 num_encoders++;
5784         }
5785
5786         drm_WARN(encoder->base.dev, num_encoders != 1,
5787                  "%d encoders for pipe %c\n",
5788                  num_encoders, pipe_name(crtc->pipe));
5789
5790         return encoder;
5791 }
5792
5793 /*
5794  * Enable PCH resources required for PCH ports:
5795  *   - PCH PLLs
5796  *   - FDI training & RX/TX
5797  *   - update transcoder timings
5798  *   - DP transcoding bits
5799  *   - transcoder
5800  */
5801 static void ilk_pch_enable(const struct intel_atomic_state *state,
5802                            const struct intel_crtc_state *crtc_state)
5803 {
5804         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5805         struct drm_device *dev = crtc->base.dev;
5806         struct drm_i915_private *dev_priv = to_i915(dev);
5807         enum pipe pipe = crtc->pipe;
5808         u32 temp;
5809
5810         assert_pch_transcoder_disabled(dev_priv, pipe);
5811
5812         if (IS_IVYBRIDGE(dev_priv))
5813                 ivb_update_fdi_bc_bifurcation(crtc_state);
5814
5815         /* Write the TU size bits before fdi link training, so that error
5816          * detection works. */
5817         intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5818                        intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5819
5820         /* For PCH output, training FDI link */
5821         dev_priv->display.fdi_link_train(crtc, crtc_state);
5822
5823         /* We need to program the right clock selection before writing the pixel
5824          * mutliplier into the DPLL. */
5825         if (HAS_PCH_CPT(dev_priv)) {
5826                 u32 sel;
5827
5828                 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5829                 temp |= TRANS_DPLL_ENABLE(pipe);
5830                 sel = TRANS_DPLLB_SEL(pipe);
5831                 if (crtc_state->shared_dpll ==
5832                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5833                         temp |= sel;
5834                 else
5835                         temp &= ~sel;
5836                 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5837         }
5838
5839         /* XXX: pch pll's can be enabled any time before we enable the PCH
5840          * transcoder, and we actually should do this to not upset any PCH
5841          * transcoder that already use the clock when we share it.
5842          *
5843          * Note that enable_shared_dpll tries to do the right thing, but
5844          * get_shared_dpll unconditionally resets the pll - we need that to have
5845          * the right LVDS enable sequence. */
5846         intel_enable_shared_dpll(crtc_state);
5847
5848         /* set transcoder timing, panel must allow it */
5849         assert_panel_unlocked(dev_priv, pipe);
5850         ilk_pch_transcoder_set_timings(crtc_state, pipe);
5851
5852         intel_fdi_normal_train(crtc);
5853
5854         /* For PCH DP, enable TRANS_DP_CTL */
5855         if (HAS_PCH_CPT(dev_priv) &&
5856             intel_crtc_has_dp_encoder(crtc_state)) {
5857                 const struct drm_display_mode *adjusted_mode =
5858                         &crtc_state->hw.adjusted_mode;
5859                 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5860                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5861                 enum port port;
5862
5863                 temp = intel_de_read(dev_priv, reg);
5864                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5865                           TRANS_DP_SYNC_MASK |
5866                           TRANS_DP_BPC_MASK);
5867                 temp |= TRANS_DP_OUTPUT_ENABLE;
5868                 temp |= bpc << 9; /* same format but at 11:9 */
5869
5870                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5871                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5872                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5873                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5874
5875                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5876                 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5877                 temp |= TRANS_DP_PORT_SEL(port);
5878
5879                 intel_de_write(dev_priv, reg, temp);
5880         }
5881
5882         ilk_enable_pch_transcoder(crtc_state);
5883 }
5884
5885 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5886 {
5887         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5888         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5889         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5890
5891         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5892
5893         lpt_program_iclkip(crtc_state);
5894
5895         /* Set transcoder timing. */
5896         ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5897
5898         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5899 }
5900
5901 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5902                                enum pipe pipe)
5903 {
5904         i915_reg_t dslreg = PIPEDSL(pipe);
5905         u32 temp;
5906
5907         temp = intel_de_read(dev_priv, dslreg);
5908         udelay(500);
5909         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5910                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5911                         drm_err(&dev_priv->drm,
5912                                 "mode set failed: pipe %c stuck\n",
5913                                 pipe_name(pipe));
5914         }
5915 }
5916
5917 /*
5918  * The hardware phase 0.0 refers to the center of the pixel.
5919  * We want to start from the top/left edge which is phase
5920  * -0.5. That matches how the hardware calculates the scaling
5921  * factors (from top-left of the first pixel to bottom-right
5922  * of the last pixel, as opposed to the pixel centers).
5923  *
5924  * For 4:2:0 subsampled chroma planes we obviously have to
5925  * adjust that so that the chroma sample position lands in
5926  * the right spot.
5927  *
5928  * Note that for packed YCbCr 4:2:2 formats there is no way to
5929  * control chroma siting. The hardware simply replicates the
5930  * chroma samples for both of the luma samples, and thus we don't
5931  * actually get the expected MPEG2 chroma siting convention :(
5932  * The same behaviour is observed on pre-SKL platforms as well.
5933  *
5934  * Theory behind the formula (note that we ignore sub-pixel
5935  * source coordinates):
5936  * s = source sample position
5937  * d = destination sample position
5938  *
5939  * Downscaling 4:1:
5940  * -0.5
5941  * | 0.0
5942  * | |     1.5 (initial phase)
5943  * | |     |
5944  * v v     v
5945  * | s | s | s | s |
5946  * |       d       |
5947  *
5948  * Upscaling 1:4:
5949  * -0.5
5950  * | -0.375 (initial phase)
5951  * | |     0.0
5952  * | |     |
5953  * v v     v
5954  * |       s       |
5955  * | d | d | d | d |
5956  */
5957 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5958 {
5959         int phase = -0x8000;
5960         u16 trip = 0;
5961
5962         if (chroma_cosited)
5963                 phase += (sub - 1) * 0x8000 / sub;
5964
5965         phase += scale / (2 * sub);
5966
5967         /*
5968          * Hardware initial phase limited to [-0.5:1.5].
5969          * Since the max hardware scale factor is 3.0, we
5970          * should never actually excdeed 1.0 here.
5971          */
5972         WARN_ON(phase < -0x8000 || phase > 0x18000);
5973
5974         if (phase < 0)
5975                 phase = 0x10000 + phase;
5976         else
5977                 trip = PS_PHASE_TRIP;
5978
5979         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5980 }
5981
5982 #define SKL_MIN_SRC_W 8
5983 #define SKL_MAX_SRC_W 4096
5984 #define SKL_MIN_SRC_H 8
5985 #define SKL_MAX_SRC_H 4096
5986 #define SKL_MIN_DST_W 8
5987 #define SKL_MAX_DST_W 4096
5988 #define SKL_MIN_DST_H 8
5989 #define SKL_MAX_DST_H 4096
5990 #define ICL_MAX_SRC_W 5120
5991 #define ICL_MAX_SRC_H 4096
5992 #define ICL_MAX_DST_W 5120
5993 #define ICL_MAX_DST_H 4096
5994 #define SKL_MIN_YUV_420_SRC_W 16
5995 #define SKL_MIN_YUV_420_SRC_H 16
5996
5997 static int
5998 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5999                   unsigned int scaler_user, int *scaler_id,
6000                   int src_w, int src_h, int dst_w, int dst_h,
6001                   const struct drm_format_info *format,
6002                   u64 modifier, bool need_scaler)
6003 {
6004         struct intel_crtc_scaler_state *scaler_state =
6005                 &crtc_state->scaler_state;
6006         struct intel_crtc *intel_crtc =
6007                 to_intel_crtc(crtc_state->uapi.crtc);
6008         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6009         const struct drm_display_mode *adjusted_mode =
6010                 &crtc_state->hw.adjusted_mode;
6011
6012         /*
6013          * Src coordinates are already rotated by 270 degrees for
6014          * the 90/270 degree plane rotation cases (to match the
6015          * GTT mapping), hence no need to account for rotation here.
6016          */
6017         if (src_w != dst_w || src_h != dst_h)
6018                 need_scaler = true;
6019
6020         /*
6021          * Scaling/fitting not supported in IF-ID mode in GEN9+
6022          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6023          * Once NV12 is enabled, handle it here while allocating scaler
6024          * for NV12.
6025          */
6026         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6027             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6028                 drm_dbg_kms(&dev_priv->drm,
6029                             "Pipe/Plane scaling not supported with IF-ID mode\n");
6030                 return -EINVAL;
6031         }
6032
6033         /*
6034          * if plane is being disabled or scaler is no more required or force detach
6035          *  - free scaler binded to this plane/crtc
6036          *  - in order to do this, update crtc->scaler_usage
6037          *
6038          * Here scaler state in crtc_state is set free so that
6039          * scaler can be assigned to other user. Actual register
6040          * update to free the scaler is done in plane/panel-fit programming.
6041          * For this purpose crtc/plane_state->scaler_id isn't reset here.
6042          */
6043         if (force_detach || !need_scaler) {
6044                 if (*scaler_id >= 0) {
6045                         scaler_state->scaler_users &= ~(1 << scaler_user);
6046                         scaler_state->scalers[*scaler_id].in_use = 0;
6047
6048                         drm_dbg_kms(&dev_priv->drm,
6049                                     "scaler_user index %u.%u: "
6050                                     "Staged freeing scaler id %d scaler_users = 0x%x\n",
6051                                     intel_crtc->pipe, scaler_user, *scaler_id,
6052                                     scaler_state->scaler_users);
6053                         *scaler_id = -1;
6054                 }
6055                 return 0;
6056         }
6057
6058         if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6059             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6060                 drm_dbg_kms(&dev_priv->drm,
6061                             "Planar YUV: src dimensions not met\n");
6062                 return -EINVAL;
6063         }
6064
6065         /* range checks */
6066         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6067             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6068             (INTEL_GEN(dev_priv) >= 11 &&
6069              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6070               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6071             (INTEL_GEN(dev_priv) < 11 &&
6072              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6073               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6074                 drm_dbg_kms(&dev_priv->drm,
6075                             "scaler_user index %u.%u: src %ux%u dst %ux%u "
6076                             "size is out of scaler range\n",
6077                             intel_crtc->pipe, scaler_user, src_w, src_h,
6078                             dst_w, dst_h);
6079                 return -EINVAL;
6080         }
6081
6082         /* mark this plane as a scaler user in crtc_state */
6083         scaler_state->scaler_users |= (1 << scaler_user);
6084         drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6085                     "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6086                     intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6087                     scaler_state->scaler_users);
6088
6089         return 0;
6090 }
6091
6092 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6093 {
6094         const struct drm_display_mode *adjusted_mode =
6095                 &crtc_state->hw.adjusted_mode;
6096         int width, height;
6097
6098         if (crtc_state->pch_pfit.enabled) {
6099                 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6100                 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6101         } else {
6102                 width = adjusted_mode->crtc_hdisplay;
6103                 height = adjusted_mode->crtc_vdisplay;
6104         }
6105
6106         return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6107                                  SKL_CRTC_INDEX,
6108                                  &crtc_state->scaler_state.scaler_id,
6109                                  crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6110                                  width, height, NULL, 0,
6111                                  crtc_state->pch_pfit.enabled);
6112 }
6113
6114 /**
6115  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6116  * @crtc_state: crtc's scaler state
6117  * @plane_state: atomic plane state to update
6118  *
6119  * Return
6120  *     0 - scaler_usage updated successfully
6121  *    error - requested scaling cannot be supported or other error condition
6122  */
6123 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6124                                    struct intel_plane_state *plane_state)
6125 {
6126         struct intel_plane *intel_plane =
6127                 to_intel_plane(plane_state->uapi.plane);
6128         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6129         struct drm_framebuffer *fb = plane_state->hw.fb;
6130         int ret;
6131         bool force_detach = !fb || !plane_state->uapi.visible;
6132         bool need_scaler = false;
6133
6134         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6135         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6136             fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6137                 need_scaler = true;
6138
6139         ret = skl_update_scaler(crtc_state, force_detach,
6140                                 drm_plane_index(&intel_plane->base),
6141                                 &plane_state->scaler_id,
6142                                 drm_rect_width(&plane_state->uapi.src) >> 16,
6143                                 drm_rect_height(&plane_state->uapi.src) >> 16,
6144                                 drm_rect_width(&plane_state->uapi.dst),
6145                                 drm_rect_height(&plane_state->uapi.dst),
6146                                 fb ? fb->format : NULL,
6147                                 fb ? fb->modifier : 0,
6148                                 need_scaler);
6149
6150         if (ret || plane_state->scaler_id < 0)
6151                 return ret;
6152
6153         /* check colorkey */
6154         if (plane_state->ckey.flags) {
6155                 drm_dbg_kms(&dev_priv->drm,
6156                             "[PLANE:%d:%s] scaling with color key not allowed",
6157                             intel_plane->base.base.id,
6158                             intel_plane->base.name);
6159                 return -EINVAL;
6160         }
6161
6162         /* Check src format */
6163         switch (fb->format->format) {
6164         case DRM_FORMAT_RGB565:
6165         case DRM_FORMAT_XBGR8888:
6166         case DRM_FORMAT_XRGB8888:
6167         case DRM_FORMAT_ABGR8888:
6168         case DRM_FORMAT_ARGB8888:
6169         case DRM_FORMAT_XRGB2101010:
6170         case DRM_FORMAT_XBGR2101010:
6171         case DRM_FORMAT_ARGB2101010:
6172         case DRM_FORMAT_ABGR2101010:
6173         case DRM_FORMAT_YUYV:
6174         case DRM_FORMAT_YVYU:
6175         case DRM_FORMAT_UYVY:
6176         case DRM_FORMAT_VYUY:
6177         case DRM_FORMAT_NV12:
6178         case DRM_FORMAT_XYUV8888:
6179         case DRM_FORMAT_P010:
6180         case DRM_FORMAT_P012:
6181         case DRM_FORMAT_P016:
6182         case DRM_FORMAT_Y210:
6183         case DRM_FORMAT_Y212:
6184         case DRM_FORMAT_Y216:
6185         case DRM_FORMAT_XVYU2101010:
6186         case DRM_FORMAT_XVYU12_16161616:
6187         case DRM_FORMAT_XVYU16161616:
6188                 break;
6189         case DRM_FORMAT_XBGR16161616F:
6190         case DRM_FORMAT_ABGR16161616F:
6191         case DRM_FORMAT_XRGB16161616F:
6192         case DRM_FORMAT_ARGB16161616F:
6193                 if (INTEL_GEN(dev_priv) >= 11)
6194                         break;
6195                 /* fall through */
6196         default:
6197                 drm_dbg_kms(&dev_priv->drm,
6198                             "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6199                             intel_plane->base.base.id, intel_plane->base.name,
6200                             fb->base.id, fb->format->format);
6201                 return -EINVAL;
6202         }
6203
6204         return 0;
6205 }
6206
6207 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6208 {
6209         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6210         int i;
6211
6212         for (i = 0; i < crtc->num_scalers; i++)
6213                 skl_detach_scaler(crtc, i);
6214 }
6215
6216 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6217 {
6218         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6219         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6220         const struct intel_crtc_scaler_state *scaler_state =
6221                 &crtc_state->scaler_state;
6222         struct drm_rect src = {
6223                 .x2 = crtc_state->pipe_src_w << 16,
6224                 .y2 = crtc_state->pipe_src_h << 16,
6225         };
6226         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6227         u16 uv_rgb_hphase, uv_rgb_vphase;
6228         enum pipe pipe = crtc->pipe;
6229         int width = drm_rect_width(dst);
6230         int height = drm_rect_height(dst);
6231         int x = dst->x1;
6232         int y = dst->y1;
6233         int hscale, vscale;
6234         unsigned long irqflags;
6235         int id;
6236
6237         if (!crtc_state->pch_pfit.enabled)
6238                 return;
6239
6240         if (drm_WARN_ON(&dev_priv->drm,
6241                         crtc_state->scaler_state.scaler_id < 0))
6242                 return;
6243
6244         hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6245         vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6246
6247         uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6248         uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6249
6250         id = scaler_state->scaler_id;
6251
6252         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6253
6254         intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6255                           PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6256         intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6257                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6258         intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6259                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6260         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6261                           x << 16 | y);
6262         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6263                           width << 16 | height);
6264
6265         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6266 }
6267
6268 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6269 {
6270         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6271         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6272         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6273         enum pipe pipe = crtc->pipe;
6274         int width = drm_rect_width(dst);
6275         int height = drm_rect_height(dst);
6276         int x = dst->x1;
6277         int y = dst->y1;
6278
6279         if (!crtc_state->pch_pfit.enabled)
6280                 return;
6281
6282         /* Force use of hard-coded filter coefficients
6283          * as some pre-programmed values are broken,
6284          * e.g. x201.
6285          */
6286         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6287                 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6288                                PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6289         else
6290                 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6291                                PF_FILTER_MED_3x3);
6292         intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6293         intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6294 }
6295
6296 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6297 {
6298         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6299         struct drm_device *dev = crtc->base.dev;
6300         struct drm_i915_private *dev_priv = to_i915(dev);
6301
6302         if (!crtc_state->ips_enabled)
6303                 return;
6304
6305         /*
6306          * We can only enable IPS after we enable a plane and wait for a vblank
6307          * This function is called from post_plane_update, which is run after
6308          * a vblank wait.
6309          */
6310         drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6311
6312         if (IS_BROADWELL(dev_priv)) {
6313                 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6314                                                          IPS_ENABLE | IPS_PCODE_CONTROL));
6315                 /* Quoting Art Runyan: "its not safe to expect any particular
6316                  * value in IPS_CTL bit 31 after enabling IPS through the
6317                  * mailbox." Moreover, the mailbox may return a bogus state,
6318                  * so we need to just enable it and continue on.
6319                  */
6320         } else {
6321                 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6322                 /* The bit only becomes 1 in the next vblank, so this wait here
6323                  * is essentially intel_wait_for_vblank. If we don't have this
6324                  * and don't wait for vblanks until the end of crtc_enable, then
6325                  * the HW state readout code will complain that the expected
6326                  * IPS_CTL value is not the one we read. */
6327                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6328                         drm_err(&dev_priv->drm,
6329                                 "Timed out waiting for IPS enable\n");
6330         }
6331 }
6332
6333 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6334 {
6335         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6336         struct drm_device *dev = crtc->base.dev;
6337         struct drm_i915_private *dev_priv = to_i915(dev);
6338
6339         if (!crtc_state->ips_enabled)
6340                 return;
6341
6342         if (IS_BROADWELL(dev_priv)) {
6343                 drm_WARN_ON(dev,
6344                             sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6345                 /*
6346                  * Wait for PCODE to finish disabling IPS. The BSpec specified
6347                  * 42ms timeout value leads to occasional timeouts so use 100ms
6348                  * instead.
6349                  */
6350                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6351                         drm_err(&dev_priv->drm,
6352                                 "Timed out waiting for IPS disable\n");
6353         } else {
6354                 intel_de_write(dev_priv, IPS_CTL, 0);
6355                 intel_de_posting_read(dev_priv, IPS_CTL);
6356         }
6357
6358         /* We need to wait for a vblank before we can disable the plane. */
6359         intel_wait_for_vblank(dev_priv, crtc->pipe);
6360 }
6361
6362 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6363 {
6364         if (intel_crtc->overlay)
6365                 (void) intel_overlay_switch_off(intel_crtc->overlay);
6366
6367         /* Let userspace switch the overlay on again. In most cases userspace
6368          * has to recompute where to put it anyway.
6369          */
6370 }
6371
6372 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6373                                        const struct intel_crtc_state *new_crtc_state)
6374 {
6375         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6376         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6377
6378         if (!old_crtc_state->ips_enabled)
6379                 return false;
6380
6381         if (needs_modeset(new_crtc_state))
6382                 return true;
6383
6384         /*
6385          * Workaround : Do not read or write the pipe palette/gamma data while
6386          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6387          *
6388          * Disable IPS before we program the LUT.
6389          */
6390         if (IS_HASWELL(dev_priv) &&
6391             (new_crtc_state->uapi.color_mgmt_changed ||
6392              new_crtc_state->update_pipe) &&
6393             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6394                 return true;
6395
6396         return !new_crtc_state->ips_enabled;
6397 }
6398
6399 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6400                                        const struct intel_crtc_state *new_crtc_state)
6401 {
6402         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6403         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6404
6405         if (!new_crtc_state->ips_enabled)
6406                 return false;
6407
6408         if (needs_modeset(new_crtc_state))
6409                 return true;
6410
6411         /*
6412          * Workaround : Do not read or write the pipe palette/gamma data while
6413          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6414          *
6415          * Re-enable IPS after the LUT has been programmed.
6416          */
6417         if (IS_HASWELL(dev_priv) &&
6418             (new_crtc_state->uapi.color_mgmt_changed ||
6419              new_crtc_state->update_pipe) &&
6420             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6421                 return true;
6422
6423         /*
6424          * We can't read out IPS on broadwell, assume the worst and
6425          * forcibly enable IPS on the first fastset.
6426          */
6427         if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6428                 return true;
6429
6430         return !old_crtc_state->ips_enabled;
6431 }
6432
6433 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6434 {
6435         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6436
6437         if (!crtc_state->nv12_planes)
6438                 return false;
6439
6440         /* WA Display #0827: Gen9:all */
6441         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6442                 return true;
6443
6444         return false;
6445 }
6446
6447 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6448 {
6449         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6450
6451         /* Wa_2006604312:icl,ehl */
6452         if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6453                 return true;
6454
6455         return false;
6456 }
6457
6458 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6459                             const struct intel_crtc_state *new_crtc_state)
6460 {
6461         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6462                 new_crtc_state->active_planes;
6463 }
6464
6465 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6466                              const struct intel_crtc_state *new_crtc_state)
6467 {
6468         return old_crtc_state->active_planes &&
6469                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6470 }
6471
6472 static void intel_post_plane_update(struct intel_atomic_state *state,
6473                                     struct intel_crtc *crtc)
6474 {
6475         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6476         const struct intel_crtc_state *old_crtc_state =
6477                 intel_atomic_get_old_crtc_state(state, crtc);
6478         const struct intel_crtc_state *new_crtc_state =
6479                 intel_atomic_get_new_crtc_state(state, crtc);
6480         enum pipe pipe = crtc->pipe;
6481
6482         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6483
6484         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6485                 intel_update_watermarks(crtc);
6486
6487         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6488                 hsw_enable_ips(new_crtc_state);
6489
6490         intel_fbc_post_update(state, crtc);
6491
6492         if (needs_nv12_wa(old_crtc_state) &&
6493             !needs_nv12_wa(new_crtc_state))
6494                 skl_wa_827(dev_priv, pipe, false);
6495
6496         if (needs_scalerclk_wa(old_crtc_state) &&
6497             !needs_scalerclk_wa(new_crtc_state))
6498                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6499 }
6500
6501 static void intel_pre_plane_update(struct intel_atomic_state *state,
6502                                    struct intel_crtc *crtc)
6503 {
6504         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6505         const struct intel_crtc_state *old_crtc_state =
6506                 intel_atomic_get_old_crtc_state(state, crtc);
6507         const struct intel_crtc_state *new_crtc_state =
6508                 intel_atomic_get_new_crtc_state(state, crtc);
6509         enum pipe pipe = crtc->pipe;
6510
6511         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6512                 hsw_disable_ips(old_crtc_state);
6513
6514         if (intel_fbc_pre_update(state, crtc))
6515                 intel_wait_for_vblank(dev_priv, pipe);
6516
6517         /* Display WA 827 */
6518         if (!needs_nv12_wa(old_crtc_state) &&
6519             needs_nv12_wa(new_crtc_state))
6520                 skl_wa_827(dev_priv, pipe, true);
6521
6522         /* Wa_2006604312:icl,ehl */
6523         if (!needs_scalerclk_wa(old_crtc_state) &&
6524             needs_scalerclk_wa(new_crtc_state))
6525                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6526
6527         /*
6528          * Vblank time updates from the shadow to live plane control register
6529          * are blocked if the memory self-refresh mode is active at that
6530          * moment. So to make sure the plane gets truly disabled, disable
6531          * first the self-refresh mode. The self-refresh enable bit in turn
6532          * will be checked/applied by the HW only at the next frame start
6533          * event which is after the vblank start event, so we need to have a
6534          * wait-for-vblank between disabling the plane and the pipe.
6535          */
6536         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6537             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6538                 intel_wait_for_vblank(dev_priv, pipe);
6539
6540         /*
6541          * IVB workaround: must disable low power watermarks for at least
6542          * one frame before enabling scaling.  LP watermarks can be re-enabled
6543          * when scaling is disabled.
6544          *
6545          * WaCxSRDisabledForSpriteScaling:ivb
6546          */
6547         if (old_crtc_state->hw.active &&
6548             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6549                 intel_wait_for_vblank(dev_priv, pipe);
6550
6551         /*
6552          * If we're doing a modeset we don't need to do any
6553          * pre-vblank watermark programming here.
6554          */
6555         if (!needs_modeset(new_crtc_state)) {
6556                 /*
6557                  * For platforms that support atomic watermarks, program the
6558                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6559                  * will be the intermediate values that are safe for both pre- and
6560                  * post- vblank; when vblank happens, the 'active' values will be set
6561                  * to the final 'target' values and we'll do this again to get the
6562                  * optimal watermarks.  For gen9+ platforms, the values we program here
6563                  * will be the final target values which will get automatically latched
6564                  * at vblank time; no further programming will be necessary.
6565                  *
6566                  * If a platform hasn't been transitioned to atomic watermarks yet,
6567                  * we'll continue to update watermarks the old way, if flags tell
6568                  * us to.
6569                  */
6570                 if (dev_priv->display.initial_watermarks)
6571                         dev_priv->display.initial_watermarks(state, crtc);
6572                 else if (new_crtc_state->update_wm_pre)
6573                         intel_update_watermarks(crtc);
6574         }
6575
6576         /*
6577          * Gen2 reports pipe underruns whenever all planes are disabled.
6578          * So disable underrun reporting before all the planes get disabled.
6579          *
6580          * We do this after .initial_watermarks() so that we have a
6581          * chance of catching underruns with the intermediate watermarks
6582          * vs. the old plane configuration.
6583          */
6584         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6585                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6586 }
6587
6588 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6589                                       struct intel_crtc *crtc)
6590 {
6591         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6592         const struct intel_crtc_state *new_crtc_state =
6593                 intel_atomic_get_new_crtc_state(state, crtc);
6594         unsigned int update_mask = new_crtc_state->update_planes;
6595         const struct intel_plane_state *old_plane_state;
6596         struct intel_plane *plane;
6597         unsigned fb_bits = 0;
6598         int i;
6599
6600         intel_crtc_dpms_overlay_disable(crtc);
6601
6602         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6603                 if (crtc->pipe != plane->pipe ||
6604                     !(update_mask & BIT(plane->id)))
6605                         continue;
6606
6607                 intel_disable_plane(plane, new_crtc_state);
6608
6609                 if (old_plane_state->uapi.visible)
6610                         fb_bits |= plane->frontbuffer_bit;
6611         }
6612
6613         intel_frontbuffer_flip(dev_priv, fb_bits);
6614 }
6615
6616 /*
6617  * intel_connector_primary_encoder - get the primary encoder for a connector
6618  * @connector: connector for which to return the encoder
6619  *
6620  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6621  * all connectors to their encoder, except for DP-MST connectors which have
6622  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6623  * pointed to by as many DP-MST connectors as there are pipes.
6624  */
6625 static struct intel_encoder *
6626 intel_connector_primary_encoder(struct intel_connector *connector)
6627 {
6628         struct intel_encoder *encoder;
6629
6630         if (connector->mst_port)
6631                 return &dp_to_dig_port(connector->mst_port)->base;
6632
6633         encoder = intel_attached_encoder(connector);
6634         drm_WARN_ON(connector->base.dev, !encoder);
6635
6636         return encoder;
6637 }
6638
6639 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6640 {
6641         struct drm_connector_state *new_conn_state;
6642         struct drm_connector *connector;
6643         int i;
6644
6645         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6646                                         i) {
6647                 struct intel_connector *intel_connector;
6648                 struct intel_encoder *encoder;
6649                 struct intel_crtc *crtc;
6650
6651                 if (!intel_connector_needs_modeset(state, connector))
6652                         continue;
6653
6654                 intel_connector = to_intel_connector(connector);
6655                 encoder = intel_connector_primary_encoder(intel_connector);
6656                 if (!encoder->update_prepare)
6657                         continue;
6658
6659                 crtc = new_conn_state->crtc ?
6660                         to_intel_crtc(new_conn_state->crtc) : NULL;
6661                 encoder->update_prepare(state, encoder, crtc);
6662         }
6663 }
6664
6665 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6666 {
6667         struct drm_connector_state *new_conn_state;
6668         struct drm_connector *connector;
6669         int i;
6670
6671         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6672                                         i) {
6673                 struct intel_connector *intel_connector;
6674                 struct intel_encoder *encoder;
6675                 struct intel_crtc *crtc;
6676
6677                 if (!intel_connector_needs_modeset(state, connector))
6678                         continue;
6679
6680                 intel_connector = to_intel_connector(connector);
6681                 encoder = intel_connector_primary_encoder(intel_connector);
6682                 if (!encoder->update_complete)
6683                         continue;
6684
6685                 crtc = new_conn_state->crtc ?
6686                         to_intel_crtc(new_conn_state->crtc) : NULL;
6687                 encoder->update_complete(state, encoder, crtc);
6688         }
6689 }
6690
6691 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6692                                           struct intel_crtc *crtc)
6693 {
6694         const struct intel_crtc_state *crtc_state =
6695                 intel_atomic_get_new_crtc_state(state, crtc);
6696         const struct drm_connector_state *conn_state;
6697         struct drm_connector *conn;
6698         int i;
6699
6700         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6701                 struct intel_encoder *encoder =
6702                         to_intel_encoder(conn_state->best_encoder);
6703
6704                 if (conn_state->crtc != &crtc->base)
6705                         continue;
6706
6707                 if (encoder->pre_pll_enable)
6708                         encoder->pre_pll_enable(state, encoder,
6709                                                 crtc_state, conn_state);
6710         }
6711 }
6712
6713 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6714                                       struct intel_crtc *crtc)
6715 {
6716         const struct intel_crtc_state *crtc_state =
6717                 intel_atomic_get_new_crtc_state(state, crtc);
6718         const struct drm_connector_state *conn_state;
6719         struct drm_connector *conn;
6720         int i;
6721
6722         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6723                 struct intel_encoder *encoder =
6724                         to_intel_encoder(conn_state->best_encoder);
6725
6726                 if (conn_state->crtc != &crtc->base)
6727                         continue;
6728
6729                 if (encoder->pre_enable)
6730                         encoder->pre_enable(state, encoder,
6731                                             crtc_state, conn_state);
6732         }
6733 }
6734
6735 static void intel_encoders_enable(struct intel_atomic_state *state,
6736                                   struct intel_crtc *crtc)
6737 {
6738         const struct intel_crtc_state *crtc_state =
6739                 intel_atomic_get_new_crtc_state(state, crtc);
6740         const struct drm_connector_state *conn_state;
6741         struct drm_connector *conn;
6742         int i;
6743
6744         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6745                 struct intel_encoder *encoder =
6746                         to_intel_encoder(conn_state->best_encoder);
6747
6748                 if (conn_state->crtc != &crtc->base)
6749                         continue;
6750
6751                 if (encoder->enable)
6752                         encoder->enable(state, encoder,
6753                                         crtc_state, conn_state);
6754                 intel_opregion_notify_encoder(encoder, true);
6755         }
6756 }
6757
6758 static void intel_encoders_disable(struct intel_atomic_state *state,
6759                                    struct intel_crtc *crtc)
6760 {
6761         const struct intel_crtc_state *old_crtc_state =
6762                 intel_atomic_get_old_crtc_state(state, crtc);
6763         const struct drm_connector_state *old_conn_state;
6764         struct drm_connector *conn;
6765         int i;
6766
6767         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6768                 struct intel_encoder *encoder =
6769                         to_intel_encoder(old_conn_state->best_encoder);
6770
6771                 if (old_conn_state->crtc != &crtc->base)
6772                         continue;
6773
6774                 intel_opregion_notify_encoder(encoder, false);
6775                 if (encoder->disable)
6776                         encoder->disable(state, encoder,
6777                                          old_crtc_state, old_conn_state);
6778         }
6779 }
6780
6781 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6782                                         struct intel_crtc *crtc)
6783 {
6784         const struct intel_crtc_state *old_crtc_state =
6785                 intel_atomic_get_old_crtc_state(state, crtc);
6786         const struct drm_connector_state *old_conn_state;
6787         struct drm_connector *conn;
6788         int i;
6789
6790         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6791                 struct intel_encoder *encoder =
6792                         to_intel_encoder(old_conn_state->best_encoder);
6793
6794                 if (old_conn_state->crtc != &crtc->base)
6795                         continue;
6796
6797                 if (encoder->post_disable)
6798                         encoder->post_disable(state, encoder,
6799                                               old_crtc_state, old_conn_state);
6800         }
6801 }
6802
6803 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6804                                             struct intel_crtc *crtc)
6805 {
6806         const struct intel_crtc_state *old_crtc_state =
6807                 intel_atomic_get_old_crtc_state(state, crtc);
6808         const struct drm_connector_state *old_conn_state;
6809         struct drm_connector *conn;
6810         int i;
6811
6812         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6813                 struct intel_encoder *encoder =
6814                         to_intel_encoder(old_conn_state->best_encoder);
6815
6816                 if (old_conn_state->crtc != &crtc->base)
6817                         continue;
6818
6819                 if (encoder->post_pll_disable)
6820                         encoder->post_pll_disable(state, encoder,
6821                                                   old_crtc_state, old_conn_state);
6822         }
6823 }
6824
6825 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6826                                        struct intel_crtc *crtc)
6827 {
6828         const struct intel_crtc_state *crtc_state =
6829                 intel_atomic_get_new_crtc_state(state, crtc);
6830         const struct drm_connector_state *conn_state;
6831         struct drm_connector *conn;
6832         int i;
6833
6834         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6835                 struct intel_encoder *encoder =
6836                         to_intel_encoder(conn_state->best_encoder);
6837
6838                 if (conn_state->crtc != &crtc->base)
6839                         continue;
6840
6841                 if (encoder->update_pipe)
6842                         encoder->update_pipe(state, encoder,
6843                                              crtc_state, conn_state);
6844         }
6845 }
6846
6847 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6848 {
6849         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6850         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6851
6852         plane->disable_plane(plane, crtc_state);
6853 }
6854
6855 static void ilk_crtc_enable(struct intel_atomic_state *state,
6856                             struct intel_crtc *crtc)
6857 {
6858         const struct intel_crtc_state *new_crtc_state =
6859                 intel_atomic_get_new_crtc_state(state, crtc);
6860         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6861         enum pipe pipe = crtc->pipe;
6862
6863         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6864                 return;
6865
6866         /*
6867          * Sometimes spurious CPU pipe underruns happen during FDI
6868          * training, at least with VGA+HDMI cloning. Suppress them.
6869          *
6870          * On ILK we get an occasional spurious CPU pipe underruns
6871          * between eDP port A enable and vdd enable. Also PCH port
6872          * enable seems to result in the occasional CPU pipe underrun.
6873          *
6874          * Spurious PCH underruns also occur during PCH enabling.
6875          */
6876         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6877         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6878
6879         if (new_crtc_state->has_pch_encoder)
6880                 intel_prepare_shared_dpll(new_crtc_state);
6881
6882         if (intel_crtc_has_dp_encoder(new_crtc_state))
6883                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6884
6885         intel_set_pipe_timings(new_crtc_state);
6886         intel_set_pipe_src_size(new_crtc_state);
6887
6888         if (new_crtc_state->has_pch_encoder)
6889                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6890                                              &new_crtc_state->fdi_m_n, NULL);
6891
6892         ilk_set_pipeconf(new_crtc_state);
6893
6894         crtc->active = true;
6895
6896         intel_encoders_pre_enable(state, crtc);
6897
6898         if (new_crtc_state->has_pch_encoder) {
6899                 /* Note: FDI PLL enabling _must_ be done before we enable the
6900                  * cpu pipes, hence this is separate from all the other fdi/pch
6901                  * enabling. */
6902                 ilk_fdi_pll_enable(new_crtc_state);
6903         } else {
6904                 assert_fdi_tx_disabled(dev_priv, pipe);
6905                 assert_fdi_rx_disabled(dev_priv, pipe);
6906         }
6907
6908         ilk_pfit_enable(new_crtc_state);
6909
6910         /*
6911          * On ILK+ LUT must be loaded before the pipe is running but with
6912          * clocks enabled
6913          */
6914         intel_color_load_luts(new_crtc_state);
6915         intel_color_commit(new_crtc_state);
6916         /* update DSPCNTR to configure gamma for pipe bottom color */
6917         intel_disable_primary_plane(new_crtc_state);
6918
6919         if (dev_priv->display.initial_watermarks)
6920                 dev_priv->display.initial_watermarks(state, crtc);
6921         intel_enable_pipe(new_crtc_state);
6922
6923         if (new_crtc_state->has_pch_encoder)
6924                 ilk_pch_enable(state, new_crtc_state);
6925
6926         intel_crtc_vblank_on(new_crtc_state);
6927
6928         intel_encoders_enable(state, crtc);
6929
6930         if (HAS_PCH_CPT(dev_priv))
6931                 cpt_verify_modeset(dev_priv, pipe);
6932
6933         /*
6934          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6935          * And a second vblank wait is needed at least on ILK with
6936          * some interlaced HDMI modes. Let's do the double wait always
6937          * in case there are more corner cases we don't know about.
6938          */
6939         if (new_crtc_state->has_pch_encoder) {
6940                 intel_wait_for_vblank(dev_priv, pipe);
6941                 intel_wait_for_vblank(dev_priv, pipe);
6942         }
6943         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6944         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6945 }
6946
6947 /* IPS only exists on ULT machines and is tied to pipe A. */
6948 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6949 {
6950         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6951 }
6952
6953 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6954                                             enum pipe pipe, bool apply)
6955 {
6956         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
6957         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6958
6959         if (apply)
6960                 val |= mask;
6961         else
6962                 val &= ~mask;
6963
6964         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
6965 }
6966
6967 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6968 {
6969         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6970         enum pipe pipe = crtc->pipe;
6971         u32 val;
6972
6973         val = MBUS_DBOX_A_CREDIT(2);
6974
6975         if (INTEL_GEN(dev_priv) >= 12) {
6976                 val |= MBUS_DBOX_BW_CREDIT(2);
6977                 val |= MBUS_DBOX_B_CREDIT(12);
6978         } else {
6979                 val |= MBUS_DBOX_BW_CREDIT(1);
6980                 val |= MBUS_DBOX_B_CREDIT(8);
6981         }
6982
6983         intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
6984 }
6985
6986 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
6987 {
6988         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6989         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6990
6991         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
6992                        HSW_LINETIME(crtc_state->linetime) |
6993                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
6994 }
6995
6996 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6997 {
6998         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6999         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7000         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7001         u32 val;
7002
7003         val = intel_de_read(dev_priv, reg);
7004         val &= ~HSW_FRAME_START_DELAY_MASK;
7005         val |= HSW_FRAME_START_DELAY(0);
7006         intel_de_write(dev_priv, reg, val);
7007 }
7008
7009 static void hsw_crtc_enable(struct intel_atomic_state *state,
7010                             struct intel_crtc *crtc)
7011 {
7012         const struct intel_crtc_state *new_crtc_state =
7013                 intel_atomic_get_new_crtc_state(state, crtc);
7014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7015         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7016         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7017         bool psl_clkgate_wa;
7018
7019         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7020                 return;
7021
7022         intel_encoders_pre_pll_enable(state, crtc);
7023
7024         if (new_crtc_state->shared_dpll)
7025                 intel_enable_shared_dpll(new_crtc_state);
7026
7027         intel_encoders_pre_enable(state, crtc);
7028
7029         if (!transcoder_is_dsi(cpu_transcoder))
7030                 intel_set_pipe_timings(new_crtc_state);
7031
7032         intel_set_pipe_src_size(new_crtc_state);
7033
7034         if (cpu_transcoder != TRANSCODER_EDP &&
7035             !transcoder_is_dsi(cpu_transcoder))
7036                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7037                                new_crtc_state->pixel_multiplier - 1);
7038
7039         if (new_crtc_state->has_pch_encoder)
7040                 intel_cpu_transcoder_set_m_n(new_crtc_state,
7041                                              &new_crtc_state->fdi_m_n, NULL);
7042
7043         if (!transcoder_is_dsi(cpu_transcoder)) {
7044                 hsw_set_frame_start_delay(new_crtc_state);
7045                 hsw_set_pipeconf(new_crtc_state);
7046         }
7047
7048         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7049                 bdw_set_pipemisc(new_crtc_state);
7050
7051         crtc->active = true;
7052
7053         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7054         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7055                 new_crtc_state->pch_pfit.enabled;
7056         if (psl_clkgate_wa)
7057                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7058
7059         if (INTEL_GEN(dev_priv) >= 9)
7060                 skl_pfit_enable(new_crtc_state);
7061         else
7062                 ilk_pfit_enable(new_crtc_state);
7063
7064         /*
7065          * On ILK+ LUT must be loaded before the pipe is running but with
7066          * clocks enabled
7067          */
7068         intel_color_load_luts(new_crtc_state);
7069         intel_color_commit(new_crtc_state);
7070         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7071         if (INTEL_GEN(dev_priv) < 9)
7072                 intel_disable_primary_plane(new_crtc_state);
7073
7074         hsw_set_linetime_wm(new_crtc_state);
7075
7076         if (INTEL_GEN(dev_priv) >= 11)
7077                 icl_set_pipe_chicken(crtc);
7078
7079         if (dev_priv->display.initial_watermarks)
7080                 dev_priv->display.initial_watermarks(state, crtc);
7081
7082         if (INTEL_GEN(dev_priv) >= 11)
7083                 icl_pipe_mbus_enable(crtc);
7084
7085         intel_encoders_enable(state, crtc);
7086
7087         if (psl_clkgate_wa) {
7088                 intel_wait_for_vblank(dev_priv, pipe);
7089                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7090         }
7091
7092         /* If we change the relative order between pipe/planes enabling, we need
7093          * to change the workaround. */
7094         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7095         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7096                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7097                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7098         }
7099 }
7100
7101 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7102 {
7103         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7104         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7105         enum pipe pipe = crtc->pipe;
7106
7107         /* To avoid upsetting the power well on haswell only disable the pfit if
7108          * it's in use. The hw state code will make sure we get this right. */
7109         if (!old_crtc_state->pch_pfit.enabled)
7110                 return;
7111
7112         intel_de_write(dev_priv, PF_CTL(pipe), 0);
7113         intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7114         intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7115 }
7116
7117 static void ilk_crtc_disable(struct intel_atomic_state *state,
7118                              struct intel_crtc *crtc)
7119 {
7120         const struct intel_crtc_state *old_crtc_state =
7121                 intel_atomic_get_old_crtc_state(state, crtc);
7122         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7123         enum pipe pipe = crtc->pipe;
7124
7125         /*
7126          * Sometimes spurious CPU pipe underruns happen when the
7127          * pipe is already disabled, but FDI RX/TX is still enabled.
7128          * Happens at least with VGA+HDMI cloning. Suppress them.
7129          */
7130         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7131         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7132
7133         intel_encoders_disable(state, crtc);
7134
7135         intel_crtc_vblank_off(old_crtc_state);
7136
7137         intel_disable_pipe(old_crtc_state);
7138
7139         ilk_pfit_disable(old_crtc_state);
7140
7141         if (old_crtc_state->has_pch_encoder)
7142                 ilk_fdi_disable(crtc);
7143
7144         intel_encoders_post_disable(state, crtc);
7145
7146         if (old_crtc_state->has_pch_encoder) {
7147                 ilk_disable_pch_transcoder(dev_priv, pipe);
7148
7149                 if (HAS_PCH_CPT(dev_priv)) {
7150                         i915_reg_t reg;
7151                         u32 temp;
7152
7153                         /* disable TRANS_DP_CTL */
7154                         reg = TRANS_DP_CTL(pipe);
7155                         temp = intel_de_read(dev_priv, reg);
7156                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7157                                   TRANS_DP_PORT_SEL_MASK);
7158                         temp |= TRANS_DP_PORT_SEL_NONE;
7159                         intel_de_write(dev_priv, reg, temp);
7160
7161                         /* disable DPLL_SEL */
7162                         temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7163                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7164                         intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7165                 }
7166
7167                 ilk_fdi_pll_disable(crtc);
7168         }
7169
7170         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7171         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7172 }
7173
7174 static void hsw_crtc_disable(struct intel_atomic_state *state,
7175                              struct intel_crtc *crtc)
7176 {
7177         /*
7178          * FIXME collapse everything to one hook.
7179          * Need care with mst->ddi interactions.
7180          */
7181         intel_encoders_disable(state, crtc);
7182         intel_encoders_post_disable(state, crtc);
7183 }
7184
7185 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7186 {
7187         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7188         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7189
7190         if (!crtc_state->gmch_pfit.control)
7191                 return;
7192
7193         /*
7194          * The panel fitter should only be adjusted whilst the pipe is disabled,
7195          * according to register description and PRM.
7196          */
7197         drm_WARN_ON(&dev_priv->drm,
7198                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7199         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7200
7201         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7202                        crtc_state->gmch_pfit.pgm_ratios);
7203         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7204
7205         /* Border color in case we don't scale up to the full screen. Black by
7206          * default, change to something else for debugging. */
7207         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7208 }
7209
7210 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7211 {
7212         if (phy == PHY_NONE)
7213                 return false;
7214
7215         if (IS_ELKHARTLAKE(dev_priv))
7216                 return phy <= PHY_C;
7217
7218         if (INTEL_GEN(dev_priv) >= 11)
7219                 return phy <= PHY_B;
7220
7221         return false;
7222 }
7223
7224 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7225 {
7226         if (INTEL_GEN(dev_priv) >= 12)
7227                 return phy >= PHY_D && phy <= PHY_I;
7228
7229         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
7230                 return phy >= PHY_C && phy <= PHY_F;
7231
7232         return false;
7233 }
7234
7235 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7236 {
7237         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
7238                 return PHY_A;
7239
7240         return (enum phy)port;
7241 }
7242
7243 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7244 {
7245         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7246                 return PORT_TC_NONE;
7247
7248         if (INTEL_GEN(dev_priv) >= 12)
7249                 return port - PORT_D;
7250
7251         return port - PORT_C;
7252 }
7253
7254 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7255 {
7256         switch (port) {
7257         case PORT_A:
7258                 return POWER_DOMAIN_PORT_DDI_A_LANES;
7259         case PORT_B:
7260                 return POWER_DOMAIN_PORT_DDI_B_LANES;
7261         case PORT_C:
7262                 return POWER_DOMAIN_PORT_DDI_C_LANES;
7263         case PORT_D:
7264                 return POWER_DOMAIN_PORT_DDI_D_LANES;
7265         case PORT_E:
7266                 return POWER_DOMAIN_PORT_DDI_E_LANES;
7267         case PORT_F:
7268                 return POWER_DOMAIN_PORT_DDI_F_LANES;
7269         case PORT_G:
7270                 return POWER_DOMAIN_PORT_DDI_G_LANES;
7271         default:
7272                 MISSING_CASE(port);
7273                 return POWER_DOMAIN_PORT_OTHER;
7274         }
7275 }
7276
7277 enum intel_display_power_domain
7278 intel_aux_power_domain(struct intel_digital_port *dig_port)
7279 {
7280         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7281         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7282
7283         if (intel_phy_is_tc(dev_priv, phy) &&
7284             dig_port->tc_mode == TC_PORT_TBT_ALT) {
7285                 switch (dig_port->aux_ch) {
7286                 case AUX_CH_C:
7287                         return POWER_DOMAIN_AUX_C_TBT;
7288                 case AUX_CH_D:
7289                         return POWER_DOMAIN_AUX_D_TBT;
7290                 case AUX_CH_E:
7291                         return POWER_DOMAIN_AUX_E_TBT;
7292                 case AUX_CH_F:
7293                         return POWER_DOMAIN_AUX_F_TBT;
7294                 case AUX_CH_G:
7295                         return POWER_DOMAIN_AUX_G_TBT;
7296                 default:
7297                         MISSING_CASE(dig_port->aux_ch);
7298                         return POWER_DOMAIN_AUX_C_TBT;
7299                 }
7300         }
7301
7302         return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7303 }
7304
7305 /*
7306  * Converts aux_ch to power_domain without caring about TBT ports for that use
7307  * intel_aux_power_domain()
7308  */
7309 enum intel_display_power_domain
7310 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7311 {
7312         switch (aux_ch) {
7313         case AUX_CH_A:
7314                 return POWER_DOMAIN_AUX_A;
7315         case AUX_CH_B:
7316                 return POWER_DOMAIN_AUX_B;
7317         case AUX_CH_C:
7318                 return POWER_DOMAIN_AUX_C;
7319         case AUX_CH_D:
7320                 return POWER_DOMAIN_AUX_D;
7321         case AUX_CH_E:
7322                 return POWER_DOMAIN_AUX_E;
7323         case AUX_CH_F:
7324                 return POWER_DOMAIN_AUX_F;
7325         case AUX_CH_G:
7326                 return POWER_DOMAIN_AUX_G;
7327         default:
7328                 MISSING_CASE(aux_ch);
7329                 return POWER_DOMAIN_AUX_A;
7330         }
7331 }
7332
7333 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7334 {
7335         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7336         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7337         struct drm_encoder *encoder;
7338         enum pipe pipe = crtc->pipe;
7339         u64 mask;
7340         enum transcoder transcoder = crtc_state->cpu_transcoder;
7341
7342         if (!crtc_state->hw.active)
7343                 return 0;
7344
7345         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7346         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7347         if (crtc_state->pch_pfit.enabled ||
7348             crtc_state->pch_pfit.force_thru)
7349                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7350
7351         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7352                                   crtc_state->uapi.encoder_mask) {
7353                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7354
7355                 mask |= BIT_ULL(intel_encoder->power_domain);
7356         }
7357
7358         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7359                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7360
7361         if (crtc_state->shared_dpll)
7362                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7363
7364         return mask;
7365 }
7366
7367 static u64
7368 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7369 {
7370         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7371         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7372         enum intel_display_power_domain domain;
7373         u64 domains, new_domains, old_domains;
7374
7375         old_domains = crtc->enabled_power_domains;
7376         crtc->enabled_power_domains = new_domains =
7377                 get_crtc_power_domains(crtc_state);
7378
7379         domains = new_domains & ~old_domains;
7380
7381         for_each_power_domain(domain, domains)
7382                 intel_display_power_get(dev_priv, domain);
7383
7384         return old_domains & ~new_domains;
7385 }
7386
7387 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7388                                       u64 domains)
7389 {
7390         enum intel_display_power_domain domain;
7391
7392         for_each_power_domain(domain, domains)
7393                 intel_display_power_put_unchecked(dev_priv, domain);
7394 }
7395
7396 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7397                                    struct intel_crtc *crtc)
7398 {
7399         const struct intel_crtc_state *new_crtc_state =
7400                 intel_atomic_get_new_crtc_state(state, crtc);
7401         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7402         enum pipe pipe = crtc->pipe;
7403
7404         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7405                 return;
7406
7407         if (intel_crtc_has_dp_encoder(new_crtc_state))
7408                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7409
7410         intel_set_pipe_timings(new_crtc_state);
7411         intel_set_pipe_src_size(new_crtc_state);
7412
7413         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7414                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7415                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7416         }
7417
7418         i9xx_set_pipeconf(new_crtc_state);
7419
7420         crtc->active = true;
7421
7422         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7423
7424         intel_encoders_pre_pll_enable(state, crtc);
7425
7426         if (IS_CHERRYVIEW(dev_priv)) {
7427                 chv_prepare_pll(crtc, new_crtc_state);
7428                 chv_enable_pll(crtc, new_crtc_state);
7429         } else {
7430                 vlv_prepare_pll(crtc, new_crtc_state);
7431                 vlv_enable_pll(crtc, new_crtc_state);
7432         }
7433
7434         intel_encoders_pre_enable(state, crtc);
7435
7436         i9xx_pfit_enable(new_crtc_state);
7437
7438         intel_color_load_luts(new_crtc_state);
7439         intel_color_commit(new_crtc_state);
7440         /* update DSPCNTR to configure gamma for pipe bottom color */
7441         intel_disable_primary_plane(new_crtc_state);
7442
7443         dev_priv->display.initial_watermarks(state, crtc);
7444         intel_enable_pipe(new_crtc_state);
7445
7446         intel_crtc_vblank_on(new_crtc_state);
7447
7448         intel_encoders_enable(state, crtc);
7449 }
7450
7451 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7452 {
7453         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7454         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7455
7456         intel_de_write(dev_priv, FP0(crtc->pipe),
7457                        crtc_state->dpll_hw_state.fp0);
7458         intel_de_write(dev_priv, FP1(crtc->pipe),
7459                        crtc_state->dpll_hw_state.fp1);
7460 }
7461
7462 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7463                              struct intel_crtc *crtc)
7464 {
7465         const struct intel_crtc_state *new_crtc_state =
7466                 intel_atomic_get_new_crtc_state(state, crtc);
7467         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7468         enum pipe pipe = crtc->pipe;
7469
7470         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7471                 return;
7472
7473         i9xx_set_pll_dividers(new_crtc_state);
7474
7475         if (intel_crtc_has_dp_encoder(new_crtc_state))
7476                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7477
7478         intel_set_pipe_timings(new_crtc_state);
7479         intel_set_pipe_src_size(new_crtc_state);
7480
7481         i9xx_set_pipeconf(new_crtc_state);
7482
7483         crtc->active = true;
7484
7485         if (!IS_GEN(dev_priv, 2))
7486                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7487
7488         intel_encoders_pre_enable(state, crtc);
7489
7490         i9xx_enable_pll(crtc, new_crtc_state);
7491
7492         i9xx_pfit_enable(new_crtc_state);
7493
7494         intel_color_load_luts(new_crtc_state);
7495         intel_color_commit(new_crtc_state);
7496         /* update DSPCNTR to configure gamma for pipe bottom color */
7497         intel_disable_primary_plane(new_crtc_state);
7498
7499         if (dev_priv->display.initial_watermarks)
7500                 dev_priv->display.initial_watermarks(state, crtc);
7501         else
7502                 intel_update_watermarks(crtc);
7503         intel_enable_pipe(new_crtc_state);
7504
7505         intel_crtc_vblank_on(new_crtc_state);
7506
7507         intel_encoders_enable(state, crtc);
7508 }
7509
7510 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7511 {
7512         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7514
7515         if (!old_crtc_state->gmch_pfit.control)
7516                 return;
7517
7518         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7519
7520         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7521                     intel_de_read(dev_priv, PFIT_CONTROL));
7522         intel_de_write(dev_priv, PFIT_CONTROL, 0);
7523 }
7524
7525 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7526                               struct intel_crtc *crtc)
7527 {
7528         struct intel_crtc_state *old_crtc_state =
7529                 intel_atomic_get_old_crtc_state(state, crtc);
7530         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7531         enum pipe pipe = crtc->pipe;
7532
7533         /*
7534          * On gen2 planes are double buffered but the pipe isn't, so we must
7535          * wait for planes to fully turn off before disabling the pipe.
7536          */
7537         if (IS_GEN(dev_priv, 2))
7538                 intel_wait_for_vblank(dev_priv, pipe);
7539
7540         intel_encoders_disable(state, crtc);
7541
7542         intel_crtc_vblank_off(old_crtc_state);
7543
7544         intel_disable_pipe(old_crtc_state);
7545
7546         i9xx_pfit_disable(old_crtc_state);
7547
7548         intel_encoders_post_disable(state, crtc);
7549
7550         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7551                 if (IS_CHERRYVIEW(dev_priv))
7552                         chv_disable_pll(dev_priv, pipe);
7553                 else if (IS_VALLEYVIEW(dev_priv))
7554                         vlv_disable_pll(dev_priv, pipe);
7555                 else
7556                         i9xx_disable_pll(old_crtc_state);
7557         }
7558
7559         intel_encoders_post_pll_disable(state, crtc);
7560
7561         if (!IS_GEN(dev_priv, 2))
7562                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7563
7564         if (!dev_priv->display.initial_watermarks)
7565                 intel_update_watermarks(crtc);
7566
7567         /* clock the pipe down to 640x480@60 to potentially save power */
7568         if (IS_I830(dev_priv))
7569                 i830_enable_pipe(dev_priv, pipe);
7570 }
7571
7572 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7573                                         struct drm_modeset_acquire_ctx *ctx)
7574 {
7575         struct intel_encoder *encoder;
7576         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7577         struct intel_bw_state *bw_state =
7578                 to_intel_bw_state(dev_priv->bw_obj.state);
7579         struct intel_cdclk_state *cdclk_state =
7580                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7581         struct intel_dbuf_state *dbuf_state =
7582                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7583         struct intel_crtc_state *crtc_state =
7584                 to_intel_crtc_state(crtc->base.state);
7585         enum intel_display_power_domain domain;
7586         struct intel_plane *plane;
7587         struct drm_atomic_state *state;
7588         struct intel_crtc_state *temp_crtc_state;
7589         enum pipe pipe = crtc->pipe;
7590         u64 domains;
7591         int ret;
7592
7593         if (!crtc_state->hw.active)
7594                 return;
7595
7596         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7597                 const struct intel_plane_state *plane_state =
7598                         to_intel_plane_state(plane->base.state);
7599
7600                 if (plane_state->uapi.visible)
7601                         intel_plane_disable_noatomic(crtc, plane);
7602         }
7603
7604         state = drm_atomic_state_alloc(&dev_priv->drm);
7605         if (!state) {
7606                 drm_dbg_kms(&dev_priv->drm,
7607                             "failed to disable [CRTC:%d:%s], out of memory",
7608                             crtc->base.base.id, crtc->base.name);
7609                 return;
7610         }
7611
7612         state->acquire_ctx = ctx;
7613
7614         /* Everything's already locked, -EDEADLK can't happen. */
7615         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7616         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7617
7618         drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7619
7620         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7621
7622         drm_atomic_state_put(state);
7623
7624         drm_dbg_kms(&dev_priv->drm,
7625                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7626                     crtc->base.base.id, crtc->base.name);
7627
7628         crtc->active = false;
7629         crtc->base.enabled = false;
7630
7631         drm_WARN_ON(&dev_priv->drm,
7632                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7633         crtc_state->uapi.active = false;
7634         crtc_state->uapi.connector_mask = 0;
7635         crtc_state->uapi.encoder_mask = 0;
7636         intel_crtc_free_hw_state(crtc_state);
7637         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7638
7639         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7640                 encoder->base.crtc = NULL;
7641
7642         intel_fbc_disable(crtc);
7643         intel_update_watermarks(crtc);
7644         intel_disable_shared_dpll(crtc_state);
7645
7646         domains = crtc->enabled_power_domains;
7647         for_each_power_domain(domain, domains)
7648                 intel_display_power_put_unchecked(dev_priv, domain);
7649         crtc->enabled_power_domains = 0;
7650
7651         dev_priv->active_pipes &= ~BIT(pipe);
7652         cdclk_state->min_cdclk[pipe] = 0;
7653         cdclk_state->min_voltage_level[pipe] = 0;
7654         cdclk_state->active_pipes &= ~BIT(pipe);
7655
7656         dbuf_state->active_pipes &= ~BIT(pipe);
7657
7658         bw_state->data_rate[pipe] = 0;
7659         bw_state->num_active_planes[pipe] = 0;
7660 }
7661
7662 /*
7663  * turn all crtc's off, but do not adjust state
7664  * This has to be paired with a call to intel_modeset_setup_hw_state.
7665  */
7666 int intel_display_suspend(struct drm_device *dev)
7667 {
7668         struct drm_i915_private *dev_priv = to_i915(dev);
7669         struct drm_atomic_state *state;
7670         int ret;
7671
7672         state = drm_atomic_helper_suspend(dev);
7673         ret = PTR_ERR_OR_ZERO(state);
7674         if (ret)
7675                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7676                         ret);
7677         else
7678                 dev_priv->modeset_restore_state = state;
7679         return ret;
7680 }
7681
7682 void intel_encoder_destroy(struct drm_encoder *encoder)
7683 {
7684         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7685
7686         drm_encoder_cleanup(encoder);
7687         kfree(intel_encoder);
7688 }
7689
7690 /* Cross check the actual hw state with our own modeset state tracking (and it's
7691  * internal consistency). */
7692 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7693                                          struct drm_connector_state *conn_state)
7694 {
7695         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7696         struct drm_i915_private *i915 = to_i915(connector->base.dev);
7697
7698         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7699                     connector->base.base.id, connector->base.name);
7700
7701         if (connector->get_hw_state(connector)) {
7702                 struct intel_encoder *encoder = intel_attached_encoder(connector);
7703
7704                 I915_STATE_WARN(!crtc_state,
7705                          "connector enabled without attached crtc\n");
7706
7707                 if (!crtc_state)
7708                         return;
7709
7710                 I915_STATE_WARN(!crtc_state->hw.active,
7711                                 "connector is active, but attached crtc isn't\n");
7712
7713                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7714                         return;
7715
7716                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7717                         "atomic encoder doesn't match attached encoder\n");
7718
7719                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7720                         "attached encoder crtc differs from connector crtc\n");
7721         } else {
7722                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7723                                 "attached crtc is active, but connector isn't\n");
7724                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7725                         "best encoder set without crtc!\n");
7726         }
7727 }
7728
7729 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7730 {
7731         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7732                 return crtc_state->fdi_lanes;
7733
7734         return 0;
7735 }
7736
7737 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7738                                struct intel_crtc_state *pipe_config)
7739 {
7740         struct drm_i915_private *dev_priv = to_i915(dev);
7741         struct drm_atomic_state *state = pipe_config->uapi.state;
7742         struct intel_crtc *other_crtc;
7743         struct intel_crtc_state *other_crtc_state;
7744
7745         drm_dbg_kms(&dev_priv->drm,
7746                     "checking fdi config on pipe %c, lanes %i\n",
7747                     pipe_name(pipe), pipe_config->fdi_lanes);
7748         if (pipe_config->fdi_lanes > 4) {
7749                 drm_dbg_kms(&dev_priv->drm,
7750                             "invalid fdi lane config on pipe %c: %i lanes\n",
7751                             pipe_name(pipe), pipe_config->fdi_lanes);
7752                 return -EINVAL;
7753         }
7754
7755         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7756                 if (pipe_config->fdi_lanes > 2) {
7757                         drm_dbg_kms(&dev_priv->drm,
7758                                     "only 2 lanes on haswell, required: %i lanes\n",
7759                                     pipe_config->fdi_lanes);
7760                         return -EINVAL;
7761                 } else {
7762                         return 0;
7763                 }
7764         }
7765
7766         if (INTEL_NUM_PIPES(dev_priv) == 2)
7767                 return 0;
7768
7769         /* Ivybridge 3 pipe is really complicated */
7770         switch (pipe) {
7771         case PIPE_A:
7772                 return 0;
7773         case PIPE_B:
7774                 if (pipe_config->fdi_lanes <= 2)
7775                         return 0;
7776
7777                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7778                 other_crtc_state =
7779                         intel_atomic_get_crtc_state(state, other_crtc);
7780                 if (IS_ERR(other_crtc_state))
7781                         return PTR_ERR(other_crtc_state);
7782
7783                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7784                         drm_dbg_kms(&dev_priv->drm,
7785                                     "invalid shared fdi lane config on pipe %c: %i lanes\n",
7786                                     pipe_name(pipe), pipe_config->fdi_lanes);
7787                         return -EINVAL;
7788                 }
7789                 return 0;
7790         case PIPE_C:
7791                 if (pipe_config->fdi_lanes > 2) {
7792                         drm_dbg_kms(&dev_priv->drm,
7793                                     "only 2 lanes on pipe %c: required %i lanes\n",
7794                                     pipe_name(pipe), pipe_config->fdi_lanes);
7795                         return -EINVAL;
7796                 }
7797
7798                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7799                 other_crtc_state =
7800                         intel_atomic_get_crtc_state(state, other_crtc);
7801                 if (IS_ERR(other_crtc_state))
7802                         return PTR_ERR(other_crtc_state);
7803
7804                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7805                         drm_dbg_kms(&dev_priv->drm,
7806                                     "fdi link B uses too many lanes to enable link C\n");
7807                         return -EINVAL;
7808                 }
7809                 return 0;
7810         default:
7811                 BUG();
7812         }
7813 }
7814
7815 #define RETRY 1
7816 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7817                                   struct intel_crtc_state *pipe_config)
7818 {
7819         struct drm_device *dev = intel_crtc->base.dev;
7820         struct drm_i915_private *i915 = to_i915(dev);
7821         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7822         int lane, link_bw, fdi_dotclock, ret;
7823         bool needs_recompute = false;
7824
7825 retry:
7826         /* FDI is a binary signal running at ~2.7GHz, encoding
7827          * each output octet as 10 bits. The actual frequency
7828          * is stored as a divider into a 100MHz clock, and the
7829          * mode pixel clock is stored in units of 1KHz.
7830          * Hence the bw of each lane in terms of the mode signal
7831          * is:
7832          */
7833         link_bw = intel_fdi_link_freq(i915, pipe_config);
7834
7835         fdi_dotclock = adjusted_mode->crtc_clock;
7836
7837         lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7838                                       pipe_config->pipe_bpp);
7839
7840         pipe_config->fdi_lanes = lane;
7841
7842         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7843                                link_bw, &pipe_config->fdi_m_n, false, false);
7844
7845         ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7846         if (ret == -EDEADLK)
7847                 return ret;
7848
7849         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7850                 pipe_config->pipe_bpp -= 2*3;
7851                 drm_dbg_kms(&i915->drm,
7852                             "fdi link bw constraint, reducing pipe bpp to %i\n",
7853                             pipe_config->pipe_bpp);
7854                 needs_recompute = true;
7855                 pipe_config->bw_constrained = true;
7856
7857                 goto retry;
7858         }
7859
7860         if (needs_recompute)
7861                 return RETRY;
7862
7863         return ret;
7864 }
7865
7866 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7867 {
7868         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7869         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7870
7871         /* IPS only exists on ULT machines and is tied to pipe A. */
7872         if (!hsw_crtc_supports_ips(crtc))
7873                 return false;
7874
7875         if (!i915_modparams.enable_ips)
7876                 return false;
7877
7878         if (crtc_state->pipe_bpp > 24)
7879                 return false;
7880
7881         /*
7882          * We compare against max which means we must take
7883          * the increased cdclk requirement into account when
7884          * calculating the new cdclk.
7885          *
7886          * Should measure whether using a lower cdclk w/o IPS
7887          */
7888         if (IS_BROADWELL(dev_priv) &&
7889             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7890                 return false;
7891
7892         return true;
7893 }
7894
7895 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7896 {
7897         struct drm_i915_private *dev_priv =
7898                 to_i915(crtc_state->uapi.crtc->dev);
7899         struct intel_atomic_state *state =
7900                 to_intel_atomic_state(crtc_state->uapi.state);
7901
7902         crtc_state->ips_enabled = false;
7903
7904         if (!hsw_crtc_state_ips_capable(crtc_state))
7905                 return 0;
7906
7907         /*
7908          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7909          * enabled and disabled dynamically based on package C states,
7910          * user space can't make reliable use of the CRCs, so let's just
7911          * completely disable it.
7912          */
7913         if (crtc_state->crc_enabled)
7914                 return 0;
7915
7916         /* IPS should be fine as long as at least one plane is enabled. */
7917         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7918                 return 0;
7919
7920         if (IS_BROADWELL(dev_priv)) {
7921                 const struct intel_cdclk_state *cdclk_state;
7922
7923                 cdclk_state = intel_atomic_get_cdclk_state(state);
7924                 if (IS_ERR(cdclk_state))
7925                         return PTR_ERR(cdclk_state);
7926
7927                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7928                 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
7929                         return 0;
7930         }
7931
7932         crtc_state->ips_enabled = true;
7933
7934         return 0;
7935 }
7936
7937 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7938 {
7939         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7940
7941         /* GDG double wide on either pipe, otherwise pipe A only */
7942         return INTEL_GEN(dev_priv) < 4 &&
7943                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7944 }
7945
7946 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
7947 {
7948         u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
7949         unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
7950
7951         /*
7952          * We only use IF-ID interlacing. If we ever use
7953          * PF-ID we'll need to adjust the pixel_rate here.
7954          */
7955
7956         if (!crtc_state->pch_pfit.enabled)
7957                 return pixel_rate;
7958
7959         pipe_w = crtc_state->pipe_src_w;
7960         pipe_h = crtc_state->pipe_src_h;
7961
7962         pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
7963         pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
7964
7965         if (pipe_w < pfit_w)
7966                 pipe_w = pfit_w;
7967         if (pipe_h < pfit_h)
7968                 pipe_h = pfit_h;
7969
7970         if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
7971                         !pfit_w || !pfit_h))
7972                 return pixel_rate;
7973
7974         return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7975                        pfit_w * pfit_h);
7976 }
7977
7978 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7979 {
7980         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7981
7982         if (HAS_GMCH(dev_priv))
7983                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7984                 crtc_state->pixel_rate =
7985                         crtc_state->hw.adjusted_mode.crtc_clock;
7986         else
7987                 crtc_state->pixel_rate =
7988                         ilk_pipe_pixel_rate(crtc_state);
7989 }
7990
7991 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7992                                      struct intel_crtc_state *pipe_config)
7993 {
7994         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7995         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7996         int clock_limit = dev_priv->max_dotclk_freq;
7997
7998         if (INTEL_GEN(dev_priv) < 4) {
7999                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8000
8001                 /*
8002                  * Enable double wide mode when the dot clock
8003                  * is > 90% of the (display) core speed.
8004                  */
8005                 if (intel_crtc_supports_double_wide(crtc) &&
8006                     adjusted_mode->crtc_clock > clock_limit) {
8007                         clock_limit = dev_priv->max_dotclk_freq;
8008                         pipe_config->double_wide = true;
8009                 }
8010         }
8011
8012         if (adjusted_mode->crtc_clock > clock_limit) {
8013                 drm_dbg_kms(&dev_priv->drm,
8014                             "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8015                             adjusted_mode->crtc_clock, clock_limit,
8016                             yesno(pipe_config->double_wide));
8017                 return -EINVAL;
8018         }
8019
8020         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8021              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8022              pipe_config->hw.ctm) {
8023                 /*
8024                  * There is only one pipe CSC unit per pipe, and we need that
8025                  * for output conversion from RGB->YCBCR. So if CTM is already
8026                  * applied we can't support YCBCR420 output.
8027                  */
8028                 drm_dbg_kms(&dev_priv->drm,
8029                             "YCBCR420 and CTM together are not possible\n");
8030                 return -EINVAL;
8031         }
8032
8033         /*
8034          * Pipe horizontal size must be even in:
8035          * - DVO ganged mode
8036          * - LVDS dual channel mode
8037          * - Double wide pipe
8038          */
8039         if (pipe_config->pipe_src_w & 1) {
8040                 if (pipe_config->double_wide) {
8041                         drm_dbg_kms(&dev_priv->drm,
8042                                     "Odd pipe source width not supported with double wide pipe\n");
8043                         return -EINVAL;
8044                 }
8045
8046                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8047                     intel_is_dual_link_lvds(dev_priv)) {
8048                         drm_dbg_kms(&dev_priv->drm,
8049                                     "Odd pipe source width not supported with dual link LVDS\n");
8050                         return -EINVAL;
8051                 }
8052         }
8053
8054         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8055          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8056          */
8057         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8058                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8059                 return -EINVAL;
8060
8061         intel_crtc_compute_pixel_rate(pipe_config);
8062
8063         if (pipe_config->has_pch_encoder)
8064                 return ilk_fdi_compute_config(crtc, pipe_config);
8065
8066         return 0;
8067 }
8068
8069 static void
8070 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8071 {
8072         while (*num > DATA_LINK_M_N_MASK ||
8073                *den > DATA_LINK_M_N_MASK) {
8074                 *num >>= 1;
8075                 *den >>= 1;
8076         }
8077 }
8078
8079 static void compute_m_n(unsigned int m, unsigned int n,
8080                         u32 *ret_m, u32 *ret_n,
8081                         bool constant_n)
8082 {
8083         /*
8084          * Several DP dongles in particular seem to be fussy about
8085          * too large link M/N values. Give N value as 0x8000 that
8086          * should be acceptable by specific devices. 0x8000 is the
8087          * specified fixed N value for asynchronous clock mode,
8088          * which the devices expect also in synchronous clock mode.
8089          */
8090         if (constant_n)
8091                 *ret_n = 0x8000;
8092         else
8093                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8094
8095         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8096         intel_reduce_m_n_ratio(ret_m, ret_n);
8097 }
8098
8099 void
8100 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8101                        int pixel_clock, int link_clock,
8102                        struct intel_link_m_n *m_n,
8103                        bool constant_n, bool fec_enable)
8104 {
8105         u32 data_clock = bits_per_pixel * pixel_clock;
8106
8107         if (fec_enable)
8108                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8109
8110         m_n->tu = 64;
8111         compute_m_n(data_clock,
8112                     link_clock * nlanes * 8,
8113                     &m_n->gmch_m, &m_n->gmch_n,
8114                     constant_n);
8115
8116         compute_m_n(pixel_clock, link_clock,
8117                     &m_n->link_m, &m_n->link_n,
8118                     constant_n);
8119 }
8120
8121 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8122 {
8123         /*
8124          * There may be no VBT; and if the BIOS enabled SSC we can
8125          * just keep using it to avoid unnecessary flicker.  Whereas if the
8126          * BIOS isn't using it, don't assume it will work even if the VBT
8127          * indicates as much.
8128          */
8129         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8130                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8131                                                        PCH_DREF_CONTROL) &
8132                         DREF_SSC1_ENABLE;
8133
8134                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8135                         drm_dbg_kms(&dev_priv->drm,
8136                                     "SSC %s by BIOS, overriding VBT which says %s\n",
8137                                     enableddisabled(bios_lvds_use_ssc),
8138                                     enableddisabled(dev_priv->vbt.lvds_use_ssc));
8139                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8140                 }
8141         }
8142 }
8143
8144 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8145 {
8146         if (i915_modparams.panel_use_ssc >= 0)
8147                 return i915_modparams.panel_use_ssc != 0;
8148         return dev_priv->vbt.lvds_use_ssc
8149                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8150 }
8151
8152 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8153 {
8154         return (1 << dpll->n) << 16 | dpll->m2;
8155 }
8156
8157 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8158 {
8159         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8160 }
8161
8162 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8163                                      struct intel_crtc_state *crtc_state,
8164                                      struct dpll *reduced_clock)
8165 {
8166         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8167         u32 fp, fp2 = 0;
8168
8169         if (IS_PINEVIEW(dev_priv)) {
8170                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8171                 if (reduced_clock)
8172                         fp2 = pnv_dpll_compute_fp(reduced_clock);
8173         } else {
8174                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8175                 if (reduced_clock)
8176                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
8177         }
8178
8179         crtc_state->dpll_hw_state.fp0 = fp;
8180
8181         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8182             reduced_clock) {
8183                 crtc_state->dpll_hw_state.fp1 = fp2;
8184         } else {
8185                 crtc_state->dpll_hw_state.fp1 = fp;
8186         }
8187 }
8188
8189 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8190                 pipe)
8191 {
8192         u32 reg_val;
8193
8194         /*
8195          * PLLB opamp always calibrates to max value of 0x3f, force enable it
8196          * and set it to a reasonable value instead.
8197          */
8198         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8199         reg_val &= 0xffffff00;
8200         reg_val |= 0x00000030;
8201         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8202
8203         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8204         reg_val &= 0x00ffffff;
8205         reg_val |= 0x8c000000;
8206         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8207
8208         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8209         reg_val &= 0xffffff00;
8210         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8211
8212         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8213         reg_val &= 0x00ffffff;
8214         reg_val |= 0xb0000000;
8215         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8216 }
8217
8218 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8219                                          const struct intel_link_m_n *m_n)
8220 {
8221         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8222         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8223         enum pipe pipe = crtc->pipe;
8224
8225         intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8226                        TU_SIZE(m_n->tu) | m_n->gmch_m);
8227         intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8228         intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8229         intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8230 }
8231
8232 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8233                                  enum transcoder transcoder)
8234 {
8235         if (IS_HASWELL(dev_priv))
8236                 return transcoder == TRANSCODER_EDP;
8237
8238         /*
8239          * Strictly speaking some registers are available before
8240          * gen7, but we only support DRRS on gen7+
8241          */
8242         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8243 }
8244
8245 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8246                                          const struct intel_link_m_n *m_n,
8247                                          const struct intel_link_m_n *m2_n2)
8248 {
8249         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8250         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8251         enum pipe pipe = crtc->pipe;
8252         enum transcoder transcoder = crtc_state->cpu_transcoder;
8253
8254         if (INTEL_GEN(dev_priv) >= 5) {
8255                 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8256                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8257                 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8258                                m_n->gmch_n);
8259                 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8260                                m_n->link_m);
8261                 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8262                                m_n->link_n);
8263                 /*
8264                  *  M2_N2 registers are set only if DRRS is supported
8265                  * (to make sure the registers are not unnecessarily accessed).
8266                  */
8267                 if (m2_n2 && crtc_state->has_drrs &&
8268                     transcoder_has_m2_n2(dev_priv, transcoder)) {
8269                         intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8270                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8271                         intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8272                                        m2_n2->gmch_n);
8273                         intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8274                                        m2_n2->link_m);
8275                         intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8276                                        m2_n2->link_n);
8277                 }
8278         } else {
8279                 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8280                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8281                 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8282                 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8283                 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8284         }
8285 }
8286
8287 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8288 {
8289         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8290         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8291
8292         if (m_n == M1_N1) {
8293                 dp_m_n = &crtc_state->dp_m_n;
8294                 dp_m2_n2 = &crtc_state->dp_m2_n2;
8295         } else if (m_n == M2_N2) {
8296
8297                 /*
8298                  * M2_N2 registers are not supported. Hence m2_n2 divider value
8299                  * needs to be programmed into M1_N1.
8300                  */
8301                 dp_m_n = &crtc_state->dp_m2_n2;
8302         } else {
8303                 drm_err(&i915->drm, "Unsupported divider value\n");
8304                 return;
8305         }
8306
8307         if (crtc_state->has_pch_encoder)
8308                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8309         else
8310                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8311 }
8312
8313 static void vlv_compute_dpll(struct intel_crtc *crtc,
8314                              struct intel_crtc_state *pipe_config)
8315 {
8316         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8317                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8318         if (crtc->pipe != PIPE_A)
8319                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8320
8321         /* DPLL not used with DSI, but still need the rest set up */
8322         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8323                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8324                         DPLL_EXT_BUFFER_ENABLE_VLV;
8325
8326         pipe_config->dpll_hw_state.dpll_md =
8327                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8328 }
8329
8330 static void chv_compute_dpll(struct intel_crtc *crtc,
8331                              struct intel_crtc_state *pipe_config)
8332 {
8333         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8334                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8335         if (crtc->pipe != PIPE_A)
8336                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8337
8338         /* DPLL not used with DSI, but still need the rest set up */
8339         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8340                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8341
8342         pipe_config->dpll_hw_state.dpll_md =
8343                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8344 }
8345
8346 static void vlv_prepare_pll(struct intel_crtc *crtc,
8347                             const struct intel_crtc_state *pipe_config)
8348 {
8349         struct drm_device *dev = crtc->base.dev;
8350         struct drm_i915_private *dev_priv = to_i915(dev);
8351         enum pipe pipe = crtc->pipe;
8352         u32 mdiv;
8353         u32 bestn, bestm1, bestm2, bestp1, bestp2;
8354         u32 coreclk, reg_val;
8355
8356         /* Enable Refclk */
8357         intel_de_write(dev_priv, DPLL(pipe),
8358                        pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8359
8360         /* No need to actually set up the DPLL with DSI */
8361         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8362                 return;
8363
8364         vlv_dpio_get(dev_priv);
8365
8366         bestn = pipe_config->dpll.n;
8367         bestm1 = pipe_config->dpll.m1;
8368         bestm2 = pipe_config->dpll.m2;
8369         bestp1 = pipe_config->dpll.p1;
8370         bestp2 = pipe_config->dpll.p2;
8371
8372         /* See eDP HDMI DPIO driver vbios notes doc */
8373
8374         /* PLL B needs special handling */
8375         if (pipe == PIPE_B)
8376                 vlv_pllb_recal_opamp(dev_priv, pipe);
8377
8378         /* Set up Tx target for periodic Rcomp update */
8379         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8380
8381         /* Disable target IRef on PLL */
8382         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8383         reg_val &= 0x00ffffff;
8384         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8385
8386         /* Disable fast lock */
8387         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8388
8389         /* Set idtafcrecal before PLL is enabled */
8390         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8391         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8392         mdiv |= ((bestn << DPIO_N_SHIFT));
8393         mdiv |= (1 << DPIO_K_SHIFT);
8394
8395         /*
8396          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8397          * but we don't support that).
8398          * Note: don't use the DAC post divider as it seems unstable.
8399          */
8400         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8401         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8402
8403         mdiv |= DPIO_ENABLE_CALIBRATION;
8404         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8405
8406         /* Set HBR and RBR LPF coefficients */
8407         if (pipe_config->port_clock == 162000 ||
8408             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8409             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8410                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8411                                  0x009f0003);
8412         else
8413                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8414                                  0x00d0000f);
8415
8416         if (intel_crtc_has_dp_encoder(pipe_config)) {
8417                 /* Use SSC source */
8418                 if (pipe == PIPE_A)
8419                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8420                                          0x0df40000);
8421                 else
8422                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8423                                          0x0df70000);
8424         } else { /* HDMI or VGA */
8425                 /* Use bend source */
8426                 if (pipe == PIPE_A)
8427                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8428                                          0x0df70000);
8429                 else
8430                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8431                                          0x0df40000);
8432         }
8433
8434         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8435         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8436         if (intel_crtc_has_dp_encoder(pipe_config))
8437                 coreclk |= 0x01000000;
8438         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8439
8440         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8441
8442         vlv_dpio_put(dev_priv);
8443 }
8444
8445 static void chv_prepare_pll(struct intel_crtc *crtc,
8446                             const struct intel_crtc_state *pipe_config)
8447 {
8448         struct drm_device *dev = crtc->base.dev;
8449         struct drm_i915_private *dev_priv = to_i915(dev);
8450         enum pipe pipe = crtc->pipe;
8451         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8452         u32 loopfilter, tribuf_calcntr;
8453         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8454         u32 dpio_val;
8455         int vco;
8456
8457         /* Enable Refclk and SSC */
8458         intel_de_write(dev_priv, DPLL(pipe),
8459                        pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8460
8461         /* No need to actually set up the DPLL with DSI */
8462         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8463                 return;
8464
8465         bestn = pipe_config->dpll.n;
8466         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8467         bestm1 = pipe_config->dpll.m1;
8468         bestm2 = pipe_config->dpll.m2 >> 22;
8469         bestp1 = pipe_config->dpll.p1;
8470         bestp2 = pipe_config->dpll.p2;
8471         vco = pipe_config->dpll.vco;
8472         dpio_val = 0;
8473         loopfilter = 0;
8474
8475         vlv_dpio_get(dev_priv);
8476
8477         /* p1 and p2 divider */
8478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8479                         5 << DPIO_CHV_S1_DIV_SHIFT |
8480                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8481                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8482                         1 << DPIO_CHV_K_DIV_SHIFT);
8483
8484         /* Feedback post-divider - m2 */
8485         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8486
8487         /* Feedback refclk divider - n and m1 */
8488         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8489                         DPIO_CHV_M1_DIV_BY_2 |
8490                         1 << DPIO_CHV_N_DIV_SHIFT);
8491
8492         /* M2 fraction division */
8493         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8494
8495         /* M2 fraction division enable */
8496         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8497         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8498         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8499         if (bestm2_frac)
8500                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8501         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8502
8503         /* Program digital lock detect threshold */
8504         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8505         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8506                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8507         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8508         if (!bestm2_frac)
8509                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8510         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8511
8512         /* Loop filter */
8513         if (vco == 5400000) {
8514                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8515                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8516                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8517                 tribuf_calcntr = 0x9;
8518         } else if (vco <= 6200000) {
8519                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8520                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8521                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8522                 tribuf_calcntr = 0x9;
8523         } else if (vco <= 6480000) {
8524                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8525                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8526                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8527                 tribuf_calcntr = 0x8;
8528         } else {
8529                 /* Not supported. Apply the same limits as in the max case */
8530                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8531                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8532                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8533                 tribuf_calcntr = 0;
8534         }
8535         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8536
8537         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8538         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8539         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8540         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8541
8542         /* AFC Recal */
8543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8544                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8545                         DPIO_AFC_RECAL);
8546
8547         vlv_dpio_put(dev_priv);
8548 }
8549
8550 /**
8551  * vlv_force_pll_on - forcibly enable just the PLL
8552  * @dev_priv: i915 private structure
8553  * @pipe: pipe PLL to enable
8554  * @dpll: PLL configuration
8555  *
8556  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8557  * in cases where we need the PLL enabled even when @pipe is not going to
8558  * be enabled.
8559  */
8560 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8561                      const struct dpll *dpll)
8562 {
8563         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8564         struct intel_crtc_state *pipe_config;
8565
8566         pipe_config = intel_crtc_state_alloc(crtc);
8567         if (!pipe_config)
8568                 return -ENOMEM;
8569
8570         pipe_config->cpu_transcoder = (enum transcoder)pipe;
8571         pipe_config->pixel_multiplier = 1;
8572         pipe_config->dpll = *dpll;
8573
8574         if (IS_CHERRYVIEW(dev_priv)) {
8575                 chv_compute_dpll(crtc, pipe_config);
8576                 chv_prepare_pll(crtc, pipe_config);
8577                 chv_enable_pll(crtc, pipe_config);
8578         } else {
8579                 vlv_compute_dpll(crtc, pipe_config);
8580                 vlv_prepare_pll(crtc, pipe_config);
8581                 vlv_enable_pll(crtc, pipe_config);
8582         }
8583
8584         kfree(pipe_config);
8585
8586         return 0;
8587 }
8588
8589 /**
8590  * vlv_force_pll_off - forcibly disable just the PLL
8591  * @dev_priv: i915 private structure
8592  * @pipe: pipe PLL to disable
8593  *
8594  * Disable the PLL for @pipe. To be used in cases where we need
8595  * the PLL enabled even when @pipe is not going to be enabled.
8596  */
8597 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8598 {
8599         if (IS_CHERRYVIEW(dev_priv))
8600                 chv_disable_pll(dev_priv, pipe);
8601         else
8602                 vlv_disable_pll(dev_priv, pipe);
8603 }
8604
8605 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8606                               struct intel_crtc_state *crtc_state,
8607                               struct dpll *reduced_clock)
8608 {
8609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8610         u32 dpll;
8611         struct dpll *clock = &crtc_state->dpll;
8612
8613         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8614
8615         dpll = DPLL_VGA_MODE_DIS;
8616
8617         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8618                 dpll |= DPLLB_MODE_LVDS;
8619         else
8620                 dpll |= DPLLB_MODE_DAC_SERIAL;
8621
8622         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8623             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8624                 dpll |= (crtc_state->pixel_multiplier - 1)
8625                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8626         }
8627
8628         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8629             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8630                 dpll |= DPLL_SDVO_HIGH_SPEED;
8631
8632         if (intel_crtc_has_dp_encoder(crtc_state))
8633                 dpll |= DPLL_SDVO_HIGH_SPEED;
8634
8635         /* compute bitmask from p1 value */
8636         if (IS_PINEVIEW(dev_priv))
8637                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8638         else {
8639                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8640                 if (IS_G4X(dev_priv) && reduced_clock)
8641                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8642         }
8643         switch (clock->p2) {
8644         case 5:
8645                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8646                 break;
8647         case 7:
8648                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8649                 break;
8650         case 10:
8651                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8652                 break;
8653         case 14:
8654                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8655                 break;
8656         }
8657         if (INTEL_GEN(dev_priv) >= 4)
8658                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8659
8660         if (crtc_state->sdvo_tv_clock)
8661                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8662         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8663                  intel_panel_use_ssc(dev_priv))
8664                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8665         else
8666                 dpll |= PLL_REF_INPUT_DREFCLK;
8667
8668         dpll |= DPLL_VCO_ENABLE;
8669         crtc_state->dpll_hw_state.dpll = dpll;
8670
8671         if (INTEL_GEN(dev_priv) >= 4) {
8672                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8673                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8674                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8675         }
8676 }
8677
8678 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8679                               struct intel_crtc_state *crtc_state,
8680                               struct dpll *reduced_clock)
8681 {
8682         struct drm_device *dev = crtc->base.dev;
8683         struct drm_i915_private *dev_priv = to_i915(dev);
8684         u32 dpll;
8685         struct dpll *clock = &crtc_state->dpll;
8686
8687         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8688
8689         dpll = DPLL_VGA_MODE_DIS;
8690
8691         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8692                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8693         } else {
8694                 if (clock->p1 == 2)
8695                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8696                 else
8697                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8698                 if (clock->p2 == 4)
8699                         dpll |= PLL_P2_DIVIDE_BY_4;
8700         }
8701
8702         /*
8703          * Bspec:
8704          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8705          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8706          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8707          *  Enable) must be set to “1” in both the DPLL A Control Register
8708          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8709          *
8710          * For simplicity We simply keep both bits always enabled in
8711          * both DPLLS. The spec says we should disable the DVO 2X clock
8712          * when not needed, but this seems to work fine in practice.
8713          */
8714         if (IS_I830(dev_priv) ||
8715             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8716                 dpll |= DPLL_DVO_2X_MODE;
8717
8718         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8719             intel_panel_use_ssc(dev_priv))
8720                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8721         else
8722                 dpll |= PLL_REF_INPUT_DREFCLK;
8723
8724         dpll |= DPLL_VCO_ENABLE;
8725         crtc_state->dpll_hw_state.dpll = dpll;
8726 }
8727
8728 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8729 {
8730         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8731         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8732         enum pipe pipe = crtc->pipe;
8733         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8734         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8735         u32 crtc_vtotal, crtc_vblank_end;
8736         int vsyncshift = 0;
8737
8738         /* We need to be careful not to changed the adjusted mode, for otherwise
8739          * the hw state checker will get angry at the mismatch. */
8740         crtc_vtotal = adjusted_mode->crtc_vtotal;
8741         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8742
8743         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8744                 /* the chip adds 2 halflines automatically */
8745                 crtc_vtotal -= 1;
8746                 crtc_vblank_end -= 1;
8747
8748                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8749                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8750                 else
8751                         vsyncshift = adjusted_mode->crtc_hsync_start -
8752                                 adjusted_mode->crtc_htotal / 2;
8753                 if (vsyncshift < 0)
8754                         vsyncshift += adjusted_mode->crtc_htotal;
8755         }
8756
8757         if (INTEL_GEN(dev_priv) > 3)
8758                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8759                                vsyncshift);
8760
8761         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8762                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8763         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8764                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8765         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8766                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8767
8768         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8769                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8770         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8771                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8772         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8773                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8774
8775         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8776          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8777          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8778          * bits. */
8779         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8780             (pipe == PIPE_B || pipe == PIPE_C))
8781                 intel_de_write(dev_priv, VTOTAL(pipe),
8782                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8783
8784 }
8785
8786 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8787 {
8788         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8789         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8790         enum pipe pipe = crtc->pipe;
8791
8792         /* pipesrc controls the size that is scaled from, which should
8793          * always be the user's requested size.
8794          */
8795         intel_de_write(dev_priv, PIPESRC(pipe),
8796                        ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8797 }
8798
8799 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8800 {
8801         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8802         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8803
8804         if (IS_GEN(dev_priv, 2))
8805                 return false;
8806
8807         if (INTEL_GEN(dev_priv) >= 9 ||
8808             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8809                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8810         else
8811                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8812 }
8813
8814 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8815                                    struct intel_crtc_state *pipe_config)
8816 {
8817         struct drm_device *dev = crtc->base.dev;
8818         struct drm_i915_private *dev_priv = to_i915(dev);
8819         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8820         u32 tmp;
8821
8822         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8823         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8824         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8825
8826         if (!transcoder_is_dsi(cpu_transcoder)) {
8827                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8828                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8829                                                         (tmp & 0xffff) + 1;
8830                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8831                                                 ((tmp >> 16) & 0xffff) + 1;
8832         }
8833         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8834         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8835         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8836
8837         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8838         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8839         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8840
8841         if (!transcoder_is_dsi(cpu_transcoder)) {
8842                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8843                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8844                                                         (tmp & 0xffff) + 1;
8845                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8846                                                 ((tmp >> 16) & 0xffff) + 1;
8847         }
8848         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8849         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8850         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8851
8852         if (intel_pipe_is_interlaced(pipe_config)) {
8853                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8854                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8855                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8856         }
8857 }
8858
8859 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8860                                     struct intel_crtc_state *pipe_config)
8861 {
8862         struct drm_device *dev = crtc->base.dev;
8863         struct drm_i915_private *dev_priv = to_i915(dev);
8864         u32 tmp;
8865
8866         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
8867         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8868         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8869
8870         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8871         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8872 }
8873
8874 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8875                                  struct intel_crtc_state *pipe_config)
8876 {
8877         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8878         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8879         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8880         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8881
8882         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8883         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8884         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8885         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8886
8887         mode->flags = pipe_config->hw.adjusted_mode.flags;
8888         mode->type = DRM_MODE_TYPE_DRIVER;
8889
8890         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8891
8892         mode->hsync = drm_mode_hsync(mode);
8893         mode->vrefresh = drm_mode_vrefresh(mode);
8894         drm_mode_set_name(mode);
8895 }
8896
8897 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8898 {
8899         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8900         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8901         u32 pipeconf;
8902
8903         pipeconf = 0;
8904
8905         /* we keep both pipes enabled on 830 */
8906         if (IS_I830(dev_priv))
8907                 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8908
8909         if (crtc_state->double_wide)
8910                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8911
8912         /* only g4x and later have fancy bpc/dither controls */
8913         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8914             IS_CHERRYVIEW(dev_priv)) {
8915                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8916                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8917                         pipeconf |= PIPECONF_DITHER_EN |
8918                                     PIPECONF_DITHER_TYPE_SP;
8919
8920                 switch (crtc_state->pipe_bpp) {
8921                 case 18:
8922                         pipeconf |= PIPECONF_6BPC;
8923                         break;
8924                 case 24:
8925                         pipeconf |= PIPECONF_8BPC;
8926                         break;
8927                 case 30:
8928                         pipeconf |= PIPECONF_10BPC;
8929                         break;
8930                 default:
8931                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8932                         BUG();
8933                 }
8934         }
8935
8936         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8937                 if (INTEL_GEN(dev_priv) < 4 ||
8938                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8939                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8940                 else
8941                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8942         } else {
8943                 pipeconf |= PIPECONF_PROGRESSIVE;
8944         }
8945
8946         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8947              crtc_state->limited_color_range)
8948                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8949
8950         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8951
8952         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8953
8954         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
8955         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
8956 }
8957
8958 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8959                                    struct intel_crtc_state *crtc_state)
8960 {
8961         struct drm_device *dev = crtc->base.dev;
8962         struct drm_i915_private *dev_priv = to_i915(dev);
8963         const struct intel_limit *limit;
8964         int refclk = 48000;
8965
8966         memset(&crtc_state->dpll_hw_state, 0,
8967                sizeof(crtc_state->dpll_hw_state));
8968
8969         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8970                 if (intel_panel_use_ssc(dev_priv)) {
8971                         refclk = dev_priv->vbt.lvds_ssc_freq;
8972                         drm_dbg_kms(&dev_priv->drm,
8973                                     "using SSC reference clock of %d kHz\n",
8974                                     refclk);
8975                 }
8976
8977                 limit = &intel_limits_i8xx_lvds;
8978         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8979                 limit = &intel_limits_i8xx_dvo;
8980         } else {
8981                 limit = &intel_limits_i8xx_dac;
8982         }
8983
8984         if (!crtc_state->clock_set &&
8985             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8986                                  refclk, NULL, &crtc_state->dpll)) {
8987                 drm_err(&dev_priv->drm,
8988                         "Couldn't find PLL settings for mode!\n");
8989                 return -EINVAL;
8990         }
8991
8992         i8xx_compute_dpll(crtc, crtc_state, NULL);
8993
8994         return 0;
8995 }
8996
8997 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8998                                   struct intel_crtc_state *crtc_state)
8999 {
9000         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9001         const struct intel_limit *limit;
9002         int refclk = 96000;
9003
9004         memset(&crtc_state->dpll_hw_state, 0,
9005                sizeof(crtc_state->dpll_hw_state));
9006
9007         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9008                 if (intel_panel_use_ssc(dev_priv)) {
9009                         refclk = dev_priv->vbt.lvds_ssc_freq;
9010                         drm_dbg_kms(&dev_priv->drm,
9011                                     "using SSC reference clock of %d kHz\n",
9012                                     refclk);
9013                 }
9014
9015                 if (intel_is_dual_link_lvds(dev_priv))
9016                         limit = &intel_limits_g4x_dual_channel_lvds;
9017                 else
9018                         limit = &intel_limits_g4x_single_channel_lvds;
9019         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9020                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9021                 limit = &intel_limits_g4x_hdmi;
9022         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9023                 limit = &intel_limits_g4x_sdvo;
9024         } else {
9025                 /* The option is for other outputs */
9026                 limit = &intel_limits_i9xx_sdvo;
9027         }
9028
9029         if (!crtc_state->clock_set &&
9030             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9031                                 refclk, NULL, &crtc_state->dpll)) {
9032                 drm_err(&dev_priv->drm,
9033                         "Couldn't find PLL settings for mode!\n");
9034                 return -EINVAL;
9035         }
9036
9037         i9xx_compute_dpll(crtc, crtc_state, NULL);
9038
9039         return 0;
9040 }
9041
9042 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9043                                   struct intel_crtc_state *crtc_state)
9044 {
9045         struct drm_device *dev = crtc->base.dev;
9046         struct drm_i915_private *dev_priv = to_i915(dev);
9047         const struct intel_limit *limit;
9048         int refclk = 96000;
9049
9050         memset(&crtc_state->dpll_hw_state, 0,
9051                sizeof(crtc_state->dpll_hw_state));
9052
9053         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9054                 if (intel_panel_use_ssc(dev_priv)) {
9055                         refclk = dev_priv->vbt.lvds_ssc_freq;
9056                         drm_dbg_kms(&dev_priv->drm,
9057                                     "using SSC reference clock of %d kHz\n",
9058                                     refclk);
9059                 }
9060
9061                 limit = &pnv_limits_lvds;
9062         } else {
9063                 limit = &pnv_limits_sdvo;
9064         }
9065
9066         if (!crtc_state->clock_set &&
9067             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9068                                 refclk, NULL, &crtc_state->dpll)) {
9069                 drm_err(&dev_priv->drm,
9070                         "Couldn't find PLL settings for mode!\n");
9071                 return -EINVAL;
9072         }
9073
9074         i9xx_compute_dpll(crtc, crtc_state, NULL);
9075
9076         return 0;
9077 }
9078
9079 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9080                                    struct intel_crtc_state *crtc_state)
9081 {
9082         struct drm_device *dev = crtc->base.dev;
9083         struct drm_i915_private *dev_priv = to_i915(dev);
9084         const struct intel_limit *limit;
9085         int refclk = 96000;
9086
9087         memset(&crtc_state->dpll_hw_state, 0,
9088                sizeof(crtc_state->dpll_hw_state));
9089
9090         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9091                 if (intel_panel_use_ssc(dev_priv)) {
9092                         refclk = dev_priv->vbt.lvds_ssc_freq;
9093                         drm_dbg_kms(&dev_priv->drm,
9094                                     "using SSC reference clock of %d kHz\n",
9095                                     refclk);
9096                 }
9097
9098                 limit = &intel_limits_i9xx_lvds;
9099         } else {
9100                 limit = &intel_limits_i9xx_sdvo;
9101         }
9102
9103         if (!crtc_state->clock_set &&
9104             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9105                                  refclk, NULL, &crtc_state->dpll)) {
9106                 drm_err(&dev_priv->drm,
9107                         "Couldn't find PLL settings for mode!\n");
9108                 return -EINVAL;
9109         }
9110
9111         i9xx_compute_dpll(crtc, crtc_state, NULL);
9112
9113         return 0;
9114 }
9115
9116 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9117                                   struct intel_crtc_state *crtc_state)
9118 {
9119         int refclk = 100000;
9120         const struct intel_limit *limit = &intel_limits_chv;
9121         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9122
9123         memset(&crtc_state->dpll_hw_state, 0,
9124                sizeof(crtc_state->dpll_hw_state));
9125
9126         if (!crtc_state->clock_set &&
9127             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9128                                 refclk, NULL, &crtc_state->dpll)) {
9129                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9130                 return -EINVAL;
9131         }
9132
9133         chv_compute_dpll(crtc, crtc_state);
9134
9135         return 0;
9136 }
9137
9138 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9139                                   struct intel_crtc_state *crtc_state)
9140 {
9141         int refclk = 100000;
9142         const struct intel_limit *limit = &intel_limits_vlv;
9143         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9144
9145         memset(&crtc_state->dpll_hw_state, 0,
9146                sizeof(crtc_state->dpll_hw_state));
9147
9148         if (!crtc_state->clock_set &&
9149             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9150                                 refclk, NULL, &crtc_state->dpll)) {
9151                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
9152                 return -EINVAL;
9153         }
9154
9155         vlv_compute_dpll(crtc, crtc_state);
9156
9157         return 0;
9158 }
9159
9160 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9161 {
9162         if (IS_I830(dev_priv))
9163                 return false;
9164
9165         return INTEL_GEN(dev_priv) >= 4 ||
9166                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9167 }
9168
9169 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9170 {
9171         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9172         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9173         u32 tmp;
9174
9175         if (!i9xx_has_pfit(dev_priv))
9176                 return;
9177
9178         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9179         if (!(tmp & PFIT_ENABLE))
9180                 return;
9181
9182         /* Check whether the pfit is attached to our pipe. */
9183         if (INTEL_GEN(dev_priv) < 4) {
9184                 if (crtc->pipe != PIPE_B)
9185                         return;
9186         } else {
9187                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9188                         return;
9189         }
9190
9191         crtc_state->gmch_pfit.control = tmp;
9192         crtc_state->gmch_pfit.pgm_ratios =
9193                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9194 }
9195
9196 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9197                                struct intel_crtc_state *pipe_config)
9198 {
9199         struct drm_device *dev = crtc->base.dev;
9200         struct drm_i915_private *dev_priv = to_i915(dev);
9201         enum pipe pipe = crtc->pipe;
9202         struct dpll clock;
9203         u32 mdiv;
9204         int refclk = 100000;
9205
9206         /* In case of DSI, DPLL will not be used */
9207         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9208                 return;
9209
9210         vlv_dpio_get(dev_priv);
9211         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9212         vlv_dpio_put(dev_priv);
9213
9214         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9215         clock.m2 = mdiv & DPIO_M2DIV_MASK;
9216         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9217         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9218         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9219
9220         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9221 }
9222
9223 static void
9224 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9225                               struct intel_initial_plane_config *plane_config)
9226 {
9227         struct drm_device *dev = crtc->base.dev;
9228         struct drm_i915_private *dev_priv = to_i915(dev);
9229         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9230         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9231         enum pipe pipe;
9232         u32 val, base, offset;
9233         int fourcc, pixel_format;
9234         unsigned int aligned_height;
9235         struct drm_framebuffer *fb;
9236         struct intel_framebuffer *intel_fb;
9237
9238         if (!plane->get_hw_state(plane, &pipe))
9239                 return;
9240
9241         drm_WARN_ON(dev, pipe != crtc->pipe);
9242
9243         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9244         if (!intel_fb) {
9245                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9246                 return;
9247         }
9248
9249         fb = &intel_fb->base;
9250
9251         fb->dev = dev;
9252
9253         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9254
9255         if (INTEL_GEN(dev_priv) >= 4) {
9256                 if (val & DISPPLANE_TILED) {
9257                         plane_config->tiling = I915_TILING_X;
9258                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9259                 }
9260
9261                 if (val & DISPPLANE_ROTATE_180)
9262                         plane_config->rotation = DRM_MODE_ROTATE_180;
9263         }
9264
9265         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9266             val & DISPPLANE_MIRROR)
9267                 plane_config->rotation |= DRM_MODE_REFLECT_X;
9268
9269         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9270         fourcc = i9xx_format_to_fourcc(pixel_format);
9271         fb->format = drm_format_info(fourcc);
9272
9273         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9274                 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9275                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9276         } else if (INTEL_GEN(dev_priv) >= 4) {
9277                 if (plane_config->tiling)
9278                         offset = intel_de_read(dev_priv,
9279                                                DSPTILEOFF(i9xx_plane));
9280                 else
9281                         offset = intel_de_read(dev_priv,
9282                                                DSPLINOFF(i9xx_plane));
9283                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9284         } else {
9285                 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9286         }
9287         plane_config->base = base;
9288
9289         val = intel_de_read(dev_priv, PIPESRC(pipe));
9290         fb->width = ((val >> 16) & 0xfff) + 1;
9291         fb->height = ((val >> 0) & 0xfff) + 1;
9292
9293         val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9294         fb->pitches[0] = val & 0xffffffc0;
9295
9296         aligned_height = intel_fb_align_height(fb, 0, fb->height);
9297
9298         plane_config->size = fb->pitches[0] * aligned_height;
9299
9300         drm_dbg_kms(&dev_priv->drm,
9301                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9302                     crtc->base.name, plane->base.name, fb->width, fb->height,
9303                     fb->format->cpp[0] * 8, base, fb->pitches[0],
9304                     plane_config->size);
9305
9306         plane_config->fb = intel_fb;
9307 }
9308
9309 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9310                                struct intel_crtc_state *pipe_config)
9311 {
9312         struct drm_device *dev = crtc->base.dev;
9313         struct drm_i915_private *dev_priv = to_i915(dev);
9314         enum pipe pipe = crtc->pipe;
9315         enum dpio_channel port = vlv_pipe_to_channel(pipe);
9316         struct dpll clock;
9317         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9318         int refclk = 100000;
9319
9320         /* In case of DSI, DPLL will not be used */
9321         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9322                 return;
9323
9324         vlv_dpio_get(dev_priv);
9325         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9326         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9327         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9328         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9329         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9330         vlv_dpio_put(dev_priv);
9331
9332         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9333         clock.m2 = (pll_dw0 & 0xff) << 22;
9334         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9335                 clock.m2 |= pll_dw2 & 0x3fffff;
9336         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9337         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9338         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9339
9340         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9341 }
9342
9343 static enum intel_output_format
9344 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9345 {
9346         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9347         u32 tmp;
9348
9349         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9350
9351         if (tmp & PIPEMISC_YUV420_ENABLE) {
9352                 /* We support 4:2:0 in full blend mode only */
9353                 drm_WARN_ON(&dev_priv->drm,
9354                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9355
9356                 return INTEL_OUTPUT_FORMAT_YCBCR420;
9357         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9358                 return INTEL_OUTPUT_FORMAT_YCBCR444;
9359         } else {
9360                 return INTEL_OUTPUT_FORMAT_RGB;
9361         }
9362 }
9363
9364 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9365 {
9366         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9367         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9368         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9369         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9370         u32 tmp;
9371
9372         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9373
9374         if (tmp & DISPPLANE_GAMMA_ENABLE)
9375                 crtc_state->gamma_enable = true;
9376
9377         if (!HAS_GMCH(dev_priv) &&
9378             tmp & DISPPLANE_PIPE_CSC_ENABLE)
9379                 crtc_state->csc_enable = true;
9380 }
9381
9382 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9383                                  struct intel_crtc_state *pipe_config)
9384 {
9385         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9386         enum intel_display_power_domain power_domain;
9387         intel_wakeref_t wakeref;
9388         u32 tmp;
9389         bool ret;
9390
9391         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9392         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9393         if (!wakeref)
9394                 return false;
9395
9396         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9397         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9398         pipe_config->shared_dpll = NULL;
9399
9400         ret = false;
9401
9402         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9403         if (!(tmp & PIPECONF_ENABLE))
9404                 goto out;
9405
9406         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9407             IS_CHERRYVIEW(dev_priv)) {
9408                 switch (tmp & PIPECONF_BPC_MASK) {
9409                 case PIPECONF_6BPC:
9410                         pipe_config->pipe_bpp = 18;
9411                         break;
9412                 case PIPECONF_8BPC:
9413                         pipe_config->pipe_bpp = 24;
9414                         break;
9415                 case PIPECONF_10BPC:
9416                         pipe_config->pipe_bpp = 30;
9417                         break;
9418                 default:
9419                         break;
9420                 }
9421         }
9422
9423         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9424             (tmp & PIPECONF_COLOR_RANGE_SELECT))
9425                 pipe_config->limited_color_range = true;
9426
9427         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9428                 PIPECONF_GAMMA_MODE_SHIFT;
9429
9430         if (IS_CHERRYVIEW(dev_priv))
9431                 pipe_config->cgm_mode = intel_de_read(dev_priv,
9432                                                       CGM_PIPE_MODE(crtc->pipe));
9433
9434         i9xx_get_pipe_color_config(pipe_config);
9435         intel_color_get_config(pipe_config);
9436
9437         if (INTEL_GEN(dev_priv) < 4)
9438                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9439
9440         intel_get_pipe_timings(crtc, pipe_config);
9441         intel_get_pipe_src_size(crtc, pipe_config);
9442
9443         i9xx_get_pfit_config(pipe_config);
9444
9445         if (INTEL_GEN(dev_priv) >= 4) {
9446                 /* No way to read it out on pipes B and C */
9447                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9448                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
9449                 else
9450                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9451                 pipe_config->pixel_multiplier =
9452                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9453                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9454                 pipe_config->dpll_hw_state.dpll_md = tmp;
9455         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9456                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9457                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9458                 pipe_config->pixel_multiplier =
9459                         ((tmp & SDVO_MULTIPLIER_MASK)
9460                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9461         } else {
9462                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9463                  * port and will be fixed up in the encoder->get_config
9464                  * function. */
9465                 pipe_config->pixel_multiplier = 1;
9466         }
9467         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9468                                                         DPLL(crtc->pipe));
9469         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9470                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9471                                                                FP0(crtc->pipe));
9472                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9473                                                                FP1(crtc->pipe));
9474         } else {
9475                 /* Mask out read-only status bits. */
9476                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9477                                                      DPLL_PORTC_READY_MASK |
9478                                                      DPLL_PORTB_READY_MASK);
9479         }
9480
9481         if (IS_CHERRYVIEW(dev_priv))
9482                 chv_crtc_clock_get(crtc, pipe_config);
9483         else if (IS_VALLEYVIEW(dev_priv))
9484                 vlv_crtc_clock_get(crtc, pipe_config);
9485         else
9486                 i9xx_crtc_clock_get(crtc, pipe_config);
9487
9488         /*
9489          * Normally the dotclock is filled in by the encoder .get_config()
9490          * but in case the pipe is enabled w/o any ports we need a sane
9491          * default.
9492          */
9493         pipe_config->hw.adjusted_mode.crtc_clock =
9494                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9495
9496         ret = true;
9497
9498 out:
9499         intel_display_power_put(dev_priv, power_domain, wakeref);
9500
9501         return ret;
9502 }
9503
9504 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9505 {
9506         struct intel_encoder *encoder;
9507         int i;
9508         u32 val, final;
9509         bool has_lvds = false;
9510         bool has_cpu_edp = false;
9511         bool has_panel = false;
9512         bool has_ck505 = false;
9513         bool can_ssc = false;
9514         bool using_ssc_source = false;
9515
9516         /* We need to take the global config into account */
9517         for_each_intel_encoder(&dev_priv->drm, encoder) {
9518                 switch (encoder->type) {
9519                 case INTEL_OUTPUT_LVDS:
9520                         has_panel = true;
9521                         has_lvds = true;
9522                         break;
9523                 case INTEL_OUTPUT_EDP:
9524                         has_panel = true;
9525                         if (encoder->port == PORT_A)
9526                                 has_cpu_edp = true;
9527                         break;
9528                 default:
9529                         break;
9530                 }
9531         }
9532
9533         if (HAS_PCH_IBX(dev_priv)) {
9534                 has_ck505 = dev_priv->vbt.display_clock_mode;
9535                 can_ssc = has_ck505;
9536         } else {
9537                 has_ck505 = false;
9538                 can_ssc = true;
9539         }
9540
9541         /* Check if any DPLLs are using the SSC source */
9542         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9543                 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9544
9545                 if (!(temp & DPLL_VCO_ENABLE))
9546                         continue;
9547
9548                 if ((temp & PLL_REF_INPUT_MASK) ==
9549                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9550                         using_ssc_source = true;
9551                         break;
9552                 }
9553         }
9554
9555         drm_dbg_kms(&dev_priv->drm,
9556                     "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9557                     has_panel, has_lvds, has_ck505, using_ssc_source);
9558
9559         /* Ironlake: try to setup display ref clock before DPLL
9560          * enabling. This is only under driver's control after
9561          * PCH B stepping, previous chipset stepping should be
9562          * ignoring this setting.
9563          */
9564         val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9565
9566         /* As we must carefully and slowly disable/enable each source in turn,
9567          * compute the final state we want first and check if we need to
9568          * make any changes at all.
9569          */
9570         final = val;
9571         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9572         if (has_ck505)
9573                 final |= DREF_NONSPREAD_CK505_ENABLE;
9574         else
9575                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9576
9577         final &= ~DREF_SSC_SOURCE_MASK;
9578         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9579         final &= ~DREF_SSC1_ENABLE;
9580
9581         if (has_panel) {
9582                 final |= DREF_SSC_SOURCE_ENABLE;
9583
9584                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9585                         final |= DREF_SSC1_ENABLE;
9586
9587                 if (has_cpu_edp) {
9588                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9589                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9590                         else
9591                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9592                 } else
9593                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9594         } else if (using_ssc_source) {
9595                 final |= DREF_SSC_SOURCE_ENABLE;
9596                 final |= DREF_SSC1_ENABLE;
9597         }
9598
9599         if (final == val)
9600                 return;
9601
9602         /* Always enable nonspread source */
9603         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9604
9605         if (has_ck505)
9606                 val |= DREF_NONSPREAD_CK505_ENABLE;
9607         else
9608                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9609
9610         if (has_panel) {
9611                 val &= ~DREF_SSC_SOURCE_MASK;
9612                 val |= DREF_SSC_SOURCE_ENABLE;
9613
9614                 /* SSC must be turned on before enabling the CPU output  */
9615                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9616                         drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9617                         val |= DREF_SSC1_ENABLE;
9618                 } else
9619                         val &= ~DREF_SSC1_ENABLE;
9620
9621                 /* Get SSC going before enabling the outputs */
9622                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9623                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9624                 udelay(200);
9625
9626                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9627
9628                 /* Enable CPU source on CPU attached eDP */
9629                 if (has_cpu_edp) {
9630                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9631                                 drm_dbg_kms(&dev_priv->drm,
9632                                             "Using SSC on eDP\n");
9633                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9634                         } else
9635                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9636                 } else
9637                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9638
9639                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9640                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9641                 udelay(200);
9642         } else {
9643                 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9644
9645                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9646
9647                 /* Turn off CPU output */
9648                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9649
9650                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9651                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9652                 udelay(200);
9653
9654                 if (!using_ssc_source) {
9655                         drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9656
9657                         /* Turn off the SSC source */
9658                         val &= ~DREF_SSC_SOURCE_MASK;
9659                         val |= DREF_SSC_SOURCE_DISABLE;
9660
9661                         /* Turn off SSC1 */
9662                         val &= ~DREF_SSC1_ENABLE;
9663
9664                         intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9665                         intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9666                         udelay(200);
9667                 }
9668         }
9669
9670         BUG_ON(val != final);
9671 }
9672
9673 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9674 {
9675         u32 tmp;
9676
9677         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9678         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9679         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9680
9681         if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9682                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9683                 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9684
9685         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9686         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9687         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9688
9689         if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9690                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9691                 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9692 }
9693
9694 /* WaMPhyProgramming:hsw */
9695 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9696 {
9697         u32 tmp;
9698
9699         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9700         tmp &= ~(0xFF << 24);
9701         tmp |= (0x12 << 24);
9702         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9703
9704         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9705         tmp |= (1 << 11);
9706         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9707
9708         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9709         tmp |= (1 << 11);
9710         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9711
9712         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9713         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9714         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9715
9716         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9717         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9718         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9719
9720         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9721         tmp &= ~(7 << 13);
9722         tmp |= (5 << 13);
9723         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9724
9725         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9726         tmp &= ~(7 << 13);
9727         tmp |= (5 << 13);
9728         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9729
9730         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9731         tmp &= ~0xFF;
9732         tmp |= 0x1C;
9733         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9734
9735         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9736         tmp &= ~0xFF;
9737         tmp |= 0x1C;
9738         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9739
9740         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9741         tmp &= ~(0xFF << 16);
9742         tmp |= (0x1C << 16);
9743         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9744
9745         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9746         tmp &= ~(0xFF << 16);
9747         tmp |= (0x1C << 16);
9748         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9749
9750         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9751         tmp |= (1 << 27);
9752         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9753
9754         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9755         tmp |= (1 << 27);
9756         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9757
9758         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9759         tmp &= ~(0xF << 28);
9760         tmp |= (4 << 28);
9761         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9762
9763         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9764         tmp &= ~(0xF << 28);
9765         tmp |= (4 << 28);
9766         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9767 }
9768
9769 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9770  * Programming" based on the parameters passed:
9771  * - Sequence to enable CLKOUT_DP
9772  * - Sequence to enable CLKOUT_DP without spread
9773  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9774  */
9775 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9776                                  bool with_spread, bool with_fdi)
9777 {
9778         u32 reg, tmp;
9779
9780         if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9781                      "FDI requires downspread\n"))
9782                 with_spread = true;
9783         if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9784                      with_fdi, "LP PCH doesn't have FDI\n"))
9785                 with_fdi = false;
9786
9787         mutex_lock(&dev_priv->sb_lock);
9788
9789         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9790         tmp &= ~SBI_SSCCTL_DISABLE;
9791         tmp |= SBI_SSCCTL_PATHALT;
9792         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9793
9794         udelay(24);
9795
9796         if (with_spread) {
9797                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9798                 tmp &= ~SBI_SSCCTL_PATHALT;
9799                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9800
9801                 if (with_fdi) {
9802                         lpt_reset_fdi_mphy(dev_priv);
9803                         lpt_program_fdi_mphy(dev_priv);
9804                 }
9805         }
9806
9807         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9808         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9809         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9810         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9811
9812         mutex_unlock(&dev_priv->sb_lock);
9813 }
9814
9815 /* Sequence to disable CLKOUT_DP */
9816 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9817 {
9818         u32 reg, tmp;
9819
9820         mutex_lock(&dev_priv->sb_lock);
9821
9822         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9823         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9824         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9825         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9826
9827         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9828         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9829                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9830                         tmp |= SBI_SSCCTL_PATHALT;
9831                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9832                         udelay(32);
9833                 }
9834                 tmp |= SBI_SSCCTL_DISABLE;
9835                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9836         }
9837
9838         mutex_unlock(&dev_priv->sb_lock);
9839 }
9840
9841 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9842
9843 static const u16 sscdivintphase[] = {
9844         [BEND_IDX( 50)] = 0x3B23,
9845         [BEND_IDX( 45)] = 0x3B23,
9846         [BEND_IDX( 40)] = 0x3C23,
9847         [BEND_IDX( 35)] = 0x3C23,
9848         [BEND_IDX( 30)] = 0x3D23,
9849         [BEND_IDX( 25)] = 0x3D23,
9850         [BEND_IDX( 20)] = 0x3E23,
9851         [BEND_IDX( 15)] = 0x3E23,
9852         [BEND_IDX( 10)] = 0x3F23,
9853         [BEND_IDX(  5)] = 0x3F23,
9854         [BEND_IDX(  0)] = 0x0025,
9855         [BEND_IDX( -5)] = 0x0025,
9856         [BEND_IDX(-10)] = 0x0125,
9857         [BEND_IDX(-15)] = 0x0125,
9858         [BEND_IDX(-20)] = 0x0225,
9859         [BEND_IDX(-25)] = 0x0225,
9860         [BEND_IDX(-30)] = 0x0325,
9861         [BEND_IDX(-35)] = 0x0325,
9862         [BEND_IDX(-40)] = 0x0425,
9863         [BEND_IDX(-45)] = 0x0425,
9864         [BEND_IDX(-50)] = 0x0525,
9865 };
9866
9867 /*
9868  * Bend CLKOUT_DP
9869  * steps -50 to 50 inclusive, in steps of 5
9870  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9871  * change in clock period = -(steps / 10) * 5.787 ps
9872  */
9873 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9874 {
9875         u32 tmp;
9876         int idx = BEND_IDX(steps);
9877
9878         if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
9879                 return;
9880
9881         if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
9882                 return;
9883
9884         mutex_lock(&dev_priv->sb_lock);
9885
9886         if (steps % 10 != 0)
9887                 tmp = 0xAAAAAAAB;
9888         else
9889                 tmp = 0x00000000;
9890         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9891
9892         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9893         tmp &= 0xffff0000;
9894         tmp |= sscdivintphase[idx];
9895         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9896
9897         mutex_unlock(&dev_priv->sb_lock);
9898 }
9899
9900 #undef BEND_IDX
9901
9902 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9903 {
9904         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9905         u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
9906
9907         if ((ctl & SPLL_PLL_ENABLE) == 0)
9908                 return false;
9909
9910         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9911             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9912                 return true;
9913
9914         if (IS_BROADWELL(dev_priv) &&
9915             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9916                 return true;
9917
9918         return false;
9919 }
9920
9921 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9922                                enum intel_dpll_id id)
9923 {
9924         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9925         u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
9926
9927         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9928                 return false;
9929
9930         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9931                 return true;
9932
9933         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9934             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9935             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9936                 return true;
9937
9938         return false;
9939 }
9940
9941 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9942 {
9943         struct intel_encoder *encoder;
9944         bool has_fdi = false;
9945
9946         for_each_intel_encoder(&dev_priv->drm, encoder) {
9947                 switch (encoder->type) {
9948                 case INTEL_OUTPUT_ANALOG:
9949                         has_fdi = true;
9950                         break;
9951                 default:
9952                         break;
9953                 }
9954         }
9955
9956         /*
9957          * The BIOS may have decided to use the PCH SSC
9958          * reference so we must not disable it until the
9959          * relevant PLLs have stopped relying on it. We'll
9960          * just leave the PCH SSC reference enabled in case
9961          * any active PLL is using it. It will get disabled
9962          * after runtime suspend if we don't have FDI.
9963          *
9964          * TODO: Move the whole reference clock handling
9965          * to the modeset sequence proper so that we can
9966          * actually enable/disable/reconfigure these things
9967          * safely. To do that we need to introduce a real
9968          * clock hierarchy. That would also allow us to do
9969          * clock bending finally.
9970          */
9971         dev_priv->pch_ssc_use = 0;
9972
9973         if (spll_uses_pch_ssc(dev_priv)) {
9974                 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
9975                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9976         }
9977
9978         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9979                 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
9980                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9981         }
9982
9983         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9984                 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
9985                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9986         }
9987
9988         if (dev_priv->pch_ssc_use)
9989                 return;
9990
9991         if (has_fdi) {
9992                 lpt_bend_clkout_dp(dev_priv, 0);
9993                 lpt_enable_clkout_dp(dev_priv, true, true);
9994         } else {
9995                 lpt_disable_clkout_dp(dev_priv);
9996         }
9997 }
9998
9999 /*
10000  * Initialize reference clocks when the driver loads
10001  */
10002 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10003 {
10004         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10005                 ilk_init_pch_refclk(dev_priv);
10006         else if (HAS_PCH_LPT(dev_priv))
10007                 lpt_init_pch_refclk(dev_priv);
10008 }
10009
10010 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10011 {
10012         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10013         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10014         enum pipe pipe = crtc->pipe;
10015         u32 val;
10016
10017         val = 0;
10018
10019         switch (crtc_state->pipe_bpp) {
10020         case 18:
10021                 val |= PIPECONF_6BPC;
10022                 break;
10023         case 24:
10024                 val |= PIPECONF_8BPC;
10025                 break;
10026         case 30:
10027                 val |= PIPECONF_10BPC;
10028                 break;
10029         case 36:
10030                 val |= PIPECONF_12BPC;
10031                 break;
10032         default:
10033                 /* Case prevented by intel_choose_pipe_bpp_dither. */
10034                 BUG();
10035         }
10036
10037         if (crtc_state->dither)
10038                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10039
10040         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10041                 val |= PIPECONF_INTERLACED_ILK;
10042         else
10043                 val |= PIPECONF_PROGRESSIVE;
10044
10045         /*
10046          * This would end up with an odd purple hue over
10047          * the entire display. Make sure we don't do it.
10048          */
10049         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10050                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10051
10052         if (crtc_state->limited_color_range)
10053                 val |= PIPECONF_COLOR_RANGE_SELECT;
10054
10055         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10056                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10057
10058         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10059
10060         val |= PIPECONF_FRAME_START_DELAY(0);
10061
10062         intel_de_write(dev_priv, PIPECONF(pipe), val);
10063         intel_de_posting_read(dev_priv, PIPECONF(pipe));
10064 }
10065
10066 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10067 {
10068         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10069         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10070         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10071         u32 val = 0;
10072
10073         if (IS_HASWELL(dev_priv) && crtc_state->dither)
10074                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10075
10076         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10077                 val |= PIPECONF_INTERLACED_ILK;
10078         else
10079                 val |= PIPECONF_PROGRESSIVE;
10080
10081         if (IS_HASWELL(dev_priv) &&
10082             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10083                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10084
10085         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10086         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10087 }
10088
10089 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10090 {
10091         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10092         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10093         u32 val = 0;
10094
10095         switch (crtc_state->pipe_bpp) {
10096         case 18:
10097                 val |= PIPEMISC_DITHER_6_BPC;
10098                 break;
10099         case 24:
10100                 val |= PIPEMISC_DITHER_8_BPC;
10101                 break;
10102         case 30:
10103                 val |= PIPEMISC_DITHER_10_BPC;
10104                 break;
10105         case 36:
10106                 val |= PIPEMISC_DITHER_12_BPC;
10107                 break;
10108         default:
10109                 MISSING_CASE(crtc_state->pipe_bpp);
10110                 break;
10111         }
10112
10113         if (crtc_state->dither)
10114                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10115
10116         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10117             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10118                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10119
10120         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10121                 val |= PIPEMISC_YUV420_ENABLE |
10122                         PIPEMISC_YUV420_MODE_FULL_BLEND;
10123
10124         if (INTEL_GEN(dev_priv) >= 11 &&
10125             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10126                                            BIT(PLANE_CURSOR))) == 0)
10127                 val |= PIPEMISC_HDR_MODE_PRECISION;
10128
10129         if (INTEL_GEN(dev_priv) >= 12)
10130                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10131
10132         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10133 }
10134
10135 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10136 {
10137         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10138         u32 tmp;
10139
10140         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10141
10142         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10143         case PIPEMISC_DITHER_6_BPC:
10144                 return 18;
10145         case PIPEMISC_DITHER_8_BPC:
10146                 return 24;
10147         case PIPEMISC_DITHER_10_BPC:
10148                 return 30;
10149         case PIPEMISC_DITHER_12_BPC:
10150                 return 36;
10151         default:
10152                 MISSING_CASE(tmp);
10153                 return 0;
10154         }
10155 }
10156
10157 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10158 {
10159         /*
10160          * Account for spread spectrum to avoid
10161          * oversubscribing the link. Max center spread
10162          * is 2.5%; use 5% for safety's sake.
10163          */
10164         u32 bps = target_clock * bpp * 21 / 20;
10165         return DIV_ROUND_UP(bps, link_bw * 8);
10166 }
10167
10168 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10169 {
10170         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10171 }
10172
10173 static void ilk_compute_dpll(struct intel_crtc *crtc,
10174                              struct intel_crtc_state *crtc_state,
10175                              struct dpll *reduced_clock)
10176 {
10177         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10178         u32 dpll, fp, fp2;
10179         int factor;
10180
10181         /* Enable autotuning of the PLL clock (if permissible) */
10182         factor = 21;
10183         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10184                 if ((intel_panel_use_ssc(dev_priv) &&
10185                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
10186                     (HAS_PCH_IBX(dev_priv) &&
10187                      intel_is_dual_link_lvds(dev_priv)))
10188                         factor = 25;
10189         } else if (crtc_state->sdvo_tv_clock) {
10190                 factor = 20;
10191         }
10192
10193         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10194
10195         if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10196                 fp |= FP_CB_TUNE;
10197
10198         if (reduced_clock) {
10199                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10200
10201                 if (reduced_clock->m < factor * reduced_clock->n)
10202                         fp2 |= FP_CB_TUNE;
10203         } else {
10204                 fp2 = fp;
10205         }
10206
10207         dpll = 0;
10208
10209         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10210                 dpll |= DPLLB_MODE_LVDS;
10211         else
10212                 dpll |= DPLLB_MODE_DAC_SERIAL;
10213
10214         dpll |= (crtc_state->pixel_multiplier - 1)
10215                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10216
10217         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10218             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10219                 dpll |= DPLL_SDVO_HIGH_SPEED;
10220
10221         if (intel_crtc_has_dp_encoder(crtc_state))
10222                 dpll |= DPLL_SDVO_HIGH_SPEED;
10223
10224         /*
10225          * The high speed IO clock is only really required for
10226          * SDVO/HDMI/DP, but we also enable it for CRT to make it
10227          * possible to share the DPLL between CRT and HDMI. Enabling
10228          * the clock needlessly does no real harm, except use up a
10229          * bit of power potentially.
10230          *
10231          * We'll limit this to IVB with 3 pipes, since it has only two
10232          * DPLLs and so DPLL sharing is the only way to get three pipes
10233          * driving PCH ports at the same time. On SNB we could do this,
10234          * and potentially avoid enabling the second DPLL, but it's not
10235          * clear if it''s a win or loss power wise. No point in doing
10236          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10237          */
10238         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10239             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10240                 dpll |= DPLL_SDVO_HIGH_SPEED;
10241
10242         /* compute bitmask from p1 value */
10243         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10244         /* also FPA1 */
10245         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10246
10247         switch (crtc_state->dpll.p2) {
10248         case 5:
10249                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10250                 break;
10251         case 7:
10252                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10253                 break;
10254         case 10:
10255                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10256                 break;
10257         case 14:
10258                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10259                 break;
10260         }
10261
10262         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10263             intel_panel_use_ssc(dev_priv))
10264                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10265         else
10266                 dpll |= PLL_REF_INPUT_DREFCLK;
10267
10268         dpll |= DPLL_VCO_ENABLE;
10269
10270         crtc_state->dpll_hw_state.dpll = dpll;
10271         crtc_state->dpll_hw_state.fp0 = fp;
10272         crtc_state->dpll_hw_state.fp1 = fp2;
10273 }
10274
10275 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10276                                   struct intel_crtc_state *crtc_state)
10277 {
10278         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10279         struct intel_atomic_state *state =
10280                 to_intel_atomic_state(crtc_state->uapi.state);
10281         const struct intel_limit *limit;
10282         int refclk = 120000;
10283
10284         memset(&crtc_state->dpll_hw_state, 0,
10285                sizeof(crtc_state->dpll_hw_state));
10286
10287         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10288         if (!crtc_state->has_pch_encoder)
10289                 return 0;
10290
10291         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10292                 if (intel_panel_use_ssc(dev_priv)) {
10293                         drm_dbg_kms(&dev_priv->drm,
10294                                     "using SSC reference clock of %d kHz\n",
10295                                     dev_priv->vbt.lvds_ssc_freq);
10296                         refclk = dev_priv->vbt.lvds_ssc_freq;
10297                 }
10298
10299                 if (intel_is_dual_link_lvds(dev_priv)) {
10300                         if (refclk == 100000)
10301                                 limit = &ilk_limits_dual_lvds_100m;
10302                         else
10303                                 limit = &ilk_limits_dual_lvds;
10304                 } else {
10305                         if (refclk == 100000)
10306                                 limit = &ilk_limits_single_lvds_100m;
10307                         else
10308                                 limit = &ilk_limits_single_lvds;
10309                 }
10310         } else {
10311                 limit = &ilk_limits_dac;
10312         }
10313
10314         if (!crtc_state->clock_set &&
10315             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10316                                 refclk, NULL, &crtc_state->dpll)) {
10317                 drm_err(&dev_priv->drm,
10318                         "Couldn't find PLL settings for mode!\n");
10319                 return -EINVAL;
10320         }
10321
10322         ilk_compute_dpll(crtc, crtc_state, NULL);
10323
10324         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10325                 drm_dbg_kms(&dev_priv->drm,
10326                             "failed to find PLL for pipe %c\n",
10327                             pipe_name(crtc->pipe));
10328                 return -EINVAL;
10329         }
10330
10331         return 0;
10332 }
10333
10334 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10335                                          struct intel_link_m_n *m_n)
10336 {
10337         struct drm_device *dev = crtc->base.dev;
10338         struct drm_i915_private *dev_priv = to_i915(dev);
10339         enum pipe pipe = crtc->pipe;
10340
10341         m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10342         m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10343         m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10344                 & ~TU_SIZE_MASK;
10345         m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10346         m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10347                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10348 }
10349
10350 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10351                                          enum transcoder transcoder,
10352                                          struct intel_link_m_n *m_n,
10353                                          struct intel_link_m_n *m2_n2)
10354 {
10355         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10356         enum pipe pipe = crtc->pipe;
10357
10358         if (INTEL_GEN(dev_priv) >= 5) {
10359                 m_n->link_m = intel_de_read(dev_priv,
10360                                             PIPE_LINK_M1(transcoder));
10361                 m_n->link_n = intel_de_read(dev_priv,
10362                                             PIPE_LINK_N1(transcoder));
10363                 m_n->gmch_m = intel_de_read(dev_priv,
10364                                             PIPE_DATA_M1(transcoder))
10365                         & ~TU_SIZE_MASK;
10366                 m_n->gmch_n = intel_de_read(dev_priv,
10367                                             PIPE_DATA_N1(transcoder));
10368                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10369                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10370
10371                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10372                         m2_n2->link_m = intel_de_read(dev_priv,
10373                                                       PIPE_LINK_M2(transcoder));
10374                         m2_n2->link_n = intel_de_read(dev_priv,
10375                                                              PIPE_LINK_N2(transcoder));
10376                         m2_n2->gmch_m = intel_de_read(dev_priv,
10377                                                              PIPE_DATA_M2(transcoder))
10378                                         & ~TU_SIZE_MASK;
10379                         m2_n2->gmch_n = intel_de_read(dev_priv,
10380                                                              PIPE_DATA_N2(transcoder));
10381                         m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10382                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10383                 }
10384         } else {
10385                 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10386                 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10387                 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10388                         & ~TU_SIZE_MASK;
10389                 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10390                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10391                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10392         }
10393 }
10394
10395 void intel_dp_get_m_n(struct intel_crtc *crtc,
10396                       struct intel_crtc_state *pipe_config)
10397 {
10398         if (pipe_config->has_pch_encoder)
10399                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10400         else
10401                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10402                                              &pipe_config->dp_m_n,
10403                                              &pipe_config->dp_m2_n2);
10404 }
10405
10406 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10407                                    struct intel_crtc_state *pipe_config)
10408 {
10409         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10410                                      &pipe_config->fdi_m_n, NULL);
10411 }
10412
10413 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10414                                   u32 pos, u32 size)
10415 {
10416         drm_rect_init(&crtc_state->pch_pfit.dst,
10417                       pos >> 16, pos & 0xffff,
10418                       size >> 16, size & 0xffff);
10419 }
10420
10421 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10422 {
10423         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10424         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10425         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10426         int id = -1;
10427         int i;
10428
10429         /* find scaler attached to this pipe */
10430         for (i = 0; i < crtc->num_scalers; i++) {
10431                 u32 ctl, pos, size;
10432
10433                 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10434                 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10435                         continue;
10436
10437                 id = i;
10438                 crtc_state->pch_pfit.enabled = true;
10439
10440                 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10441                 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10442
10443                 ilk_get_pfit_pos_size(crtc_state, pos, size);
10444
10445                 scaler_state->scalers[i].in_use = true;
10446                 break;
10447         }
10448
10449         scaler_state->scaler_id = id;
10450         if (id >= 0)
10451                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10452         else
10453                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10454 }
10455
10456 static void
10457 skl_get_initial_plane_config(struct intel_crtc *crtc,
10458                              struct intel_initial_plane_config *plane_config)
10459 {
10460         struct drm_device *dev = crtc->base.dev;
10461         struct drm_i915_private *dev_priv = to_i915(dev);
10462         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10463         enum plane_id plane_id = plane->id;
10464         enum pipe pipe;
10465         u32 val, base, offset, stride_mult, tiling, alpha;
10466         int fourcc, pixel_format;
10467         unsigned int aligned_height;
10468         struct drm_framebuffer *fb;
10469         struct intel_framebuffer *intel_fb;
10470
10471         if (!plane->get_hw_state(plane, &pipe))
10472                 return;
10473
10474         drm_WARN_ON(dev, pipe != crtc->pipe);
10475
10476         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10477         if (!intel_fb) {
10478                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10479                 return;
10480         }
10481
10482         fb = &intel_fb->base;
10483
10484         fb->dev = dev;
10485
10486         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10487
10488         if (INTEL_GEN(dev_priv) >= 11)
10489                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10490         else
10491                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10492
10493         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10494                 alpha = intel_de_read(dev_priv,
10495                                       PLANE_COLOR_CTL(pipe, plane_id));
10496                 alpha &= PLANE_COLOR_ALPHA_MASK;
10497         } else {
10498                 alpha = val & PLANE_CTL_ALPHA_MASK;
10499         }
10500
10501         fourcc = skl_format_to_fourcc(pixel_format,
10502                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10503         fb->format = drm_format_info(fourcc);
10504
10505         tiling = val & PLANE_CTL_TILED_MASK;
10506         switch (tiling) {
10507         case PLANE_CTL_TILED_LINEAR:
10508                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10509                 break;
10510         case PLANE_CTL_TILED_X:
10511                 plane_config->tiling = I915_TILING_X;
10512                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10513                 break;
10514         case PLANE_CTL_TILED_Y:
10515                 plane_config->tiling = I915_TILING_Y;
10516                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10517                         fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10518                                 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10519                                 I915_FORMAT_MOD_Y_TILED_CCS;
10520                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10521                         fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10522                 else
10523                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10524                 break;
10525         case PLANE_CTL_TILED_YF:
10526                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10527                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10528                 else
10529                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10530                 break;
10531         default:
10532                 MISSING_CASE(tiling);
10533                 goto error;
10534         }
10535
10536         /*
10537          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10538          * while i915 HW rotation is clockwise, thats why this swapping.
10539          */
10540         switch (val & PLANE_CTL_ROTATE_MASK) {
10541         case PLANE_CTL_ROTATE_0:
10542                 plane_config->rotation = DRM_MODE_ROTATE_0;
10543                 break;
10544         case PLANE_CTL_ROTATE_90:
10545                 plane_config->rotation = DRM_MODE_ROTATE_270;
10546                 break;
10547         case PLANE_CTL_ROTATE_180:
10548                 plane_config->rotation = DRM_MODE_ROTATE_180;
10549                 break;
10550         case PLANE_CTL_ROTATE_270:
10551                 plane_config->rotation = DRM_MODE_ROTATE_90;
10552                 break;
10553         }
10554
10555         if (INTEL_GEN(dev_priv) >= 10 &&
10556             val & PLANE_CTL_FLIP_HORIZONTAL)
10557                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10558
10559         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10560         plane_config->base = base;
10561
10562         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10563
10564         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10565         fb->height = ((val >> 16) & 0xffff) + 1;
10566         fb->width = ((val >> 0) & 0xffff) + 1;
10567
10568         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10569         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10570         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10571
10572         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10573
10574         plane_config->size = fb->pitches[0] * aligned_height;
10575
10576         drm_dbg_kms(&dev_priv->drm,
10577                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10578                     crtc->base.name, plane->base.name, fb->width, fb->height,
10579                     fb->format->cpp[0] * 8, base, fb->pitches[0],
10580                     plane_config->size);
10581
10582         plane_config->fb = intel_fb;
10583         return;
10584
10585 error:
10586         kfree(intel_fb);
10587 }
10588
10589 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10590 {
10591         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10592         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10593         u32 ctl, pos, size;
10594
10595         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10596         if ((ctl & PF_ENABLE) == 0)
10597                 return;
10598
10599         crtc_state->pch_pfit.enabled = true;
10600
10601         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10602         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10603
10604         ilk_get_pfit_pos_size(crtc_state, pos, size);
10605
10606         /*
10607          * We currently do not free assignements of panel fitters on
10608          * ivb/hsw (since we don't use the higher upscaling modes which
10609          * differentiates them) so just WARN about this case for now.
10610          */
10611         drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10612                     (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10613 }
10614
10615 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10616                                 struct intel_crtc_state *pipe_config)
10617 {
10618         struct drm_device *dev = crtc->base.dev;
10619         struct drm_i915_private *dev_priv = to_i915(dev);
10620         enum intel_display_power_domain power_domain;
10621         intel_wakeref_t wakeref;
10622         u32 tmp;
10623         bool ret;
10624
10625         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10626         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10627         if (!wakeref)
10628                 return false;
10629
10630         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10631         pipe_config->shared_dpll = NULL;
10632
10633         ret = false;
10634         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10635         if (!(tmp & PIPECONF_ENABLE))
10636                 goto out;
10637
10638         switch (tmp & PIPECONF_BPC_MASK) {
10639         case PIPECONF_6BPC:
10640                 pipe_config->pipe_bpp = 18;
10641                 break;
10642         case PIPECONF_8BPC:
10643                 pipe_config->pipe_bpp = 24;
10644                 break;
10645         case PIPECONF_10BPC:
10646                 pipe_config->pipe_bpp = 30;
10647                 break;
10648         case PIPECONF_12BPC:
10649                 pipe_config->pipe_bpp = 36;
10650                 break;
10651         default:
10652                 break;
10653         }
10654
10655         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10656                 pipe_config->limited_color_range = true;
10657
10658         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10659         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10660         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10661                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10662                 break;
10663         default:
10664                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10665                 break;
10666         }
10667
10668         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10669                 PIPECONF_GAMMA_MODE_SHIFT;
10670
10671         pipe_config->csc_mode = intel_de_read(dev_priv,
10672                                               PIPE_CSC_MODE(crtc->pipe));
10673
10674         i9xx_get_pipe_color_config(pipe_config);
10675         intel_color_get_config(pipe_config);
10676
10677         if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10678                 struct intel_shared_dpll *pll;
10679                 enum intel_dpll_id pll_id;
10680
10681                 pipe_config->has_pch_encoder = true;
10682
10683                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10684                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10685                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10686
10687                 ilk_get_fdi_m_n_config(crtc, pipe_config);
10688
10689                 if (HAS_PCH_IBX(dev_priv)) {
10690                         /*
10691                          * The pipe->pch transcoder and pch transcoder->pll
10692                          * mapping is fixed.
10693                          */
10694                         pll_id = (enum intel_dpll_id) crtc->pipe;
10695                 } else {
10696                         tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10697                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10698                                 pll_id = DPLL_ID_PCH_PLL_B;
10699                         else
10700                                 pll_id= DPLL_ID_PCH_PLL_A;
10701                 }
10702
10703                 pipe_config->shared_dpll =
10704                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10705                 pll = pipe_config->shared_dpll;
10706
10707                 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10708                                                  &pipe_config->dpll_hw_state));
10709
10710                 tmp = pipe_config->dpll_hw_state.dpll;
10711                 pipe_config->pixel_multiplier =
10712                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10713                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10714
10715                 ilk_pch_clock_get(crtc, pipe_config);
10716         } else {
10717                 pipe_config->pixel_multiplier = 1;
10718         }
10719
10720         intel_get_pipe_timings(crtc, pipe_config);
10721         intel_get_pipe_src_size(crtc, pipe_config);
10722
10723         ilk_get_pfit_config(pipe_config);
10724
10725         ret = true;
10726
10727 out:
10728         intel_display_power_put(dev_priv, power_domain, wakeref);
10729
10730         return ret;
10731 }
10732
10733 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10734                                   struct intel_crtc_state *crtc_state)
10735 {
10736         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10737         struct intel_atomic_state *state =
10738                 to_intel_atomic_state(crtc_state->uapi.state);
10739
10740         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10741             INTEL_GEN(dev_priv) >= 11) {
10742                 struct intel_encoder *encoder =
10743                         intel_get_crtc_new_encoder(state, crtc_state);
10744
10745                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10746                         drm_dbg_kms(&dev_priv->drm,
10747                                     "failed to find PLL for pipe %c\n",
10748                                     pipe_name(crtc->pipe));
10749                         return -EINVAL;
10750                 }
10751         }
10752
10753         return 0;
10754 }
10755
10756 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10757                             struct intel_crtc_state *pipe_config)
10758 {
10759         enum intel_dpll_id id;
10760         u32 temp;
10761
10762         temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10763         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10764
10765         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10766                 return;
10767
10768         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10769 }
10770
10771 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10772                             struct intel_crtc_state *pipe_config)
10773 {
10774         enum phy phy = intel_port_to_phy(dev_priv, port);
10775         enum icl_port_dpll_id port_dpll_id;
10776         enum intel_dpll_id id;
10777         u32 temp;
10778
10779         if (intel_phy_is_combo(dev_priv, phy)) {
10780                 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
10781                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10782                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10783                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10784         } else if (intel_phy_is_tc(dev_priv, phy)) {
10785                 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10786
10787                 if (clk_sel == DDI_CLK_SEL_MG) {
10788                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10789                                                                     port));
10790                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10791                 } else {
10792                         drm_WARN_ON(&dev_priv->drm,
10793                                     clk_sel < DDI_CLK_SEL_TBT_162);
10794                         id = DPLL_ID_ICL_TBTPLL;
10795                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10796                 }
10797         } else {
10798                 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10799                 return;
10800         }
10801
10802         pipe_config->icl_port_dplls[port_dpll_id].pll =
10803                 intel_get_shared_dpll_by_id(dev_priv, id);
10804
10805         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10806 }
10807
10808 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10809                                 enum port port,
10810                                 struct intel_crtc_state *pipe_config)
10811 {
10812         enum intel_dpll_id id;
10813
10814         switch (port) {
10815         case PORT_A:
10816                 id = DPLL_ID_SKL_DPLL0;
10817                 break;
10818         case PORT_B:
10819                 id = DPLL_ID_SKL_DPLL1;
10820                 break;
10821         case PORT_C:
10822                 id = DPLL_ID_SKL_DPLL2;
10823                 break;
10824         default:
10825                 drm_err(&dev_priv->drm, "Incorrect port type\n");
10826                 return;
10827         }
10828
10829         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10830 }
10831
10832 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10833                             struct intel_crtc_state *pipe_config)
10834 {
10835         enum intel_dpll_id id;
10836         u32 temp;
10837
10838         temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10839         id = temp >> (port * 3 + 1);
10840
10841         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10842                 return;
10843
10844         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10845 }
10846
10847 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10848                             struct intel_crtc_state *pipe_config)
10849 {
10850         enum intel_dpll_id id;
10851         u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
10852
10853         switch (ddi_pll_sel) {
10854         case PORT_CLK_SEL_WRPLL1:
10855                 id = DPLL_ID_WRPLL1;
10856                 break;
10857         case PORT_CLK_SEL_WRPLL2:
10858                 id = DPLL_ID_WRPLL2;
10859                 break;
10860         case PORT_CLK_SEL_SPLL:
10861                 id = DPLL_ID_SPLL;
10862                 break;
10863         case PORT_CLK_SEL_LCPLL_810:
10864                 id = DPLL_ID_LCPLL_810;
10865                 break;
10866         case PORT_CLK_SEL_LCPLL_1350:
10867                 id = DPLL_ID_LCPLL_1350;
10868                 break;
10869         case PORT_CLK_SEL_LCPLL_2700:
10870                 id = DPLL_ID_LCPLL_2700;
10871                 break;
10872         default:
10873                 MISSING_CASE(ddi_pll_sel);
10874                 /* fall through */
10875         case PORT_CLK_SEL_NONE:
10876                 return;
10877         }
10878
10879         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10880 }
10881
10882 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10883                                      struct intel_crtc_state *pipe_config,
10884                                      u64 *power_domain_mask,
10885                                      intel_wakeref_t *wakerefs)
10886 {
10887         struct drm_device *dev = crtc->base.dev;
10888         struct drm_i915_private *dev_priv = to_i915(dev);
10889         enum intel_display_power_domain power_domain;
10890         unsigned long panel_transcoder_mask = 0;
10891         unsigned long enabled_panel_transcoders = 0;
10892         enum transcoder panel_transcoder;
10893         intel_wakeref_t wf;
10894         u32 tmp;
10895
10896         if (INTEL_GEN(dev_priv) >= 11)
10897                 panel_transcoder_mask |=
10898                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10899
10900         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP))
10901                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10902
10903         /*
10904          * The pipe->transcoder mapping is fixed with the exception of the eDP
10905          * and DSI transcoders handled below.
10906          */
10907         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10908
10909         /*
10910          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10911          * consistency and less surprising code; it's in always on power).
10912          */
10913         for_each_set_bit(panel_transcoder,
10914                          &panel_transcoder_mask,
10915                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10916                 bool force_thru = false;
10917                 enum pipe trans_pipe;
10918
10919                 tmp = intel_de_read(dev_priv,
10920                                     TRANS_DDI_FUNC_CTL(panel_transcoder));
10921                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10922                         continue;
10923
10924                 /*
10925                  * Log all enabled ones, only use the first one.
10926                  *
10927                  * FIXME: This won't work for two separate DSI displays.
10928                  */
10929                 enabled_panel_transcoders |= BIT(panel_transcoder);
10930                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10931                         continue;
10932
10933                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10934                 default:
10935                         drm_WARN(dev, 1,
10936                                  "unknown pipe linked to transcoder %s\n",
10937                                  transcoder_name(panel_transcoder));
10938                         /* fall through */
10939                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10940                         force_thru = true;
10941                         /* fall through */
10942                 case TRANS_DDI_EDP_INPUT_A_ON:
10943                         trans_pipe = PIPE_A;
10944                         break;
10945                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10946                         trans_pipe = PIPE_B;
10947                         break;
10948                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10949                         trans_pipe = PIPE_C;
10950                         break;
10951                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
10952                         trans_pipe = PIPE_D;
10953                         break;
10954                 }
10955
10956                 if (trans_pipe == crtc->pipe) {
10957                         pipe_config->cpu_transcoder = panel_transcoder;
10958                         pipe_config->pch_pfit.force_thru = force_thru;
10959                 }
10960         }
10961
10962         /*
10963          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10964          */
10965         drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10966                     enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10967
10968         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10969         drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
10970
10971         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10972         if (!wf)
10973                 return false;
10974
10975         wakerefs[power_domain] = wf;
10976         *power_domain_mask |= BIT_ULL(power_domain);
10977
10978         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
10979
10980         return tmp & PIPECONF_ENABLE;
10981 }
10982
10983 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10984                                          struct intel_crtc_state *pipe_config,
10985                                          u64 *power_domain_mask,
10986                                          intel_wakeref_t *wakerefs)
10987 {
10988         struct drm_device *dev = crtc->base.dev;
10989         struct drm_i915_private *dev_priv = to_i915(dev);
10990         enum intel_display_power_domain power_domain;
10991         enum transcoder cpu_transcoder;
10992         intel_wakeref_t wf;
10993         enum port port;
10994         u32 tmp;
10995
10996         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10997                 if (port == PORT_A)
10998                         cpu_transcoder = TRANSCODER_DSI_A;
10999                 else
11000                         cpu_transcoder = TRANSCODER_DSI_C;
11001
11002                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11003                 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11004
11005                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11006                 if (!wf)
11007                         continue;
11008
11009                 wakerefs[power_domain] = wf;
11010                 *power_domain_mask |= BIT_ULL(power_domain);
11011
11012                 /*
11013                  * The PLL needs to be enabled with a valid divider
11014                  * configuration, otherwise accessing DSI registers will hang
11015                  * the machine. See BSpec North Display Engine
11016                  * registers/MIPI[BXT]. We can break out here early, since we
11017                  * need the same DSI PLL to be enabled for both DSI ports.
11018                  */
11019                 if (!bxt_dsi_pll_is_enabled(dev_priv))
11020                         break;
11021
11022                 /* XXX: this works for video mode only */
11023                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11024                 if (!(tmp & DPI_ENABLE))
11025                         continue;
11026
11027                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11028                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11029                         continue;
11030
11031                 pipe_config->cpu_transcoder = cpu_transcoder;
11032                 break;
11033         }
11034
11035         return transcoder_is_dsi(pipe_config->cpu_transcoder);
11036 }
11037
11038 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11039                                    struct intel_crtc_state *pipe_config)
11040 {
11041         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11042         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11043         struct intel_shared_dpll *pll;
11044         enum port port;
11045         u32 tmp;
11046
11047         if (transcoder_is_dsi(cpu_transcoder)) {
11048                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11049                                                 PORT_A : PORT_B;
11050         } else {
11051                 tmp = intel_de_read(dev_priv,
11052                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
11053                 if (INTEL_GEN(dev_priv) >= 12)
11054                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11055                 else
11056                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11057         }
11058
11059         if (INTEL_GEN(dev_priv) >= 11)
11060                 icl_get_ddi_pll(dev_priv, port, pipe_config);
11061         else if (IS_CANNONLAKE(dev_priv))
11062                 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11063         else if (IS_GEN9_BC(dev_priv))
11064                 skl_get_ddi_pll(dev_priv, port, pipe_config);
11065         else if (IS_GEN9_LP(dev_priv))
11066                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11067         else
11068                 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11069
11070         pll = pipe_config->shared_dpll;
11071         if (pll) {
11072                 drm_WARN_ON(&dev_priv->drm,
11073                             !pll->info->funcs->get_hw_state(dev_priv, pll,
11074                                                 &pipe_config->dpll_hw_state));
11075         }
11076
11077         /*
11078          * Haswell has only FDI/PCH transcoder A. It is which is connected to
11079          * DDI E. So just check whether this pipe is wired to DDI E and whether
11080          * the PCH transcoder is on.
11081          */
11082         if (INTEL_GEN(dev_priv) < 9 &&
11083             (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11084                 pipe_config->has_pch_encoder = true;
11085
11086                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11087                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11088                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
11089
11090                 ilk_get_fdi_m_n_config(crtc, pipe_config);
11091         }
11092 }
11093
11094 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11095                                 struct intel_crtc_state *pipe_config)
11096 {
11097         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11098         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11099         enum intel_display_power_domain power_domain;
11100         u64 power_domain_mask;
11101         bool active;
11102         u32 tmp;
11103
11104         pipe_config->master_transcoder = INVALID_TRANSCODER;
11105
11106         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11107         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11108         if (!wf)
11109                 return false;
11110
11111         wakerefs[power_domain] = wf;
11112         power_domain_mask = BIT_ULL(power_domain);
11113
11114         pipe_config->shared_dpll = NULL;
11115
11116         active = hsw_get_transcoder_state(crtc, pipe_config,
11117                                           &power_domain_mask, wakerefs);
11118
11119         if (IS_GEN9_LP(dev_priv) &&
11120             bxt_get_dsi_transcoder_state(crtc, pipe_config,
11121                                          &power_domain_mask, wakerefs)) {
11122                 drm_WARN_ON(&dev_priv->drm, active);
11123                 active = true;
11124         }
11125
11126         if (!active)
11127                 goto out;
11128
11129         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11130             INTEL_GEN(dev_priv) >= 11) {
11131                 hsw_get_ddi_port_state(crtc, pipe_config);
11132                 intel_get_pipe_timings(crtc, pipe_config);
11133         }
11134
11135         intel_get_pipe_src_size(crtc, pipe_config);
11136
11137         if (IS_HASWELL(dev_priv)) {
11138                 u32 tmp = intel_de_read(dev_priv,
11139                                         PIPECONF(pipe_config->cpu_transcoder));
11140
11141                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11142                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11143                 else
11144                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11145         } else {
11146                 pipe_config->output_format =
11147                         bdw_get_pipemisc_output_format(crtc);
11148
11149                 /*
11150                  * Currently there is no interface defined to
11151                  * check user preference between RGB/YCBCR444
11152                  * or YCBCR420. So the only possible case for
11153                  * YCBCR444 usage is driving YCBCR420 output
11154                  * with LSPCON, when pipe is configured for
11155                  * YCBCR444 output and LSPCON takes care of
11156                  * downsampling it.
11157                  */
11158                 pipe_config->lspcon_downsampling =
11159                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
11160         }
11161
11162         pipe_config->gamma_mode = intel_de_read(dev_priv,
11163                                                 GAMMA_MODE(crtc->pipe));
11164
11165         pipe_config->csc_mode = intel_de_read(dev_priv,
11166                                               PIPE_CSC_MODE(crtc->pipe));
11167
11168         if (INTEL_GEN(dev_priv) >= 9) {
11169                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11170
11171                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11172                         pipe_config->gamma_enable = true;
11173
11174                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11175                         pipe_config->csc_enable = true;
11176         } else {
11177                 i9xx_get_pipe_color_config(pipe_config);
11178         }
11179
11180         intel_color_get_config(pipe_config);
11181
11182         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11183         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11184         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11185                 pipe_config->ips_linetime =
11186                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11187
11188         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11189         drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11190
11191         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11192         if (wf) {
11193                 wakerefs[power_domain] = wf;
11194                 power_domain_mask |= BIT_ULL(power_domain);
11195
11196                 if (INTEL_GEN(dev_priv) >= 9)
11197                         skl_get_pfit_config(pipe_config);
11198                 else
11199                         ilk_get_pfit_config(pipe_config);
11200         }
11201
11202         if (hsw_crtc_supports_ips(crtc)) {
11203                 if (IS_HASWELL(dev_priv))
11204                         pipe_config->ips_enabled = intel_de_read(dev_priv,
11205                                                                  IPS_CTL) & IPS_ENABLE;
11206                 else {
11207                         /*
11208                          * We cannot readout IPS state on broadwell, set to
11209                          * true so we can set it to a defined state on first
11210                          * commit.
11211                          */
11212                         pipe_config->ips_enabled = true;
11213                 }
11214         }
11215
11216         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11217             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11218                 pipe_config->pixel_multiplier =
11219                         intel_de_read(dev_priv,
11220                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11221         } else {
11222                 pipe_config->pixel_multiplier = 1;
11223         }
11224
11225 out:
11226         for_each_power_domain(power_domain, power_domain_mask)
11227                 intel_display_power_put(dev_priv,
11228                                         power_domain, wakerefs[power_domain]);
11229
11230         return active;
11231 }
11232
11233 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11234 {
11235         struct drm_i915_private *dev_priv =
11236                 to_i915(plane_state->uapi.plane->dev);
11237         const struct drm_framebuffer *fb = plane_state->hw.fb;
11238         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11239         u32 base;
11240
11241         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11242                 base = sg_dma_address(obj->mm.pages->sgl);
11243         else
11244                 base = intel_plane_ggtt_offset(plane_state);
11245
11246         return base + plane_state->color_plane[0].offset;
11247 }
11248
11249 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11250 {
11251         int x = plane_state->uapi.dst.x1;
11252         int y = plane_state->uapi.dst.y1;
11253         u32 pos = 0;
11254
11255         if (x < 0) {
11256                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11257                 x = -x;
11258         }
11259         pos |= x << CURSOR_X_SHIFT;
11260
11261         if (y < 0) {
11262                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11263                 y = -y;
11264         }
11265         pos |= y << CURSOR_Y_SHIFT;
11266
11267         return pos;
11268 }
11269
11270 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11271 {
11272         const struct drm_mode_config *config =
11273                 &plane_state->uapi.plane->dev->mode_config;
11274         int width = drm_rect_width(&plane_state->uapi.dst);
11275         int height = drm_rect_height(&plane_state->uapi.dst);
11276
11277         return width > 0 && width <= config->cursor_width &&
11278                 height > 0 && height <= config->cursor_height;
11279 }
11280
11281 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11282 {
11283         struct drm_i915_private *dev_priv =
11284                 to_i915(plane_state->uapi.plane->dev);
11285         unsigned int rotation = plane_state->hw.rotation;
11286         int src_x, src_y;
11287         u32 offset;
11288         int ret;
11289
11290         ret = intel_plane_compute_gtt(plane_state);
11291         if (ret)
11292                 return ret;
11293
11294         if (!plane_state->uapi.visible)
11295                 return 0;
11296
11297         src_x = plane_state->uapi.src.x1 >> 16;
11298         src_y = plane_state->uapi.src.y1 >> 16;
11299
11300         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11301         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11302                                                     plane_state, 0);
11303
11304         if (src_x != 0 || src_y != 0) {
11305                 drm_dbg_kms(&dev_priv->drm,
11306                             "Arbitrary cursor panning not supported\n");
11307                 return -EINVAL;
11308         }
11309
11310         /*
11311          * Put the final coordinates back so that the src
11312          * coordinate checks will see the right values.
11313          */
11314         drm_rect_translate_to(&plane_state->uapi.src,
11315                               src_x << 16, src_y << 16);
11316
11317         /* ILK+ do this automagically in hardware */
11318         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11319                 const struct drm_framebuffer *fb = plane_state->hw.fb;
11320                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11321                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11322
11323                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11324         }
11325
11326         plane_state->color_plane[0].offset = offset;
11327         plane_state->color_plane[0].x = src_x;
11328         plane_state->color_plane[0].y = src_y;
11329
11330         return 0;
11331 }
11332
11333 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11334                               struct intel_plane_state *plane_state)
11335 {
11336         const struct drm_framebuffer *fb = plane_state->hw.fb;
11337         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11338         int ret;
11339
11340         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11341                 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11342                 return -EINVAL;
11343         }
11344
11345         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11346                                                   &crtc_state->uapi,
11347                                                   DRM_PLANE_HELPER_NO_SCALING,
11348                                                   DRM_PLANE_HELPER_NO_SCALING,
11349                                                   true, true);
11350         if (ret)
11351                 return ret;
11352
11353         /* Use the unclipped src/dst rectangles, which we program to hw */
11354         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11355         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11356
11357         ret = intel_cursor_check_surface(plane_state);
11358         if (ret)
11359                 return ret;
11360
11361         if (!plane_state->uapi.visible)
11362                 return 0;
11363
11364         ret = intel_plane_check_src_coordinates(plane_state);
11365         if (ret)
11366                 return ret;
11367
11368         return 0;
11369 }
11370
11371 static unsigned int
11372 i845_cursor_max_stride(struct intel_plane *plane,
11373                        u32 pixel_format, u64 modifier,
11374                        unsigned int rotation)
11375 {
11376         return 2048;
11377 }
11378
11379 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11380 {
11381         u32 cntl = 0;
11382
11383         if (crtc_state->gamma_enable)
11384                 cntl |= CURSOR_GAMMA_ENABLE;
11385
11386         return cntl;
11387 }
11388
11389 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11390                            const struct intel_plane_state *plane_state)
11391 {
11392         return CURSOR_ENABLE |
11393                 CURSOR_FORMAT_ARGB |
11394                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11395 }
11396
11397 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11398 {
11399         int width = drm_rect_width(&plane_state->uapi.dst);
11400
11401         /*
11402          * 845g/865g are only limited by the width of their cursors,
11403          * the height is arbitrary up to the precision of the register.
11404          */
11405         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11406 }
11407
11408 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11409                              struct intel_plane_state *plane_state)
11410 {
11411         const struct drm_framebuffer *fb = plane_state->hw.fb;
11412         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11413         int ret;
11414
11415         ret = intel_check_cursor(crtc_state, plane_state);
11416         if (ret)
11417                 return ret;
11418
11419         /* if we want to turn off the cursor ignore width and height */
11420         if (!fb)
11421                 return 0;
11422
11423         /* Check for which cursor types we support */
11424         if (!i845_cursor_size_ok(plane_state)) {
11425                 drm_dbg_kms(&i915->drm,
11426                             "Cursor dimension %dx%d not supported\n",
11427                             drm_rect_width(&plane_state->uapi.dst),
11428                             drm_rect_height(&plane_state->uapi.dst));
11429                 return -EINVAL;
11430         }
11431
11432         drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11433                     plane_state->color_plane[0].stride != fb->pitches[0]);
11434
11435         switch (fb->pitches[0]) {
11436         case 256:
11437         case 512:
11438         case 1024:
11439         case 2048:
11440                 break;
11441         default:
11442                  drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11443                              fb->pitches[0]);
11444                 return -EINVAL;
11445         }
11446
11447         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11448
11449         return 0;
11450 }
11451
11452 static void i845_update_cursor(struct intel_plane *plane,
11453                                const struct intel_crtc_state *crtc_state,
11454                                const struct intel_plane_state *plane_state)
11455 {
11456         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11457         u32 cntl = 0, base = 0, pos = 0, size = 0;
11458         unsigned long irqflags;
11459
11460         if (plane_state && plane_state->uapi.visible) {
11461                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11462                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11463
11464                 cntl = plane_state->ctl |
11465                         i845_cursor_ctl_crtc(crtc_state);
11466
11467                 size = (height << 12) | width;
11468
11469                 base = intel_cursor_base(plane_state);
11470                 pos = intel_cursor_position(plane_state);
11471         }
11472
11473         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11474
11475         /* On these chipsets we can only modify the base/size/stride
11476          * whilst the cursor is disabled.
11477          */
11478         if (plane->cursor.base != base ||
11479             plane->cursor.size != size ||
11480             plane->cursor.cntl != cntl) {
11481                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11482                 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11483                 intel_de_write_fw(dev_priv, CURSIZE, size);
11484                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11485                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11486
11487                 plane->cursor.base = base;
11488                 plane->cursor.size = size;
11489                 plane->cursor.cntl = cntl;
11490         } else {
11491                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11492         }
11493
11494         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11495 }
11496
11497 static void i845_disable_cursor(struct intel_plane *plane,
11498                                 const struct intel_crtc_state *crtc_state)
11499 {
11500         i845_update_cursor(plane, crtc_state, NULL);
11501 }
11502
11503 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11504                                      enum pipe *pipe)
11505 {
11506         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11507         enum intel_display_power_domain power_domain;
11508         intel_wakeref_t wakeref;
11509         bool ret;
11510
11511         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11512         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11513         if (!wakeref)
11514                 return false;
11515
11516         ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11517
11518         *pipe = PIPE_A;
11519
11520         intel_display_power_put(dev_priv, power_domain, wakeref);
11521
11522         return ret;
11523 }
11524
11525 static unsigned int
11526 i9xx_cursor_max_stride(struct intel_plane *plane,
11527                        u32 pixel_format, u64 modifier,
11528                        unsigned int rotation)
11529 {
11530         return plane->base.dev->mode_config.cursor_width * 4;
11531 }
11532
11533 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11534 {
11535         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11536         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11537         u32 cntl = 0;
11538
11539         if (INTEL_GEN(dev_priv) >= 11)
11540                 return cntl;
11541
11542         if (crtc_state->gamma_enable)
11543                 cntl = MCURSOR_GAMMA_ENABLE;
11544
11545         if (crtc_state->csc_enable)
11546                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11547
11548         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11549                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11550
11551         return cntl;
11552 }
11553
11554 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11555                            const struct intel_plane_state *plane_state)
11556 {
11557         struct drm_i915_private *dev_priv =
11558                 to_i915(plane_state->uapi.plane->dev);
11559         u32 cntl = 0;
11560
11561         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11562                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11563
11564         switch (drm_rect_width(&plane_state->uapi.dst)) {
11565         case 64:
11566                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11567                 break;
11568         case 128:
11569                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11570                 break;
11571         case 256:
11572                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11573                 break;
11574         default:
11575                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11576                 return 0;
11577         }
11578
11579         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11580                 cntl |= MCURSOR_ROTATE_180;
11581
11582         return cntl;
11583 }
11584
11585 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11586 {
11587         struct drm_i915_private *dev_priv =
11588                 to_i915(plane_state->uapi.plane->dev);
11589         int width = drm_rect_width(&plane_state->uapi.dst);
11590         int height = drm_rect_height(&plane_state->uapi.dst);
11591
11592         if (!intel_cursor_size_ok(plane_state))
11593                 return false;
11594
11595         /* Cursor width is limited to a few power-of-two sizes */
11596         switch (width) {
11597         case 256:
11598         case 128:
11599         case 64:
11600                 break;
11601         default:
11602                 return false;
11603         }
11604
11605         /*
11606          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11607          * height from 8 lines up to the cursor width, when the
11608          * cursor is not rotated. Everything else requires square
11609          * cursors.
11610          */
11611         if (HAS_CUR_FBC(dev_priv) &&
11612             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11613                 if (height < 8 || height > width)
11614                         return false;
11615         } else {
11616                 if (height != width)
11617                         return false;
11618         }
11619
11620         return true;
11621 }
11622
11623 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11624                              struct intel_plane_state *plane_state)
11625 {
11626         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11627         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11628         const struct drm_framebuffer *fb = plane_state->hw.fb;
11629         enum pipe pipe = plane->pipe;
11630         int ret;
11631
11632         ret = intel_check_cursor(crtc_state, plane_state);
11633         if (ret)
11634                 return ret;
11635
11636         /* if we want to turn off the cursor ignore width and height */
11637         if (!fb)
11638                 return 0;
11639
11640         /* Check for which cursor types we support */
11641         if (!i9xx_cursor_size_ok(plane_state)) {
11642                 drm_dbg(&dev_priv->drm,
11643                         "Cursor dimension %dx%d not supported\n",
11644                         drm_rect_width(&plane_state->uapi.dst),
11645                         drm_rect_height(&plane_state->uapi.dst));
11646                 return -EINVAL;
11647         }
11648
11649         drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11650                     plane_state->color_plane[0].stride != fb->pitches[0]);
11651
11652         if (fb->pitches[0] !=
11653             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11654                 drm_dbg_kms(&dev_priv->drm,
11655                             "Invalid cursor stride (%u) (cursor width %d)\n",
11656                             fb->pitches[0],
11657                             drm_rect_width(&plane_state->uapi.dst));
11658                 return -EINVAL;
11659         }
11660
11661         /*
11662          * There's something wrong with the cursor on CHV pipe C.
11663          * If it straddles the left edge of the screen then
11664          * moving it away from the edge or disabling it often
11665          * results in a pipe underrun, and often that can lead to
11666          * dead pipe (constant underrun reported, and it scans
11667          * out just a solid color). To recover from that, the
11668          * display power well must be turned off and on again.
11669          * Refuse the put the cursor into that compromised position.
11670          */
11671         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11672             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11673                 drm_dbg_kms(&dev_priv->drm,
11674                             "CHV cursor C not allowed to straddle the left screen edge\n");
11675                 return -EINVAL;
11676         }
11677
11678         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11679
11680         return 0;
11681 }
11682
11683 static void i9xx_update_cursor(struct intel_plane *plane,
11684                                const struct intel_crtc_state *crtc_state,
11685                                const struct intel_plane_state *plane_state)
11686 {
11687         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11688         enum pipe pipe = plane->pipe;
11689         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11690         unsigned long irqflags;
11691
11692         if (plane_state && plane_state->uapi.visible) {
11693                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11694                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11695
11696                 cntl = plane_state->ctl |
11697                         i9xx_cursor_ctl_crtc(crtc_state);
11698
11699                 if (width != height)
11700                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11701
11702                 base = intel_cursor_base(plane_state);
11703                 pos = intel_cursor_position(plane_state);
11704         }
11705
11706         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11707
11708         /*
11709          * On some platforms writing CURCNTR first will also
11710          * cause CURPOS to be armed by the CURBASE write.
11711          * Without the CURCNTR write the CURPOS write would
11712          * arm itself. Thus we always update CURCNTR before
11713          * CURPOS.
11714          *
11715          * On other platforms CURPOS always requires the
11716          * CURBASE write to arm the update. Additonally
11717          * a write to any of the cursor register will cancel
11718          * an already armed cursor update. Thus leaving out
11719          * the CURBASE write after CURPOS could lead to a
11720          * cursor that doesn't appear to move, or even change
11721          * shape. Thus we always write CURBASE.
11722          *
11723          * The other registers are armed by by the CURBASE write
11724          * except when the plane is getting enabled at which time
11725          * the CURCNTR write arms the update.
11726          */
11727
11728         if (INTEL_GEN(dev_priv) >= 9)
11729                 skl_write_cursor_wm(plane, crtc_state);
11730
11731         if (plane->cursor.base != base ||
11732             plane->cursor.size != fbc_ctl ||
11733             plane->cursor.cntl != cntl) {
11734                 if (HAS_CUR_FBC(dev_priv))
11735                         intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11736                                           fbc_ctl);
11737                 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11738                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11739                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11740
11741                 plane->cursor.base = base;
11742                 plane->cursor.size = fbc_ctl;
11743                 plane->cursor.cntl = cntl;
11744         } else {
11745                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11746                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11747         }
11748
11749         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11750 }
11751
11752 static void i9xx_disable_cursor(struct intel_plane *plane,
11753                                 const struct intel_crtc_state *crtc_state)
11754 {
11755         i9xx_update_cursor(plane, crtc_state, NULL);
11756 }
11757
11758 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11759                                      enum pipe *pipe)
11760 {
11761         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11762         enum intel_display_power_domain power_domain;
11763         intel_wakeref_t wakeref;
11764         bool ret;
11765         u32 val;
11766
11767         /*
11768          * Not 100% correct for planes that can move between pipes,
11769          * but that's only the case for gen2-3 which don't have any
11770          * display power wells.
11771          */
11772         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11773         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11774         if (!wakeref)
11775                 return false;
11776
11777         val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11778
11779         ret = val & MCURSOR_MODE;
11780
11781         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11782                 *pipe = plane->pipe;
11783         else
11784                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11785                         MCURSOR_PIPE_SELECT_SHIFT;
11786
11787         intel_display_power_put(dev_priv, power_domain, wakeref);
11788
11789         return ret;
11790 }
11791
11792 /* VESA 640x480x72Hz mode to set on the pipe */
11793 static const struct drm_display_mode load_detect_mode = {
11794         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11795                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11796 };
11797
11798 struct drm_framebuffer *
11799 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11800                          struct drm_mode_fb_cmd2 *mode_cmd)
11801 {
11802         struct intel_framebuffer *intel_fb;
11803         int ret;
11804
11805         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11806         if (!intel_fb)
11807                 return ERR_PTR(-ENOMEM);
11808
11809         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11810         if (ret)
11811                 goto err;
11812
11813         return &intel_fb->base;
11814
11815 err:
11816         kfree(intel_fb);
11817         return ERR_PTR(ret);
11818 }
11819
11820 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11821                                         struct drm_crtc *crtc)
11822 {
11823         struct drm_plane *plane;
11824         struct drm_plane_state *plane_state;
11825         int ret, i;
11826
11827         ret = drm_atomic_add_affected_planes(state, crtc);
11828         if (ret)
11829                 return ret;
11830
11831         for_each_new_plane_in_state(state, plane, plane_state, i) {
11832                 if (plane_state->crtc != crtc)
11833                         continue;
11834
11835                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11836                 if (ret)
11837                         return ret;
11838
11839                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11840         }
11841
11842         return 0;
11843 }
11844
11845 int intel_get_load_detect_pipe(struct drm_connector *connector,
11846                                struct intel_load_detect_pipe *old,
11847                                struct drm_modeset_acquire_ctx *ctx)
11848 {
11849         struct intel_crtc *intel_crtc;
11850         struct intel_encoder *intel_encoder =
11851                 intel_attached_encoder(to_intel_connector(connector));
11852         struct drm_crtc *possible_crtc;
11853         struct drm_encoder *encoder = &intel_encoder->base;
11854         struct drm_crtc *crtc = NULL;
11855         struct drm_device *dev = encoder->dev;
11856         struct drm_i915_private *dev_priv = to_i915(dev);
11857         struct drm_mode_config *config = &dev->mode_config;
11858         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11859         struct drm_connector_state *connector_state;
11860         struct intel_crtc_state *crtc_state;
11861         int ret, i = -1;
11862
11863         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11864                     connector->base.id, connector->name,
11865                     encoder->base.id, encoder->name);
11866
11867         old->restore_state = NULL;
11868
11869         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
11870
11871         /*
11872          * Algorithm gets a little messy:
11873          *
11874          *   - if the connector already has an assigned crtc, use it (but make
11875          *     sure it's on first)
11876          *
11877          *   - try to find the first unused crtc that can drive this connector,
11878          *     and use that if we find one
11879          */
11880
11881         /* See if we already have a CRTC for this connector */
11882         if (connector->state->crtc) {
11883                 crtc = connector->state->crtc;
11884
11885                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11886                 if (ret)
11887                         goto fail;
11888
11889                 /* Make sure the crtc and connector are running */
11890                 goto found;
11891         }
11892
11893         /* Find an unused one (if possible) */
11894         for_each_crtc(dev, possible_crtc) {
11895                 i++;
11896                 if (!(encoder->possible_crtcs & (1 << i)))
11897                         continue;
11898
11899                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11900                 if (ret)
11901                         goto fail;
11902
11903                 if (possible_crtc->state->enable) {
11904                         drm_modeset_unlock(&possible_crtc->mutex);
11905                         continue;
11906                 }
11907
11908                 crtc = possible_crtc;
11909                 break;
11910         }
11911
11912         /*
11913          * If we didn't find an unused CRTC, don't use any.
11914          */
11915         if (!crtc) {
11916                 drm_dbg_kms(&dev_priv->drm,
11917                             "no pipe available for load-detect\n");
11918                 ret = -ENODEV;
11919                 goto fail;
11920         }
11921
11922 found:
11923         intel_crtc = to_intel_crtc(crtc);
11924
11925         state = drm_atomic_state_alloc(dev);
11926         restore_state = drm_atomic_state_alloc(dev);
11927         if (!state || !restore_state) {
11928                 ret = -ENOMEM;
11929                 goto fail;
11930         }
11931
11932         state->acquire_ctx = ctx;
11933         restore_state->acquire_ctx = ctx;
11934
11935         connector_state = drm_atomic_get_connector_state(state, connector);
11936         if (IS_ERR(connector_state)) {
11937                 ret = PTR_ERR(connector_state);
11938                 goto fail;
11939         }
11940
11941         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11942         if (ret)
11943                 goto fail;
11944
11945         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11946         if (IS_ERR(crtc_state)) {
11947                 ret = PTR_ERR(crtc_state);
11948                 goto fail;
11949         }
11950
11951         crtc_state->uapi.active = true;
11952
11953         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11954                                            &load_detect_mode);
11955         if (ret)
11956                 goto fail;
11957
11958         ret = intel_modeset_disable_planes(state, crtc);
11959         if (ret)
11960                 goto fail;
11961
11962         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11963         if (!ret)
11964                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11965         if (!ret)
11966                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11967         if (ret) {
11968                 drm_dbg_kms(&dev_priv->drm,
11969                             "Failed to create a copy of old state to restore: %i\n",
11970                             ret);
11971                 goto fail;
11972         }
11973
11974         ret = drm_atomic_commit(state);
11975         if (ret) {
11976                 drm_dbg_kms(&dev_priv->drm,
11977                             "failed to set mode on load-detect pipe\n");
11978                 goto fail;
11979         }
11980
11981         old->restore_state = restore_state;
11982         drm_atomic_state_put(state);
11983
11984         /* let the connector get through one full cycle before testing */
11985         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11986         return true;
11987
11988 fail:
11989         if (state) {
11990                 drm_atomic_state_put(state);
11991                 state = NULL;
11992         }
11993         if (restore_state) {
11994                 drm_atomic_state_put(restore_state);
11995                 restore_state = NULL;
11996         }
11997
11998         if (ret == -EDEADLK)
11999                 return ret;
12000
12001         return false;
12002 }
12003
12004 void intel_release_load_detect_pipe(struct drm_connector *connector,
12005                                     struct intel_load_detect_pipe *old,
12006                                     struct drm_modeset_acquire_ctx *ctx)
12007 {
12008         struct intel_encoder *intel_encoder =
12009                 intel_attached_encoder(to_intel_connector(connector));
12010         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12011         struct drm_encoder *encoder = &intel_encoder->base;
12012         struct drm_atomic_state *state = old->restore_state;
12013         int ret;
12014
12015         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12016                     connector->base.id, connector->name,
12017                     encoder->base.id, encoder->name);
12018
12019         if (!state)
12020                 return;
12021
12022         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12023         if (ret)
12024                 drm_dbg_kms(&i915->drm,
12025                             "Couldn't release load detect pipe: %i\n", ret);
12026         drm_atomic_state_put(state);
12027 }
12028
12029 static int i9xx_pll_refclk(struct drm_device *dev,
12030                            const struct intel_crtc_state *pipe_config)
12031 {
12032         struct drm_i915_private *dev_priv = to_i915(dev);
12033         u32 dpll = pipe_config->dpll_hw_state.dpll;
12034
12035         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12036                 return dev_priv->vbt.lvds_ssc_freq;
12037         else if (HAS_PCH_SPLIT(dev_priv))
12038                 return 120000;
12039         else if (!IS_GEN(dev_priv, 2))
12040                 return 96000;
12041         else
12042                 return 48000;
12043 }
12044
12045 /* Returns the clock of the currently programmed mode of the given pipe. */
12046 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12047                                 struct intel_crtc_state *pipe_config)
12048 {
12049         struct drm_device *dev = crtc->base.dev;
12050         struct drm_i915_private *dev_priv = to_i915(dev);
12051         enum pipe pipe = crtc->pipe;
12052         u32 dpll = pipe_config->dpll_hw_state.dpll;
12053         u32 fp;
12054         struct dpll clock;
12055         int port_clock;
12056         int refclk = i9xx_pll_refclk(dev, pipe_config);
12057
12058         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12059                 fp = pipe_config->dpll_hw_state.fp0;
12060         else
12061                 fp = pipe_config->dpll_hw_state.fp1;
12062
12063         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12064         if (IS_PINEVIEW(dev_priv)) {
12065                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12066                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12067         } else {
12068                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12069                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12070         }
12071
12072         if (!IS_GEN(dev_priv, 2)) {
12073                 if (IS_PINEVIEW(dev_priv))
12074                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12075                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12076                 else
12077                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12078                                DPLL_FPA01_P1_POST_DIV_SHIFT);
12079
12080                 switch (dpll & DPLL_MODE_MASK) {
12081                 case DPLLB_MODE_DAC_SERIAL:
12082                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12083                                 5 : 10;
12084                         break;
12085                 case DPLLB_MODE_LVDS:
12086                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12087                                 7 : 14;
12088                         break;
12089                 default:
12090                         drm_dbg_kms(&dev_priv->drm,
12091                                     "Unknown DPLL mode %08x in programmed "
12092                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
12093                         return;
12094                 }
12095
12096                 if (IS_PINEVIEW(dev_priv))
12097                         port_clock = pnv_calc_dpll_params(refclk, &clock);
12098                 else
12099                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
12100         } else {
12101                 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12102                                                                  LVDS);
12103                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12104
12105                 if (is_lvds) {
12106                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12107                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
12108
12109                         if (lvds & LVDS_CLKB_POWER_UP)
12110                                 clock.p2 = 7;
12111                         else
12112                                 clock.p2 = 14;
12113                 } else {
12114                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
12115                                 clock.p1 = 2;
12116                         else {
12117                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12118                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12119                         }
12120                         if (dpll & PLL_P2_DIVIDE_BY_4)
12121                                 clock.p2 = 4;
12122                         else
12123                                 clock.p2 = 2;
12124                 }
12125
12126                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12127         }
12128
12129         /*
12130          * This value includes pixel_multiplier. We will use
12131          * port_clock to compute adjusted_mode.crtc_clock in the
12132          * encoder's get_config() function.
12133          */
12134         pipe_config->port_clock = port_clock;
12135 }
12136
12137 int intel_dotclock_calculate(int link_freq,
12138                              const struct intel_link_m_n *m_n)
12139 {
12140         /*
12141          * The calculation for the data clock is:
12142          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12143          * But we want to avoid losing precison if possible, so:
12144          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12145          *
12146          * and the link clock is simpler:
12147          * link_clock = (m * link_clock) / n
12148          */
12149
12150         if (!m_n->link_n)
12151                 return 0;
12152
12153         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12154 }
12155
12156 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12157                               struct intel_crtc_state *pipe_config)
12158 {
12159         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12160
12161         /* read out port_clock from the DPLL */
12162         i9xx_crtc_clock_get(crtc, pipe_config);
12163
12164         /*
12165          * In case there is an active pipe without active ports,
12166          * we may need some idea for the dotclock anyway.
12167          * Calculate one based on the FDI configuration.
12168          */
12169         pipe_config->hw.adjusted_mode.crtc_clock =
12170                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12171                                          &pipe_config->fdi_m_n);
12172 }
12173
12174 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12175                                    struct intel_crtc *crtc)
12176 {
12177         memset(crtc_state, 0, sizeof(*crtc_state));
12178
12179         __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12180
12181         crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12182         crtc_state->master_transcoder = INVALID_TRANSCODER;
12183         crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12184         crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12185         crtc_state->scaler_state.scaler_id = -1;
12186         crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12187 }
12188
12189 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12190 {
12191         struct intel_crtc_state *crtc_state;
12192
12193         crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12194
12195         if (crtc_state)
12196                 intel_crtc_state_reset(crtc_state, crtc);
12197
12198         return crtc_state;
12199 }
12200
12201 /* Returns the currently programmed mode of the given encoder. */
12202 struct drm_display_mode *
12203 intel_encoder_current_mode(struct intel_encoder *encoder)
12204 {
12205         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12206         struct intel_crtc_state *crtc_state;
12207         struct drm_display_mode *mode;
12208         struct intel_crtc *crtc;
12209         enum pipe pipe;
12210
12211         if (!encoder->get_hw_state(encoder, &pipe))
12212                 return NULL;
12213
12214         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12215
12216         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12217         if (!mode)
12218                 return NULL;
12219
12220         crtc_state = intel_crtc_state_alloc(crtc);
12221         if (!crtc_state) {
12222                 kfree(mode);
12223                 return NULL;
12224         }
12225
12226         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12227                 kfree(crtc_state);
12228                 kfree(mode);
12229                 return NULL;
12230         }
12231
12232         encoder->get_config(encoder, crtc_state);
12233
12234         intel_mode_from_pipe_config(mode, crtc_state);
12235
12236         kfree(crtc_state);
12237
12238         return mode;
12239 }
12240
12241 static void intel_crtc_destroy(struct drm_crtc *crtc)
12242 {
12243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12244
12245         drm_crtc_cleanup(crtc);
12246         kfree(intel_crtc);
12247 }
12248
12249 /**
12250  * intel_wm_need_update - Check whether watermarks need updating
12251  * @cur: current plane state
12252  * @new: new plane state
12253  *
12254  * Check current plane state versus the new one to determine whether
12255  * watermarks need to be recalculated.
12256  *
12257  * Returns true or false.
12258  */
12259 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12260                                  struct intel_plane_state *new)
12261 {
12262         /* Update watermarks on tiling or size changes. */
12263         if (new->uapi.visible != cur->uapi.visible)
12264                 return true;
12265
12266         if (!cur->hw.fb || !new->hw.fb)
12267                 return false;
12268
12269         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12270             cur->hw.rotation != new->hw.rotation ||
12271             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12272             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12273             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12274             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12275                 return true;
12276
12277         return false;
12278 }
12279
12280 static bool needs_scaling(const struct intel_plane_state *state)
12281 {
12282         int src_w = drm_rect_width(&state->uapi.src) >> 16;
12283         int src_h = drm_rect_height(&state->uapi.src) >> 16;
12284         int dst_w = drm_rect_width(&state->uapi.dst);
12285         int dst_h = drm_rect_height(&state->uapi.dst);
12286
12287         return (src_w != dst_w || src_h != dst_h);
12288 }
12289
12290 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12291                                     struct intel_crtc_state *crtc_state,
12292                                     const struct intel_plane_state *old_plane_state,
12293                                     struct intel_plane_state *plane_state)
12294 {
12295         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12296         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12297         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12298         bool mode_changed = needs_modeset(crtc_state);
12299         bool was_crtc_enabled = old_crtc_state->hw.active;
12300         bool is_crtc_enabled = crtc_state->hw.active;
12301         bool turn_off, turn_on, visible, was_visible;
12302         int ret;
12303
12304         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12305                 ret = skl_update_scaler_plane(crtc_state, plane_state);
12306                 if (ret)
12307                         return ret;
12308         }
12309
12310         was_visible = old_plane_state->uapi.visible;
12311         visible = plane_state->uapi.visible;
12312
12313         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12314                 was_visible = false;
12315
12316         /*
12317          * Visibility is calculated as if the crtc was on, but
12318          * after scaler setup everything depends on it being off
12319          * when the crtc isn't active.
12320          *
12321          * FIXME this is wrong for watermarks. Watermarks should also
12322          * be computed as if the pipe would be active. Perhaps move
12323          * per-plane wm computation to the .check_plane() hook, and
12324          * only combine the results from all planes in the current place?
12325          */
12326         if (!is_crtc_enabled) {
12327                 intel_plane_set_invisible(crtc_state, plane_state);
12328                 visible = false;
12329         }
12330
12331         if (!was_visible && !visible)
12332                 return 0;
12333
12334         turn_off = was_visible && (!visible || mode_changed);
12335         turn_on = visible && (!was_visible || mode_changed);
12336
12337         drm_dbg_atomic(&dev_priv->drm,
12338                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12339                        crtc->base.base.id, crtc->base.name,
12340                        plane->base.base.id, plane->base.name,
12341                        was_visible, visible,
12342                        turn_off, turn_on, mode_changed);
12343
12344         if (turn_on) {
12345                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12346                         crtc_state->update_wm_pre = true;
12347
12348                 /* must disable cxsr around plane enable/disable */
12349                 if (plane->id != PLANE_CURSOR)
12350                         crtc_state->disable_cxsr = true;
12351         } else if (turn_off) {
12352                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12353                         crtc_state->update_wm_post = true;
12354
12355                 /* must disable cxsr around plane enable/disable */
12356                 if (plane->id != PLANE_CURSOR)
12357                         crtc_state->disable_cxsr = true;
12358         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12359                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12360                         /* FIXME bollocks */
12361                         crtc_state->update_wm_pre = true;
12362                         crtc_state->update_wm_post = true;
12363                 }
12364         }
12365
12366         if (visible || was_visible)
12367                 crtc_state->fb_bits |= plane->frontbuffer_bit;
12368
12369         /*
12370          * ILK/SNB DVSACNTR/Sprite Enable
12371          * IVB SPR_CTL/Sprite Enable
12372          * "When in Self Refresh Big FIFO mode, a write to enable the
12373          *  plane will be internally buffered and delayed while Big FIFO
12374          *  mode is exiting."
12375          *
12376          * Which means that enabling the sprite can take an extra frame
12377          * when we start in big FIFO mode (LP1+). Thus we need to drop
12378          * down to LP0 and wait for vblank in order to make sure the
12379          * sprite gets enabled on the next vblank after the register write.
12380          * Doing otherwise would risk enabling the sprite one frame after
12381          * we've already signalled flip completion. We can resume LP1+
12382          * once the sprite has been enabled.
12383          *
12384          *
12385          * WaCxSRDisabledForSpriteScaling:ivb
12386          * IVB SPR_SCALE/Scaling Enable
12387          * "Low Power watermarks must be disabled for at least one
12388          *  frame before enabling sprite scaling, and kept disabled
12389          *  until sprite scaling is disabled."
12390          *
12391          * ILK/SNB DVSASCALE/Scaling Enable
12392          * "When in Self Refresh Big FIFO mode, scaling enable will be
12393          *  masked off while Big FIFO mode is exiting."
12394          *
12395          * Despite the w/a only being listed for IVB we assume that
12396          * the ILK/SNB note has similar ramifications, hence we apply
12397          * the w/a on all three platforms.
12398          *
12399          * With experimental results seems this is needed also for primary
12400          * plane, not only sprite plane.
12401          */
12402         if (plane->id != PLANE_CURSOR &&
12403             (IS_GEN_RANGE(dev_priv, 5, 6) ||
12404              IS_IVYBRIDGE(dev_priv)) &&
12405             (turn_on || (!needs_scaling(old_plane_state) &&
12406                          needs_scaling(plane_state))))
12407                 crtc_state->disable_lp_wm = true;
12408
12409         return 0;
12410 }
12411
12412 static bool encoders_cloneable(const struct intel_encoder *a,
12413                                const struct intel_encoder *b)
12414 {
12415         /* masks could be asymmetric, so check both ways */
12416         return a == b || (a->cloneable & (1 << b->type) &&
12417                           b->cloneable & (1 << a->type));
12418 }
12419
12420 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12421                                          struct intel_crtc *crtc,
12422                                          struct intel_encoder *encoder)
12423 {
12424         struct intel_encoder *source_encoder;
12425         struct drm_connector *connector;
12426         struct drm_connector_state *connector_state;
12427         int i;
12428
12429         for_each_new_connector_in_state(state, connector, connector_state, i) {
12430                 if (connector_state->crtc != &crtc->base)
12431                         continue;
12432
12433                 source_encoder =
12434                         to_intel_encoder(connector_state->best_encoder);
12435                 if (!encoders_cloneable(encoder, source_encoder))
12436                         return false;
12437         }
12438
12439         return true;
12440 }
12441
12442 static int icl_add_linked_planes(struct intel_atomic_state *state)
12443 {
12444         struct intel_plane *plane, *linked;
12445         struct intel_plane_state *plane_state, *linked_plane_state;
12446         int i;
12447
12448         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12449                 linked = plane_state->planar_linked_plane;
12450
12451                 if (!linked)
12452                         continue;
12453
12454                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12455                 if (IS_ERR(linked_plane_state))
12456                         return PTR_ERR(linked_plane_state);
12457
12458                 drm_WARN_ON(state->base.dev,
12459                             linked_plane_state->planar_linked_plane != plane);
12460                 drm_WARN_ON(state->base.dev,
12461                             linked_plane_state->planar_slave == plane_state->planar_slave);
12462         }
12463
12464         return 0;
12465 }
12466
12467 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12468 {
12469         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12470         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12471         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12472         struct intel_plane *plane, *linked;
12473         struct intel_plane_state *plane_state;
12474         int i;
12475
12476         if (INTEL_GEN(dev_priv) < 11)
12477                 return 0;
12478
12479         /*
12480          * Destroy all old plane links and make the slave plane invisible
12481          * in the crtc_state->active_planes mask.
12482          */
12483         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12484                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12485                         continue;
12486
12487                 plane_state->planar_linked_plane = NULL;
12488                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12489                         crtc_state->active_planes &= ~BIT(plane->id);
12490                         crtc_state->update_planes |= BIT(plane->id);
12491                 }
12492
12493                 plane_state->planar_slave = false;
12494         }
12495
12496         if (!crtc_state->nv12_planes)
12497                 return 0;
12498
12499         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12500                 struct intel_plane_state *linked_state = NULL;
12501
12502                 if (plane->pipe != crtc->pipe ||
12503                     !(crtc_state->nv12_planes & BIT(plane->id)))
12504                         continue;
12505
12506                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12507                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12508                                 continue;
12509
12510                         if (crtc_state->active_planes & BIT(linked->id))
12511                                 continue;
12512
12513                         linked_state = intel_atomic_get_plane_state(state, linked);
12514                         if (IS_ERR(linked_state))
12515                                 return PTR_ERR(linked_state);
12516
12517                         break;
12518                 }
12519
12520                 if (!linked_state) {
12521                         drm_dbg_kms(&dev_priv->drm,
12522                                     "Need %d free Y planes for planar YUV\n",
12523                                     hweight8(crtc_state->nv12_planes));
12524
12525                         return -EINVAL;
12526                 }
12527
12528                 plane_state->planar_linked_plane = linked;
12529
12530                 linked_state->planar_slave = true;
12531                 linked_state->planar_linked_plane = plane;
12532                 crtc_state->active_planes |= BIT(linked->id);
12533                 crtc_state->update_planes |= BIT(linked->id);
12534                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12535                             linked->base.name, plane->base.name);
12536
12537                 /* Copy parameters to slave plane */
12538                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12539                 linked_state->color_ctl = plane_state->color_ctl;
12540                 linked_state->view = plane_state->view;
12541                 memcpy(linked_state->color_plane, plane_state->color_plane,
12542                        sizeof(linked_state->color_plane));
12543
12544                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12545                 linked_state->uapi.src = plane_state->uapi.src;
12546                 linked_state->uapi.dst = plane_state->uapi.dst;
12547
12548                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12549                         if (linked->id == PLANE_SPRITE5)
12550                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12551                         else if (linked->id == PLANE_SPRITE4)
12552                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12553                         else if (linked->id == PLANE_SPRITE3)
12554                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12555                         else if (linked->id == PLANE_SPRITE2)
12556                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12557                         else
12558                                 MISSING_CASE(linked->id);
12559                 }
12560         }
12561
12562         return 0;
12563 }
12564
12565 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12566 {
12567         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12568         struct intel_atomic_state *state =
12569                 to_intel_atomic_state(new_crtc_state->uapi.state);
12570         const struct intel_crtc_state *old_crtc_state =
12571                 intel_atomic_get_old_crtc_state(state, crtc);
12572
12573         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12574 }
12575
12576 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12577 {
12578         const struct drm_display_mode *adjusted_mode =
12579                 &crtc_state->hw.adjusted_mode;
12580
12581         if (!crtc_state->hw.enable)
12582                 return 0;
12583
12584         return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12585                                  adjusted_mode->crtc_clock);
12586 }
12587
12588 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12589                                const struct intel_cdclk_state *cdclk_state)
12590 {
12591         const struct drm_display_mode *adjusted_mode =
12592                 &crtc_state->hw.adjusted_mode;
12593
12594         if (!crtc_state->hw.enable)
12595                 return 0;
12596
12597         return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12598                                  cdclk_state->logical.cdclk);
12599 }
12600
12601 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12602 {
12603         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12604         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12605         const struct drm_display_mode *adjusted_mode =
12606                 &crtc_state->hw.adjusted_mode;
12607         u16 linetime_wm;
12608
12609         if (!crtc_state->hw.enable)
12610                 return 0;
12611
12612         linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12613                                    crtc_state->pixel_rate);
12614
12615         /* Display WA #1135: BXT:ALL GLK:ALL */
12616         if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12617                 linetime_wm /= 2;
12618
12619         return linetime_wm;
12620 }
12621
12622 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12623                                    struct intel_crtc *crtc)
12624 {
12625         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12626         struct intel_crtc_state *crtc_state =
12627                 intel_atomic_get_new_crtc_state(state, crtc);
12628         const struct intel_cdclk_state *cdclk_state;
12629
12630         if (INTEL_GEN(dev_priv) >= 9)
12631                 crtc_state->linetime = skl_linetime_wm(crtc_state);
12632         else
12633                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12634
12635         if (!hsw_crtc_supports_ips(crtc))
12636                 return 0;
12637
12638         cdclk_state = intel_atomic_get_cdclk_state(state);
12639         if (IS_ERR(cdclk_state))
12640                 return PTR_ERR(cdclk_state);
12641
12642         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12643                                                        cdclk_state);
12644
12645         return 0;
12646 }
12647
12648 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12649                                    struct intel_crtc *crtc)
12650 {
12651         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12652         struct intel_crtc_state *crtc_state =
12653                 intel_atomic_get_new_crtc_state(state, crtc);
12654         bool mode_changed = needs_modeset(crtc_state);
12655         int ret;
12656
12657         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12658             mode_changed && !crtc_state->hw.active)
12659                 crtc_state->update_wm_post = true;
12660
12661         if (mode_changed && crtc_state->hw.enable &&
12662             dev_priv->display.crtc_compute_clock &&
12663             !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12664                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12665                 if (ret)
12666                         return ret;
12667         }
12668
12669         /*
12670          * May need to update pipe gamma enable bits
12671          * when C8 planes are getting enabled/disabled.
12672          */
12673         if (c8_planes_changed(crtc_state))
12674                 crtc_state->uapi.color_mgmt_changed = true;
12675
12676         if (mode_changed || crtc_state->update_pipe ||
12677             crtc_state->uapi.color_mgmt_changed) {
12678                 ret = intel_color_check(crtc_state);
12679                 if (ret)
12680                         return ret;
12681         }
12682
12683         if (dev_priv->display.compute_pipe_wm) {
12684                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12685                 if (ret) {
12686                         drm_dbg_kms(&dev_priv->drm,
12687                                     "Target pipe watermarks are invalid\n");
12688                         return ret;
12689                 }
12690         }
12691
12692         if (dev_priv->display.compute_intermediate_wm) {
12693                 if (drm_WARN_ON(&dev_priv->drm,
12694                                 !dev_priv->display.compute_pipe_wm))
12695                         return 0;
12696
12697                 /*
12698                  * Calculate 'intermediate' watermarks that satisfy both the
12699                  * old state and the new state.  We can program these
12700                  * immediately.
12701                  */
12702                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12703                 if (ret) {
12704                         drm_dbg_kms(&dev_priv->drm,
12705                                     "No valid intermediate pipe watermarks are possible\n");
12706                         return ret;
12707                 }
12708         }
12709
12710         if (INTEL_GEN(dev_priv) >= 9) {
12711                 if (mode_changed || crtc_state->update_pipe) {
12712                         ret = skl_update_scaler_crtc(crtc_state);
12713                         if (ret)
12714                                 return ret;
12715                 }
12716
12717                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12718                 if (ret)
12719                         return ret;
12720         }
12721
12722         if (HAS_IPS(dev_priv)) {
12723                 ret = hsw_compute_ips_config(crtc_state);
12724                 if (ret)
12725                         return ret;
12726         }
12727
12728         if (INTEL_GEN(dev_priv) >= 9 ||
12729             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12730                 ret = hsw_compute_linetime_wm(state, crtc);
12731                 if (ret)
12732                         return ret;
12733
12734         }
12735
12736         return 0;
12737 }
12738
12739 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12740 {
12741         struct intel_connector *connector;
12742         struct drm_connector_list_iter conn_iter;
12743
12744         drm_connector_list_iter_begin(dev, &conn_iter);
12745         for_each_intel_connector_iter(connector, &conn_iter) {
12746                 if (connector->base.state->crtc)
12747                         drm_connector_put(&connector->base);
12748
12749                 if (connector->base.encoder) {
12750                         connector->base.state->best_encoder =
12751                                 connector->base.encoder;
12752                         connector->base.state->crtc =
12753                                 connector->base.encoder->crtc;
12754
12755                         drm_connector_get(&connector->base);
12756                 } else {
12757                         connector->base.state->best_encoder = NULL;
12758                         connector->base.state->crtc = NULL;
12759                 }
12760         }
12761         drm_connector_list_iter_end(&conn_iter);
12762 }
12763
12764 static int
12765 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12766                       struct intel_crtc_state *pipe_config)
12767 {
12768         struct drm_connector *connector = conn_state->connector;
12769         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12770         const struct drm_display_info *info = &connector->display_info;
12771         int bpp;
12772
12773         switch (conn_state->max_bpc) {
12774         case 6 ... 7:
12775                 bpp = 6 * 3;
12776                 break;
12777         case 8 ... 9:
12778                 bpp = 8 * 3;
12779                 break;
12780         case 10 ... 11:
12781                 bpp = 10 * 3;
12782                 break;
12783         case 12:
12784                 bpp = 12 * 3;
12785                 break;
12786         default:
12787                 return -EINVAL;
12788         }
12789
12790         if (bpp < pipe_config->pipe_bpp) {
12791                 drm_dbg_kms(&i915->drm,
12792                             "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12793                             "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12794                             connector->base.id, connector->name,
12795                             bpp, 3 * info->bpc,
12796                             3 * conn_state->max_requested_bpc,
12797                             pipe_config->pipe_bpp);
12798
12799                 pipe_config->pipe_bpp = bpp;
12800         }
12801
12802         return 0;
12803 }
12804
12805 static int
12806 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12807                           struct intel_crtc_state *pipe_config)
12808 {
12809         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12810         struct drm_atomic_state *state = pipe_config->uapi.state;
12811         struct drm_connector *connector;
12812         struct drm_connector_state *connector_state;
12813         int bpp, i;
12814
12815         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12816             IS_CHERRYVIEW(dev_priv)))
12817                 bpp = 10*3;
12818         else if (INTEL_GEN(dev_priv) >= 5)
12819                 bpp = 12*3;
12820         else
12821                 bpp = 8*3;
12822
12823         pipe_config->pipe_bpp = bpp;
12824
12825         /* Clamp display bpp to connector max bpp */
12826         for_each_new_connector_in_state(state, connector, connector_state, i) {
12827                 int ret;
12828
12829                 if (connector_state->crtc != &crtc->base)
12830                         continue;
12831
12832                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12833                 if (ret)
12834                         return ret;
12835         }
12836
12837         return 0;
12838 }
12839
12840 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
12841                                     const struct drm_display_mode *mode)
12842 {
12843         drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
12844                     "type: 0x%x flags: 0x%x\n",
12845                     mode->crtc_clock,
12846                     mode->crtc_hdisplay, mode->crtc_hsync_start,
12847                     mode->crtc_hsync_end, mode->crtc_htotal,
12848                     mode->crtc_vdisplay, mode->crtc_vsync_start,
12849                     mode->crtc_vsync_end, mode->crtc_vtotal,
12850                     mode->type, mode->flags);
12851 }
12852
12853 static void
12854 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12855                       const char *id, unsigned int lane_count,
12856                       const struct intel_link_m_n *m_n)
12857 {
12858         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12859
12860         drm_dbg_kms(&i915->drm,
12861                     "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12862                     id, lane_count,
12863                     m_n->gmch_m, m_n->gmch_n,
12864                     m_n->link_m, m_n->link_n, m_n->tu);
12865 }
12866
12867 static void
12868 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12869                      const union hdmi_infoframe *frame)
12870 {
12871         if (!drm_debug_enabled(DRM_UT_KMS))
12872                 return;
12873
12874         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12875 }
12876
12877 static void
12878 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
12879                       const struct drm_dp_vsc_sdp *vsc)
12880 {
12881         if (!drm_debug_enabled(DRM_UT_KMS))
12882                 return;
12883
12884         drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
12885 }
12886
12887 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12888
12889 static const char * const output_type_str[] = {
12890         OUTPUT_TYPE(UNUSED),
12891         OUTPUT_TYPE(ANALOG),
12892         OUTPUT_TYPE(DVO),
12893         OUTPUT_TYPE(SDVO),
12894         OUTPUT_TYPE(LVDS),
12895         OUTPUT_TYPE(TVOUT),
12896         OUTPUT_TYPE(HDMI),
12897         OUTPUT_TYPE(DP),
12898         OUTPUT_TYPE(EDP),
12899         OUTPUT_TYPE(DSI),
12900         OUTPUT_TYPE(DDI),
12901         OUTPUT_TYPE(DP_MST),
12902 };
12903
12904 #undef OUTPUT_TYPE
12905
12906 static void snprintf_output_types(char *buf, size_t len,
12907                                   unsigned int output_types)
12908 {
12909         char *str = buf;
12910         int i;
12911
12912         str[0] = '\0';
12913
12914         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12915                 int r;
12916
12917                 if ((output_types & BIT(i)) == 0)
12918                         continue;
12919
12920                 r = snprintf(str, len, "%s%s",
12921                              str != buf ? "," : "", output_type_str[i]);
12922                 if (r >= len)
12923                         break;
12924                 str += r;
12925                 len -= r;
12926
12927                 output_types &= ~BIT(i);
12928         }
12929
12930         WARN_ON_ONCE(output_types != 0);
12931 }
12932
12933 static const char * const output_format_str[] = {
12934         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12935         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12936         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12937         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12938 };
12939
12940 static const char *output_formats(enum intel_output_format format)
12941 {
12942         if (format >= ARRAY_SIZE(output_format_str))
12943                 format = INTEL_OUTPUT_FORMAT_INVALID;
12944         return output_format_str[format];
12945 }
12946
12947 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12948 {
12949         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12950         struct drm_i915_private *i915 = to_i915(plane->base.dev);
12951         const struct drm_framebuffer *fb = plane_state->hw.fb;
12952         struct drm_format_name_buf format_name;
12953
12954         if (!fb) {
12955                 drm_dbg_kms(&i915->drm,
12956                             "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12957                             plane->base.base.id, plane->base.name,
12958                             yesno(plane_state->uapi.visible));
12959                 return;
12960         }
12961
12962         drm_dbg_kms(&i915->drm,
12963                     "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12964                     plane->base.base.id, plane->base.name,
12965                     fb->base.id, fb->width, fb->height,
12966                     drm_get_format_name(fb->format->format, &format_name),
12967                     yesno(plane_state->uapi.visible));
12968         drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
12969                     plane_state->hw.rotation, plane_state->scaler_id);
12970         if (plane_state->uapi.visible)
12971                 drm_dbg_kms(&i915->drm,
12972                             "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12973                             DRM_RECT_FP_ARG(&plane_state->uapi.src),
12974                             DRM_RECT_ARG(&plane_state->uapi.dst));
12975 }
12976
12977 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12978                                    struct intel_atomic_state *state,
12979                                    const char *context)
12980 {
12981         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12982         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12983         const struct intel_plane_state *plane_state;
12984         struct intel_plane *plane;
12985         char buf[64];
12986         int i;
12987
12988         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
12989                     crtc->base.base.id, crtc->base.name,
12990                     yesno(pipe_config->hw.enable), context);
12991
12992         if (!pipe_config->hw.enable)
12993                 goto dump_planes;
12994
12995         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12996         drm_dbg_kms(&dev_priv->drm,
12997                     "active: %s, output_types: %s (0x%x), output format: %s\n",
12998                     yesno(pipe_config->hw.active),
12999                     buf, pipe_config->output_types,
13000                     output_formats(pipe_config->output_format));
13001
13002         drm_dbg_kms(&dev_priv->drm,
13003                     "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13004                     transcoder_name(pipe_config->cpu_transcoder),
13005                     pipe_config->pipe_bpp, pipe_config->dither);
13006
13007         drm_dbg_kms(&dev_priv->drm,
13008                     "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13009                     transcoder_name(pipe_config->master_transcoder),
13010                     pipe_config->sync_mode_slaves_mask);
13011
13012         if (pipe_config->has_pch_encoder)
13013                 intel_dump_m_n_config(pipe_config, "fdi",
13014                                       pipe_config->fdi_lanes,
13015                                       &pipe_config->fdi_m_n);
13016
13017         if (intel_crtc_has_dp_encoder(pipe_config)) {
13018                 intel_dump_m_n_config(pipe_config, "dp m_n",
13019                                 pipe_config->lane_count, &pipe_config->dp_m_n);
13020                 if (pipe_config->has_drrs)
13021                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
13022                                               pipe_config->lane_count,
13023                                               &pipe_config->dp_m2_n2);
13024         }
13025
13026         drm_dbg_kms(&dev_priv->drm,
13027                     "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13028                     pipe_config->has_audio, pipe_config->has_infoframe,
13029                     pipe_config->infoframes.enable);
13030
13031         if (pipe_config->infoframes.enable &
13032             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13033                 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13034                             pipe_config->infoframes.gcp);
13035         if (pipe_config->infoframes.enable &
13036             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13037                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13038         if (pipe_config->infoframes.enable &
13039             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13040                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13041         if (pipe_config->infoframes.enable &
13042             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13043                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13044         if (pipe_config->infoframes.enable &
13045             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13046                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13047         if (pipe_config->infoframes.enable &
13048             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13049                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13050         if (pipe_config->infoframes.enable &
13051             intel_hdmi_infoframe_enable(DP_SDP_VSC))
13052                 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13053
13054         drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13055         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13056         drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13057         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13058         intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13059         drm_dbg_kms(&dev_priv->drm,
13060                     "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13061                     pipe_config->port_clock,
13062                     pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13063                     pipe_config->pixel_rate);
13064
13065         drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13066                     pipe_config->linetime, pipe_config->ips_linetime);
13067
13068         if (INTEL_GEN(dev_priv) >= 9)
13069                 drm_dbg_kms(&dev_priv->drm,
13070                             "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13071                             crtc->num_scalers,
13072                             pipe_config->scaler_state.scaler_users,
13073                             pipe_config->scaler_state.scaler_id);
13074
13075         if (HAS_GMCH(dev_priv))
13076                 drm_dbg_kms(&dev_priv->drm,
13077                             "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13078                             pipe_config->gmch_pfit.control,
13079                             pipe_config->gmch_pfit.pgm_ratios,
13080                             pipe_config->gmch_pfit.lvds_border_bits);
13081         else
13082                 drm_dbg_kms(&dev_priv->drm,
13083                             "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13084                             DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13085                             enableddisabled(pipe_config->pch_pfit.enabled),
13086                             yesno(pipe_config->pch_pfit.force_thru));
13087
13088         drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13089                     pipe_config->ips_enabled, pipe_config->double_wide);
13090
13091         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13092
13093         if (IS_CHERRYVIEW(dev_priv))
13094                 drm_dbg_kms(&dev_priv->drm,
13095                             "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13096                             pipe_config->cgm_mode, pipe_config->gamma_mode,
13097                             pipe_config->gamma_enable, pipe_config->csc_enable);
13098         else
13099                 drm_dbg_kms(&dev_priv->drm,
13100                             "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13101                             pipe_config->csc_mode, pipe_config->gamma_mode,
13102                             pipe_config->gamma_enable, pipe_config->csc_enable);
13103
13104         drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13105                     transcoder_name(pipe_config->mst_master_transcoder));
13106
13107 dump_planes:
13108         if (!state)
13109                 return;
13110
13111         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13112                 if (plane->pipe == crtc->pipe)
13113                         intel_dump_plane_state(plane_state);
13114         }
13115 }
13116
13117 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13118 {
13119         struct drm_device *dev = state->base.dev;
13120         struct drm_connector *connector;
13121         struct drm_connector_list_iter conn_iter;
13122         unsigned int used_ports = 0;
13123         unsigned int used_mst_ports = 0;
13124         bool ret = true;
13125
13126         /*
13127          * We're going to peek into connector->state,
13128          * hence connection_mutex must be held.
13129          */
13130         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13131
13132         /*
13133          * Walk the connector list instead of the encoder
13134          * list to detect the problem on ddi platforms
13135          * where there's just one encoder per digital port.
13136          */
13137         drm_connector_list_iter_begin(dev, &conn_iter);
13138         drm_for_each_connector_iter(connector, &conn_iter) {
13139                 struct drm_connector_state *connector_state;
13140                 struct intel_encoder *encoder;
13141
13142                 connector_state =
13143                         drm_atomic_get_new_connector_state(&state->base,
13144                                                            connector);
13145                 if (!connector_state)
13146                         connector_state = connector->state;
13147
13148                 if (!connector_state->best_encoder)
13149                         continue;
13150
13151                 encoder = to_intel_encoder(connector_state->best_encoder);
13152
13153                 drm_WARN_ON(dev, !connector_state->crtc);
13154
13155                 switch (encoder->type) {
13156                 case INTEL_OUTPUT_DDI:
13157                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13158                                 break;
13159                         /* else, fall through */
13160                 case INTEL_OUTPUT_DP:
13161                 case INTEL_OUTPUT_HDMI:
13162                 case INTEL_OUTPUT_EDP:
13163                         /* the same port mustn't appear more than once */
13164                         if (used_ports & BIT(encoder->port))
13165                                 ret = false;
13166
13167                         used_ports |= BIT(encoder->port);
13168                         break;
13169                 case INTEL_OUTPUT_DP_MST:
13170                         used_mst_ports |=
13171                                 1 << encoder->port;
13172                         break;
13173                 default:
13174                         break;
13175                 }
13176         }
13177         drm_connector_list_iter_end(&conn_iter);
13178
13179         /* can't mix MST and SST/HDMI on the same port */
13180         if (used_ports & used_mst_ports)
13181                 return false;
13182
13183         return ret;
13184 }
13185
13186 static void
13187 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13188 {
13189         intel_crtc_copy_color_blobs(crtc_state);
13190 }
13191
13192 static void
13193 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13194 {
13195         crtc_state->hw.enable = crtc_state->uapi.enable;
13196         crtc_state->hw.active = crtc_state->uapi.active;
13197         crtc_state->hw.mode = crtc_state->uapi.mode;
13198         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13199         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13200 }
13201
13202 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13203 {
13204         crtc_state->uapi.enable = crtc_state->hw.enable;
13205         crtc_state->uapi.active = crtc_state->hw.active;
13206         drm_WARN_ON(crtc_state->uapi.crtc->dev,
13207                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13208
13209         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13210
13211         /* copy color blobs to uapi */
13212         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13213                                   crtc_state->hw.degamma_lut);
13214         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13215                                   crtc_state->hw.gamma_lut);
13216         drm_property_replace_blob(&crtc_state->uapi.ctm,
13217                                   crtc_state->hw.ctm);
13218 }
13219
13220 static int
13221 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13222 {
13223         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13224         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13225         struct intel_crtc_state *saved_state;
13226
13227         saved_state = intel_crtc_state_alloc(crtc);
13228         if (!saved_state)
13229                 return -ENOMEM;
13230
13231         /* free the old crtc_state->hw members */
13232         intel_crtc_free_hw_state(crtc_state);
13233
13234         /* FIXME: before the switch to atomic started, a new pipe_config was
13235          * kzalloc'd. Code that depends on any field being zero should be
13236          * fixed, so that the crtc_state can be safely duplicated. For now,
13237          * only fields that are know to not cause problems are preserved. */
13238
13239         saved_state->uapi = crtc_state->uapi;
13240         saved_state->scaler_state = crtc_state->scaler_state;
13241         saved_state->shared_dpll = crtc_state->shared_dpll;
13242         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13243         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13244                sizeof(saved_state->icl_port_dplls));
13245         saved_state->crc_enabled = crtc_state->crc_enabled;
13246         if (IS_G4X(dev_priv) ||
13247             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13248                 saved_state->wm = crtc_state->wm;
13249
13250         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13251         kfree(saved_state);
13252
13253         intel_crtc_copy_uapi_to_hw_state(crtc_state);
13254
13255         return 0;
13256 }
13257
13258 static int
13259 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13260 {
13261         struct drm_crtc *crtc = pipe_config->uapi.crtc;
13262         struct drm_atomic_state *state = pipe_config->uapi.state;
13263         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13264         struct drm_connector *connector;
13265         struct drm_connector_state *connector_state;
13266         int base_bpp, ret, i;
13267         bool retry = true;
13268
13269         pipe_config->cpu_transcoder =
13270                 (enum transcoder) to_intel_crtc(crtc)->pipe;
13271
13272         /*
13273          * Sanitize sync polarity flags based on requested ones. If neither
13274          * positive or negative polarity is requested, treat this as meaning
13275          * negative polarity.
13276          */
13277         if (!(pipe_config->hw.adjusted_mode.flags &
13278               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13279                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13280
13281         if (!(pipe_config->hw.adjusted_mode.flags &
13282               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13283                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13284
13285         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13286                                         pipe_config);
13287         if (ret)
13288                 return ret;
13289
13290         base_bpp = pipe_config->pipe_bpp;
13291
13292         /*
13293          * Determine the real pipe dimensions. Note that stereo modes can
13294          * increase the actual pipe size due to the frame doubling and
13295          * insertion of additional space for blanks between the frame. This
13296          * is stored in the crtc timings. We use the requested mode to do this
13297          * computation to clearly distinguish it from the adjusted mode, which
13298          * can be changed by the connectors in the below retry loop.
13299          */
13300         drm_mode_get_hv_timing(&pipe_config->hw.mode,
13301                                &pipe_config->pipe_src_w,
13302                                &pipe_config->pipe_src_h);
13303
13304         for_each_new_connector_in_state(state, connector, connector_state, i) {
13305                 struct intel_encoder *encoder =
13306                         to_intel_encoder(connector_state->best_encoder);
13307
13308                 if (connector_state->crtc != crtc)
13309                         continue;
13310
13311                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13312                         drm_dbg_kms(&i915->drm,
13313                                     "rejecting invalid cloning configuration\n");
13314                         return -EINVAL;
13315                 }
13316
13317                 /*
13318                  * Determine output_types before calling the .compute_config()
13319                  * hooks so that the hooks can use this information safely.
13320                  */
13321                 if (encoder->compute_output_type)
13322                         pipe_config->output_types |=
13323                                 BIT(encoder->compute_output_type(encoder, pipe_config,
13324                                                                  connector_state));
13325                 else
13326                         pipe_config->output_types |= BIT(encoder->type);
13327         }
13328
13329 encoder_retry:
13330         /* Ensure the port clock defaults are reset when retrying. */
13331         pipe_config->port_clock = 0;
13332         pipe_config->pixel_multiplier = 1;
13333
13334         /* Fill in default crtc timings, allow encoders to overwrite them. */
13335         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13336                               CRTC_STEREO_DOUBLE);
13337
13338         /* Pass our mode to the connectors and the CRTC to give them a chance to
13339          * adjust it according to limitations or connector properties, and also
13340          * a chance to reject the mode entirely.
13341          */
13342         for_each_new_connector_in_state(state, connector, connector_state, i) {
13343                 struct intel_encoder *encoder =
13344                         to_intel_encoder(connector_state->best_encoder);
13345
13346                 if (connector_state->crtc != crtc)
13347                         continue;
13348
13349                 ret = encoder->compute_config(encoder, pipe_config,
13350                                               connector_state);
13351                 if (ret < 0) {
13352                         if (ret != -EDEADLK)
13353                                 drm_dbg_kms(&i915->drm,
13354                                             "Encoder config failure: %d\n",
13355                                             ret);
13356                         return ret;
13357                 }
13358         }
13359
13360         /* Set default port clock if not overwritten by the encoder. Needs to be
13361          * done afterwards in case the encoder adjusts the mode. */
13362         if (!pipe_config->port_clock)
13363                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13364                         * pipe_config->pixel_multiplier;
13365
13366         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13367         if (ret == -EDEADLK)
13368                 return ret;
13369         if (ret < 0) {
13370                 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13371                 return ret;
13372         }
13373
13374         if (ret == RETRY) {
13375                 if (drm_WARN(&i915->drm, !retry,
13376                              "loop in pipe configuration computation\n"))
13377                         return -EINVAL;
13378
13379                 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13380                 retry = false;
13381                 goto encoder_retry;
13382         }
13383
13384         /* Dithering seems to not pass-through bits correctly when it should, so
13385          * only enable it on 6bpc panels and when its not a compliance
13386          * test requesting 6bpc video pattern.
13387          */
13388         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13389                 !pipe_config->dither_force_disable;
13390         drm_dbg_kms(&i915->drm,
13391                     "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13392                     base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13393
13394         /*
13395          * Make drm_calc_timestamping_constants in
13396          * drm_atomic_helper_update_legacy_modeset_state() happy
13397          */
13398         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
13399
13400         return 0;
13401 }
13402
13403 static int
13404 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13405 {
13406         struct intel_atomic_state *state =
13407                 to_intel_atomic_state(crtc_state->uapi.state);
13408         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13409         struct drm_connector_state *conn_state;
13410         struct drm_connector *connector;
13411         int i;
13412
13413         for_each_new_connector_in_state(&state->base, connector,
13414                                         conn_state, i) {
13415                 struct intel_encoder *encoder =
13416                         to_intel_encoder(conn_state->best_encoder);
13417                 int ret;
13418
13419                 if (conn_state->crtc != &crtc->base ||
13420                     !encoder->compute_config_late)
13421                         continue;
13422
13423                 ret = encoder->compute_config_late(encoder, crtc_state,
13424                                                    conn_state);
13425                 if (ret)
13426                         return ret;
13427         }
13428
13429         return 0;
13430 }
13431
13432 bool intel_fuzzy_clock_check(int clock1, int clock2)
13433 {
13434         int diff;
13435
13436         if (clock1 == clock2)
13437                 return true;
13438
13439         if (!clock1 || !clock2)
13440                 return false;
13441
13442         diff = abs(clock1 - clock2);
13443
13444         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13445                 return true;
13446
13447         return false;
13448 }
13449
13450 static bool
13451 intel_compare_m_n(unsigned int m, unsigned int n,
13452                   unsigned int m2, unsigned int n2,
13453                   bool exact)
13454 {
13455         if (m == m2 && n == n2)
13456                 return true;
13457
13458         if (exact || !m || !n || !m2 || !n2)
13459                 return false;
13460
13461         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13462
13463         if (n > n2) {
13464                 while (n > n2) {
13465                         m2 <<= 1;
13466                         n2 <<= 1;
13467                 }
13468         } else if (n < n2) {
13469                 while (n < n2) {
13470                         m <<= 1;
13471                         n <<= 1;
13472                 }
13473         }
13474
13475         if (n != n2)
13476                 return false;
13477
13478         return intel_fuzzy_clock_check(m, m2);
13479 }
13480
13481 static bool
13482 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13483                        const struct intel_link_m_n *m2_n2,
13484                        bool exact)
13485 {
13486         return m_n->tu == m2_n2->tu &&
13487                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13488                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13489                 intel_compare_m_n(m_n->link_m, m_n->link_n,
13490                                   m2_n2->link_m, m2_n2->link_n, exact);
13491 }
13492
13493 static bool
13494 intel_compare_infoframe(const union hdmi_infoframe *a,
13495                         const union hdmi_infoframe *b)
13496 {
13497         return memcmp(a, b, sizeof(*a)) == 0;
13498 }
13499
13500 static bool
13501 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13502                          const struct drm_dp_vsc_sdp *b)
13503 {
13504         return memcmp(a, b, sizeof(*a)) == 0;
13505 }
13506
13507 static void
13508 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13509                                bool fastset, const char *name,
13510                                const union hdmi_infoframe *a,
13511                                const union hdmi_infoframe *b)
13512 {
13513         if (fastset) {
13514                 if (!drm_debug_enabled(DRM_UT_KMS))
13515                         return;
13516
13517                 drm_dbg_kms(&dev_priv->drm,
13518                             "fastset mismatch in %s infoframe\n", name);
13519                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13520                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13521                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13522                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13523         } else {
13524                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13525                 drm_err(&dev_priv->drm, "expected:\n");
13526                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13527                 drm_err(&dev_priv->drm, "found:\n");
13528                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13529         }
13530 }
13531
13532 static void
13533 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13534                                 bool fastset, const char *name,
13535                                 const struct drm_dp_vsc_sdp *a,
13536                                 const struct drm_dp_vsc_sdp *b)
13537 {
13538         if (fastset) {
13539                 if (!drm_debug_enabled(DRM_UT_KMS))
13540                         return;
13541
13542                 drm_dbg_kms(&dev_priv->drm,
13543                             "fastset mismatch in %s dp sdp\n", name);
13544                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13545                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13546                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13547                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13548         } else {
13549                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13550                 drm_err(&dev_priv->drm, "expected:\n");
13551                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13552                 drm_err(&dev_priv->drm, "found:\n");
13553                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13554         }
13555 }
13556
13557 static void __printf(4, 5)
13558 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13559                      const char *name, const char *format, ...)
13560 {
13561         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13562         struct va_format vaf;
13563         va_list args;
13564
13565         va_start(args, format);
13566         vaf.fmt = format;
13567         vaf.va = &args;
13568
13569         if (fastset)
13570                 drm_dbg_kms(&i915->drm,
13571                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13572                             crtc->base.base.id, crtc->base.name, name, &vaf);
13573         else
13574                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13575                         crtc->base.base.id, crtc->base.name, name, &vaf);
13576
13577         va_end(args);
13578 }
13579
13580 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13581 {
13582         if (i915_modparams.fastboot != -1)
13583                 return i915_modparams.fastboot;
13584
13585         /* Enable fastboot by default on Skylake and newer */
13586         if (INTEL_GEN(dev_priv) >= 9)
13587                 return true;
13588
13589         /* Enable fastboot by default on VLV and CHV */
13590         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13591                 return true;
13592
13593         /* Disabled by default on all others */
13594         return false;
13595 }
13596
13597 static bool
13598 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13599                           const struct intel_crtc_state *pipe_config,
13600                           bool fastset)
13601 {
13602         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13603         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13604         bool ret = true;
13605         u32 bp_gamma = 0;
13606         bool fixup_inherited = fastset &&
13607                 current_config->inherited && !pipe_config->inherited;
13608
13609         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13610                 drm_dbg_kms(&dev_priv->drm,
13611                             "initial modeset and fastboot not set\n");
13612                 ret = false;
13613         }
13614
13615 #define PIPE_CONF_CHECK_X(name) do { \
13616         if (current_config->name != pipe_config->name) { \
13617                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13618                                      "(expected 0x%08x, found 0x%08x)", \
13619                                      current_config->name, \
13620                                      pipe_config->name); \
13621                 ret = false; \
13622         } \
13623 } while (0)
13624
13625 #define PIPE_CONF_CHECK_I(name) do { \
13626         if (current_config->name != pipe_config->name) { \
13627                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13628                                      "(expected %i, found %i)", \
13629                                      current_config->name, \
13630                                      pipe_config->name); \
13631                 ret = false; \
13632         } \
13633 } while (0)
13634
13635 #define PIPE_CONF_CHECK_BOOL(name) do { \
13636         if (current_config->name != pipe_config->name) { \
13637                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13638                                      "(expected %s, found %s)", \
13639                                      yesno(current_config->name), \
13640                                      yesno(pipe_config->name)); \
13641                 ret = false; \
13642         } \
13643 } while (0)
13644
13645 /*
13646  * Checks state where we only read out the enabling, but not the entire
13647  * state itself (like full infoframes or ELD for audio). These states
13648  * require a full modeset on bootup to fix up.
13649  */
13650 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13651         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13652                 PIPE_CONF_CHECK_BOOL(name); \
13653         } else { \
13654                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13655                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13656                                      yesno(current_config->name), \
13657                                      yesno(pipe_config->name)); \
13658                 ret = false; \
13659         } \
13660 } while (0)
13661
13662 #define PIPE_CONF_CHECK_P(name) do { \
13663         if (current_config->name != pipe_config->name) { \
13664                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13665                                      "(expected %p, found %p)", \
13666                                      current_config->name, \
13667                                      pipe_config->name); \
13668                 ret = false; \
13669         } \
13670 } while (0)
13671
13672 #define PIPE_CONF_CHECK_M_N(name) do { \
13673         if (!intel_compare_link_m_n(&current_config->name, \
13674                                     &pipe_config->name,\
13675                                     !fastset)) { \
13676                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13677                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13678                                      "found tu %i, gmch %i/%i link %i/%i)", \
13679                                      current_config->name.tu, \
13680                                      current_config->name.gmch_m, \
13681                                      current_config->name.gmch_n, \
13682                                      current_config->name.link_m, \
13683                                      current_config->name.link_n, \
13684                                      pipe_config->name.tu, \
13685                                      pipe_config->name.gmch_m, \
13686                                      pipe_config->name.gmch_n, \
13687                                      pipe_config->name.link_m, \
13688                                      pipe_config->name.link_n); \
13689                 ret = false; \
13690         } \
13691 } while (0)
13692
13693 /* This is required for BDW+ where there is only one set of registers for
13694  * switching between high and low RR.
13695  * This macro can be used whenever a comparison has to be made between one
13696  * hw state and multiple sw state variables.
13697  */
13698 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13699         if (!intel_compare_link_m_n(&current_config->name, \
13700                                     &pipe_config->name, !fastset) && \
13701             !intel_compare_link_m_n(&current_config->alt_name, \
13702                                     &pipe_config->name, !fastset)) { \
13703                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13704                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13705                                      "or tu %i gmch %i/%i link %i/%i, " \
13706                                      "found tu %i, gmch %i/%i link %i/%i)", \
13707                                      current_config->name.tu, \
13708                                      current_config->name.gmch_m, \
13709                                      current_config->name.gmch_n, \
13710                                      current_config->name.link_m, \
13711                                      current_config->name.link_n, \
13712                                      current_config->alt_name.tu, \
13713                                      current_config->alt_name.gmch_m, \
13714                                      current_config->alt_name.gmch_n, \
13715                                      current_config->alt_name.link_m, \
13716                                      current_config->alt_name.link_n, \
13717                                      pipe_config->name.tu, \
13718                                      pipe_config->name.gmch_m, \
13719                                      pipe_config->name.gmch_n, \
13720                                      pipe_config->name.link_m, \
13721                                      pipe_config->name.link_n); \
13722                 ret = false; \
13723         } \
13724 } while (0)
13725
13726 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13727         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13728                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13729                                      "(%x) (expected %i, found %i)", \
13730                                      (mask), \
13731                                      current_config->name & (mask), \
13732                                      pipe_config->name & (mask)); \
13733                 ret = false; \
13734         } \
13735 } while (0)
13736
13737 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13738         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13739                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13740                                      "(expected %i, found %i)", \
13741                                      current_config->name, \
13742                                      pipe_config->name); \
13743                 ret = false; \
13744         } \
13745 } while (0)
13746
13747 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13748         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13749                                      &pipe_config->infoframes.name)) { \
13750                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13751                                                &current_config->infoframes.name, \
13752                                                &pipe_config->infoframes.name); \
13753                 ret = false; \
13754         } \
13755 } while (0)
13756
13757 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
13758         if (!current_config->has_psr && !pipe_config->has_psr && \
13759             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
13760                                       &pipe_config->infoframes.name)) { \
13761                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
13762                                                 &current_config->infoframes.name, \
13763                                                 &pipe_config->infoframes.name); \
13764                 ret = false; \
13765         } \
13766 } while (0)
13767
13768 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13769         if (current_config->name1 != pipe_config->name1) { \
13770                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13771                                 "(expected %i, found %i, won't compare lut values)", \
13772                                 current_config->name1, \
13773                                 pipe_config->name1); \
13774                 ret = false;\
13775         } else { \
13776                 if (!intel_color_lut_equal(current_config->name2, \
13777                                         pipe_config->name2, pipe_config->name1, \
13778                                         bit_precision)) { \
13779                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13780                                         "hw_state doesn't match sw_state"); \
13781                         ret = false; \
13782                 } \
13783         } \
13784 } while (0)
13785
13786 #define PIPE_CONF_QUIRK(quirk) \
13787         ((current_config->quirks | pipe_config->quirks) & (quirk))
13788
13789         PIPE_CONF_CHECK_I(cpu_transcoder);
13790
13791         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13792         PIPE_CONF_CHECK_I(fdi_lanes);
13793         PIPE_CONF_CHECK_M_N(fdi_m_n);
13794
13795         PIPE_CONF_CHECK_I(lane_count);
13796         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13797
13798         if (INTEL_GEN(dev_priv) < 8) {
13799                 PIPE_CONF_CHECK_M_N(dp_m_n);
13800
13801                 if (current_config->has_drrs)
13802                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13803         } else
13804                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13805
13806         PIPE_CONF_CHECK_X(output_types);
13807
13808         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13809         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13810         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13811         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13812         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13813         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13814
13815         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13816         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13817         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13818         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13819         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13820         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13821
13822         PIPE_CONF_CHECK_I(pixel_multiplier);
13823         PIPE_CONF_CHECK_I(output_format);
13824         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13825         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13826             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13827                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13828
13829         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13830         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13831         PIPE_CONF_CHECK_BOOL(has_infoframe);
13832         PIPE_CONF_CHECK_BOOL(fec_enable);
13833
13834         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13835
13836         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13837                               DRM_MODE_FLAG_INTERLACE);
13838
13839         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13840                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13841                                       DRM_MODE_FLAG_PHSYNC);
13842                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13843                                       DRM_MODE_FLAG_NHSYNC);
13844                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13845                                       DRM_MODE_FLAG_PVSYNC);
13846                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13847                                       DRM_MODE_FLAG_NVSYNC);
13848         }
13849
13850         PIPE_CONF_CHECK_X(gmch_pfit.control);
13851         /* pfit ratios are autocomputed by the hw on gen4+ */
13852         if (INTEL_GEN(dev_priv) < 4)
13853                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13854         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13855
13856         /*
13857          * Changing the EDP transcoder input mux
13858          * (A_ONOFF vs. A_ON) requires a full modeset.
13859          */
13860         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13861
13862         if (!fastset) {
13863                 PIPE_CONF_CHECK_I(pipe_src_w);
13864                 PIPE_CONF_CHECK_I(pipe_src_h);
13865
13866                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13867                 if (current_config->pch_pfit.enabled) {
13868                         PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
13869                         PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
13870                         PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
13871                         PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
13872                 }
13873
13874                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13875                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13876
13877                 PIPE_CONF_CHECK_X(gamma_mode);
13878                 if (IS_CHERRYVIEW(dev_priv))
13879                         PIPE_CONF_CHECK_X(cgm_mode);
13880                 else
13881                         PIPE_CONF_CHECK_X(csc_mode);
13882                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13883                 PIPE_CONF_CHECK_BOOL(csc_enable);
13884
13885                 PIPE_CONF_CHECK_I(linetime);
13886                 PIPE_CONF_CHECK_I(ips_linetime);
13887
13888                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13889                 if (bp_gamma)
13890                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13891         }
13892
13893         PIPE_CONF_CHECK_BOOL(double_wide);
13894
13895         PIPE_CONF_CHECK_P(shared_dpll);
13896         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13897         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13898         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13899         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13900         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13901         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13902         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13903         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13904         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13905         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13906         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13907         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13908         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13909         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13910         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13911         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13912         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13913         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13914         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13915         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13916         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13917         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13918         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13919         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13920         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13921         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13922         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13923         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13924         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13925         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13926         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13927
13928         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13929         PIPE_CONF_CHECK_X(dsi_pll.div);
13930
13931         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13932                 PIPE_CONF_CHECK_I(pipe_bpp);
13933
13934         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13935         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13936
13937         PIPE_CONF_CHECK_I(min_voltage_level);
13938
13939         PIPE_CONF_CHECK_X(infoframes.enable);
13940         PIPE_CONF_CHECK_X(infoframes.gcp);
13941         PIPE_CONF_CHECK_INFOFRAME(avi);
13942         PIPE_CONF_CHECK_INFOFRAME(spd);
13943         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13944         PIPE_CONF_CHECK_INFOFRAME(drm);
13945         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
13946
13947         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
13948         PIPE_CONF_CHECK_I(master_transcoder);
13949
13950         PIPE_CONF_CHECK_I(dsc.compression_enable);
13951         PIPE_CONF_CHECK_I(dsc.dsc_split);
13952         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
13953
13954         PIPE_CONF_CHECK_I(mst_master_transcoder);
13955
13956 #undef PIPE_CONF_CHECK_X
13957 #undef PIPE_CONF_CHECK_I
13958 #undef PIPE_CONF_CHECK_BOOL
13959 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13960 #undef PIPE_CONF_CHECK_P
13961 #undef PIPE_CONF_CHECK_FLAGS
13962 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13963 #undef PIPE_CONF_CHECK_COLOR_LUT
13964 #undef PIPE_CONF_QUIRK
13965
13966         return ret;
13967 }
13968
13969 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13970                                            const struct intel_crtc_state *pipe_config)
13971 {
13972         if (pipe_config->has_pch_encoder) {
13973                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13974                                                             &pipe_config->fdi_m_n);
13975                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13976
13977                 /*
13978                  * FDI already provided one idea for the dotclock.
13979                  * Yell if the encoder disagrees.
13980                  */
13981                 drm_WARN(&dev_priv->drm,
13982                          !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13983                          "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13984                          fdi_dotclock, dotclock);
13985         }
13986 }
13987
13988 static void verify_wm_state(struct intel_crtc *crtc,
13989                             struct intel_crtc_state *new_crtc_state)
13990 {
13991         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13992         struct skl_hw_state {
13993                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13994                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13995                 struct skl_pipe_wm wm;
13996         } *hw;
13997         struct skl_pipe_wm *sw_wm;
13998         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13999         u8 hw_enabled_slices;
14000         const enum pipe pipe = crtc->pipe;
14001         int plane, level, max_level = ilk_wm_max_level(dev_priv);
14002
14003         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14004                 return;
14005
14006         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14007         if (!hw)
14008                 return;
14009
14010         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14011         sw_wm = &new_crtc_state->wm.skl.optimal;
14012
14013         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14014
14015         hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14016
14017         if (INTEL_GEN(dev_priv) >= 11 &&
14018             hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14019                 drm_err(&dev_priv->drm,
14020                         "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14021                         dev_priv->dbuf.enabled_slices,
14022                         hw_enabled_slices);
14023
14024         /* planes */
14025         for_each_universal_plane(dev_priv, pipe, plane) {
14026                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14027
14028                 hw_plane_wm = &hw->wm.planes[plane];
14029                 sw_plane_wm = &sw_wm->planes[plane];
14030
14031                 /* Watermarks */
14032                 for (level = 0; level <= max_level; level++) {
14033                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14034                                                 &sw_plane_wm->wm[level]) ||
14035                             (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14036                                                                &sw_plane_wm->sagv_wm0)))
14037                                 continue;
14038
14039                         drm_err(&dev_priv->drm,
14040                                 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14041                                 pipe_name(pipe), plane + 1, level,
14042                                 sw_plane_wm->wm[level].plane_en,
14043                                 sw_plane_wm->wm[level].plane_res_b,
14044                                 sw_plane_wm->wm[level].plane_res_l,
14045                                 hw_plane_wm->wm[level].plane_en,
14046                                 hw_plane_wm->wm[level].plane_res_b,
14047                                 hw_plane_wm->wm[level].plane_res_l);
14048                 }
14049
14050                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14051                                          &sw_plane_wm->trans_wm)) {
14052                         drm_err(&dev_priv->drm,
14053                                 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14054                                 pipe_name(pipe), plane + 1,
14055                                 sw_plane_wm->trans_wm.plane_en,
14056                                 sw_plane_wm->trans_wm.plane_res_b,
14057                                 sw_plane_wm->trans_wm.plane_res_l,
14058                                 hw_plane_wm->trans_wm.plane_en,
14059                                 hw_plane_wm->trans_wm.plane_res_b,
14060                                 hw_plane_wm->trans_wm.plane_res_l);
14061                 }
14062
14063                 /* DDB */
14064                 hw_ddb_entry = &hw->ddb_y[plane];
14065                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14066
14067                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14068                         drm_err(&dev_priv->drm,
14069                                 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14070                                 pipe_name(pipe), plane + 1,
14071                                 sw_ddb_entry->start, sw_ddb_entry->end,
14072                                 hw_ddb_entry->start, hw_ddb_entry->end);
14073                 }
14074         }
14075
14076         /*
14077          * cursor
14078          * If the cursor plane isn't active, we may not have updated it's ddb
14079          * allocation. In that case since the ddb allocation will be updated
14080          * once the plane becomes visible, we can skip this check
14081          */
14082         if (1) {
14083                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14084
14085                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14086                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14087
14088                 /* Watermarks */
14089                 for (level = 0; level <= max_level; level++) {
14090                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14091                                                 &sw_plane_wm->wm[level]) ||
14092                             (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14093                                                                &sw_plane_wm->sagv_wm0)))
14094                                 continue;
14095
14096                         drm_err(&dev_priv->drm,
14097                                 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14098                                 pipe_name(pipe), level,
14099                                 sw_plane_wm->wm[level].plane_en,
14100                                 sw_plane_wm->wm[level].plane_res_b,
14101                                 sw_plane_wm->wm[level].plane_res_l,
14102                                 hw_plane_wm->wm[level].plane_en,
14103                                 hw_plane_wm->wm[level].plane_res_b,
14104                                 hw_plane_wm->wm[level].plane_res_l);
14105                 }
14106
14107                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14108                                          &sw_plane_wm->trans_wm)) {
14109                         drm_err(&dev_priv->drm,
14110                                 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14111                                 pipe_name(pipe),
14112                                 sw_plane_wm->trans_wm.plane_en,
14113                                 sw_plane_wm->trans_wm.plane_res_b,
14114                                 sw_plane_wm->trans_wm.plane_res_l,
14115                                 hw_plane_wm->trans_wm.plane_en,
14116                                 hw_plane_wm->trans_wm.plane_res_b,
14117                                 hw_plane_wm->trans_wm.plane_res_l);
14118                 }
14119
14120                 /* DDB */
14121                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14122                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14123
14124                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14125                         drm_err(&dev_priv->drm,
14126                                 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14127                                 pipe_name(pipe),
14128                                 sw_ddb_entry->start, sw_ddb_entry->end,
14129                                 hw_ddb_entry->start, hw_ddb_entry->end);
14130                 }
14131         }
14132
14133         kfree(hw);
14134 }
14135
14136 static void
14137 verify_connector_state(struct intel_atomic_state *state,
14138                        struct intel_crtc *crtc)
14139 {
14140         struct drm_connector *connector;
14141         struct drm_connector_state *new_conn_state;
14142         int i;
14143
14144         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14145                 struct drm_encoder *encoder = connector->encoder;
14146                 struct intel_crtc_state *crtc_state = NULL;
14147
14148                 if (new_conn_state->crtc != &crtc->base)
14149                         continue;
14150
14151                 if (crtc)
14152                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14153
14154                 intel_connector_verify_state(crtc_state, new_conn_state);
14155
14156                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14157                      "connector's atomic encoder doesn't match legacy encoder\n");
14158         }
14159 }
14160
14161 static void
14162 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14163 {
14164         struct intel_encoder *encoder;
14165         struct drm_connector *connector;
14166         struct drm_connector_state *old_conn_state, *new_conn_state;
14167         int i;
14168
14169         for_each_intel_encoder(&dev_priv->drm, encoder) {
14170                 bool enabled = false, found = false;
14171                 enum pipe pipe;
14172
14173                 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14174                             encoder->base.base.id,
14175                             encoder->base.name);
14176
14177                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14178                                                    new_conn_state, i) {
14179                         if (old_conn_state->best_encoder == &encoder->base)
14180                                 found = true;
14181
14182                         if (new_conn_state->best_encoder != &encoder->base)
14183                                 continue;
14184                         found = enabled = true;
14185
14186                         I915_STATE_WARN(new_conn_state->crtc !=
14187                                         encoder->base.crtc,
14188                              "connector's crtc doesn't match encoder crtc\n");
14189                 }
14190
14191                 if (!found)
14192                         continue;
14193
14194                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14195                      "encoder's enabled state mismatch "
14196                      "(expected %i, found %i)\n",
14197                      !!encoder->base.crtc, enabled);
14198
14199                 if (!encoder->base.crtc) {
14200                         bool active;
14201
14202                         active = encoder->get_hw_state(encoder, &pipe);
14203                         I915_STATE_WARN(active,
14204                              "encoder detached but still enabled on pipe %c.\n",
14205                              pipe_name(pipe));
14206                 }
14207         }
14208 }
14209
14210 static void
14211 verify_crtc_state(struct intel_crtc *crtc,
14212                   struct intel_crtc_state *old_crtc_state,
14213                   struct intel_crtc_state *new_crtc_state)
14214 {
14215         struct drm_device *dev = crtc->base.dev;
14216         struct drm_i915_private *dev_priv = to_i915(dev);
14217         struct intel_encoder *encoder;
14218         struct intel_crtc_state *pipe_config = old_crtc_state;
14219         struct drm_atomic_state *state = old_crtc_state->uapi.state;
14220         bool active;
14221
14222         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14223         intel_crtc_free_hw_state(old_crtc_state);
14224         intel_crtc_state_reset(old_crtc_state, crtc);
14225         old_crtc_state->uapi.state = state;
14226
14227         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14228                     crtc->base.name);
14229
14230         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
14231
14232         /* we keep both pipes enabled on 830 */
14233         if (IS_I830(dev_priv))
14234                 active = new_crtc_state->hw.active;
14235
14236         I915_STATE_WARN(new_crtc_state->hw.active != active,
14237                         "crtc active state doesn't match with hw state "
14238                         "(expected %i, found %i)\n",
14239                         new_crtc_state->hw.active, active);
14240
14241         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14242                         "transitional active state does not match atomic hw state "
14243                         "(expected %i, found %i)\n",
14244                         new_crtc_state->hw.active, crtc->active);
14245
14246         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14247                 enum pipe pipe;
14248
14249                 active = encoder->get_hw_state(encoder, &pipe);
14250                 I915_STATE_WARN(active != new_crtc_state->hw.active,
14251                                 "[ENCODER:%i] active %i with crtc active %i\n",
14252                                 encoder->base.base.id, active,
14253                                 new_crtc_state->hw.active);
14254
14255                 I915_STATE_WARN(active && crtc->pipe != pipe,
14256                                 "Encoder connected to wrong pipe %c\n",
14257                                 pipe_name(pipe));
14258
14259                 if (active)
14260                         encoder->get_config(encoder, pipe_config);
14261         }
14262
14263         intel_crtc_compute_pixel_rate(pipe_config);
14264
14265         if (!new_crtc_state->hw.active)
14266                 return;
14267
14268         intel_pipe_config_sanity_check(dev_priv, pipe_config);
14269
14270         if (!intel_pipe_config_compare(new_crtc_state,
14271                                        pipe_config, false)) {
14272                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14273                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14274                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14275         }
14276 }
14277
14278 static void
14279 intel_verify_planes(struct intel_atomic_state *state)
14280 {
14281         struct intel_plane *plane;
14282         const struct intel_plane_state *plane_state;
14283         int i;
14284
14285         for_each_new_intel_plane_in_state(state, plane,
14286                                           plane_state, i)
14287                 assert_plane(plane, plane_state->planar_slave ||
14288                              plane_state->uapi.visible);
14289 }
14290
14291 static void
14292 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14293                          struct intel_shared_dpll *pll,
14294                          struct intel_crtc *crtc,
14295                          struct intel_crtc_state *new_crtc_state)
14296 {
14297         struct intel_dpll_hw_state dpll_hw_state;
14298         unsigned int crtc_mask;
14299         bool active;
14300
14301         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14302
14303         drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14304
14305         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14306
14307         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14308                 I915_STATE_WARN(!pll->on && pll->active_mask,
14309                      "pll in active use but not on in sw tracking\n");
14310                 I915_STATE_WARN(pll->on && !pll->active_mask,
14311                      "pll is on but not used by any active crtc\n");
14312                 I915_STATE_WARN(pll->on != active,
14313                      "pll on state mismatch (expected %i, found %i)\n",
14314                      pll->on, active);
14315         }
14316
14317         if (!crtc) {
14318                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14319                                 "more active pll users than references: %x vs %x\n",
14320                                 pll->active_mask, pll->state.crtc_mask);
14321
14322                 return;
14323         }
14324
14325         crtc_mask = drm_crtc_mask(&crtc->base);
14326
14327         if (new_crtc_state->hw.active)
14328                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14329                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14330                                 pipe_name(crtc->pipe), pll->active_mask);
14331         else
14332                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14333                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14334                                 pipe_name(crtc->pipe), pll->active_mask);
14335
14336         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14337                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14338                         crtc_mask, pll->state.crtc_mask);
14339
14340         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14341                                           &dpll_hw_state,
14342                                           sizeof(dpll_hw_state)),
14343                         "pll hw state mismatch\n");
14344 }
14345
14346 static void
14347 verify_shared_dpll_state(struct intel_crtc *crtc,
14348                          struct intel_crtc_state *old_crtc_state,
14349                          struct intel_crtc_state *new_crtc_state)
14350 {
14351         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14352
14353         if (new_crtc_state->shared_dpll)
14354                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14355
14356         if (old_crtc_state->shared_dpll &&
14357             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14358                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14359                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14360
14361                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14362                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14363                                 pipe_name(crtc->pipe));
14364                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14365                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14366                                 pipe_name(crtc->pipe));
14367         }
14368 }
14369
14370 static void
14371 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14372                           struct intel_atomic_state *state,
14373                           struct intel_crtc_state *old_crtc_state,
14374                           struct intel_crtc_state *new_crtc_state)
14375 {
14376         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14377                 return;
14378
14379         verify_wm_state(crtc, new_crtc_state);
14380         verify_connector_state(state, crtc);
14381         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14382         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14383 }
14384
14385 static void
14386 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14387 {
14388         int i;
14389
14390         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14391                 verify_single_dpll_state(dev_priv,
14392                                          &dev_priv->dpll.shared_dplls[i],
14393                                          NULL, NULL);
14394 }
14395
14396 static void
14397 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14398                               struct intel_atomic_state *state)
14399 {
14400         verify_encoder_state(dev_priv, state);
14401         verify_connector_state(state, NULL);
14402         verify_disabled_dpll_state(dev_priv);
14403 }
14404
14405 static void
14406 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14407 {
14408         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14409         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14410         const struct drm_display_mode *adjusted_mode =
14411                 &crtc_state->hw.adjusted_mode;
14412
14413         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14414
14415         crtc->mode_flags = crtc_state->mode_flags;
14416
14417         /*
14418          * The scanline counter increments at the leading edge of hsync.
14419          *
14420          * On most platforms it starts counting from vtotal-1 on the
14421          * first active line. That means the scanline counter value is
14422          * always one less than what we would expect. Ie. just after
14423          * start of vblank, which also occurs at start of hsync (on the
14424          * last active line), the scanline counter will read vblank_start-1.
14425          *
14426          * On gen2 the scanline counter starts counting from 1 instead
14427          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14428          * to keep the value positive), instead of adding one.
14429          *
14430          * On HSW+ the behaviour of the scanline counter depends on the output
14431          * type. For DP ports it behaves like most other platforms, but on HDMI
14432          * there's an extra 1 line difference. So we need to add two instead of
14433          * one to the value.
14434          *
14435          * On VLV/CHV DSI the scanline counter would appear to increment
14436          * approx. 1/3 of a scanline before start of vblank. Unfortunately
14437          * that means we can't tell whether we're in vblank or not while
14438          * we're on that particular line. We must still set scanline_offset
14439          * to 1 so that the vblank timestamps come out correct when we query
14440          * the scanline counter from within the vblank interrupt handler.
14441          * However if queried just before the start of vblank we'll get an
14442          * answer that's slightly in the future.
14443          */
14444         if (IS_GEN(dev_priv, 2)) {
14445                 int vtotal;
14446
14447                 vtotal = adjusted_mode->crtc_vtotal;
14448                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14449                         vtotal /= 2;
14450
14451                 crtc->scanline_offset = vtotal - 1;
14452         } else if (HAS_DDI(dev_priv) &&
14453                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14454                 crtc->scanline_offset = 2;
14455         } else {
14456                 crtc->scanline_offset = 1;
14457         }
14458 }
14459
14460 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14461 {
14462         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14463         struct intel_crtc_state *new_crtc_state;
14464         struct intel_crtc *crtc;
14465         int i;
14466
14467         if (!dev_priv->display.crtc_compute_clock)
14468                 return;
14469
14470         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14471                 if (!needs_modeset(new_crtc_state))
14472                         continue;
14473
14474                 intel_release_shared_dplls(state, crtc);
14475         }
14476 }
14477
14478 /*
14479  * This implements the workaround described in the "notes" section of the mode
14480  * set sequence documentation. When going from no pipes or single pipe to
14481  * multiple pipes, and planes are enabled after the pipe, we need to wait at
14482  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14483  */
14484 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14485 {
14486         struct intel_crtc_state *crtc_state;
14487         struct intel_crtc *crtc;
14488         struct intel_crtc_state *first_crtc_state = NULL;
14489         struct intel_crtc_state *other_crtc_state = NULL;
14490         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14491         int i;
14492
14493         /* look at all crtc's that are going to be enabled in during modeset */
14494         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14495                 if (!crtc_state->hw.active ||
14496                     !needs_modeset(crtc_state))
14497                         continue;
14498
14499                 if (first_crtc_state) {
14500                         other_crtc_state = crtc_state;
14501                         break;
14502                 } else {
14503                         first_crtc_state = crtc_state;
14504                         first_pipe = crtc->pipe;
14505                 }
14506         }
14507
14508         /* No workaround needed? */
14509         if (!first_crtc_state)
14510                 return 0;
14511
14512         /* w/a possibly needed, check how many crtc's are already enabled. */
14513         for_each_intel_crtc(state->base.dev, crtc) {
14514                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14515                 if (IS_ERR(crtc_state))
14516                         return PTR_ERR(crtc_state);
14517
14518                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14519
14520                 if (!crtc_state->hw.active ||
14521                     needs_modeset(crtc_state))
14522                         continue;
14523
14524                 /* 2 or more enabled crtcs means no need for w/a */
14525                 if (enabled_pipe != INVALID_PIPE)
14526                         return 0;
14527
14528                 enabled_pipe = crtc->pipe;
14529         }
14530
14531         if (enabled_pipe != INVALID_PIPE)
14532                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14533         else if (other_crtc_state)
14534                 other_crtc_state->hsw_workaround_pipe = first_pipe;
14535
14536         return 0;
14537 }
14538
14539 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14540                            u8 active_pipes)
14541 {
14542         const struct intel_crtc_state *crtc_state;
14543         struct intel_crtc *crtc;
14544         int i;
14545
14546         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14547                 if (crtc_state->hw.active)
14548                         active_pipes |= BIT(crtc->pipe);
14549                 else
14550                         active_pipes &= ~BIT(crtc->pipe);
14551         }
14552
14553         return active_pipes;
14554 }
14555
14556 static int intel_modeset_checks(struct intel_atomic_state *state)
14557 {
14558         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14559         int ret;
14560
14561         state->modeset = true;
14562         state->active_pipes = intel_calc_active_pipes(state, dev_priv->active_pipes);
14563
14564         if (state->active_pipes != dev_priv->active_pipes) {
14565                 ret = _intel_atomic_lock_global_state(state);
14566                 if (ret)
14567                         return ret;
14568         }
14569
14570         if (IS_HASWELL(dev_priv))
14571                 return hsw_mode_set_planes_workaround(state);
14572
14573         return 0;
14574 }
14575
14576 /*
14577  * Handle calculation of various watermark data at the end of the atomic check
14578  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14579  * handlers to ensure that all derived state has been updated.
14580  */
14581 static int calc_watermark_data(struct intel_atomic_state *state)
14582 {
14583         struct drm_device *dev = state->base.dev;
14584         struct drm_i915_private *dev_priv = to_i915(dev);
14585
14586         /* Is there platform-specific watermark information to calculate? */
14587         if (dev_priv->display.compute_global_watermarks)
14588                 return dev_priv->display.compute_global_watermarks(state);
14589
14590         return 0;
14591 }
14592
14593 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14594                                      struct intel_crtc_state *new_crtc_state)
14595 {
14596         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14597                 return;
14598
14599         new_crtc_state->uapi.mode_changed = false;
14600         new_crtc_state->update_pipe = true;
14601 }
14602
14603 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14604                                     struct intel_crtc_state *new_crtc_state)
14605 {
14606         /*
14607          * If we're not doing the full modeset we want to
14608          * keep the current M/N values as they may be
14609          * sufficiently different to the computed values
14610          * to cause problems.
14611          *
14612          * FIXME: should really copy more fuzzy state here
14613          */
14614         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14615         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14616         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14617         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14618 }
14619
14620 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14621                                           struct intel_crtc *crtc,
14622                                           u8 plane_ids_mask)
14623 {
14624         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14625         struct intel_plane *plane;
14626
14627         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14628                 struct intel_plane_state *plane_state;
14629
14630                 if ((plane_ids_mask & BIT(plane->id)) == 0)
14631                         continue;
14632
14633                 plane_state = intel_atomic_get_plane_state(state, plane);
14634                 if (IS_ERR(plane_state))
14635                         return PTR_ERR(plane_state);
14636         }
14637
14638         return 0;
14639 }
14640
14641 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14642 {
14643         /* See {hsw,vlv,ivb}_plane_ratio() */
14644         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14645                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14646                 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14647 }
14648
14649 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14650 {
14651         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14652         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14653         struct intel_plane_state *plane_state;
14654         struct intel_plane *plane;
14655         struct intel_crtc *crtc;
14656         int i, ret;
14657
14658         ret = icl_add_linked_planes(state);
14659         if (ret)
14660                 return ret;
14661
14662         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14663                 ret = intel_plane_atomic_check(state, plane);
14664                 if (ret) {
14665                         drm_dbg_atomic(&dev_priv->drm,
14666                                        "[PLANE:%d:%s] atomic driver check failed\n",
14667                                        plane->base.base.id, plane->base.name);
14668                         return ret;
14669                 }
14670         }
14671
14672         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14673                                             new_crtc_state, i) {
14674                 u8 old_active_planes, new_active_planes;
14675
14676                 ret = icl_check_nv12_planes(new_crtc_state);
14677                 if (ret)
14678                         return ret;
14679
14680                 /*
14681                  * On some platforms the number of active planes affects
14682                  * the planes' minimum cdclk calculation. Add such planes
14683                  * to the state before we compute the minimum cdclk.
14684                  */
14685                 if (!active_planes_affects_min_cdclk(dev_priv))
14686                         continue;
14687
14688                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14689                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14690
14691                 /*
14692                  * Not only the number of planes, but if the plane configuration had
14693                  * changed might already mean we need to recompute min CDCLK,
14694                  * because different planes might consume different amount of Dbuf bandwidth
14695                  * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14696                  */
14697                 if (old_active_planes == new_active_planes)
14698                         continue;
14699
14700                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14701                 if (ret)
14702                         return ret;
14703         }
14704
14705         return 0;
14706 }
14707
14708 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14709                                     bool *need_cdclk_calc)
14710 {
14711         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14712         int i;
14713         struct intel_plane_state *plane_state;
14714         struct intel_plane *plane;
14715         int ret;
14716         struct intel_cdclk_state *new_cdclk_state;
14717         struct intel_crtc_state *new_crtc_state;
14718         struct intel_crtc *crtc;
14719         /*
14720          * active_planes bitmask has been updated, and potentially
14721          * affected planes are part of the state. We can now
14722          * compute the minimum cdclk for each plane.
14723          */
14724         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14725                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14726                 if (ret)
14727                         return ret;
14728         }
14729
14730         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14731
14732         if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
14733                 *need_cdclk_calc = true;
14734
14735         ret = dev_priv->display.bw_calc_min_cdclk(state);
14736         if (ret)
14737                 return ret;
14738
14739         if (!new_cdclk_state)
14740                 return 0;
14741
14742         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14743                 struct intel_bw_state *bw_state;
14744                 int min_cdclk = 0;
14745
14746                 min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
14747
14748                 bw_state = intel_atomic_get_bw_state(state);
14749                 if (IS_ERR(bw_state))
14750                         return PTR_ERR(bw_state);
14751
14752                 /*
14753                  * Currently do this change only if we need to increase
14754                  */
14755                 if (bw_state->min_cdclk > min_cdclk)
14756                         *need_cdclk_calc = true;
14757         }
14758
14759         return 0;
14760 }
14761
14762 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14763 {
14764         struct intel_crtc_state *crtc_state;
14765         struct intel_crtc *crtc;
14766         int i;
14767
14768         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14769                 int ret = intel_crtc_atomic_check(state, crtc);
14770                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14771                 if (ret) {
14772                         drm_dbg_atomic(&i915->drm,
14773                                        "[CRTC:%d:%s] atomic driver check failed\n",
14774                                        crtc->base.base.id, crtc->base.name);
14775                         return ret;
14776                 }
14777         }
14778
14779         return 0;
14780 }
14781
14782 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14783                                                u8 transcoders)
14784 {
14785         const struct intel_crtc_state *new_crtc_state;
14786         struct intel_crtc *crtc;
14787         int i;
14788
14789         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14790                 if (new_crtc_state->hw.enable &&
14791                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14792                     needs_modeset(new_crtc_state))
14793                         return true;
14794         }
14795
14796         return false;
14797 }
14798
14799 /**
14800  * intel_atomic_check - validate state object
14801  * @dev: drm device
14802  * @_state: state to validate
14803  */
14804 static int intel_atomic_check(struct drm_device *dev,
14805                               struct drm_atomic_state *_state)
14806 {
14807         struct drm_i915_private *dev_priv = to_i915(dev);
14808         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14809         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14810         struct intel_crtc *crtc;
14811         int ret, i;
14812         bool any_ms = false;
14813
14814         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14815                                             new_crtc_state, i) {
14816                 if (new_crtc_state->inherited != old_crtc_state->inherited)
14817                         new_crtc_state->uapi.mode_changed = true;
14818         }
14819
14820         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14821         if (ret)
14822                 goto fail;
14823
14824         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14825                                             new_crtc_state, i) {
14826                 if (!needs_modeset(new_crtc_state)) {
14827                         /* Light copy */
14828                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14829
14830                         continue;
14831                 }
14832
14833                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14834                 if (ret)
14835                         goto fail;
14836
14837                 if (!new_crtc_state->hw.enable)
14838                         continue;
14839
14840                 ret = intel_modeset_pipe_config(new_crtc_state);
14841                 if (ret)
14842                         goto fail;
14843         }
14844
14845         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14846                                             new_crtc_state, i) {
14847                 if (!needs_modeset(new_crtc_state))
14848                         continue;
14849
14850                 ret = intel_modeset_pipe_config_late(new_crtc_state);
14851                 if (ret)
14852                         goto fail;
14853
14854                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14855         }
14856
14857         /**
14858          * Check if fastset is allowed by external dependencies like other
14859          * pipes and transcoders.
14860          *
14861          * Right now it only forces a fullmodeset when the MST master
14862          * transcoder did not changed but the pipe of the master transcoder
14863          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
14864          * in case of port synced crtcs, if one of the synced crtcs
14865          * needs a full modeset, all other synced crtcs should be
14866          * forced a full modeset.
14867          */
14868         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14869                 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
14870                         continue;
14871
14872                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
14873                         enum transcoder master = new_crtc_state->mst_master_transcoder;
14874
14875                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
14876                                 new_crtc_state->uapi.mode_changed = true;
14877                                 new_crtc_state->update_pipe = false;
14878                         }
14879                 }
14880
14881                 if (is_trans_port_sync_mode(new_crtc_state)) {
14882                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
14883
14884                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
14885                                 trans |= BIT(new_crtc_state->master_transcoder);
14886
14887                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
14888                                 new_crtc_state->uapi.mode_changed = true;
14889                                 new_crtc_state->update_pipe = false;
14890                         }
14891                 }
14892         }
14893
14894         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14895                                             new_crtc_state, i) {
14896                 if (needs_modeset(new_crtc_state)) {
14897                         any_ms = true;
14898                         continue;
14899                 }
14900
14901                 if (!new_crtc_state->update_pipe)
14902                         continue;
14903
14904                 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
14905         }
14906
14907         if (any_ms && !check_digital_port_conflicts(state)) {
14908                 drm_dbg_kms(&dev_priv->drm,
14909                             "rejecting conflicting digital port configuration\n");
14910                 ret = EINVAL;
14911                 goto fail;
14912         }
14913
14914         ret = drm_dp_mst_atomic_check(&state->base);
14915         if (ret)
14916                 goto fail;
14917
14918         ret = intel_atomic_check_planes(state);
14919         if (ret)
14920                 goto fail;
14921
14922         /*
14923          * distrust_bios_wm will force a full dbuf recomputation
14924          * but the hardware state will only get updated accordingly
14925          * if state->modeset==true. Hence distrust_bios_wm==true &&
14926          * state->modeset==false is an invalid combination which
14927          * would cause the hardware and software dbuf state to get
14928          * out of sync. We must prevent that.
14929          *
14930          * FIXME clean up this mess and introduce better
14931          * state tracking for dbuf.
14932          */
14933         if (dev_priv->wm.distrust_bios_wm)
14934                 any_ms = true;
14935
14936         if (any_ms) {
14937                 ret = intel_modeset_checks(state);
14938                 if (ret)
14939                         goto fail;
14940         }
14941
14942         intel_fbc_choose_crtc(dev_priv, state);
14943         ret = calc_watermark_data(state);
14944         if (ret)
14945                 goto fail;
14946
14947         ret = intel_bw_atomic_check(state);
14948         if (ret)
14949                 goto fail;
14950
14951         ret = intel_atomic_check_cdclk(state, &any_ms);
14952         if (ret)
14953                 goto fail;
14954
14955         if (any_ms) {
14956                 ret = intel_modeset_calc_cdclk(state);
14957                 if (ret)
14958                         return ret;
14959
14960                 intel_modeset_clear_plls(state);
14961         }
14962
14963         ret = intel_atomic_check_crtcs(state);
14964         if (ret)
14965                 goto fail;
14966
14967         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14968                                             new_crtc_state, i) {
14969                 if (!needs_modeset(new_crtc_state) &&
14970                     !new_crtc_state->update_pipe)
14971                         continue;
14972
14973                 intel_dump_pipe_config(new_crtc_state, state,
14974                                        needs_modeset(new_crtc_state) ?
14975                                        "[modeset]" : "[fastset]");
14976         }
14977
14978         return 0;
14979
14980  fail:
14981         if (ret == -EDEADLK)
14982                 return ret;
14983
14984         /*
14985          * FIXME would probably be nice to know which crtc specifically
14986          * caused the failure, in cases where we can pinpoint it.
14987          */
14988         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14989                                             new_crtc_state, i)
14990                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14991
14992         return ret;
14993 }
14994
14995 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14996 {
14997         struct intel_crtc_state *crtc_state;
14998         struct intel_crtc *crtc;
14999         int i, ret;
15000
15001         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15002         if (ret < 0)
15003                 return ret;
15004
15005         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15006                 bool mode_changed = needs_modeset(crtc_state);
15007
15008                 if (mode_changed || crtc_state->update_pipe ||
15009                     crtc_state->uapi.color_mgmt_changed) {
15010                         intel_dsb_prepare(crtc_state);
15011                 }
15012         }
15013
15014         return 0;
15015 }
15016
15017 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15018 {
15019         struct drm_device *dev = crtc->base.dev;
15020         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15021
15022         if (!vblank->max_vblank_count)
15023                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15024
15025         return crtc->base.funcs->get_vblank_counter(&crtc->base);
15026 }
15027
15028 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15029                                   struct intel_crtc_state *crtc_state)
15030 {
15031         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15032
15033         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15034                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15035
15036         if (crtc_state->has_pch_encoder) {
15037                 enum pipe pch_transcoder =
15038                         intel_crtc_pch_transcoder(crtc);
15039
15040                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15041         }
15042 }
15043
15044 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15045                                const struct intel_crtc_state *new_crtc_state)
15046 {
15047         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15048         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15049
15050         /*
15051          * Update pipe size and adjust fitter if needed: the reason for this is
15052          * that in compute_mode_changes we check the native mode (not the pfit
15053          * mode) to see if we can flip rather than do a full mode set. In the
15054          * fastboot case, we'll flip, but if we don't update the pipesrc and
15055          * pfit state, we'll end up with a big fb scanned out into the wrong
15056          * sized surface.
15057          */
15058         intel_set_pipe_src_size(new_crtc_state);
15059
15060         /* on skylake this is done by detaching scalers */
15061         if (INTEL_GEN(dev_priv) >= 9) {
15062                 skl_detach_scalers(new_crtc_state);
15063
15064                 if (new_crtc_state->pch_pfit.enabled)
15065                         skl_pfit_enable(new_crtc_state);
15066         } else if (HAS_PCH_SPLIT(dev_priv)) {
15067                 if (new_crtc_state->pch_pfit.enabled)
15068                         ilk_pfit_enable(new_crtc_state);
15069                 else if (old_crtc_state->pch_pfit.enabled)
15070                         ilk_pfit_disable(old_crtc_state);
15071         }
15072
15073         /*
15074          * The register is supposedly single buffered so perhaps
15075          * not 100% correct to do this here. But SKL+ calculate
15076          * this based on the adjust pixel rate so pfit changes do
15077          * affect it and so it must be updated for fastsets.
15078          * HSW/BDW only really need this here for fastboot, after
15079          * that the value should not change without a full modeset.
15080          */
15081         if (INTEL_GEN(dev_priv) >= 9 ||
15082             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15083                 hsw_set_linetime_wm(new_crtc_state);
15084
15085         if (INTEL_GEN(dev_priv) >= 11)
15086                 icl_set_pipe_chicken(crtc);
15087 }
15088
15089 static void commit_pipe_config(struct intel_atomic_state *state,
15090                                struct intel_crtc *crtc)
15091 {
15092         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15093         const struct intel_crtc_state *old_crtc_state =
15094                 intel_atomic_get_old_crtc_state(state, crtc);
15095         const struct intel_crtc_state *new_crtc_state =
15096                 intel_atomic_get_new_crtc_state(state, crtc);
15097         bool modeset = needs_modeset(new_crtc_state);
15098
15099         /*
15100          * During modesets pipe configuration was programmed as the
15101          * CRTC was enabled.
15102          */
15103         if (!modeset) {
15104                 if (new_crtc_state->uapi.color_mgmt_changed ||
15105                     new_crtc_state->update_pipe)
15106                         intel_color_commit(new_crtc_state);
15107
15108                 if (INTEL_GEN(dev_priv) >= 9)
15109                         skl_detach_scalers(new_crtc_state);
15110
15111                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15112                         bdw_set_pipemisc(new_crtc_state);
15113
15114                 if (new_crtc_state->update_pipe)
15115                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
15116         }
15117
15118         if (dev_priv->display.atomic_update_watermarks)
15119                 dev_priv->display.atomic_update_watermarks(state, crtc);
15120 }
15121
15122 static void intel_enable_crtc(struct intel_atomic_state *state,
15123                               struct intel_crtc *crtc)
15124 {
15125         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15126         const struct intel_crtc_state *new_crtc_state =
15127                 intel_atomic_get_new_crtc_state(state, crtc);
15128
15129         if (!needs_modeset(new_crtc_state))
15130                 return;
15131
15132         intel_crtc_update_active_timings(new_crtc_state);
15133
15134         dev_priv->display.crtc_enable(state, crtc);
15135
15136         /* vblanks work again, re-enable pipe CRC. */
15137         intel_crtc_enable_pipe_crc(crtc);
15138 }
15139
15140 static void intel_update_crtc(struct intel_atomic_state *state,
15141                               struct intel_crtc *crtc)
15142 {
15143         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15144         const struct intel_crtc_state *old_crtc_state =
15145                 intel_atomic_get_old_crtc_state(state, crtc);
15146         struct intel_crtc_state *new_crtc_state =
15147                 intel_atomic_get_new_crtc_state(state, crtc);
15148         bool modeset = needs_modeset(new_crtc_state);
15149
15150         if (!modeset) {
15151                 if (new_crtc_state->preload_luts &&
15152                     (new_crtc_state->uapi.color_mgmt_changed ||
15153                      new_crtc_state->update_pipe))
15154                         intel_color_load_luts(new_crtc_state);
15155
15156                 intel_pre_plane_update(state, crtc);
15157
15158                 if (new_crtc_state->update_pipe)
15159                         intel_encoders_update_pipe(state, crtc);
15160         }
15161
15162         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15163                 intel_fbc_disable(crtc);
15164         else
15165                 intel_fbc_enable(state, crtc);
15166
15167         /* Perform vblank evasion around commit operation */
15168         intel_pipe_update_start(new_crtc_state);
15169
15170         commit_pipe_config(state, crtc);
15171
15172         if (INTEL_GEN(dev_priv) >= 9)
15173                 skl_update_planes_on_crtc(state, crtc);
15174         else
15175                 i9xx_update_planes_on_crtc(state, crtc);
15176
15177         intel_pipe_update_end(new_crtc_state);
15178
15179         /*
15180          * We usually enable FIFO underrun interrupts as part of the
15181          * CRTC enable sequence during modesets.  But when we inherit a
15182          * valid pipe configuration from the BIOS we need to take care
15183          * of enabling them on the CRTC's first fastset.
15184          */
15185         if (new_crtc_state->update_pipe && !modeset &&
15186             old_crtc_state->inherited)
15187                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15188 }
15189
15190
15191 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15192                                           struct intel_crtc_state *old_crtc_state,
15193                                           struct intel_crtc_state *new_crtc_state,
15194                                           struct intel_crtc *crtc)
15195 {
15196         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15197
15198         intel_crtc_disable_planes(state, crtc);
15199
15200         /*
15201          * We need to disable pipe CRC before disabling the pipe,
15202          * or we race against vblank off.
15203          */
15204         intel_crtc_disable_pipe_crc(crtc);
15205
15206         dev_priv->display.crtc_disable(state, crtc);
15207         crtc->active = false;
15208         intel_fbc_disable(crtc);
15209         intel_disable_shared_dpll(old_crtc_state);
15210
15211         /* FIXME unify this for all platforms */
15212         if (!new_crtc_state->hw.active &&
15213             !HAS_GMCH(dev_priv) &&
15214             dev_priv->display.initial_watermarks)
15215                 dev_priv->display.initial_watermarks(state, crtc);
15216 }
15217
15218 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15219 {
15220         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15221         struct intel_crtc *crtc;
15222         u32 handled = 0;
15223         int i;
15224
15225         /* Only disable port sync and MST slaves */
15226         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15227                                             new_crtc_state, i) {
15228                 if (!needs_modeset(new_crtc_state))
15229                         continue;
15230
15231                 if (!old_crtc_state->hw.active)
15232                         continue;
15233
15234                 /* In case of Transcoder port Sync master slave CRTCs can be
15235                  * assigned in any order and we need to make sure that
15236                  * slave CRTCs are disabled first and then master CRTC since
15237                  * Slave vblanks are masked till Master Vblanks.
15238                  */
15239                 if (!is_trans_port_sync_slave(old_crtc_state) &&
15240                     !intel_dp_mst_is_slave_trans(old_crtc_state))
15241                         continue;
15242
15243                 intel_pre_plane_update(state, crtc);
15244                 intel_old_crtc_state_disables(state, old_crtc_state,
15245                                               new_crtc_state, crtc);
15246                 handled |= BIT(crtc->pipe);
15247         }
15248
15249         /* Disable everything else left on */
15250         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15251                                             new_crtc_state, i) {
15252                 if (!needs_modeset(new_crtc_state) ||
15253                     (handled & BIT(crtc->pipe)))
15254                         continue;
15255
15256                 intel_pre_plane_update(state, crtc);
15257                 if (old_crtc_state->hw.active)
15258                         intel_old_crtc_state_disables(state, old_crtc_state,
15259                                                       new_crtc_state, crtc);
15260         }
15261 }
15262
15263 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15264 {
15265         struct intel_crtc_state *new_crtc_state;
15266         struct intel_crtc *crtc;
15267         int i;
15268
15269         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15270                 if (!new_crtc_state->hw.active)
15271                         continue;
15272
15273                 intel_enable_crtc(state, crtc);
15274                 intel_update_crtc(state, crtc);
15275         }
15276 }
15277
15278 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15279 {
15280         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15281         struct intel_crtc *crtc;
15282         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15283         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15284         u8 update_pipes = 0, modeset_pipes = 0;
15285         int i;
15286
15287         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15288                 enum pipe pipe = crtc->pipe;
15289
15290                 if (!new_crtc_state->hw.active)
15291                         continue;
15292
15293                 /* ignore allocations for crtc's that have been turned off. */
15294                 if (!needs_modeset(new_crtc_state)) {
15295                         entries[pipe] = old_crtc_state->wm.skl.ddb;
15296                         update_pipes |= BIT(pipe);
15297                 } else {
15298                         modeset_pipes |= BIT(pipe);
15299                 }
15300         }
15301
15302         /*
15303          * Whenever the number of active pipes changes, we need to make sure we
15304          * update the pipes in the right order so that their ddb allocations
15305          * never overlap with each other between CRTC updates. Otherwise we'll
15306          * cause pipe underruns and other bad stuff.
15307          *
15308          * So first lets enable all pipes that do not need a fullmodeset as
15309          * those don't have any external dependency.
15310          */
15311         while (update_pipes) {
15312                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15313                                                     new_crtc_state, i) {
15314                         enum pipe pipe = crtc->pipe;
15315
15316                         if ((update_pipes & BIT(pipe)) == 0)
15317                                 continue;
15318
15319                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15320                                                         entries, I915_MAX_PIPES, pipe))
15321                                 continue;
15322
15323                         entries[pipe] = new_crtc_state->wm.skl.ddb;
15324                         update_pipes &= ~BIT(pipe);
15325
15326                         intel_update_crtc(state, crtc);
15327
15328                         /*
15329                          * If this is an already active pipe, it's DDB changed,
15330                          * and this isn't the last pipe that needs updating
15331                          * then we need to wait for a vblank to pass for the
15332                          * new ddb allocation to take effect.
15333                          */
15334                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15335                                                  &old_crtc_state->wm.skl.ddb) &&
15336                             (update_pipes | modeset_pipes))
15337                                 intel_wait_for_vblank(dev_priv, pipe);
15338                 }
15339         }
15340
15341         update_pipes = modeset_pipes;
15342
15343         /*
15344          * Enable all pipes that needs a modeset and do not depends on other
15345          * pipes
15346          */
15347         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15348                 enum pipe pipe = crtc->pipe;
15349
15350                 if ((modeset_pipes & BIT(pipe)) == 0)
15351                         continue;
15352
15353                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15354                     is_trans_port_sync_master(new_crtc_state))
15355                         continue;
15356
15357                 modeset_pipes &= ~BIT(pipe);
15358
15359                 intel_enable_crtc(state, crtc);
15360         }
15361
15362         /*
15363          * Then we enable all remaining pipes that depend on other
15364          * pipes: MST slaves and port sync masters.
15365          */
15366         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15367                 enum pipe pipe = crtc->pipe;
15368
15369                 if ((modeset_pipes & BIT(pipe)) == 0)
15370                         continue;
15371
15372                 modeset_pipes &= ~BIT(pipe);
15373
15374                 intel_enable_crtc(state, crtc);
15375         }
15376
15377         /*
15378          * Finally we do the plane updates/etc. for all pipes that got enabled.
15379          */
15380         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15381                 enum pipe pipe = crtc->pipe;
15382
15383                 if ((update_pipes & BIT(pipe)) == 0)
15384                         continue;
15385
15386                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15387                                                                         entries, I915_MAX_PIPES, pipe));
15388
15389                 entries[pipe] = new_crtc_state->wm.skl.ddb;
15390                 update_pipes &= ~BIT(pipe);
15391
15392                 intel_update_crtc(state, crtc);
15393         }
15394
15395         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15396         drm_WARN_ON(&dev_priv->drm, update_pipes);
15397 }
15398
15399 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15400 {
15401         struct intel_atomic_state *state, *next;
15402         struct llist_node *freed;
15403
15404         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15405         llist_for_each_entry_safe(state, next, freed, freed)
15406                 drm_atomic_state_put(&state->base);
15407 }
15408
15409 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15410 {
15411         struct drm_i915_private *dev_priv =
15412                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15413
15414         intel_atomic_helper_free_state(dev_priv);
15415 }
15416
15417 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15418 {
15419         struct wait_queue_entry wait_fence, wait_reset;
15420         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15421
15422         init_wait_entry(&wait_fence, 0);
15423         init_wait_entry(&wait_reset, 0);
15424         for (;;) {
15425                 prepare_to_wait(&intel_state->commit_ready.wait,
15426                                 &wait_fence, TASK_UNINTERRUPTIBLE);
15427                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15428                                               I915_RESET_MODESET),
15429                                 &wait_reset, TASK_UNINTERRUPTIBLE);
15430
15431
15432                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15433                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15434                         break;
15435
15436                 schedule();
15437         }
15438         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15439         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15440                                   I915_RESET_MODESET),
15441                     &wait_reset);
15442 }
15443
15444 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15445 {
15446         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15447         struct intel_crtc *crtc;
15448         int i;
15449
15450         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15451                                             new_crtc_state, i)
15452                 intel_dsb_cleanup(old_crtc_state);
15453 }
15454
15455 static void intel_atomic_cleanup_work(struct work_struct *work)
15456 {
15457         struct intel_atomic_state *state =
15458                 container_of(work, struct intel_atomic_state, base.commit_work);
15459         struct drm_i915_private *i915 = to_i915(state->base.dev);
15460
15461         intel_cleanup_dsbs(state);
15462         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15463         drm_atomic_helper_commit_cleanup_done(&state->base);
15464         drm_atomic_state_put(&state->base);
15465
15466         intel_atomic_helper_free_state(i915);
15467 }
15468
15469 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15470 {
15471         struct drm_device *dev = state->base.dev;
15472         struct drm_i915_private *dev_priv = to_i915(dev);
15473         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15474         struct intel_crtc *crtc;
15475         u64 put_domains[I915_MAX_PIPES] = {};
15476         intel_wakeref_t wakeref = 0;
15477         int i;
15478
15479         intel_atomic_commit_fence_wait(state);
15480
15481         drm_atomic_helper_wait_for_dependencies(&state->base);
15482
15483         if (state->modeset)
15484                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15485
15486         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15487                                             new_crtc_state, i) {
15488                 if (needs_modeset(new_crtc_state) ||
15489                     new_crtc_state->update_pipe) {
15490
15491                         put_domains[crtc->pipe] =
15492                                 modeset_get_crtc_power_domains(new_crtc_state);
15493                 }
15494         }
15495
15496         intel_commit_modeset_disables(state);
15497
15498         /* FIXME: Eventually get rid of our crtc->config pointer */
15499         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15500                 crtc->config = new_crtc_state;
15501
15502         if (state->modeset) {
15503                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15504
15505                 intel_set_cdclk_pre_plane_update(state);
15506
15507                 intel_modeset_verify_disabled(dev_priv, state);
15508         }
15509
15510         intel_sagv_pre_plane_update(state);
15511
15512         /* Complete the events for pipes that have now been disabled */
15513         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15514                 bool modeset = needs_modeset(new_crtc_state);
15515
15516                 /* Complete events for now disable pipes here. */
15517                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15518                         spin_lock_irq(&dev->event_lock);
15519                         drm_crtc_send_vblank_event(&crtc->base,
15520                                                    new_crtc_state->uapi.event);
15521                         spin_unlock_irq(&dev->event_lock);
15522
15523                         new_crtc_state->uapi.event = NULL;
15524                 }
15525         }
15526
15527         if (state->modeset)
15528                 intel_encoders_update_prepare(state);
15529
15530         intel_dbuf_pre_plane_update(state);
15531
15532         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15533         dev_priv->display.commit_modeset_enables(state);
15534
15535         if (state->modeset) {
15536                 intel_encoders_update_complete(state);
15537
15538                 intel_set_cdclk_post_plane_update(state);
15539         }
15540
15541         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15542          * already, but still need the state for the delayed optimization. To
15543          * fix this:
15544          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15545          * - schedule that vblank worker _before_ calling hw_done
15546          * - at the start of commit_tail, cancel it _synchrously
15547          * - switch over to the vblank wait helper in the core after that since
15548          *   we don't need out special handling any more.
15549          */
15550         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15551
15552         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15553                 if (new_crtc_state->hw.active &&
15554                     !needs_modeset(new_crtc_state) &&
15555                     !new_crtc_state->preload_luts &&
15556                     (new_crtc_state->uapi.color_mgmt_changed ||
15557                      new_crtc_state->update_pipe))
15558                         intel_color_load_luts(new_crtc_state);
15559         }
15560
15561         /*
15562          * Now that the vblank has passed, we can go ahead and program the
15563          * optimal watermarks on platforms that need two-step watermark
15564          * programming.
15565          *
15566          * TODO: Move this (and other cleanup) to an async worker eventually.
15567          */
15568         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15569                                             new_crtc_state, i) {
15570                 /*
15571                  * Gen2 reports pipe underruns whenever all planes are disabled.
15572                  * So re-enable underrun reporting after some planes get enabled.
15573                  *
15574                  * We do this before .optimize_watermarks() so that we have a
15575                  * chance of catching underruns with the intermediate watermarks
15576                  * vs. the new plane configuration.
15577                  */
15578                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15579                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15580
15581                 if (dev_priv->display.optimize_watermarks)
15582                         dev_priv->display.optimize_watermarks(state, crtc);
15583         }
15584
15585         intel_dbuf_post_plane_update(state);
15586
15587         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15588                 intel_post_plane_update(state, crtc);
15589
15590                 if (put_domains[i])
15591                         modeset_put_power_domains(dev_priv, put_domains[i]);
15592
15593                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15594
15595                 /*
15596                  * DSB cleanup is done in cleanup_work aligning with framebuffer
15597                  * cleanup. So copy and reset the dsb structure to sync with
15598                  * commit_done and later do dsb cleanup in cleanup_work.
15599                  */
15600                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15601         }
15602
15603         /* Underruns don't always raise interrupts, so check manually */
15604         intel_check_cpu_fifo_underruns(dev_priv);
15605         intel_check_pch_fifo_underruns(dev_priv);
15606
15607         if (state->modeset)
15608                 intel_verify_planes(state);
15609
15610         intel_sagv_post_plane_update(state);
15611
15612         drm_atomic_helper_commit_hw_done(&state->base);
15613
15614         if (state->modeset) {
15615                 /* As one of the primary mmio accessors, KMS has a high
15616                  * likelihood of triggering bugs in unclaimed access. After we
15617                  * finish modesetting, see if an error has been flagged, and if
15618                  * so enable debugging for the next modeset - and hope we catch
15619                  * the culprit.
15620                  */
15621                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15622                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15623         }
15624         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15625
15626         /*
15627          * Defer the cleanup of the old state to a separate worker to not
15628          * impede the current task (userspace for blocking modesets) that
15629          * are executed inline. For out-of-line asynchronous modesets/flips,
15630          * deferring to a new worker seems overkill, but we would place a
15631          * schedule point (cond_resched()) here anyway to keep latencies
15632          * down.
15633          */
15634         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15635         queue_work(system_highpri_wq, &state->base.commit_work);
15636 }
15637
15638 static void intel_atomic_commit_work(struct work_struct *work)
15639 {
15640         struct intel_atomic_state *state =
15641                 container_of(work, struct intel_atomic_state, base.commit_work);
15642
15643         intel_atomic_commit_tail(state);
15644 }
15645
15646 static int __i915_sw_fence_call
15647 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15648                           enum i915_sw_fence_notify notify)
15649 {
15650         struct intel_atomic_state *state =
15651                 container_of(fence, struct intel_atomic_state, commit_ready);
15652
15653         switch (notify) {
15654         case FENCE_COMPLETE:
15655                 /* we do blocking waits in the worker, nothing to do here */
15656                 break;
15657         case FENCE_FREE:
15658                 {
15659                         struct intel_atomic_helper *helper =
15660                                 &to_i915(state->base.dev)->atomic_helper;
15661
15662                         if (llist_add(&state->freed, &helper->free_list))
15663                                 schedule_work(&helper->free_work);
15664                         break;
15665                 }
15666         }
15667
15668         return NOTIFY_DONE;
15669 }
15670
15671 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15672 {
15673         struct intel_plane_state *old_plane_state, *new_plane_state;
15674         struct intel_plane *plane;
15675         int i;
15676
15677         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15678                                              new_plane_state, i)
15679                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15680                                         to_intel_frontbuffer(new_plane_state->hw.fb),
15681                                         plane->frontbuffer_bit);
15682 }
15683
15684 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
15685 {
15686         struct intel_crtc *crtc;
15687
15688         for_each_intel_crtc(&dev_priv->drm, crtc)
15689                 drm_modeset_lock_assert_held(&crtc->base.mutex);
15690 }
15691
15692 static int intel_atomic_commit(struct drm_device *dev,
15693                                struct drm_atomic_state *_state,
15694                                bool nonblock)
15695 {
15696         struct intel_atomic_state *state = to_intel_atomic_state(_state);
15697         struct drm_i915_private *dev_priv = to_i915(dev);
15698         int ret = 0;
15699
15700         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15701
15702         drm_atomic_state_get(&state->base);
15703         i915_sw_fence_init(&state->commit_ready,
15704                            intel_atomic_commit_ready);
15705
15706         /*
15707          * The intel_legacy_cursor_update() fast path takes care
15708          * of avoiding the vblank waits for simple cursor
15709          * movement and flips. For cursor on/off and size changes,
15710          * we want to perform the vblank waits so that watermark
15711          * updates happen during the correct frames. Gen9+ have
15712          * double buffered watermarks and so shouldn't need this.
15713          *
15714          * Unset state->legacy_cursor_update before the call to
15715          * drm_atomic_helper_setup_commit() because otherwise
15716          * drm_atomic_helper_wait_for_flip_done() is a noop and
15717          * we get FIFO underruns because we didn't wait
15718          * for vblank.
15719          *
15720          * FIXME doing watermarks and fb cleanup from a vblank worker
15721          * (assuming we had any) would solve these problems.
15722          */
15723         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15724                 struct intel_crtc_state *new_crtc_state;
15725                 struct intel_crtc *crtc;
15726                 int i;
15727
15728                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15729                         if (new_crtc_state->wm.need_postvbl_update ||
15730                             new_crtc_state->update_wm_post)
15731                                 state->base.legacy_cursor_update = false;
15732         }
15733
15734         ret = intel_atomic_prepare_commit(state);
15735         if (ret) {
15736                 drm_dbg_atomic(&dev_priv->drm,
15737                                "Preparing state failed with %i\n", ret);
15738                 i915_sw_fence_commit(&state->commit_ready);
15739                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15740                 return ret;
15741         }
15742
15743         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15744         if (!ret)
15745                 ret = drm_atomic_helper_swap_state(&state->base, true);
15746         if (!ret)
15747                 intel_atomic_swap_global_state(state);
15748
15749         if (ret) {
15750                 struct intel_crtc_state *new_crtc_state;
15751                 struct intel_crtc *crtc;
15752                 int i;
15753
15754                 i915_sw_fence_commit(&state->commit_ready);
15755
15756                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15757                         intel_dsb_cleanup(new_crtc_state);
15758
15759                 drm_atomic_helper_cleanup_planes(dev, &state->base);
15760                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15761                 return ret;
15762         }
15763         dev_priv->wm.distrust_bios_wm = false;
15764         intel_shared_dpll_swap_state(state);
15765         intel_atomic_track_fbs(state);
15766
15767         if (state->global_state_changed) {
15768                 assert_global_state_locked(dev_priv);
15769
15770                 dev_priv->active_pipes = state->active_pipes;
15771         }
15772
15773         drm_atomic_state_get(&state->base);
15774         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15775
15776         i915_sw_fence_commit(&state->commit_ready);
15777         if (nonblock && state->modeset) {
15778                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15779         } else if (nonblock) {
15780                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15781         } else {
15782                 if (state->modeset)
15783                         flush_workqueue(dev_priv->modeset_wq);
15784                 intel_atomic_commit_tail(state);
15785         }
15786
15787         return 0;
15788 }
15789
15790 struct wait_rps_boost {
15791         struct wait_queue_entry wait;
15792
15793         struct drm_crtc *crtc;
15794         struct i915_request *request;
15795 };
15796
15797 static int do_rps_boost(struct wait_queue_entry *_wait,
15798                         unsigned mode, int sync, void *key)
15799 {
15800         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15801         struct i915_request *rq = wait->request;
15802
15803         /*
15804          * If we missed the vblank, but the request is already running it
15805          * is reasonable to assume that it will complete before the next
15806          * vblank without our intervention, so leave RPS alone.
15807          */
15808         if (!i915_request_started(rq))
15809                 intel_rps_boost(rq);
15810         i915_request_put(rq);
15811
15812         drm_crtc_vblank_put(wait->crtc);
15813
15814         list_del(&wait->wait.entry);
15815         kfree(wait);
15816         return 1;
15817 }
15818
15819 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15820                                        struct dma_fence *fence)
15821 {
15822         struct wait_rps_boost *wait;
15823
15824         if (!dma_fence_is_i915(fence))
15825                 return;
15826
15827         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15828                 return;
15829
15830         if (drm_crtc_vblank_get(crtc))
15831                 return;
15832
15833         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15834         if (!wait) {
15835                 drm_crtc_vblank_put(crtc);
15836                 return;
15837         }
15838
15839         wait->request = to_request(dma_fence_get(fence));
15840         wait->crtc = crtc;
15841
15842         wait->wait.func = do_rps_boost;
15843         wait->wait.flags = 0;
15844
15845         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15846 }
15847
15848 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15849 {
15850         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15851         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15852         struct drm_framebuffer *fb = plane_state->hw.fb;
15853         struct i915_vma *vma;
15854
15855         if (plane->id == PLANE_CURSOR &&
15856             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15857                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15858                 const int align = intel_cursor_alignment(dev_priv);
15859                 int err;
15860
15861                 err = i915_gem_object_attach_phys(obj, align);
15862                 if (err)
15863                         return err;
15864         }
15865
15866         vma = intel_pin_and_fence_fb_obj(fb,
15867                                          &plane_state->view,
15868                                          intel_plane_uses_fence(plane_state),
15869                                          &plane_state->flags);
15870         if (IS_ERR(vma))
15871                 return PTR_ERR(vma);
15872
15873         plane_state->vma = vma;
15874
15875         return 0;
15876 }
15877
15878 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15879 {
15880         struct i915_vma *vma;
15881
15882         vma = fetch_and_zero(&old_plane_state->vma);
15883         if (vma)
15884                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15885 }
15886
15887 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15888 {
15889         struct i915_sched_attr attr = {
15890                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15891         };
15892
15893         i915_gem_object_wait_priority(obj, 0, &attr);
15894 }
15895
15896 /**
15897  * intel_prepare_plane_fb - Prepare fb for usage on plane
15898  * @_plane: drm plane to prepare for
15899  * @_new_plane_state: the plane state being prepared
15900  *
15901  * Prepares a framebuffer for usage on a display plane.  Generally this
15902  * involves pinning the underlying object and updating the frontbuffer tracking
15903  * bits.  Some older platforms need special physical address handling for
15904  * cursor planes.
15905  *
15906  * Returns 0 on success, negative error code on failure.
15907  */
15908 int
15909 intel_prepare_plane_fb(struct drm_plane *_plane,
15910                        struct drm_plane_state *_new_plane_state)
15911 {
15912         struct intel_plane *plane = to_intel_plane(_plane);
15913         struct intel_plane_state *new_plane_state =
15914                 to_intel_plane_state(_new_plane_state);
15915         struct intel_atomic_state *state =
15916                 to_intel_atomic_state(new_plane_state->uapi.state);
15917         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15918         const struct intel_plane_state *old_plane_state =
15919                 intel_atomic_get_old_plane_state(state, plane);
15920         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
15921         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
15922         int ret;
15923
15924         if (old_obj) {
15925                 const struct intel_crtc_state *crtc_state =
15926                         intel_atomic_get_new_crtc_state(state,
15927                                                         to_intel_crtc(old_plane_state->hw.crtc));
15928
15929                 /* Big Hammer, we also need to ensure that any pending
15930                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15931                  * current scanout is retired before unpinning the old
15932                  * framebuffer. Note that we rely on userspace rendering
15933                  * into the buffer attached to the pipe they are waiting
15934                  * on. If not, userspace generates a GPU hang with IPEHR
15935                  * point to the MI_WAIT_FOR_EVENT.
15936                  *
15937                  * This should only fail upon a hung GPU, in which case we
15938                  * can safely continue.
15939                  */
15940                 if (needs_modeset(crtc_state)) {
15941                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
15942                                                               old_obj->base.resv, NULL,
15943                                                               false, 0,
15944                                                               GFP_KERNEL);
15945                         if (ret < 0)
15946                                 return ret;
15947                 }
15948         }
15949
15950         if (new_plane_state->uapi.fence) { /* explicit fencing */
15951                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
15952                                                     new_plane_state->uapi.fence,
15953                                                     i915_fence_timeout(dev_priv),
15954                                                     GFP_KERNEL);
15955                 if (ret < 0)
15956                         return ret;
15957         }
15958
15959         if (!obj)
15960                 return 0;
15961
15962         ret = i915_gem_object_pin_pages(obj);
15963         if (ret)
15964                 return ret;
15965
15966         ret = intel_plane_pin_fb(new_plane_state);
15967
15968         i915_gem_object_unpin_pages(obj);
15969         if (ret)
15970                 return ret;
15971
15972         fb_obj_bump_render_priority(obj);
15973         i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
15974
15975         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15976                 struct dma_fence *fence;
15977
15978                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
15979                                                       obj->base.resv, NULL,
15980                                                       false,
15981                                                       i915_fence_timeout(dev_priv),
15982                                                       GFP_KERNEL);
15983                 if (ret < 0)
15984                         goto unpin_fb;
15985
15986                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15987                 if (fence) {
15988                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15989                                                    fence);
15990                         dma_fence_put(fence);
15991                 }
15992         } else {
15993                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15994                                            new_plane_state->uapi.fence);
15995         }
15996
15997         /*
15998          * We declare pageflips to be interactive and so merit a small bias
15999          * towards upclocking to deliver the frame on time. By only changing
16000          * the RPS thresholds to sample more regularly and aim for higher
16001          * clocks we can hopefully deliver low power workloads (like kodi)
16002          * that are not quite steady state without resorting to forcing
16003          * maximum clocks following a vblank miss (see do_rps_boost()).
16004          */
16005         if (!state->rps_interactive) {
16006                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16007                 state->rps_interactive = true;
16008         }
16009
16010         return 0;
16011
16012 unpin_fb:
16013         intel_plane_unpin_fb(new_plane_state);
16014
16015         return ret;
16016 }
16017
16018 /**
16019  * intel_cleanup_plane_fb - Cleans up an fb after plane use
16020  * @plane: drm plane to clean up for
16021  * @_old_plane_state: the state from the previous modeset
16022  *
16023  * Cleans up a framebuffer that has just been removed from a plane.
16024  */
16025 void
16026 intel_cleanup_plane_fb(struct drm_plane *plane,
16027                        struct drm_plane_state *_old_plane_state)
16028 {
16029         struct intel_plane_state *old_plane_state =
16030                 to_intel_plane_state(_old_plane_state);
16031         struct intel_atomic_state *state =
16032                 to_intel_atomic_state(old_plane_state->uapi.state);
16033         struct drm_i915_private *dev_priv = to_i915(plane->dev);
16034         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16035
16036         if (!obj)
16037                 return;
16038
16039         if (state->rps_interactive) {
16040                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16041                 state->rps_interactive = false;
16042         }
16043
16044         /* Should only be called after a successful intel_prepare_plane_fb()! */
16045         intel_plane_unpin_fb(old_plane_state);
16046 }
16047
16048 /**
16049  * intel_plane_destroy - destroy a plane
16050  * @plane: plane to destroy
16051  *
16052  * Common destruction function for all types of planes (primary, cursor,
16053  * sprite).
16054  */
16055 void intel_plane_destroy(struct drm_plane *plane)
16056 {
16057         drm_plane_cleanup(plane);
16058         kfree(to_intel_plane(plane));
16059 }
16060
16061 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16062                                             u32 format, u64 modifier)
16063 {
16064         switch (modifier) {
16065         case DRM_FORMAT_MOD_LINEAR:
16066         case I915_FORMAT_MOD_X_TILED:
16067                 break;
16068         default:
16069                 return false;
16070         }
16071
16072         switch (format) {
16073         case DRM_FORMAT_C8:
16074         case DRM_FORMAT_RGB565:
16075         case DRM_FORMAT_XRGB1555:
16076         case DRM_FORMAT_XRGB8888:
16077                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16078                         modifier == I915_FORMAT_MOD_X_TILED;
16079         default:
16080                 return false;
16081         }
16082 }
16083
16084 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16085                                             u32 format, u64 modifier)
16086 {
16087         switch (modifier) {
16088         case DRM_FORMAT_MOD_LINEAR:
16089         case I915_FORMAT_MOD_X_TILED:
16090                 break;
16091         default:
16092                 return false;
16093         }
16094
16095         switch (format) {
16096         case DRM_FORMAT_C8:
16097         case DRM_FORMAT_RGB565:
16098         case DRM_FORMAT_XRGB8888:
16099         case DRM_FORMAT_XBGR8888:
16100         case DRM_FORMAT_ARGB8888:
16101         case DRM_FORMAT_ABGR8888:
16102         case DRM_FORMAT_XRGB2101010:
16103         case DRM_FORMAT_XBGR2101010:
16104         case DRM_FORMAT_ARGB2101010:
16105         case DRM_FORMAT_ABGR2101010:
16106         case DRM_FORMAT_XBGR16161616F:
16107                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16108                         modifier == I915_FORMAT_MOD_X_TILED;
16109         default:
16110                 return false;
16111         }
16112 }
16113
16114 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16115                                               u32 format, u64 modifier)
16116 {
16117         return modifier == DRM_FORMAT_MOD_LINEAR &&
16118                 format == DRM_FORMAT_ARGB8888;
16119 }
16120
16121 static const struct drm_plane_funcs i965_plane_funcs = {
16122         .update_plane = drm_atomic_helper_update_plane,
16123         .disable_plane = drm_atomic_helper_disable_plane,
16124         .destroy = intel_plane_destroy,
16125         .atomic_duplicate_state = intel_plane_duplicate_state,
16126         .atomic_destroy_state = intel_plane_destroy_state,
16127         .format_mod_supported = i965_plane_format_mod_supported,
16128 };
16129
16130 static const struct drm_plane_funcs i8xx_plane_funcs = {
16131         .update_plane = drm_atomic_helper_update_plane,
16132         .disable_plane = drm_atomic_helper_disable_plane,
16133         .destroy = intel_plane_destroy,
16134         .atomic_duplicate_state = intel_plane_duplicate_state,
16135         .atomic_destroy_state = intel_plane_destroy_state,
16136         .format_mod_supported = i8xx_plane_format_mod_supported,
16137 };
16138
16139 static int
16140 intel_legacy_cursor_update(struct drm_plane *_plane,
16141                            struct drm_crtc *_crtc,
16142                            struct drm_framebuffer *fb,
16143                            int crtc_x, int crtc_y,
16144                            unsigned int crtc_w, unsigned int crtc_h,
16145                            u32 src_x, u32 src_y,
16146                            u32 src_w, u32 src_h,
16147                            struct drm_modeset_acquire_ctx *ctx)
16148 {
16149         struct intel_plane *plane = to_intel_plane(_plane);
16150         struct intel_crtc *crtc = to_intel_crtc(_crtc);
16151         struct intel_plane_state *old_plane_state =
16152                 to_intel_plane_state(plane->base.state);
16153         struct intel_plane_state *new_plane_state;
16154         struct intel_crtc_state *crtc_state =
16155                 to_intel_crtc_state(crtc->base.state);
16156         struct intel_crtc_state *new_crtc_state;
16157         int ret;
16158
16159         /*
16160          * When crtc is inactive or there is a modeset pending,
16161          * wait for it to complete in the slowpath
16162          */
16163         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16164             crtc_state->update_pipe)
16165                 goto slow;
16166
16167         /*
16168          * Don't do an async update if there is an outstanding commit modifying
16169          * the plane.  This prevents our async update's changes from getting
16170          * overridden by a previous synchronous update's state.
16171          */
16172         if (old_plane_state->uapi.commit &&
16173             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16174                 goto slow;
16175
16176         /*
16177          * If any parameters change that may affect watermarks,
16178          * take the slowpath. Only changing fb or position should be
16179          * in the fastpath.
16180          */
16181         if (old_plane_state->uapi.crtc != &crtc->base ||
16182             old_plane_state->uapi.src_w != src_w ||
16183             old_plane_state->uapi.src_h != src_h ||
16184             old_plane_state->uapi.crtc_w != crtc_w ||
16185             old_plane_state->uapi.crtc_h != crtc_h ||
16186             !old_plane_state->uapi.fb != !fb)
16187                 goto slow;
16188
16189         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16190         if (!new_plane_state)
16191                 return -ENOMEM;
16192
16193         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16194         if (!new_crtc_state) {
16195                 ret = -ENOMEM;
16196                 goto out_free;
16197         }
16198
16199         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16200
16201         new_plane_state->uapi.src_x = src_x;
16202         new_plane_state->uapi.src_y = src_y;
16203         new_plane_state->uapi.src_w = src_w;
16204         new_plane_state->uapi.src_h = src_h;
16205         new_plane_state->uapi.crtc_x = crtc_x;
16206         new_plane_state->uapi.crtc_y = crtc_y;
16207         new_plane_state->uapi.crtc_w = crtc_w;
16208         new_plane_state->uapi.crtc_h = crtc_h;
16209
16210         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16211
16212         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16213                                                   old_plane_state, new_plane_state);
16214         if (ret)
16215                 goto out_free;
16216
16217         ret = intel_plane_pin_fb(new_plane_state);
16218         if (ret)
16219                 goto out_free;
16220
16221         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16222                                 ORIGIN_FLIP);
16223         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16224                                 to_intel_frontbuffer(new_plane_state->hw.fb),
16225                                 plane->frontbuffer_bit);
16226
16227         /* Swap plane state */
16228         plane->base.state = &new_plane_state->uapi;
16229
16230         /*
16231          * We cannot swap crtc_state as it may be in use by an atomic commit or
16232          * page flip that's running simultaneously. If we swap crtc_state and
16233          * destroy the old state, we will cause a use-after-free there.
16234          *
16235          * Only update active_planes, which is needed for our internal
16236          * bookkeeping. Either value will do the right thing when updating
16237          * planes atomically. If the cursor was part of the atomic update then
16238          * we would have taken the slowpath.
16239          */
16240         crtc_state->active_planes = new_crtc_state->active_planes;
16241
16242         if (new_plane_state->uapi.visible)
16243                 intel_update_plane(plane, crtc_state, new_plane_state);
16244         else
16245                 intel_disable_plane(plane, crtc_state);
16246
16247         intel_plane_unpin_fb(old_plane_state);
16248
16249 out_free:
16250         if (new_crtc_state)
16251                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16252         if (ret)
16253                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16254         else
16255                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16256         return ret;
16257
16258 slow:
16259         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16260                                               crtc_x, crtc_y, crtc_w, crtc_h,
16261                                               src_x, src_y, src_w, src_h, ctx);
16262 }
16263
16264 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16265         .update_plane = intel_legacy_cursor_update,
16266         .disable_plane = drm_atomic_helper_disable_plane,
16267         .destroy = intel_plane_destroy,
16268         .atomic_duplicate_state = intel_plane_duplicate_state,
16269         .atomic_destroy_state = intel_plane_destroy_state,
16270         .format_mod_supported = intel_cursor_format_mod_supported,
16271 };
16272
16273 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16274                                enum i9xx_plane_id i9xx_plane)
16275 {
16276         if (!HAS_FBC(dev_priv))
16277                 return false;
16278
16279         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16280                 return i9xx_plane == PLANE_A; /* tied to pipe A */
16281         else if (IS_IVYBRIDGE(dev_priv))
16282                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16283                         i9xx_plane == PLANE_C;
16284         else if (INTEL_GEN(dev_priv) >= 4)
16285                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16286         else
16287                 return i9xx_plane == PLANE_A;
16288 }
16289
16290 static struct intel_plane *
16291 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16292 {
16293         struct intel_plane *plane;
16294         const struct drm_plane_funcs *plane_funcs;
16295         unsigned int supported_rotations;
16296         const u32 *formats;
16297         int num_formats;
16298         int ret, zpos;
16299
16300         if (INTEL_GEN(dev_priv) >= 9)
16301                 return skl_universal_plane_create(dev_priv, pipe,
16302                                                   PLANE_PRIMARY);
16303
16304         plane = intel_plane_alloc();
16305         if (IS_ERR(plane))
16306                 return plane;
16307
16308         plane->pipe = pipe;
16309         /*
16310          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16311          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16312          */
16313         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
16314                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16315         else
16316                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16317         plane->id = PLANE_PRIMARY;
16318         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16319
16320         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16321         if (plane->has_fbc) {
16322                 struct intel_fbc *fbc = &dev_priv->fbc;
16323
16324                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16325         }
16326
16327         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16328                 formats = vlv_primary_formats;
16329                 num_formats = ARRAY_SIZE(vlv_primary_formats);
16330         } else if (INTEL_GEN(dev_priv) >= 4) {
16331                 /*
16332                  * WaFP16GammaEnabling:ivb
16333                  * "Workaround : When using the 64-bit format, the plane
16334                  *  output on each color channel has one quarter amplitude.
16335                  *  It can be brought up to full amplitude by using pipe
16336                  *  gamma correction or pipe color space conversion to
16337                  *  multiply the plane output by four."
16338                  *
16339                  * There is no dedicated plane gamma for the primary plane,
16340                  * and using the pipe gamma/csc could conflict with other
16341                  * planes, so we choose not to expose fp16 on IVB primary
16342                  * planes. HSW primary planes no longer have this problem.
16343                  */
16344                 if (IS_IVYBRIDGE(dev_priv)) {
16345                         formats = ivb_primary_formats;
16346                         num_formats = ARRAY_SIZE(ivb_primary_formats);
16347                 } else {
16348                         formats = i965_primary_formats;
16349                         num_formats = ARRAY_SIZE(i965_primary_formats);
16350                 }
16351         } else {
16352                 formats = i8xx_primary_formats;
16353                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16354         }
16355
16356         if (INTEL_GEN(dev_priv) >= 4)
16357                 plane_funcs = &i965_plane_funcs;
16358         else
16359                 plane_funcs = &i8xx_plane_funcs;
16360
16361         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16362                 plane->min_cdclk = vlv_plane_min_cdclk;
16363         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16364                 plane->min_cdclk = hsw_plane_min_cdclk;
16365         else if (IS_IVYBRIDGE(dev_priv))
16366                 plane->min_cdclk = ivb_plane_min_cdclk;
16367         else
16368                 plane->min_cdclk = i9xx_plane_min_cdclk;
16369
16370         plane->max_stride = i9xx_plane_max_stride;
16371         plane->update_plane = i9xx_update_plane;
16372         plane->disable_plane = i9xx_disable_plane;
16373         plane->get_hw_state = i9xx_plane_get_hw_state;
16374         plane->check_plane = i9xx_plane_check;
16375
16376         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16377                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16378                                                0, plane_funcs,
16379                                                formats, num_formats,
16380                                                i9xx_format_modifiers,
16381                                                DRM_PLANE_TYPE_PRIMARY,
16382                                                "primary %c", pipe_name(pipe));
16383         else
16384                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16385                                                0, plane_funcs,
16386                                                formats, num_formats,
16387                                                i9xx_format_modifiers,
16388                                                DRM_PLANE_TYPE_PRIMARY,
16389                                                "plane %c",
16390                                                plane_name(plane->i9xx_plane));
16391         if (ret)
16392                 goto fail;
16393
16394         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16395                 supported_rotations =
16396                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16397                         DRM_MODE_REFLECT_X;
16398         } else if (INTEL_GEN(dev_priv) >= 4) {
16399                 supported_rotations =
16400                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16401         } else {
16402                 supported_rotations = DRM_MODE_ROTATE_0;
16403         }
16404
16405         if (INTEL_GEN(dev_priv) >= 4)
16406                 drm_plane_create_rotation_property(&plane->base,
16407                                                    DRM_MODE_ROTATE_0,
16408                                                    supported_rotations);
16409
16410         zpos = 0;
16411         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16412
16413         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16414
16415         return plane;
16416
16417 fail:
16418         intel_plane_free(plane);
16419
16420         return ERR_PTR(ret);
16421 }
16422
16423 static struct intel_plane *
16424 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16425                           enum pipe pipe)
16426 {
16427         struct intel_plane *cursor;
16428         int ret, zpos;
16429
16430         cursor = intel_plane_alloc();
16431         if (IS_ERR(cursor))
16432                 return cursor;
16433
16434         cursor->pipe = pipe;
16435         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16436         cursor->id = PLANE_CURSOR;
16437         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16438
16439         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16440                 cursor->max_stride = i845_cursor_max_stride;
16441                 cursor->update_plane = i845_update_cursor;
16442                 cursor->disable_plane = i845_disable_cursor;
16443                 cursor->get_hw_state = i845_cursor_get_hw_state;
16444                 cursor->check_plane = i845_check_cursor;
16445         } else {
16446                 cursor->max_stride = i9xx_cursor_max_stride;
16447                 cursor->update_plane = i9xx_update_cursor;
16448                 cursor->disable_plane = i9xx_disable_cursor;
16449                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16450                 cursor->check_plane = i9xx_check_cursor;
16451         }
16452
16453         cursor->cursor.base = ~0;
16454         cursor->cursor.cntl = ~0;
16455
16456         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16457                 cursor->cursor.size = ~0;
16458
16459         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16460                                        0, &intel_cursor_plane_funcs,
16461                                        intel_cursor_formats,
16462                                        ARRAY_SIZE(intel_cursor_formats),
16463                                        cursor_format_modifiers,
16464                                        DRM_PLANE_TYPE_CURSOR,
16465                                        "cursor %c", pipe_name(pipe));
16466         if (ret)
16467                 goto fail;
16468
16469         if (INTEL_GEN(dev_priv) >= 4)
16470                 drm_plane_create_rotation_property(&cursor->base,
16471                                                    DRM_MODE_ROTATE_0,
16472                                                    DRM_MODE_ROTATE_0 |
16473                                                    DRM_MODE_ROTATE_180);
16474
16475         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16476         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16477
16478         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16479
16480         return cursor;
16481
16482 fail:
16483         intel_plane_free(cursor);
16484
16485         return ERR_PTR(ret);
16486 }
16487
16488 #define INTEL_CRTC_FUNCS \
16489         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16490         .set_config = drm_atomic_helper_set_config, \
16491         .destroy = intel_crtc_destroy, \
16492         .page_flip = drm_atomic_helper_page_flip, \
16493         .atomic_duplicate_state = intel_crtc_duplicate_state, \
16494         .atomic_destroy_state = intel_crtc_destroy_state, \
16495         .set_crc_source = intel_crtc_set_crc_source, \
16496         .verify_crc_source = intel_crtc_verify_crc_source, \
16497         .get_crc_sources = intel_crtc_get_crc_sources
16498
16499 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16500         INTEL_CRTC_FUNCS,
16501
16502         .get_vblank_counter = g4x_get_vblank_counter,
16503         .enable_vblank = bdw_enable_vblank,
16504         .disable_vblank = bdw_disable_vblank,
16505         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16506 };
16507
16508 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16509         INTEL_CRTC_FUNCS,
16510
16511         .get_vblank_counter = g4x_get_vblank_counter,
16512         .enable_vblank = ilk_enable_vblank,
16513         .disable_vblank = ilk_disable_vblank,
16514         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16515 };
16516
16517 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16518         INTEL_CRTC_FUNCS,
16519
16520         .get_vblank_counter = g4x_get_vblank_counter,
16521         .enable_vblank = i965_enable_vblank,
16522         .disable_vblank = i965_disable_vblank,
16523         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16524 };
16525
16526 static const struct drm_crtc_funcs i965_crtc_funcs = {
16527         INTEL_CRTC_FUNCS,
16528
16529         .get_vblank_counter = i915_get_vblank_counter,
16530         .enable_vblank = i965_enable_vblank,
16531         .disable_vblank = i965_disable_vblank,
16532         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16533 };
16534
16535 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16536         INTEL_CRTC_FUNCS,
16537
16538         .get_vblank_counter = i915_get_vblank_counter,
16539         .enable_vblank = i915gm_enable_vblank,
16540         .disable_vblank = i915gm_disable_vblank,
16541         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16542 };
16543
16544 static const struct drm_crtc_funcs i915_crtc_funcs = {
16545         INTEL_CRTC_FUNCS,
16546
16547         .get_vblank_counter = i915_get_vblank_counter,
16548         .enable_vblank = i8xx_enable_vblank,
16549         .disable_vblank = i8xx_disable_vblank,
16550         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16551 };
16552
16553 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16554         INTEL_CRTC_FUNCS,
16555
16556         /* no hw vblank counter */
16557         .enable_vblank = i8xx_enable_vblank,
16558         .disable_vblank = i8xx_disable_vblank,
16559         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16560 };
16561
16562 static struct intel_crtc *intel_crtc_alloc(void)
16563 {
16564         struct intel_crtc_state *crtc_state;
16565         struct intel_crtc *crtc;
16566
16567         crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16568         if (!crtc)
16569                 return ERR_PTR(-ENOMEM);
16570
16571         crtc_state = intel_crtc_state_alloc(crtc);
16572         if (!crtc_state) {
16573                 kfree(crtc);
16574                 return ERR_PTR(-ENOMEM);
16575         }
16576
16577         crtc->base.state = &crtc_state->uapi;
16578         crtc->config = crtc_state;
16579
16580         return crtc;
16581 }
16582
16583 static void intel_crtc_free(struct intel_crtc *crtc)
16584 {
16585         intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16586         kfree(crtc);
16587 }
16588
16589 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16590 {
16591         struct intel_plane *plane;
16592
16593         for_each_intel_plane(&dev_priv->drm, plane) {
16594                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16595                                                                   plane->pipe);
16596
16597                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16598         }
16599 }
16600
16601 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16602 {
16603         struct intel_plane *primary, *cursor;
16604         const struct drm_crtc_funcs *funcs;
16605         struct intel_crtc *crtc;
16606         int sprite, ret;
16607
16608         crtc = intel_crtc_alloc();
16609         if (IS_ERR(crtc))
16610                 return PTR_ERR(crtc);
16611
16612         crtc->pipe = pipe;
16613         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16614
16615         primary = intel_primary_plane_create(dev_priv, pipe);
16616         if (IS_ERR(primary)) {
16617                 ret = PTR_ERR(primary);
16618                 goto fail;
16619         }
16620         crtc->plane_ids_mask |= BIT(primary->id);
16621
16622         for_each_sprite(dev_priv, pipe, sprite) {
16623                 struct intel_plane *plane;
16624
16625                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16626                 if (IS_ERR(plane)) {
16627                         ret = PTR_ERR(plane);
16628                         goto fail;
16629                 }
16630                 crtc->plane_ids_mask |= BIT(plane->id);
16631         }
16632
16633         cursor = intel_cursor_plane_create(dev_priv, pipe);
16634         if (IS_ERR(cursor)) {
16635                 ret = PTR_ERR(cursor);
16636                 goto fail;
16637         }
16638         crtc->plane_ids_mask |= BIT(cursor->id);
16639
16640         if (HAS_GMCH(dev_priv)) {
16641                 if (IS_CHERRYVIEW(dev_priv) ||
16642                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16643                         funcs = &g4x_crtc_funcs;
16644                 else if (IS_GEN(dev_priv, 4))
16645                         funcs = &i965_crtc_funcs;
16646                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16647                         funcs = &i915gm_crtc_funcs;
16648                 else if (IS_GEN(dev_priv, 3))
16649                         funcs = &i915_crtc_funcs;
16650                 else
16651                         funcs = &i8xx_crtc_funcs;
16652         } else {
16653                 if (INTEL_GEN(dev_priv) >= 8)
16654                         funcs = &bdw_crtc_funcs;
16655                 else
16656                         funcs = &ilk_crtc_funcs;
16657         }
16658
16659         ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16660                                         &primary->base, &cursor->base,
16661                                         funcs, "pipe %c", pipe_name(pipe));
16662         if (ret)
16663                 goto fail;
16664
16665         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16666                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16667         dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16668
16669         if (INTEL_GEN(dev_priv) < 9) {
16670                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16671
16672                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16673                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16674                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16675         }
16676
16677         intel_color_init(crtc);
16678
16679         intel_crtc_crc_init(crtc);
16680
16681         drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16682
16683         return 0;
16684
16685 fail:
16686         intel_crtc_free(crtc);
16687
16688         return ret;
16689 }
16690
16691 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16692                                       struct drm_file *file)
16693 {
16694         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16695         struct drm_crtc *drmmode_crtc;
16696         struct intel_crtc *crtc;
16697
16698         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
16699         if (!drmmode_crtc)
16700                 return -ENOENT;
16701
16702         crtc = to_intel_crtc(drmmode_crtc);
16703         pipe_from_crtc_id->pipe = crtc->pipe;
16704
16705         return 0;
16706 }
16707
16708 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
16709 {
16710         struct drm_device *dev = encoder->base.dev;
16711         struct intel_encoder *source_encoder;
16712         u32 possible_clones = 0;
16713
16714         for_each_intel_encoder(dev, source_encoder) {
16715                 if (encoders_cloneable(encoder, source_encoder))
16716                         possible_clones |= drm_encoder_mask(&source_encoder->base);
16717         }
16718
16719         return possible_clones;
16720 }
16721
16722 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16723 {
16724         struct drm_device *dev = encoder->base.dev;
16725         struct intel_crtc *crtc;
16726         u32 possible_crtcs = 0;
16727
16728         for_each_intel_crtc(dev, crtc) {
16729                 if (encoder->pipe_mask & BIT(crtc->pipe))
16730                         possible_crtcs |= drm_crtc_mask(&crtc->base);
16731         }
16732
16733         return possible_crtcs;
16734 }
16735
16736 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16737 {
16738         if (!IS_MOBILE(dev_priv))
16739                 return false;
16740
16741         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
16742                 return false;
16743
16744         if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
16745                 return false;
16746
16747         return true;
16748 }
16749
16750 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16751 {
16752         if (INTEL_GEN(dev_priv) >= 9)
16753                 return false;
16754
16755         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16756                 return false;
16757
16758         if (HAS_PCH_LPT_H(dev_priv) &&
16759             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16760                 return false;
16761
16762         /* DDI E can't be used if DDI A requires 4 lanes */
16763         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16764                 return false;
16765
16766         if (!dev_priv->vbt.int_crt_support)
16767                 return false;
16768
16769         return true;
16770 }
16771
16772 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16773 {
16774         int pps_num;
16775         int pps_idx;
16776
16777         if (HAS_DDI(dev_priv))
16778                 return;
16779         /*
16780          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16781          * everywhere where registers can be write protected.
16782          */
16783         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16784                 pps_num = 2;
16785         else
16786                 pps_num = 1;
16787
16788         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16789                 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
16790
16791                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16792                 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
16793         }
16794 }
16795
16796 static void intel_pps_init(struct drm_i915_private *dev_priv)
16797 {
16798         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16799                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16800         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16801                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16802         else
16803                 dev_priv->pps_mmio_base = PPS_BASE;
16804
16805         intel_pps_unlock_regs_wa(dev_priv);
16806 }
16807
16808 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16809 {
16810         struct intel_encoder *encoder;
16811         bool dpd_is_edp = false;
16812
16813         intel_pps_init(dev_priv);
16814
16815         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16816                 return;
16817
16818         if (INTEL_GEN(dev_priv) >= 12) {
16819                 intel_ddi_init(dev_priv, PORT_A);
16820                 intel_ddi_init(dev_priv, PORT_B);
16821                 intel_ddi_init(dev_priv, PORT_D);
16822                 intel_ddi_init(dev_priv, PORT_E);
16823                 intel_ddi_init(dev_priv, PORT_F);
16824                 intel_ddi_init(dev_priv, PORT_G);
16825                 intel_ddi_init(dev_priv, PORT_H);
16826                 intel_ddi_init(dev_priv, PORT_I);
16827                 icl_dsi_init(dev_priv);
16828         } else if (IS_ELKHARTLAKE(dev_priv)) {
16829                 intel_ddi_init(dev_priv, PORT_A);
16830                 intel_ddi_init(dev_priv, PORT_B);
16831                 intel_ddi_init(dev_priv, PORT_C);
16832                 intel_ddi_init(dev_priv, PORT_D);
16833                 icl_dsi_init(dev_priv);
16834         } else if (IS_GEN(dev_priv, 11)) {
16835                 intel_ddi_init(dev_priv, PORT_A);
16836                 intel_ddi_init(dev_priv, PORT_B);
16837                 intel_ddi_init(dev_priv, PORT_C);
16838                 intel_ddi_init(dev_priv, PORT_D);
16839                 intel_ddi_init(dev_priv, PORT_E);
16840                 /*
16841                  * On some ICL SKUs port F is not present. No strap bits for
16842                  * this, so rely on VBT.
16843                  * Work around broken VBTs on SKUs known to have no port F.
16844                  */
16845                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16846                     intel_bios_is_port_present(dev_priv, PORT_F))
16847                         intel_ddi_init(dev_priv, PORT_F);
16848
16849                 icl_dsi_init(dev_priv);
16850         } else if (IS_GEN9_LP(dev_priv)) {
16851                 /*
16852                  * FIXME: Broxton doesn't support port detection via the
16853                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16854                  * detect the ports.
16855                  */
16856                 intel_ddi_init(dev_priv, PORT_A);
16857                 intel_ddi_init(dev_priv, PORT_B);
16858                 intel_ddi_init(dev_priv, PORT_C);
16859
16860                 vlv_dsi_init(dev_priv);
16861         } else if (HAS_DDI(dev_priv)) {
16862                 int found;
16863
16864                 if (intel_ddi_crt_present(dev_priv))
16865                         intel_crt_init(dev_priv);
16866
16867                 /*
16868                  * Haswell uses DDI functions to detect digital outputs.
16869                  * On SKL pre-D0 the strap isn't connected, so we assume
16870                  * it's there.
16871                  */
16872                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16873                 /* WaIgnoreDDIAStrap: skl */
16874                 if (found || IS_GEN9_BC(dev_priv))
16875                         intel_ddi_init(dev_priv, PORT_A);
16876
16877                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16878                  * register */
16879                 found = intel_de_read(dev_priv, SFUSE_STRAP);
16880
16881                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16882                         intel_ddi_init(dev_priv, PORT_B);
16883                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16884                         intel_ddi_init(dev_priv, PORT_C);
16885                 if (found & SFUSE_STRAP_DDID_DETECTED)
16886                         intel_ddi_init(dev_priv, PORT_D);
16887                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16888                         intel_ddi_init(dev_priv, PORT_F);
16889                 /*
16890                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16891                  */
16892                 if (IS_GEN9_BC(dev_priv) &&
16893                     intel_bios_is_port_present(dev_priv, PORT_E))
16894                         intel_ddi_init(dev_priv, PORT_E);
16895
16896         } else if (HAS_PCH_SPLIT(dev_priv)) {
16897                 int found;
16898
16899                 /*
16900                  * intel_edp_init_connector() depends on this completing first,
16901                  * to prevent the registration of both eDP and LVDS and the
16902                  * incorrect sharing of the PPS.
16903                  */
16904                 intel_lvds_init(dev_priv);
16905                 intel_crt_init(dev_priv);
16906
16907                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16908
16909                 if (ilk_has_edp_a(dev_priv))
16910                         intel_dp_init(dev_priv, DP_A, PORT_A);
16911
16912                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
16913                         /* PCH SDVOB multiplex with HDMIB */
16914                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16915                         if (!found)
16916                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16917                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
16918                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16919                 }
16920
16921                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
16922                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16923
16924                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
16925                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16926
16927                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
16928                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16929
16930                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
16931                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16932         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16933                 bool has_edp, has_port;
16934
16935                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16936                         intel_crt_init(dev_priv);
16937
16938                 /*
16939                  * The DP_DETECTED bit is the latched state of the DDC
16940                  * SDA pin at boot. However since eDP doesn't require DDC
16941                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16942                  * eDP ports may have been muxed to an alternate function.
16943                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16944                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16945                  * detect eDP ports.
16946                  *
16947                  * Sadly the straps seem to be missing sometimes even for HDMI
16948                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16949                  * and VBT for the presence of the port. Additionally we can't
16950                  * trust the port type the VBT declares as we've seen at least
16951                  * HDMI ports that the VBT claim are DP or eDP.
16952                  */
16953                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16954                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16955                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
16956                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16957                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16958                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16959
16960                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16961                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16962                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
16963                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16964                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16965                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16966
16967                 if (IS_CHERRYVIEW(dev_priv)) {
16968                         /*
16969                          * eDP not supported on port D,
16970                          * so no need to worry about it
16971                          */
16972                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16973                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
16974                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16975                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
16976                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16977                 }
16978
16979                 vlv_dsi_init(dev_priv);
16980         } else if (IS_PINEVIEW(dev_priv)) {
16981                 intel_lvds_init(dev_priv);
16982                 intel_crt_init(dev_priv);
16983         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16984                 bool found = false;
16985
16986                 if (IS_MOBILE(dev_priv))
16987                         intel_lvds_init(dev_priv);
16988
16989                 intel_crt_init(dev_priv);
16990
16991                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
16992                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
16993                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16994                         if (!found && IS_G4X(dev_priv)) {
16995                                 drm_dbg_kms(&dev_priv->drm,
16996                                             "probing HDMI on SDVOB\n");
16997                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16998                         }
16999
17000                         if (!found && IS_G4X(dev_priv))
17001                                 intel_dp_init(dev_priv, DP_B, PORT_B);
17002                 }
17003
17004                 /* Before G4X SDVOC doesn't have its own detect register */
17005
17006                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17007                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17008                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17009                 }
17010
17011                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17012
17013                         if (IS_G4X(dev_priv)) {
17014                                 drm_dbg_kms(&dev_priv->drm,
17015                                             "probing HDMI on SDVOC\n");
17016                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17017                         }
17018                         if (IS_G4X(dev_priv))
17019                                 intel_dp_init(dev_priv, DP_C, PORT_C);
17020                 }
17021
17022                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17023                         intel_dp_init(dev_priv, DP_D, PORT_D);
17024
17025                 if (SUPPORTS_TV(dev_priv))
17026                         intel_tv_init(dev_priv);
17027         } else if (IS_GEN(dev_priv, 2)) {
17028                 if (IS_I85X(dev_priv))
17029                         intel_lvds_init(dev_priv);
17030
17031                 intel_crt_init(dev_priv);
17032                 intel_dvo_init(dev_priv);
17033         }
17034
17035         intel_psr_init(dev_priv);
17036
17037         for_each_intel_encoder(&dev_priv->drm, encoder) {
17038                 encoder->base.possible_crtcs =
17039                         intel_encoder_possible_crtcs(encoder);
17040                 encoder->base.possible_clones =
17041                         intel_encoder_possible_clones(encoder);
17042         }
17043
17044         intel_init_pch_refclk(dev_priv);
17045
17046         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17047 }
17048
17049 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17050 {
17051         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17052
17053         drm_framebuffer_cleanup(fb);
17054         intel_frontbuffer_put(intel_fb->frontbuffer);
17055
17056         kfree(intel_fb);
17057 }
17058
17059 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17060                                                 struct drm_file *file,
17061                                                 unsigned int *handle)
17062 {
17063         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17064         struct drm_i915_private *i915 = to_i915(obj->base.dev);
17065
17066         if (obj->userptr.mm) {
17067                 drm_dbg(&i915->drm,
17068                         "attempting to use a userptr for a framebuffer, denied\n");
17069                 return -EINVAL;
17070         }
17071
17072         return drm_gem_handle_create(file, &obj->base, handle);
17073 }
17074
17075 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17076                                         struct drm_file *file,
17077                                         unsigned flags, unsigned color,
17078                                         struct drm_clip_rect *clips,
17079                                         unsigned num_clips)
17080 {
17081         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17082
17083         i915_gem_object_flush_if_display(obj);
17084         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17085
17086         return 0;
17087 }
17088
17089 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17090         .destroy = intel_user_framebuffer_destroy,
17091         .create_handle = intel_user_framebuffer_create_handle,
17092         .dirty = intel_user_framebuffer_dirty,
17093 };
17094
17095 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17096                                   struct drm_i915_gem_object *obj,
17097                                   struct drm_mode_fb_cmd2 *mode_cmd)
17098 {
17099         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17100         struct drm_framebuffer *fb = &intel_fb->base;
17101         u32 max_stride;
17102         unsigned int tiling, stride;
17103         int ret = -EINVAL;
17104         int i;
17105
17106         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17107         if (!intel_fb->frontbuffer)
17108                 return -ENOMEM;
17109
17110         i915_gem_object_lock(obj);
17111         tiling = i915_gem_object_get_tiling(obj);
17112         stride = i915_gem_object_get_stride(obj);
17113         i915_gem_object_unlock(obj);
17114
17115         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17116                 /*
17117                  * If there's a fence, enforce that
17118                  * the fb modifier and tiling mode match.
17119                  */
17120                 if (tiling != I915_TILING_NONE &&
17121                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17122                         drm_dbg_kms(&dev_priv->drm,
17123                                     "tiling_mode doesn't match fb modifier\n");
17124                         goto err;
17125                 }
17126         } else {
17127                 if (tiling == I915_TILING_X) {
17128                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17129                 } else if (tiling == I915_TILING_Y) {
17130                         drm_dbg_kms(&dev_priv->drm,
17131                                     "No Y tiling for legacy addfb\n");
17132                         goto err;
17133                 }
17134         }
17135
17136         if (!drm_any_plane_has_format(&dev_priv->drm,
17137                                       mode_cmd->pixel_format,
17138                                       mode_cmd->modifier[0])) {
17139                 struct drm_format_name_buf format_name;
17140
17141                 drm_dbg_kms(&dev_priv->drm,
17142                             "unsupported pixel format %s / modifier 0x%llx\n",
17143                             drm_get_format_name(mode_cmd->pixel_format,
17144                                                 &format_name),
17145                             mode_cmd->modifier[0]);
17146                 goto err;
17147         }
17148
17149         /*
17150          * gen2/3 display engine uses the fence if present,
17151          * so the tiling mode must match the fb modifier exactly.
17152          */
17153         if (INTEL_GEN(dev_priv) < 4 &&
17154             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17155                 drm_dbg_kms(&dev_priv->drm,
17156                             "tiling_mode must match fb modifier exactly on gen2/3\n");
17157                 goto err;
17158         }
17159
17160         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17161                                          mode_cmd->modifier[0]);
17162         if (mode_cmd->pitches[0] > max_stride) {
17163                 drm_dbg_kms(&dev_priv->drm,
17164                             "%s pitch (%u) must be at most %d\n",
17165                             mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17166                             "tiled" : "linear",
17167                             mode_cmd->pitches[0], max_stride);
17168                 goto err;
17169         }
17170
17171         /*
17172          * If there's a fence, enforce that
17173          * the fb pitch and fence stride match.
17174          */
17175         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17176                 drm_dbg_kms(&dev_priv->drm,
17177                             "pitch (%d) must match tiling stride (%d)\n",
17178                             mode_cmd->pitches[0], stride);
17179                 goto err;
17180         }
17181
17182         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17183         if (mode_cmd->offsets[0] != 0) {
17184                 drm_dbg_kms(&dev_priv->drm,
17185                             "plane 0 offset (0x%08x) must be 0\n",
17186                             mode_cmd->offsets[0]);
17187                 goto err;
17188         }
17189
17190         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17191
17192         for (i = 0; i < fb->format->num_planes; i++) {
17193                 u32 stride_alignment;
17194
17195                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17196                         drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17197                                     i);
17198                         goto err;
17199                 }
17200
17201                 stride_alignment = intel_fb_stride_alignment(fb, i);
17202                 if (fb->pitches[i] & (stride_alignment - 1)) {
17203                         drm_dbg_kms(&dev_priv->drm,
17204                                     "plane %d pitch (%d) must be at least %u byte aligned\n",
17205                                     i, fb->pitches[i], stride_alignment);
17206                         goto err;
17207                 }
17208
17209                 if (is_gen12_ccs_plane(fb, i)) {
17210                         int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17211
17212                         if (fb->pitches[i] != ccs_aux_stride) {
17213                                 drm_dbg_kms(&dev_priv->drm,
17214                                             "ccs aux plane %d pitch (%d) must be %d\n",
17215                                             i,
17216                                             fb->pitches[i], ccs_aux_stride);
17217                                 goto err;
17218                         }
17219                 }
17220
17221                 fb->obj[i] = &obj->base;
17222         }
17223
17224         ret = intel_fill_fb_info(dev_priv, fb);
17225         if (ret)
17226                 goto err;
17227
17228         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17229         if (ret) {
17230                 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17231                 goto err;
17232         }
17233
17234         return 0;
17235
17236 err:
17237         intel_frontbuffer_put(intel_fb->frontbuffer);
17238         return ret;
17239 }
17240
17241 static struct drm_framebuffer *
17242 intel_user_framebuffer_create(struct drm_device *dev,
17243                               struct drm_file *filp,
17244                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
17245 {
17246         struct drm_framebuffer *fb;
17247         struct drm_i915_gem_object *obj;
17248         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17249
17250         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17251         if (!obj)
17252                 return ERR_PTR(-ENOENT);
17253
17254         fb = intel_framebuffer_create(obj, &mode_cmd);
17255         i915_gem_object_put(obj);
17256
17257         return fb;
17258 }
17259
17260 static enum drm_mode_status
17261 intel_mode_valid(struct drm_device *dev,
17262                  const struct drm_display_mode *mode)
17263 {
17264         struct drm_i915_private *dev_priv = to_i915(dev);
17265         int hdisplay_max, htotal_max;
17266         int vdisplay_max, vtotal_max;
17267
17268         /*
17269          * Can't reject DBLSCAN here because Xorg ddxen can add piles
17270          * of DBLSCAN modes to the output's mode list when they detect
17271          * the scaling mode property on the connector. And they don't
17272          * ask the kernel to validate those modes in any way until
17273          * modeset time at which point the client gets a protocol error.
17274          * So in order to not upset those clients we silently ignore the
17275          * DBLSCAN flag on such connectors. For other connectors we will
17276          * reject modes with the DBLSCAN flag in encoder->compute_config().
17277          * And we always reject DBLSCAN modes in connector->mode_valid()
17278          * as we never want such modes on the connector's mode list.
17279          */
17280
17281         if (mode->vscan > 1)
17282                 return MODE_NO_VSCAN;
17283
17284         if (mode->flags & DRM_MODE_FLAG_HSKEW)
17285                 return MODE_H_ILLEGAL;
17286
17287         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17288                            DRM_MODE_FLAG_NCSYNC |
17289                            DRM_MODE_FLAG_PCSYNC))
17290                 return MODE_HSYNC;
17291
17292         if (mode->flags & (DRM_MODE_FLAG_BCAST |
17293                            DRM_MODE_FLAG_PIXMUX |
17294                            DRM_MODE_FLAG_CLKDIV2))
17295                 return MODE_BAD;
17296
17297         /* Transcoder timing limits */
17298         if (INTEL_GEN(dev_priv) >= 11) {
17299                 hdisplay_max = 16384;
17300                 vdisplay_max = 8192;
17301                 htotal_max = 16384;
17302                 vtotal_max = 8192;
17303         } else if (INTEL_GEN(dev_priv) >= 9 ||
17304                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17305                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17306                 vdisplay_max = 4096;
17307                 htotal_max = 8192;
17308                 vtotal_max = 8192;
17309         } else if (INTEL_GEN(dev_priv) >= 3) {
17310                 hdisplay_max = 4096;
17311                 vdisplay_max = 4096;
17312                 htotal_max = 8192;
17313                 vtotal_max = 8192;
17314         } else {
17315                 hdisplay_max = 2048;
17316                 vdisplay_max = 2048;
17317                 htotal_max = 4096;
17318                 vtotal_max = 4096;
17319         }
17320
17321         if (mode->hdisplay > hdisplay_max ||
17322             mode->hsync_start > htotal_max ||
17323             mode->hsync_end > htotal_max ||
17324             mode->htotal > htotal_max)
17325                 return MODE_H_ILLEGAL;
17326
17327         if (mode->vdisplay > vdisplay_max ||
17328             mode->vsync_start > vtotal_max ||
17329             mode->vsync_end > vtotal_max ||
17330             mode->vtotal > vtotal_max)
17331                 return MODE_V_ILLEGAL;
17332
17333         if (INTEL_GEN(dev_priv) >= 5) {
17334                 if (mode->hdisplay < 64 ||
17335                     mode->htotal - mode->hdisplay < 32)
17336                         return MODE_H_ILLEGAL;
17337
17338                 if (mode->vtotal - mode->vdisplay < 5)
17339                         return MODE_V_ILLEGAL;
17340         } else {
17341                 if (mode->htotal - mode->hdisplay < 32)
17342                         return MODE_H_ILLEGAL;
17343
17344                 if (mode->vtotal - mode->vdisplay < 3)
17345                         return MODE_V_ILLEGAL;
17346         }
17347
17348         return MODE_OK;
17349 }
17350
17351 enum drm_mode_status
17352 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17353                                 const struct drm_display_mode *mode)
17354 {
17355         int plane_width_max, plane_height_max;
17356
17357         /*
17358          * intel_mode_valid() should be
17359          * sufficient on older platforms.
17360          */
17361         if (INTEL_GEN(dev_priv) < 9)
17362                 return MODE_OK;
17363
17364         /*
17365          * Most people will probably want a fullscreen
17366          * plane so let's not advertize modes that are
17367          * too big for that.
17368          */
17369         if (INTEL_GEN(dev_priv) >= 11) {
17370                 plane_width_max = 5120;
17371                 plane_height_max = 4320;
17372         } else {
17373                 plane_width_max = 5120;
17374                 plane_height_max = 4096;
17375         }
17376
17377         if (mode->hdisplay > plane_width_max)
17378                 return MODE_H_ILLEGAL;
17379
17380         if (mode->vdisplay > plane_height_max)
17381                 return MODE_V_ILLEGAL;
17382
17383         return MODE_OK;
17384 }
17385
17386 static const struct drm_mode_config_funcs intel_mode_funcs = {
17387         .fb_create = intel_user_framebuffer_create,
17388         .get_format_info = intel_get_format_info,
17389         .output_poll_changed = intel_fbdev_output_poll_changed,
17390         .mode_valid = intel_mode_valid,
17391         .atomic_check = intel_atomic_check,
17392         .atomic_commit = intel_atomic_commit,
17393         .atomic_state_alloc = intel_atomic_state_alloc,
17394         .atomic_state_clear = intel_atomic_state_clear,
17395         .atomic_state_free = intel_atomic_state_free,
17396 };
17397
17398 /**
17399  * intel_init_display_hooks - initialize the display modesetting hooks
17400  * @dev_priv: device private
17401  */
17402 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17403 {
17404         intel_init_cdclk_hooks(dev_priv);
17405
17406         if (INTEL_GEN(dev_priv) >= 9) {
17407                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17408                 dev_priv->display.get_initial_plane_config =
17409                         skl_get_initial_plane_config;
17410                 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17411                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17412                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17413         } else if (HAS_DDI(dev_priv)) {
17414                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17415                 dev_priv->display.get_initial_plane_config =
17416                         i9xx_get_initial_plane_config;
17417                 dev_priv->display.crtc_compute_clock =
17418                         hsw_crtc_compute_clock;
17419                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17420                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17421         } else if (HAS_PCH_SPLIT(dev_priv)) {
17422                 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17423                 dev_priv->display.get_initial_plane_config =
17424                         i9xx_get_initial_plane_config;
17425                 dev_priv->display.crtc_compute_clock =
17426                         ilk_crtc_compute_clock;
17427                 dev_priv->display.crtc_enable = ilk_crtc_enable;
17428                 dev_priv->display.crtc_disable = ilk_crtc_disable;
17429         } else if (IS_CHERRYVIEW(dev_priv)) {
17430                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17431                 dev_priv->display.get_initial_plane_config =
17432                         i9xx_get_initial_plane_config;
17433                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17434                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17435                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17436         } else if (IS_VALLEYVIEW(dev_priv)) {
17437                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17438                 dev_priv->display.get_initial_plane_config =
17439                         i9xx_get_initial_plane_config;
17440                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17441                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17442                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17443         } else if (IS_G4X(dev_priv)) {
17444                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17445                 dev_priv->display.get_initial_plane_config =
17446                         i9xx_get_initial_plane_config;
17447                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17448                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17449                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17450         } else if (IS_PINEVIEW(dev_priv)) {
17451                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17452                 dev_priv->display.get_initial_plane_config =
17453                         i9xx_get_initial_plane_config;
17454                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17455                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17456                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17457         } else if (!IS_GEN(dev_priv, 2)) {
17458                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17459                 dev_priv->display.get_initial_plane_config =
17460                         i9xx_get_initial_plane_config;
17461                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17462                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17463                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17464         } else {
17465                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17466                 dev_priv->display.get_initial_plane_config =
17467                         i9xx_get_initial_plane_config;
17468                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17469                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17470                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17471         }
17472
17473         if (IS_GEN(dev_priv, 5)) {
17474                 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17475         } else if (IS_GEN(dev_priv, 6)) {
17476                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17477         } else if (IS_IVYBRIDGE(dev_priv)) {
17478                 /* FIXME: detect B0+ stepping and use auto training */
17479                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17480         }
17481
17482         if (INTEL_GEN(dev_priv) >= 9)
17483                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17484         else
17485                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17486
17487 }
17488
17489 void intel_modeset_init_hw(struct drm_i915_private *i915)
17490 {
17491         struct intel_cdclk_state *cdclk_state =
17492                 to_intel_cdclk_state(i915->cdclk.obj.state);
17493         struct intel_dbuf_state *dbuf_state =
17494                 to_intel_dbuf_state(i915->dbuf.obj.state);
17495
17496         intel_update_cdclk(i915);
17497         intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17498         cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17499
17500         dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17501 }
17502
17503 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17504 {
17505         struct drm_plane *plane;
17506         struct intel_crtc *crtc;
17507
17508         for_each_intel_crtc(state->dev, crtc) {
17509                 struct intel_crtc_state *crtc_state;
17510
17511                 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17512                 if (IS_ERR(crtc_state))
17513                         return PTR_ERR(crtc_state);
17514
17515                 if (crtc_state->hw.active) {
17516                         /*
17517                          * Preserve the inherited flag to avoid
17518                          * taking the full modeset path.
17519                          */
17520                         crtc_state->inherited = true;
17521                 }
17522         }
17523
17524         drm_for_each_plane(plane, state->dev) {
17525                 struct drm_plane_state *plane_state;
17526
17527                 plane_state = drm_atomic_get_plane_state(state, plane);
17528                 if (IS_ERR(plane_state))
17529                         return PTR_ERR(plane_state);
17530         }
17531
17532         return 0;
17533 }
17534
17535 /*
17536  * Calculate what we think the watermarks should be for the state we've read
17537  * out of the hardware and then immediately program those watermarks so that
17538  * we ensure the hardware settings match our internal state.
17539  *
17540  * We can calculate what we think WM's should be by creating a duplicate of the
17541  * current state (which was constructed during hardware readout) and running it
17542  * through the atomic check code to calculate new watermark values in the
17543  * state object.
17544  */
17545 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17546 {
17547         struct drm_atomic_state *state;
17548         struct intel_atomic_state *intel_state;
17549         struct intel_crtc *crtc;
17550         struct intel_crtc_state *crtc_state;
17551         struct drm_modeset_acquire_ctx ctx;
17552         int ret;
17553         int i;
17554
17555         /* Only supported on platforms that use atomic watermark design */
17556         if (!dev_priv->display.optimize_watermarks)
17557                 return;
17558
17559         state = drm_atomic_state_alloc(&dev_priv->drm);
17560         if (drm_WARN_ON(&dev_priv->drm, !state))
17561                 return;
17562
17563         intel_state = to_intel_atomic_state(state);
17564
17565         drm_modeset_acquire_init(&ctx, 0);
17566
17567 retry:
17568         state->acquire_ctx = &ctx;
17569
17570         /*
17571          * Hardware readout is the only time we don't want to calculate
17572          * intermediate watermarks (since we don't trust the current
17573          * watermarks).
17574          */
17575         if (!HAS_GMCH(dev_priv))
17576                 intel_state->skip_intermediate_wm = true;
17577
17578         ret = sanitize_watermarks_add_affected(state);
17579         if (ret)
17580                 goto fail;
17581
17582         ret = intel_atomic_check(&dev_priv->drm, state);
17583         if (ret)
17584                 goto fail;
17585
17586         /* Write calculated watermark values back */
17587         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17588                 crtc_state->wm.need_postvbl_update = true;
17589                 dev_priv->display.optimize_watermarks(intel_state, crtc);
17590
17591                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17592         }
17593
17594 fail:
17595         if (ret == -EDEADLK) {
17596                 drm_atomic_state_clear(state);
17597                 drm_modeset_backoff(&ctx);
17598                 goto retry;
17599         }
17600
17601         /*
17602          * If we fail here, it means that the hardware appears to be
17603          * programmed in a way that shouldn't be possible, given our
17604          * understanding of watermark requirements.  This might mean a
17605          * mistake in the hardware readout code or a mistake in the
17606          * watermark calculations for a given platform.  Raise a WARN
17607          * so that this is noticeable.
17608          *
17609          * If this actually happens, we'll have to just leave the
17610          * BIOS-programmed watermarks untouched and hope for the best.
17611          */
17612         drm_WARN(&dev_priv->drm, ret,
17613                  "Could not determine valid watermarks for inherited state\n");
17614
17615         drm_atomic_state_put(state);
17616
17617         drm_modeset_drop_locks(&ctx);
17618         drm_modeset_acquire_fini(&ctx);
17619 }
17620
17621 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17622 {
17623         if (IS_GEN(dev_priv, 5)) {
17624                 u32 fdi_pll_clk =
17625                         intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17626
17627                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17628         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17629                 dev_priv->fdi_pll_freq = 270000;
17630         } else {
17631                 return;
17632         }
17633
17634         drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17635 }
17636
17637 static int intel_initial_commit(struct drm_device *dev)
17638 {
17639         struct drm_atomic_state *state = NULL;
17640         struct drm_modeset_acquire_ctx ctx;
17641         struct intel_crtc *crtc;
17642         int ret = 0;
17643
17644         state = drm_atomic_state_alloc(dev);
17645         if (!state)
17646                 return -ENOMEM;
17647
17648         drm_modeset_acquire_init(&ctx, 0);
17649
17650 retry:
17651         state->acquire_ctx = &ctx;
17652
17653         for_each_intel_crtc(dev, crtc) {
17654                 struct intel_crtc_state *crtc_state =
17655                         intel_atomic_get_crtc_state(state, crtc);
17656
17657                 if (IS_ERR(crtc_state)) {
17658                         ret = PTR_ERR(crtc_state);
17659                         goto out;
17660                 }
17661
17662                 if (crtc_state->hw.active) {
17663                         /*
17664                          * We've not yet detected sink capabilities
17665                          * (audio,infoframes,etc.) and thus we don't want to
17666                          * force a full state recomputation yet. We want that to
17667                          * happen only for the first real commit from userspace.
17668                          * So preserve the inherited flag for the time being.
17669                          */
17670                         crtc_state->inherited = true;
17671
17672                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
17673                         if (ret)
17674                                 goto out;
17675
17676                         /*
17677                          * FIXME hack to force a LUT update to avoid the
17678                          * plane update forcing the pipe gamma on without
17679                          * having a proper LUT loaded. Remove once we
17680                          * have readout for pipe gamma enable.
17681                          */
17682                         crtc_state->uapi.color_mgmt_changed = true;
17683
17684                         /*
17685                          * FIXME hack to force full modeset when DSC is being
17686                          * used.
17687                          *
17688                          * As long as we do not have full state readout and
17689                          * config comparison of crtc_state->dsc, we have no way
17690                          * to ensure reliable fastset. Remove once we have
17691                          * readout for DSC.
17692                          */
17693                         if (crtc_state->dsc.compression_enable) {
17694                                 ret = drm_atomic_add_affected_connectors(state,
17695                                                                          &crtc->base);
17696                                 if (ret)
17697                                         goto out;
17698                                 crtc_state->uapi.mode_changed = true;
17699                                 drm_dbg_kms(dev, "Force full modeset for DSC\n");
17700                         }
17701                 }
17702         }
17703
17704         ret = drm_atomic_commit(state);
17705
17706 out:
17707         if (ret == -EDEADLK) {
17708                 drm_atomic_state_clear(state);
17709                 drm_modeset_backoff(&ctx);
17710                 goto retry;
17711         }
17712
17713         drm_atomic_state_put(state);
17714
17715         drm_modeset_drop_locks(&ctx);
17716         drm_modeset_acquire_fini(&ctx);
17717
17718         return ret;
17719 }
17720
17721 static void intel_mode_config_init(struct drm_i915_private *i915)
17722 {
17723         struct drm_mode_config *mode_config = &i915->drm.mode_config;
17724
17725         drm_mode_config_init(&i915->drm);
17726         INIT_LIST_HEAD(&i915->global_obj_list);
17727
17728         mode_config->min_width = 0;
17729         mode_config->min_height = 0;
17730
17731         mode_config->preferred_depth = 24;
17732         mode_config->prefer_shadow = 1;
17733
17734         mode_config->allow_fb_modifiers = true;
17735
17736         mode_config->funcs = &intel_mode_funcs;
17737
17738         /*
17739          * Maximum framebuffer dimensions, chosen to match
17740          * the maximum render engine surface size on gen4+.
17741          */
17742         if (INTEL_GEN(i915) >= 7) {
17743                 mode_config->max_width = 16384;
17744                 mode_config->max_height = 16384;
17745         } else if (INTEL_GEN(i915) >= 4) {
17746                 mode_config->max_width = 8192;
17747                 mode_config->max_height = 8192;
17748         } else if (IS_GEN(i915, 3)) {
17749                 mode_config->max_width = 4096;
17750                 mode_config->max_height = 4096;
17751         } else {
17752                 mode_config->max_width = 2048;
17753                 mode_config->max_height = 2048;
17754         }
17755
17756         if (IS_I845G(i915) || IS_I865G(i915)) {
17757                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
17758                 mode_config->cursor_height = 1023;
17759         } else if (IS_I830(i915) || IS_I85X(i915) ||
17760                    IS_I915G(i915) || IS_I915GM(i915)) {
17761                 mode_config->cursor_width = 64;
17762                 mode_config->cursor_height = 64;
17763         } else {
17764                 mode_config->cursor_width = 256;
17765                 mode_config->cursor_height = 256;
17766         }
17767 }
17768
17769 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
17770 {
17771         intel_atomic_global_obj_cleanup(i915);
17772         drm_mode_config_cleanup(&i915->drm);
17773 }
17774
17775 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
17776 {
17777         if (plane_config->fb) {
17778                 struct drm_framebuffer *fb = &plane_config->fb->base;
17779
17780                 /* We may only have the stub and not a full framebuffer */
17781                 if (drm_framebuffer_read_refcount(fb))
17782                         drm_framebuffer_put(fb);
17783                 else
17784                         kfree(fb);
17785         }
17786
17787         if (plane_config->vma)
17788                 i915_vma_put(plane_config->vma);
17789 }
17790
17791 /* part #1: call before irq install */
17792 int intel_modeset_init_noirq(struct drm_i915_private *i915)
17793 {
17794         int ret;
17795
17796         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
17797         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
17798                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
17799
17800         intel_mode_config_init(i915);
17801
17802         ret = intel_cdclk_init(i915);
17803         if (ret)
17804                 return ret;
17805
17806         ret = intel_dbuf_init(i915);
17807         if (ret)
17808                 return ret;
17809
17810         ret = intel_bw_init(i915);
17811         if (ret)
17812                 return ret;
17813
17814         init_llist_head(&i915->atomic_helper.free_list);
17815         INIT_WORK(&i915->atomic_helper.free_work,
17816                   intel_atomic_helper_free_state_worker);
17817
17818         intel_init_quirks(i915);
17819
17820         intel_fbc_init(i915);
17821
17822         return 0;
17823 }
17824
17825 /* part #2: call after irq install */
17826 int intel_modeset_init(struct drm_i915_private *i915)
17827 {
17828         struct drm_device *dev = &i915->drm;
17829         enum pipe pipe;
17830         struct intel_crtc *crtc;
17831         int ret;
17832
17833         intel_init_pm(i915);
17834
17835         intel_panel_sanitize_ssc(i915);
17836
17837         intel_gmbus_setup(i915);
17838
17839         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
17840                     INTEL_NUM_PIPES(i915),
17841                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17842
17843         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
17844                 for_each_pipe(i915, pipe) {
17845                         ret = intel_crtc_init(i915, pipe);
17846                         if (ret) {
17847                                 intel_mode_config_cleanup(i915);
17848                                 return ret;
17849                         }
17850                 }
17851         }
17852
17853         intel_plane_possible_crtcs_init(i915);
17854         intel_shared_dpll_init(dev);
17855         intel_update_fdi_pll_freq(i915);
17856
17857         intel_update_czclk(i915);
17858         intel_modeset_init_hw(i915);
17859
17860         intel_hdcp_component_init(i915);
17861
17862         if (i915->max_cdclk_freq == 0)
17863                 intel_update_max_cdclk(i915);
17864
17865         /* Just disable it once at startup */
17866         intel_vga_disable(i915);
17867         intel_setup_outputs(i915);
17868
17869         drm_modeset_lock_all(dev);
17870         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17871         drm_modeset_unlock_all(dev);
17872
17873         for_each_intel_crtc(dev, crtc) {
17874                 struct intel_initial_plane_config plane_config = {};
17875
17876                 if (!crtc->active)
17877                         continue;
17878
17879                 /*
17880                  * Note that reserving the BIOS fb up front prevents us
17881                  * from stuffing other stolen allocations like the ring
17882                  * on top.  This prevents some ugliness at boot time, and
17883                  * can even allow for smooth boot transitions if the BIOS
17884                  * fb is large enough for the active pipe configuration.
17885                  */
17886                 i915->display.get_initial_plane_config(crtc, &plane_config);
17887
17888                 /*
17889                  * If the fb is shared between multiple heads, we'll
17890                  * just get the first one.
17891                  */
17892                 intel_find_initial_plane_obj(crtc, &plane_config);
17893
17894                 plane_config_fini(&plane_config);
17895         }
17896
17897         /*
17898          * Make sure hardware watermarks really match the state we read out.
17899          * Note that we need to do this after reconstructing the BIOS fb's
17900          * since the watermark calculation done here will use pstate->fb.
17901          */
17902         if (!HAS_GMCH(i915))
17903                 sanitize_watermarks(i915);
17904
17905         /*
17906          * Force all active planes to recompute their states. So that on
17907          * mode_setcrtc after probe, all the intel_plane_state variables
17908          * are already calculated and there is no assert_plane warnings
17909          * during bootup.
17910          */
17911         ret = intel_initial_commit(dev);
17912         if (ret)
17913                 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
17914
17915         return 0;
17916 }
17917
17918 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17919 {
17920         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17921         /* 640x480@60Hz, ~25175 kHz */
17922         struct dpll clock = {
17923                 .m1 = 18,
17924                 .m2 = 7,
17925                 .p1 = 13,
17926                 .p2 = 4,
17927                 .n = 2,
17928         };
17929         u32 dpll, fp;
17930         int i;
17931
17932         drm_WARN_ON(&dev_priv->drm,
17933                     i9xx_calc_dpll_params(48000, &clock) != 25154);
17934
17935         drm_dbg_kms(&dev_priv->drm,
17936                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17937                     pipe_name(pipe), clock.vco, clock.dot);
17938
17939         fp = i9xx_dpll_compute_fp(&clock);
17940         dpll = DPLL_DVO_2X_MODE |
17941                 DPLL_VGA_MODE_DIS |
17942                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17943                 PLL_P2_DIVIDE_BY_4 |
17944                 PLL_REF_INPUT_DREFCLK |
17945                 DPLL_VCO_ENABLE;
17946
17947         intel_de_write(dev_priv, FP0(pipe), fp);
17948         intel_de_write(dev_priv, FP1(pipe), fp);
17949
17950         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17951         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17952         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17953         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17954         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17955         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17956         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17957
17958         /*
17959          * Apparently we need to have VGA mode enabled prior to changing
17960          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17961          * dividers, even though the register value does change.
17962          */
17963         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17964         intel_de_write(dev_priv, DPLL(pipe), dpll);
17965
17966         /* Wait for the clocks to stabilize. */
17967         intel_de_posting_read(dev_priv, DPLL(pipe));
17968         udelay(150);
17969
17970         /* The pixel multiplier can only be updated once the
17971          * DPLL is enabled and the clocks are stable.
17972          *
17973          * So write it again.
17974          */
17975         intel_de_write(dev_priv, DPLL(pipe), dpll);
17976
17977         /* We do this three times for luck */
17978         for (i = 0; i < 3 ; i++) {
17979                 intel_de_write(dev_priv, DPLL(pipe), dpll);
17980                 intel_de_posting_read(dev_priv, DPLL(pipe));
17981                 udelay(150); /* wait for warmup */
17982         }
17983
17984         intel_de_write(dev_priv, PIPECONF(pipe),
17985                        PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17986         intel_de_posting_read(dev_priv, PIPECONF(pipe));
17987
17988         intel_wait_for_pipe_scanline_moving(crtc);
17989 }
17990
17991 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17992 {
17993         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17994
17995         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
17996                     pipe_name(pipe));
17997
17998         drm_WARN_ON(&dev_priv->drm,
17999                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18000                     DISPLAY_PLANE_ENABLE);
18001         drm_WARN_ON(&dev_priv->drm,
18002                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18003                     DISPLAY_PLANE_ENABLE);
18004         drm_WARN_ON(&dev_priv->drm,
18005                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18006                     DISPLAY_PLANE_ENABLE);
18007         drm_WARN_ON(&dev_priv->drm,
18008                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18009         drm_WARN_ON(&dev_priv->drm,
18010                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18011
18012         intel_de_write(dev_priv, PIPECONF(pipe), 0);
18013         intel_de_posting_read(dev_priv, PIPECONF(pipe));
18014
18015         intel_wait_for_pipe_scanline_stopped(crtc);
18016
18017         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18018         intel_de_posting_read(dev_priv, DPLL(pipe));
18019 }
18020
18021 static void
18022 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18023 {
18024         struct intel_crtc *crtc;
18025
18026         if (INTEL_GEN(dev_priv) >= 4)
18027                 return;
18028
18029         for_each_intel_crtc(&dev_priv->drm, crtc) {
18030                 struct intel_plane *plane =
18031                         to_intel_plane(crtc->base.primary);
18032                 struct intel_crtc *plane_crtc;
18033                 enum pipe pipe;
18034
18035                 if (!plane->get_hw_state(plane, &pipe))
18036                         continue;
18037
18038                 if (pipe == crtc->pipe)
18039                         continue;
18040
18041                 drm_dbg_kms(&dev_priv->drm,
18042                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18043                             plane->base.base.id, plane->base.name);
18044
18045                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18046                 intel_plane_disable_noatomic(plane_crtc, plane);
18047         }
18048 }
18049
18050 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18051 {
18052         struct drm_device *dev = crtc->base.dev;
18053         struct intel_encoder *encoder;
18054
18055         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18056                 return true;
18057
18058         return false;
18059 }
18060
18061 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18062 {
18063         struct drm_device *dev = encoder->base.dev;
18064         struct intel_connector *connector;
18065
18066         for_each_connector_on_encoder(dev, &encoder->base, connector)
18067                 return connector;
18068
18069         return NULL;
18070 }
18071
18072 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18073                               enum pipe pch_transcoder)
18074 {
18075         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18076                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18077 }
18078
18079 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18080 {
18081         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18082         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18083         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18084
18085         if (INTEL_GEN(dev_priv) >= 9 ||
18086             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18087                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18088                 u32 val;
18089
18090                 if (transcoder_is_dsi(cpu_transcoder))
18091                         return;
18092
18093                 val = intel_de_read(dev_priv, reg);
18094                 val &= ~HSW_FRAME_START_DELAY_MASK;
18095                 val |= HSW_FRAME_START_DELAY(0);
18096                 intel_de_write(dev_priv, reg, val);
18097         } else {
18098                 i915_reg_t reg = PIPECONF(cpu_transcoder);
18099                 u32 val;
18100
18101                 val = intel_de_read(dev_priv, reg);
18102                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18103                 val |= PIPECONF_FRAME_START_DELAY(0);
18104                 intel_de_write(dev_priv, reg, val);
18105         }
18106
18107         if (!crtc_state->has_pch_encoder)
18108                 return;
18109
18110         if (HAS_PCH_IBX(dev_priv)) {
18111                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18112                 u32 val;
18113
18114                 val = intel_de_read(dev_priv, reg);
18115                 val &= ~TRANS_FRAME_START_DELAY_MASK;
18116                 val |= TRANS_FRAME_START_DELAY(0);
18117                 intel_de_write(dev_priv, reg, val);
18118         } else {
18119                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18120                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18121                 u32 val;
18122
18123                 val = intel_de_read(dev_priv, reg);
18124                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18125                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18126                 intel_de_write(dev_priv, reg, val);
18127         }
18128 }
18129
18130 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18131                                 struct drm_modeset_acquire_ctx *ctx)
18132 {
18133         struct drm_device *dev = crtc->base.dev;
18134         struct drm_i915_private *dev_priv = to_i915(dev);
18135         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18136
18137         if (crtc_state->hw.active) {
18138                 struct intel_plane *plane;
18139
18140                 /* Clear any frame start delays used for debugging left by the BIOS */
18141                 intel_sanitize_frame_start_delay(crtc_state);
18142
18143                 /* Disable everything but the primary plane */
18144                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18145                         const struct intel_plane_state *plane_state =
18146                                 to_intel_plane_state(plane->base.state);
18147
18148                         if (plane_state->uapi.visible &&
18149                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18150                                 intel_plane_disable_noatomic(crtc, plane);
18151                 }
18152
18153                 /*
18154                  * Disable any background color set by the BIOS, but enable the
18155                  * gamma and CSC to match how we program our planes.
18156                  */
18157                 if (INTEL_GEN(dev_priv) >= 9)
18158                         intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18159                                        SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18160         }
18161
18162         /* Adjust the state of the output pipe according to whether we
18163          * have active connectors/encoders. */
18164         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18165                 intel_crtc_disable_noatomic(crtc, ctx);
18166
18167         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18168                 /*
18169                  * We start out with underrun reporting disabled to avoid races.
18170                  * For correct bookkeeping mark this on active crtcs.
18171                  *
18172                  * Also on gmch platforms we dont have any hardware bits to
18173                  * disable the underrun reporting. Which means we need to start
18174                  * out with underrun reporting disabled also on inactive pipes,
18175                  * since otherwise we'll complain about the garbage we read when
18176                  * e.g. coming up after runtime pm.
18177                  *
18178                  * No protection against concurrent access is required - at
18179                  * worst a fifo underrun happens which also sets this to false.
18180                  */
18181                 crtc->cpu_fifo_underrun_disabled = true;
18182                 /*
18183                  * We track the PCH trancoder underrun reporting state
18184                  * within the crtc. With crtc for pipe A housing the underrun
18185                  * reporting state for PCH transcoder A, crtc for pipe B housing
18186                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18187                  * and marking underrun reporting as disabled for the non-existing
18188                  * PCH transcoders B and C would prevent enabling the south
18189                  * error interrupt (see cpt_can_enable_serr_int()).
18190                  */
18191                 if (has_pch_trancoder(dev_priv, crtc->pipe))
18192                         crtc->pch_fifo_underrun_disabled = true;
18193         }
18194 }
18195
18196 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18197 {
18198         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18199
18200         /*
18201          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18202          * the hardware when a high res displays plugged in. DPLL P
18203          * divider is zero, and the pipe timings are bonkers. We'll
18204          * try to disable everything in that case.
18205          *
18206          * FIXME would be nice to be able to sanitize this state
18207          * without several WARNs, but for now let's take the easy
18208          * road.
18209          */
18210         return IS_GEN(dev_priv, 6) &&
18211                 crtc_state->hw.active &&
18212                 crtc_state->shared_dpll &&
18213                 crtc_state->port_clock == 0;
18214 }
18215
18216 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18217 {
18218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18219         struct intel_connector *connector;
18220         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18221         struct intel_crtc_state *crtc_state = crtc ?
18222                 to_intel_crtc_state(crtc->base.state) : NULL;
18223
18224         /* We need to check both for a crtc link (meaning that the
18225          * encoder is active and trying to read from a pipe) and the
18226          * pipe itself being active. */
18227         bool has_active_crtc = crtc_state &&
18228                 crtc_state->hw.active;
18229
18230         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18231                 drm_dbg_kms(&dev_priv->drm,
18232                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18233                             pipe_name(crtc->pipe));
18234                 has_active_crtc = false;
18235         }
18236
18237         connector = intel_encoder_find_connector(encoder);
18238         if (connector && !has_active_crtc) {
18239                 drm_dbg_kms(&dev_priv->drm,
18240                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18241                             encoder->base.base.id,
18242                             encoder->base.name);
18243
18244                 /* Connector is active, but has no active pipe. This is
18245                  * fallout from our resume register restoring. Disable
18246                  * the encoder manually again. */
18247                 if (crtc_state) {
18248                         struct drm_encoder *best_encoder;
18249
18250                         drm_dbg_kms(&dev_priv->drm,
18251                                     "[ENCODER:%d:%s] manually disabled\n",
18252                                     encoder->base.base.id,
18253                                     encoder->base.name);
18254
18255                         /* avoid oopsing in case the hooks consult best_encoder */
18256                         best_encoder = connector->base.state->best_encoder;
18257                         connector->base.state->best_encoder = &encoder->base;
18258
18259                         /* FIXME NULL atomic state passed! */
18260                         if (encoder->disable)
18261                                 encoder->disable(NULL, encoder, crtc_state,
18262                                                  connector->base.state);
18263                         if (encoder->post_disable)
18264                                 encoder->post_disable(NULL, encoder, crtc_state,
18265                                                       connector->base.state);
18266
18267                         connector->base.state->best_encoder = best_encoder;
18268                 }
18269                 encoder->base.crtc = NULL;
18270
18271                 /* Inconsistent output/port/pipe state happens presumably due to
18272                  * a bug in one of the get_hw_state functions. Or someplace else
18273                  * in our code, like the register restore mess on resume. Clamp
18274                  * things to off as a safer default. */
18275
18276                 connector->base.dpms = DRM_MODE_DPMS_OFF;
18277                 connector->base.encoder = NULL;
18278         }
18279
18280         /* notify opregion of the sanitized encoder state */
18281         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18282
18283         if (INTEL_GEN(dev_priv) >= 11)
18284                 icl_sanitize_encoder_pll_mapping(encoder);
18285 }
18286
18287 /* FIXME read out full plane state for all planes */
18288 static void readout_plane_state(struct drm_i915_private *dev_priv)
18289 {
18290         struct intel_plane *plane;
18291         struct intel_crtc *crtc;
18292
18293         for_each_intel_plane(&dev_priv->drm, plane) {
18294                 struct intel_plane_state *plane_state =
18295                         to_intel_plane_state(plane->base.state);
18296                 struct intel_crtc_state *crtc_state;
18297                 enum pipe pipe = PIPE_A;
18298                 bool visible;
18299
18300                 visible = plane->get_hw_state(plane, &pipe);
18301
18302                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18303                 crtc_state = to_intel_crtc_state(crtc->base.state);
18304
18305                 intel_set_plane_visible(crtc_state, plane_state, visible);
18306
18307                 drm_dbg_kms(&dev_priv->drm,
18308                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18309                             plane->base.base.id, plane->base.name,
18310                             enableddisabled(visible), pipe_name(pipe));
18311         }
18312
18313         for_each_intel_crtc(&dev_priv->drm, crtc) {
18314                 struct intel_crtc_state *crtc_state =
18315                         to_intel_crtc_state(crtc->base.state);
18316
18317                 fixup_active_planes(crtc_state);
18318         }
18319 }
18320
18321 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18322 {
18323         struct drm_i915_private *dev_priv = to_i915(dev);
18324         struct intel_cdclk_state *cdclk_state =
18325                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18326         struct intel_dbuf_state *dbuf_state =
18327                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18328         enum pipe pipe;
18329         struct intel_crtc *crtc;
18330         struct intel_encoder *encoder;
18331         struct intel_connector *connector;
18332         struct drm_connector_list_iter conn_iter;
18333         u8 active_pipes = 0;
18334
18335         for_each_intel_crtc(dev, crtc) {
18336                 struct intel_crtc_state *crtc_state =
18337                         to_intel_crtc_state(crtc->base.state);
18338
18339                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18340                 intel_crtc_free_hw_state(crtc_state);
18341                 intel_crtc_state_reset(crtc_state, crtc);
18342
18343                 crtc_state->hw.active = crtc_state->hw.enable =
18344                         dev_priv->display.get_pipe_config(crtc, crtc_state);
18345
18346                 crtc->base.enabled = crtc_state->hw.enable;
18347                 crtc->active = crtc_state->hw.active;
18348
18349                 if (crtc_state->hw.active)
18350                         active_pipes |= BIT(crtc->pipe);
18351
18352                 drm_dbg_kms(&dev_priv->drm,
18353                             "[CRTC:%d:%s] hw state readout: %s\n",
18354                             crtc->base.base.id, crtc->base.name,
18355                             enableddisabled(crtc_state->hw.active));
18356         }
18357
18358         dev_priv->active_pipes = cdclk_state->active_pipes =
18359                 dbuf_state->active_pipes = active_pipes;
18360
18361         readout_plane_state(dev_priv);
18362
18363         intel_dpll_readout_hw_state(dev_priv);
18364
18365         for_each_intel_encoder(dev, encoder) {
18366                 pipe = 0;
18367
18368                 if (encoder->get_hw_state(encoder, &pipe)) {
18369                         struct intel_crtc_state *crtc_state;
18370
18371                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18372                         crtc_state = to_intel_crtc_state(crtc->base.state);
18373
18374                         encoder->base.crtc = &crtc->base;
18375                         encoder->get_config(encoder, crtc_state);
18376                 } else {
18377                         encoder->base.crtc = NULL;
18378                 }
18379
18380                 drm_dbg_kms(&dev_priv->drm,
18381                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18382                             encoder->base.base.id, encoder->base.name,
18383                             enableddisabled(encoder->base.crtc),
18384                             pipe_name(pipe));
18385         }
18386
18387         drm_connector_list_iter_begin(dev, &conn_iter);
18388         for_each_intel_connector_iter(connector, &conn_iter) {
18389                 if (connector->get_hw_state(connector)) {
18390                         struct intel_crtc_state *crtc_state;
18391                         struct intel_crtc *crtc;
18392
18393                         connector->base.dpms = DRM_MODE_DPMS_ON;
18394
18395                         encoder = intel_attached_encoder(connector);
18396                         connector->base.encoder = &encoder->base;
18397
18398                         crtc = to_intel_crtc(encoder->base.crtc);
18399                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18400
18401                         if (crtc_state && crtc_state->hw.active) {
18402                                 /*
18403                                  * This has to be done during hardware readout
18404                                  * because anything calling .crtc_disable may
18405                                  * rely on the connector_mask being accurate.
18406                                  */
18407                                 crtc_state->uapi.connector_mask |=
18408                                         drm_connector_mask(&connector->base);
18409                                 crtc_state->uapi.encoder_mask |=
18410                                         drm_encoder_mask(&encoder->base);
18411                         }
18412                 } else {
18413                         connector->base.dpms = DRM_MODE_DPMS_OFF;
18414                         connector->base.encoder = NULL;
18415                 }
18416                 drm_dbg_kms(&dev_priv->drm,
18417                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
18418                             connector->base.base.id, connector->base.name,
18419                             enableddisabled(connector->base.encoder));
18420         }
18421         drm_connector_list_iter_end(&conn_iter);
18422
18423         for_each_intel_crtc(dev, crtc) {
18424                 struct intel_bw_state *bw_state =
18425                         to_intel_bw_state(dev_priv->bw_obj.state);
18426                 struct intel_crtc_state *crtc_state =
18427                         to_intel_crtc_state(crtc->base.state);
18428                 struct intel_plane *plane;
18429                 int min_cdclk = 0;
18430
18431                 if (crtc_state->hw.active) {
18432                         struct drm_display_mode *mode = &crtc_state->hw.mode;
18433
18434                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18435                                                     crtc_state);
18436
18437                         *mode = crtc_state->hw.adjusted_mode;
18438                         mode->hdisplay = crtc_state->pipe_src_w;
18439                         mode->vdisplay = crtc_state->pipe_src_h;
18440
18441                         /*
18442                          * The initial mode needs to be set in order to keep
18443                          * the atomic core happy. It wants a valid mode if the
18444                          * crtc's enabled, so we do the above call.
18445                          *
18446                          * But we don't set all the derived state fully, hence
18447                          * set a flag to indicate that a full recalculation is
18448                          * needed on the next commit.
18449                          */
18450                         crtc_state->inherited = true;
18451
18452                         intel_crtc_compute_pixel_rate(crtc_state);
18453
18454                         intel_crtc_update_active_timings(crtc_state);
18455
18456                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
18457                 }
18458
18459                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18460                         const struct intel_plane_state *plane_state =
18461                                 to_intel_plane_state(plane->base.state);
18462
18463                         /*
18464                          * FIXME don't have the fb yet, so can't
18465                          * use intel_plane_data_rate() :(
18466                          */
18467                         if (plane_state->uapi.visible)
18468                                 crtc_state->data_rate[plane->id] =
18469                                         4 * crtc_state->pixel_rate;
18470                         /*
18471                          * FIXME don't have the fb yet, so can't
18472                          * use plane->min_cdclk() :(
18473                          */
18474                         if (plane_state->uapi.visible && plane->min_cdclk) {
18475                                 if (crtc_state->double_wide ||
18476                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18477                                         crtc_state->min_cdclk[plane->id] =
18478                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18479                                 else
18480                                         crtc_state->min_cdclk[plane->id] =
18481                                                 crtc_state->pixel_rate;
18482                         }
18483                         drm_dbg_kms(&dev_priv->drm,
18484                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
18485                                     plane->base.base.id, plane->base.name,
18486                                     crtc_state->min_cdclk[plane->id]);
18487                 }
18488
18489                 if (crtc_state->hw.active) {
18490                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18491                         if (drm_WARN_ON(dev, min_cdclk < 0))
18492                                 min_cdclk = 0;
18493                 }
18494
18495                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18496                 cdclk_state->min_voltage_level[crtc->pipe] =
18497                         crtc_state->min_voltage_level;
18498
18499                 intel_bw_crtc_update(bw_state, crtc_state);
18500
18501                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18502         }
18503 }
18504
18505 static void
18506 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18507 {
18508         struct intel_encoder *encoder;
18509
18510         for_each_intel_encoder(&dev_priv->drm, encoder) {
18511                 struct intel_crtc_state *crtc_state;
18512
18513                 if (!encoder->get_power_domains)
18514                         continue;
18515
18516                 /*
18517                  * MST-primary and inactive encoders don't have a crtc state
18518                  * and neither of these require any power domain references.
18519                  */
18520                 if (!encoder->base.crtc)
18521                         continue;
18522
18523                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18524                 encoder->get_power_domains(encoder, crtc_state);
18525         }
18526 }
18527
18528 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18529 {
18530         /*
18531          * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18532          * Also known as Wa_14010480278.
18533          */
18534         if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18535                 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18536                                intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18537
18538         if (IS_HASWELL(dev_priv)) {
18539                 /*
18540                  * WaRsPkgCStateDisplayPMReq:hsw
18541                  * System hang if this isn't done before disabling all planes!
18542                  */
18543                 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18544                                intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18545         }
18546 }
18547
18548 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18549                                        enum port port, i915_reg_t hdmi_reg)
18550 {
18551         u32 val = intel_de_read(dev_priv, hdmi_reg);
18552
18553         if (val & SDVO_ENABLE ||
18554             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18555                 return;
18556
18557         drm_dbg_kms(&dev_priv->drm,
18558                     "Sanitizing transcoder select for HDMI %c\n",
18559                     port_name(port));
18560
18561         val &= ~SDVO_PIPE_SEL_MASK;
18562         val |= SDVO_PIPE_SEL(PIPE_A);
18563
18564         intel_de_write(dev_priv, hdmi_reg, val);
18565 }
18566
18567 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18568                                      enum port port, i915_reg_t dp_reg)
18569 {
18570         u32 val = intel_de_read(dev_priv, dp_reg);
18571
18572         if (val & DP_PORT_EN ||
18573             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18574                 return;
18575
18576         drm_dbg_kms(&dev_priv->drm,
18577                     "Sanitizing transcoder select for DP %c\n",
18578                     port_name(port));
18579
18580         val &= ~DP_PIPE_SEL_MASK;
18581         val |= DP_PIPE_SEL(PIPE_A);
18582
18583         intel_de_write(dev_priv, dp_reg, val);
18584 }
18585
18586 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18587 {
18588         /*
18589          * The BIOS may select transcoder B on some of the PCH
18590          * ports even it doesn't enable the port. This would trip
18591          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18592          * Sanitize the transcoder select bits to prevent that. We
18593          * assume that the BIOS never actually enabled the port,
18594          * because if it did we'd actually have to toggle the port
18595          * on and back off to make the transcoder A select stick
18596          * (see. intel_dp_link_down(), intel_disable_hdmi(),
18597          * intel_disable_sdvo()).
18598          */
18599         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18600         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18601         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18602
18603         /* PCH SDVOB multiplex with HDMIB */
18604         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18605         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18606         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18607 }
18608
18609 /* Scan out the current hw modeset state,
18610  * and sanitizes it to the current state
18611  */
18612 static void
18613 intel_modeset_setup_hw_state(struct drm_device *dev,
18614                              struct drm_modeset_acquire_ctx *ctx)
18615 {
18616         struct drm_i915_private *dev_priv = to_i915(dev);
18617         struct intel_encoder *encoder;
18618         struct intel_crtc *crtc;
18619         intel_wakeref_t wakeref;
18620
18621         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
18622
18623         intel_early_display_was(dev_priv);
18624         intel_modeset_readout_hw_state(dev);
18625
18626         /* HW state is read out, now we need to sanitize this mess. */
18627
18628         /* Sanitize the TypeC port mode upfront, encoders depend on this */
18629         for_each_intel_encoder(dev, encoder) {
18630                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
18631
18632                 /* We need to sanitize only the MST primary port. */
18633                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
18634                     intel_phy_is_tc(dev_priv, phy))
18635                         intel_tc_port_sanitize(enc_to_dig_port(encoder));
18636         }
18637
18638         get_encoder_power_domains(dev_priv);
18639
18640         if (HAS_PCH_IBX(dev_priv))
18641                 ibx_sanitize_pch_ports(dev_priv);
18642
18643         /*
18644          * intel_sanitize_plane_mapping() may need to do vblank
18645          * waits, so we need vblank interrupts restored beforehand.
18646          */
18647         for_each_intel_crtc(&dev_priv->drm, crtc) {
18648                 struct intel_crtc_state *crtc_state =
18649                         to_intel_crtc_state(crtc->base.state);
18650
18651                 drm_crtc_vblank_reset(&crtc->base);
18652
18653                 if (crtc_state->hw.active)
18654                         intel_crtc_vblank_on(crtc_state);
18655         }
18656
18657         intel_sanitize_plane_mapping(dev_priv);
18658
18659         for_each_intel_encoder(dev, encoder)
18660                 intel_sanitize_encoder(encoder);
18661
18662         for_each_intel_crtc(&dev_priv->drm, crtc) {
18663                 struct intel_crtc_state *crtc_state =
18664                         to_intel_crtc_state(crtc->base.state);
18665
18666                 intel_sanitize_crtc(crtc, ctx);
18667                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
18668         }
18669
18670         intel_modeset_update_connector_atomic_state(dev);
18671
18672         intel_dpll_sanitize_state(dev_priv);
18673
18674         if (IS_G4X(dev_priv)) {
18675                 g4x_wm_get_hw_state(dev_priv);
18676                 g4x_wm_sanitize(dev_priv);
18677         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
18678                 vlv_wm_get_hw_state(dev_priv);
18679                 vlv_wm_sanitize(dev_priv);
18680         } else if (INTEL_GEN(dev_priv) >= 9) {
18681                 skl_wm_get_hw_state(dev_priv);
18682         } else if (HAS_PCH_SPLIT(dev_priv)) {
18683                 ilk_wm_get_hw_state(dev_priv);
18684         }
18685
18686         for_each_intel_crtc(dev, crtc) {
18687                 struct intel_crtc_state *crtc_state =
18688                         to_intel_crtc_state(crtc->base.state);
18689                 u64 put_domains;
18690
18691                 put_domains = modeset_get_crtc_power_domains(crtc_state);
18692                 if (drm_WARN_ON(dev, put_domains))
18693                         modeset_put_power_domains(dev_priv, put_domains);
18694         }
18695
18696         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
18697 }
18698
18699 void intel_display_resume(struct drm_device *dev)
18700 {
18701         struct drm_i915_private *dev_priv = to_i915(dev);
18702         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
18703         struct drm_modeset_acquire_ctx ctx;
18704         int ret;
18705
18706         dev_priv->modeset_restore_state = NULL;
18707         if (state)
18708                 state->acquire_ctx = &ctx;
18709
18710         drm_modeset_acquire_init(&ctx, 0);
18711
18712         while (1) {
18713                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
18714                 if (ret != -EDEADLK)
18715                         break;
18716
18717                 drm_modeset_backoff(&ctx);
18718         }
18719
18720         if (!ret)
18721                 ret = __intel_display_resume(dev, state, &ctx);
18722
18723         intel_enable_ipc(dev_priv);
18724         drm_modeset_drop_locks(&ctx);
18725         drm_modeset_acquire_fini(&ctx);
18726
18727         if (ret)
18728                 drm_err(&dev_priv->drm,
18729                         "Restoring old state failed with %i\n", ret);
18730         if (state)
18731                 drm_atomic_state_put(state);
18732 }
18733
18734 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
18735 {
18736         struct intel_connector *connector;
18737         struct drm_connector_list_iter conn_iter;
18738
18739         /* Kill all the work that may have been queued by hpd. */
18740         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
18741         for_each_intel_connector_iter(connector, &conn_iter) {
18742                 if (connector->modeset_retry_work.func)
18743                         cancel_work_sync(&connector->modeset_retry_work);
18744                 if (connector->hdcp.shim) {
18745                         cancel_delayed_work_sync(&connector->hdcp.check_work);
18746                         cancel_work_sync(&connector->hdcp.prop_work);
18747                 }
18748         }
18749         drm_connector_list_iter_end(&conn_iter);
18750 }
18751
18752 /* part #1: call before irq uninstall */
18753 void intel_modeset_driver_remove(struct drm_i915_private *i915)
18754 {
18755         flush_workqueue(i915->flip_wq);
18756         flush_workqueue(i915->modeset_wq);
18757
18758         flush_work(&i915->atomic_helper.free_work);
18759         drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
18760 }
18761
18762 /* part #2: call after irq uninstall */
18763 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
18764 {
18765         /*
18766          * Due to the hpd irq storm handling the hotplug work can re-arm the
18767          * poll handlers. Hence disable polling after hpd handling is shut down.
18768          */
18769         intel_hpd_poll_fini(i915);
18770
18771         /*
18772          * MST topology needs to be suspended so we don't have any calls to
18773          * fbdev after it's finalized. MST will be destroyed later as part of
18774          * drm_mode_config_cleanup()
18775          */
18776         intel_dp_mst_suspend(i915);
18777
18778         /* poll work can call into fbdev, hence clean that up afterwards */
18779         intel_fbdev_fini(i915);
18780
18781         intel_unregister_dsm_handler();
18782
18783         intel_fbc_global_disable(i915);
18784
18785         /* flush any delayed tasks or pending work */
18786         flush_scheduled_work();
18787
18788         intel_hdcp_component_fini(i915);
18789
18790         intel_mode_config_cleanup(i915);
18791
18792         intel_overlay_cleanup(i915);
18793
18794         intel_gmbus_teardown(i915);
18795
18796         destroy_workqueue(i915->flip_wq);
18797         destroy_workqueue(i915->modeset_wq);
18798
18799         intel_fbc_cleanup_cfb(i915);
18800 }
18801
18802 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
18803
18804 struct intel_display_error_state {
18805
18806         u32 power_well_driver;
18807
18808         struct intel_cursor_error_state {
18809                 u32 control;
18810                 u32 position;
18811                 u32 base;
18812                 u32 size;
18813         } cursor[I915_MAX_PIPES];
18814
18815         struct intel_pipe_error_state {
18816                 bool power_domain_on;
18817                 u32 source;
18818                 u32 stat;
18819         } pipe[I915_MAX_PIPES];
18820
18821         struct intel_plane_error_state {
18822                 u32 control;
18823                 u32 stride;
18824                 u32 size;
18825                 u32 pos;
18826                 u32 addr;
18827                 u32 surface;
18828                 u32 tile_offset;
18829         } plane[I915_MAX_PIPES];
18830
18831         struct intel_transcoder_error_state {
18832                 bool available;
18833                 bool power_domain_on;
18834                 enum transcoder cpu_transcoder;
18835
18836                 u32 conf;
18837
18838                 u32 htotal;
18839                 u32 hblank;
18840                 u32 hsync;
18841                 u32 vtotal;
18842                 u32 vblank;
18843                 u32 vsync;
18844         } transcoder[5];
18845 };
18846
18847 struct intel_display_error_state *
18848 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18849 {
18850         struct intel_display_error_state *error;
18851         int transcoders[] = {
18852                 TRANSCODER_A,
18853                 TRANSCODER_B,
18854                 TRANSCODER_C,
18855                 TRANSCODER_D,
18856                 TRANSCODER_EDP,
18857         };
18858         int i;
18859
18860         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
18861
18862         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
18863                 return NULL;
18864
18865         error = kzalloc(sizeof(*error), GFP_ATOMIC);
18866         if (error == NULL)
18867                 return NULL;
18868
18869         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18870                 error->power_well_driver = intel_de_read(dev_priv,
18871                                                          HSW_PWR_WELL_CTL2);
18872
18873         for_each_pipe(dev_priv, i) {
18874                 error->pipe[i].power_domain_on =
18875                         __intel_display_power_is_enabled(dev_priv,
18876                                                          POWER_DOMAIN_PIPE(i));
18877                 if (!error->pipe[i].power_domain_on)
18878                         continue;
18879
18880                 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
18881                 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
18882                 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
18883
18884                 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
18885                 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
18886                 if (INTEL_GEN(dev_priv) <= 3) {
18887                         error->plane[i].size = intel_de_read(dev_priv,
18888                                                              DSPSIZE(i));
18889                         error->plane[i].pos = intel_de_read(dev_priv,
18890                                                             DSPPOS(i));
18891                 }
18892                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18893                         error->plane[i].addr = intel_de_read(dev_priv,
18894                                                              DSPADDR(i));
18895                 if (INTEL_GEN(dev_priv) >= 4) {
18896                         error->plane[i].surface = intel_de_read(dev_priv,
18897                                                                 DSPSURF(i));
18898                         error->plane[i].tile_offset = intel_de_read(dev_priv,
18899                                                                     DSPTILEOFF(i));
18900                 }
18901
18902                 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
18903
18904                 if (HAS_GMCH(dev_priv))
18905                         error->pipe[i].stat = intel_de_read(dev_priv,
18906                                                             PIPESTAT(i));
18907         }
18908
18909         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18910                 enum transcoder cpu_transcoder = transcoders[i];
18911
18912                 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
18913                         continue;
18914
18915                 error->transcoder[i].available = true;
18916                 error->transcoder[i].power_domain_on =
18917                         __intel_display_power_is_enabled(dev_priv,
18918                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18919                 if (!error->transcoder[i].power_domain_on)
18920                         continue;
18921
18922                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18923
18924                 error->transcoder[i].conf = intel_de_read(dev_priv,
18925                                                           PIPECONF(cpu_transcoder));
18926                 error->transcoder[i].htotal = intel_de_read(dev_priv,
18927                                                             HTOTAL(cpu_transcoder));
18928                 error->transcoder[i].hblank = intel_de_read(dev_priv,
18929                                                             HBLANK(cpu_transcoder));
18930                 error->transcoder[i].hsync = intel_de_read(dev_priv,
18931                                                            HSYNC(cpu_transcoder));
18932                 error->transcoder[i].vtotal = intel_de_read(dev_priv,
18933                                                             VTOTAL(cpu_transcoder));
18934                 error->transcoder[i].vblank = intel_de_read(dev_priv,
18935                                                             VBLANK(cpu_transcoder));
18936                 error->transcoder[i].vsync = intel_de_read(dev_priv,
18937                                                            VSYNC(cpu_transcoder));
18938         }
18939
18940         return error;
18941 }
18942
18943 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18944
18945 void
18946 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18947                                 struct intel_display_error_state *error)
18948 {
18949         struct drm_i915_private *dev_priv = m->i915;
18950         int i;
18951
18952         if (!error)
18953                 return;
18954
18955         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18956         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18957                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18958                            error->power_well_driver);
18959         for_each_pipe(dev_priv, i) {
18960                 err_printf(m, "Pipe [%d]:\n", i);
18961                 err_printf(m, "  Power: %s\n",
18962                            onoff(error->pipe[i].power_domain_on));
18963                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18964                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18965
18966                 err_printf(m, "Plane [%d]:\n", i);
18967                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18968                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18969                 if (INTEL_GEN(dev_priv) <= 3) {
18970                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18971                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18972                 }
18973                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18974                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18975                 if (INTEL_GEN(dev_priv) >= 4) {
18976                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18977                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18978                 }
18979
18980                 err_printf(m, "Cursor [%d]:\n", i);
18981                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18982                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18983                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18984         }
18985
18986         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18987                 if (!error->transcoder[i].available)
18988                         continue;
18989
18990                 err_printf(m, "CPU transcoder: %s\n",
18991                            transcoder_name(error->transcoder[i].cpu_transcoder));
18992                 err_printf(m, "  Power: %s\n",
18993                            onoff(error->transcoder[i].power_domain_on));
18994                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
18995                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18996                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18997                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18998                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18999                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
19000                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
19001         }
19002 }
19003
19004 #endif