1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2019 Intel Corporation
11 #include "i915_trace.h"
12 #include "intel_uncore.h"
15 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
17 return intel_uncore_read(&i915->uncore, reg);
21 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
23 intel_uncore_posting_read(&i915->uncore, reg);
27 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
29 intel_uncore_write(&i915->uncore, reg, val);
33 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
35 intel_uncore_rmw(&i915->uncore, reg, clear, set);
39 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
40 u32 mask, u32 value, unsigned int timeout)
42 return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
46 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
47 u32 mask, unsigned int timeout)
49 return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
53 intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
54 u32 mask, unsigned int timeout)
56 return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
60 * Unlocked mmio-accessors, think carefully before using these.
62 * Certain architectures will die if the same cacheline is concurrently accessed
63 * by different clients (e.g. on Ivybridge). Access to registers should
64 * therefore generally be serialised, by either the dev_priv->uncore.lock or
65 * a more localised lock guarding all access to that bank of registers.
68 intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
72 val = intel_uncore_read_fw(&i915->uncore, reg);
73 trace_i915_reg_rw(false, reg, val, sizeof(val), true);
79 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
81 trace_i915_reg_rw(true, reg, val, sizeof(val), true);
82 intel_uncore_write_fw(&i915->uncore, reg, val);
85 #endif /* __INTEL_DE_H__ */