drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_dp.h"
  36 #include "intel_dp_link_training.h"
  37 #include "intel_dpio_phy.h"
  38 #include "intel_drv.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_vdsc.h"
  49
  50 struct ddi_buf_trans {
  51         u32 trans1;     /* balance leg enable, de-emph level */
  52         u32 trans2;     /* vref sel, vswing */
  53         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  54 };
  55
  56 static const u8 index_to_dp_signal_levels[] = {
  57         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  58         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  59         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  60         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  61         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  62         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  63         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  64         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  67 };
  68
  69 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  70  * them for both DP and FDI transports, allowing those ports to
  71  * automatically adapt to HDMI connections as well
  72  */
  73 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  74         { 0x00FFFFFF, 0x0006000E, 0x0 },
  75         { 0x00D75FFF, 0x0005000A, 0x0 },
  76         { 0x00C30FFF, 0x00040006, 0x0 },
  77         { 0x80AAAFFF, 0x000B0000, 0x0 },
  78         { 0x00FFFFFF, 0x0005000A, 0x0 },
  79         { 0x00D75FFF, 0x000C0004, 0x0 },
  80         { 0x80C30FFF, 0x000B0000, 0x0 },
  81         { 0x00FFFFFF, 0x00040006, 0x0 },
  82         { 0x80D75FFF, 0x000B0000, 0x0 },
  83 };
  84
  85 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  86         { 0x00FFFFFF, 0x0007000E, 0x0 },
  87         { 0x00D75FFF, 0x000F000A, 0x0 },
  88         { 0x00C30FFF, 0x00060006, 0x0 },
  89         { 0x00AAAFFF, 0x001E0000, 0x0 },
  90         { 0x00FFFFFF, 0x000F000A, 0x0 },
  91         { 0x00D75FFF, 0x00160004, 0x0 },
  92         { 0x00C30FFF, 0x001E0000, 0x0 },
  93         { 0x00FFFFFF, 0x00060006, 0x0 },
  94         { 0x00D75FFF, 0x001E0000, 0x0 },
  95 };
  96
  97 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  98                                         /* Idx  NT mV d T mV d  db      */
  99         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 100         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 101         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 102         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 103         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 104         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 105         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 106         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 107         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 108         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 109         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 110         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 111 };
 112
 113 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 114         { 0x00FFFFFF, 0x00000012, 0x0 },
 115         { 0x00EBAFFF, 0x00020011, 0x0 },
 116         { 0x00C71FFF, 0x0006000F, 0x0 },
 117         { 0x00AAAFFF, 0x000E000A, 0x0 },
 118         { 0x00FFFFFF, 0x00020011, 0x0 },
 119         { 0x00DB6FFF, 0x0005000F, 0x0 },
 120         { 0x00BEEFFF, 0x000A000C, 0x0 },
 121         { 0x00FFFFFF, 0x0005000F, 0x0 },
 122         { 0x00DB6FFF, 0x000A000C, 0x0 },
 123 };
 124
 125 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 126         { 0x00FFFFFF, 0x0007000E, 0x0 },
 127         { 0x00D75FFF, 0x000E000A, 0x0 },
 128         { 0x00BEFFFF, 0x00140006, 0x0 },
 129         { 0x80B2CFFF, 0x001B0002, 0x0 },
 130         { 0x00FFFFFF, 0x000E000A, 0x0 },
 131         { 0x00DB6FFF, 0x00160005, 0x0 },
 132         { 0x80C71FFF, 0x001A0002, 0x0 },
 133         { 0x00F7DFFF, 0x00180004, 0x0 },
 134         { 0x80D75FFF, 0x001B0002, 0x0 },
 135 };
 136
 137 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 138         { 0x00FFFFFF, 0x0001000E, 0x0 },
 139         { 0x00D75FFF, 0x0004000A, 0x0 },
 140         { 0x00C30FFF, 0x00070006, 0x0 },
 141         { 0x00AAAFFF, 0x000C0000, 0x0 },
 142         { 0x00FFFFFF, 0x0004000A, 0x0 },
 143         { 0x00D75FFF, 0x00090004, 0x0 },
 144         { 0x00C30FFF, 0x000C0000, 0x0 },
 145         { 0x00FFFFFF, 0x00070006, 0x0 },
 146         { 0x00D75FFF, 0x000C0000, 0x0 },
 147 };
 148
 149 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 150                                         /* Idx  NT mV d T mV df db      */
 151         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 152         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 153         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 154         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 155         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 156         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 157         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 158         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 159         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 160         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 161 };
 162
 163 /* Skylake H and S */
 164 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 165         { 0x00002016, 0x000000A0, 0x0 },
 166         { 0x00005012, 0x0000009B, 0x0 },
 167         { 0x00007011, 0x00000088, 0x0 },
 168         { 0x80009010, 0x000000C0, 0x1 },
 169         { 0x00002016, 0x0000009B, 0x0 },
 170         { 0x00005012, 0x00000088, 0x0 },
 171         { 0x80007011, 0x000000C0, 0x1 },
 172         { 0x00002016, 0x000000DF, 0x0 },
 173         { 0x80005012, 0x000000C0, 0x1 },
 174 };
 175
 176 /* Skylake U */
 177 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 178         { 0x0000201B, 0x000000A2, 0x0 },
 179         { 0x00005012, 0x00000088, 0x0 },
 180         { 0x80007011, 0x000000CD, 0x1 },
 181         { 0x80009010, 0x000000C0, 0x1 },
 182         { 0x0000201B, 0x0000009D, 0x0 },
 183         { 0x80005012, 0x000000C0, 0x1 },
 184         { 0x80007011, 0x000000C0, 0x1 },
 185         { 0x00002016, 0x00000088, 0x0 },
 186         { 0x80005012, 0x000000C0, 0x1 },
 187 };
 188
 189 /* Skylake Y */
 190 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 191         { 0x00000018, 0x000000A2, 0x0 },
 192         { 0x00005012, 0x00000088, 0x0 },
 193         { 0x80007011, 0x000000CD, 0x3 },
 194         { 0x80009010, 0x000000C0, 0x3 },
 195         { 0x00000018, 0x0000009D, 0x0 },
 196         { 0x80005012, 0x000000C0, 0x3 },
 197         { 0x80007011, 0x000000C0, 0x3 },
 198         { 0x00000018, 0x00000088, 0x0 },
 199         { 0x80005012, 0x000000C0, 0x3 },
 200 };
 201
 202 /* Kabylake H and S */
 203 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 204         { 0x00002016, 0x000000A0, 0x0 },
 205         { 0x00005012, 0x0000009B, 0x0 },
 206         { 0x00007011, 0x00000088, 0x0 },
 207         { 0x80009010, 0x000000C0, 0x1 },
 208         { 0x00002016, 0x0000009B, 0x0 },
 209         { 0x00005012, 0x00000088, 0x0 },
 210         { 0x80007011, 0x000000C0, 0x1 },
 211         { 0x00002016, 0x00000097, 0x0 },
 212         { 0x80005012, 0x000000C0, 0x1 },
 213 };
 214
 215 /* Kabylake U */
 216 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 217         { 0x0000201B, 0x000000A1, 0x0 },
 218         { 0x00005012, 0x00000088, 0x0 },
 219         { 0x80007011, 0x000000CD, 0x3 },
 220         { 0x80009010, 0x000000C0, 0x3 },
 221         { 0x0000201B, 0x0000009D, 0x0 },
 222         { 0x80005012, 0x000000C0, 0x3 },
 223         { 0x80007011, 0x000000C0, 0x3 },
 224         { 0x00002016, 0x0000004F, 0x0 },
 225         { 0x80005012, 0x000000C0, 0x3 },
 226 };
 227
 228 /* Kabylake Y */
 229 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 230         { 0x00001017, 0x000000A1, 0x0 },
 231         { 0x00005012, 0x00000088, 0x0 },
 232         { 0x80007011, 0x000000CD, 0x3 },
 233         { 0x8000800F, 0x000000C0, 0x3 },
 234         { 0x00001017, 0x0000009D, 0x0 },
 235         { 0x80005012, 0x000000C0, 0x3 },
 236         { 0x80007011, 0x000000C0, 0x3 },
 237         { 0x00001017, 0x0000004C, 0x0 },
 238         { 0x80005012, 0x000000C0, 0x3 },
 239 };
 240
 241 /*
 242  * Skylake/Kabylake H and S
 243  * eDP 1.4 low vswing translation parameters
 244  */
 245 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 246         { 0x00000018, 0x000000A8, 0x0 },
 247         { 0x00004013, 0x000000A9, 0x0 },
 248         { 0x00007011, 0x000000A2, 0x0 },
 249         { 0x00009010, 0x0000009C, 0x0 },
 250         { 0x00000018, 0x000000A9, 0x0 },
 251         { 0x00006013, 0x000000A2, 0x0 },
 252         { 0x00007011, 0x000000A6, 0x0 },
 253         { 0x00000018, 0x000000AB, 0x0 },
 254         { 0x00007013, 0x0000009F, 0x0 },
 255         { 0x00000018, 0x000000DF, 0x0 },
 256 };
 257
 258 /*
 259  * Skylake/Kabylake U
 260  * eDP 1.4 low vswing translation parameters
 261  */
 262 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 263         { 0x00000018, 0x000000A8, 0x0 },
 264         { 0x00004013, 0x000000A9, 0x0 },
 265         { 0x00007011, 0x000000A2, 0x0 },
 266         { 0x00009010, 0x0000009C, 0x0 },
 267         { 0x00000018, 0x000000A9, 0x0 },
 268         { 0x00006013, 0x000000A2, 0x0 },
 269         { 0x00007011, 0x000000A6, 0x0 },
 270         { 0x00002016, 0x000000AB, 0x0 },
 271         { 0x00005013, 0x0000009F, 0x0 },
 272         { 0x00000018, 0x000000DF, 0x0 },
 273 };
 274
 275 /*
 276  * Skylake/Kabylake Y
 277  * eDP 1.4 low vswing translation parameters
 278  */
 279 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 280         { 0x00000018, 0x000000A8, 0x0 },
 281         { 0x00004013, 0x000000AB, 0x0 },
 282         { 0x00007011, 0x000000A4, 0x0 },
 283         { 0x00009010, 0x000000DF, 0x0 },
 284         { 0x00000018, 0x000000AA, 0x0 },
 285         { 0x00006013, 0x000000A4, 0x0 },
 286         { 0x00007011, 0x0000009D, 0x0 },
 287         { 0x00000018, 0x000000A0, 0x0 },
 288         { 0x00006012, 0x000000DF, 0x0 },
 289         { 0x00000018, 0x0000008A, 0x0 },
 290 };
 291
 292 /* Skylake/Kabylake U, H and S */
 293 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 294         { 0x00000018, 0x000000AC, 0x0 },
 295         { 0x00005012, 0x0000009D, 0x0 },
 296         { 0x00007011, 0x00000088, 0x0 },
 297         { 0x00000018, 0x000000A1, 0x0 },
 298         { 0x00000018, 0x00000098, 0x0 },
 299         { 0x00004013, 0x00000088, 0x0 },
 300         { 0x80006012, 0x000000CD, 0x1 },
 301         { 0x00000018, 0x000000DF, 0x0 },
 302         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 303         { 0x80003015, 0x000000C0, 0x1 },
 304         { 0x80000018, 0x000000C0, 0x1 },
 305 };
 306
 307 /* Skylake/Kabylake Y */
 308 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 309         { 0x00000018, 0x000000A1, 0x0 },
 310         { 0x00005012, 0x000000DF, 0x0 },
 311         { 0x80007011, 0x000000CB, 0x3 },
 312         { 0x00000018, 0x000000A4, 0x0 },
 313         { 0x00000018, 0x0000009D, 0x0 },
 314         { 0x00004013, 0x00000080, 0x0 },
 315         { 0x80006013, 0x000000C0, 0x3 },
 316         { 0x00000018, 0x0000008A, 0x0 },
 317         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 318         { 0x80003015, 0x000000C0, 0x3 },
 319         { 0x80000018, 0x000000C0, 0x3 },
 320 };
 321
 322 struct bxt_ddi_buf_trans {
 323         u8 margin;      /* swing value */
 324         u8 scale;       /* scale value */
 325         u8 enable;      /* scale enable */
 326         u8 deemphasis;
 327 };
 328
 329 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 330                                         /* Idx  NT mV diff      db  */
 331         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 332         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 333         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 334         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 335         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 336         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 337         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 338         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 339         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 340         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 341 };
 342
 343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 344                                         /* Idx  NT mV diff      db  */
 345         { 26, 0, 0, 128, },     /* 0:   200             0   */
 346         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 347         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 348         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 349         { 32, 0, 0, 128, },     /* 4:   250             0   */
 350         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 351         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 352         { 43, 0, 0, 128, },     /* 7:   300             0   */
 353         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 354         { 48, 0, 0, 128, },     /* 9:   300             0   */
 355 };
 356
 357 /* BSpec has 2 recommended values - entries 0 and 8.
 358  * Using the entry with higher vswing.
 359  */
 360 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 361                                         /* Idx  NT mV diff      db  */
 362         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 363         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 364         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 365         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 366         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 367         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 368         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 369         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 370         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 371         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 372 };
 373
 374 struct cnl_ddi_buf_trans {
 375         u8 dw2_swing_sel;
 376         u8 dw7_n_scalar;
 377         u8 dw4_cursor_coeff;
 378         u8 dw4_post_cursor_2;
 379         u8 dw4_post_cursor_1;
 380 };
 381
 382 /* Voltage Swing Programming for VccIO 0.85V for DP */
 383 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 384                                                 /* NT mV Trans mV db    */
 385         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 386         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 387         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 388         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 389         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 390         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 391         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 392         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 393         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 394         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 395 };
 396
 397 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 398 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 399                                                 /* NT mV Trans mV db    */
 400         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 401         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 402         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 403         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 404         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 405         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 406         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 407 };
 408
 409 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 410 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 411                                                 /* NT mV Trans mV db    */
 412         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 413         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 414         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 415         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 416         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 417         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 418         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 419         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 420         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 421 };
 422
 423 /* Voltage Swing Programming for VccIO 0.95V for DP */
 424 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 425                                                 /* NT mV Trans mV db    */
 426         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 427         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 428         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 429         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 430         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 431         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 432         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 433         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 434         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 435         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 436 };
 437
 438 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 439 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 440                                                 /* NT mV Trans mV db    */
 441         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 442         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 443         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 444         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 445         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 446         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 447         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 448         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 449         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 450         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 451         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 452 };
 453
 454 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 455 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 456                                                 /* NT mV Trans mV db    */
 457         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 458         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 459         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 460         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 461         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 462         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 463         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 464         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 465         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 466         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 467 };
 468
 469 /* Voltage Swing Programming for VccIO 1.05V for DP */
 470 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 471                                                 /* NT mV Trans mV db    */
 472         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 473         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 474         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 475         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 476         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 477         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 478         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 479         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 480         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 481         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 482 };
 483
 484 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 485 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 486                                                 /* NT mV Trans mV db    */
 487         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 488         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 489         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 490         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 491         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 492         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 493         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 494         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 495         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 496         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 497         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 498 };
 499
 500 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 501 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 502                                                 /* NT mV Trans mV db    */
 503         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 504         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 505         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 506         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 507         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 508         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 509         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 510         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 511         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 512 };
 513
 514 /* icl_combo_phy_ddi_translations */
 515 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 516                                                 /* NT mV Trans mV db    */
 517         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 518         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 519         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 520         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 521         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 522         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 523         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 524         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 525         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 526         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 527 };
 528
 529 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 530                                                 /* NT mV Trans mV db    */
 531         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 532         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 533         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 534         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 535         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 536         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 537         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 538         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 539         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 540         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 541 };
 542
 543 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 544                                                 /* NT mV Trans mV db    */
 545         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 546         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 547         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 548         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 549         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 550         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 551         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 552         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 553         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 554         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 555 };
 556
 557 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 558                                                 /* NT mV Trans mV db    */
 559         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 560         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 561         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 562         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 563         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 564         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 565         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 566 };
 567
 568 struct icl_mg_phy_ddi_buf_trans {
 569         u32 cri_txdeemph_override_5_0;
 570         u32 cri_txdeemph_override_11_6;
 571         u32 cri_txdeemph_override_17_12;
 572 };
 573
 574 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 575                                 /* Voltage swing  pre-emphasis */
 576         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 577         { 0x0, 0x23, 0x08 },    /* 0              1   */
 578         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 579         { 0x0, 0x00, 0x00 },    /* 0              3   */
 580         { 0x0, 0x23, 0x00 },    /* 1              0   */
 581         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 582         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 583         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 584         { 0x0, 0x33, 0x0C },    /* 2              1   */
 585         { 0x0, 0x00, 0x00 },    /* 3              0   */
 586 };
 587
 588 static const struct ddi_buf_trans *
 589 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 590 {
 591         if (dev_priv->vbt.edp.low_vswing) {
 592                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 593                 return bdw_ddi_translations_edp;
 594         } else {
 595                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 596                 return bdw_ddi_translations_dp;
 597         }
 598 }
 599
 600 static const struct ddi_buf_trans *
 601 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 602 {
 603         if (IS_SKL_ULX(dev_priv)) {
 604                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 605                 return skl_y_ddi_translations_dp;
 606         } else if (IS_SKL_ULT(dev_priv)) {
 607                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 608                 return skl_u_ddi_translations_dp;
 609         } else {
 610                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 611                 return skl_ddi_translations_dp;
 612         }
 613 }
 614
 615 static const struct ddi_buf_trans *
 616 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 619                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 620                 return kbl_y_ddi_translations_dp;
 621         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 622                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 623                 return kbl_u_ddi_translations_dp;
 624         } else {
 625                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 626                 return kbl_ddi_translations_dp;
 627         }
 628 }
 629
 630 static const struct ddi_buf_trans *
 631 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 632 {
 633         if (dev_priv->vbt.edp.low_vswing) {
 634                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 635                     IS_CFL_ULX(dev_priv)) {
 636                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 637                         return skl_y_ddi_translations_edp;
 638                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 639                            IS_CFL_ULT(dev_priv)) {
 640                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 641                         return skl_u_ddi_translations_edp;
 642                 } else {
 643                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 644                         return skl_ddi_translations_edp;
 645                 }
 646         }
 647
 648         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 649                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 650         else
 651                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 652 }
 653
 654 static const struct ddi_buf_trans *
 655 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 656 {
 657         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 658             IS_CFL_ULX(dev_priv)) {
 659                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 660                 return skl_y_ddi_translations_hdmi;
 661         } else {
 662                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 663                 return skl_ddi_translations_hdmi;
 664         }
 665 }
 666
 667 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 668 {
 669         /* Only DDIA and DDIE can select the 10th register with DP */
 670         if (port == PORT_A || port == PORT_E)
 671                 return min(n_entries, 10);
 672         else
 673                 return min(n_entries, 9);
 674 }
 675
 676 static const struct ddi_buf_trans *
 677 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 678                            enum port port, int *n_entries)
 679 {
 680         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 681                 const struct ddi_buf_trans *ddi_translations =
 682                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 683                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 684                 return ddi_translations;
 685         } else if (IS_SKYLAKE(dev_priv)) {
 686                 const struct ddi_buf_trans *ddi_translations =
 687                         skl_get_buf_trans_dp(dev_priv, n_entries);
 688                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 689                 return ddi_translations;
 690         } else if (IS_BROADWELL(dev_priv)) {
 691                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 692                 return  bdw_ddi_translations_dp;
 693         } else if (IS_HASWELL(dev_priv)) {
 694                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 695                 return hsw_ddi_translations_dp;
 696         }
 697
 698         *n_entries = 0;
 699         return NULL;
 700 }
 701
 702 static const struct ddi_buf_trans *
 703 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 704                             enum port port, int *n_entries)
 705 {
 706         if (IS_GEN9_BC(dev_priv)) {
 707                 const struct ddi_buf_trans *ddi_translations =
 708                         skl_get_buf_trans_edp(dev_priv, n_entries);
 709                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 710                 return ddi_translations;
 711         } else if (IS_BROADWELL(dev_priv)) {
 712                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 713         } else if (IS_HASWELL(dev_priv)) {
 714                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 715                 return hsw_ddi_translations_dp;
 716         }
 717
 718         *n_entries = 0;
 719         return NULL;
 720 }
 721
 722 static const struct ddi_buf_trans *
 723 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 724                             int *n_entries)
 725 {
 726         if (IS_BROADWELL(dev_priv)) {
 727                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 728                 return bdw_ddi_translations_fdi;
 729         } else if (IS_HASWELL(dev_priv)) {
 730                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 731                 return hsw_ddi_translations_fdi;
 732         }
 733
 734         *n_entries = 0;
 735         return NULL;
 736 }
 737
 738 static const struct ddi_buf_trans *
 739 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 740                              int *n_entries)
 741 {
 742         if (IS_GEN9_BC(dev_priv)) {
 743                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 744         } else if (IS_BROADWELL(dev_priv)) {
 745                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 746                 return bdw_ddi_translations_hdmi;
 747         } else if (IS_HASWELL(dev_priv)) {
 748                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 749                 return hsw_ddi_translations_hdmi;
 750         }
 751
 752         *n_entries = 0;
 753         return NULL;
 754 }
 755
 756 static const struct bxt_ddi_buf_trans *
 757 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 758 {
 759         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 760         return bxt_ddi_translations_dp;
 761 }
 762
 763 static const struct bxt_ddi_buf_trans *
 764 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 765 {
 766         if (dev_priv->vbt.edp.low_vswing) {
 767                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 768                 return bxt_ddi_translations_edp;
 769         }
 770
 771         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 772 }
 773
 774 static const struct bxt_ddi_buf_trans *
 775 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 776 {
 777         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 778         return bxt_ddi_translations_hdmi;
 779 }
 780
 781 static const struct cnl_ddi_buf_trans *
 782 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 783 {
 784         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 785
 786         if (voltage == VOLTAGE_INFO_0_85V) {
 787                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 788                 return cnl_ddi_translations_hdmi_0_85V;
 789         } else if (voltage == VOLTAGE_INFO_0_95V) {
 790                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 791                 return cnl_ddi_translations_hdmi_0_95V;
 792         } else if (voltage == VOLTAGE_INFO_1_05V) {
 793                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 794                 return cnl_ddi_translations_hdmi_1_05V;
 795         } else {
 796                 *n_entries = 1; /* shut up gcc */
 797                 MISSING_CASE(voltage);
 798         }
 799         return NULL;
 800 }
 801
 802 static const struct cnl_ddi_buf_trans *
 803 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 804 {
 805         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 806
 807         if (voltage == VOLTAGE_INFO_0_85V) {
 808                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 809                 return cnl_ddi_translations_dp_0_85V;
 810         } else if (voltage == VOLTAGE_INFO_0_95V) {
 811                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 812                 return cnl_ddi_translations_dp_0_95V;
 813         } else if (voltage == VOLTAGE_INFO_1_05V) {
 814                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 815                 return cnl_ddi_translations_dp_1_05V;
 816         } else {
 817                 *n_entries = 1; /* shut up gcc */
 818                 MISSING_CASE(voltage);
 819         }
 820         return NULL;
 821 }
 822
 823 static const struct cnl_ddi_buf_trans *
 824 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 825 {
 826         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 827
 828         if (dev_priv->vbt.edp.low_vswing) {
 829                 if (voltage == VOLTAGE_INFO_0_85V) {
 830                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 831                         return cnl_ddi_translations_edp_0_85V;
 832                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 833                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 834                         return cnl_ddi_translations_edp_0_95V;
 835                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 836                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 837                         return cnl_ddi_translations_edp_1_05V;
 838                 } else {
 839                         *n_entries = 1; /* shut up gcc */
 840                         MISSING_CASE(voltage);
 841                 }
 842                 return NULL;
 843         } else {
 844                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 845         }
 846 }
 847
 848 static const struct cnl_ddi_buf_trans *
 849 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 850                         int type, int rate, int *n_entries)
 851 {
 852         if (type == INTEL_OUTPUT_HDMI) {
 853                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 854                 return icl_combo_phy_ddi_translations_hdmi;
 855         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 856                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 857                 return icl_combo_phy_ddi_translations_edp_hbr3;
 858         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 859                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 860                 return icl_combo_phy_ddi_translations_edp_hbr2;
 861         }
 862
 863         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 864         return icl_combo_phy_ddi_translations_dp_hbr2;
 865 }
 866
 867 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 868 {
 869         int n_entries, level, default_entry;
 870
 871         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 872
 873         if (INTEL_GEN(dev_priv) >= 11) {
 874                 if (intel_port_is_combophy(dev_priv, port))
 875                         icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 876                                                 0, &n_entries);
 877                 else
 878                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 879                 default_entry = n_entries - 1;
 880         } else if (IS_CANNONLAKE(dev_priv)) {
 881                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 882                 default_entry = n_entries - 1;
 883         } else if (IS_GEN9_LP(dev_priv)) {
 884                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 885                 default_entry = n_entries - 1;
 886         } else if (IS_GEN9_BC(dev_priv)) {
 887                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 888                 default_entry = 8;
 889         } else if (IS_BROADWELL(dev_priv)) {
 890                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 891                 default_entry = 7;
 892         } else if (IS_HASWELL(dev_priv)) {
 893                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 894                 default_entry = 6;
 895         } else {
 896                 WARN(1, "ddi translation table missing\n");
 897                 return 0;
 898         }
 899
 900         /* Choose a good default if VBT is badly populated */
 901         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 902                 level = default_entry;
 903
 904         if (WARN_ON_ONCE(n_entries == 0))
 905                 return 0;
 906         if (WARN_ON_ONCE(level >= n_entries))
 907                 level = n_entries - 1;
 908
 909         return level;
 910 }
 911
 912 /*
 913  * Starting with Haswell, DDI port buffers must be programmed with correct
 914  * values in advance. This function programs the correct values for
 915  * DP/eDP/FDI use cases.
 916  */
 917 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 918                                          const struct intel_crtc_state *crtc_state)
 919 {
 920         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 921         u32 iboost_bit = 0;
 922         int i, n_entries;
 923         enum port port = encoder->port;
 924         const struct ddi_buf_trans *ddi_translations;
 925
 926         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 927                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 928                                                                &n_entries);
 929         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 930                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 931                                                                &n_entries);
 932         else
 933                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 934                                                               &n_entries);
 935
 936         /* If we're boosting the current, set bit 31 of trans1 */
 937         if (IS_GEN9_BC(dev_priv) &&
 938             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 939                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 940
 941         for (i = 0; i < n_entries; i++) {
 942                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 943                            ddi_translations[i].trans1 | iboost_bit);
 944                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 945                            ddi_translations[i].trans2);
 946         }
 947 }
 948
 949 /*
 950  * Starting with Haswell, DDI port buffers must be programmed with correct
 951  * values in advance. This function programs the correct values for
 952  * HDMI/DVI use cases.
 953  */
 954 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 955                                            int level)
 956 {
 957         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 958         u32 iboost_bit = 0;
 959         int n_entries;
 960         enum port port = encoder->port;
 961         const struct ddi_buf_trans *ddi_translations;
 962
 963         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 964
 965         if (WARN_ON_ONCE(!ddi_translations))
 966                 return;
 967         if (WARN_ON_ONCE(level >= n_entries))
 968                 level = n_entries - 1;
 969
 970         /* If we're boosting the current, set bit 31 of trans1 */
 971         if (IS_GEN9_BC(dev_priv) &&
 972             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 973                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 974
 975         /* Entry 9 is for HDMI: */
 976         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 977                    ddi_translations[level].trans1 | iboost_bit);
 978         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 979                    ddi_translations[level].trans2);
 980 }
 981
 982 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 983                                     enum port port)
 984 {
 985         i915_reg_t reg = DDI_BUF_CTL(port);
 986         int i;
 987
 988         for (i = 0; i < 16; i++) {
 989                 udelay(1);
 990                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 991                         return;
 992         }
 993         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 994 }
 995
 996 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 997 {
 998         switch (pll->info->id) {
 999         case DPLL_ID_WRPLL1:
1000                 return PORT_CLK_SEL_WRPLL1;
1001         case DPLL_ID_WRPLL2:
1002                 return PORT_CLK_SEL_WRPLL2;
1003         case DPLL_ID_SPLL:
1004                 return PORT_CLK_SEL_SPLL;
1005         case DPLL_ID_LCPLL_810:
1006                 return PORT_CLK_SEL_LCPLL_810;
1007         case DPLL_ID_LCPLL_1350:
1008                 return PORT_CLK_SEL_LCPLL_1350;
1009         case DPLL_ID_LCPLL_2700:
1010                 return PORT_CLK_SEL_LCPLL_2700;
1011         default:
1012                 MISSING_CASE(pll->info->id);
1013                 return PORT_CLK_SEL_NONE;
1014         }
1015 }
1016
1017 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1018                                   const struct intel_crtc_state *crtc_state)
1019 {
1020         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1021         int clock = crtc_state->port_clock;
1022         const enum intel_dpll_id id = pll->info->id;
1023
1024         switch (id) {
1025         default:
1026                 /*
1027                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1028                  * here, so do warn if this get passed in
1029                  */
1030                 MISSING_CASE(id);
1031                 return DDI_CLK_SEL_NONE;
1032         case DPLL_ID_ICL_TBTPLL:
1033                 switch (clock) {
1034                 case 162000:
1035                         return DDI_CLK_SEL_TBT_162;
1036                 case 270000:
1037                         return DDI_CLK_SEL_TBT_270;
1038                 case 540000:
1039                         return DDI_CLK_SEL_TBT_540;
1040                 case 810000:
1041                         return DDI_CLK_SEL_TBT_810;
1042                 default:
1043                         MISSING_CASE(clock);
1044                         return DDI_CLK_SEL_NONE;
1045                 }
1046         case DPLL_ID_ICL_MGPLL1:
1047         case DPLL_ID_ICL_MGPLL2:
1048         case DPLL_ID_ICL_MGPLL3:
1049         case DPLL_ID_ICL_MGPLL4:
1050                 return DDI_CLK_SEL_MG;
1051         }
1052 }
1053
1054 /* Starting with Haswell, different DDI ports can work in FDI mode for
1055  * connection to the PCH-located connectors. For this, it is necessary to train
1056  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1057  *
1058  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1059  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1060  * DDI A (which is used for eDP)
1061  */
1062
1063 void hsw_fdi_link_train(struct intel_crtc *crtc,
1064                         const struct intel_crtc_state *crtc_state)
1065 {
1066         struct drm_device *dev = crtc->base.dev;
1067         struct drm_i915_private *dev_priv = to_i915(dev);
1068         struct intel_encoder *encoder;
1069         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1070
1071         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1072                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1073                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1074         }
1075
1076         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1077          * mode set "sequence for CRT port" document:
1078          * - TP1 to TP2 time with the default value
1079          * - FDI delay to 90h
1080          *
1081          * WaFDIAutoLinkSetTimingOverrride:hsw
1082          */
1083         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1084                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1085                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1086
1087         /* Enable the PCH Receiver FDI PLL */
1088         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1089                      FDI_RX_PLL_ENABLE |
1090                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1091         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1092         POSTING_READ(FDI_RX_CTL(PIPE_A));
1093         udelay(220);
1094
1095         /* Switch from Rawclk to PCDclk */
1096         rx_ctl_val |= FDI_PCDCLK;
1097         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1098
1099         /* Configure Port Clock Select */
1100         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1101         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1102         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1103
1104         /* Start the training iterating through available voltages and emphasis,
1105          * testing each value twice. */
1106         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1107                 /* Configure DP_TP_CTL with auto-training */
1108                 I915_WRITE(DP_TP_CTL(PORT_E),
1109                                         DP_TP_CTL_FDI_AUTOTRAIN |
1110                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1111                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1112                                         DP_TP_CTL_ENABLE);
1113
1114                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1115                  * DDI E does not support port reversal, the functionality is
1116                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1117                  * port reversal bit */
1118                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1119                            DDI_BUF_CTL_ENABLE |
1120                            ((crtc_state->fdi_lanes - 1) << 1) |
1121                            DDI_BUF_TRANS_SELECT(i / 2));
1122                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1123
1124                 udelay(600);
1125
1126                 /* Program PCH FDI Receiver TU */
1127                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1128
1129                 /* Enable PCH FDI Receiver with auto-training */
1130                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1131                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1132                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1133
1134                 /* Wait for FDI receiver lane calibration */
1135                 udelay(30);
1136
1137                 /* Unset FDI_RX_MISC pwrdn lanes */
1138                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1139                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1140                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1141                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1142
1143                 /* Wait for FDI auto training time */
1144                 udelay(5);
1145
1146                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1147                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1148                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1149                         break;
1150                 }
1151
1152                 /*
1153                  * Leave things enabled even if we failed to train FDI.
1154                  * Results in less fireworks from the state checker.
1155                  */
1156                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1157                         DRM_ERROR("FDI link training failed!\n");
1158                         break;
1159                 }
1160
1161                 rx_ctl_val &= ~FDI_RX_ENABLE;
1162                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1163                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1164
1165                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1166                 temp &= ~DDI_BUF_CTL_ENABLE;
1167                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1168                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1169
1170                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1171                 temp = I915_READ(DP_TP_CTL(PORT_E));
1172                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1173                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1174                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1175                 POSTING_READ(DP_TP_CTL(PORT_E));
1176
1177                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1178
1179                 /* Reset FDI_RX_MISC pwrdn lanes */
1180                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1181                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1182                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1183                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1184                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1185         }
1186
1187         /* Enable normal pixel sending for FDI */
1188         I915_WRITE(DP_TP_CTL(PORT_E),
1189                    DP_TP_CTL_FDI_AUTOTRAIN |
1190                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1191                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1192                    DP_TP_CTL_ENABLE);
1193 }
1194
1195 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1196 {
1197         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1198         struct intel_digital_port *intel_dig_port =
1199                 enc_to_dig_port(&encoder->base);
1200
1201         intel_dp->DP = intel_dig_port->saved_port_bits |
1202                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1203         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1204 }
1205
1206 static struct intel_encoder *
1207 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1208 {
1209         struct drm_device *dev = crtc->base.dev;
1210         struct intel_encoder *encoder, *ret = NULL;
1211         int num_encoders = 0;
1212
1213         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1214                 ret = encoder;
1215                 num_encoders++;
1216         }
1217
1218         if (num_encoders != 1)
1219                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1220                      pipe_name(crtc->pipe));
1221
1222         BUG_ON(ret == NULL);
1223         return ret;
1224 }
1225
1226 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1227                                    i915_reg_t reg)
1228 {
1229         int refclk;
1230         int n, p, r;
1231         u32 wrpll;
1232
1233         wrpll = I915_READ(reg);
1234         switch (wrpll & WRPLL_REF_MASK) {
1235         case WRPLL_REF_SPECIAL_HSW:
1236                 /*
1237                  * muxed-SSC for BDW.
1238                  * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1239                  * for the non-SSC reference frequency.
1240                  */
1241                 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1242                         if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1243                                 refclk = 24;
1244                         else
1245                                 refclk = 135;
1246                         break;
1247                 }
1248                 /* fall through */
1249         case WRPLL_REF_PCH_SSC:
1250                 /*
1251                  * We could calculate spread here, but our checking
1252                  * code only cares about 5% accuracy, and spread is a max of
1253                  * 0.5% downspread.
1254                  */
1255                 refclk = 135;
1256                 break;
1257         case WRPLL_REF_LCPLL:
1258                 refclk = 2700;
1259                 break;
1260         default:
1261                 MISSING_CASE(wrpll);
1262                 return 0;
1263         }
1264
1265         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1266         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1267         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1268
1269         /* Convert to KHz, p & r have a fixed point portion */
1270         return (refclk * n * 100) / (p * r);
1271 }
1272
1273 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1274 {
1275         u32 p0, p1, p2, dco_freq;
1276
1277         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1278         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1279
1280         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1281                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1282         else
1283                 p1 = 1;
1284
1285
1286         switch (p0) {
1287         case DPLL_CFGCR2_PDIV_1:
1288                 p0 = 1;
1289                 break;
1290         case DPLL_CFGCR2_PDIV_2:
1291                 p0 = 2;
1292                 break;
1293         case DPLL_CFGCR2_PDIV_3:
1294                 p0 = 3;
1295                 break;
1296         case DPLL_CFGCR2_PDIV_7:
1297                 p0 = 7;
1298                 break;
1299         }
1300
1301         switch (p2) {
1302         case DPLL_CFGCR2_KDIV_5:
1303                 p2 = 5;
1304                 break;
1305         case DPLL_CFGCR2_KDIV_2:
1306                 p2 = 2;
1307                 break;
1308         case DPLL_CFGCR2_KDIV_3:
1309                 p2 = 3;
1310                 break;
1311         case DPLL_CFGCR2_KDIV_1:
1312                 p2 = 1;
1313                 break;
1314         }
1315
1316         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1317                 * 24 * 1000;
1318
1319         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1320                      * 24 * 1000) / 0x8000;
1321
1322         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1323                 return 0;
1324
1325         return dco_freq / (p0 * p1 * p2 * 5);
1326 }
1327
1328 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1329                         struct intel_dpll_hw_state *pll_state)
1330 {
1331         u32 p0, p1, p2, dco_freq, ref_clock;
1332
1333         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1334         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1335
1336         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1337                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1338                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1339         else
1340                 p1 = 1;
1341
1342
1343         switch (p0) {
1344         case DPLL_CFGCR1_PDIV_2:
1345                 p0 = 2;
1346                 break;
1347         case DPLL_CFGCR1_PDIV_3:
1348                 p0 = 3;
1349                 break;
1350         case DPLL_CFGCR1_PDIV_5:
1351                 p0 = 5;
1352                 break;
1353         case DPLL_CFGCR1_PDIV_7:
1354                 p0 = 7;
1355                 break;
1356         }
1357
1358         switch (p2) {
1359         case DPLL_CFGCR1_KDIV_1:
1360                 p2 = 1;
1361                 break;
1362         case DPLL_CFGCR1_KDIV_2:
1363                 p2 = 2;
1364                 break;
1365         case DPLL_CFGCR1_KDIV_3:
1366                 p2 = 3;
1367                 break;
1368         }
1369
1370         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1371
1372         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1373                 * ref_clock;
1374
1375         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1376                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1377
1378         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1379                 return 0;
1380
1381         return dco_freq / (p0 * p1 * p2 * 5);
1382 }
1383
1384 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1385                                  enum port port)
1386 {
1387         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1388
1389         switch (val) {
1390         case DDI_CLK_SEL_NONE:
1391                 return 0;
1392         case DDI_CLK_SEL_TBT_162:
1393                 return 162000;
1394         case DDI_CLK_SEL_TBT_270:
1395                 return 270000;
1396         case DDI_CLK_SEL_TBT_540:
1397                 return 540000;
1398         case DDI_CLK_SEL_TBT_810:
1399                 return 810000;
1400         default:
1401                 MISSING_CASE(val);
1402                 return 0;
1403         }
1404 }
1405
1406 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1407                                 const struct intel_dpll_hw_state *pll_state)
1408 {
1409         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1410         u64 tmp;
1411
1412         ref_clock = dev_priv->cdclk.hw.ref;
1413
1414         m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1415         m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1416         m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1417                 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1418                 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1419
1420         switch (pll_state->mg_clktop2_hsclkctl &
1421                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1422         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1423                 div1 = 2;
1424                 break;
1425         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1426                 div1 = 3;
1427                 break;
1428         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1429                 div1 = 5;
1430                 break;
1431         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1432                 div1 = 7;
1433                 break;
1434         default:
1435                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1436                 return 0;
1437         }
1438
1439         div2 = (pll_state->mg_clktop2_hsclkctl &
1440                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1441                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1442
1443         /* div2 value of 0 is same as 1 means no div */
1444         if (div2 == 0)
1445                 div2 = 1;
1446
1447         /*
1448          * Adjust the original formula to delay the division by 2^22 in order to
1449          * minimize possible rounding errors.
1450          */
1451         tmp = (u64)m1 * m2_int * ref_clock +
1452               (((u64)m1 * m2_frac * ref_clock) >> 22);
1453         tmp = div_u64(tmp, 5 * div1 * div2);
1454
1455         return tmp;
1456 }
1457
1458 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1459 {
1460         int dotclock;
1461
1462         if (pipe_config->has_pch_encoder)
1463                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1464                                                     &pipe_config->fdi_m_n);
1465         else if (intel_crtc_has_dp_encoder(pipe_config))
1466                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1467                                                     &pipe_config->dp_m_n);
1468         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1469                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1470         else
1471                 dotclock = pipe_config->port_clock;
1472
1473         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1474             !intel_crtc_has_dp_encoder(pipe_config))
1475                 dotclock *= 2;
1476
1477         if (pipe_config->pixel_multiplier)
1478                 dotclock /= pipe_config->pixel_multiplier;
1479
1480         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1481 }
1482
1483 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1484                               struct intel_crtc_state *pipe_config)
1485 {
1486         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1487         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1488         enum port port = encoder->port;
1489         int link_clock;
1490
1491         if (intel_port_is_combophy(dev_priv, port)) {
1492                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1493         } else {
1494                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1495                                                 pipe_config->shared_dpll);
1496
1497                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1498                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1499                 else
1500                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1501         }
1502
1503         pipe_config->port_clock = link_clock;
1504
1505         ddi_dotclock_get(pipe_config);
1506 }
1507
1508 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1509                               struct intel_crtc_state *pipe_config)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1512         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1513         int link_clock;
1514
1515         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1516                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1517         } else {
1518                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1519
1520                 switch (link_clock) {
1521                 case DPLL_CFGCR0_LINK_RATE_810:
1522                         link_clock = 81000;
1523                         break;
1524                 case DPLL_CFGCR0_LINK_RATE_1080:
1525                         link_clock = 108000;
1526                         break;
1527                 case DPLL_CFGCR0_LINK_RATE_1350:
1528                         link_clock = 135000;
1529                         break;
1530                 case DPLL_CFGCR0_LINK_RATE_1620:
1531                         link_clock = 162000;
1532                         break;
1533                 case DPLL_CFGCR0_LINK_RATE_2160:
1534                         link_clock = 216000;
1535                         break;
1536                 case DPLL_CFGCR0_LINK_RATE_2700:
1537                         link_clock = 270000;
1538                         break;
1539                 case DPLL_CFGCR0_LINK_RATE_3240:
1540                         link_clock = 324000;
1541                         break;
1542                 case DPLL_CFGCR0_LINK_RATE_4050:
1543                         link_clock = 405000;
1544                         break;
1545                 default:
1546                         WARN(1, "Unsupported link rate\n");
1547                         break;
1548                 }
1549                 link_clock *= 2;
1550         }
1551
1552         pipe_config->port_clock = link_clock;
1553
1554         ddi_dotclock_get(pipe_config);
1555 }
1556
1557 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1558                               struct intel_crtc_state *pipe_config)
1559 {
1560         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1561         int link_clock;
1562
1563         /*
1564          * ctrl1 register is already shifted for each pll, just use 0 to get
1565          * the internal shift for each field
1566          */
1567         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1568                 link_clock = skl_calc_wrpll_link(pll_state);
1569         } else {
1570                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1571                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1572
1573                 switch (link_clock) {
1574                 case DPLL_CTRL1_LINK_RATE_810:
1575                         link_clock = 81000;
1576                         break;
1577                 case DPLL_CTRL1_LINK_RATE_1080:
1578                         link_clock = 108000;
1579                         break;
1580                 case DPLL_CTRL1_LINK_RATE_1350:
1581                         link_clock = 135000;
1582                         break;
1583                 case DPLL_CTRL1_LINK_RATE_1620:
1584                         link_clock = 162000;
1585                         break;
1586                 case DPLL_CTRL1_LINK_RATE_2160:
1587                         link_clock = 216000;
1588                         break;
1589                 case DPLL_CTRL1_LINK_RATE_2700:
1590                         link_clock = 270000;
1591                         break;
1592                 default:
1593                         WARN(1, "Unsupported link rate\n");
1594                         break;
1595                 }
1596                 link_clock *= 2;
1597         }
1598
1599         pipe_config->port_clock = link_clock;
1600
1601         ddi_dotclock_get(pipe_config);
1602 }
1603
1604 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1605                               struct intel_crtc_state *pipe_config)
1606 {
1607         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1608         int link_clock = 0;
1609         u32 val, pll;
1610
1611         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1612         switch (val & PORT_CLK_SEL_MASK) {
1613         case PORT_CLK_SEL_LCPLL_810:
1614                 link_clock = 81000;
1615                 break;
1616         case PORT_CLK_SEL_LCPLL_1350:
1617                 link_clock = 135000;
1618                 break;
1619         case PORT_CLK_SEL_LCPLL_2700:
1620                 link_clock = 270000;
1621                 break;
1622         case PORT_CLK_SEL_WRPLL1:
1623                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1624                 break;
1625         case PORT_CLK_SEL_WRPLL2:
1626                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1627                 break;
1628         case PORT_CLK_SEL_SPLL:
1629                 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1630                 if (pll == SPLL_FREQ_810MHz)
1631                         link_clock = 81000;
1632                 else if (pll == SPLL_FREQ_1350MHz)
1633                         link_clock = 135000;
1634                 else if (pll == SPLL_FREQ_2700MHz)
1635                         link_clock = 270000;
1636                 else {
1637                         WARN(1, "bad spll freq\n");
1638                         return;
1639                 }
1640                 break;
1641         default:
1642                 WARN(1, "bad port clock sel\n");
1643                 return;
1644         }
1645
1646         pipe_config->port_clock = link_clock * 2;
1647
1648         ddi_dotclock_get(pipe_config);
1649 }
1650
1651 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1652 {
1653         struct dpll clock;
1654
1655         clock.m1 = 2;
1656         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1657         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1658                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1659         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1660         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1661         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1662
1663         return chv_calc_dpll_params(100000, &clock);
1664 }
1665
1666 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1667                               struct intel_crtc_state *pipe_config)
1668 {
1669         pipe_config->port_clock =
1670                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1671
1672         ddi_dotclock_get(pipe_config);
1673 }
1674
1675 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1676                                 struct intel_crtc_state *pipe_config)
1677 {
1678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1679
1680         if (INTEL_GEN(dev_priv) >= 11)
1681                 icl_ddi_clock_get(encoder, pipe_config);
1682         else if (IS_CANNONLAKE(dev_priv))
1683                 cnl_ddi_clock_get(encoder, pipe_config);
1684         else if (IS_GEN9_LP(dev_priv))
1685                 bxt_ddi_clock_get(encoder, pipe_config);
1686         else if (IS_GEN9_BC(dev_priv))
1687                 skl_ddi_clock_get(encoder, pipe_config);
1688         else if (INTEL_GEN(dev_priv) <= 8)
1689                 hsw_ddi_clock_get(encoder, pipe_config);
1690 }
1691
1692 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1693 {
1694         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1695         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1696         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1697         u32 temp;
1698
1699         if (!intel_crtc_has_dp_encoder(crtc_state))
1700                 return;
1701
1702         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1703
1704         temp = TRANS_MSA_SYNC_CLK;
1705
1706         if (crtc_state->limited_color_range)
1707                 temp |= TRANS_MSA_CEA_RANGE;
1708
1709         switch (crtc_state->pipe_bpp) {
1710         case 18:
1711                 temp |= TRANS_MSA_6_BPC;
1712                 break;
1713         case 24:
1714                 temp |= TRANS_MSA_8_BPC;
1715                 break;
1716         case 30:
1717                 temp |= TRANS_MSA_10_BPC;
1718                 break;
1719         case 36:
1720                 temp |= TRANS_MSA_12_BPC;
1721                 break;
1722         default:
1723                 MISSING_CASE(crtc_state->pipe_bpp);
1724                 break;
1725         }
1726
1727         /*
1728          * As per DP 1.2 spec section 2.3.4.3 while sending
1729          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1730          * colorspace information. The output colorspace encoding is BT601.
1731          */
1732         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1733                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1734         /*
1735          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1736          * of Color Encoding Format and Content Color Gamut] while sending
1737          * YCBCR 420 signals we should program MSA MISC1 fields which
1738          * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1739          */
1740         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1741                 temp |= TRANS_MSA_USE_VSC_SDP;
1742         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1743 }
1744
1745 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1746                                     bool state)
1747 {
1748         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1749         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1750         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1751         u32 temp;
1752
1753         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1754         if (state == true)
1755                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1756         else
1757                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1758         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1759 }
1760
1761 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1762 {
1763         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1764         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1765         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1766         enum pipe pipe = crtc->pipe;
1767         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1768         enum port port = encoder->port;
1769         u32 temp;
1770
1771         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1772         temp = TRANS_DDI_FUNC_ENABLE;
1773         temp |= TRANS_DDI_SELECT_PORT(port);
1774
1775         switch (crtc_state->pipe_bpp) {
1776         case 18:
1777                 temp |= TRANS_DDI_BPC_6;
1778                 break;
1779         case 24:
1780                 temp |= TRANS_DDI_BPC_8;
1781                 break;
1782         case 30:
1783                 temp |= TRANS_DDI_BPC_10;
1784                 break;
1785         case 36:
1786                 temp |= TRANS_DDI_BPC_12;
1787                 break;
1788         default:
1789                 BUG();
1790         }
1791
1792         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1793                 temp |= TRANS_DDI_PVSYNC;
1794         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1795                 temp |= TRANS_DDI_PHSYNC;
1796
1797         if (cpu_transcoder == TRANSCODER_EDP) {
1798                 switch (pipe) {
1799                 case PIPE_A:
1800                         /* On Haswell, can only use the always-on power well for
1801                          * eDP when not using the panel fitter, and when not
1802                          * using motion blur mitigation (which we don't
1803                          * support). */
1804                         if (crtc_state->pch_pfit.force_thru)
1805                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1806                         else
1807                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1808                         break;
1809                 case PIPE_B:
1810                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1811                         break;
1812                 case PIPE_C:
1813                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1814                         break;
1815                 default:
1816                         BUG();
1817                         break;
1818                 }
1819         }
1820
1821         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1822                 if (crtc_state->has_hdmi_sink)
1823                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1824                 else
1825                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1826
1827                 if (crtc_state->hdmi_scrambling)
1828                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1829                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1830                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1831         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1832                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1833                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1834         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1835                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1836                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1837         } else {
1838                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1839                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1840         }
1841
1842         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1843 }
1844
1845 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1846 {
1847         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1848         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1849         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1850         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1851         u32 val = I915_READ(reg);
1852
1853         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1854         val |= TRANS_DDI_PORT_NONE;
1855         I915_WRITE(reg, val);
1856
1857         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1858             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1859                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1860                 /* Quirk time at 100ms for reliable operation */
1861                 msleep(100);
1862         }
1863 }
1864
1865 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1866                                      bool enable)
1867 {
1868         struct drm_device *dev = intel_encoder->base.dev;
1869         struct drm_i915_private *dev_priv = to_i915(dev);
1870         intel_wakeref_t wakeref;
1871         enum pipe pipe = 0;
1872         int ret = 0;
1873         u32 tmp;
1874
1875         wakeref = intel_display_power_get_if_enabled(dev_priv,
1876                                                      intel_encoder->power_domain);
1877         if (WARN_ON(!wakeref))
1878                 return -ENXIO;
1879
1880         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1881                 ret = -EIO;
1882                 goto out;
1883         }
1884
1885         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1886         if (enable)
1887                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1888         else
1889                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1890         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1891 out:
1892         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1893         return ret;
1894 }
1895
1896 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1897 {
1898         struct drm_device *dev = intel_connector->base.dev;
1899         struct drm_i915_private *dev_priv = to_i915(dev);
1900         struct intel_encoder *encoder = intel_connector->encoder;
1901         int type = intel_connector->base.connector_type;
1902         enum port port = encoder->port;
1903         enum transcoder cpu_transcoder;
1904         intel_wakeref_t wakeref;
1905         enum pipe pipe = 0;
1906         u32 tmp;
1907         bool ret;
1908
1909         wakeref = intel_display_power_get_if_enabled(dev_priv,
1910                                                      encoder->power_domain);
1911         if (!wakeref)
1912                 return false;
1913
1914         if (!encoder->get_hw_state(encoder, &pipe)) {
1915                 ret = false;
1916                 goto out;
1917         }
1918
1919         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1920                 cpu_transcoder = TRANSCODER_EDP;
1921         else
1922                 cpu_transcoder = (enum transcoder) pipe;
1923
1924         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1925
1926         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1927         case TRANS_DDI_MODE_SELECT_HDMI:
1928         case TRANS_DDI_MODE_SELECT_DVI:
1929                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1930                 break;
1931
1932         case TRANS_DDI_MODE_SELECT_DP_SST:
1933                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1934                       type == DRM_MODE_CONNECTOR_DisplayPort;
1935                 break;
1936
1937         case TRANS_DDI_MODE_SELECT_DP_MST:
1938                 /* if the transcoder is in MST state then
1939                  * connector isn't connected */
1940                 ret = false;
1941                 break;
1942
1943         case TRANS_DDI_MODE_SELECT_FDI:
1944                 ret = type == DRM_MODE_CONNECTOR_VGA;
1945                 break;
1946
1947         default:
1948                 ret = false;
1949                 break;
1950         }
1951
1952 out:
1953         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1954
1955         return ret;
1956 }
1957
1958 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1959                                         u8 *pipe_mask, bool *is_dp_mst)
1960 {
1961         struct drm_device *dev = encoder->base.dev;
1962         struct drm_i915_private *dev_priv = to_i915(dev);
1963         enum port port = encoder->port;
1964         intel_wakeref_t wakeref;
1965         enum pipe p;
1966         u32 tmp;
1967         u8 mst_pipe_mask;
1968
1969         *pipe_mask = 0;
1970         *is_dp_mst = false;
1971
1972         wakeref = intel_display_power_get_if_enabled(dev_priv,
1973                                                      encoder->power_domain);
1974         if (!wakeref)
1975                 return;
1976
1977         tmp = I915_READ(DDI_BUF_CTL(port));
1978         if (!(tmp & DDI_BUF_CTL_ENABLE))
1979                 goto out;
1980
1981         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1982                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1983
1984                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1985                 default:
1986                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1987                         /* fallthrough */
1988                 case TRANS_DDI_EDP_INPUT_A_ON:
1989                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1990                         *pipe_mask = BIT(PIPE_A);
1991                         break;
1992                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1993                         *pipe_mask = BIT(PIPE_B);
1994                         break;
1995                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1996                         *pipe_mask = BIT(PIPE_C);
1997                         break;
1998                 }
1999
2000                 goto out;
2001         }
2002
2003         mst_pipe_mask = 0;
2004         for_each_pipe(dev_priv, p) {
2005                 enum transcoder cpu_transcoder = (enum transcoder)p;
2006
2007                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2008
2009                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2010                         continue;
2011
2012                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2013                     TRANS_DDI_MODE_SELECT_DP_MST)
2014                         mst_pipe_mask |= BIT(p);
2015
2016                 *pipe_mask |= BIT(p);
2017         }
2018
2019         if (!*pipe_mask)
2020                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2021                               port_name(port));
2022
2023         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2024                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2025                               port_name(port), *pipe_mask);
2026                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2027         }
2028
2029         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2030                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2031                               port_name(port), *pipe_mask, mst_pipe_mask);
2032         else
2033                 *is_dp_mst = mst_pipe_mask;
2034
2035 out:
2036         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2037                 tmp = I915_READ(BXT_PHY_CTL(port));
2038                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2039                             BXT_PHY_LANE_POWERDOWN_ACK |
2040                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2041                         DRM_ERROR("Port %c enabled but PHY powered down? "
2042                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2043         }
2044
2045         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2046 }
2047
2048 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2049                             enum pipe *pipe)
2050 {
2051         u8 pipe_mask;
2052         bool is_mst;
2053
2054         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2055
2056         if (is_mst || !pipe_mask)
2057                 return false;
2058
2059         *pipe = ffs(pipe_mask) - 1;
2060
2061         return true;
2062 }
2063
2064 static inline enum intel_display_power_domain
2065 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2066 {
2067         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2068          * DC states enabled at the same time, while for driver initiated AUX
2069          * transfers we need the same AUX IOs to be powered but with DC states
2070          * disabled. Accordingly use the AUX power domain here which leaves DC
2071          * states enabled.
2072          * However, for non-A AUX ports the corresponding non-EDP transcoders
2073          * would have already enabled power well 2 and DC_OFF. This means we can
2074          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2075          * specific AUX_IO reference without powering up any extra wells.
2076          * Note that PSR is enabled only on Port A even though this function
2077          * returns the correct domain for other ports too.
2078          */
2079         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2080                                               intel_aux_power_domain(dig_port);
2081 }
2082
2083 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2084                                         struct intel_crtc_state *crtc_state)
2085 {
2086         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2087         struct intel_digital_port *dig_port;
2088
2089         /*
2090          * TODO: Add support for MST encoders. Atm, the following should never
2091          * happen since fake-MST encoders don't set their get_power_domains()
2092          * hook.
2093          */
2094         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2095                 return;
2096
2097         dig_port = enc_to_dig_port(&encoder->base);
2098         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2099
2100         /*
2101          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2102          * ports.
2103          */
2104         if (intel_crtc_has_dp_encoder(crtc_state) ||
2105             intel_port_is_tc(dev_priv, encoder->port))
2106                 intel_display_power_get(dev_priv,
2107                                         intel_ddi_main_link_aux_domain(dig_port));
2108
2109         /*
2110          * VDSC power is needed when DSC is enabled
2111          */
2112         if (crtc_state->dsc_params.compression_enable)
2113                 intel_display_power_get(dev_priv,
2114                                         intel_dsc_power_domain(crtc_state));
2115 }
2116
2117 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2118 {
2119         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2120         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2121         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2122         enum port port = encoder->port;
2123         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2124
2125         if (cpu_transcoder != TRANSCODER_EDP)
2126                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2127                            TRANS_CLK_SEL_PORT(port));
2128 }
2129
2130 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2131 {
2132         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2133         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2134
2135         if (cpu_transcoder != TRANSCODER_EDP)
2136                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2137                            TRANS_CLK_SEL_DISABLED);
2138 }
2139
2140 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2141                                 enum port port, u8 iboost)
2142 {
2143         u32 tmp;
2144
2145         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2146         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2147         if (iboost)
2148                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2149         else
2150                 tmp |= BALANCE_LEG_DISABLE(port);
2151         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2152 }
2153
2154 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2155                                int level, enum intel_output_type type)
2156 {
2157         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2158         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2159         enum port port = encoder->port;
2160         u8 iboost;
2161
2162         if (type == INTEL_OUTPUT_HDMI)
2163                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2164         else
2165                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2166
2167         if (iboost == 0) {
2168                 const struct ddi_buf_trans *ddi_translations;
2169                 int n_entries;
2170
2171                 if (type == INTEL_OUTPUT_HDMI)
2172                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2173                 else if (type == INTEL_OUTPUT_EDP)
2174                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2175                 else
2176                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2177
2178                 if (WARN_ON_ONCE(!ddi_translations))
2179                         return;
2180                 if (WARN_ON_ONCE(level >= n_entries))
2181                         level = n_entries - 1;
2182
2183                 iboost = ddi_translations[level].i_boost;
2184         }
2185
2186         /* Make sure that the requested I_boost is valid */
2187         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2188                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2189                 return;
2190         }
2191
2192         _skl_ddi_set_iboost(dev_priv, port, iboost);
2193
2194         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2195                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2196 }
2197
2198 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2199                                     int level, enum intel_output_type type)
2200 {
2201         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2202         const struct bxt_ddi_buf_trans *ddi_translations;
2203         enum port port = encoder->port;
2204         int n_entries;
2205
2206         if (type == INTEL_OUTPUT_HDMI)
2207                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2208         else if (type == INTEL_OUTPUT_EDP)
2209                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2210         else
2211                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2212
2213         if (WARN_ON_ONCE(!ddi_translations))
2214                 return;
2215         if (WARN_ON_ONCE(level >= n_entries))
2216                 level = n_entries - 1;
2217
2218         bxt_ddi_phy_set_signal_level(dev_priv, port,
2219                                      ddi_translations[level].margin,
2220                                      ddi_translations[level].scale,
2221                                      ddi_translations[level].enable,
2222                                      ddi_translations[level].deemphasis);
2223 }
2224
2225 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2226 {
2227         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2228         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2229         enum port port = encoder->port;
2230         int n_entries;
2231
2232         if (INTEL_GEN(dev_priv) >= 11) {
2233                 if (intel_port_is_combophy(dev_priv, port))
2234                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2235                                                 intel_dp->link_rate, &n_entries);
2236                 else
2237                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2238         } else if (IS_CANNONLAKE(dev_priv)) {
2239                 if (encoder->type == INTEL_OUTPUT_EDP)
2240                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2241                 else
2242                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2243         } else if (IS_GEN9_LP(dev_priv)) {
2244                 if (encoder->type == INTEL_OUTPUT_EDP)
2245                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2246                 else
2247                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2248         } else {
2249                 if (encoder->type == INTEL_OUTPUT_EDP)
2250                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2251                 else
2252                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2253         }
2254
2255         if (WARN_ON(n_entries < 1))
2256                 n_entries = 1;
2257         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2258                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2259
2260         return index_to_dp_signal_levels[n_entries - 1] &
2261                 DP_TRAIN_VOLTAGE_SWING_MASK;
2262 }
2263
2264 /*
2265  * We assume that the full set of pre-emphasis values can be
2266  * used on all DDI platforms. Should that change we need to
2267  * rethink this code.
2268  */
2269 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2270 {
2271         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2272         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2273                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2274         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2275                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2276         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2277                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2278         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2279         default:
2280                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2281         }
2282 }
2283
2284 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2285                                    int level, enum intel_output_type type)
2286 {
2287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2288         const struct cnl_ddi_buf_trans *ddi_translations;
2289         enum port port = encoder->port;
2290         int n_entries, ln;
2291         u32 val;
2292
2293         if (type == INTEL_OUTPUT_HDMI)
2294                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2295         else if (type == INTEL_OUTPUT_EDP)
2296                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2297         else
2298                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2299
2300         if (WARN_ON_ONCE(!ddi_translations))
2301                 return;
2302         if (WARN_ON_ONCE(level >= n_entries))
2303                 level = n_entries - 1;
2304
2305         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2306         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2307         val &= ~SCALING_MODE_SEL_MASK;
2308         val |= SCALING_MODE_SEL(2);
2309         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2310
2311         /* Program PORT_TX_DW2 */
2312         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2313         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2314                  RCOMP_SCALAR_MASK);
2315         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2316         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2317         /* Rcomp scalar is fixed as 0x98 for every table entry */
2318         val |= RCOMP_SCALAR(0x98);
2319         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2320
2321         /* Program PORT_TX_DW4 */
2322         /* We cannot write to GRP. It would overrite individual loadgen */
2323         for (ln = 0; ln < 4; ln++) {
2324                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2325                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2326                          CURSOR_COEFF_MASK);
2327                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2328                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2329                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2330                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2331         }
2332
2333         /* Program PORT_TX_DW5 */
2334         /* All DW5 values are fixed for every table entry */
2335         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2336         val &= ~RTERM_SELECT_MASK;
2337         val |= RTERM_SELECT(6);
2338         val |= TAP3_DISABLE;
2339         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2340
2341         /* Program PORT_TX_DW7 */
2342         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2343         val &= ~N_SCALAR_MASK;
2344         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2345         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2346 }
2347
2348 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2349                                     int level, enum intel_output_type type)
2350 {
2351         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2352         enum port port = encoder->port;
2353         int width, rate, ln;
2354         u32 val;
2355
2356         if (type == INTEL_OUTPUT_HDMI) {
2357                 width = 4;
2358                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2359         } else {
2360                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2361
2362                 width = intel_dp->lane_count;
2363                 rate = intel_dp->link_rate;
2364         }
2365
2366         /*
2367          * 1. If port type is eDP or DP,
2368          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2369          * else clear to 0b.
2370          */
2371         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2372         if (type != INTEL_OUTPUT_HDMI)
2373                 val |= COMMON_KEEPER_EN;
2374         else
2375                 val &= ~COMMON_KEEPER_EN;
2376         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2377
2378         /* 2. Program loadgen select */
2379         /*
2380          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2381          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2382          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2383          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2384          */
2385         for (ln = 0; ln <= 3; ln++) {
2386                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2387                 val &= ~LOADGEN_SELECT;
2388
2389                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2390                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2391                         val |= LOADGEN_SELECT;
2392                 }
2393                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2394         }
2395
2396         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2397         val = I915_READ(CNL_PORT_CL1CM_DW5);
2398         val |= SUS_CLOCK_CONFIG;
2399         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2400
2401         /* 4. Clear training enable to change swing values */
2402         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2403         val &= ~TX_TRAINING_EN;
2404         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2405
2406         /* 5. Program swing and de-emphasis */
2407         cnl_ddi_vswing_program(encoder, level, type);
2408
2409         /* 6. Set training enable to trigger update */
2410         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2411         val |= TX_TRAINING_EN;
2412         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2413 }
2414
2415 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2416                                         u32 level, enum port port, int type,
2417                                         int rate)
2418 {
2419         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2420         u32 n_entries, val;
2421         int ln;
2422
2423         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2424                                                    rate, &n_entries);
2425         if (!ddi_translations)
2426                 return;
2427
2428         if (level >= n_entries) {
2429                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2430                 level = n_entries - 1;
2431         }
2432
2433         /* Set PORT_TX_DW5 */
2434         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2435         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2436                   TAP2_DISABLE | TAP3_DISABLE);
2437         val |= SCALING_MODE_SEL(0x2);
2438         val |= RTERM_SELECT(0x6);
2439         val |= TAP3_DISABLE;
2440         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2441
2442         /* Program PORT_TX_DW2 */
2443         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2444         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2445                  RCOMP_SCALAR_MASK);
2446         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2447         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2448         /* Program Rcomp scalar for every table entry */
2449         val |= RCOMP_SCALAR(0x98);
2450         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2451
2452         /* Program PORT_TX_DW4 */
2453         /* We cannot write to GRP. It would overwrite individual loadgen. */
2454         for (ln = 0; ln <= 3; ln++) {
2455                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2456                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2457                          CURSOR_COEFF_MASK);
2458                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2459                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2460                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2461                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2462         }
2463
2464         /* Program PORT_TX_DW7 */
2465         val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2466         val &= ~N_SCALAR_MASK;
2467         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2468         I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2469 }
2470
2471 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2472                                               u32 level,
2473                                               enum intel_output_type type)
2474 {
2475         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2476         enum port port = encoder->port;
2477         int width = 0;
2478         int rate = 0;
2479         u32 val;
2480         int ln = 0;
2481
2482         if (type == INTEL_OUTPUT_HDMI) {
2483                 width = 4;
2484                 /* Rate is always < than 6GHz for HDMI */
2485         } else {
2486                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2487
2488                 width = intel_dp->lane_count;
2489                 rate = intel_dp->link_rate;
2490         }
2491
2492         /*
2493          * 1. If port type is eDP or DP,
2494          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2495          * else clear to 0b.
2496          */
2497         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2498         if (type == INTEL_OUTPUT_HDMI)
2499                 val &= ~COMMON_KEEPER_EN;
2500         else
2501                 val |= COMMON_KEEPER_EN;
2502         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2503
2504         /* 2. Program loadgen select */
2505         /*
2506          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2507          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2508          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2509          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2510          */
2511         for (ln = 0; ln <= 3; ln++) {
2512                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2513                 val &= ~LOADGEN_SELECT;
2514
2515                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2516                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2517                         val |= LOADGEN_SELECT;
2518                 }
2519                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2520         }
2521
2522         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2523         val = I915_READ(ICL_PORT_CL_DW5(port));
2524         val |= SUS_CLOCK_CONFIG;
2525         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2526
2527         /* 4. Clear training enable to change swing values */
2528         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2529         val &= ~TX_TRAINING_EN;
2530         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2531
2532         /* 5. Program swing and de-emphasis */
2533         icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2534
2535         /* 6. Set training enable to trigger update */
2536         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2537         val |= TX_TRAINING_EN;
2538         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2539 }
2540
2541 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2542                                            int link_clock,
2543                                            u32 level)
2544 {
2545         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2546         enum port port = encoder->port;
2547         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2548         u32 n_entries, val;
2549         int ln;
2550
2551         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2552         ddi_translations = icl_mg_phy_ddi_translations;
2553         /* The table does not have values for level 3 and level 9. */
2554         if (level >= n_entries || level == 3 || level == 9) {
2555                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2556                               level, n_entries - 2);
2557                 level = n_entries - 2;
2558         }
2559
2560         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2561         for (ln = 0; ln < 2; ln++) {
2562                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2563                 val &= ~CRI_USE_FS32;
2564                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2565
2566                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2567                 val &= ~CRI_USE_FS32;
2568                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2569         }
2570
2571         /* Program MG_TX_SWINGCTRL with values from vswing table */
2572         for (ln = 0; ln < 2; ln++) {
2573                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2574                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2575                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2576                         ddi_translations[level].cri_txdeemph_override_17_12);
2577                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2578
2579                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2580                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2581                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2582                         ddi_translations[level].cri_txdeemph_override_17_12);
2583                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2584         }
2585
2586         /* Program MG_TX_DRVCTRL with values from vswing table */
2587         for (ln = 0; ln < 2; ln++) {
2588                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2589                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2590                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2591                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2592                         ddi_translations[level].cri_txdeemph_override_5_0) |
2593                         CRI_TXDEEMPH_OVERRIDE_11_6(
2594                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2595                         CRI_TXDEEMPH_OVERRIDE_EN;
2596                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2597
2598                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2599                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2600                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2601                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2602                         ddi_translations[level].cri_txdeemph_override_5_0) |
2603                         CRI_TXDEEMPH_OVERRIDE_11_6(
2604                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2605                         CRI_TXDEEMPH_OVERRIDE_EN;
2606                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2607
2608                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2609         }
2610
2611         /*
2612          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2613          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2614          * values from table for which TX1 and TX2 enabled.
2615          */
2616         for (ln = 0; ln < 2; ln++) {
2617                 val = I915_READ(MG_CLKHUB(ln, port));
2618                 if (link_clock < 300000)
2619                         val |= CFG_LOW_RATE_LKREN_EN;
2620                 else
2621                         val &= ~CFG_LOW_RATE_LKREN_EN;
2622                 I915_WRITE(MG_CLKHUB(ln, port), val);
2623         }
2624
2625         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2626         for (ln = 0; ln < 2; ln++) {
2627                 val = I915_READ(MG_TX1_DCC(ln, port));
2628                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2629                 if (link_clock <= 500000) {
2630                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2631                 } else {
2632                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2633                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2634                 }
2635                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2636
2637                 val = I915_READ(MG_TX2_DCC(ln, port));
2638                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2639                 if (link_clock <= 500000) {
2640                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2641                 } else {
2642                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2643                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2644                 }
2645                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2646         }
2647
2648         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2649         for (ln = 0; ln < 2; ln++) {
2650                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2651                 val |= CRI_CALCINIT;
2652                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2653
2654                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2655                 val |= CRI_CALCINIT;
2656                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2657         }
2658 }
2659
2660 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2661                                     int link_clock,
2662                                     u32 level,
2663                                     enum intel_output_type type)
2664 {
2665         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2666         enum port port = encoder->port;
2667
2668         if (intel_port_is_combophy(dev_priv, port))
2669                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2670         else
2671                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2672 }
2673
2674 static u32 translate_signal_level(int signal_levels)
2675 {
2676         int i;
2677
2678         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2679                 if (index_to_dp_signal_levels[i] == signal_levels)
2680                         return i;
2681         }
2682
2683         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2684              signal_levels);
2685
2686         return 0;
2687 }
2688
2689 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2690 {
2691         u8 train_set = intel_dp->train_set[0];
2692         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2693                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2694
2695         return translate_signal_level(signal_levels);
2696 }
2697
2698 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2699 {
2700         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2701         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2702         struct intel_encoder *encoder = &dport->base;
2703         int level = intel_ddi_dp_level(intel_dp);
2704
2705         if (INTEL_GEN(dev_priv) >= 11)
2706                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2707                                         level, encoder->type);
2708         else if (IS_CANNONLAKE(dev_priv))
2709                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2710         else
2711                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2712
2713         return 0;
2714 }
2715
2716 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2717 {
2718         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2719         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2720         struct intel_encoder *encoder = &dport->base;
2721         int level = intel_ddi_dp_level(intel_dp);
2722
2723         if (IS_GEN9_BC(dev_priv))
2724                 skl_ddi_set_iboost(encoder, level, encoder->type);
2725
2726         return DDI_BUF_TRANS_SELECT(level);
2727 }
2728
2729 static inline
2730 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2731                               enum port port)
2732 {
2733         if (intel_port_is_combophy(dev_priv, port)) {
2734                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2735         } else if (intel_port_is_tc(dev_priv, port)) {
2736                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2737
2738                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2739         }
2740
2741         return 0;
2742 }
2743
2744 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2745                                   const struct intel_crtc_state *crtc_state)
2746 {
2747         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2748         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2749         enum port port = encoder->port;
2750         u32 val;
2751
2752         mutex_lock(&dev_priv->dpll_lock);
2753
2754         val = I915_READ(DPCLKA_CFGCR0_ICL);
2755         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2756
2757         if (intel_port_is_combophy(dev_priv, port)) {
2758                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2759                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2760                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2761                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2762         }
2763
2764         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2765         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2766
2767         mutex_unlock(&dev_priv->dpll_lock);
2768 }
2769
2770 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2771 {
2772         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2773         enum port port = encoder->port;
2774         u32 val;
2775
2776         mutex_lock(&dev_priv->dpll_lock);
2777
2778         val = I915_READ(DPCLKA_CFGCR0_ICL);
2779         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2780         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2781
2782         mutex_unlock(&dev_priv->dpll_lock);
2783 }
2784
2785 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2786 {
2787         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2788         u32 val;
2789         enum port port;
2790         u32 port_mask;
2791         bool ddi_clk_needed;
2792
2793         /*
2794          * In case of DP MST, we sanitize the primary encoder only, not the
2795          * virtual ones.
2796          */
2797         if (encoder->type == INTEL_OUTPUT_DP_MST)
2798                 return;
2799
2800         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2801                 u8 pipe_mask;
2802                 bool is_mst;
2803
2804                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2805                 /*
2806                  * In the unlikely case that BIOS enables DP in MST mode, just
2807                  * warn since our MST HW readout is incomplete.
2808                  */
2809                 if (WARN_ON(is_mst))
2810                         return;
2811         }
2812
2813         port_mask = BIT(encoder->port);
2814         ddi_clk_needed = encoder->base.crtc;
2815
2816         if (encoder->type == INTEL_OUTPUT_DSI) {
2817                 struct intel_encoder *other_encoder;
2818
2819                 port_mask = intel_dsi_encoder_ports(encoder);
2820                 /*
2821                  * Sanity check that we haven't incorrectly registered another
2822                  * encoder using any of the ports of this DSI encoder.
2823                  */
2824                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2825                         if (other_encoder == encoder)
2826                                 continue;
2827
2828                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2829                                 return;
2830                 }
2831                 /*
2832                  * For DSI we keep the ddi clocks gated
2833                  * except during enable/disable sequence.
2834                  */
2835                 ddi_clk_needed = false;
2836         }
2837
2838         val = I915_READ(DPCLKA_CFGCR0_ICL);
2839         for_each_port_masked(port, port_mask) {
2840                 bool ddi_clk_ungated = !(val &
2841                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2842                                                                    port));
2843
2844                 if (ddi_clk_needed == ddi_clk_ungated)
2845                         continue;
2846
2847                 /*
2848                  * Punt on the case now where clock is gated, but it would
2849                  * be needed by the port. Something else is really broken then.
2850                  */
2851                 if (WARN_ON(ddi_clk_needed))
2852                         continue;
2853
2854                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2855                          port_name(port));
2856                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2857                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2858         }
2859 }
2860
2861 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2862                                  const struct intel_crtc_state *crtc_state)
2863 {
2864         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2865         enum port port = encoder->port;
2866         u32 val;
2867         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2868
2869         if (WARN_ON(!pll))
2870                 return;
2871
2872         mutex_lock(&dev_priv->dpll_lock);
2873
2874         if (INTEL_GEN(dev_priv) >= 11) {
2875                 if (!intel_port_is_combophy(dev_priv, port))
2876                         I915_WRITE(DDI_CLK_SEL(port),
2877                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2878         } else if (IS_CANNONLAKE(dev_priv)) {
2879                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2880                 val = I915_READ(DPCLKA_CFGCR0);
2881                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2882                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2883                 I915_WRITE(DPCLKA_CFGCR0, val);
2884
2885                 /*
2886                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2887                  * This step and the step before must be done with separate
2888                  * register writes.
2889                  */
2890                 val = I915_READ(DPCLKA_CFGCR0);
2891                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2892                 I915_WRITE(DPCLKA_CFGCR0, val);
2893         } else if (IS_GEN9_BC(dev_priv)) {
2894                 /* DDI -> PLL mapping  */
2895                 val = I915_READ(DPLL_CTRL2);
2896
2897                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2898                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2899                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2900                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2901
2902                 I915_WRITE(DPLL_CTRL2, val);
2903
2904         } else if (INTEL_GEN(dev_priv) < 9) {
2905                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2906         }
2907
2908         mutex_unlock(&dev_priv->dpll_lock);
2909 }
2910
2911 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2912 {
2913         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2914         enum port port = encoder->port;
2915
2916         if (INTEL_GEN(dev_priv) >= 11) {
2917                 if (!intel_port_is_combophy(dev_priv, port))
2918                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2919         } else if (IS_CANNONLAKE(dev_priv)) {
2920                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2921                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2922         } else if (IS_GEN9_BC(dev_priv)) {
2923                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2924                            DPLL_CTRL2_DDI_CLK_OFF(port));
2925         } else if (INTEL_GEN(dev_priv) < 9) {
2926                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2927         }
2928 }
2929
2930 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2931 {
2932         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2933         enum port port = dig_port->base.port;
2934         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2935         u32 val;
2936         int ln;
2937
2938         if (tc_port == PORT_TC_NONE)
2939                 return;
2940
2941         for (ln = 0; ln < 2; ln++) {
2942                 val = I915_READ(MG_DP_MODE(ln, port));
2943                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2944                        MG_DP_MODE_CFG_TRPWR_GATING |
2945                        MG_DP_MODE_CFG_CLNPWR_GATING |
2946                        MG_DP_MODE_CFG_DIGPWR_GATING |
2947                        MG_DP_MODE_CFG_GAONPWR_GATING;
2948                 I915_WRITE(MG_DP_MODE(ln, port), val);
2949         }
2950
2951         val = I915_READ(MG_MISC_SUS0(tc_port));
2952         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2953                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2954                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2955                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2956                MG_MISC_SUS0_CFG_TRPWR_GATING |
2957                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2958                MG_MISC_SUS0_CFG_DGPWR_GATING;
2959         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2960 }
2961
2962 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2963 {
2964         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2965         enum port port = dig_port->base.port;
2966         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2967         u32 val;
2968         int ln;
2969
2970         if (tc_port == PORT_TC_NONE)
2971                 return;
2972
2973         for (ln = 0; ln < 2; ln++) {
2974                 val = I915_READ(MG_DP_MODE(ln, port));
2975                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2976                          MG_DP_MODE_CFG_TRPWR_GATING |
2977                          MG_DP_MODE_CFG_CLNPWR_GATING |
2978                          MG_DP_MODE_CFG_DIGPWR_GATING |
2979                          MG_DP_MODE_CFG_GAONPWR_GATING);
2980                 I915_WRITE(MG_DP_MODE(ln, port), val);
2981         }
2982
2983         val = I915_READ(MG_MISC_SUS0(tc_port));
2984         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2985                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
2986                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
2987                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
2988                  MG_MISC_SUS0_CFG_TRPWR_GATING |
2989                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
2990                  MG_MISC_SUS0_CFG_DGPWR_GATING);
2991         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2992 }
2993
2994 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2995 {
2996         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2997         enum port port = intel_dig_port->base.port;
2998         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2999         u32 ln0, ln1, lane_info;
3000
3001         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
3002                 return;
3003
3004         ln0 = I915_READ(MG_DP_MODE(0, port));
3005         ln1 = I915_READ(MG_DP_MODE(1, port));
3006
3007         switch (intel_dig_port->tc_type) {
3008         case TC_PORT_TYPEC:
3009                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3010                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3011
3012                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3013                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3014                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3015
3016                 switch (lane_info) {
3017                 case 0x1:
3018                 case 0x4:
3019                         break;
3020                 case 0x2:
3021                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3022                         break;
3023                 case 0x3:
3024                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3025                                MG_DP_MODE_CFG_DP_X2_MODE;
3026                         break;
3027                 case 0x8:
3028                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3029                         break;
3030                 case 0xC:
3031                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3032                                MG_DP_MODE_CFG_DP_X2_MODE;
3033                         break;
3034                 case 0xF:
3035                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3036                                MG_DP_MODE_CFG_DP_X2_MODE;
3037                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3038                                MG_DP_MODE_CFG_DP_X2_MODE;
3039                         break;
3040                 default:
3041                         MISSING_CASE(lane_info);
3042                 }
3043                 break;
3044
3045         case TC_PORT_LEGACY:
3046                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3047                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3048                 break;
3049
3050         default:
3051                 MISSING_CASE(intel_dig_port->tc_type);
3052                 return;
3053         }
3054
3055         I915_WRITE(MG_DP_MODE(0, port), ln0);
3056         I915_WRITE(MG_DP_MODE(1, port), ln1);
3057 }
3058
3059 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3060                                         const struct intel_crtc_state *crtc_state)
3061 {
3062         if (!crtc_state->fec_enable)
3063                 return;
3064
3065         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3066                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3067 }
3068
3069 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3070                                  const struct intel_crtc_state *crtc_state)
3071 {
3072         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3073         enum port port = encoder->port;
3074         u32 val;
3075
3076         if (!crtc_state->fec_enable)
3077                 return;
3078
3079         val = I915_READ(DP_TP_CTL(port));
3080         val |= DP_TP_CTL_FEC_ENABLE;
3081         I915_WRITE(DP_TP_CTL(port), val);
3082
3083         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3084                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3085                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3086                                     1))
3087                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3088 }
3089
3090 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3091                                         const struct intel_crtc_state *crtc_state)
3092 {
3093         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3094         enum port port = encoder->port;
3095         u32 val;
3096
3097         if (!crtc_state->fec_enable)
3098                 return;
3099
3100         val = I915_READ(DP_TP_CTL(port));
3101         val &= ~DP_TP_CTL_FEC_ENABLE;
3102         I915_WRITE(DP_TP_CTL(port), val);
3103         POSTING_READ(DP_TP_CTL(port));
3104 }
3105
3106 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3107                                     const struct intel_crtc_state *crtc_state,
3108                                     const struct drm_connector_state *conn_state)
3109 {
3110         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3111         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3112         enum port port = encoder->port;
3113         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3114         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3115         int level = intel_ddi_dp_level(intel_dp);
3116
3117         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3118
3119         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3120                                  crtc_state->lane_count, is_mst);
3121
3122         intel_edp_panel_on(intel_dp);
3123
3124         intel_ddi_clk_select(encoder, crtc_state);
3125
3126         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3127
3128         icl_program_mg_dp_mode(dig_port);
3129         icl_disable_phy_clock_gating(dig_port);
3130
3131         if (INTEL_GEN(dev_priv) >= 11)
3132                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3133                                         level, encoder->type);
3134         else if (IS_CANNONLAKE(dev_priv))
3135                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3136         else if (IS_GEN9_LP(dev_priv))
3137                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3138         else
3139                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3140
3141         if (intel_port_is_combophy(dev_priv, port)) {
3142                 bool lane_reversal =
3143                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3144
3145                 intel_combo_phy_power_up_lanes(dev_priv, port, false,
3146                                                crtc_state->lane_count,
3147                                                lane_reversal);
3148         }
3149
3150         intel_ddi_init_dp_buf_reg(encoder);
3151         if (!is_mst)
3152                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3153         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3154                                               true);
3155         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3156         intel_dp_start_link_train(intel_dp);
3157         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3158                 intel_dp_stop_link_train(intel_dp);
3159
3160         intel_ddi_enable_fec(encoder, crtc_state);
3161
3162         icl_enable_phy_clock_gating(dig_port);
3163
3164         if (!is_mst)
3165                 intel_ddi_enable_pipe_clock(crtc_state);
3166
3167         intel_dsc_enable(encoder, crtc_state);
3168 }
3169
3170 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3171                                       const struct intel_crtc_state *crtc_state,
3172                                       const struct drm_connector_state *conn_state)
3173 {
3174         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3175         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3176         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3177         enum port port = encoder->port;
3178         int level = intel_ddi_hdmi_level(dev_priv, port);
3179         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3180
3181         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3182         intel_ddi_clk_select(encoder, crtc_state);
3183
3184         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3185
3186         icl_program_mg_dp_mode(dig_port);
3187         icl_disable_phy_clock_gating(dig_port);
3188
3189         if (INTEL_GEN(dev_priv) >= 11)
3190                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3191                                         level, INTEL_OUTPUT_HDMI);
3192         else if (IS_CANNONLAKE(dev_priv))
3193                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3194         else if (IS_GEN9_LP(dev_priv))
3195                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3196         else
3197                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3198
3199         icl_enable_phy_clock_gating(dig_port);
3200
3201         if (IS_GEN9_BC(dev_priv))
3202                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3203
3204         intel_ddi_enable_pipe_clock(crtc_state);
3205
3206         intel_dig_port->set_infoframes(encoder,
3207                                        crtc_state->has_infoframe,
3208                                        crtc_state, conn_state);
3209 }
3210
3211 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3212                                  const struct intel_crtc_state *crtc_state,
3213                                  const struct drm_connector_state *conn_state)
3214 {
3215         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3216         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3217         enum pipe pipe = crtc->pipe;
3218
3219         /*
3220          * When called from DP MST code:
3221          * - conn_state will be NULL
3222          * - encoder will be the main encoder (ie. mst->primary)
3223          * - the main connector associated with this port
3224          *   won't be active or linked to a crtc
3225          * - crtc_state will be the state of the first stream to
3226          *   be activated on this port, and it may not be the same
3227          *   stream that will be deactivated last, but each stream
3228          *   should have a state that is identical when it comes to
3229          *   the DP link parameteres
3230          */
3231
3232         WARN_ON(crtc_state->has_pch_encoder);
3233
3234         if (INTEL_GEN(dev_priv) >= 11)
3235                 icl_map_plls_to_ports(encoder, crtc_state);
3236
3237         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3238
3239         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3240                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3241         } else {
3242                 struct intel_lspcon *lspcon =
3243                                 enc_to_intel_lspcon(&encoder->base);
3244
3245                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3246                 if (lspcon->active) {
3247                         struct intel_digital_port *dig_port =
3248                                         enc_to_dig_port(&encoder->base);
3249
3250                         dig_port->set_infoframes(encoder,
3251                                                  crtc_state->has_infoframe,
3252                                                  crtc_state, conn_state);
3253                 }
3254         }
3255 }
3256
3257 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3258                                   const struct intel_crtc_state *crtc_state)
3259 {
3260         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3261         enum port port = encoder->port;
3262         bool wait = false;
3263         u32 val;
3264
3265         val = I915_READ(DDI_BUF_CTL(port));
3266         if (val & DDI_BUF_CTL_ENABLE) {
3267                 val &= ~DDI_BUF_CTL_ENABLE;
3268                 I915_WRITE(DDI_BUF_CTL(port), val);
3269                 wait = true;
3270         }
3271
3272         val = I915_READ(DP_TP_CTL(port));
3273         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3274         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3275         I915_WRITE(DP_TP_CTL(port), val);
3276
3277         /* Disable FEC in DP Sink */
3278         intel_ddi_disable_fec_state(encoder, crtc_state);
3279
3280         if (wait)
3281                 intel_wait_ddi_buf_idle(dev_priv, port);
3282 }
3283
3284 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3285                                       const struct intel_crtc_state *old_crtc_state,
3286                                       const struct drm_connector_state *old_conn_state)
3287 {
3288         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3289         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3290         struct intel_dp *intel_dp = &dig_port->dp;
3291         bool is_mst = intel_crtc_has_type(old_crtc_state,
3292                                           INTEL_OUTPUT_DP_MST);
3293
3294         if (!is_mst) {
3295                 intel_ddi_disable_pipe_clock(old_crtc_state);
3296                 /*
3297                  * Power down sink before disabling the port, otherwise we end
3298                  * up getting interrupts from the sink on detecting link loss.
3299                  */
3300                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3301         }
3302
3303         intel_disable_ddi_buf(encoder, old_crtc_state);
3304
3305         intel_edp_panel_vdd_on(intel_dp);
3306         intel_edp_panel_off(intel_dp);
3307
3308         intel_display_power_put_unchecked(dev_priv,
3309                                           dig_port->ddi_io_power_domain);
3310
3311         intel_ddi_clk_disable(encoder);
3312 }
3313
3314 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3315                                         const struct intel_crtc_state *old_crtc_state,
3316                                         const struct drm_connector_state *old_conn_state)
3317 {
3318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3319         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3320         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3321
3322         dig_port->set_infoframes(encoder, false,
3323                                  old_crtc_state, old_conn_state);
3324
3325         intel_ddi_disable_pipe_clock(old_crtc_state);
3326
3327         intel_disable_ddi_buf(encoder, old_crtc_state);
3328
3329         intel_display_power_put_unchecked(dev_priv,
3330                                           dig_port->ddi_io_power_domain);
3331
3332         intel_ddi_clk_disable(encoder);
3333
3334         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3335 }
3336
3337 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3338                                    const struct intel_crtc_state *old_crtc_state,
3339                                    const struct drm_connector_state *old_conn_state)
3340 {
3341         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3342
3343         /*
3344          * When called from DP MST code:
3345          * - old_conn_state will be NULL
3346          * - encoder will be the main encoder (ie. mst->primary)
3347          * - the main connector associated with this port
3348          *   won't be active or linked to a crtc
3349          * - old_crtc_state will be the state of the last stream to
3350          *   be deactivated on this port, and it may not be the same
3351          *   stream that was activated last, but each stream
3352          *   should have a state that is identical when it comes to
3353          *   the DP link parameteres
3354          */
3355
3356         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3357                 intel_ddi_post_disable_hdmi(encoder,
3358                                             old_crtc_state, old_conn_state);
3359         else
3360                 intel_ddi_post_disable_dp(encoder,
3361                                           old_crtc_state, old_conn_state);
3362
3363         if (INTEL_GEN(dev_priv) >= 11)
3364                 icl_unmap_plls_to_ports(encoder);
3365 }
3366
3367 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3368                                 const struct intel_crtc_state *old_crtc_state,
3369                                 const struct drm_connector_state *old_conn_state)
3370 {
3371         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3372         u32 val;
3373
3374         /*
3375          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3376          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3377          * step 13 is the correct place for it. Step 18 is where it was
3378          * originally before the BUN.
3379          */
3380         val = I915_READ(FDI_RX_CTL(PIPE_A));
3381         val &= ~FDI_RX_ENABLE;
3382         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3383
3384         intel_disable_ddi_buf(encoder, old_crtc_state);
3385         intel_ddi_clk_disable(encoder);
3386
3387         val = I915_READ(FDI_RX_MISC(PIPE_A));
3388         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3389         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3390         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3391
3392         val = I915_READ(FDI_RX_CTL(PIPE_A));
3393         val &= ~FDI_PCDCLK;
3394         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3395
3396         val = I915_READ(FDI_RX_CTL(PIPE_A));
3397         val &= ~FDI_RX_PLL_ENABLE;
3398         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3399 }
3400
3401 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3402                                 const struct intel_crtc_state *crtc_state,
3403                                 const struct drm_connector_state *conn_state)
3404 {
3405         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3406         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3407         enum port port = encoder->port;
3408
3409         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3410                 intel_dp_stop_link_train(intel_dp);
3411
3412         intel_edp_backlight_on(crtc_state, conn_state);
3413         intel_psr_enable(intel_dp, crtc_state);
3414         intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
3415         intel_edp_drrs_enable(intel_dp, crtc_state);
3416
3417         if (crtc_state->has_audio)
3418                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3419 }
3420
3421 static i915_reg_t
3422 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3423                                enum port port)
3424 {
3425         static const i915_reg_t regs[] = {
3426                 [PORT_A] = CHICKEN_TRANS_EDP,
3427                 [PORT_B] = CHICKEN_TRANS_A,
3428                 [PORT_C] = CHICKEN_TRANS_B,
3429                 [PORT_D] = CHICKEN_TRANS_C,
3430                 [PORT_E] = CHICKEN_TRANS_A,
3431         };
3432
3433         WARN_ON(INTEL_GEN(dev_priv) < 9);
3434
3435         if (WARN_ON(port < PORT_A || port > PORT_E))
3436                 port = PORT_A;
3437
3438         return regs[port];
3439 }
3440
3441 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3442                                   const struct intel_crtc_state *crtc_state,
3443                                   const struct drm_connector_state *conn_state)
3444 {
3445         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3446         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3447         struct drm_connector *connector = conn_state->connector;
3448         enum port port = encoder->port;
3449
3450         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3451                                                crtc_state->hdmi_high_tmds_clock_ratio,
3452                                                crtc_state->hdmi_scrambling))
3453                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3454                           connector->base.id, connector->name);
3455
3456         /* Display WA #1143: skl,kbl,cfl */
3457         if (IS_GEN9_BC(dev_priv)) {
3458                 /*
3459                  * For some reason these chicken bits have been
3460                  * stuffed into a transcoder register, event though
3461                  * the bits affect a specific DDI port rather than
3462                  * a specific transcoder.
3463                  */
3464                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3465                 u32 val;
3466
3467                 val = I915_READ(reg);
3468
3469                 if (port == PORT_E)
3470                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3471                                 DDIE_TRAINING_OVERRIDE_VALUE;
3472                 else
3473                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3474                                 DDI_TRAINING_OVERRIDE_VALUE;
3475
3476                 I915_WRITE(reg, val);
3477                 POSTING_READ(reg);
3478
3479                 udelay(1);
3480
3481                 if (port == PORT_E)
3482                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3483                                  DDIE_TRAINING_OVERRIDE_VALUE);
3484                 else
3485                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3486                                  DDI_TRAINING_OVERRIDE_VALUE);
3487
3488                 I915_WRITE(reg, val);
3489         }
3490
3491         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3492          * are ignored so nothing special needs to be done besides
3493          * enabling the port.
3494          */
3495         I915_WRITE(DDI_BUF_CTL(port),
3496                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3497
3498         if (crtc_state->has_audio)
3499                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3500 }
3501
3502 static void intel_enable_ddi(struct intel_encoder *encoder,
3503                              const struct intel_crtc_state *crtc_state,
3504                              const struct drm_connector_state *conn_state)
3505 {
3506         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3507                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3508         else
3509                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3510
3511         /* Enable hdcp if it's desired */
3512         if (conn_state->content_protection ==
3513             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3514                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3515 }
3516
3517 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3518                                  const struct intel_crtc_state *old_crtc_state,
3519                                  const struct drm_connector_state *old_conn_state)
3520 {
3521         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3522
3523         intel_dp->link_trained = false;
3524
3525         if (old_crtc_state->has_audio)
3526                 intel_audio_codec_disable(encoder,
3527                                           old_crtc_state, old_conn_state);
3528
3529         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3530         intel_psr_disable(intel_dp, old_crtc_state);
3531         intel_edp_backlight_off(old_conn_state);
3532         /* Disable the decompression in DP Sink */
3533         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3534                                               false);
3535 }
3536
3537 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3538                                    const struct intel_crtc_state *old_crtc_state,
3539                                    const struct drm_connector_state *old_conn_state)
3540 {
3541         struct drm_connector *connector = old_conn_state->connector;
3542
3543         if (old_crtc_state->has_audio)
3544                 intel_audio_codec_disable(encoder,
3545                                           old_crtc_state, old_conn_state);
3546
3547         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3548                                                false, false))
3549                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3550                               connector->base.id, connector->name);
3551 }
3552
3553 static void intel_disable_ddi(struct intel_encoder *encoder,
3554                               const struct intel_crtc_state *old_crtc_state,
3555                               const struct drm_connector_state *old_conn_state)
3556 {
3557         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3558
3559         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3560                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3561         else
3562                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3563 }
3564
3565 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3566                                      const struct intel_crtc_state *crtc_state,
3567                                      const struct drm_connector_state *conn_state)
3568 {
3569         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3570
3571         intel_ddi_set_pipe_settings(crtc_state);
3572
3573         intel_psr_update(intel_dp, crtc_state);
3574         intel_edp_drrs_enable(intel_dp, crtc_state);
3575
3576         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3577 }
3578
3579 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3580                                   const struct intel_crtc_state *crtc_state,
3581                                   const struct drm_connector_state *conn_state)
3582 {
3583         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3584                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3585
3586         if (conn_state->content_protection ==
3587             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3588                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3589         else if (conn_state->content_protection ==
3590                  DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3591                 intel_hdcp_disable(to_intel_connector(conn_state->connector));
3592 }
3593
3594 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3595                                          const struct intel_crtc_state *pipe_config,
3596                                          enum port port)
3597 {
3598         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3599         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3600         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3601         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3602         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3603
3604         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3605         switch (pipe_config->lane_count) {
3606         case 1:
3607                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3608                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3609                 break;
3610         case 2:
3611                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3612                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3613                 break;
3614         case 4:
3615                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3616                 break;
3617         default:
3618                 MISSING_CASE(pipe_config->lane_count);
3619         }
3620         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3621 }
3622
3623 static void
3624 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3625                          const struct intel_crtc_state *crtc_state,
3626                          const struct drm_connector_state *conn_state)
3627 {
3628         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3629         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3630         enum port port = encoder->port;
3631
3632         if (intel_crtc_has_dp_encoder(crtc_state) ||
3633             intel_port_is_tc(dev_priv, encoder->port))
3634                 intel_display_power_get(dev_priv,
3635                                         intel_ddi_main_link_aux_domain(dig_port));
3636
3637         if (IS_GEN9_LP(dev_priv))
3638                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3639                                                 crtc_state->lane_lat_optim_mask);
3640
3641         /*
3642          * Program the lane count for static/dynamic connections on Type-C ports.
3643          * Skip this step for TBT.
3644          */
3645         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3646             dig_port->tc_type == TC_PORT_TBT)
3647                 return;
3648
3649         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3650 }
3651
3652 static void
3653 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3654                            const struct intel_crtc_state *crtc_state,
3655                            const struct drm_connector_state *conn_state)
3656 {
3657         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3658         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3659
3660         if (intel_crtc_has_dp_encoder(crtc_state) ||
3661             intel_port_is_tc(dev_priv, encoder->port))
3662                 intel_display_power_put_unchecked(dev_priv,
3663                                                   intel_ddi_main_link_aux_domain(dig_port));
3664 }
3665
3666 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3667 {
3668         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3669         struct drm_i915_private *dev_priv =
3670                 to_i915(intel_dig_port->base.base.dev);
3671         enum port port = intel_dig_port->base.port;
3672         u32 val;
3673         bool wait = false;
3674
3675         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3676                 val = I915_READ(DDI_BUF_CTL(port));
3677                 if (val & DDI_BUF_CTL_ENABLE) {
3678                         val &= ~DDI_BUF_CTL_ENABLE;
3679                         I915_WRITE(DDI_BUF_CTL(port), val);
3680                         wait = true;
3681                 }
3682
3683                 val = I915_READ(DP_TP_CTL(port));
3684                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3685                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3686                 I915_WRITE(DP_TP_CTL(port), val);
3687                 POSTING_READ(DP_TP_CTL(port));
3688
3689                 if (wait)
3690                         intel_wait_ddi_buf_idle(dev_priv, port);
3691         }
3692
3693         val = DP_TP_CTL_ENABLE |
3694               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3695         if (intel_dp->link_mst)
3696                 val |= DP_TP_CTL_MODE_MST;
3697         else {
3698                 val |= DP_TP_CTL_MODE_SST;
3699                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3700                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3701         }
3702         I915_WRITE(DP_TP_CTL(port), val);
3703         POSTING_READ(DP_TP_CTL(port));
3704
3705         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3706         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3707         POSTING_READ(DDI_BUF_CTL(port));
3708
3709         udelay(600);
3710 }
3711
3712 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3713                                        enum transcoder cpu_transcoder)
3714 {
3715         if (cpu_transcoder == TRANSCODER_EDP)
3716                 return false;
3717
3718         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3719                 return false;
3720
3721         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3722                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3723 }
3724
3725 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3726                                          struct intel_crtc_state *crtc_state)
3727 {
3728         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3729                 crtc_state->min_voltage_level = 1;
3730         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3731                 crtc_state->min_voltage_level = 2;
3732 }
3733
3734 void intel_ddi_get_config(struct intel_encoder *encoder,
3735                           struct intel_crtc_state *pipe_config)
3736 {
3737         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3738         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3739         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3740         struct intel_digital_port *intel_dig_port;
3741         u32 temp, flags = 0;
3742
3743         /* XXX: DSI transcoder paranoia */
3744         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3745                 return;
3746
3747         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3748         if (temp & TRANS_DDI_PHSYNC)
3749                 flags |= DRM_MODE_FLAG_PHSYNC;
3750         else
3751                 flags |= DRM_MODE_FLAG_NHSYNC;
3752         if (temp & TRANS_DDI_PVSYNC)
3753                 flags |= DRM_MODE_FLAG_PVSYNC;
3754         else
3755                 flags |= DRM_MODE_FLAG_NVSYNC;
3756
3757         pipe_config->base.adjusted_mode.flags |= flags;
3758
3759         switch (temp & TRANS_DDI_BPC_MASK) {
3760         case TRANS_DDI_BPC_6:
3761                 pipe_config->pipe_bpp = 18;
3762                 break;
3763         case TRANS_DDI_BPC_8:
3764                 pipe_config->pipe_bpp = 24;
3765                 break;
3766         case TRANS_DDI_BPC_10:
3767                 pipe_config->pipe_bpp = 30;
3768                 break;
3769         case TRANS_DDI_BPC_12:
3770                 pipe_config->pipe_bpp = 36;
3771                 break;
3772         default:
3773                 break;
3774         }
3775
3776         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3777         case TRANS_DDI_MODE_SELECT_HDMI:
3778                 pipe_config->has_hdmi_sink = true;
3779                 intel_dig_port = enc_to_dig_port(&encoder->base);
3780
3781                 pipe_config->infoframes.enable |=
3782                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3783
3784                 if (pipe_config->infoframes.enable)
3785                         pipe_config->has_infoframe = true;
3786
3787                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3788                         pipe_config->hdmi_scrambling = true;
3789                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3790                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3791                 /* fall through */
3792         case TRANS_DDI_MODE_SELECT_DVI:
3793                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3794                 pipe_config->lane_count = 4;
3795                 break;
3796         case TRANS_DDI_MODE_SELECT_FDI:
3797                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3798                 break;
3799         case TRANS_DDI_MODE_SELECT_DP_SST:
3800                 if (encoder->type == INTEL_OUTPUT_EDP)
3801                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3802                 else
3803                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3804                 pipe_config->lane_count =
3805                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3806                 intel_dp_get_m_n(intel_crtc, pipe_config);
3807                 break;
3808         case TRANS_DDI_MODE_SELECT_DP_MST:
3809                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3810                 pipe_config->lane_count =
3811                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3812                 intel_dp_get_m_n(intel_crtc, pipe_config);
3813                 break;
3814         default:
3815                 break;
3816         }
3817
3818         pipe_config->has_audio =
3819                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3820
3821         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3822             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3823                 /*
3824                  * This is a big fat ugly hack.
3825                  *
3826                  * Some machines in UEFI boot mode provide us a VBT that has 18
3827                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3828                  * unknown we fail to light up. Yet the same BIOS boots up with
3829                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3830                  * max, not what it tells us to use.
3831                  *
3832                  * Note: This will still be broken if the eDP panel is not lit
3833                  * up by the BIOS, and thus we can't get the mode at module
3834                  * load.
3835                  */
3836                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3837                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3838                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3839         }
3840
3841         intel_ddi_clock_get(encoder, pipe_config);
3842
3843         if (IS_GEN9_LP(dev_priv))
3844                 pipe_config->lane_lat_optim_mask =
3845                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3846
3847         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3848
3849         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3850
3851         intel_read_infoframe(encoder, pipe_config,
3852                              HDMI_INFOFRAME_TYPE_AVI,
3853                              &pipe_config->infoframes.avi);
3854         intel_read_infoframe(encoder, pipe_config,
3855                              HDMI_INFOFRAME_TYPE_SPD,
3856                              &pipe_config->infoframes.spd);
3857         intel_read_infoframe(encoder, pipe_config,
3858                              HDMI_INFOFRAME_TYPE_VENDOR,
3859                              &pipe_config->infoframes.hdmi);
3860         intel_read_infoframe(encoder, pipe_config,
3861                              HDMI_INFOFRAME_TYPE_DRM,
3862                              &pipe_config->infoframes.drm);
3863 }
3864
3865 static enum intel_output_type
3866 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3867                               struct intel_crtc_state *crtc_state,
3868                               struct drm_connector_state *conn_state)
3869 {
3870         switch (conn_state->connector->connector_type) {
3871         case DRM_MODE_CONNECTOR_HDMIA:
3872                 return INTEL_OUTPUT_HDMI;
3873         case DRM_MODE_CONNECTOR_eDP:
3874                 return INTEL_OUTPUT_EDP;
3875         case DRM_MODE_CONNECTOR_DisplayPort:
3876                 return INTEL_OUTPUT_DP;
3877         default:
3878                 MISSING_CASE(conn_state->connector->connector_type);
3879                 return INTEL_OUTPUT_UNUSED;
3880         }
3881 }
3882
3883 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3884                                     struct intel_crtc_state *pipe_config,
3885                                     struct drm_connector_state *conn_state)
3886 {
3887         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3888         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3889         enum port port = encoder->port;
3890         int ret;
3891
3892         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3893                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3894
3895         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3896                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3897         else
3898                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3899         if (ret)
3900                 return ret;
3901
3902         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3903             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3904                 pipe_config->pch_pfit.force_thru =
3905                         pipe_config->pch_pfit.enabled ||
3906                         pipe_config->crc_enabled;
3907
3908         if (IS_GEN9_LP(dev_priv))
3909                 pipe_config->lane_lat_optim_mask =
3910                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3911
3912         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3913
3914         return 0;
3915 }
3916
3917 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3918 {
3919         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3920         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3921
3922         intel_dp_encoder_suspend(encoder);
3923
3924         /*
3925          * TODO: disconnect also from USB DP alternate mode once we have a
3926          * way to handle the modeset restore in that mode during resume
3927          * even if the sink has disappeared while being suspended.
3928          */
3929         if (dig_port->tc_legacy_port)
3930                 icl_tc_phy_disconnect(i915, dig_port);
3931 }
3932
3933 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3934 {
3935         struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3936         struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3937
3938         if (intel_port_is_tc(i915, dig_port->base.port))
3939                 intel_digital_port_connected(&dig_port->base);
3940
3941         intel_dp_encoder_reset(drm_encoder);
3942 }
3943
3944 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3945 {
3946         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3947         struct drm_i915_private *i915 = to_i915(encoder->dev);
3948
3949         intel_dp_encoder_flush_work(encoder);
3950
3951         if (intel_port_is_tc(i915, dig_port->base.port))
3952                 icl_tc_phy_disconnect(i915, dig_port);
3953
3954         drm_encoder_cleanup(encoder);
3955         kfree(dig_port);
3956 }
3957
3958 static const struct drm_encoder_funcs intel_ddi_funcs = {
3959         .reset = intel_ddi_encoder_reset,
3960         .destroy = intel_ddi_encoder_destroy,
3961 };
3962
3963 static struct intel_connector *
3964 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3965 {
3966         struct intel_connector *connector;
3967         enum port port = intel_dig_port->base.port;
3968
3969         connector = intel_connector_alloc();
3970         if (!connector)
3971                 return NULL;
3972
3973         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3974         intel_dig_port->dp.prepare_link_retrain =
3975                 intel_ddi_prepare_link_retrain;
3976
3977         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3978                 kfree(connector);
3979                 return NULL;
3980         }
3981
3982         return connector;
3983 }
3984
3985 static int modeset_pipe(struct drm_crtc *crtc,
3986                         struct drm_modeset_acquire_ctx *ctx)
3987 {
3988         struct drm_atomic_state *state;
3989         struct drm_crtc_state *crtc_state;
3990         int ret;
3991
3992         state = drm_atomic_state_alloc(crtc->dev);
3993         if (!state)
3994                 return -ENOMEM;
3995
3996         state->acquire_ctx = ctx;
3997
3998         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3999         if (IS_ERR(crtc_state)) {
4000                 ret = PTR_ERR(crtc_state);
4001                 goto out;
4002         }
4003
4004         crtc_state->connectors_changed = true;
4005
4006         ret = drm_atomic_commit(state);
4007 out:
4008         drm_atomic_state_put(state);
4009
4010         return ret;
4011 }
4012
4013 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4014                                  struct drm_modeset_acquire_ctx *ctx)
4015 {
4016         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4017         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4018         struct intel_connector *connector = hdmi->attached_connector;
4019         struct i2c_adapter *adapter =
4020                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4021         struct drm_connector_state *conn_state;
4022         struct intel_crtc_state *crtc_state;
4023         struct intel_crtc *crtc;
4024         u8 config;
4025         int ret;
4026
4027         if (!connector || connector->base.status != connector_status_connected)
4028                 return 0;
4029
4030         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4031                                ctx);
4032         if (ret)
4033                 return ret;
4034
4035         conn_state = connector->base.state;
4036
4037         crtc = to_intel_crtc(conn_state->crtc);
4038         if (!crtc)
4039                 return 0;
4040
4041         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4042         if (ret)
4043                 return ret;
4044
4045         crtc_state = to_intel_crtc_state(crtc->base.state);
4046
4047         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4048
4049         if (!crtc_state->base.active)
4050                 return 0;
4051
4052         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4053             !crtc_state->hdmi_scrambling)
4054                 return 0;
4055
4056         if (conn_state->commit &&
4057             !try_wait_for_completion(&conn_state->commit->hw_done))
4058                 return 0;
4059
4060         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4061         if (ret < 0) {
4062                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4063                 return 0;
4064         }
4065
4066         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4067             crtc_state->hdmi_high_tmds_clock_ratio &&
4068             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4069             crtc_state->hdmi_scrambling)
4070                 return 0;
4071
4072         /*
4073          * HDMI 2.0 says that one should not send scrambled data
4074          * prior to configuring the sink scrambling, and that
4075          * TMDS clock/data transmission should be suspended when
4076          * changing the TMDS clock rate in the sink. So let's
4077          * just do a full modeset here, even though some sinks
4078          * would be perfectly happy if were to just reconfigure
4079          * the SCDC settings on the fly.
4080          */
4081         return modeset_pipe(&crtc->base, ctx);
4082 }
4083
4084 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4085                               struct intel_connector *connector)
4086 {
4087         struct drm_modeset_acquire_ctx ctx;
4088         bool changed;
4089         int ret;
4090
4091         changed = intel_encoder_hotplug(encoder, connector);
4092
4093         drm_modeset_acquire_init(&ctx, 0);
4094
4095         for (;;) {
4096                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4097                         ret = intel_hdmi_reset_link(encoder, &ctx);
4098                 else
4099                         ret = intel_dp_retrain_link(encoder, &ctx);
4100
4101                 if (ret == -EDEADLK) {
4102                         drm_modeset_backoff(&ctx);
4103                         continue;
4104                 }
4105
4106                 break;
4107         }
4108
4109         drm_modeset_drop_locks(&ctx);
4110         drm_modeset_acquire_fini(&ctx);
4111         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4112
4113         return changed;
4114 }
4115
4116 static struct intel_connector *
4117 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4118 {
4119         struct intel_connector *connector;
4120         enum port port = intel_dig_port->base.port;
4121
4122         connector = intel_connector_alloc();
4123         if (!connector)
4124                 return NULL;
4125
4126         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4127         intel_hdmi_init_connector(intel_dig_port, connector);
4128
4129         return connector;
4130 }
4131
4132 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4133 {
4134         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4135
4136         if (dport->base.port != PORT_A)
4137                 return false;
4138
4139         if (dport->saved_port_bits & DDI_A_4_LANES)
4140                 return false;
4141
4142         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4143          *                     supported configuration
4144          */
4145         if (IS_GEN9_LP(dev_priv))
4146                 return true;
4147
4148         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4149          *             one who does also have a full A/E split called
4150          *             DDI_F what makes DDI_E useless. However for this
4151          *             case let's trust VBT info.
4152          */
4153         if (IS_CANNONLAKE(dev_priv) &&
4154             !intel_bios_is_port_present(dev_priv, PORT_E))
4155                 return true;
4156
4157         return false;
4158 }
4159
4160 static int
4161 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4162 {
4163         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4164         enum port port = intel_dport->base.port;
4165         int max_lanes = 4;
4166
4167         if (INTEL_GEN(dev_priv) >= 11)
4168                 return max_lanes;
4169
4170         if (port == PORT_A || port == PORT_E) {
4171                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4172                         max_lanes = port == PORT_A ? 4 : 0;
4173                 else
4174                         /* Both A and E share 2 lanes */
4175                         max_lanes = 2;
4176         }
4177
4178         /*
4179          * Some BIOS might fail to set this bit on port A if eDP
4180          * wasn't lit up at boot.  Force this bit set when needed
4181          * so we use the proper lane count for our calculations.
4182          */
4183         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4184                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4185                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4186                 max_lanes = 4;
4187         }
4188
4189         return max_lanes;
4190 }
4191
4192 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4193 {
4194         struct ddi_vbt_port_info *port_info =
4195                 &dev_priv->vbt.ddi_port_info[port];
4196         struct intel_digital_port *intel_dig_port;
4197         struct intel_encoder *intel_encoder;
4198         struct drm_encoder *encoder;
4199         bool init_hdmi, init_dp, init_lspcon = false;
4200         enum pipe pipe;
4201
4202         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4203         init_dp = port_info->supports_dp;
4204
4205         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4206                 /*
4207                  * Lspcon device needs to be driven with DP connector
4208                  * with special detection sequence. So make sure DP
4209                  * is initialized before lspcon.
4210                  */
4211                 init_dp = true;
4212                 init_lspcon = true;
4213                 init_hdmi = false;
4214                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4215         }
4216
4217         if (!init_dp && !init_hdmi) {
4218                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4219                               port_name(port));
4220                 return;
4221         }
4222
4223         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4224         if (!intel_dig_port)
4225                 return;
4226
4227         intel_encoder = &intel_dig_port->base;
4228         encoder = &intel_encoder->base;
4229
4230         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4231                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4232
4233         intel_encoder->hotplug = intel_ddi_hotplug;
4234         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4235         intel_encoder->compute_config = intel_ddi_compute_config;
4236         intel_encoder->enable = intel_enable_ddi;
4237         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4238         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4239         intel_encoder->pre_enable = intel_ddi_pre_enable;
4240         intel_encoder->disable = intel_disable_ddi;
4241         intel_encoder->post_disable = intel_ddi_post_disable;
4242         intel_encoder->update_pipe = intel_ddi_update_pipe;
4243         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4244         intel_encoder->get_config = intel_ddi_get_config;
4245         intel_encoder->suspend = intel_ddi_encoder_suspend;
4246         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4247         intel_encoder->type = INTEL_OUTPUT_DDI;
4248         intel_encoder->power_domain = intel_port_to_power_domain(port);
4249         intel_encoder->port = port;
4250         intel_encoder->cloneable = 0;
4251         for_each_pipe(dev_priv, pipe)
4252                 intel_encoder->crtc_mask |= BIT(pipe);
4253
4254         if (INTEL_GEN(dev_priv) >= 11)
4255                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4256                         DDI_BUF_PORT_REVERSAL;
4257         else
4258                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4259                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4260         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4261         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4262         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4263
4264         intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4265                                          !port_info->supports_typec_usb &&
4266                                          !port_info->supports_tbt;
4267
4268         switch (port) {
4269         case PORT_A:
4270                 intel_dig_port->ddi_io_power_domain =
4271                         POWER_DOMAIN_PORT_DDI_A_IO;
4272                 break;
4273         case PORT_B:
4274                 intel_dig_port->ddi_io_power_domain =
4275                         POWER_DOMAIN_PORT_DDI_B_IO;
4276                 break;
4277         case PORT_C:
4278                 intel_dig_port->ddi_io_power_domain =
4279                         POWER_DOMAIN_PORT_DDI_C_IO;
4280                 break;
4281         case PORT_D:
4282                 intel_dig_port->ddi_io_power_domain =
4283                         POWER_DOMAIN_PORT_DDI_D_IO;
4284                 break;
4285         case PORT_E:
4286                 intel_dig_port->ddi_io_power_domain =
4287                         POWER_DOMAIN_PORT_DDI_E_IO;
4288                 break;
4289         case PORT_F:
4290                 intel_dig_port->ddi_io_power_domain =
4291                         POWER_DOMAIN_PORT_DDI_F_IO;
4292                 break;
4293         default:
4294                 MISSING_CASE(port);
4295         }
4296
4297         if (init_dp) {
4298                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4299                         goto err;
4300
4301                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4302         }
4303
4304         /* In theory we don't need the encoder->type check, but leave it just in
4305          * case we have some really bad VBTs... */
4306         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4307                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4308                         goto err;
4309         }
4310
4311         if (init_lspcon) {
4312                 if (lspcon_init(intel_dig_port))
4313                         /* TODO: handle hdmi info frame part */
4314                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4315                                 port_name(port));
4316                 else
4317                         /*
4318                          * LSPCON init faied, but DP init was success, so
4319                          * lets try to drive as DP++ port.
4320                          */
4321                         DRM_ERROR("LSPCON init failed on port %c\n",
4322                                 port_name(port));
4323         }
4324
4325         intel_infoframe_init(intel_dig_port);
4326
4327         if (intel_port_is_tc(dev_priv, port))
4328                 intel_digital_port_connected(intel_encoder);
4329
4330         return;
4331
4332 err:
4333         drm_encoder_cleanup(encoder);
4334         kfree(intel_dig_port);
4335 }