drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_link_training.h"
  38 #include "intel_dpio_phy.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_tc.h"
  49 #include "intel_vdsc.h"
  50
  51 struct ddi_buf_trans {
  52         u32 trans1;     /* balance leg enable, de-emph level */
  53         u32 trans2;     /* vref sel, vswing */
  54         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  55 };
  56
  57 static const u8 index_to_dp_signal_levels[] = {
  58         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  59         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  60         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  61         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  62         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  63         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  64         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  65         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  66         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  67         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68 };
  69
  70 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  71  * them for both DP and FDI transports, allowing those ports to
  72  * automatically adapt to HDMI connections as well
  73  */
  74 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  75         { 0x00FFFFFF, 0x0006000E, 0x0 },
  76         { 0x00D75FFF, 0x0005000A, 0x0 },
  77         { 0x00C30FFF, 0x00040006, 0x0 },
  78         { 0x80AAAFFF, 0x000B0000, 0x0 },
  79         { 0x00FFFFFF, 0x0005000A, 0x0 },
  80         { 0x00D75FFF, 0x000C0004, 0x0 },
  81         { 0x80C30FFF, 0x000B0000, 0x0 },
  82         { 0x00FFFFFF, 0x00040006, 0x0 },
  83         { 0x80D75FFF, 0x000B0000, 0x0 },
  84 };
  85
  86 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  87         { 0x00FFFFFF, 0x0007000E, 0x0 },
  88         { 0x00D75FFF, 0x000F000A, 0x0 },
  89         { 0x00C30FFF, 0x00060006, 0x0 },
  90         { 0x00AAAFFF, 0x001E0000, 0x0 },
  91         { 0x00FFFFFF, 0x000F000A, 0x0 },
  92         { 0x00D75FFF, 0x00160004, 0x0 },
  93         { 0x00C30FFF, 0x001E0000, 0x0 },
  94         { 0x00FFFFFF, 0x00060006, 0x0 },
  95         { 0x00D75FFF, 0x001E0000, 0x0 },
  96 };
  97
  98 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  99                                         /* Idx  NT mV d T mV d  db      */
 100         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 101         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 102         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 103         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 104         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 105         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 106         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 107         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 108         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 109         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 110         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 111         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 112 };
 113
 114 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 115         { 0x00FFFFFF, 0x00000012, 0x0 },
 116         { 0x00EBAFFF, 0x00020011, 0x0 },
 117         { 0x00C71FFF, 0x0006000F, 0x0 },
 118         { 0x00AAAFFF, 0x000E000A, 0x0 },
 119         { 0x00FFFFFF, 0x00020011, 0x0 },
 120         { 0x00DB6FFF, 0x0005000F, 0x0 },
 121         { 0x00BEEFFF, 0x000A000C, 0x0 },
 122         { 0x00FFFFFF, 0x0005000F, 0x0 },
 123         { 0x00DB6FFF, 0x000A000C, 0x0 },
 124 };
 125
 126 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 127         { 0x00FFFFFF, 0x0007000E, 0x0 },
 128         { 0x00D75FFF, 0x000E000A, 0x0 },
 129         { 0x00BEFFFF, 0x00140006, 0x0 },
 130         { 0x80B2CFFF, 0x001B0002, 0x0 },
 131         { 0x00FFFFFF, 0x000E000A, 0x0 },
 132         { 0x00DB6FFF, 0x00160005, 0x0 },
 133         { 0x80C71FFF, 0x001A0002, 0x0 },
 134         { 0x00F7DFFF, 0x00180004, 0x0 },
 135         { 0x80D75FFF, 0x001B0002, 0x0 },
 136 };
 137
 138 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 139         { 0x00FFFFFF, 0x0001000E, 0x0 },
 140         { 0x00D75FFF, 0x0004000A, 0x0 },
 141         { 0x00C30FFF, 0x00070006, 0x0 },
 142         { 0x00AAAFFF, 0x000C0000, 0x0 },
 143         { 0x00FFFFFF, 0x0004000A, 0x0 },
 144         { 0x00D75FFF, 0x00090004, 0x0 },
 145         { 0x00C30FFF, 0x000C0000, 0x0 },
 146         { 0x00FFFFFF, 0x00070006, 0x0 },
 147         { 0x00D75FFF, 0x000C0000, 0x0 },
 148 };
 149
 150 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 151                                         /* Idx  NT mV d T mV df db      */
 152         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 153         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 154         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 155         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 156         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 157         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 158         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 159         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 160         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 161         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 162 };
 163
 164 /* Skylake H and S */
 165 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 166         { 0x00002016, 0x000000A0, 0x0 },
 167         { 0x00005012, 0x0000009B, 0x0 },
 168         { 0x00007011, 0x00000088, 0x0 },
 169         { 0x80009010, 0x000000C0, 0x1 },
 170         { 0x00002016, 0x0000009B, 0x0 },
 171         { 0x00005012, 0x00000088, 0x0 },
 172         { 0x80007011, 0x000000C0, 0x1 },
 173         { 0x00002016, 0x000000DF, 0x0 },
 174         { 0x80005012, 0x000000C0, 0x1 },
 175 };
 176
 177 /* Skylake U */
 178 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 179         { 0x0000201B, 0x000000A2, 0x0 },
 180         { 0x00005012, 0x00000088, 0x0 },
 181         { 0x80007011, 0x000000CD, 0x1 },
 182         { 0x80009010, 0x000000C0, 0x1 },
 183         { 0x0000201B, 0x0000009D, 0x0 },
 184         { 0x80005012, 0x000000C0, 0x1 },
 185         { 0x80007011, 0x000000C0, 0x1 },
 186         { 0x00002016, 0x00000088, 0x0 },
 187         { 0x80005012, 0x000000C0, 0x1 },
 188 };
 189
 190 /* Skylake Y */
 191 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 192         { 0x00000018, 0x000000A2, 0x0 },
 193         { 0x00005012, 0x00000088, 0x0 },
 194         { 0x80007011, 0x000000CD, 0x3 },
 195         { 0x80009010, 0x000000C0, 0x3 },
 196         { 0x00000018, 0x0000009D, 0x0 },
 197         { 0x80005012, 0x000000C0, 0x3 },
 198         { 0x80007011, 0x000000C0, 0x3 },
 199         { 0x00000018, 0x00000088, 0x0 },
 200         { 0x80005012, 0x000000C0, 0x3 },
 201 };
 202
 203 /* Kabylake H and S */
 204 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 205         { 0x00002016, 0x000000A0, 0x0 },
 206         { 0x00005012, 0x0000009B, 0x0 },
 207         { 0x00007011, 0x00000088, 0x0 },
 208         { 0x80009010, 0x000000C0, 0x1 },
 209         { 0x00002016, 0x0000009B, 0x0 },
 210         { 0x00005012, 0x00000088, 0x0 },
 211         { 0x80007011, 0x000000C0, 0x1 },
 212         { 0x00002016, 0x00000097, 0x0 },
 213         { 0x80005012, 0x000000C0, 0x1 },
 214 };
 215
 216 /* Kabylake U */
 217 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 218         { 0x0000201B, 0x000000A1, 0x0 },
 219         { 0x00005012, 0x00000088, 0x0 },
 220         { 0x80007011, 0x000000CD, 0x3 },
 221         { 0x80009010, 0x000000C0, 0x3 },
 222         { 0x0000201B, 0x0000009D, 0x0 },
 223         { 0x80005012, 0x000000C0, 0x3 },
 224         { 0x80007011, 0x000000C0, 0x3 },
 225         { 0x00002016, 0x0000004F, 0x0 },
 226         { 0x80005012, 0x000000C0, 0x3 },
 227 };
 228
 229 /* Kabylake Y */
 230 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 231         { 0x00001017, 0x000000A1, 0x0 },
 232         { 0x00005012, 0x00000088, 0x0 },
 233         { 0x80007011, 0x000000CD, 0x3 },
 234         { 0x8000800F, 0x000000C0, 0x3 },
 235         { 0x00001017, 0x0000009D, 0x0 },
 236         { 0x80005012, 0x000000C0, 0x3 },
 237         { 0x80007011, 0x000000C0, 0x3 },
 238         { 0x00001017, 0x0000004C, 0x0 },
 239         { 0x80005012, 0x000000C0, 0x3 },
 240 };
 241
 242 /*
 243  * Skylake/Kabylake H and S
 244  * eDP 1.4 low vswing translation parameters
 245  */
 246 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 247         { 0x00000018, 0x000000A8, 0x0 },
 248         { 0x00004013, 0x000000A9, 0x0 },
 249         { 0x00007011, 0x000000A2, 0x0 },
 250         { 0x00009010, 0x0000009C, 0x0 },
 251         { 0x00000018, 0x000000A9, 0x0 },
 252         { 0x00006013, 0x000000A2, 0x0 },
 253         { 0x00007011, 0x000000A6, 0x0 },
 254         { 0x00000018, 0x000000AB, 0x0 },
 255         { 0x00007013, 0x0000009F, 0x0 },
 256         { 0x00000018, 0x000000DF, 0x0 },
 257 };
 258
 259 /*
 260  * Skylake/Kabylake U
 261  * eDP 1.4 low vswing translation parameters
 262  */
 263 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 264         { 0x00000018, 0x000000A8, 0x0 },
 265         { 0x00004013, 0x000000A9, 0x0 },
 266         { 0x00007011, 0x000000A2, 0x0 },
 267         { 0x00009010, 0x0000009C, 0x0 },
 268         { 0x00000018, 0x000000A9, 0x0 },
 269         { 0x00006013, 0x000000A2, 0x0 },
 270         { 0x00007011, 0x000000A6, 0x0 },
 271         { 0x00002016, 0x000000AB, 0x0 },
 272         { 0x00005013, 0x0000009F, 0x0 },
 273         { 0x00000018, 0x000000DF, 0x0 },
 274 };
 275
 276 /*
 277  * Skylake/Kabylake Y
 278  * eDP 1.4 low vswing translation parameters
 279  */
 280 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 281         { 0x00000018, 0x000000A8, 0x0 },
 282         { 0x00004013, 0x000000AB, 0x0 },
 283         { 0x00007011, 0x000000A4, 0x0 },
 284         { 0x00009010, 0x000000DF, 0x0 },
 285         { 0x00000018, 0x000000AA, 0x0 },
 286         { 0x00006013, 0x000000A4, 0x0 },
 287         { 0x00007011, 0x0000009D, 0x0 },
 288         { 0x00000018, 0x000000A0, 0x0 },
 289         { 0x00006012, 0x000000DF, 0x0 },
 290         { 0x00000018, 0x0000008A, 0x0 },
 291 };
 292
 293 /* Skylake/Kabylake U, H and S */
 294 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 295         { 0x00000018, 0x000000AC, 0x0 },
 296         { 0x00005012, 0x0000009D, 0x0 },
 297         { 0x00007011, 0x00000088, 0x0 },
 298         { 0x00000018, 0x000000A1, 0x0 },
 299         { 0x00000018, 0x00000098, 0x0 },
 300         { 0x00004013, 0x00000088, 0x0 },
 301         { 0x80006012, 0x000000CD, 0x1 },
 302         { 0x00000018, 0x000000DF, 0x0 },
 303         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 304         { 0x80003015, 0x000000C0, 0x1 },
 305         { 0x80000018, 0x000000C0, 0x1 },
 306 };
 307
 308 /* Skylake/Kabylake Y */
 309 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 310         { 0x00000018, 0x000000A1, 0x0 },
 311         { 0x00005012, 0x000000DF, 0x0 },
 312         { 0x80007011, 0x000000CB, 0x3 },
 313         { 0x00000018, 0x000000A4, 0x0 },
 314         { 0x00000018, 0x0000009D, 0x0 },
 315         { 0x00004013, 0x00000080, 0x0 },
 316         { 0x80006013, 0x000000C0, 0x3 },
 317         { 0x00000018, 0x0000008A, 0x0 },
 318         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 319         { 0x80003015, 0x000000C0, 0x3 },
 320         { 0x80000018, 0x000000C0, 0x3 },
 321 };
 322
 323 struct bxt_ddi_buf_trans {
 324         u8 margin;      /* swing value */
 325         u8 scale;       /* scale value */
 326         u8 enable;      /* scale enable */
 327         u8 deemphasis;
 328 };
 329
 330 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 331                                         /* Idx  NT mV diff      db  */
 332         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 333         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 334         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 335         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 336         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 337         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 338         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 339         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 340         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 341         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 342 };
 343
 344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 345                                         /* Idx  NT mV diff      db  */
 346         { 26, 0, 0, 128, },     /* 0:   200             0   */
 347         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 348         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 349         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 350         { 32, 0, 0, 128, },     /* 4:   250             0   */
 351         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 352         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 353         { 43, 0, 0, 128, },     /* 7:   300             0   */
 354         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 355         { 48, 0, 0, 128, },     /* 9:   300             0   */
 356 };
 357
 358 /* BSpec has 2 recommended values - entries 0 and 8.
 359  * Using the entry with higher vswing.
 360  */
 361 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 362                                         /* Idx  NT mV diff      db  */
 363         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 364         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 365         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 366         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 367         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 368         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 369         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 370         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 371         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 372         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 373 };
 374
 375 struct cnl_ddi_buf_trans {
 376         u8 dw2_swing_sel;
 377         u8 dw7_n_scalar;
 378         u8 dw4_cursor_coeff;
 379         u8 dw4_post_cursor_2;
 380         u8 dw4_post_cursor_1;
 381 };
 382
 383 /* Voltage Swing Programming for VccIO 0.85V for DP */
 384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 385                                                 /* NT mV Trans mV db    */
 386         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 387         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 388         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 389         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 390         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 391         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 392         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 393         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 394         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 395         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 396 };
 397
 398 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 400                                                 /* NT mV Trans mV db    */
 401         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 402         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 403         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 404         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 405         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 406         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 407         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 408 };
 409
 410 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 411 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 412                                                 /* NT mV Trans mV db    */
 413         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 414         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 415         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 416         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 417         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 418         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 419         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 420         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 421         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 422 };
 423
 424 /* Voltage Swing Programming for VccIO 0.95V for DP */
 425 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 426                                                 /* NT mV Trans mV db    */
 427         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 428         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 429         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 430         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 431         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 432         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 433         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 434         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 435         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 436         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 437 };
 438
 439 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 440 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 441                                                 /* NT mV Trans mV db    */
 442         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 443         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 444         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 445         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 446         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 447         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 448         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 449         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 450         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 451         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 452         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 453 };
 454
 455 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 456 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 457                                                 /* NT mV Trans mV db    */
 458         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 459         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 460         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 461         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 462         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 463         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 464         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 465         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 466         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 467         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 468 };
 469
 470 /* Voltage Swing Programming for VccIO 1.05V for DP */
 471 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 472                                                 /* NT mV Trans mV db    */
 473         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 474         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 475         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 476         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 477         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 478         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 479         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 480         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 481         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 482         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 483 };
 484
 485 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 486 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 487                                                 /* NT mV Trans mV db    */
 488         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 489         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 490         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 491         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 492         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 493         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 494         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 495         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 496         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 497         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 498         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 499 };
 500
 501 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 502 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 503                                                 /* NT mV Trans mV db    */
 504         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 505         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 506         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 507         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 508         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 509         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 510         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 511         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 512         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 513 };
 514
 515 /* icl_combo_phy_ddi_translations */
 516 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 517                                                 /* NT mV Trans mV db    */
 518         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 519         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 520         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 521         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 522         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 523         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 524         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 525         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 526         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 527         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 528 };
 529
 530 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 531                                                 /* NT mV Trans mV db    */
 532         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 533         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 534         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 535         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 536         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 537         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 538         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 539         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 540         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 541         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 542 };
 543
 544 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 545                                                 /* NT mV Trans mV db    */
 546         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 547         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 548         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 549         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 550         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 551         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 552         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 553         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 554         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 555         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 556 };
 557
 558 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 559                                                 /* NT mV Trans mV db    */
 560         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 561         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 562         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 563         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 564         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 565         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 566         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 567 };
 568
 569 struct icl_mg_phy_ddi_buf_trans {
 570         u32 cri_txdeemph_override_5_0;
 571         u32 cri_txdeemph_override_11_6;
 572         u32 cri_txdeemph_override_17_12;
 573 };
 574
 575 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 576                                 /* Voltage swing  pre-emphasis */
 577         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 578         { 0x0, 0x23, 0x08 },    /* 0              1   */
 579         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 580         { 0x0, 0x00, 0x00 },    /* 0              3   */
 581         { 0x0, 0x23, 0x00 },    /* 1              0   */
 582         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 583         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 584         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 585         { 0x0, 0x33, 0x0C },    /* 2              1   */
 586         { 0x0, 0x00, 0x00 },    /* 3              0   */
 587 };
 588
 589 static const struct ddi_buf_trans *
 590 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 591 {
 592         if (dev_priv->vbt.edp.low_vswing) {
 593                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 594                 return bdw_ddi_translations_edp;
 595         } else {
 596                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 597                 return bdw_ddi_translations_dp;
 598         }
 599 }
 600
 601 static const struct ddi_buf_trans *
 602 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 603 {
 604         if (IS_SKL_ULX(dev_priv)) {
 605                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 606                 return skl_y_ddi_translations_dp;
 607         } else if (IS_SKL_ULT(dev_priv)) {
 608                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 609                 return skl_u_ddi_translations_dp;
 610         } else {
 611                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 612                 return skl_ddi_translations_dp;
 613         }
 614 }
 615
 616 static const struct ddi_buf_trans *
 617 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 618 {
 619         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 620                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 621                 return kbl_y_ddi_translations_dp;
 622         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 623                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 624                 return kbl_u_ddi_translations_dp;
 625         } else {
 626                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 627                 return kbl_ddi_translations_dp;
 628         }
 629 }
 630
 631 static const struct ddi_buf_trans *
 632 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 633 {
 634         if (dev_priv->vbt.edp.low_vswing) {
 635                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 636                     IS_CFL_ULX(dev_priv)) {
 637                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 638                         return skl_y_ddi_translations_edp;
 639                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 640                            IS_CFL_ULT(dev_priv)) {
 641                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 642                         return skl_u_ddi_translations_edp;
 643                 } else {
 644                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 645                         return skl_ddi_translations_edp;
 646                 }
 647         }
 648
 649         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 650                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 651         else
 652                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 653 }
 654
 655 static const struct ddi_buf_trans *
 656 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 657 {
 658         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 659             IS_CFL_ULX(dev_priv)) {
 660                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 661                 return skl_y_ddi_translations_hdmi;
 662         } else {
 663                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 664                 return skl_ddi_translations_hdmi;
 665         }
 666 }
 667
 668 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 669 {
 670         /* Only DDIA and DDIE can select the 10th register with DP */
 671         if (port == PORT_A || port == PORT_E)
 672                 return min(n_entries, 10);
 673         else
 674                 return min(n_entries, 9);
 675 }
 676
 677 static const struct ddi_buf_trans *
 678 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 679                            enum port port, int *n_entries)
 680 {
 681         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 682                 const struct ddi_buf_trans *ddi_translations =
 683                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 684                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 685                 return ddi_translations;
 686         } else if (IS_SKYLAKE(dev_priv)) {
 687                 const struct ddi_buf_trans *ddi_translations =
 688                         skl_get_buf_trans_dp(dev_priv, n_entries);
 689                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 690                 return ddi_translations;
 691         } else if (IS_BROADWELL(dev_priv)) {
 692                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 693                 return  bdw_ddi_translations_dp;
 694         } else if (IS_HASWELL(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 696                 return hsw_ddi_translations_dp;
 697         }
 698
 699         *n_entries = 0;
 700         return NULL;
 701 }
 702
 703 static const struct ddi_buf_trans *
 704 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 705                             enum port port, int *n_entries)
 706 {
 707         if (IS_GEN9_BC(dev_priv)) {
 708                 const struct ddi_buf_trans *ddi_translations =
 709                         skl_get_buf_trans_edp(dev_priv, n_entries);
 710                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 711                 return ddi_translations;
 712         } else if (IS_BROADWELL(dev_priv)) {
 713                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 714         } else if (IS_HASWELL(dev_priv)) {
 715                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 716                 return hsw_ddi_translations_dp;
 717         }
 718
 719         *n_entries = 0;
 720         return NULL;
 721 }
 722
 723 static const struct ddi_buf_trans *
 724 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 725                             int *n_entries)
 726 {
 727         if (IS_BROADWELL(dev_priv)) {
 728                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 729                 return bdw_ddi_translations_fdi;
 730         } else if (IS_HASWELL(dev_priv)) {
 731                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 732                 return hsw_ddi_translations_fdi;
 733         }
 734
 735         *n_entries = 0;
 736         return NULL;
 737 }
 738
 739 static const struct ddi_buf_trans *
 740 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 741                              int *n_entries)
 742 {
 743         if (IS_GEN9_BC(dev_priv)) {
 744                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 745         } else if (IS_BROADWELL(dev_priv)) {
 746                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 747                 return bdw_ddi_translations_hdmi;
 748         } else if (IS_HASWELL(dev_priv)) {
 749                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 750                 return hsw_ddi_translations_hdmi;
 751         }
 752
 753         *n_entries = 0;
 754         return NULL;
 755 }
 756
 757 static const struct bxt_ddi_buf_trans *
 758 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 759 {
 760         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 761         return bxt_ddi_translations_dp;
 762 }
 763
 764 static const struct bxt_ddi_buf_trans *
 765 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 766 {
 767         if (dev_priv->vbt.edp.low_vswing) {
 768                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 769                 return bxt_ddi_translations_edp;
 770         }
 771
 772         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 773 }
 774
 775 static const struct bxt_ddi_buf_trans *
 776 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 777 {
 778         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 779         return bxt_ddi_translations_hdmi;
 780 }
 781
 782 static const struct cnl_ddi_buf_trans *
 783 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 784 {
 785         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 786
 787         if (voltage == VOLTAGE_INFO_0_85V) {
 788                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 789                 return cnl_ddi_translations_hdmi_0_85V;
 790         } else if (voltage == VOLTAGE_INFO_0_95V) {
 791                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 792                 return cnl_ddi_translations_hdmi_0_95V;
 793         } else if (voltage == VOLTAGE_INFO_1_05V) {
 794                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 795                 return cnl_ddi_translations_hdmi_1_05V;
 796         } else {
 797                 *n_entries = 1; /* shut up gcc */
 798                 MISSING_CASE(voltage);
 799         }
 800         return NULL;
 801 }
 802
 803 static const struct cnl_ddi_buf_trans *
 804 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 805 {
 806         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 807
 808         if (voltage == VOLTAGE_INFO_0_85V) {
 809                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 810                 return cnl_ddi_translations_dp_0_85V;
 811         } else if (voltage == VOLTAGE_INFO_0_95V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 813                 return cnl_ddi_translations_dp_0_95V;
 814         } else if (voltage == VOLTAGE_INFO_1_05V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 816                 return cnl_ddi_translations_dp_1_05V;
 817         } else {
 818                 *n_entries = 1; /* shut up gcc */
 819                 MISSING_CASE(voltage);
 820         }
 821         return NULL;
 822 }
 823
 824 static const struct cnl_ddi_buf_trans *
 825 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 826 {
 827         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 828
 829         if (dev_priv->vbt.edp.low_vswing) {
 830                 if (voltage == VOLTAGE_INFO_0_85V) {
 831                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 832                         return cnl_ddi_translations_edp_0_85V;
 833                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 834                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 835                         return cnl_ddi_translations_edp_0_95V;
 836                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 837                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 838                         return cnl_ddi_translations_edp_1_05V;
 839                 } else {
 840                         *n_entries = 1; /* shut up gcc */
 841                         MISSING_CASE(voltage);
 842                 }
 843                 return NULL;
 844         } else {
 845                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 846         }
 847 }
 848
 849 static const struct cnl_ddi_buf_trans *
 850 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 851                         int *n_entries)
 852 {
 853         if (type == INTEL_OUTPUT_HDMI) {
 854                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 855                 return icl_combo_phy_ddi_translations_hdmi;
 856         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 857                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 858                 return icl_combo_phy_ddi_translations_edp_hbr3;
 859         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 860                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 861                 return icl_combo_phy_ddi_translations_edp_hbr2;
 862         }
 863
 864         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 865         return icl_combo_phy_ddi_translations_dp_hbr2;
 866 }
 867
 868 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 869 {
 870         int n_entries, level, default_entry;
 871         enum phy phy = intel_port_to_phy(dev_priv, port);
 872
 873         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 874
 875         if (INTEL_GEN(dev_priv) >= 11) {
 876                 if (intel_phy_is_combo(dev_priv, phy))
 877                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 878                                                 0, &n_entries);
 879                 else
 880                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 881                 default_entry = n_entries - 1;
 882         } else if (IS_CANNONLAKE(dev_priv)) {
 883                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 884                 default_entry = n_entries - 1;
 885         } else if (IS_GEN9_LP(dev_priv)) {
 886                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 887                 default_entry = n_entries - 1;
 888         } else if (IS_GEN9_BC(dev_priv)) {
 889                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 890                 default_entry = 8;
 891         } else if (IS_BROADWELL(dev_priv)) {
 892                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 893                 default_entry = 7;
 894         } else if (IS_HASWELL(dev_priv)) {
 895                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 896                 default_entry = 6;
 897         } else {
 898                 WARN(1, "ddi translation table missing\n");
 899                 return 0;
 900         }
 901
 902         /* Choose a good default if VBT is badly populated */
 903         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 904                 level = default_entry;
 905
 906         if (WARN_ON_ONCE(n_entries == 0))
 907                 return 0;
 908         if (WARN_ON_ONCE(level >= n_entries))
 909                 level = n_entries - 1;
 910
 911         return level;
 912 }
 913
 914 /*
 915  * Starting with Haswell, DDI port buffers must be programmed with correct
 916  * values in advance. This function programs the correct values for
 917  * DP/eDP/FDI use cases.
 918  */
 919 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 920                                          const struct intel_crtc_state *crtc_state)
 921 {
 922         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 923         u32 iboost_bit = 0;
 924         int i, n_entries;
 925         enum port port = encoder->port;
 926         const struct ddi_buf_trans *ddi_translations;
 927
 928         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 929                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 930                                                                &n_entries);
 931         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 932                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 933                                                                &n_entries);
 934         else
 935                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 936                                                               &n_entries);
 937
 938         /* If we're boosting the current, set bit 31 of trans1 */
 939         if (IS_GEN9_BC(dev_priv) &&
 940             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 941                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 942
 943         for (i = 0; i < n_entries; i++) {
 944                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 945                            ddi_translations[i].trans1 | iboost_bit);
 946                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 947                            ddi_translations[i].trans2);
 948         }
 949 }
 950
 951 /*
 952  * Starting with Haswell, DDI port buffers must be programmed with correct
 953  * values in advance. This function programs the correct values for
 954  * HDMI/DVI use cases.
 955  */
 956 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 957                                            int level)
 958 {
 959         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 960         u32 iboost_bit = 0;
 961         int n_entries;
 962         enum port port = encoder->port;
 963         const struct ddi_buf_trans *ddi_translations;
 964
 965         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 966
 967         if (WARN_ON_ONCE(!ddi_translations))
 968                 return;
 969         if (WARN_ON_ONCE(level >= n_entries))
 970                 level = n_entries - 1;
 971
 972         /* If we're boosting the current, set bit 31 of trans1 */
 973         if (IS_GEN9_BC(dev_priv) &&
 974             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 975                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 976
 977         /* Entry 9 is for HDMI: */
 978         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 979                    ddi_translations[level].trans1 | iboost_bit);
 980         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 981                    ddi_translations[level].trans2);
 982 }
 983
 984 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 985                                     enum port port)
 986 {
 987         i915_reg_t reg = DDI_BUF_CTL(port);
 988         int i;
 989
 990         for (i = 0; i < 16; i++) {
 991                 udelay(1);
 992                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 993                         return;
 994         }
 995         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 996 }
 997
 998 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 999 {
1000         switch (pll->info->id) {
1001         case DPLL_ID_WRPLL1:
1002                 return PORT_CLK_SEL_WRPLL1;
1003         case DPLL_ID_WRPLL2:
1004                 return PORT_CLK_SEL_WRPLL2;
1005         case DPLL_ID_SPLL:
1006                 return PORT_CLK_SEL_SPLL;
1007         case DPLL_ID_LCPLL_810:
1008                 return PORT_CLK_SEL_LCPLL_810;
1009         case DPLL_ID_LCPLL_1350:
1010                 return PORT_CLK_SEL_LCPLL_1350;
1011         case DPLL_ID_LCPLL_2700:
1012                 return PORT_CLK_SEL_LCPLL_2700;
1013         default:
1014                 MISSING_CASE(pll->info->id);
1015                 return PORT_CLK_SEL_NONE;
1016         }
1017 }
1018
1019 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1020                                   const struct intel_crtc_state *crtc_state)
1021 {
1022         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1023         int clock = crtc_state->port_clock;
1024         const enum intel_dpll_id id = pll->info->id;
1025
1026         switch (id) {
1027         default:
1028                 /*
1029                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1030                  * here, so do warn if this get passed in
1031                  */
1032                 MISSING_CASE(id);
1033                 return DDI_CLK_SEL_NONE;
1034         case DPLL_ID_ICL_TBTPLL:
1035                 switch (clock) {
1036                 case 162000:
1037                         return DDI_CLK_SEL_TBT_162;
1038                 case 270000:
1039                         return DDI_CLK_SEL_TBT_270;
1040                 case 540000:
1041                         return DDI_CLK_SEL_TBT_540;
1042                 case 810000:
1043                         return DDI_CLK_SEL_TBT_810;
1044                 default:
1045                         MISSING_CASE(clock);
1046                         return DDI_CLK_SEL_NONE;
1047                 }
1048         case DPLL_ID_ICL_MGPLL1:
1049         case DPLL_ID_ICL_MGPLL2:
1050         case DPLL_ID_ICL_MGPLL3:
1051         case DPLL_ID_ICL_MGPLL4:
1052                 return DDI_CLK_SEL_MG;
1053         }
1054 }
1055
1056 /* Starting with Haswell, different DDI ports can work in FDI mode for
1057  * connection to the PCH-located connectors. For this, it is necessary to train
1058  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1059  *
1060  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1061  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1062  * DDI A (which is used for eDP)
1063  */
1064
1065 void hsw_fdi_link_train(struct intel_crtc *crtc,
1066                         const struct intel_crtc_state *crtc_state)
1067 {
1068         struct drm_device *dev = crtc->base.dev;
1069         struct drm_i915_private *dev_priv = to_i915(dev);
1070         struct intel_encoder *encoder;
1071         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1072
1073         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1074                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1075                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1076         }
1077
1078         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1079          * mode set "sequence for CRT port" document:
1080          * - TP1 to TP2 time with the default value
1081          * - FDI delay to 90h
1082          *
1083          * WaFDIAutoLinkSetTimingOverrride:hsw
1084          */
1085         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1086                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1087                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1088
1089         /* Enable the PCH Receiver FDI PLL */
1090         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1091                      FDI_RX_PLL_ENABLE |
1092                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1093         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1094         POSTING_READ(FDI_RX_CTL(PIPE_A));
1095         udelay(220);
1096
1097         /* Switch from Rawclk to PCDclk */
1098         rx_ctl_val |= FDI_PCDCLK;
1099         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1100
1101         /* Configure Port Clock Select */
1102         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1103         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1104         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1105
1106         /* Start the training iterating through available voltages and emphasis,
1107          * testing each value twice. */
1108         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1109                 /* Configure DP_TP_CTL with auto-training */
1110                 I915_WRITE(DP_TP_CTL(PORT_E),
1111                                         DP_TP_CTL_FDI_AUTOTRAIN |
1112                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1113                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1114                                         DP_TP_CTL_ENABLE);
1115
1116                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1117                  * DDI E does not support port reversal, the functionality is
1118                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1119                  * port reversal bit */
1120                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1121                            DDI_BUF_CTL_ENABLE |
1122                            ((crtc_state->fdi_lanes - 1) << 1) |
1123                            DDI_BUF_TRANS_SELECT(i / 2));
1124                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1125
1126                 udelay(600);
1127
1128                 /* Program PCH FDI Receiver TU */
1129                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1130
1131                 /* Enable PCH FDI Receiver with auto-training */
1132                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1133                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1134                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1135
1136                 /* Wait for FDI receiver lane calibration */
1137                 udelay(30);
1138
1139                 /* Unset FDI_RX_MISC pwrdn lanes */
1140                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1141                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1142                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1143                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1144
1145                 /* Wait for FDI auto training time */
1146                 udelay(5);
1147
1148                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1149                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1150                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1151                         break;
1152                 }
1153
1154                 /*
1155                  * Leave things enabled even if we failed to train FDI.
1156                  * Results in less fireworks from the state checker.
1157                  */
1158                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1159                         DRM_ERROR("FDI link training failed!\n");
1160                         break;
1161                 }
1162
1163                 rx_ctl_val &= ~FDI_RX_ENABLE;
1164                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1165                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1166
1167                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1168                 temp &= ~DDI_BUF_CTL_ENABLE;
1169                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1170                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1171
1172                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1173                 temp = I915_READ(DP_TP_CTL(PORT_E));
1174                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1175                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1176                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1177                 POSTING_READ(DP_TP_CTL(PORT_E));
1178
1179                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1180
1181                 /* Reset FDI_RX_MISC pwrdn lanes */
1182                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1185                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1186                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1187         }
1188
1189         /* Enable normal pixel sending for FDI */
1190         I915_WRITE(DP_TP_CTL(PORT_E),
1191                    DP_TP_CTL_FDI_AUTOTRAIN |
1192                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1193                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1194                    DP_TP_CTL_ENABLE);
1195 }
1196
1197 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1198 {
1199         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1200         struct intel_digital_port *intel_dig_port =
1201                 enc_to_dig_port(&encoder->base);
1202
1203         intel_dp->DP = intel_dig_port->saved_port_bits |
1204                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1205         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1206 }
1207
1208 static struct intel_encoder *
1209 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1210 {
1211         struct drm_device *dev = crtc->base.dev;
1212         struct intel_encoder *encoder, *ret = NULL;
1213         int num_encoders = 0;
1214
1215         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1216                 ret = encoder;
1217                 num_encoders++;
1218         }
1219
1220         if (num_encoders != 1)
1221                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1222                      pipe_name(crtc->pipe));
1223
1224         BUG_ON(ret == NULL);
1225         return ret;
1226 }
1227
1228 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1229                                    i915_reg_t reg)
1230 {
1231         int refclk;
1232         int n, p, r;
1233         u32 wrpll;
1234
1235         wrpll = I915_READ(reg);
1236         switch (wrpll & WRPLL_REF_MASK) {
1237         case WRPLL_REF_SPECIAL_HSW:
1238                 /*
1239                  * muxed-SSC for BDW.
1240                  * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1241                  * for the non-SSC reference frequency.
1242                  */
1243                 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1244                         if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1245                                 refclk = 24;
1246                         else
1247                                 refclk = 135;
1248                         break;
1249                 }
1250                 /* fall through */
1251         case WRPLL_REF_PCH_SSC:
1252                 /*
1253                  * We could calculate spread here, but our checking
1254                  * code only cares about 5% accuracy, and spread is a max of
1255                  * 0.5% downspread.
1256                  */
1257                 refclk = 135;
1258                 break;
1259         case WRPLL_REF_LCPLL:
1260                 refclk = 2700;
1261                 break;
1262         default:
1263                 MISSING_CASE(wrpll);
1264                 return 0;
1265         }
1266
1267         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1268         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1269         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1270
1271         /* Convert to KHz, p & r have a fixed point portion */
1272         return (refclk * n * 100) / (p * r);
1273 }
1274
1275 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1276 {
1277         u32 p0, p1, p2, dco_freq;
1278
1279         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1280         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1281
1282         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1283                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1284         else
1285                 p1 = 1;
1286
1287
1288         switch (p0) {
1289         case DPLL_CFGCR2_PDIV_1:
1290                 p0 = 1;
1291                 break;
1292         case DPLL_CFGCR2_PDIV_2:
1293                 p0 = 2;
1294                 break;
1295         case DPLL_CFGCR2_PDIV_3:
1296                 p0 = 3;
1297                 break;
1298         case DPLL_CFGCR2_PDIV_7:
1299                 p0 = 7;
1300                 break;
1301         }
1302
1303         switch (p2) {
1304         case DPLL_CFGCR2_KDIV_5:
1305                 p2 = 5;
1306                 break;
1307         case DPLL_CFGCR2_KDIV_2:
1308                 p2 = 2;
1309                 break;
1310         case DPLL_CFGCR2_KDIV_3:
1311                 p2 = 3;
1312                 break;
1313         case DPLL_CFGCR2_KDIV_1:
1314                 p2 = 1;
1315                 break;
1316         }
1317
1318         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1319                 * 24 * 1000;
1320
1321         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1322                      * 24 * 1000) / 0x8000;
1323
1324         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1325                 return 0;
1326
1327         return dco_freq / (p0 * p1 * p2 * 5);
1328 }
1329
1330 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1331                         struct intel_dpll_hw_state *pll_state)
1332 {
1333         u32 p0, p1, p2, dco_freq, ref_clock;
1334
1335         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1336         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1337
1338         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1339                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1340                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1341         else
1342                 p1 = 1;
1343
1344
1345         switch (p0) {
1346         case DPLL_CFGCR1_PDIV_2:
1347                 p0 = 2;
1348                 break;
1349         case DPLL_CFGCR1_PDIV_3:
1350                 p0 = 3;
1351                 break;
1352         case DPLL_CFGCR1_PDIV_5:
1353                 p0 = 5;
1354                 break;
1355         case DPLL_CFGCR1_PDIV_7:
1356                 p0 = 7;
1357                 break;
1358         }
1359
1360         switch (p2) {
1361         case DPLL_CFGCR1_KDIV_1:
1362                 p2 = 1;
1363                 break;
1364         case DPLL_CFGCR1_KDIV_2:
1365                 p2 = 2;
1366                 break;
1367         case DPLL_CFGCR1_KDIV_3:
1368                 p2 = 3;
1369                 break;
1370         }
1371
1372         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1373
1374         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1375                 * ref_clock;
1376
1377         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1378                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1379
1380         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1381                 return 0;
1382
1383         return dco_freq / (p0 * p1 * p2 * 5);
1384 }
1385
1386 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1387                                  enum port port)
1388 {
1389         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1390
1391         switch (val) {
1392         case DDI_CLK_SEL_NONE:
1393                 return 0;
1394         case DDI_CLK_SEL_TBT_162:
1395                 return 162000;
1396         case DDI_CLK_SEL_TBT_270:
1397                 return 270000;
1398         case DDI_CLK_SEL_TBT_540:
1399                 return 540000;
1400         case DDI_CLK_SEL_TBT_810:
1401                 return 810000;
1402         default:
1403                 MISSING_CASE(val);
1404                 return 0;
1405         }
1406 }
1407
1408 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1409                                 const struct intel_dpll_hw_state *pll_state)
1410 {
1411         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1412         u64 tmp;
1413
1414         ref_clock = dev_priv->cdclk.hw.ref;
1415
1416         m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1417         m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1418         m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1419                 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1420                 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1421
1422         switch (pll_state->mg_clktop2_hsclkctl &
1423                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1424         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1425                 div1 = 2;
1426                 break;
1427         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1428                 div1 = 3;
1429                 break;
1430         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1431                 div1 = 5;
1432                 break;
1433         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1434                 div1 = 7;
1435                 break;
1436         default:
1437                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1438                 return 0;
1439         }
1440
1441         div2 = (pll_state->mg_clktop2_hsclkctl &
1442                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1443                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1444
1445         /* div2 value of 0 is same as 1 means no div */
1446         if (div2 == 0)
1447                 div2 = 1;
1448
1449         /*
1450          * Adjust the original formula to delay the division by 2^22 in order to
1451          * minimize possible rounding errors.
1452          */
1453         tmp = (u64)m1 * m2_int * ref_clock +
1454               (((u64)m1 * m2_frac * ref_clock) >> 22);
1455         tmp = div_u64(tmp, 5 * div1 * div2);
1456
1457         return tmp;
1458 }
1459
1460 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1461 {
1462         int dotclock;
1463
1464         if (pipe_config->has_pch_encoder)
1465                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1466                                                     &pipe_config->fdi_m_n);
1467         else if (intel_crtc_has_dp_encoder(pipe_config))
1468                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1469                                                     &pipe_config->dp_m_n);
1470         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1471                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1472         else
1473                 dotclock = pipe_config->port_clock;
1474
1475         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1476             !intel_crtc_has_dp_encoder(pipe_config))
1477                 dotclock *= 2;
1478
1479         if (pipe_config->pixel_multiplier)
1480                 dotclock /= pipe_config->pixel_multiplier;
1481
1482         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1483 }
1484
1485 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1486                               struct intel_crtc_state *pipe_config)
1487 {
1488         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1489         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1490         enum port port = encoder->port;
1491         enum phy phy = intel_port_to_phy(dev_priv, port);
1492         int link_clock;
1493
1494         if (intel_phy_is_combo(dev_priv, phy)) {
1495                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1496         } else {
1497                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1498                                                 pipe_config->shared_dpll);
1499
1500                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1501                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1502                 else
1503                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1504         }
1505
1506         pipe_config->port_clock = link_clock;
1507
1508         ddi_dotclock_get(pipe_config);
1509 }
1510
1511 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1512                               struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1515         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1516         int link_clock;
1517
1518         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1519                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1520         } else {
1521                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1522
1523                 switch (link_clock) {
1524                 case DPLL_CFGCR0_LINK_RATE_810:
1525                         link_clock = 81000;
1526                         break;
1527                 case DPLL_CFGCR0_LINK_RATE_1080:
1528                         link_clock = 108000;
1529                         break;
1530                 case DPLL_CFGCR0_LINK_RATE_1350:
1531                         link_clock = 135000;
1532                         break;
1533                 case DPLL_CFGCR0_LINK_RATE_1620:
1534                         link_clock = 162000;
1535                         break;
1536                 case DPLL_CFGCR0_LINK_RATE_2160:
1537                         link_clock = 216000;
1538                         break;
1539                 case DPLL_CFGCR0_LINK_RATE_2700:
1540                         link_clock = 270000;
1541                         break;
1542                 case DPLL_CFGCR0_LINK_RATE_3240:
1543                         link_clock = 324000;
1544                         break;
1545                 case DPLL_CFGCR0_LINK_RATE_4050:
1546                         link_clock = 405000;
1547                         break;
1548                 default:
1549                         WARN(1, "Unsupported link rate\n");
1550                         break;
1551                 }
1552                 link_clock *= 2;
1553         }
1554
1555         pipe_config->port_clock = link_clock;
1556
1557         ddi_dotclock_get(pipe_config);
1558 }
1559
1560 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1561                               struct intel_crtc_state *pipe_config)
1562 {
1563         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1564         int link_clock;
1565
1566         /*
1567          * ctrl1 register is already shifted for each pll, just use 0 to get
1568          * the internal shift for each field
1569          */
1570         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1571                 link_clock = skl_calc_wrpll_link(pll_state);
1572         } else {
1573                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1574                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1575
1576                 switch (link_clock) {
1577                 case DPLL_CTRL1_LINK_RATE_810:
1578                         link_clock = 81000;
1579                         break;
1580                 case DPLL_CTRL1_LINK_RATE_1080:
1581                         link_clock = 108000;
1582                         break;
1583                 case DPLL_CTRL1_LINK_RATE_1350:
1584                         link_clock = 135000;
1585                         break;
1586                 case DPLL_CTRL1_LINK_RATE_1620:
1587                         link_clock = 162000;
1588                         break;
1589                 case DPLL_CTRL1_LINK_RATE_2160:
1590                         link_clock = 216000;
1591                         break;
1592                 case DPLL_CTRL1_LINK_RATE_2700:
1593                         link_clock = 270000;
1594                         break;
1595                 default:
1596                         WARN(1, "Unsupported link rate\n");
1597                         break;
1598                 }
1599                 link_clock *= 2;
1600         }
1601
1602         pipe_config->port_clock = link_clock;
1603
1604         ddi_dotclock_get(pipe_config);
1605 }
1606
1607 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1608                               struct intel_crtc_state *pipe_config)
1609 {
1610         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1611         int link_clock = 0;
1612         u32 val, pll;
1613
1614         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1615         switch (val & PORT_CLK_SEL_MASK) {
1616         case PORT_CLK_SEL_LCPLL_810:
1617                 link_clock = 81000;
1618                 break;
1619         case PORT_CLK_SEL_LCPLL_1350:
1620                 link_clock = 135000;
1621                 break;
1622         case PORT_CLK_SEL_LCPLL_2700:
1623                 link_clock = 270000;
1624                 break;
1625         case PORT_CLK_SEL_WRPLL1:
1626                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1627                 break;
1628         case PORT_CLK_SEL_WRPLL2:
1629                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1630                 break;
1631         case PORT_CLK_SEL_SPLL:
1632                 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1633                 if (pll == SPLL_FREQ_810MHz)
1634                         link_clock = 81000;
1635                 else if (pll == SPLL_FREQ_1350MHz)
1636                         link_clock = 135000;
1637                 else if (pll == SPLL_FREQ_2700MHz)
1638                         link_clock = 270000;
1639                 else {
1640                         WARN(1, "bad spll freq\n");
1641                         return;
1642                 }
1643                 break;
1644         default:
1645                 WARN(1, "bad port clock sel\n");
1646                 return;
1647         }
1648
1649         pipe_config->port_clock = link_clock * 2;
1650
1651         ddi_dotclock_get(pipe_config);
1652 }
1653
1654 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1655 {
1656         struct dpll clock;
1657
1658         clock.m1 = 2;
1659         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1660         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1661                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1662         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1663         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1664         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1665
1666         return chv_calc_dpll_params(100000, &clock);
1667 }
1668
1669 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1670                               struct intel_crtc_state *pipe_config)
1671 {
1672         pipe_config->port_clock =
1673                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1674
1675         ddi_dotclock_get(pipe_config);
1676 }
1677
1678 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1679                                 struct intel_crtc_state *pipe_config)
1680 {
1681         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1682
1683         if (INTEL_GEN(dev_priv) >= 11)
1684                 icl_ddi_clock_get(encoder, pipe_config);
1685         else if (IS_CANNONLAKE(dev_priv))
1686                 cnl_ddi_clock_get(encoder, pipe_config);
1687         else if (IS_GEN9_LP(dev_priv))
1688                 bxt_ddi_clock_get(encoder, pipe_config);
1689         else if (IS_GEN9_BC(dev_priv))
1690                 skl_ddi_clock_get(encoder, pipe_config);
1691         else if (INTEL_GEN(dev_priv) <= 8)
1692                 hsw_ddi_clock_get(encoder, pipe_config);
1693 }
1694
1695 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1696 {
1697         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1698         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1699         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1700         u32 temp;
1701
1702         if (!intel_crtc_has_dp_encoder(crtc_state))
1703                 return;
1704
1705         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1706
1707         temp = TRANS_MSA_SYNC_CLK;
1708
1709         switch (crtc_state->pipe_bpp) {
1710         case 18:
1711                 temp |= TRANS_MSA_6_BPC;
1712                 break;
1713         case 24:
1714                 temp |= TRANS_MSA_8_BPC;
1715                 break;
1716         case 30:
1717                 temp |= TRANS_MSA_10_BPC;
1718                 break;
1719         case 36:
1720                 temp |= TRANS_MSA_12_BPC;
1721                 break;
1722         default:
1723                 MISSING_CASE(crtc_state->pipe_bpp);
1724                 break;
1725         }
1726
1727         /* nonsense combination */
1728         WARN_ON(crtc_state->limited_color_range &&
1729                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1730
1731         if (crtc_state->limited_color_range)
1732                 temp |= TRANS_MSA_CEA_RANGE;
1733
1734         /*
1735          * As per DP 1.2 spec section 2.3.4.3 while sending
1736          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1737          * colorspace information.
1738          */
1739         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1740                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR |
1741                         TRANS_MSA_YCBCR_BT709;
1742
1743         /*
1744          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1745          * of Color Encoding Format and Content Color Gamut] while sending
1746          * YCBCR 420 signals we should program MSA MISC1 fields which
1747          * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1748          */
1749         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1750                 temp |= TRANS_MSA_USE_VSC_SDP;
1751         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1752 }
1753
1754 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1755                                     bool state)
1756 {
1757         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1758         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1759         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1760         u32 temp;
1761
1762         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1763         if (state == true)
1764                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1765         else
1766                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1767         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1768 }
1769
1770 /*
1771  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1772  *
1773  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1774  * intel_ddi_config_transcoder_func().
1775  */
1776 static u32
1777 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1778 {
1779         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1780         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1781         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1782         enum pipe pipe = crtc->pipe;
1783         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1784         enum port port = encoder->port;
1785         u32 temp;
1786
1787         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1788         temp = TRANS_DDI_FUNC_ENABLE;
1789         if (INTEL_GEN(dev_priv) >= 12)
1790                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1791         else
1792                 temp |= TRANS_DDI_SELECT_PORT(port);
1793
1794         switch (crtc_state->pipe_bpp) {
1795         case 18:
1796                 temp |= TRANS_DDI_BPC_6;
1797                 break;
1798         case 24:
1799                 temp |= TRANS_DDI_BPC_8;
1800                 break;
1801         case 30:
1802                 temp |= TRANS_DDI_BPC_10;
1803                 break;
1804         case 36:
1805                 temp |= TRANS_DDI_BPC_12;
1806                 break;
1807         default:
1808                 BUG();
1809         }
1810
1811         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1812                 temp |= TRANS_DDI_PVSYNC;
1813         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1814                 temp |= TRANS_DDI_PHSYNC;
1815
1816         if (cpu_transcoder == TRANSCODER_EDP) {
1817                 switch (pipe) {
1818                 case PIPE_A:
1819                         /* On Haswell, can only use the always-on power well for
1820                          * eDP when not using the panel fitter, and when not
1821                          * using motion blur mitigation (which we don't
1822                          * support). */
1823                         if (crtc_state->pch_pfit.force_thru)
1824                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1825                         else
1826                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1827                         break;
1828                 case PIPE_B:
1829                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1830                         break;
1831                 case PIPE_C:
1832                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1833                         break;
1834                 default:
1835                         BUG();
1836                         break;
1837                 }
1838         }
1839
1840         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1841                 if (crtc_state->has_hdmi_sink)
1842                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1843                 else
1844                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1845
1846                 if (crtc_state->hdmi_scrambling)
1847                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1848                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1849                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1850         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1851                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1852                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1853         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1854                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1855                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1856         } else {
1857                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1858                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1859         }
1860
1861         return temp;
1862 }
1863
1864 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1865 {
1866         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1867         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1868         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1869         u32 temp;
1870
1871         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1872         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1873 }
1874
1875 /*
1876  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1877  * bit.
1878  */
1879 static void
1880 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1881 {
1882         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1883         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1884         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1885         u32 temp;
1886
1887         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1888         temp &= ~TRANS_DDI_FUNC_ENABLE;
1889         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1890 }
1891
1892 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1893 {
1894         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1895         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1896         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1897         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1898         u32 val = I915_READ(reg);
1899
1900         if (INTEL_GEN(dev_priv) >= 12) {
1901                 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1902                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1903         } else {
1904                 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1905                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1906         }
1907         I915_WRITE(reg, val);
1908
1909         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1910             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1911                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1912                 /* Quirk time at 100ms for reliable operation */
1913                 msleep(100);
1914         }
1915 }
1916
1917 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1918                                      bool enable)
1919 {
1920         struct drm_device *dev = intel_encoder->base.dev;
1921         struct drm_i915_private *dev_priv = to_i915(dev);
1922         intel_wakeref_t wakeref;
1923         enum pipe pipe = 0;
1924         int ret = 0;
1925         u32 tmp;
1926
1927         wakeref = intel_display_power_get_if_enabled(dev_priv,
1928                                                      intel_encoder->power_domain);
1929         if (WARN_ON(!wakeref))
1930                 return -ENXIO;
1931
1932         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1933                 ret = -EIO;
1934                 goto out;
1935         }
1936
1937         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1938         if (enable)
1939                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1940         else
1941                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1942         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1943 out:
1944         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1945         return ret;
1946 }
1947
1948 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1949 {
1950         struct drm_device *dev = intel_connector->base.dev;
1951         struct drm_i915_private *dev_priv = to_i915(dev);
1952         struct intel_encoder *encoder = intel_connector->encoder;
1953         int type = intel_connector->base.connector_type;
1954         enum port port = encoder->port;
1955         enum transcoder cpu_transcoder;
1956         intel_wakeref_t wakeref;
1957         enum pipe pipe = 0;
1958         u32 tmp;
1959         bool ret;
1960
1961         wakeref = intel_display_power_get_if_enabled(dev_priv,
1962                                                      encoder->power_domain);
1963         if (!wakeref)
1964                 return false;
1965
1966         if (!encoder->get_hw_state(encoder, &pipe)) {
1967                 ret = false;
1968                 goto out;
1969         }
1970
1971         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1972                 cpu_transcoder = TRANSCODER_EDP;
1973         else
1974                 cpu_transcoder = (enum transcoder) pipe;
1975
1976         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1977
1978         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1979         case TRANS_DDI_MODE_SELECT_HDMI:
1980         case TRANS_DDI_MODE_SELECT_DVI:
1981                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1982                 break;
1983
1984         case TRANS_DDI_MODE_SELECT_DP_SST:
1985                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1986                       type == DRM_MODE_CONNECTOR_DisplayPort;
1987                 break;
1988
1989         case TRANS_DDI_MODE_SELECT_DP_MST:
1990                 /* if the transcoder is in MST state then
1991                  * connector isn't connected */
1992                 ret = false;
1993                 break;
1994
1995         case TRANS_DDI_MODE_SELECT_FDI:
1996                 ret = type == DRM_MODE_CONNECTOR_VGA;
1997                 break;
1998
1999         default:
2000                 ret = false;
2001                 break;
2002         }
2003
2004 out:
2005         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2006
2007         return ret;
2008 }
2009
2010 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2011                                         u8 *pipe_mask, bool *is_dp_mst)
2012 {
2013         struct drm_device *dev = encoder->base.dev;
2014         struct drm_i915_private *dev_priv = to_i915(dev);
2015         enum port port = encoder->port;
2016         intel_wakeref_t wakeref;
2017         enum pipe p;
2018         u32 tmp;
2019         u8 mst_pipe_mask;
2020
2021         *pipe_mask = 0;
2022         *is_dp_mst = false;
2023
2024         wakeref = intel_display_power_get_if_enabled(dev_priv,
2025                                                      encoder->power_domain);
2026         if (!wakeref)
2027                 return;
2028
2029         tmp = I915_READ(DDI_BUF_CTL(port));
2030         if (!(tmp & DDI_BUF_CTL_ENABLE))
2031                 goto out;
2032
2033         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
2034                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2035
2036                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2037                 default:
2038                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2039                         /* fallthrough */
2040                 case TRANS_DDI_EDP_INPUT_A_ON:
2041                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2042                         *pipe_mask = BIT(PIPE_A);
2043                         break;
2044                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2045                         *pipe_mask = BIT(PIPE_B);
2046                         break;
2047                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2048                         *pipe_mask = BIT(PIPE_C);
2049                         break;
2050                 }
2051
2052                 goto out;
2053         }
2054
2055         mst_pipe_mask = 0;
2056         for_each_pipe(dev_priv, p) {
2057                 enum transcoder cpu_transcoder = (enum transcoder)p;
2058                 unsigned int port_mask, ddi_select;
2059                 intel_wakeref_t trans_wakeref;
2060
2061                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2062                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2063                 if (!trans_wakeref)
2064                         continue;
2065
2066                 if (INTEL_GEN(dev_priv) >= 12) {
2067                         port_mask = TGL_TRANS_DDI_PORT_MASK;
2068                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2069                 } else {
2070                         port_mask = TRANS_DDI_PORT_MASK;
2071                         ddi_select = TRANS_DDI_SELECT_PORT(port);
2072                 }
2073
2074                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2075                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2076                                         trans_wakeref);
2077
2078                 if ((tmp & port_mask) != ddi_select)
2079                         continue;
2080
2081                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2082                     TRANS_DDI_MODE_SELECT_DP_MST)
2083                         mst_pipe_mask |= BIT(p);
2084
2085                 *pipe_mask |= BIT(p);
2086         }
2087
2088         if (!*pipe_mask)
2089                 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2090                               encoder->base.base.id, encoder->base.name);
2091
2092         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2093                 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2094                               encoder->base.base.id, encoder->base.name,
2095                               *pipe_mask);
2096                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2097         }
2098
2099         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2100                 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2101                               encoder->base.base.id, encoder->base.name,
2102                               *pipe_mask, mst_pipe_mask);
2103         else
2104                 *is_dp_mst = mst_pipe_mask;
2105
2106 out:
2107         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2108                 tmp = I915_READ(BXT_PHY_CTL(port));
2109                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2110                             BXT_PHY_LANE_POWERDOWN_ACK |
2111                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2112                         DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2113                                   "(PHY_CTL %08x)\n", encoder->base.base.id,
2114                                   encoder->base.name, tmp);
2115         }
2116
2117         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2118 }
2119
2120 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2121                             enum pipe *pipe)
2122 {
2123         u8 pipe_mask;
2124         bool is_mst;
2125
2126         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2127
2128         if (is_mst || !pipe_mask)
2129                 return false;
2130
2131         *pipe = ffs(pipe_mask) - 1;
2132
2133         return true;
2134 }
2135
2136 static inline enum intel_display_power_domain
2137 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2138 {
2139         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2140          * DC states enabled at the same time, while for driver initiated AUX
2141          * transfers we need the same AUX IOs to be powered but with DC states
2142          * disabled. Accordingly use the AUX power domain here which leaves DC
2143          * states enabled.
2144          * However, for non-A AUX ports the corresponding non-EDP transcoders
2145          * would have already enabled power well 2 and DC_OFF. This means we can
2146          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2147          * specific AUX_IO reference without powering up any extra wells.
2148          * Note that PSR is enabled only on Port A even though this function
2149          * returns the correct domain for other ports too.
2150          */
2151         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2152                                               intel_aux_power_domain(dig_port);
2153 }
2154
2155 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2156                                         struct intel_crtc_state *crtc_state)
2157 {
2158         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2159         struct intel_digital_port *dig_port;
2160         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2161
2162         /*
2163          * TODO: Add support for MST encoders. Atm, the following should never
2164          * happen since fake-MST encoders don't set their get_power_domains()
2165          * hook.
2166          */
2167         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2168                 return;
2169
2170         dig_port = enc_to_dig_port(&encoder->base);
2171         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2172
2173         /*
2174          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2175          * ports.
2176          */
2177         if (intel_crtc_has_dp_encoder(crtc_state) ||
2178             intel_phy_is_tc(dev_priv, phy))
2179                 intel_display_power_get(dev_priv,
2180                                         intel_ddi_main_link_aux_domain(dig_port));
2181
2182         /*
2183          * VDSC power is needed when DSC is enabled
2184          */
2185         if (crtc_state->dsc_params.compression_enable)
2186                 intel_display_power_get(dev_priv,
2187                                         intel_dsc_power_domain(crtc_state));
2188 }
2189
2190 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2191 {
2192         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2193         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2194         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2195         enum port port = encoder->port;
2196         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2197
2198         if (cpu_transcoder != TRANSCODER_EDP) {
2199                 if (INTEL_GEN(dev_priv) >= 12)
2200                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2201                                    TGL_TRANS_CLK_SEL_PORT(port));
2202                 else
2203                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2204                                    TRANS_CLK_SEL_PORT(port));
2205         }
2206 }
2207
2208 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2209 {
2210         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2211         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2212
2213         if (cpu_transcoder != TRANSCODER_EDP) {
2214                 if (INTEL_GEN(dev_priv) >= 12)
2215                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2216                                    TGL_TRANS_CLK_SEL_DISABLED);
2217                 else
2218                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2219                                    TRANS_CLK_SEL_DISABLED);
2220         }
2221 }
2222
2223 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2224                                 enum port port, u8 iboost)
2225 {
2226         u32 tmp;
2227
2228         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2229         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2230         if (iboost)
2231                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2232         else
2233                 tmp |= BALANCE_LEG_DISABLE(port);
2234         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2235 }
2236
2237 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2238                                int level, enum intel_output_type type)
2239 {
2240         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2242         enum port port = encoder->port;
2243         u8 iboost;
2244
2245         if (type == INTEL_OUTPUT_HDMI)
2246                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2247         else
2248                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2249
2250         if (iboost == 0) {
2251                 const struct ddi_buf_trans *ddi_translations;
2252                 int n_entries;
2253
2254                 if (type == INTEL_OUTPUT_HDMI)
2255                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2256                 else if (type == INTEL_OUTPUT_EDP)
2257                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2258                 else
2259                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2260
2261                 if (WARN_ON_ONCE(!ddi_translations))
2262                         return;
2263                 if (WARN_ON_ONCE(level >= n_entries))
2264                         level = n_entries - 1;
2265
2266                 iboost = ddi_translations[level].i_boost;
2267         }
2268
2269         /* Make sure that the requested I_boost is valid */
2270         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2271                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2272                 return;
2273         }
2274
2275         _skl_ddi_set_iboost(dev_priv, port, iboost);
2276
2277         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2278                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2279 }
2280
2281 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2282                                     int level, enum intel_output_type type)
2283 {
2284         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2285         const struct bxt_ddi_buf_trans *ddi_translations;
2286         enum port port = encoder->port;
2287         int n_entries;
2288
2289         if (type == INTEL_OUTPUT_HDMI)
2290                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2291         else if (type == INTEL_OUTPUT_EDP)
2292                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2293         else
2294                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2295
2296         if (WARN_ON_ONCE(!ddi_translations))
2297                 return;
2298         if (WARN_ON_ONCE(level >= n_entries))
2299                 level = n_entries - 1;
2300
2301         bxt_ddi_phy_set_signal_level(dev_priv, port,
2302                                      ddi_translations[level].margin,
2303                                      ddi_translations[level].scale,
2304                                      ddi_translations[level].enable,
2305                                      ddi_translations[level].deemphasis);
2306 }
2307
2308 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2309 {
2310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2311         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2312         enum port port = encoder->port;
2313         enum phy phy = intel_port_to_phy(dev_priv, port);
2314         int n_entries;
2315
2316         if (INTEL_GEN(dev_priv) >= 11) {
2317                 if (intel_phy_is_combo(dev_priv, phy))
2318                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2319                                                 intel_dp->link_rate, &n_entries);
2320                 else
2321                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2322         } else if (IS_CANNONLAKE(dev_priv)) {
2323                 if (encoder->type == INTEL_OUTPUT_EDP)
2324                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2325                 else
2326                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2327         } else if (IS_GEN9_LP(dev_priv)) {
2328                 if (encoder->type == INTEL_OUTPUT_EDP)
2329                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2330                 else
2331                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2332         } else {
2333                 if (encoder->type == INTEL_OUTPUT_EDP)
2334                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2335                 else
2336                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2337         }
2338
2339         if (WARN_ON(n_entries < 1))
2340                 n_entries = 1;
2341         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2342                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2343
2344         return index_to_dp_signal_levels[n_entries - 1] &
2345                 DP_TRAIN_VOLTAGE_SWING_MASK;
2346 }
2347
2348 /*
2349  * We assume that the full set of pre-emphasis values can be
2350  * used on all DDI platforms. Should that change we need to
2351  * rethink this code.
2352  */
2353 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2354 {
2355         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2356         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2357                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2358         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2359                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2360         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2361                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2362         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2363         default:
2364                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2365         }
2366 }
2367
2368 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2369                                    int level, enum intel_output_type type)
2370 {
2371         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2372         const struct cnl_ddi_buf_trans *ddi_translations;
2373         enum port port = encoder->port;
2374         int n_entries, ln;
2375         u32 val;
2376
2377         if (type == INTEL_OUTPUT_HDMI)
2378                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2379         else if (type == INTEL_OUTPUT_EDP)
2380                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2381         else
2382                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2383
2384         if (WARN_ON_ONCE(!ddi_translations))
2385                 return;
2386         if (WARN_ON_ONCE(level >= n_entries))
2387                 level = n_entries - 1;
2388
2389         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2390         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2391         val &= ~SCALING_MODE_SEL_MASK;
2392         val |= SCALING_MODE_SEL(2);
2393         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2394
2395         /* Program PORT_TX_DW2 */
2396         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2397         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2398                  RCOMP_SCALAR_MASK);
2399         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2400         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2401         /* Rcomp scalar is fixed as 0x98 for every table entry */
2402         val |= RCOMP_SCALAR(0x98);
2403         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2404
2405         /* Program PORT_TX_DW4 */
2406         /* We cannot write to GRP. It would overrite individual loadgen */
2407         for (ln = 0; ln < 4; ln++) {
2408                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2409                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2410                          CURSOR_COEFF_MASK);
2411                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2412                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2413                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2414                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2415         }
2416
2417         /* Program PORT_TX_DW5 */
2418         /* All DW5 values are fixed for every table entry */
2419         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2420         val &= ~RTERM_SELECT_MASK;
2421         val |= RTERM_SELECT(6);
2422         val |= TAP3_DISABLE;
2423         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2424
2425         /* Program PORT_TX_DW7 */
2426         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2427         val &= ~N_SCALAR_MASK;
2428         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2429         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2430 }
2431
2432 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2433                                     int level, enum intel_output_type type)
2434 {
2435         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2436         enum port port = encoder->port;
2437         int width, rate, ln;
2438         u32 val;
2439
2440         if (type == INTEL_OUTPUT_HDMI) {
2441                 width = 4;
2442                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2443         } else {
2444                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2445
2446                 width = intel_dp->lane_count;
2447                 rate = intel_dp->link_rate;
2448         }
2449
2450         /*
2451          * 1. If port type is eDP or DP,
2452          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2453          * else clear to 0b.
2454          */
2455         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2456         if (type != INTEL_OUTPUT_HDMI)
2457                 val |= COMMON_KEEPER_EN;
2458         else
2459                 val &= ~COMMON_KEEPER_EN;
2460         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2461
2462         /* 2. Program loadgen select */
2463         /*
2464          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2465          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2466          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2467          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2468          */
2469         for (ln = 0; ln <= 3; ln++) {
2470                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2471                 val &= ~LOADGEN_SELECT;
2472
2473                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2474                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2475                         val |= LOADGEN_SELECT;
2476                 }
2477                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2478         }
2479
2480         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2481         val = I915_READ(CNL_PORT_CL1CM_DW5);
2482         val |= SUS_CLOCK_CONFIG;
2483         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2484
2485         /* 4. Clear training enable to change swing values */
2486         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2487         val &= ~TX_TRAINING_EN;
2488         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2489
2490         /* 5. Program swing and de-emphasis */
2491         cnl_ddi_vswing_program(encoder, level, type);
2492
2493         /* 6. Set training enable to trigger update */
2494         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2495         val |= TX_TRAINING_EN;
2496         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2497 }
2498
2499 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2500                                         u32 level, enum phy phy, int type,
2501                                         int rate)
2502 {
2503         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2504         u32 n_entries, val;
2505         int ln;
2506
2507         ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2508                                                    &n_entries);
2509         if (!ddi_translations)
2510                 return;
2511
2512         if (level >= n_entries) {
2513                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2514                 level = n_entries - 1;
2515         }
2516
2517         /* Set PORT_TX_DW5 */
2518         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2519         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2520                   TAP2_DISABLE | TAP3_DISABLE);
2521         val |= SCALING_MODE_SEL(0x2);
2522         val |= RTERM_SELECT(0x6);
2523         val |= TAP3_DISABLE;
2524         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2525
2526         /* Program PORT_TX_DW2 */
2527         val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2528         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2529                  RCOMP_SCALAR_MASK);
2530         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2531         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2532         /* Program Rcomp scalar for every table entry */
2533         val |= RCOMP_SCALAR(0x98);
2534         I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2535
2536         /* Program PORT_TX_DW4 */
2537         /* We cannot write to GRP. It would overwrite individual loadgen. */
2538         for (ln = 0; ln <= 3; ln++) {
2539                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2540                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2541                          CURSOR_COEFF_MASK);
2542                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2543                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2544                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2545                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2546         }
2547
2548         /* Program PORT_TX_DW7 */
2549         val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2550         val &= ~N_SCALAR_MASK;
2551         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2552         I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2553 }
2554
2555 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2556                                               u32 level,
2557                                               enum intel_output_type type)
2558 {
2559         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2560         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2561         int width = 0;
2562         int rate = 0;
2563         u32 val;
2564         int ln = 0;
2565
2566         if (type == INTEL_OUTPUT_HDMI) {
2567                 width = 4;
2568                 /* Rate is always < than 6GHz for HDMI */
2569         } else {
2570                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2571
2572                 width = intel_dp->lane_count;
2573                 rate = intel_dp->link_rate;
2574         }
2575
2576         /*
2577          * 1. If port type is eDP or DP,
2578          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2579          * else clear to 0b.
2580          */
2581         val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2582         if (type == INTEL_OUTPUT_HDMI)
2583                 val &= ~COMMON_KEEPER_EN;
2584         else
2585                 val |= COMMON_KEEPER_EN;
2586         I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2587
2588         /* 2. Program loadgen select */
2589         /*
2590          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2591          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2592          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2593          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2594          */
2595         for (ln = 0; ln <= 3; ln++) {
2596                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2597                 val &= ~LOADGEN_SELECT;
2598
2599                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2600                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2601                         val |= LOADGEN_SELECT;
2602                 }
2603                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2604         }
2605
2606         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2607         val = I915_READ(ICL_PORT_CL_DW5(phy));
2608         val |= SUS_CLOCK_CONFIG;
2609         I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2610
2611         /* 4. Clear training enable to change swing values */
2612         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2613         val &= ~TX_TRAINING_EN;
2614         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2615
2616         /* 5. Program swing and de-emphasis */
2617         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2618
2619         /* 6. Set training enable to trigger update */
2620         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2621         val |= TX_TRAINING_EN;
2622         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2623 }
2624
2625 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2626                                            int link_clock,
2627                                            u32 level)
2628 {
2629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2630         enum port port = encoder->port;
2631         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2632         u32 n_entries, val;
2633         int ln;
2634
2635         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2636         ddi_translations = icl_mg_phy_ddi_translations;
2637         /* The table does not have values for level 3 and level 9. */
2638         if (level >= n_entries || level == 3 || level == 9) {
2639                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2640                               level, n_entries - 2);
2641                 level = n_entries - 2;
2642         }
2643
2644         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2645         for (ln = 0; ln < 2; ln++) {
2646                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2647                 val &= ~CRI_USE_FS32;
2648                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2649
2650                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2651                 val &= ~CRI_USE_FS32;
2652                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2653         }
2654
2655         /* Program MG_TX_SWINGCTRL with values from vswing table */
2656         for (ln = 0; ln < 2; ln++) {
2657                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2658                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2659                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2660                         ddi_translations[level].cri_txdeemph_override_17_12);
2661                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2662
2663                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2664                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2665                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2666                         ddi_translations[level].cri_txdeemph_override_17_12);
2667                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2668         }
2669
2670         /* Program MG_TX_DRVCTRL with values from vswing table */
2671         for (ln = 0; ln < 2; ln++) {
2672                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2673                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2674                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2675                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2676                         ddi_translations[level].cri_txdeemph_override_5_0) |
2677                         CRI_TXDEEMPH_OVERRIDE_11_6(
2678                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2679                         CRI_TXDEEMPH_OVERRIDE_EN;
2680                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2681
2682                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2683                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2684                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2685                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2686                         ddi_translations[level].cri_txdeemph_override_5_0) |
2687                         CRI_TXDEEMPH_OVERRIDE_11_6(
2688                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2689                         CRI_TXDEEMPH_OVERRIDE_EN;
2690                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2691
2692                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2693         }
2694
2695         /*
2696          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2697          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2698          * values from table for which TX1 and TX2 enabled.
2699          */
2700         for (ln = 0; ln < 2; ln++) {
2701                 val = I915_READ(MG_CLKHUB(ln, port));
2702                 if (link_clock < 300000)
2703                         val |= CFG_LOW_RATE_LKREN_EN;
2704                 else
2705                         val &= ~CFG_LOW_RATE_LKREN_EN;
2706                 I915_WRITE(MG_CLKHUB(ln, port), val);
2707         }
2708
2709         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2710         for (ln = 0; ln < 2; ln++) {
2711                 val = I915_READ(MG_TX1_DCC(ln, port));
2712                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2713                 if (link_clock <= 500000) {
2714                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2715                 } else {
2716                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2717                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2718                 }
2719                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2720
2721                 val = I915_READ(MG_TX2_DCC(ln, port));
2722                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2723                 if (link_clock <= 500000) {
2724                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2725                 } else {
2726                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2727                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2728                 }
2729                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2730         }
2731
2732         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2733         for (ln = 0; ln < 2; ln++) {
2734                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2735                 val |= CRI_CALCINIT;
2736                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2737
2738                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2739                 val |= CRI_CALCINIT;
2740                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2741         }
2742 }
2743
2744 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2745                                     int link_clock,
2746                                     u32 level,
2747                                     enum intel_output_type type)
2748 {
2749         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2750         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2751
2752         if (intel_phy_is_combo(dev_priv, phy))
2753                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2754         else
2755                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2756 }
2757
2758 static u32 translate_signal_level(int signal_levels)
2759 {
2760         int i;
2761
2762         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2763                 if (index_to_dp_signal_levels[i] == signal_levels)
2764                         return i;
2765         }
2766
2767         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2768              signal_levels);
2769
2770         return 0;
2771 }
2772
2773 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2774 {
2775         u8 train_set = intel_dp->train_set[0];
2776         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2777                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2778
2779         return translate_signal_level(signal_levels);
2780 }
2781
2782 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2783 {
2784         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2785         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2786         struct intel_encoder *encoder = &dport->base;
2787         int level = intel_ddi_dp_level(intel_dp);
2788
2789         if (INTEL_GEN(dev_priv) >= 11)
2790                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2791                                         level, encoder->type);
2792         else if (IS_CANNONLAKE(dev_priv))
2793                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2794         else
2795                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2796
2797         return 0;
2798 }
2799
2800 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2801 {
2802         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2803         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2804         struct intel_encoder *encoder = &dport->base;
2805         int level = intel_ddi_dp_level(intel_dp);
2806
2807         if (IS_GEN9_BC(dev_priv))
2808                 skl_ddi_set_iboost(encoder, level, encoder->type);
2809
2810         return DDI_BUF_TRANS_SELECT(level);
2811 }
2812
2813 static inline
2814 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2815                               enum phy phy)
2816 {
2817         if (intel_phy_is_combo(dev_priv, phy)) {
2818                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2819         } else if (intel_phy_is_tc(dev_priv, phy)) {
2820                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2821                                                         (enum port)phy);
2822
2823                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2824         }
2825
2826         return 0;
2827 }
2828
2829 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2830                                   const struct intel_crtc_state *crtc_state)
2831 {
2832         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2833         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2834         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2835         u32 val;
2836
2837         mutex_lock(&dev_priv->dpll_lock);
2838
2839         val = I915_READ(ICL_DPCLKA_CFGCR0);
2840         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2841
2842         if (intel_phy_is_combo(dev_priv, phy)) {
2843                 /*
2844                  * Even though this register references DDIs, note that we
2845                  * want to pass the PHY rather than the port (DDI).  For
2846                  * ICL, port=phy in all cases so it doesn't matter, but for
2847                  * EHL the bspec notes the following:
2848                  *
2849                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2850                  *   Clock Select chooses the PLL for both DDIA and DDID and
2851                  *   drives port A in all cases."
2852                  */
2853                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2854                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2855                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2856                 POSTING_READ(ICL_DPCLKA_CFGCR0);
2857         }
2858
2859         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2860         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2861
2862         mutex_unlock(&dev_priv->dpll_lock);
2863 }
2864
2865 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2866 {
2867         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2868         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2869         u32 val;
2870
2871         mutex_lock(&dev_priv->dpll_lock);
2872
2873         val = I915_READ(ICL_DPCLKA_CFGCR0);
2874         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2875         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2876
2877         mutex_unlock(&dev_priv->dpll_lock);
2878 }
2879
2880 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2881 {
2882         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2883         u32 val;
2884         enum port port;
2885         u32 port_mask;
2886         bool ddi_clk_needed;
2887
2888         /*
2889          * In case of DP MST, we sanitize the primary encoder only, not the
2890          * virtual ones.
2891          */
2892         if (encoder->type == INTEL_OUTPUT_DP_MST)
2893                 return;
2894
2895         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2896                 u8 pipe_mask;
2897                 bool is_mst;
2898
2899                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2900                 /*
2901                  * In the unlikely case that BIOS enables DP in MST mode, just
2902                  * warn since our MST HW readout is incomplete.
2903                  */
2904                 if (WARN_ON(is_mst))
2905                         return;
2906         }
2907
2908         port_mask = BIT(encoder->port);
2909         ddi_clk_needed = encoder->base.crtc;
2910
2911         if (encoder->type == INTEL_OUTPUT_DSI) {
2912                 struct intel_encoder *other_encoder;
2913
2914                 port_mask = intel_dsi_encoder_ports(encoder);
2915                 /*
2916                  * Sanity check that we haven't incorrectly registered another
2917                  * encoder using any of the ports of this DSI encoder.
2918                  */
2919                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2920                         if (other_encoder == encoder)
2921                                 continue;
2922
2923                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2924                                 return;
2925                 }
2926                 /*
2927                  * For DSI we keep the ddi clocks gated
2928                  * except during enable/disable sequence.
2929                  */
2930                 ddi_clk_needed = false;
2931         }
2932
2933         val = I915_READ(ICL_DPCLKA_CFGCR0);
2934         for_each_port_masked(port, port_mask) {
2935                 enum phy phy = intel_port_to_phy(dev_priv, port);
2936
2937                 bool ddi_clk_ungated = !(val &
2938                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2939                                                                    phy));
2940
2941                 if (ddi_clk_needed == ddi_clk_ungated)
2942                         continue;
2943
2944                 /*
2945                  * Punt on the case now where clock is gated, but it would
2946                  * be needed by the port. Something else is really broken then.
2947                  */
2948                 if (WARN_ON(ddi_clk_needed))
2949                         continue;
2950
2951                 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2952                          phy_name(port));
2953                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2954                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2955         }
2956 }
2957
2958 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2959                                  const struct intel_crtc_state *crtc_state)
2960 {
2961         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2962         enum port port = encoder->port;
2963         enum phy phy = intel_port_to_phy(dev_priv, port);
2964         u32 val;
2965         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2966
2967         if (WARN_ON(!pll))
2968                 return;
2969
2970         mutex_lock(&dev_priv->dpll_lock);
2971
2972         if (INTEL_GEN(dev_priv) >= 11) {
2973                 if (!intel_phy_is_combo(dev_priv, phy))
2974                         I915_WRITE(DDI_CLK_SEL(port),
2975                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2976                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2977                         /*
2978                          * MG does not exist but the programming is required
2979                          * to ungate DDIC and DDID
2980                          */
2981                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
2982         } else if (IS_CANNONLAKE(dev_priv)) {
2983                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2984                 val = I915_READ(DPCLKA_CFGCR0);
2985                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2986                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2987                 I915_WRITE(DPCLKA_CFGCR0, val);
2988
2989                 /*
2990                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2991                  * This step and the step before must be done with separate
2992                  * register writes.
2993                  */
2994                 val = I915_READ(DPCLKA_CFGCR0);
2995                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2996                 I915_WRITE(DPCLKA_CFGCR0, val);
2997         } else if (IS_GEN9_BC(dev_priv)) {
2998                 /* DDI -> PLL mapping  */
2999                 val = I915_READ(DPLL_CTRL2);
3000
3001                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3002                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3003                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3004                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3005
3006                 I915_WRITE(DPLL_CTRL2, val);
3007
3008         } else if (INTEL_GEN(dev_priv) < 9) {
3009                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
3010         }
3011
3012         mutex_unlock(&dev_priv->dpll_lock);
3013 }
3014
3015 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3016 {
3017         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3018         enum port port = encoder->port;
3019         enum phy phy = intel_port_to_phy(dev_priv, port);
3020
3021         if (INTEL_GEN(dev_priv) >= 11) {
3022                 if (!intel_phy_is_combo(dev_priv, phy) ||
3023                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3024                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3025         } else if (IS_CANNONLAKE(dev_priv)) {
3026                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3027                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3028         } else if (IS_GEN9_BC(dev_priv)) {
3029                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3030                            DPLL_CTRL2_DDI_CLK_OFF(port));
3031         } else if (INTEL_GEN(dev_priv) < 9) {
3032                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3033         }
3034 }
3035
3036 static void
3037 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
3038 {
3039         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3040         enum port port = dig_port->base.port;
3041         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3042         u32 val, bits;
3043         int ln;
3044
3045         if (tc_port == PORT_TC_NONE)
3046                 return;
3047
3048         bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
3049                MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
3050                MG_DP_MODE_CFG_GAONPWR_GATING;
3051
3052         for (ln = 0; ln < 2; ln++) {
3053                 val = I915_READ(MG_DP_MODE(ln, port));
3054                 if (enable)
3055                         val |= bits;
3056                 else
3057                         val &= ~bits;
3058                 I915_WRITE(MG_DP_MODE(ln, port), val);
3059         }
3060
3061         bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING |
3062                MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING |
3063                MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING;
3064
3065         val = I915_READ(MG_MISC_SUS0(tc_port));
3066         if (enable)
3067                 val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
3068         else
3069                 val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
3070         I915_WRITE(MG_MISC_SUS0(tc_port), val);
3071 }
3072
3073 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3074 {
3075         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3076         enum port port = intel_dig_port->base.port;
3077         u32 ln0, ln1, lane_mask;
3078
3079         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3080                 return;
3081
3082         ln0 = I915_READ(MG_DP_MODE(0, port));
3083         ln1 = I915_READ(MG_DP_MODE(1, port));
3084
3085         switch (intel_dig_port->tc_mode) {
3086         case TC_PORT_DP_ALT:
3087                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3088                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3089
3090                 lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
3091
3092                 switch (lane_mask) {
3093                 case 0x1:
3094                 case 0x4:
3095                         break;
3096                 case 0x2:
3097                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3098                         break;
3099                 case 0x3:
3100                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3101                                MG_DP_MODE_CFG_DP_X2_MODE;
3102                         break;
3103                 case 0x8:
3104                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3105                         break;
3106                 case 0xC:
3107                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3108                                MG_DP_MODE_CFG_DP_X2_MODE;
3109                         break;
3110                 case 0xF:
3111                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3112                                MG_DP_MODE_CFG_DP_X2_MODE;
3113                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3114                                MG_DP_MODE_CFG_DP_X2_MODE;
3115                         break;
3116                 default:
3117                         MISSING_CASE(lane_mask);
3118                 }
3119                 break;
3120
3121         case TC_PORT_LEGACY:
3122                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3123                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3124                 break;
3125
3126         default:
3127                 MISSING_CASE(intel_dig_port->tc_mode);
3128                 return;
3129         }
3130
3131         I915_WRITE(MG_DP_MODE(0, port), ln0);
3132         I915_WRITE(MG_DP_MODE(1, port), ln1);
3133 }
3134
3135 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3136                                         const struct intel_crtc_state *crtc_state)
3137 {
3138         if (!crtc_state->fec_enable)
3139                 return;
3140
3141         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3142                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3143 }
3144
3145 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3146                                  const struct intel_crtc_state *crtc_state)
3147 {
3148         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3149         struct intel_dp *intel_dp;
3150         u32 val;
3151
3152         if (!crtc_state->fec_enable)
3153                 return;
3154
3155         intel_dp = enc_to_intel_dp(&encoder->base);
3156         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3157         val |= DP_TP_CTL_FEC_ENABLE;
3158         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3159
3160         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3161                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3162                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3163 }
3164
3165 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3166                                         const struct intel_crtc_state *crtc_state)
3167 {
3168         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3169         struct intel_dp *intel_dp;
3170         u32 val;
3171
3172         if (!crtc_state->fec_enable)
3173                 return;
3174
3175         intel_dp = enc_to_intel_dp(&encoder->base);
3176         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3177         val &= ~DP_TP_CTL_FEC_ENABLE;
3178         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3179         POSTING_READ(intel_dp->regs.dp_tp_ctl);
3180 }
3181
3182 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3183                                   const struct intel_crtc_state *crtc_state,
3184                                   const struct drm_connector_state *conn_state)
3185 {
3186         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3187         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3188         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3189         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3190         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3191         int level = intel_ddi_dp_level(intel_dp);
3192         enum transcoder transcoder = crtc_state->cpu_transcoder;
3193
3194         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3195                                  crtc_state->lane_count, is_mst);
3196
3197         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3198         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3199
3200         /* 1.a got on intel_atomic_commit_tail() */
3201
3202         /* 2. */
3203         intel_edp_panel_on(intel_dp);
3204
3205         /*
3206          * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
3207          * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
3208          * haswell_crtc_enable()->intel_enable_shared_dpll()
3209          */
3210
3211         /* 4.b */
3212         intel_ddi_clk_select(encoder, crtc_state);
3213
3214         /* 5. */
3215         if (!intel_phy_is_tc(dev_priv, phy) ||
3216             dig_port->tc_mode != TC_PORT_TBT_ALT)
3217                 intel_display_power_get(dev_priv,
3218                                         dig_port->ddi_io_power_domain);
3219
3220         /* 6. */
3221         icl_program_mg_dp_mode(dig_port);
3222
3223         /*
3224          * 7.a - Steps in this function should only be executed over MST
3225          * master, what will be taken in care by MST hook
3226          * intel_mst_pre_enable_dp()
3227          */
3228         intel_ddi_enable_pipe_clock(crtc_state);
3229
3230         /* 7.b */
3231         intel_ddi_config_transcoder_func(crtc_state);
3232
3233         /* 7.d */
3234         icl_phy_set_clock_gating(dig_port, false);
3235
3236         /* 7.e */
3237         icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3238                                 encoder->type);
3239
3240         /* 7.f */
3241         if (intel_phy_is_combo(dev_priv, phy)) {
3242                 bool lane_reversal =
3243                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3244
3245                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3246                                                crtc_state->lane_count,
3247                                                lane_reversal);
3248         }
3249
3250         /* 7.g */
3251         intel_ddi_init_dp_buf_reg(encoder);
3252
3253         if (!is_mst)
3254                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3255
3256         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3257         /*
3258          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3259          * in the FEC_CONFIGURATION register to 1 before initiating link
3260          * training
3261          */
3262         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3263         /* 7.c, 7.h, 7.i, 7.j */
3264         intel_dp_start_link_train(intel_dp);
3265
3266         /* 7.k */
3267         intel_dp_stop_link_train(intel_dp);
3268
3269         /* 7.l */
3270         intel_ddi_enable_fec(encoder, crtc_state);
3271         intel_dsc_enable(encoder, crtc_state);
3272 }
3273
3274 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3275                                   const struct intel_crtc_state *crtc_state,
3276                                   const struct drm_connector_state *conn_state)
3277 {
3278         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3279         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3280         enum port port = encoder->port;
3281         enum phy phy = intel_port_to_phy(dev_priv, port);
3282         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3283         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3284         int level = intel_ddi_dp_level(intel_dp);
3285
3286         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3287
3288         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3289                                  crtc_state->lane_count, is_mst);
3290
3291         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3292         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3293
3294         intel_edp_panel_on(intel_dp);
3295
3296         intel_ddi_clk_select(encoder, crtc_state);
3297
3298         if (!intel_phy_is_tc(dev_priv, phy) ||
3299             dig_port->tc_mode != TC_PORT_TBT_ALT)
3300                 intel_display_power_get(dev_priv,
3301                                         dig_port->ddi_io_power_domain);
3302
3303         icl_program_mg_dp_mode(dig_port);
3304         icl_phy_set_clock_gating(dig_port, false);
3305
3306         if (INTEL_GEN(dev_priv) >= 11)
3307                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3308                                         level, encoder->type);
3309         else if (IS_CANNONLAKE(dev_priv))
3310                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3311         else if (IS_GEN9_LP(dev_priv))
3312                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3313         else
3314                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3315
3316         if (intel_phy_is_combo(dev_priv, phy)) {
3317                 bool lane_reversal =
3318                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3319
3320                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3321                                                crtc_state->lane_count,
3322                                                lane_reversal);
3323         }
3324
3325         intel_ddi_init_dp_buf_reg(encoder);
3326         if (!is_mst)
3327                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3328         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3329                                               true);
3330         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3331         intel_dp_start_link_train(intel_dp);
3332         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3333                 intel_dp_stop_link_train(intel_dp);
3334
3335         intel_ddi_enable_fec(encoder, crtc_state);
3336
3337         icl_phy_set_clock_gating(dig_port, true);
3338
3339         if (!is_mst)
3340                 intel_ddi_enable_pipe_clock(crtc_state);
3341
3342         intel_dsc_enable(encoder, crtc_state);
3343 }
3344
3345 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3346                                     const struct intel_crtc_state *crtc_state,
3347                                     const struct drm_connector_state *conn_state)
3348 {
3349         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3350
3351         if (INTEL_GEN(dev_priv) >= 12)
3352                 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3353         else
3354                 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3355 }
3356
3357 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3358                                       const struct intel_crtc_state *crtc_state,
3359                                       const struct drm_connector_state *conn_state)
3360 {
3361         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3362         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3363         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3364         enum port port = encoder->port;
3365         int level = intel_ddi_hdmi_level(dev_priv, port);
3366         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3367
3368         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3369         intel_ddi_clk_select(encoder, crtc_state);
3370
3371         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3372
3373         icl_program_mg_dp_mode(dig_port);
3374         icl_phy_set_clock_gating(dig_port, false);
3375
3376         if (INTEL_GEN(dev_priv) >= 11)
3377                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3378                                         level, INTEL_OUTPUT_HDMI);
3379         else if (IS_CANNONLAKE(dev_priv))
3380                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3381         else if (IS_GEN9_LP(dev_priv))
3382                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3383         else
3384                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3385
3386         icl_phy_set_clock_gating(dig_port, true);
3387
3388         if (IS_GEN9_BC(dev_priv))
3389                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3390
3391         intel_ddi_enable_pipe_clock(crtc_state);
3392
3393         intel_dig_port->set_infoframes(encoder,
3394                                        crtc_state->has_infoframe,
3395                                        crtc_state, conn_state);
3396 }
3397
3398 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3399                                  const struct intel_crtc_state *crtc_state,
3400                                  const struct drm_connector_state *conn_state)
3401 {
3402         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3403         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3404         enum pipe pipe = crtc->pipe;
3405
3406         /*
3407          * When called from DP MST code:
3408          * - conn_state will be NULL
3409          * - encoder will be the main encoder (ie. mst->primary)
3410          * - the main connector associated with this port
3411          *   won't be active or linked to a crtc
3412          * - crtc_state will be the state of the first stream to
3413          *   be activated on this port, and it may not be the same
3414          *   stream that will be deactivated last, but each stream
3415          *   should have a state that is identical when it comes to
3416          *   the DP link parameteres
3417          */
3418
3419         WARN_ON(crtc_state->has_pch_encoder);
3420
3421         if (INTEL_GEN(dev_priv) >= 11)
3422                 icl_map_plls_to_ports(encoder, crtc_state);
3423
3424         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3425
3426         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3427                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3428         } else {
3429                 struct intel_lspcon *lspcon =
3430                                 enc_to_intel_lspcon(&encoder->base);
3431
3432                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3433                 if (lspcon->active) {
3434                         struct intel_digital_port *dig_port =
3435                                         enc_to_dig_port(&encoder->base);
3436
3437                         dig_port->set_infoframes(encoder,
3438                                                  crtc_state->has_infoframe,
3439                                                  crtc_state, conn_state);
3440                 }
3441         }
3442 }
3443
3444 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3445                                   const struct intel_crtc_state *crtc_state)
3446 {
3447         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3448         enum port port = encoder->port;
3449         bool wait = false;
3450         u32 val;
3451
3452         val = I915_READ(DDI_BUF_CTL(port));
3453         if (val & DDI_BUF_CTL_ENABLE) {
3454                 val &= ~DDI_BUF_CTL_ENABLE;
3455                 I915_WRITE(DDI_BUF_CTL(port), val);
3456                 wait = true;
3457         }
3458
3459         if (intel_crtc_has_dp_encoder(crtc_state)) {
3460                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3461
3462                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3463                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3464                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3465                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3466         }
3467
3468         /* Disable FEC in DP Sink */
3469         intel_ddi_disable_fec_state(encoder, crtc_state);
3470
3471         if (wait)
3472                 intel_wait_ddi_buf_idle(dev_priv, port);
3473 }
3474
3475 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3476                                       const struct intel_crtc_state *old_crtc_state,
3477                                       const struct drm_connector_state *old_conn_state)
3478 {
3479         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3480         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3481         struct intel_dp *intel_dp = &dig_port->dp;
3482         bool is_mst = intel_crtc_has_type(old_crtc_state,
3483                                           INTEL_OUTPUT_DP_MST);
3484         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3485
3486         if (!is_mst) {
3487                 intel_ddi_disable_pipe_clock(old_crtc_state);
3488                 /*
3489                  * Power down sink before disabling the port, otherwise we end
3490                  * up getting interrupts from the sink on detecting link loss.
3491                  */
3492                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3493         }
3494
3495         intel_disable_ddi_buf(encoder, old_crtc_state);
3496
3497         intel_edp_panel_vdd_on(intel_dp);
3498         intel_edp_panel_off(intel_dp);
3499
3500         if (!intel_phy_is_tc(dev_priv, phy) ||
3501             dig_port->tc_mode != TC_PORT_TBT_ALT)
3502                 intel_display_power_put_unchecked(dev_priv,
3503                                                   dig_port->ddi_io_power_domain);
3504
3505         intel_ddi_clk_disable(encoder);
3506 }
3507
3508 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3509                                         const struct intel_crtc_state *old_crtc_state,
3510                                         const struct drm_connector_state *old_conn_state)
3511 {
3512         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3513         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3514         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3515
3516         dig_port->set_infoframes(encoder, false,
3517                                  old_crtc_state, old_conn_state);
3518
3519         intel_ddi_disable_pipe_clock(old_crtc_state);
3520
3521         intel_disable_ddi_buf(encoder, old_crtc_state);
3522
3523         intel_display_power_put_unchecked(dev_priv,
3524                                           dig_port->ddi_io_power_domain);
3525
3526         intel_ddi_clk_disable(encoder);
3527
3528         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3529 }
3530
3531 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3532                                    const struct intel_crtc_state *old_crtc_state,
3533                                    const struct drm_connector_state *old_conn_state)
3534 {
3535         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3536
3537         /*
3538          * When called from DP MST code:
3539          * - old_conn_state will be NULL
3540          * - encoder will be the main encoder (ie. mst->primary)
3541          * - the main connector associated with this port
3542          *   won't be active or linked to a crtc
3543          * - old_crtc_state will be the state of the last stream to
3544          *   be deactivated on this port, and it may not be the same
3545          *   stream that was activated last, but each stream
3546          *   should have a state that is identical when it comes to
3547          *   the DP link parameteres
3548          */
3549
3550         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3551                 intel_ddi_post_disable_hdmi(encoder,
3552                                             old_crtc_state, old_conn_state);
3553         else
3554                 intel_ddi_post_disable_dp(encoder,
3555                                           old_crtc_state, old_conn_state);
3556
3557         if (INTEL_GEN(dev_priv) >= 11)
3558                 icl_unmap_plls_to_ports(encoder);
3559 }
3560
3561 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3562                                 const struct intel_crtc_state *old_crtc_state,
3563                                 const struct drm_connector_state *old_conn_state)
3564 {
3565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3566         u32 val;
3567
3568         /*
3569          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3570          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3571          * step 13 is the correct place for it. Step 18 is where it was
3572          * originally before the BUN.
3573          */
3574         val = I915_READ(FDI_RX_CTL(PIPE_A));
3575         val &= ~FDI_RX_ENABLE;
3576         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3577
3578         intel_disable_ddi_buf(encoder, old_crtc_state);
3579         intel_ddi_clk_disable(encoder);
3580
3581         val = I915_READ(FDI_RX_MISC(PIPE_A));
3582         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3583         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3584         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3585
3586         val = I915_READ(FDI_RX_CTL(PIPE_A));
3587         val &= ~FDI_PCDCLK;
3588         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3589
3590         val = I915_READ(FDI_RX_CTL(PIPE_A));
3591         val &= ~FDI_RX_PLL_ENABLE;
3592         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3593 }
3594
3595 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3596                                 const struct intel_crtc_state *crtc_state,
3597                                 const struct drm_connector_state *conn_state)
3598 {
3599         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3600         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3601         enum port port = encoder->port;
3602
3603         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3604                 intel_dp_stop_link_train(intel_dp);
3605
3606         intel_edp_backlight_on(crtc_state, conn_state);
3607         intel_psr_enable(intel_dp, crtc_state);
3608         intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
3609         intel_edp_drrs_enable(intel_dp, crtc_state);
3610
3611         if (crtc_state->has_audio)
3612                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3613 }
3614
3615 static i915_reg_t
3616 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3617                                enum port port)
3618 {
3619         static const i915_reg_t regs[] = {
3620                 [PORT_A] = CHICKEN_TRANS_EDP,
3621                 [PORT_B] = CHICKEN_TRANS_A,
3622                 [PORT_C] = CHICKEN_TRANS_B,
3623                 [PORT_D] = CHICKEN_TRANS_C,
3624                 [PORT_E] = CHICKEN_TRANS_A,
3625         };
3626
3627         WARN_ON(INTEL_GEN(dev_priv) < 9);
3628
3629         if (WARN_ON(port < PORT_A || port > PORT_E))
3630                 port = PORT_A;
3631
3632         return regs[port];
3633 }
3634
3635 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3636                                   const struct intel_crtc_state *crtc_state,
3637                                   const struct drm_connector_state *conn_state)
3638 {
3639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3640         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3641         struct drm_connector *connector = conn_state->connector;
3642         enum port port = encoder->port;
3643
3644         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3645                                                crtc_state->hdmi_high_tmds_clock_ratio,
3646                                                crtc_state->hdmi_scrambling))
3647                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3648                           connector->base.id, connector->name);
3649
3650         /* Display WA #1143: skl,kbl,cfl */
3651         if (IS_GEN9_BC(dev_priv)) {
3652                 /*
3653                  * For some reason these chicken bits have been
3654                  * stuffed into a transcoder register, event though
3655                  * the bits affect a specific DDI port rather than
3656                  * a specific transcoder.
3657                  */
3658                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3659                 u32 val;
3660
3661                 val = I915_READ(reg);
3662
3663                 if (port == PORT_E)
3664                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3665                                 DDIE_TRAINING_OVERRIDE_VALUE;
3666                 else
3667                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3668                                 DDI_TRAINING_OVERRIDE_VALUE;
3669
3670                 I915_WRITE(reg, val);
3671                 POSTING_READ(reg);
3672
3673                 udelay(1);
3674
3675                 if (port == PORT_E)
3676                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3677                                  DDIE_TRAINING_OVERRIDE_VALUE);
3678                 else
3679                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3680                                  DDI_TRAINING_OVERRIDE_VALUE);
3681
3682                 I915_WRITE(reg, val);
3683         }
3684
3685         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3686          * are ignored so nothing special needs to be done besides
3687          * enabling the port.
3688          */
3689         I915_WRITE(DDI_BUF_CTL(port),
3690                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3691
3692         if (crtc_state->has_audio)
3693                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3694 }
3695
3696 static void intel_enable_ddi(struct intel_encoder *encoder,
3697                              const struct intel_crtc_state *crtc_state,
3698                              const struct drm_connector_state *conn_state)
3699 {
3700         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3701                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3702         else
3703                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3704
3705         /* Enable hdcp if it's desired */
3706         if (conn_state->content_protection ==
3707             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3708                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3709                                   (u8)conn_state->hdcp_content_type);
3710 }
3711
3712 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3713                                  const struct intel_crtc_state *old_crtc_state,
3714                                  const struct drm_connector_state *old_conn_state)
3715 {
3716         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3717
3718         intel_dp->link_trained = false;
3719
3720         if (old_crtc_state->has_audio)
3721                 intel_audio_codec_disable(encoder,
3722                                           old_crtc_state, old_conn_state);
3723
3724         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3725         intel_psr_disable(intel_dp, old_crtc_state);
3726         intel_edp_backlight_off(old_conn_state);
3727         /* Disable the decompression in DP Sink */
3728         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3729                                               false);
3730 }
3731
3732 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3733                                    const struct intel_crtc_state *old_crtc_state,
3734                                    const struct drm_connector_state *old_conn_state)
3735 {
3736         struct drm_connector *connector = old_conn_state->connector;
3737
3738         if (old_crtc_state->has_audio)
3739                 intel_audio_codec_disable(encoder,
3740                                           old_crtc_state, old_conn_state);
3741
3742         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3743                                                false, false))
3744                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3745                               connector->base.id, connector->name);
3746 }
3747
3748 static void intel_disable_ddi(struct intel_encoder *encoder,
3749                               const struct intel_crtc_state *old_crtc_state,
3750                               const struct drm_connector_state *old_conn_state)
3751 {
3752         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3753
3754         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3755                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3756         else
3757                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3758 }
3759
3760 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3761                                      const struct intel_crtc_state *crtc_state,
3762                                      const struct drm_connector_state *conn_state)
3763 {
3764         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3765
3766         intel_ddi_set_pipe_settings(crtc_state);
3767
3768         intel_psr_update(intel_dp, crtc_state);
3769         intel_edp_drrs_enable(intel_dp, crtc_state);
3770
3771         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3772 }
3773
3774 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3775                                   const struct intel_crtc_state *crtc_state,
3776                                   const struct drm_connector_state *conn_state)
3777 {
3778         struct intel_connector *connector =
3779                                 to_intel_connector(conn_state->connector);
3780         struct intel_hdcp *hdcp = &connector->hdcp;
3781         bool content_protection_type_changed =
3782                         (conn_state->hdcp_content_type != hdcp->content_type &&
3783                          conn_state->content_protection !=
3784                          DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
3785
3786         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3787                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3788
3789         /*
3790          * During the HDCP encryption session if Type change is requested,
3791          * disable the HDCP and reenable it with new TYPE value.
3792          */
3793         if (conn_state->content_protection ==
3794             DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
3795             content_protection_type_changed)
3796                 intel_hdcp_disable(connector);
3797
3798         /*
3799          * Mark the hdcp state as DESIRED after the hdcp disable of type
3800          * change procedure.
3801          */
3802         if (content_protection_type_changed) {
3803                 mutex_lock(&hdcp->mutex);
3804                 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3805                 schedule_work(&hdcp->prop_work);
3806                 mutex_unlock(&hdcp->mutex);
3807         }
3808
3809         if (conn_state->content_protection ==
3810             DRM_MODE_CONTENT_PROTECTION_DESIRED ||
3811             content_protection_type_changed)
3812                 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
3813 }
3814
3815 static void
3816 intel_ddi_update_prepare(struct intel_atomic_state *state,
3817                          struct intel_encoder *encoder,
3818                          struct intel_crtc *crtc)
3819 {
3820         struct intel_crtc_state *crtc_state =
3821                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3822         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3823
3824         WARN_ON(crtc && crtc->active);
3825
3826         intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3827         if (crtc_state && crtc_state->base.active)
3828                 intel_update_active_dpll(state, crtc, encoder);
3829 }
3830
3831 static void
3832 intel_ddi_update_complete(struct intel_atomic_state *state,
3833                           struct intel_encoder *encoder,
3834                           struct intel_crtc *crtc)
3835 {
3836         intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3837 }
3838
3839 static void
3840 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3841                          const struct intel_crtc_state *crtc_state,
3842                          const struct drm_connector_state *conn_state)
3843 {
3844         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3845         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3846         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3847         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3848
3849         if (is_tc_port)
3850                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3851
3852         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3853                 intel_display_power_get(dev_priv,
3854                                         intel_ddi_main_link_aux_domain(dig_port));
3855
3856         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3857                 /*
3858                  * Program the lane count for static/dynamic connections on
3859                  * Type-C ports.  Skip this step for TBT.
3860                  */
3861                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3862         else if (IS_GEN9_LP(dev_priv))
3863                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3864                                                 crtc_state->lane_lat_optim_mask);
3865 }
3866
3867 static void
3868 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3869                            const struct intel_crtc_state *crtc_state,
3870                            const struct drm_connector_state *conn_state)
3871 {
3872         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3873         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3874         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3875         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3876
3877         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3878                 intel_display_power_put_unchecked(dev_priv,
3879                                                   intel_ddi_main_link_aux_domain(dig_port));
3880
3881         if (is_tc_port)
3882                 intel_tc_port_put_link(dig_port);
3883 }
3884
3885 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3886 {
3887         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3888         struct drm_i915_private *dev_priv =
3889                 to_i915(intel_dig_port->base.base.dev);
3890         enum port port = intel_dig_port->base.port;
3891         u32 val;
3892         bool wait = false;
3893
3894         if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
3895                 val = I915_READ(DDI_BUF_CTL(port));
3896                 if (val & DDI_BUF_CTL_ENABLE) {
3897                         val &= ~DDI_BUF_CTL_ENABLE;
3898                         I915_WRITE(DDI_BUF_CTL(port), val);
3899                         wait = true;
3900                 }
3901
3902                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3903                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3904                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3905                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3906                 POSTING_READ(intel_dp->regs.dp_tp_ctl);
3907
3908                 if (wait)
3909                         intel_wait_ddi_buf_idle(dev_priv, port);
3910         }
3911
3912         val = DP_TP_CTL_ENABLE |
3913               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3914         if (intel_dp->link_mst)
3915                 val |= DP_TP_CTL_MODE_MST;
3916         else {
3917                 val |= DP_TP_CTL_MODE_SST;
3918                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3919                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3920         }
3921         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3922         POSTING_READ(intel_dp->regs.dp_tp_ctl);
3923
3924         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3925         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3926         POSTING_READ(DDI_BUF_CTL(port));
3927
3928         udelay(600);
3929 }
3930
3931 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3932                                        enum transcoder cpu_transcoder)
3933 {
3934         if (cpu_transcoder == TRANSCODER_EDP)
3935                 return false;
3936
3937         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3938                 return false;
3939
3940         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3941                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3942 }
3943
3944 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3945                                          struct intel_crtc_state *crtc_state)
3946 {
3947         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3948                 crtc_state->min_voltage_level = 1;
3949         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3950                 crtc_state->min_voltage_level = 2;
3951 }
3952
3953 void intel_ddi_get_config(struct intel_encoder *encoder,
3954                           struct intel_crtc_state *pipe_config)
3955 {
3956         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3957         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3958         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3959         u32 temp, flags = 0;
3960
3961         /* XXX: DSI transcoder paranoia */
3962         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3963                 return;
3964
3965         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3966         if (temp & TRANS_DDI_PHSYNC)
3967                 flags |= DRM_MODE_FLAG_PHSYNC;
3968         else
3969                 flags |= DRM_MODE_FLAG_NHSYNC;
3970         if (temp & TRANS_DDI_PVSYNC)
3971                 flags |= DRM_MODE_FLAG_PVSYNC;
3972         else
3973                 flags |= DRM_MODE_FLAG_NVSYNC;
3974
3975         pipe_config->base.adjusted_mode.flags |= flags;
3976
3977         switch (temp & TRANS_DDI_BPC_MASK) {
3978         case TRANS_DDI_BPC_6:
3979                 pipe_config->pipe_bpp = 18;
3980                 break;
3981         case TRANS_DDI_BPC_8:
3982                 pipe_config->pipe_bpp = 24;
3983                 break;
3984         case TRANS_DDI_BPC_10:
3985                 pipe_config->pipe_bpp = 30;
3986                 break;
3987         case TRANS_DDI_BPC_12:
3988                 pipe_config->pipe_bpp = 36;
3989                 break;
3990         default:
3991                 break;
3992         }
3993
3994         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3995         case TRANS_DDI_MODE_SELECT_HDMI:
3996                 pipe_config->has_hdmi_sink = true;
3997
3998                 pipe_config->infoframes.enable |=
3999                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4000
4001                 if (pipe_config->infoframes.enable)
4002                         pipe_config->has_infoframe = true;
4003
4004                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4005                         pipe_config->hdmi_scrambling = true;
4006                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4007                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4008                 /* fall through */
4009         case TRANS_DDI_MODE_SELECT_DVI:
4010                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4011                 pipe_config->lane_count = 4;
4012                 break;
4013         case TRANS_DDI_MODE_SELECT_FDI:
4014                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4015                 break;
4016         case TRANS_DDI_MODE_SELECT_DP_SST:
4017                 if (encoder->type == INTEL_OUTPUT_EDP)
4018                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4019                 else
4020                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4021                 pipe_config->lane_count =
4022                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4023                 intel_dp_get_m_n(intel_crtc, pipe_config);
4024
4025                 if (INTEL_GEN(dev_priv) >= 11) {
4026                         i915_reg_t dp_tp_ctl;
4027
4028                         if (IS_GEN(dev_priv, 11))
4029                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4030                         else
4031                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4032
4033                         pipe_config->fec_enable =
4034                                 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4035
4036                         DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
4037                                       encoder->base.base.id, encoder->base.name,
4038                                       pipe_config->fec_enable);
4039                 }
4040
4041                 break;
4042         case TRANS_DDI_MODE_SELECT_DP_MST:
4043                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4044                 pipe_config->lane_count =
4045                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4046                 intel_dp_get_m_n(intel_crtc, pipe_config);
4047                 break;
4048         default:
4049                 break;
4050         }
4051
4052         pipe_config->has_audio =
4053                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4054
4055         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4056             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4057                 /*
4058                  * This is a big fat ugly hack.
4059                  *
4060                  * Some machines in UEFI boot mode provide us a VBT that has 18
4061                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4062                  * unknown we fail to light up. Yet the same BIOS boots up with
4063                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4064                  * max, not what it tells us to use.
4065                  *
4066                  * Note: This will still be broken if the eDP panel is not lit
4067                  * up by the BIOS, and thus we can't get the mode at module
4068                  * load.
4069                  */
4070                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4071                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4072                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4073         }
4074
4075         intel_ddi_clock_get(encoder, pipe_config);
4076
4077         if (IS_GEN9_LP(dev_priv))
4078                 pipe_config->lane_lat_optim_mask =
4079                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4080
4081         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4082
4083         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4084
4085         intel_read_infoframe(encoder, pipe_config,
4086                              HDMI_INFOFRAME_TYPE_AVI,
4087                              &pipe_config->infoframes.avi);
4088         intel_read_infoframe(encoder, pipe_config,
4089                              HDMI_INFOFRAME_TYPE_SPD,
4090                              &pipe_config->infoframes.spd);
4091         intel_read_infoframe(encoder, pipe_config,
4092                              HDMI_INFOFRAME_TYPE_VENDOR,
4093                              &pipe_config->infoframes.hdmi);
4094         intel_read_infoframe(encoder, pipe_config,
4095                              HDMI_INFOFRAME_TYPE_DRM,
4096                              &pipe_config->infoframes.drm);
4097 }
4098
4099 static enum intel_output_type
4100 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4101                               struct intel_crtc_state *crtc_state,
4102                               struct drm_connector_state *conn_state)
4103 {
4104         switch (conn_state->connector->connector_type) {
4105         case DRM_MODE_CONNECTOR_HDMIA:
4106                 return INTEL_OUTPUT_HDMI;
4107         case DRM_MODE_CONNECTOR_eDP:
4108                 return INTEL_OUTPUT_EDP;
4109         case DRM_MODE_CONNECTOR_DisplayPort:
4110                 return INTEL_OUTPUT_DP;
4111         default:
4112                 MISSING_CASE(conn_state->connector->connector_type);
4113                 return INTEL_OUTPUT_UNUSED;
4114         }
4115 }
4116
4117 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4118                                     struct intel_crtc_state *pipe_config,
4119                                     struct drm_connector_state *conn_state)
4120 {
4121         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
4122         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4123         enum port port = encoder->port;
4124         int ret;
4125
4126         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
4127                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4128
4129         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
4130                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4131         else
4132                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4133         if (ret)
4134                 return ret;
4135
4136         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4137             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4138                 pipe_config->pch_pfit.force_thru =
4139                         pipe_config->pch_pfit.enabled ||
4140                         pipe_config->crc_enabled;
4141
4142         if (IS_GEN9_LP(dev_priv))
4143                 pipe_config->lane_lat_optim_mask =
4144                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4145
4146         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4147
4148         return 0;
4149 }
4150
4151 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4152 {
4153         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4154
4155         intel_dp_encoder_flush_work(encoder);
4156
4157         drm_encoder_cleanup(encoder);
4158         kfree(dig_port);
4159 }
4160
4161 static const struct drm_encoder_funcs intel_ddi_funcs = {
4162         .reset = intel_dp_encoder_reset,
4163         .destroy = intel_ddi_encoder_destroy,
4164 };
4165
4166 static struct intel_connector *
4167 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4168 {
4169         struct intel_connector *connector;
4170         enum port port = intel_dig_port->base.port;
4171
4172         connector = intel_connector_alloc();
4173         if (!connector)
4174                 return NULL;
4175
4176         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4177         intel_dig_port->dp.prepare_link_retrain =
4178                 intel_ddi_prepare_link_retrain;
4179
4180         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4181                 kfree(connector);
4182                 return NULL;
4183         }
4184
4185         return connector;
4186 }
4187
4188 static int modeset_pipe(struct drm_crtc *crtc,
4189                         struct drm_modeset_acquire_ctx *ctx)
4190 {
4191         struct drm_atomic_state *state;
4192         struct drm_crtc_state *crtc_state;
4193         int ret;
4194
4195         state = drm_atomic_state_alloc(crtc->dev);
4196         if (!state)
4197                 return -ENOMEM;
4198
4199         state->acquire_ctx = ctx;
4200
4201         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4202         if (IS_ERR(crtc_state)) {
4203                 ret = PTR_ERR(crtc_state);
4204                 goto out;
4205         }
4206
4207         crtc_state->connectors_changed = true;
4208
4209         ret = drm_atomic_commit(state);
4210 out:
4211         drm_atomic_state_put(state);
4212
4213         return ret;
4214 }
4215
4216 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4217                                  struct drm_modeset_acquire_ctx *ctx)
4218 {
4219         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4220         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4221         struct intel_connector *connector = hdmi->attached_connector;
4222         struct i2c_adapter *adapter =
4223                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4224         struct drm_connector_state *conn_state;
4225         struct intel_crtc_state *crtc_state;
4226         struct intel_crtc *crtc;
4227         u8 config;
4228         int ret;
4229
4230         if (!connector || connector->base.status != connector_status_connected)
4231                 return 0;
4232
4233         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4234                                ctx);
4235         if (ret)
4236                 return ret;
4237
4238         conn_state = connector->base.state;
4239
4240         crtc = to_intel_crtc(conn_state->crtc);
4241         if (!crtc)
4242                 return 0;
4243
4244         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4245         if (ret)
4246                 return ret;
4247
4248         crtc_state = to_intel_crtc_state(crtc->base.state);
4249
4250         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4251
4252         if (!crtc_state->base.active)
4253                 return 0;
4254
4255         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4256             !crtc_state->hdmi_scrambling)
4257                 return 0;
4258
4259         if (conn_state->commit &&
4260             !try_wait_for_completion(&conn_state->commit->hw_done))
4261                 return 0;
4262
4263         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4264         if (ret < 0) {
4265                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4266                 return 0;
4267         }
4268
4269         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4270             crtc_state->hdmi_high_tmds_clock_ratio &&
4271             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4272             crtc_state->hdmi_scrambling)
4273                 return 0;
4274
4275         /*
4276          * HDMI 2.0 says that one should not send scrambled data
4277          * prior to configuring the sink scrambling, and that
4278          * TMDS clock/data transmission should be suspended when
4279          * changing the TMDS clock rate in the sink. So let's
4280          * just do a full modeset here, even though some sinks
4281          * would be perfectly happy if were to just reconfigure
4282          * the SCDC settings on the fly.
4283          */
4284         return modeset_pipe(&crtc->base, ctx);
4285 }
4286
4287 static enum intel_hotplug_state
4288 intel_ddi_hotplug(struct intel_encoder *encoder,
4289                   struct intel_connector *connector,
4290                   bool irq_received)
4291 {
4292         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4293         struct drm_modeset_acquire_ctx ctx;
4294         enum intel_hotplug_state state;
4295         int ret;
4296
4297         state = intel_encoder_hotplug(encoder, connector, irq_received);
4298
4299         drm_modeset_acquire_init(&ctx, 0);
4300
4301         for (;;) {
4302                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4303                         ret = intel_hdmi_reset_link(encoder, &ctx);
4304                 else
4305                         ret = intel_dp_retrain_link(encoder, &ctx);
4306
4307                 if (ret == -EDEADLK) {
4308                         drm_modeset_backoff(&ctx);
4309                         continue;
4310                 }
4311
4312                 break;
4313         }
4314
4315         drm_modeset_drop_locks(&ctx);
4316         drm_modeset_acquire_fini(&ctx);
4317         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4318
4319         /*
4320          * Unpowered type-c dongles can take some time to boot and be
4321          * responsible, so here giving some time to those dongles to power up
4322          * and then retrying the probe.
4323          *
4324          * On many platforms the HDMI live state signal is known to be
4325          * unreliable, so we can't use it to detect if a sink is connected or
4326          * not. Instead we detect if it's connected based on whether we can
4327          * read the EDID or not. That in turn has a problem during disconnect,
4328          * since the HPD interrupt may be raised before the DDC lines get
4329          * disconnected (due to how the required length of DDC vs. HPD
4330          * connector pins are specified) and so we'll still be able to get a
4331          * valid EDID. To solve this schedule another detection cycle if this
4332          * time around we didn't detect any change in the sink's connection
4333          * status.
4334          */
4335         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4336             !dig_port->dp.is_mst)
4337                 state = INTEL_HOTPLUG_RETRY;
4338
4339         return state;
4340 }
4341
4342 static struct intel_connector *
4343 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4344 {
4345         struct intel_connector *connector;
4346         enum port port = intel_dig_port->base.port;
4347
4348         connector = intel_connector_alloc();
4349         if (!connector)
4350                 return NULL;
4351
4352         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4353         intel_hdmi_init_connector(intel_dig_port, connector);
4354
4355         return connector;
4356 }
4357
4358 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4359 {
4360         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4361
4362         if (dport->base.port != PORT_A)
4363                 return false;
4364
4365         if (dport->saved_port_bits & DDI_A_4_LANES)
4366                 return false;
4367
4368         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4369          *                     supported configuration
4370          */
4371         if (IS_GEN9_LP(dev_priv))
4372                 return true;
4373
4374         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4375          *             one who does also have a full A/E split called
4376          *             DDI_F what makes DDI_E useless. However for this
4377          *             case let's trust VBT info.
4378          */
4379         if (IS_CANNONLAKE(dev_priv) &&
4380             !intel_bios_is_port_present(dev_priv, PORT_E))
4381                 return true;
4382
4383         return false;
4384 }
4385
4386 static int
4387 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4388 {
4389         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4390         enum port port = intel_dport->base.port;
4391         int max_lanes = 4;
4392
4393         if (INTEL_GEN(dev_priv) >= 11)
4394                 return max_lanes;
4395
4396         if (port == PORT_A || port == PORT_E) {
4397                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4398                         max_lanes = port == PORT_A ? 4 : 0;
4399                 else
4400                         /* Both A and E share 2 lanes */
4401                         max_lanes = 2;
4402         }
4403
4404         /*
4405          * Some BIOS might fail to set this bit on port A if eDP
4406          * wasn't lit up at boot.  Force this bit set when needed
4407          * so we use the proper lane count for our calculations.
4408          */
4409         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4410                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4411                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4412                 max_lanes = 4;
4413         }
4414
4415         return max_lanes;
4416 }
4417
4418 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4419 {
4420         struct ddi_vbt_port_info *port_info =
4421                 &dev_priv->vbt.ddi_port_info[port];
4422         struct intel_digital_port *intel_dig_port;
4423         struct intel_encoder *intel_encoder;
4424         struct drm_encoder *encoder;
4425         bool init_hdmi, init_dp, init_lspcon = false;
4426         enum pipe pipe;
4427         enum phy phy = intel_port_to_phy(dev_priv, port);
4428
4429         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4430         init_dp = port_info->supports_dp;
4431
4432         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4433                 /*
4434                  * Lspcon device needs to be driven with DP connector
4435                  * with special detection sequence. So make sure DP
4436                  * is initialized before lspcon.
4437                  */
4438                 init_dp = true;
4439                 init_lspcon = true;
4440                 init_hdmi = false;
4441                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4442         }
4443
4444         if (!init_dp && !init_hdmi) {
4445                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4446                               port_name(port));
4447                 return;
4448         }
4449
4450         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4451         if (!intel_dig_port)
4452                 return;
4453
4454         intel_encoder = &intel_dig_port->base;
4455         encoder = &intel_encoder->base;
4456
4457         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4458                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4459
4460         intel_encoder->hotplug = intel_ddi_hotplug;
4461         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4462         intel_encoder->compute_config = intel_ddi_compute_config;
4463         intel_encoder->enable = intel_enable_ddi;
4464         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4465         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4466         intel_encoder->pre_enable = intel_ddi_pre_enable;
4467         intel_encoder->disable = intel_disable_ddi;
4468         intel_encoder->post_disable = intel_ddi_post_disable;
4469         intel_encoder->update_pipe = intel_ddi_update_pipe;
4470         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4471         intel_encoder->get_config = intel_ddi_get_config;
4472         intel_encoder->suspend = intel_dp_encoder_suspend;
4473         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4474         intel_encoder->type = INTEL_OUTPUT_DDI;
4475         intel_encoder->power_domain = intel_port_to_power_domain(port);
4476         intel_encoder->port = port;
4477         intel_encoder->cloneable = 0;
4478         for_each_pipe(dev_priv, pipe)
4479                 intel_encoder->crtc_mask |= BIT(pipe);
4480
4481         if (INTEL_GEN(dev_priv) >= 11)
4482                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4483                         DDI_BUF_PORT_REVERSAL;
4484         else
4485                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4486                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4487         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4488         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4489         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4490
4491         if (intel_phy_is_tc(dev_priv, phy)) {
4492                 bool is_legacy = !port_info->supports_typec_usb &&
4493                                  !port_info->supports_tbt;
4494
4495                 intel_tc_port_init(intel_dig_port, is_legacy);
4496
4497                 intel_encoder->update_prepare = intel_ddi_update_prepare;
4498                 intel_encoder->update_complete = intel_ddi_update_complete;
4499         }
4500
4501         switch (port) {
4502         case PORT_A:
4503                 intel_dig_port->ddi_io_power_domain =
4504                         POWER_DOMAIN_PORT_DDI_A_IO;
4505                 break;
4506         case PORT_B:
4507                 intel_dig_port->ddi_io_power_domain =
4508                         POWER_DOMAIN_PORT_DDI_B_IO;
4509                 break;
4510         case PORT_C:
4511                 intel_dig_port->ddi_io_power_domain =
4512                         POWER_DOMAIN_PORT_DDI_C_IO;
4513                 break;
4514         case PORT_D:
4515                 intel_dig_port->ddi_io_power_domain =
4516                         POWER_DOMAIN_PORT_DDI_D_IO;
4517                 break;
4518         case PORT_E:
4519                 intel_dig_port->ddi_io_power_domain =
4520                         POWER_DOMAIN_PORT_DDI_E_IO;
4521                 break;
4522         case PORT_F:
4523                 intel_dig_port->ddi_io_power_domain =
4524                         POWER_DOMAIN_PORT_DDI_F_IO;
4525                 break;
4526         case PORT_G:
4527                 intel_dig_port->ddi_io_power_domain =
4528                         POWER_DOMAIN_PORT_DDI_G_IO;
4529                 break;
4530         case PORT_H:
4531                 intel_dig_port->ddi_io_power_domain =
4532                         POWER_DOMAIN_PORT_DDI_H_IO;
4533                 break;
4534         case PORT_I:
4535                 intel_dig_port->ddi_io_power_domain =
4536                         POWER_DOMAIN_PORT_DDI_I_IO;
4537                 break;
4538         default:
4539                 MISSING_CASE(port);
4540         }
4541
4542         if (init_dp) {
4543                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4544                         goto err;
4545
4546                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4547         }
4548
4549         /* In theory we don't need the encoder->type check, but leave it just in
4550          * case we have some really bad VBTs... */
4551         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4552                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4553                         goto err;
4554         }
4555
4556         if (init_lspcon) {
4557                 if (lspcon_init(intel_dig_port))
4558                         /* TODO: handle hdmi info frame part */
4559                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4560                                 port_name(port));
4561                 else
4562                         /*
4563                          * LSPCON init faied, but DP init was success, so
4564                          * lets try to drive as DP++ port.
4565                          */
4566                         DRM_ERROR("LSPCON init failed on port %c\n",
4567                                 port_name(port));
4568         }
4569
4570         intel_infoframe_init(intel_dig_port);
4571
4572         return;
4573
4574 err:
4575         drm_encoder_cleanup(encoder);
4576         kfree(intel_dig_port);
4577 }