drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_link_training.h"
  38 #include "intel_dpio_phy.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_tc.h"
  49 #include "intel_vdsc.h"
  50
  51 struct ddi_buf_trans {
  52         u32 trans1;     /* balance leg enable, de-emph level */
  53         u32 trans2;     /* vref sel, vswing */
  54         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  55 };
  56
  57 static const u8 index_to_dp_signal_levels[] = {
  58         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  59         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  60         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  61         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  62         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  63         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  64         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  65         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  66         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  67         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68 };
  69
  70 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  71  * them for both DP and FDI transports, allowing those ports to
  72  * automatically adapt to HDMI connections as well
  73  */
  74 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  75         { 0x00FFFFFF, 0x0006000E, 0x0 },
  76         { 0x00D75FFF, 0x0005000A, 0x0 },
  77         { 0x00C30FFF, 0x00040006, 0x0 },
  78         { 0x80AAAFFF, 0x000B0000, 0x0 },
  79         { 0x00FFFFFF, 0x0005000A, 0x0 },
  80         { 0x00D75FFF, 0x000C0004, 0x0 },
  81         { 0x80C30FFF, 0x000B0000, 0x0 },
  82         { 0x00FFFFFF, 0x00040006, 0x0 },
  83         { 0x80D75FFF, 0x000B0000, 0x0 },
  84 };
  85
  86 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  87         { 0x00FFFFFF, 0x0007000E, 0x0 },
  88         { 0x00D75FFF, 0x000F000A, 0x0 },
  89         { 0x00C30FFF, 0x00060006, 0x0 },
  90         { 0x00AAAFFF, 0x001E0000, 0x0 },
  91         { 0x00FFFFFF, 0x000F000A, 0x0 },
  92         { 0x00D75FFF, 0x00160004, 0x0 },
  93         { 0x00C30FFF, 0x001E0000, 0x0 },
  94         { 0x00FFFFFF, 0x00060006, 0x0 },
  95         { 0x00D75FFF, 0x001E0000, 0x0 },
  96 };
  97
  98 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  99                                         /* Idx  NT mV d T mV d  db      */
 100         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 101         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 102         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 103         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 104         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 105         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 106         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 107         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 108         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 109         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 110         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 111         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 112 };
 113
 114 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 115         { 0x00FFFFFF, 0x00000012, 0x0 },
 116         { 0x00EBAFFF, 0x00020011, 0x0 },
 117         { 0x00C71FFF, 0x0006000F, 0x0 },
 118         { 0x00AAAFFF, 0x000E000A, 0x0 },
 119         { 0x00FFFFFF, 0x00020011, 0x0 },
 120         { 0x00DB6FFF, 0x0005000F, 0x0 },
 121         { 0x00BEEFFF, 0x000A000C, 0x0 },
 122         { 0x00FFFFFF, 0x0005000F, 0x0 },
 123         { 0x00DB6FFF, 0x000A000C, 0x0 },
 124 };
 125
 126 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 127         { 0x00FFFFFF, 0x0007000E, 0x0 },
 128         { 0x00D75FFF, 0x000E000A, 0x0 },
 129         { 0x00BEFFFF, 0x00140006, 0x0 },
 130         { 0x80B2CFFF, 0x001B0002, 0x0 },
 131         { 0x00FFFFFF, 0x000E000A, 0x0 },
 132         { 0x00DB6FFF, 0x00160005, 0x0 },
 133         { 0x80C71FFF, 0x001A0002, 0x0 },
 134         { 0x00F7DFFF, 0x00180004, 0x0 },
 135         { 0x80D75FFF, 0x001B0002, 0x0 },
 136 };
 137
 138 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 139         { 0x00FFFFFF, 0x0001000E, 0x0 },
 140         { 0x00D75FFF, 0x0004000A, 0x0 },
 141         { 0x00C30FFF, 0x00070006, 0x0 },
 142         { 0x00AAAFFF, 0x000C0000, 0x0 },
 143         { 0x00FFFFFF, 0x0004000A, 0x0 },
 144         { 0x00D75FFF, 0x00090004, 0x0 },
 145         { 0x00C30FFF, 0x000C0000, 0x0 },
 146         { 0x00FFFFFF, 0x00070006, 0x0 },
 147         { 0x00D75FFF, 0x000C0000, 0x0 },
 148 };
 149
 150 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 151                                         /* Idx  NT mV d T mV df db      */
 152         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 153         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 154         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 155         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 156         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 157         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 158         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 159         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 160         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 161         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 162 };
 163
 164 /* Skylake H and S */
 165 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 166         { 0x00002016, 0x000000A0, 0x0 },
 167         { 0x00005012, 0x0000009B, 0x0 },
 168         { 0x00007011, 0x00000088, 0x0 },
 169         { 0x80009010, 0x000000C0, 0x1 },
 170         { 0x00002016, 0x0000009B, 0x0 },
 171         { 0x00005012, 0x00000088, 0x0 },
 172         { 0x80007011, 0x000000C0, 0x1 },
 173         { 0x00002016, 0x000000DF, 0x0 },
 174         { 0x80005012, 0x000000C0, 0x1 },
 175 };
 176
 177 /* Skylake U */
 178 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 179         { 0x0000201B, 0x000000A2, 0x0 },
 180         { 0x00005012, 0x00000088, 0x0 },
 181         { 0x80007011, 0x000000CD, 0x1 },
 182         { 0x80009010, 0x000000C0, 0x1 },
 183         { 0x0000201B, 0x0000009D, 0x0 },
 184         { 0x80005012, 0x000000C0, 0x1 },
 185         { 0x80007011, 0x000000C0, 0x1 },
 186         { 0x00002016, 0x00000088, 0x0 },
 187         { 0x80005012, 0x000000C0, 0x1 },
 188 };
 189
 190 /* Skylake Y */
 191 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 192         { 0x00000018, 0x000000A2, 0x0 },
 193         { 0x00005012, 0x00000088, 0x0 },
 194         { 0x80007011, 0x000000CD, 0x3 },
 195         { 0x80009010, 0x000000C0, 0x3 },
 196         { 0x00000018, 0x0000009D, 0x0 },
 197         { 0x80005012, 0x000000C0, 0x3 },
 198         { 0x80007011, 0x000000C0, 0x3 },
 199         { 0x00000018, 0x00000088, 0x0 },
 200         { 0x80005012, 0x000000C0, 0x3 },
 201 };
 202
 203 /* Kabylake H and S */
 204 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 205         { 0x00002016, 0x000000A0, 0x0 },
 206         { 0x00005012, 0x0000009B, 0x0 },
 207         { 0x00007011, 0x00000088, 0x0 },
 208         { 0x80009010, 0x000000C0, 0x1 },
 209         { 0x00002016, 0x0000009B, 0x0 },
 210         { 0x00005012, 0x00000088, 0x0 },
 211         { 0x80007011, 0x000000C0, 0x1 },
 212         { 0x00002016, 0x00000097, 0x0 },
 213         { 0x80005012, 0x000000C0, 0x1 },
 214 };
 215
 216 /* Kabylake U */
 217 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 218         { 0x0000201B, 0x000000A1, 0x0 },
 219         { 0x00005012, 0x00000088, 0x0 },
 220         { 0x80007011, 0x000000CD, 0x3 },
 221         { 0x80009010, 0x000000C0, 0x3 },
 222         { 0x0000201B, 0x0000009D, 0x0 },
 223         { 0x80005012, 0x000000C0, 0x3 },
 224         { 0x80007011, 0x000000C0, 0x3 },
 225         { 0x00002016, 0x0000004F, 0x0 },
 226         { 0x80005012, 0x000000C0, 0x3 },
 227 };
 228
 229 /* Kabylake Y */
 230 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 231         { 0x00001017, 0x000000A1, 0x0 },
 232         { 0x00005012, 0x00000088, 0x0 },
 233         { 0x80007011, 0x000000CD, 0x3 },
 234         { 0x8000800F, 0x000000C0, 0x3 },
 235         { 0x00001017, 0x0000009D, 0x0 },
 236         { 0x80005012, 0x000000C0, 0x3 },
 237         { 0x80007011, 0x000000C0, 0x3 },
 238         { 0x00001017, 0x0000004C, 0x0 },
 239         { 0x80005012, 0x000000C0, 0x3 },
 240 };
 241
 242 /*
 243  * Skylake/Kabylake H and S
 244  * eDP 1.4 low vswing translation parameters
 245  */
 246 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 247         { 0x00000018, 0x000000A8, 0x0 },
 248         { 0x00004013, 0x000000A9, 0x0 },
 249         { 0x00007011, 0x000000A2, 0x0 },
 250         { 0x00009010, 0x0000009C, 0x0 },
 251         { 0x00000018, 0x000000A9, 0x0 },
 252         { 0x00006013, 0x000000A2, 0x0 },
 253         { 0x00007011, 0x000000A6, 0x0 },
 254         { 0x00000018, 0x000000AB, 0x0 },
 255         { 0x00007013, 0x0000009F, 0x0 },
 256         { 0x00000018, 0x000000DF, 0x0 },
 257 };
 258
 259 /*
 260  * Skylake/Kabylake U
 261  * eDP 1.4 low vswing translation parameters
 262  */
 263 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 264         { 0x00000018, 0x000000A8, 0x0 },
 265         { 0x00004013, 0x000000A9, 0x0 },
 266         { 0x00007011, 0x000000A2, 0x0 },
 267         { 0x00009010, 0x0000009C, 0x0 },
 268         { 0x00000018, 0x000000A9, 0x0 },
 269         { 0x00006013, 0x000000A2, 0x0 },
 270         { 0x00007011, 0x000000A6, 0x0 },
 271         { 0x00002016, 0x000000AB, 0x0 },
 272         { 0x00005013, 0x0000009F, 0x0 },
 273         { 0x00000018, 0x000000DF, 0x0 },
 274 };
 275
 276 /*
 277  * Skylake/Kabylake Y
 278  * eDP 1.4 low vswing translation parameters
 279  */
 280 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 281         { 0x00000018, 0x000000A8, 0x0 },
 282         { 0x00004013, 0x000000AB, 0x0 },
 283         { 0x00007011, 0x000000A4, 0x0 },
 284         { 0x00009010, 0x000000DF, 0x0 },
 285         { 0x00000018, 0x000000AA, 0x0 },
 286         { 0x00006013, 0x000000A4, 0x0 },
 287         { 0x00007011, 0x0000009D, 0x0 },
 288         { 0x00000018, 0x000000A0, 0x0 },
 289         { 0x00006012, 0x000000DF, 0x0 },
 290         { 0x00000018, 0x0000008A, 0x0 },
 291 };
 292
 293 /* Skylake/Kabylake U, H and S */
 294 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 295         { 0x00000018, 0x000000AC, 0x0 },
 296         { 0x00005012, 0x0000009D, 0x0 },
 297         { 0x00007011, 0x00000088, 0x0 },
 298         { 0x00000018, 0x000000A1, 0x0 },
 299         { 0x00000018, 0x00000098, 0x0 },
 300         { 0x00004013, 0x00000088, 0x0 },
 301         { 0x80006012, 0x000000CD, 0x1 },
 302         { 0x00000018, 0x000000DF, 0x0 },
 303         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 304         { 0x80003015, 0x000000C0, 0x1 },
 305         { 0x80000018, 0x000000C0, 0x1 },
 306 };
 307
 308 /* Skylake/Kabylake Y */
 309 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 310         { 0x00000018, 0x000000A1, 0x0 },
 311         { 0x00005012, 0x000000DF, 0x0 },
 312         { 0x80007011, 0x000000CB, 0x3 },
 313         { 0x00000018, 0x000000A4, 0x0 },
 314         { 0x00000018, 0x0000009D, 0x0 },
 315         { 0x00004013, 0x00000080, 0x0 },
 316         { 0x80006013, 0x000000C0, 0x3 },
 317         { 0x00000018, 0x0000008A, 0x0 },
 318         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 319         { 0x80003015, 0x000000C0, 0x3 },
 320         { 0x80000018, 0x000000C0, 0x3 },
 321 };
 322
 323 struct bxt_ddi_buf_trans {
 324         u8 margin;      /* swing value */
 325         u8 scale;       /* scale value */
 326         u8 enable;      /* scale enable */
 327         u8 deemphasis;
 328 };
 329
 330 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 331                                         /* Idx  NT mV diff      db  */
 332         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 333         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 334         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 335         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 336         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 337         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 338         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 339         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 340         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 341         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 342 };
 343
 344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 345                                         /* Idx  NT mV diff      db  */
 346         { 26, 0, 0, 128, },     /* 0:   200             0   */
 347         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 348         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 349         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 350         { 32, 0, 0, 128, },     /* 4:   250             0   */
 351         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 352         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 353         { 43, 0, 0, 128, },     /* 7:   300             0   */
 354         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 355         { 48, 0, 0, 128, },     /* 9:   300             0   */
 356 };
 357
 358 /* BSpec has 2 recommended values - entries 0 and 8.
 359  * Using the entry with higher vswing.
 360  */
 361 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 362                                         /* Idx  NT mV diff      db  */
 363         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 364         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 365         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 366         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 367         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 368         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 369         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 370         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 371         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 372         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 373 };
 374
 375 struct cnl_ddi_buf_trans {
 376         u8 dw2_swing_sel;
 377         u8 dw7_n_scalar;
 378         u8 dw4_cursor_coeff;
 379         u8 dw4_post_cursor_2;
 380         u8 dw4_post_cursor_1;
 381 };
 382
 383 /* Voltage Swing Programming for VccIO 0.85V for DP */
 384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 385                                                 /* NT mV Trans mV db    */
 386         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 387         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 388         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 389         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 390         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 391         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 392         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 393         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 394         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 395         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 396 };
 397
 398 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 400                                                 /* NT mV Trans mV db    */
 401         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 402         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 403         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 404         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 405         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 406         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 407         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 408 };
 409
 410 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 411 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 412                                                 /* NT mV Trans mV db    */
 413         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 414         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 415         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 416         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 417         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 418         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 419         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 420         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 421         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 422 };
 423
 424 /* Voltage Swing Programming for VccIO 0.95V for DP */
 425 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 426                                                 /* NT mV Trans mV db    */
 427         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 428         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 429         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 430         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 431         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 432         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 433         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 434         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 435         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 436         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 437 };
 438
 439 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 440 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 441                                                 /* NT mV Trans mV db    */
 442         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 443         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 444         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 445         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 446         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 447         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 448         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 449         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 450         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 451         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 452         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 453 };
 454
 455 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 456 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 457                                                 /* NT mV Trans mV db    */
 458         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 459         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 460         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 461         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 462         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 463         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 464         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 465         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 466         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 467         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 468 };
 469
 470 /* Voltage Swing Programming for VccIO 1.05V for DP */
 471 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 472                                                 /* NT mV Trans mV db    */
 473         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 474         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 475         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 476         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 477         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 478         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 479         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 480         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 481         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 482         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 483 };
 484
 485 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 486 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 487                                                 /* NT mV Trans mV db    */
 488         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 489         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 490         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 491         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 492         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 493         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 494         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 495         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 496         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 497         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 498         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 499 };
 500
 501 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 502 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 503                                                 /* NT mV Trans mV db    */
 504         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 505         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 506         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 507         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 508         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 509         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 510         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 511         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 512         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 513 };
 514
 515 /* icl_combo_phy_ddi_translations */
 516 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 517                                                 /* NT mV Trans mV db    */
 518         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 519         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 520         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 521         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 522         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 523         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 524         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 525         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 526         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 527         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 528 };
 529
 530 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 531                                                 /* NT mV Trans mV db    */
 532         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 533         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 534         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 535         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 536         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 537         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 538         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 539         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 540         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 541         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 542 };
 543
 544 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 545                                                 /* NT mV Trans mV db    */
 546         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 547         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 548         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 549         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 550         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 551         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 552         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 553         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 554         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 555         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 556 };
 557
 558 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 559                                                 /* NT mV Trans mV db    */
 560         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 561         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 562         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 563         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 564         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 565         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 566         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 567 };
 568
 569 struct icl_mg_phy_ddi_buf_trans {
 570         u32 cri_txdeemph_override_5_0;
 571         u32 cri_txdeemph_override_11_6;
 572         u32 cri_txdeemph_override_17_12;
 573 };
 574
 575 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 576                                 /* Voltage swing  pre-emphasis */
 577         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 578         { 0x0, 0x23, 0x08 },    /* 0              1   */
 579         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 580         { 0x0, 0x00, 0x00 },    /* 0              3   */
 581         { 0x0, 0x23, 0x00 },    /* 1              0   */
 582         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 583         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 584         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 585         { 0x0, 0x33, 0x0C },    /* 2              1   */
 586         { 0x0, 0x00, 0x00 },    /* 3              0   */
 587 };
 588
 589 static const struct ddi_buf_trans *
 590 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 591 {
 592         if (dev_priv->vbt.edp.low_vswing) {
 593                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 594                 return bdw_ddi_translations_edp;
 595         } else {
 596                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 597                 return bdw_ddi_translations_dp;
 598         }
 599 }
 600
 601 static const struct ddi_buf_trans *
 602 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 603 {
 604         if (IS_SKL_ULX(dev_priv)) {
 605                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 606                 return skl_y_ddi_translations_dp;
 607         } else if (IS_SKL_ULT(dev_priv)) {
 608                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 609                 return skl_u_ddi_translations_dp;
 610         } else {
 611                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 612                 return skl_ddi_translations_dp;
 613         }
 614 }
 615
 616 static const struct ddi_buf_trans *
 617 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 618 {
 619         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 620                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 621                 return kbl_y_ddi_translations_dp;
 622         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 623                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 624                 return kbl_u_ddi_translations_dp;
 625         } else {
 626                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 627                 return kbl_ddi_translations_dp;
 628         }
 629 }
 630
 631 static const struct ddi_buf_trans *
 632 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 633 {
 634         if (dev_priv->vbt.edp.low_vswing) {
 635                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 636                     IS_CFL_ULX(dev_priv)) {
 637                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 638                         return skl_y_ddi_translations_edp;
 639                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 640                            IS_CFL_ULT(dev_priv)) {
 641                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 642                         return skl_u_ddi_translations_edp;
 643                 } else {
 644                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 645                         return skl_ddi_translations_edp;
 646                 }
 647         }
 648
 649         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 650                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 651         else
 652                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 653 }
 654
 655 static const struct ddi_buf_trans *
 656 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 657 {
 658         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 659             IS_CFL_ULX(dev_priv)) {
 660                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 661                 return skl_y_ddi_translations_hdmi;
 662         } else {
 663                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 664                 return skl_ddi_translations_hdmi;
 665         }
 666 }
 667
 668 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 669 {
 670         /* Only DDIA and DDIE can select the 10th register with DP */
 671         if (port == PORT_A || port == PORT_E)
 672                 return min(n_entries, 10);
 673         else
 674                 return min(n_entries, 9);
 675 }
 676
 677 static const struct ddi_buf_trans *
 678 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 679                            enum port port, int *n_entries)
 680 {
 681         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 682                 const struct ddi_buf_trans *ddi_translations =
 683                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 684                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 685                 return ddi_translations;
 686         } else if (IS_SKYLAKE(dev_priv)) {
 687                 const struct ddi_buf_trans *ddi_translations =
 688                         skl_get_buf_trans_dp(dev_priv, n_entries);
 689                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 690                 return ddi_translations;
 691         } else if (IS_BROADWELL(dev_priv)) {
 692                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 693                 return  bdw_ddi_translations_dp;
 694         } else if (IS_HASWELL(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 696                 return hsw_ddi_translations_dp;
 697         }
 698
 699         *n_entries = 0;
 700         return NULL;
 701 }
 702
 703 static const struct ddi_buf_trans *
 704 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 705                             enum port port, int *n_entries)
 706 {
 707         if (IS_GEN9_BC(dev_priv)) {
 708                 const struct ddi_buf_trans *ddi_translations =
 709                         skl_get_buf_trans_edp(dev_priv, n_entries);
 710                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 711                 return ddi_translations;
 712         } else if (IS_BROADWELL(dev_priv)) {
 713                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 714         } else if (IS_HASWELL(dev_priv)) {
 715                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 716                 return hsw_ddi_translations_dp;
 717         }
 718
 719         *n_entries = 0;
 720         return NULL;
 721 }
 722
 723 static const struct ddi_buf_trans *
 724 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 725                             int *n_entries)
 726 {
 727         if (IS_BROADWELL(dev_priv)) {
 728                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 729                 return bdw_ddi_translations_fdi;
 730         } else if (IS_HASWELL(dev_priv)) {
 731                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 732                 return hsw_ddi_translations_fdi;
 733         }
 734
 735         *n_entries = 0;
 736         return NULL;
 737 }
 738
 739 static const struct ddi_buf_trans *
 740 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 741                              int *n_entries)
 742 {
 743         if (IS_GEN9_BC(dev_priv)) {
 744                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 745         } else if (IS_BROADWELL(dev_priv)) {
 746                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 747                 return bdw_ddi_translations_hdmi;
 748         } else if (IS_HASWELL(dev_priv)) {
 749                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 750                 return hsw_ddi_translations_hdmi;
 751         }
 752
 753         *n_entries = 0;
 754         return NULL;
 755 }
 756
 757 static const struct bxt_ddi_buf_trans *
 758 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 759 {
 760         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 761         return bxt_ddi_translations_dp;
 762 }
 763
 764 static const struct bxt_ddi_buf_trans *
 765 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 766 {
 767         if (dev_priv->vbt.edp.low_vswing) {
 768                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 769                 return bxt_ddi_translations_edp;
 770         }
 771
 772         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 773 }
 774
 775 static const struct bxt_ddi_buf_trans *
 776 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 777 {
 778         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 779         return bxt_ddi_translations_hdmi;
 780 }
 781
 782 static const struct cnl_ddi_buf_trans *
 783 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 784 {
 785         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 786
 787         if (voltage == VOLTAGE_INFO_0_85V) {
 788                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 789                 return cnl_ddi_translations_hdmi_0_85V;
 790         } else if (voltage == VOLTAGE_INFO_0_95V) {
 791                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 792                 return cnl_ddi_translations_hdmi_0_95V;
 793         } else if (voltage == VOLTAGE_INFO_1_05V) {
 794                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 795                 return cnl_ddi_translations_hdmi_1_05V;
 796         } else {
 797                 *n_entries = 1; /* shut up gcc */
 798                 MISSING_CASE(voltage);
 799         }
 800         return NULL;
 801 }
 802
 803 static const struct cnl_ddi_buf_trans *
 804 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 805 {
 806         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 807
 808         if (voltage == VOLTAGE_INFO_0_85V) {
 809                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 810                 return cnl_ddi_translations_dp_0_85V;
 811         } else if (voltage == VOLTAGE_INFO_0_95V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 813                 return cnl_ddi_translations_dp_0_95V;
 814         } else if (voltage == VOLTAGE_INFO_1_05V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 816                 return cnl_ddi_translations_dp_1_05V;
 817         } else {
 818                 *n_entries = 1; /* shut up gcc */
 819                 MISSING_CASE(voltage);
 820         }
 821         return NULL;
 822 }
 823
 824 static const struct cnl_ddi_buf_trans *
 825 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 826 {
 827         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 828
 829         if (dev_priv->vbt.edp.low_vswing) {
 830                 if (voltage == VOLTAGE_INFO_0_85V) {
 831                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 832                         return cnl_ddi_translations_edp_0_85V;
 833                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 834                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 835                         return cnl_ddi_translations_edp_0_95V;
 836                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 837                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 838                         return cnl_ddi_translations_edp_1_05V;
 839                 } else {
 840                         *n_entries = 1; /* shut up gcc */
 841                         MISSING_CASE(voltage);
 842                 }
 843                 return NULL;
 844         } else {
 845                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 846         }
 847 }
 848
 849 static const struct cnl_ddi_buf_trans *
 850 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 851                         int *n_entries)
 852 {
 853         if (type == INTEL_OUTPUT_HDMI) {
 854                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 855                 return icl_combo_phy_ddi_translations_hdmi;
 856         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 857                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 858                 return icl_combo_phy_ddi_translations_edp_hbr3;
 859         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 860                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 861                 return icl_combo_phy_ddi_translations_edp_hbr2;
 862         }
 863
 864         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 865         return icl_combo_phy_ddi_translations_dp_hbr2;
 866 }
 867
 868 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 869 {
 870         int n_entries, level, default_entry;
 871         enum phy phy = intel_port_to_phy(dev_priv, port);
 872
 873         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 874
 875         if (INTEL_GEN(dev_priv) >= 11) {
 876                 if (intel_phy_is_combo(dev_priv, phy))
 877                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 878                                                 0, &n_entries);
 879                 else
 880                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 881                 default_entry = n_entries - 1;
 882         } else if (IS_CANNONLAKE(dev_priv)) {
 883                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 884                 default_entry = n_entries - 1;
 885         } else if (IS_GEN9_LP(dev_priv)) {
 886                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 887                 default_entry = n_entries - 1;
 888         } else if (IS_GEN9_BC(dev_priv)) {
 889                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 890                 default_entry = 8;
 891         } else if (IS_BROADWELL(dev_priv)) {
 892                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 893                 default_entry = 7;
 894         } else if (IS_HASWELL(dev_priv)) {
 895                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 896                 default_entry = 6;
 897         } else {
 898                 WARN(1, "ddi translation table missing\n");
 899                 return 0;
 900         }
 901
 902         /* Choose a good default if VBT is badly populated */
 903         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 904                 level = default_entry;
 905
 906         if (WARN_ON_ONCE(n_entries == 0))
 907                 return 0;
 908         if (WARN_ON_ONCE(level >= n_entries))
 909                 level = n_entries - 1;
 910
 911         return level;
 912 }
 913
 914 /*
 915  * Starting with Haswell, DDI port buffers must be programmed with correct
 916  * values in advance. This function programs the correct values for
 917  * DP/eDP/FDI use cases.
 918  */
 919 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 920                                          const struct intel_crtc_state *crtc_state)
 921 {
 922         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 923         u32 iboost_bit = 0;
 924         int i, n_entries;
 925         enum port port = encoder->port;
 926         const struct ddi_buf_trans *ddi_translations;
 927
 928         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 929                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 930                                                                &n_entries);
 931         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 932                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 933                                                                &n_entries);
 934         else
 935                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 936                                                               &n_entries);
 937
 938         /* If we're boosting the current, set bit 31 of trans1 */
 939         if (IS_GEN9_BC(dev_priv) &&
 940             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 941                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 942
 943         for (i = 0; i < n_entries; i++) {
 944                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 945                            ddi_translations[i].trans1 | iboost_bit);
 946                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 947                            ddi_translations[i].trans2);
 948         }
 949 }
 950
 951 /*
 952  * Starting with Haswell, DDI port buffers must be programmed with correct
 953  * values in advance. This function programs the correct values for
 954  * HDMI/DVI use cases.
 955  */
 956 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 957                                            int level)
 958 {
 959         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 960         u32 iboost_bit = 0;
 961         int n_entries;
 962         enum port port = encoder->port;
 963         const struct ddi_buf_trans *ddi_translations;
 964
 965         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 966
 967         if (WARN_ON_ONCE(!ddi_translations))
 968                 return;
 969         if (WARN_ON_ONCE(level >= n_entries))
 970                 level = n_entries - 1;
 971
 972         /* If we're boosting the current, set bit 31 of trans1 */
 973         if (IS_GEN9_BC(dev_priv) &&
 974             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 975                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 976
 977         /* Entry 9 is for HDMI: */
 978         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 979                    ddi_translations[level].trans1 | iboost_bit);
 980         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 981                    ddi_translations[level].trans2);
 982 }
 983
 984 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 985                                     enum port port)
 986 {
 987         i915_reg_t reg = DDI_BUF_CTL(port);
 988         int i;
 989
 990         for (i = 0; i < 16; i++) {
 991                 udelay(1);
 992                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 993                         return;
 994         }
 995         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 996 }
 997
 998 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 999 {
1000         switch (pll->info->id) {
1001         case DPLL_ID_WRPLL1:
1002                 return PORT_CLK_SEL_WRPLL1;
1003         case DPLL_ID_WRPLL2:
1004                 return PORT_CLK_SEL_WRPLL2;
1005         case DPLL_ID_SPLL:
1006                 return PORT_CLK_SEL_SPLL;
1007         case DPLL_ID_LCPLL_810:
1008                 return PORT_CLK_SEL_LCPLL_810;
1009         case DPLL_ID_LCPLL_1350:
1010                 return PORT_CLK_SEL_LCPLL_1350;
1011         case DPLL_ID_LCPLL_2700:
1012                 return PORT_CLK_SEL_LCPLL_2700;
1013         default:
1014                 MISSING_CASE(pll->info->id);
1015                 return PORT_CLK_SEL_NONE;
1016         }
1017 }
1018
1019 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1020                                   const struct intel_crtc_state *crtc_state)
1021 {
1022         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1023         int clock = crtc_state->port_clock;
1024         const enum intel_dpll_id id = pll->info->id;
1025
1026         switch (id) {
1027         default:
1028                 /*
1029                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1030                  * here, so do warn if this get passed in
1031                  */
1032                 MISSING_CASE(id);
1033                 return DDI_CLK_SEL_NONE;
1034         case DPLL_ID_ICL_TBTPLL:
1035                 switch (clock) {
1036                 case 162000:
1037                         return DDI_CLK_SEL_TBT_162;
1038                 case 270000:
1039                         return DDI_CLK_SEL_TBT_270;
1040                 case 540000:
1041                         return DDI_CLK_SEL_TBT_540;
1042                 case 810000:
1043                         return DDI_CLK_SEL_TBT_810;
1044                 default:
1045                         MISSING_CASE(clock);
1046                         return DDI_CLK_SEL_NONE;
1047                 }
1048         case DPLL_ID_ICL_MGPLL1:
1049         case DPLL_ID_ICL_MGPLL2:
1050         case DPLL_ID_ICL_MGPLL3:
1051         case DPLL_ID_ICL_MGPLL4:
1052         case DPLL_ID_TGL_MGPLL5:
1053         case DPLL_ID_TGL_MGPLL6:
1054                 return DDI_CLK_SEL_MG;
1055         }
1056 }
1057
1058 /* Starting with Haswell, different DDI ports can work in FDI mode for
1059  * connection to the PCH-located connectors. For this, it is necessary to train
1060  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1061  *
1062  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1063  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1064  * DDI A (which is used for eDP)
1065  */
1066
1067 void hsw_fdi_link_train(struct intel_crtc *crtc,
1068                         const struct intel_crtc_state *crtc_state)
1069 {
1070         struct drm_device *dev = crtc->base.dev;
1071         struct drm_i915_private *dev_priv = to_i915(dev);
1072         struct intel_encoder *encoder;
1073         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1074
1075         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1076                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1077                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1078         }
1079
1080         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1081          * mode set "sequence for CRT port" document:
1082          * - TP1 to TP2 time with the default value
1083          * - FDI delay to 90h
1084          *
1085          * WaFDIAutoLinkSetTimingOverrride:hsw
1086          */
1087         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1088                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1089                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1090
1091         /* Enable the PCH Receiver FDI PLL */
1092         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1093                      FDI_RX_PLL_ENABLE |
1094                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1095         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1096         POSTING_READ(FDI_RX_CTL(PIPE_A));
1097         udelay(220);
1098
1099         /* Switch from Rawclk to PCDclk */
1100         rx_ctl_val |= FDI_PCDCLK;
1101         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1102
1103         /* Configure Port Clock Select */
1104         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1105         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1106         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1107
1108         /* Start the training iterating through available voltages and emphasis,
1109          * testing each value twice. */
1110         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1111                 /* Configure DP_TP_CTL with auto-training */
1112                 I915_WRITE(DP_TP_CTL(PORT_E),
1113                                         DP_TP_CTL_FDI_AUTOTRAIN |
1114                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1115                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1116                                         DP_TP_CTL_ENABLE);
1117
1118                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1119                  * DDI E does not support port reversal, the functionality is
1120                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1121                  * port reversal bit */
1122                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1123                            DDI_BUF_CTL_ENABLE |
1124                            ((crtc_state->fdi_lanes - 1) << 1) |
1125                            DDI_BUF_TRANS_SELECT(i / 2));
1126                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1127
1128                 udelay(600);
1129
1130                 /* Program PCH FDI Receiver TU */
1131                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1132
1133                 /* Enable PCH FDI Receiver with auto-training */
1134                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1135                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1137
1138                 /* Wait for FDI receiver lane calibration */
1139                 udelay(30);
1140
1141                 /* Unset FDI_RX_MISC pwrdn lanes */
1142                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1143                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1144                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1145                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1146
1147                 /* Wait for FDI auto training time */
1148                 udelay(5);
1149
1150                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1151                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1152                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1153                         break;
1154                 }
1155
1156                 /*
1157                  * Leave things enabled even if we failed to train FDI.
1158                  * Results in less fireworks from the state checker.
1159                  */
1160                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1161                         DRM_ERROR("FDI link training failed!\n");
1162                         break;
1163                 }
1164
1165                 rx_ctl_val &= ~FDI_RX_ENABLE;
1166                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1167                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1168
1169                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1170                 temp &= ~DDI_BUF_CTL_ENABLE;
1171                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1172                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1173
1174                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1175                 temp = I915_READ(DP_TP_CTL(PORT_E));
1176                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1177                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1178                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1179                 POSTING_READ(DP_TP_CTL(PORT_E));
1180
1181                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1182
1183                 /* Reset FDI_RX_MISC pwrdn lanes */
1184                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1185                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1186                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1187                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1188                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1189         }
1190
1191         /* Enable normal pixel sending for FDI */
1192         I915_WRITE(DP_TP_CTL(PORT_E),
1193                    DP_TP_CTL_FDI_AUTOTRAIN |
1194                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1195                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1196                    DP_TP_CTL_ENABLE);
1197 }
1198
1199 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1200 {
1201         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1202         struct intel_digital_port *intel_dig_port =
1203                 enc_to_dig_port(&encoder->base);
1204
1205         intel_dp->DP = intel_dig_port->saved_port_bits |
1206                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1207         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1208 }
1209
1210 static struct intel_encoder *
1211 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1212 {
1213         struct drm_device *dev = crtc->base.dev;
1214         struct intel_encoder *encoder, *ret = NULL;
1215         int num_encoders = 0;
1216
1217         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1218                 ret = encoder;
1219                 num_encoders++;
1220         }
1221
1222         if (num_encoders != 1)
1223                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1224                      pipe_name(crtc->pipe));
1225
1226         BUG_ON(ret == NULL);
1227         return ret;
1228 }
1229
1230 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1231                                    i915_reg_t reg)
1232 {
1233         int refclk;
1234         int n, p, r;
1235         u32 wrpll;
1236
1237         wrpll = I915_READ(reg);
1238         switch (wrpll & WRPLL_REF_MASK) {
1239         case WRPLL_REF_SPECIAL_HSW:
1240                 /*
1241                  * muxed-SSC for BDW.
1242                  * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1243                  * for the non-SSC reference frequency.
1244                  */
1245                 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1246                         if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1247                                 refclk = 24;
1248                         else
1249                                 refclk = 135;
1250                         break;
1251                 }
1252                 /* fall through */
1253         case WRPLL_REF_PCH_SSC:
1254                 /*
1255                  * We could calculate spread here, but our checking
1256                  * code only cares about 5% accuracy, and spread is a max of
1257                  * 0.5% downspread.
1258                  */
1259                 refclk = 135;
1260                 break;
1261         case WRPLL_REF_LCPLL:
1262                 refclk = 2700;
1263                 break;
1264         default:
1265                 MISSING_CASE(wrpll);
1266                 return 0;
1267         }
1268
1269         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1270         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1271         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1272
1273         /* Convert to KHz, p & r have a fixed point portion */
1274         return (refclk * n * 100) / (p * r);
1275 }
1276
1277 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1278 {
1279         u32 p0, p1, p2, dco_freq;
1280
1281         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1282         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1283
1284         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1285                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1286         else
1287                 p1 = 1;
1288
1289
1290         switch (p0) {
1291         case DPLL_CFGCR2_PDIV_1:
1292                 p0 = 1;
1293                 break;
1294         case DPLL_CFGCR2_PDIV_2:
1295                 p0 = 2;
1296                 break;
1297         case DPLL_CFGCR2_PDIV_3:
1298                 p0 = 3;
1299                 break;
1300         case DPLL_CFGCR2_PDIV_7:
1301                 p0 = 7;
1302                 break;
1303         }
1304
1305         switch (p2) {
1306         case DPLL_CFGCR2_KDIV_5:
1307                 p2 = 5;
1308                 break;
1309         case DPLL_CFGCR2_KDIV_2:
1310                 p2 = 2;
1311                 break;
1312         case DPLL_CFGCR2_KDIV_3:
1313                 p2 = 3;
1314                 break;
1315         case DPLL_CFGCR2_KDIV_1:
1316                 p2 = 1;
1317                 break;
1318         }
1319
1320         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1321                 * 24 * 1000;
1322
1323         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1324                      * 24 * 1000) / 0x8000;
1325
1326         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1327                 return 0;
1328
1329         return dco_freq / (p0 * p1 * p2 * 5);
1330 }
1331
1332 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1333                         struct intel_dpll_hw_state *pll_state)
1334 {
1335         u32 p0, p1, p2, dco_freq, ref_clock;
1336
1337         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1338         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1339
1340         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1341                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1342                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1343         else
1344                 p1 = 1;
1345
1346
1347         switch (p0) {
1348         case DPLL_CFGCR1_PDIV_2:
1349                 p0 = 2;
1350                 break;
1351         case DPLL_CFGCR1_PDIV_3:
1352                 p0 = 3;
1353                 break;
1354         case DPLL_CFGCR1_PDIV_5:
1355                 p0 = 5;
1356                 break;
1357         case DPLL_CFGCR1_PDIV_7:
1358                 p0 = 7;
1359                 break;
1360         }
1361
1362         switch (p2) {
1363         case DPLL_CFGCR1_KDIV_1:
1364                 p2 = 1;
1365                 break;
1366         case DPLL_CFGCR1_KDIV_2:
1367                 p2 = 2;
1368                 break;
1369         case DPLL_CFGCR1_KDIV_3:
1370                 p2 = 3;
1371                 break;
1372         }
1373
1374         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1375
1376         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1377                 * ref_clock;
1378
1379         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1380                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1381
1382         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1383                 return 0;
1384
1385         return dco_freq / (p0 * p1 * p2 * 5);
1386 }
1387
1388 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1389                                  enum port port)
1390 {
1391         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1392
1393         switch (val) {
1394         case DDI_CLK_SEL_NONE:
1395                 return 0;
1396         case DDI_CLK_SEL_TBT_162:
1397                 return 162000;
1398         case DDI_CLK_SEL_TBT_270:
1399                 return 270000;
1400         case DDI_CLK_SEL_TBT_540:
1401                 return 540000;
1402         case DDI_CLK_SEL_TBT_810:
1403                 return 810000;
1404         default:
1405                 MISSING_CASE(val);
1406                 return 0;
1407         }
1408 }
1409
1410 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1411                                 const struct intel_dpll_hw_state *pll_state)
1412 {
1413         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1414         u64 tmp;
1415
1416         ref_clock = dev_priv->cdclk.hw.ref;
1417
1418         if (INTEL_GEN(dev_priv) >= 12) {
1419                 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
1420                 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
1421                 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
1422
1423                 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
1424                         m2_frac = pll_state->mg_pll_bias &
1425                                   DKL_PLL_BIAS_FBDIV_FRAC_MASK;
1426                         m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
1427                 } else {
1428                         m2_frac = 0;
1429                 }
1430         } else {
1431                 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1432                 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1433
1434                 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
1435                         m2_frac = pll_state->mg_pll_div0 &
1436                                   MG_PLL_DIV0_FBDIV_FRAC_MASK;
1437                         m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
1438                 } else {
1439                         m2_frac = 0;
1440                 }
1441         }
1442
1443         switch (pll_state->mg_clktop2_hsclkctl &
1444                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1445         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1446                 div1 = 2;
1447                 break;
1448         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1449                 div1 = 3;
1450                 break;
1451         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1452                 div1 = 5;
1453                 break;
1454         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1455                 div1 = 7;
1456                 break;
1457         default:
1458                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1459                 return 0;
1460         }
1461
1462         div2 = (pll_state->mg_clktop2_hsclkctl &
1463                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1464                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1465
1466         /* div2 value of 0 is same as 1 means no div */
1467         if (div2 == 0)
1468                 div2 = 1;
1469
1470         /*
1471          * Adjust the original formula to delay the division by 2^22 in order to
1472          * minimize possible rounding errors.
1473          */
1474         tmp = (u64)m1 * m2_int * ref_clock +
1475               (((u64)m1 * m2_frac * ref_clock) >> 22);
1476         tmp = div_u64(tmp, 5 * div1 * div2);
1477
1478         return tmp;
1479 }
1480
1481 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1482 {
1483         int dotclock;
1484
1485         if (pipe_config->has_pch_encoder)
1486                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1487                                                     &pipe_config->fdi_m_n);
1488         else if (intel_crtc_has_dp_encoder(pipe_config))
1489                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1490                                                     &pipe_config->dp_m_n);
1491         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1492                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1493         else
1494                 dotclock = pipe_config->port_clock;
1495
1496         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1497             !intel_crtc_has_dp_encoder(pipe_config))
1498                 dotclock *= 2;
1499
1500         if (pipe_config->pixel_multiplier)
1501                 dotclock /= pipe_config->pixel_multiplier;
1502
1503         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1504 }
1505
1506 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1507                               struct intel_crtc_state *pipe_config)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1510         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1511         enum port port = encoder->port;
1512         enum phy phy = intel_port_to_phy(dev_priv, port);
1513         int link_clock;
1514
1515         if (intel_phy_is_combo(dev_priv, phy)) {
1516                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1517         } else {
1518                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1519                                                 pipe_config->shared_dpll);
1520
1521                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1522                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1523                 else
1524                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1525         }
1526
1527         pipe_config->port_clock = link_clock;
1528
1529         ddi_dotclock_get(pipe_config);
1530 }
1531
1532 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1533                               struct intel_crtc_state *pipe_config)
1534 {
1535         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1536         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1537         int link_clock;
1538
1539         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1540                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1541         } else {
1542                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1543
1544                 switch (link_clock) {
1545                 case DPLL_CFGCR0_LINK_RATE_810:
1546                         link_clock = 81000;
1547                         break;
1548                 case DPLL_CFGCR0_LINK_RATE_1080:
1549                         link_clock = 108000;
1550                         break;
1551                 case DPLL_CFGCR0_LINK_RATE_1350:
1552                         link_clock = 135000;
1553                         break;
1554                 case DPLL_CFGCR0_LINK_RATE_1620:
1555                         link_clock = 162000;
1556                         break;
1557                 case DPLL_CFGCR0_LINK_RATE_2160:
1558                         link_clock = 216000;
1559                         break;
1560                 case DPLL_CFGCR0_LINK_RATE_2700:
1561                         link_clock = 270000;
1562                         break;
1563                 case DPLL_CFGCR0_LINK_RATE_3240:
1564                         link_clock = 324000;
1565                         break;
1566                 case DPLL_CFGCR0_LINK_RATE_4050:
1567                         link_clock = 405000;
1568                         break;
1569                 default:
1570                         WARN(1, "Unsupported link rate\n");
1571                         break;
1572                 }
1573                 link_clock *= 2;
1574         }
1575
1576         pipe_config->port_clock = link_clock;
1577
1578         ddi_dotclock_get(pipe_config);
1579 }
1580
1581 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1582                               struct intel_crtc_state *pipe_config)
1583 {
1584         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1585         int link_clock;
1586
1587         /*
1588          * ctrl1 register is already shifted for each pll, just use 0 to get
1589          * the internal shift for each field
1590          */
1591         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1592                 link_clock = skl_calc_wrpll_link(pll_state);
1593         } else {
1594                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1595                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1596
1597                 switch (link_clock) {
1598                 case DPLL_CTRL1_LINK_RATE_810:
1599                         link_clock = 81000;
1600                         break;
1601                 case DPLL_CTRL1_LINK_RATE_1080:
1602                         link_clock = 108000;
1603                         break;
1604                 case DPLL_CTRL1_LINK_RATE_1350:
1605                         link_clock = 135000;
1606                         break;
1607                 case DPLL_CTRL1_LINK_RATE_1620:
1608                         link_clock = 162000;
1609                         break;
1610                 case DPLL_CTRL1_LINK_RATE_2160:
1611                         link_clock = 216000;
1612                         break;
1613                 case DPLL_CTRL1_LINK_RATE_2700:
1614                         link_clock = 270000;
1615                         break;
1616                 default:
1617                         WARN(1, "Unsupported link rate\n");
1618                         break;
1619                 }
1620                 link_clock *= 2;
1621         }
1622
1623         pipe_config->port_clock = link_clock;
1624
1625         ddi_dotclock_get(pipe_config);
1626 }
1627
1628 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1629                               struct intel_crtc_state *pipe_config)
1630 {
1631         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1632         int link_clock = 0;
1633         u32 val, pll;
1634
1635         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1636         switch (val & PORT_CLK_SEL_MASK) {
1637         case PORT_CLK_SEL_LCPLL_810:
1638                 link_clock = 81000;
1639                 break;
1640         case PORT_CLK_SEL_LCPLL_1350:
1641                 link_clock = 135000;
1642                 break;
1643         case PORT_CLK_SEL_LCPLL_2700:
1644                 link_clock = 270000;
1645                 break;
1646         case PORT_CLK_SEL_WRPLL1:
1647                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1648                 break;
1649         case PORT_CLK_SEL_WRPLL2:
1650                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1651                 break;
1652         case PORT_CLK_SEL_SPLL:
1653                 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1654                 if (pll == SPLL_FREQ_810MHz)
1655                         link_clock = 81000;
1656                 else if (pll == SPLL_FREQ_1350MHz)
1657                         link_clock = 135000;
1658                 else if (pll == SPLL_FREQ_2700MHz)
1659                         link_clock = 270000;
1660                 else {
1661                         WARN(1, "bad spll freq\n");
1662                         return;
1663                 }
1664                 break;
1665         default:
1666                 WARN(1, "bad port clock sel\n");
1667                 return;
1668         }
1669
1670         pipe_config->port_clock = link_clock * 2;
1671
1672         ddi_dotclock_get(pipe_config);
1673 }
1674
1675 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1676 {
1677         struct dpll clock;
1678
1679         clock.m1 = 2;
1680         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1681         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1682                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1683         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1684         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1685         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1686
1687         return chv_calc_dpll_params(100000, &clock);
1688 }
1689
1690 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1691                               struct intel_crtc_state *pipe_config)
1692 {
1693         pipe_config->port_clock =
1694                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1695
1696         ddi_dotclock_get(pipe_config);
1697 }
1698
1699 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1700                                 struct intel_crtc_state *pipe_config)
1701 {
1702         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1703
1704         if (INTEL_GEN(dev_priv) >= 11)
1705                 icl_ddi_clock_get(encoder, pipe_config);
1706         else if (IS_CANNONLAKE(dev_priv))
1707                 cnl_ddi_clock_get(encoder, pipe_config);
1708         else if (IS_GEN9_LP(dev_priv))
1709                 bxt_ddi_clock_get(encoder, pipe_config);
1710         else if (IS_GEN9_BC(dev_priv))
1711                 skl_ddi_clock_get(encoder, pipe_config);
1712         else if (INTEL_GEN(dev_priv) <= 8)
1713                 hsw_ddi_clock_get(encoder, pipe_config);
1714 }
1715
1716 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1717 {
1718         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1719         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1720         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1721         u32 temp;
1722
1723         if (!intel_crtc_has_dp_encoder(crtc_state))
1724                 return;
1725
1726         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1727
1728         temp = TRANS_MSA_SYNC_CLK;
1729
1730         switch (crtc_state->pipe_bpp) {
1731         case 18:
1732                 temp |= TRANS_MSA_6_BPC;
1733                 break;
1734         case 24:
1735                 temp |= TRANS_MSA_8_BPC;
1736                 break;
1737         case 30:
1738                 temp |= TRANS_MSA_10_BPC;
1739                 break;
1740         case 36:
1741                 temp |= TRANS_MSA_12_BPC;
1742                 break;
1743         default:
1744                 MISSING_CASE(crtc_state->pipe_bpp);
1745                 break;
1746         }
1747
1748         /* nonsense combination */
1749         WARN_ON(crtc_state->limited_color_range &&
1750                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1751
1752         if (crtc_state->limited_color_range)
1753                 temp |= TRANS_MSA_CEA_RANGE;
1754
1755         /*
1756          * As per DP 1.2 spec section 2.3.4.3 while sending
1757          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1758          * colorspace information.
1759          */
1760         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1761                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR |
1762                         TRANS_MSA_YCBCR_BT709;
1763
1764         /*
1765          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1766          * of Color Encoding Format and Content Color Gamut] while sending
1767          * YCBCR 420 signals we should program MSA MISC1 fields which
1768          * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1769          */
1770         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1771                 temp |= TRANS_MSA_USE_VSC_SDP;
1772         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1773 }
1774
1775 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1776                                     bool state)
1777 {
1778         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1779         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1780         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1781         u32 temp;
1782
1783         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1784         if (state == true)
1785                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1786         else
1787                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1788         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1789 }
1790
1791 /*
1792  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1793  *
1794  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1795  * intel_ddi_config_transcoder_func().
1796  */
1797 static u32
1798 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1799 {
1800         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1801         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1802         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1803         enum pipe pipe = crtc->pipe;
1804         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1805         enum port port = encoder->port;
1806         u32 temp;
1807
1808         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1809         temp = TRANS_DDI_FUNC_ENABLE;
1810         if (INTEL_GEN(dev_priv) >= 12)
1811                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1812         else
1813                 temp |= TRANS_DDI_SELECT_PORT(port);
1814
1815         switch (crtc_state->pipe_bpp) {
1816         case 18:
1817                 temp |= TRANS_DDI_BPC_6;
1818                 break;
1819         case 24:
1820                 temp |= TRANS_DDI_BPC_8;
1821                 break;
1822         case 30:
1823                 temp |= TRANS_DDI_BPC_10;
1824                 break;
1825         case 36:
1826                 temp |= TRANS_DDI_BPC_12;
1827                 break;
1828         default:
1829                 BUG();
1830         }
1831
1832         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1833                 temp |= TRANS_DDI_PVSYNC;
1834         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1835                 temp |= TRANS_DDI_PHSYNC;
1836
1837         if (cpu_transcoder == TRANSCODER_EDP) {
1838                 switch (pipe) {
1839                 case PIPE_A:
1840                         /* On Haswell, can only use the always-on power well for
1841                          * eDP when not using the panel fitter, and when not
1842                          * using motion blur mitigation (which we don't
1843                          * support). */
1844                         if (crtc_state->pch_pfit.force_thru)
1845                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1846                         else
1847                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1848                         break;
1849                 case PIPE_B:
1850                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1851                         break;
1852                 case PIPE_C:
1853                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1854                         break;
1855                 default:
1856                         BUG();
1857                         break;
1858                 }
1859         }
1860
1861         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1862                 if (crtc_state->has_hdmi_sink)
1863                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1864                 else
1865                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1866
1867                 if (crtc_state->hdmi_scrambling)
1868                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1869                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1870                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1871         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1872                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1873                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1874         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1875                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1876                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1877         } else {
1878                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1879                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1880         }
1881
1882         return temp;
1883 }
1884
1885 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1886 {
1887         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1888         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1889         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1890         u32 temp;
1891
1892         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1893         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1894 }
1895
1896 /*
1897  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1898  * bit.
1899  */
1900 static void
1901 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1902 {
1903         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1904         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1905         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1906         u32 temp;
1907
1908         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1909         temp &= ~TRANS_DDI_FUNC_ENABLE;
1910         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1911 }
1912
1913 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1914 {
1915         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1916         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1917         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1918         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1919         u32 val = I915_READ(reg);
1920
1921         if (INTEL_GEN(dev_priv) >= 12) {
1922                 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1923                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1924         } else {
1925                 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1926                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1927         }
1928         I915_WRITE(reg, val);
1929
1930         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1931             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1932                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1933                 /* Quirk time at 100ms for reliable operation */
1934                 msleep(100);
1935         }
1936 }
1937
1938 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1939                                      bool enable)
1940 {
1941         struct drm_device *dev = intel_encoder->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         intel_wakeref_t wakeref;
1944         enum pipe pipe = 0;
1945         int ret = 0;
1946         u32 tmp;
1947
1948         wakeref = intel_display_power_get_if_enabled(dev_priv,
1949                                                      intel_encoder->power_domain);
1950         if (WARN_ON(!wakeref))
1951                 return -ENXIO;
1952
1953         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1954                 ret = -EIO;
1955                 goto out;
1956         }
1957
1958         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1959         if (enable)
1960                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1961         else
1962                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1963         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1964 out:
1965         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1966         return ret;
1967 }
1968
1969 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1970 {
1971         struct drm_device *dev = intel_connector->base.dev;
1972         struct drm_i915_private *dev_priv = to_i915(dev);
1973         struct intel_encoder *encoder = intel_connector->encoder;
1974         int type = intel_connector->base.connector_type;
1975         enum port port = encoder->port;
1976         enum transcoder cpu_transcoder;
1977         intel_wakeref_t wakeref;
1978         enum pipe pipe = 0;
1979         u32 tmp;
1980         bool ret;
1981
1982         wakeref = intel_display_power_get_if_enabled(dev_priv,
1983                                                      encoder->power_domain);
1984         if (!wakeref)
1985                 return false;
1986
1987         if (!encoder->get_hw_state(encoder, &pipe)) {
1988                 ret = false;
1989                 goto out;
1990         }
1991
1992         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1993                 cpu_transcoder = TRANSCODER_EDP;
1994         else
1995                 cpu_transcoder = (enum transcoder) pipe;
1996
1997         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1998
1999         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2000         case TRANS_DDI_MODE_SELECT_HDMI:
2001         case TRANS_DDI_MODE_SELECT_DVI:
2002                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2003                 break;
2004
2005         case TRANS_DDI_MODE_SELECT_DP_SST:
2006                 ret = type == DRM_MODE_CONNECTOR_eDP ||
2007                       type == DRM_MODE_CONNECTOR_DisplayPort;
2008                 break;
2009
2010         case TRANS_DDI_MODE_SELECT_DP_MST:
2011                 /* if the transcoder is in MST state then
2012                  * connector isn't connected */
2013                 ret = false;
2014                 break;
2015
2016         case TRANS_DDI_MODE_SELECT_FDI:
2017                 ret = type == DRM_MODE_CONNECTOR_VGA;
2018                 break;
2019
2020         default:
2021                 ret = false;
2022                 break;
2023         }
2024
2025 out:
2026         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2027
2028         return ret;
2029 }
2030
2031 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2032                                         u8 *pipe_mask, bool *is_dp_mst)
2033 {
2034         struct drm_device *dev = encoder->base.dev;
2035         struct drm_i915_private *dev_priv = to_i915(dev);
2036         enum port port = encoder->port;
2037         intel_wakeref_t wakeref;
2038         enum pipe p;
2039         u32 tmp;
2040         u8 mst_pipe_mask;
2041
2042         *pipe_mask = 0;
2043         *is_dp_mst = false;
2044
2045         wakeref = intel_display_power_get_if_enabled(dev_priv,
2046                                                      encoder->power_domain);
2047         if (!wakeref)
2048                 return;
2049
2050         tmp = I915_READ(DDI_BUF_CTL(port));
2051         if (!(tmp & DDI_BUF_CTL_ENABLE))
2052                 goto out;
2053
2054         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
2055                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2056
2057                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2058                 default:
2059                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2060                         /* fallthrough */
2061                 case TRANS_DDI_EDP_INPUT_A_ON:
2062                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2063                         *pipe_mask = BIT(PIPE_A);
2064                         break;
2065                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2066                         *pipe_mask = BIT(PIPE_B);
2067                         break;
2068                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2069                         *pipe_mask = BIT(PIPE_C);
2070                         break;
2071                 }
2072
2073                 goto out;
2074         }
2075
2076         mst_pipe_mask = 0;
2077         for_each_pipe(dev_priv, p) {
2078                 enum transcoder cpu_transcoder = (enum transcoder)p;
2079                 unsigned int port_mask, ddi_select;
2080                 intel_wakeref_t trans_wakeref;
2081
2082                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2083                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2084                 if (!trans_wakeref)
2085                         continue;
2086
2087                 if (INTEL_GEN(dev_priv) >= 12) {
2088                         port_mask = TGL_TRANS_DDI_PORT_MASK;
2089                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2090                 } else {
2091                         port_mask = TRANS_DDI_PORT_MASK;
2092                         ddi_select = TRANS_DDI_SELECT_PORT(port);
2093                 }
2094
2095                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2096                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2097                                         trans_wakeref);
2098
2099                 if ((tmp & port_mask) != ddi_select)
2100                         continue;
2101
2102                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2103                     TRANS_DDI_MODE_SELECT_DP_MST)
2104                         mst_pipe_mask |= BIT(p);
2105
2106                 *pipe_mask |= BIT(p);
2107         }
2108
2109         if (!*pipe_mask)
2110                 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2111                               encoder->base.base.id, encoder->base.name);
2112
2113         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2114                 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2115                               encoder->base.base.id, encoder->base.name,
2116                               *pipe_mask);
2117                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2118         }
2119
2120         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2121                 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2122                               encoder->base.base.id, encoder->base.name,
2123                               *pipe_mask, mst_pipe_mask);
2124         else
2125                 *is_dp_mst = mst_pipe_mask;
2126
2127 out:
2128         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2129                 tmp = I915_READ(BXT_PHY_CTL(port));
2130                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2131                             BXT_PHY_LANE_POWERDOWN_ACK |
2132                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2133                         DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2134                                   "(PHY_CTL %08x)\n", encoder->base.base.id,
2135                                   encoder->base.name, tmp);
2136         }
2137
2138         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2139 }
2140
2141 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2142                             enum pipe *pipe)
2143 {
2144         u8 pipe_mask;
2145         bool is_mst;
2146
2147         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2148
2149         if (is_mst || !pipe_mask)
2150                 return false;
2151
2152         *pipe = ffs(pipe_mask) - 1;
2153
2154         return true;
2155 }
2156
2157 static inline enum intel_display_power_domain
2158 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2159 {
2160         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2161          * DC states enabled at the same time, while for driver initiated AUX
2162          * transfers we need the same AUX IOs to be powered but with DC states
2163          * disabled. Accordingly use the AUX power domain here which leaves DC
2164          * states enabled.
2165          * However, for non-A AUX ports the corresponding non-EDP transcoders
2166          * would have already enabled power well 2 and DC_OFF. This means we can
2167          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2168          * specific AUX_IO reference without powering up any extra wells.
2169          * Note that PSR is enabled only on Port A even though this function
2170          * returns the correct domain for other ports too.
2171          */
2172         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2173                                               intel_aux_power_domain(dig_port);
2174 }
2175
2176 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2177                                         struct intel_crtc_state *crtc_state)
2178 {
2179         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2180         struct intel_digital_port *dig_port;
2181         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2182
2183         /*
2184          * TODO: Add support for MST encoders. Atm, the following should never
2185          * happen since fake-MST encoders don't set their get_power_domains()
2186          * hook.
2187          */
2188         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2189                 return;
2190
2191         dig_port = enc_to_dig_port(&encoder->base);
2192         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2193
2194         /*
2195          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2196          * ports.
2197          */
2198         if (intel_crtc_has_dp_encoder(crtc_state) ||
2199             intel_phy_is_tc(dev_priv, phy))
2200                 intel_display_power_get(dev_priv,
2201                                         intel_ddi_main_link_aux_domain(dig_port));
2202
2203         /*
2204          * VDSC power is needed when DSC is enabled
2205          */
2206         if (crtc_state->dsc_params.compression_enable)
2207                 intel_display_power_get(dev_priv,
2208                                         intel_dsc_power_domain(crtc_state));
2209 }
2210
2211 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2212 {
2213         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2214         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2215         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2216         enum port port = encoder->port;
2217         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2218
2219         if (cpu_transcoder != TRANSCODER_EDP) {
2220                 if (INTEL_GEN(dev_priv) >= 12)
2221                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2222                                    TGL_TRANS_CLK_SEL_PORT(port));
2223                 else
2224                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2225                                    TRANS_CLK_SEL_PORT(port));
2226         }
2227 }
2228
2229 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2230 {
2231         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2232         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2233
2234         if (cpu_transcoder != TRANSCODER_EDP) {
2235                 if (INTEL_GEN(dev_priv) >= 12)
2236                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2237                                    TGL_TRANS_CLK_SEL_DISABLED);
2238                 else
2239                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2240                                    TRANS_CLK_SEL_DISABLED);
2241         }
2242 }
2243
2244 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2245                                 enum port port, u8 iboost)
2246 {
2247         u32 tmp;
2248
2249         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2250         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2251         if (iboost)
2252                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2253         else
2254                 tmp |= BALANCE_LEG_DISABLE(port);
2255         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2256 }
2257
2258 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2259                                int level, enum intel_output_type type)
2260 {
2261         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2263         enum port port = encoder->port;
2264         u8 iboost;
2265
2266         if (type == INTEL_OUTPUT_HDMI)
2267                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2268         else
2269                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2270
2271         if (iboost == 0) {
2272                 const struct ddi_buf_trans *ddi_translations;
2273                 int n_entries;
2274
2275                 if (type == INTEL_OUTPUT_HDMI)
2276                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2277                 else if (type == INTEL_OUTPUT_EDP)
2278                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2279                 else
2280                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2281
2282                 if (WARN_ON_ONCE(!ddi_translations))
2283                         return;
2284                 if (WARN_ON_ONCE(level >= n_entries))
2285                         level = n_entries - 1;
2286
2287                 iboost = ddi_translations[level].i_boost;
2288         }
2289
2290         /* Make sure that the requested I_boost is valid */
2291         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2292                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2293                 return;
2294         }
2295
2296         _skl_ddi_set_iboost(dev_priv, port, iboost);
2297
2298         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2299                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2300 }
2301
2302 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2303                                     int level, enum intel_output_type type)
2304 {
2305         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2306         const struct bxt_ddi_buf_trans *ddi_translations;
2307         enum port port = encoder->port;
2308         int n_entries;
2309
2310         if (type == INTEL_OUTPUT_HDMI)
2311                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2312         else if (type == INTEL_OUTPUT_EDP)
2313                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2314         else
2315                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2316
2317         if (WARN_ON_ONCE(!ddi_translations))
2318                 return;
2319         if (WARN_ON_ONCE(level >= n_entries))
2320                 level = n_entries - 1;
2321
2322         bxt_ddi_phy_set_signal_level(dev_priv, port,
2323                                      ddi_translations[level].margin,
2324                                      ddi_translations[level].scale,
2325                                      ddi_translations[level].enable,
2326                                      ddi_translations[level].deemphasis);
2327 }
2328
2329 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2330 {
2331         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2332         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2333         enum port port = encoder->port;
2334         enum phy phy = intel_port_to_phy(dev_priv, port);
2335         int n_entries;
2336
2337         if (INTEL_GEN(dev_priv) >= 11) {
2338                 if (intel_phy_is_combo(dev_priv, phy))
2339                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2340                                                 intel_dp->link_rate, &n_entries);
2341                 else
2342                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2343         } else if (IS_CANNONLAKE(dev_priv)) {
2344                 if (encoder->type == INTEL_OUTPUT_EDP)
2345                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2346                 else
2347                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2348         } else if (IS_GEN9_LP(dev_priv)) {
2349                 if (encoder->type == INTEL_OUTPUT_EDP)
2350                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2351                 else
2352                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2353         } else {
2354                 if (encoder->type == INTEL_OUTPUT_EDP)
2355                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2356                 else
2357                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2358         }
2359
2360         if (WARN_ON(n_entries < 1))
2361                 n_entries = 1;
2362         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2363                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2364
2365         return index_to_dp_signal_levels[n_entries - 1] &
2366                 DP_TRAIN_VOLTAGE_SWING_MASK;
2367 }
2368
2369 /*
2370  * We assume that the full set of pre-emphasis values can be
2371  * used on all DDI platforms. Should that change we need to
2372  * rethink this code.
2373  */
2374 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2375 {
2376         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2377         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2378                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2379         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2380                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2381         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2382                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2383         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2384         default:
2385                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2386         }
2387 }
2388
2389 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2390                                    int level, enum intel_output_type type)
2391 {
2392         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2393         const struct cnl_ddi_buf_trans *ddi_translations;
2394         enum port port = encoder->port;
2395         int n_entries, ln;
2396         u32 val;
2397
2398         if (type == INTEL_OUTPUT_HDMI)
2399                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2400         else if (type == INTEL_OUTPUT_EDP)
2401                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2402         else
2403                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2404
2405         if (WARN_ON_ONCE(!ddi_translations))
2406                 return;
2407         if (WARN_ON_ONCE(level >= n_entries))
2408                 level = n_entries - 1;
2409
2410         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2411         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2412         val &= ~SCALING_MODE_SEL_MASK;
2413         val |= SCALING_MODE_SEL(2);
2414         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2415
2416         /* Program PORT_TX_DW2 */
2417         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2418         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2419                  RCOMP_SCALAR_MASK);
2420         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2421         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2422         /* Rcomp scalar is fixed as 0x98 for every table entry */
2423         val |= RCOMP_SCALAR(0x98);
2424         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2425
2426         /* Program PORT_TX_DW4 */
2427         /* We cannot write to GRP. It would overrite individual loadgen */
2428         for (ln = 0; ln < 4; ln++) {
2429                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2430                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2431                          CURSOR_COEFF_MASK);
2432                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2433                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2434                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2435                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2436         }
2437
2438         /* Program PORT_TX_DW5 */
2439         /* All DW5 values are fixed for every table entry */
2440         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2441         val &= ~RTERM_SELECT_MASK;
2442         val |= RTERM_SELECT(6);
2443         val |= TAP3_DISABLE;
2444         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2445
2446         /* Program PORT_TX_DW7 */
2447         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2448         val &= ~N_SCALAR_MASK;
2449         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2450         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2451 }
2452
2453 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2454                                     int level, enum intel_output_type type)
2455 {
2456         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2457         enum port port = encoder->port;
2458         int width, rate, ln;
2459         u32 val;
2460
2461         if (type == INTEL_OUTPUT_HDMI) {
2462                 width = 4;
2463                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2464         } else {
2465                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2466
2467                 width = intel_dp->lane_count;
2468                 rate = intel_dp->link_rate;
2469         }
2470
2471         /*
2472          * 1. If port type is eDP or DP,
2473          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2474          * else clear to 0b.
2475          */
2476         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2477         if (type != INTEL_OUTPUT_HDMI)
2478                 val |= COMMON_KEEPER_EN;
2479         else
2480                 val &= ~COMMON_KEEPER_EN;
2481         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2482
2483         /* 2. Program loadgen select */
2484         /*
2485          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2486          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2487          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2488          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2489          */
2490         for (ln = 0; ln <= 3; ln++) {
2491                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2492                 val &= ~LOADGEN_SELECT;
2493
2494                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2495                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2496                         val |= LOADGEN_SELECT;
2497                 }
2498                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2499         }
2500
2501         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2502         val = I915_READ(CNL_PORT_CL1CM_DW5);
2503         val |= SUS_CLOCK_CONFIG;
2504         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2505
2506         /* 4. Clear training enable to change swing values */
2507         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2508         val &= ~TX_TRAINING_EN;
2509         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2510
2511         /* 5. Program swing and de-emphasis */
2512         cnl_ddi_vswing_program(encoder, level, type);
2513
2514         /* 6. Set training enable to trigger update */
2515         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2516         val |= TX_TRAINING_EN;
2517         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2518 }
2519
2520 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2521                                         u32 level, enum phy phy, int type,
2522                                         int rate)
2523 {
2524         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2525         u32 n_entries, val;
2526         int ln;
2527
2528         ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2529                                                    &n_entries);
2530         if (!ddi_translations)
2531                 return;
2532
2533         if (level >= n_entries) {
2534                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2535                 level = n_entries - 1;
2536         }
2537
2538         /* Set PORT_TX_DW5 */
2539         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2540         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2541                   TAP2_DISABLE | TAP3_DISABLE);
2542         val |= SCALING_MODE_SEL(0x2);
2543         val |= RTERM_SELECT(0x6);
2544         val |= TAP3_DISABLE;
2545         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2546
2547         /* Program PORT_TX_DW2 */
2548         val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2549         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2550                  RCOMP_SCALAR_MASK);
2551         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2552         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2553         /* Program Rcomp scalar for every table entry */
2554         val |= RCOMP_SCALAR(0x98);
2555         I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2556
2557         /* Program PORT_TX_DW4 */
2558         /* We cannot write to GRP. It would overwrite individual loadgen. */
2559         for (ln = 0; ln <= 3; ln++) {
2560                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2561                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2562                          CURSOR_COEFF_MASK);
2563                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2564                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2565                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2566                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2567         }
2568
2569         /* Program PORT_TX_DW7 */
2570         val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2571         val &= ~N_SCALAR_MASK;
2572         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2573         I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2574 }
2575
2576 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2577                                               u32 level,
2578                                               enum intel_output_type type)
2579 {
2580         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2581         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2582         int width = 0;
2583         int rate = 0;
2584         u32 val;
2585         int ln = 0;
2586
2587         if (type == INTEL_OUTPUT_HDMI) {
2588                 width = 4;
2589                 /* Rate is always < than 6GHz for HDMI */
2590         } else {
2591                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2592
2593                 width = intel_dp->lane_count;
2594                 rate = intel_dp->link_rate;
2595         }
2596
2597         /*
2598          * 1. If port type is eDP or DP,
2599          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2600          * else clear to 0b.
2601          */
2602         val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2603         if (type == INTEL_OUTPUT_HDMI)
2604                 val &= ~COMMON_KEEPER_EN;
2605         else
2606                 val |= COMMON_KEEPER_EN;
2607         I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2608
2609         /* 2. Program loadgen select */
2610         /*
2611          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2612          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2613          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2614          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2615          */
2616         for (ln = 0; ln <= 3; ln++) {
2617                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2618                 val &= ~LOADGEN_SELECT;
2619
2620                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2621                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2622                         val |= LOADGEN_SELECT;
2623                 }
2624                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2625         }
2626
2627         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2628         val = I915_READ(ICL_PORT_CL_DW5(phy));
2629         val |= SUS_CLOCK_CONFIG;
2630         I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2631
2632         /* 4. Clear training enable to change swing values */
2633         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2634         val &= ~TX_TRAINING_EN;
2635         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2636
2637         /* 5. Program swing and de-emphasis */
2638         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2639
2640         /* 6. Set training enable to trigger update */
2641         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2642         val |= TX_TRAINING_EN;
2643         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2644 }
2645
2646 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2647                                            int link_clock,
2648                                            u32 level)
2649 {
2650         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2651         enum port port = encoder->port;
2652         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2653         u32 n_entries, val;
2654         int ln;
2655
2656         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2657         ddi_translations = icl_mg_phy_ddi_translations;
2658         /* The table does not have values for level 3 and level 9. */
2659         if (level >= n_entries || level == 3 || level == 9) {
2660                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2661                               level, n_entries - 2);
2662                 level = n_entries - 2;
2663         }
2664
2665         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2666         for (ln = 0; ln < 2; ln++) {
2667                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2668                 val &= ~CRI_USE_FS32;
2669                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2670
2671                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2672                 val &= ~CRI_USE_FS32;
2673                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2674         }
2675
2676         /* Program MG_TX_SWINGCTRL with values from vswing table */
2677         for (ln = 0; ln < 2; ln++) {
2678                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2679                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2680                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2681                         ddi_translations[level].cri_txdeemph_override_17_12);
2682                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2683
2684                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2685                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2686                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2687                         ddi_translations[level].cri_txdeemph_override_17_12);
2688                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2689         }
2690
2691         /* Program MG_TX_DRVCTRL with values from vswing table */
2692         for (ln = 0; ln < 2; ln++) {
2693                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2694                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2695                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2696                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2697                         ddi_translations[level].cri_txdeemph_override_5_0) |
2698                         CRI_TXDEEMPH_OVERRIDE_11_6(
2699                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2700                         CRI_TXDEEMPH_OVERRIDE_EN;
2701                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2702
2703                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2704                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2705                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2706                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2707                         ddi_translations[level].cri_txdeemph_override_5_0) |
2708                         CRI_TXDEEMPH_OVERRIDE_11_6(
2709                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2710                         CRI_TXDEEMPH_OVERRIDE_EN;
2711                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2712
2713                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2714         }
2715
2716         /*
2717          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2718          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2719          * values from table for which TX1 and TX2 enabled.
2720          */
2721         for (ln = 0; ln < 2; ln++) {
2722                 val = I915_READ(MG_CLKHUB(ln, port));
2723                 if (link_clock < 300000)
2724                         val |= CFG_LOW_RATE_LKREN_EN;
2725                 else
2726                         val &= ~CFG_LOW_RATE_LKREN_EN;
2727                 I915_WRITE(MG_CLKHUB(ln, port), val);
2728         }
2729
2730         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2731         for (ln = 0; ln < 2; ln++) {
2732                 val = I915_READ(MG_TX1_DCC(ln, port));
2733                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2734                 if (link_clock <= 500000) {
2735                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2736                 } else {
2737                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2738                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2739                 }
2740                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2741
2742                 val = I915_READ(MG_TX2_DCC(ln, port));
2743                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2744                 if (link_clock <= 500000) {
2745                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2746                 } else {
2747                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2748                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2749                 }
2750                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2751         }
2752
2753         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2754         for (ln = 0; ln < 2; ln++) {
2755                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2756                 val |= CRI_CALCINIT;
2757                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2758
2759                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2760                 val |= CRI_CALCINIT;
2761                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2762         }
2763 }
2764
2765 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2766                                     int link_clock,
2767                                     u32 level,
2768                                     enum intel_output_type type)
2769 {
2770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2771         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2772
2773         if (intel_phy_is_combo(dev_priv, phy))
2774                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2775         else
2776                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2777 }
2778
2779 static u32 translate_signal_level(int signal_levels)
2780 {
2781         int i;
2782
2783         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2784                 if (index_to_dp_signal_levels[i] == signal_levels)
2785                         return i;
2786         }
2787
2788         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2789              signal_levels);
2790
2791         return 0;
2792 }
2793
2794 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2795 {
2796         u8 train_set = intel_dp->train_set[0];
2797         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2798                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2799
2800         return translate_signal_level(signal_levels);
2801 }
2802
2803 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2804 {
2805         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2806         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2807         struct intel_encoder *encoder = &dport->base;
2808         int level = intel_ddi_dp_level(intel_dp);
2809
2810         if (INTEL_GEN(dev_priv) >= 11)
2811                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2812                                         level, encoder->type);
2813         else if (IS_CANNONLAKE(dev_priv))
2814                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2815         else
2816                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2817
2818         return 0;
2819 }
2820
2821 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2822 {
2823         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2824         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2825         struct intel_encoder *encoder = &dport->base;
2826         int level = intel_ddi_dp_level(intel_dp);
2827
2828         if (IS_GEN9_BC(dev_priv))
2829                 skl_ddi_set_iboost(encoder, level, encoder->type);
2830
2831         return DDI_BUF_TRANS_SELECT(level);
2832 }
2833
2834 static inline
2835 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2836                               enum phy phy)
2837 {
2838         if (intel_phy_is_combo(dev_priv, phy)) {
2839                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2840         } else if (intel_phy_is_tc(dev_priv, phy)) {
2841                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2842                                                         (enum port)phy);
2843
2844                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2845         }
2846
2847         return 0;
2848 }
2849
2850 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2851                                   const struct intel_crtc_state *crtc_state)
2852 {
2853         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2854         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2855         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2856         u32 val;
2857
2858         mutex_lock(&dev_priv->dpll_lock);
2859
2860         val = I915_READ(ICL_DPCLKA_CFGCR0);
2861         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2862
2863         if (intel_phy_is_combo(dev_priv, phy)) {
2864                 /*
2865                  * Even though this register references DDIs, note that we
2866                  * want to pass the PHY rather than the port (DDI).  For
2867                  * ICL, port=phy in all cases so it doesn't matter, but for
2868                  * EHL the bspec notes the following:
2869                  *
2870                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2871                  *   Clock Select chooses the PLL for both DDIA and DDID and
2872                  *   drives port A in all cases."
2873                  */
2874                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2875                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2876                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2877                 POSTING_READ(ICL_DPCLKA_CFGCR0);
2878         }
2879
2880         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2881         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2882
2883         mutex_unlock(&dev_priv->dpll_lock);
2884 }
2885
2886 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2887 {
2888         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2889         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2890         u32 val;
2891
2892         mutex_lock(&dev_priv->dpll_lock);
2893
2894         val = I915_READ(ICL_DPCLKA_CFGCR0);
2895         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2896         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2897
2898         mutex_unlock(&dev_priv->dpll_lock);
2899 }
2900
2901 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2902 {
2903         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2904         u32 val;
2905         enum port port;
2906         u32 port_mask;
2907         bool ddi_clk_needed;
2908
2909         /*
2910          * In case of DP MST, we sanitize the primary encoder only, not the
2911          * virtual ones.
2912          */
2913         if (encoder->type == INTEL_OUTPUT_DP_MST)
2914                 return;
2915
2916         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2917                 u8 pipe_mask;
2918                 bool is_mst;
2919
2920                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2921                 /*
2922                  * In the unlikely case that BIOS enables DP in MST mode, just
2923                  * warn since our MST HW readout is incomplete.
2924                  */
2925                 if (WARN_ON(is_mst))
2926                         return;
2927         }
2928
2929         port_mask = BIT(encoder->port);
2930         ddi_clk_needed = encoder->base.crtc;
2931
2932         if (encoder->type == INTEL_OUTPUT_DSI) {
2933                 struct intel_encoder *other_encoder;
2934
2935                 port_mask = intel_dsi_encoder_ports(encoder);
2936                 /*
2937                  * Sanity check that we haven't incorrectly registered another
2938                  * encoder using any of the ports of this DSI encoder.
2939                  */
2940                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2941                         if (other_encoder == encoder)
2942                                 continue;
2943
2944                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2945                                 return;
2946                 }
2947                 /*
2948                  * For DSI we keep the ddi clocks gated
2949                  * except during enable/disable sequence.
2950                  */
2951                 ddi_clk_needed = false;
2952         }
2953
2954         val = I915_READ(ICL_DPCLKA_CFGCR0);
2955         for_each_port_masked(port, port_mask) {
2956                 enum phy phy = intel_port_to_phy(dev_priv, port);
2957
2958                 bool ddi_clk_ungated = !(val &
2959                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2960                                                                    phy));
2961
2962                 if (ddi_clk_needed == ddi_clk_ungated)
2963                         continue;
2964
2965                 /*
2966                  * Punt on the case now where clock is gated, but it would
2967                  * be needed by the port. Something else is really broken then.
2968                  */
2969                 if (WARN_ON(ddi_clk_needed))
2970                         continue;
2971
2972                 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2973                          phy_name(port));
2974                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2975                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2976         }
2977 }
2978
2979 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2980                                  const struct intel_crtc_state *crtc_state)
2981 {
2982         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2983         enum port port = encoder->port;
2984         enum phy phy = intel_port_to_phy(dev_priv, port);
2985         u32 val;
2986         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2987
2988         if (WARN_ON(!pll))
2989                 return;
2990
2991         mutex_lock(&dev_priv->dpll_lock);
2992
2993         if (INTEL_GEN(dev_priv) >= 11) {
2994                 if (!intel_phy_is_combo(dev_priv, phy))
2995                         I915_WRITE(DDI_CLK_SEL(port),
2996                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2997                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2998                         /*
2999                          * MG does not exist but the programming is required
3000                          * to ungate DDIC and DDID
3001                          */
3002                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
3003         } else if (IS_CANNONLAKE(dev_priv)) {
3004                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3005                 val = I915_READ(DPCLKA_CFGCR0);
3006                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3007                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3008                 I915_WRITE(DPCLKA_CFGCR0, val);
3009
3010                 /*
3011                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3012                  * This step and the step before must be done with separate
3013                  * register writes.
3014                  */
3015                 val = I915_READ(DPCLKA_CFGCR0);
3016                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3017                 I915_WRITE(DPCLKA_CFGCR0, val);
3018         } else if (IS_GEN9_BC(dev_priv)) {
3019                 /* DDI -> PLL mapping  */
3020                 val = I915_READ(DPLL_CTRL2);
3021
3022                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3023                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3024                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3025                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3026
3027                 I915_WRITE(DPLL_CTRL2, val);
3028
3029         } else if (INTEL_GEN(dev_priv) < 9) {
3030                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
3031         }
3032
3033         mutex_unlock(&dev_priv->dpll_lock);
3034 }
3035
3036 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3037 {
3038         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3039         enum port port = encoder->port;
3040         enum phy phy = intel_port_to_phy(dev_priv, port);
3041
3042         if (INTEL_GEN(dev_priv) >= 11) {
3043                 if (!intel_phy_is_combo(dev_priv, phy) ||
3044                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3045                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3046         } else if (IS_CANNONLAKE(dev_priv)) {
3047                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3048                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3049         } else if (IS_GEN9_BC(dev_priv)) {
3050                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3051                            DPLL_CTRL2_DDI_CLK_OFF(port));
3052         } else if (INTEL_GEN(dev_priv) < 9) {
3053                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3054         }
3055 }
3056
3057 static void
3058 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
3059 {
3060         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3061         enum port port = dig_port->base.port;
3062         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3063         u32 val, bits;
3064         int ln;
3065
3066         if (tc_port == PORT_TC_NONE)
3067                 return;
3068
3069         bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
3070                MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
3071                MG_DP_MODE_CFG_GAONPWR_GATING;
3072
3073         for (ln = 0; ln < 2; ln++) {
3074                 val = I915_READ(MG_DP_MODE(ln, port));
3075                 if (enable)
3076                         val |= bits;
3077                 else
3078                         val &= ~bits;
3079                 I915_WRITE(MG_DP_MODE(ln, port), val);
3080         }
3081
3082         bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING |
3083                MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING |
3084                MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING;
3085
3086         val = I915_READ(MG_MISC_SUS0(tc_port));
3087         if (enable)
3088                 val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
3089         else
3090                 val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
3091         I915_WRITE(MG_MISC_SUS0(tc_port), val);
3092 }
3093
3094 static void
3095 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
3096                        const struct intel_crtc_state *crtc_state)
3097 {
3098         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3099         enum port port = intel_dig_port->base.port;
3100         u32 ln0, ln1, pin_assignment;
3101         u8 width;
3102
3103         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3104                 return;
3105
3106         ln0 = I915_READ(MG_DP_MODE(0, port));
3107         ln1 = I915_READ(MG_DP_MODE(1, port));
3108
3109         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
3110         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3111
3112         /* DPPATC */
3113         pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
3114         width = crtc_state->lane_count;
3115
3116         switch (pin_assignment) {
3117         case 0x0:
3118                 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
3119                 if (width == 1) {
3120                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3121                 } else {
3122                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3123                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3124                 }
3125                 break;
3126         case 0x1:
3127                 if (width == 4) {
3128                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3129                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3130                 }
3131                 break;
3132         case 0x2:
3133                 if (width == 2) {
3134                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3135                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3136                 }
3137                 break;
3138         case 0x3:
3139         case 0x5:
3140                 if (width == 1) {
3141                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3142                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3143                 } else {
3144                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3145                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3146                 }
3147                 break;
3148         case 0x4:
3149         case 0x6:
3150                 if (width == 1) {
3151                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3152                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3153                 } else {
3154                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3155                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3156                 }
3157                 break;
3158         default:
3159                 MISSING_CASE(pin_assignment);
3160         }
3161
3162         I915_WRITE(MG_DP_MODE(0, port), ln0);
3163         I915_WRITE(MG_DP_MODE(1, port), ln1);
3164 }
3165
3166 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3167                                         const struct intel_crtc_state *crtc_state)
3168 {
3169         if (!crtc_state->fec_enable)
3170                 return;
3171
3172         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3173                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3174 }
3175
3176 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3177                                  const struct intel_crtc_state *crtc_state)
3178 {
3179         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3180         struct intel_dp *intel_dp;
3181         u32 val;
3182
3183         if (!crtc_state->fec_enable)
3184                 return;
3185
3186         intel_dp = enc_to_intel_dp(&encoder->base);
3187         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3188         val |= DP_TP_CTL_FEC_ENABLE;
3189         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3190
3191         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3192                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3193                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3194 }
3195
3196 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3197                                         const struct intel_crtc_state *crtc_state)
3198 {
3199         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3200         struct intel_dp *intel_dp;
3201         u32 val;
3202
3203         if (!crtc_state->fec_enable)
3204                 return;
3205
3206         intel_dp = enc_to_intel_dp(&encoder->base);
3207         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3208         val &= ~DP_TP_CTL_FEC_ENABLE;
3209         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3210         POSTING_READ(intel_dp->regs.dp_tp_ctl);
3211 }
3212
3213 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3214                                   const struct intel_crtc_state *crtc_state,
3215                                   const struct drm_connector_state *conn_state)
3216 {
3217         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3219         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3220         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3221         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3222         int level = intel_ddi_dp_level(intel_dp);
3223         enum transcoder transcoder = crtc_state->cpu_transcoder;
3224
3225         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3226                                  crtc_state->lane_count, is_mst);
3227
3228         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3229         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3230
3231         /* 1.a got on intel_atomic_commit_tail() */
3232
3233         /* 2. */
3234         intel_edp_panel_on(intel_dp);
3235
3236         /*
3237          * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
3238          * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
3239          * haswell_crtc_enable()->intel_enable_shared_dpll()
3240          */
3241
3242         /* 4.b */
3243         intel_ddi_clk_select(encoder, crtc_state);
3244
3245         /* 5. */
3246         if (!intel_phy_is_tc(dev_priv, phy) ||
3247             dig_port->tc_mode != TC_PORT_TBT_ALT)
3248                 intel_display_power_get(dev_priv,
3249                                         dig_port->ddi_io_power_domain);
3250
3251         /* 6. */
3252         icl_program_mg_dp_mode(dig_port, crtc_state);
3253
3254         /*
3255          * 7.a - Steps in this function should only be executed over MST
3256          * master, what will be taken in care by MST hook
3257          * intel_mst_pre_enable_dp()
3258          */
3259         intel_ddi_enable_pipe_clock(crtc_state);
3260
3261         /* 7.b */
3262         intel_ddi_config_transcoder_func(crtc_state);
3263
3264         /* 7.d */
3265         icl_phy_set_clock_gating(dig_port, false);
3266
3267         /* 7.e */
3268         icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3269                                 encoder->type);
3270
3271         /* 7.f */
3272         if (intel_phy_is_combo(dev_priv, phy)) {
3273                 bool lane_reversal =
3274                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3275
3276                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3277                                                crtc_state->lane_count,
3278                                                lane_reversal);
3279         }
3280
3281         /* 7.g */
3282         intel_ddi_init_dp_buf_reg(encoder);
3283
3284         if (!is_mst)
3285                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3286
3287         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3288         /*
3289          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3290          * in the FEC_CONFIGURATION register to 1 before initiating link
3291          * training
3292          */
3293         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3294         /* 7.c, 7.h, 7.i, 7.j */
3295         intel_dp_start_link_train(intel_dp);
3296
3297         /* 7.k */
3298         intel_dp_stop_link_train(intel_dp);
3299
3300         /* 7.l */
3301         intel_ddi_enable_fec(encoder, crtc_state);
3302         intel_dsc_enable(encoder, crtc_state);
3303 }
3304
3305 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3306                                   const struct intel_crtc_state *crtc_state,
3307                                   const struct drm_connector_state *conn_state)
3308 {
3309         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3311         enum port port = encoder->port;
3312         enum phy phy = intel_port_to_phy(dev_priv, port);
3313         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3314         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3315         int level = intel_ddi_dp_level(intel_dp);
3316
3317         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3318
3319         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3320                                  crtc_state->lane_count, is_mst);
3321
3322         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3323         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3324
3325         intel_edp_panel_on(intel_dp);
3326
3327         intel_ddi_clk_select(encoder, crtc_state);
3328
3329         if (!intel_phy_is_tc(dev_priv, phy) ||
3330             dig_port->tc_mode != TC_PORT_TBT_ALT)
3331                 intel_display_power_get(dev_priv,
3332                                         dig_port->ddi_io_power_domain);
3333
3334         icl_program_mg_dp_mode(dig_port, crtc_state);
3335         icl_phy_set_clock_gating(dig_port, false);
3336
3337         if (INTEL_GEN(dev_priv) >= 11)
3338                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3339                                         level, encoder->type);
3340         else if (IS_CANNONLAKE(dev_priv))
3341                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3342         else if (IS_GEN9_LP(dev_priv))
3343                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3344         else
3345                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3346
3347         if (intel_phy_is_combo(dev_priv, phy)) {
3348                 bool lane_reversal =
3349                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3350
3351                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3352                                                crtc_state->lane_count,
3353                                                lane_reversal);
3354         }
3355
3356         intel_ddi_init_dp_buf_reg(encoder);
3357         if (!is_mst)
3358                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3359         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3360                                               true);
3361         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3362         intel_dp_start_link_train(intel_dp);
3363         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3364                 intel_dp_stop_link_train(intel_dp);
3365
3366         intel_ddi_enable_fec(encoder, crtc_state);
3367
3368         icl_phy_set_clock_gating(dig_port, true);
3369
3370         if (!is_mst)
3371                 intel_ddi_enable_pipe_clock(crtc_state);
3372
3373         intel_dsc_enable(encoder, crtc_state);
3374 }
3375
3376 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3377                                     const struct intel_crtc_state *crtc_state,
3378                                     const struct drm_connector_state *conn_state)
3379 {
3380         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3381
3382         if (INTEL_GEN(dev_priv) >= 12)
3383                 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3384         else
3385                 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3386 }
3387
3388 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3389                                       const struct intel_crtc_state *crtc_state,
3390                                       const struct drm_connector_state *conn_state)
3391 {
3392         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3393         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3394         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3395         enum port port = encoder->port;
3396         int level = intel_ddi_hdmi_level(dev_priv, port);
3397         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3398
3399         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3400         intel_ddi_clk_select(encoder, crtc_state);
3401
3402         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3403
3404         icl_program_mg_dp_mode(dig_port, crtc_state);
3405         icl_phy_set_clock_gating(dig_port, false);
3406
3407         if (INTEL_GEN(dev_priv) >= 11)
3408                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3409                                         level, INTEL_OUTPUT_HDMI);
3410         else if (IS_CANNONLAKE(dev_priv))
3411                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3412         else if (IS_GEN9_LP(dev_priv))
3413                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3414         else
3415                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3416
3417         icl_phy_set_clock_gating(dig_port, true);
3418
3419         if (IS_GEN9_BC(dev_priv))
3420                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3421
3422         intel_ddi_enable_pipe_clock(crtc_state);
3423
3424         intel_dig_port->set_infoframes(encoder,
3425                                        crtc_state->has_infoframe,
3426                                        crtc_state, conn_state);
3427 }
3428
3429 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3430                                  const struct intel_crtc_state *crtc_state,
3431                                  const struct drm_connector_state *conn_state)
3432 {
3433         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3434         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3435         enum pipe pipe = crtc->pipe;
3436
3437         /*
3438          * When called from DP MST code:
3439          * - conn_state will be NULL
3440          * - encoder will be the main encoder (ie. mst->primary)
3441          * - the main connector associated with this port
3442          *   won't be active or linked to a crtc
3443          * - crtc_state will be the state of the first stream to
3444          *   be activated on this port, and it may not be the same
3445          *   stream that will be deactivated last, but each stream
3446          *   should have a state that is identical when it comes to
3447          *   the DP link parameteres
3448          */
3449
3450         WARN_ON(crtc_state->has_pch_encoder);
3451
3452         if (INTEL_GEN(dev_priv) >= 11)
3453                 icl_map_plls_to_ports(encoder, crtc_state);
3454
3455         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3456
3457         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3458                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3459         } else {
3460                 struct intel_lspcon *lspcon =
3461                                 enc_to_intel_lspcon(&encoder->base);
3462
3463                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3464                 if (lspcon->active) {
3465                         struct intel_digital_port *dig_port =
3466                                         enc_to_dig_port(&encoder->base);
3467
3468                         dig_port->set_infoframes(encoder,
3469                                                  crtc_state->has_infoframe,
3470                                                  crtc_state, conn_state);
3471                 }
3472         }
3473 }
3474
3475 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3476                                   const struct intel_crtc_state *crtc_state)
3477 {
3478         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3479         enum port port = encoder->port;
3480         bool wait = false;
3481         u32 val;
3482
3483         val = I915_READ(DDI_BUF_CTL(port));
3484         if (val & DDI_BUF_CTL_ENABLE) {
3485                 val &= ~DDI_BUF_CTL_ENABLE;
3486                 I915_WRITE(DDI_BUF_CTL(port), val);
3487                 wait = true;
3488         }
3489
3490         if (intel_crtc_has_dp_encoder(crtc_state)) {
3491                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3492
3493                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3494                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3495                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3496                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3497         }
3498
3499         /* Disable FEC in DP Sink */
3500         intel_ddi_disable_fec_state(encoder, crtc_state);
3501
3502         if (wait)
3503                 intel_wait_ddi_buf_idle(dev_priv, port);
3504 }
3505
3506 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3507                                       const struct intel_crtc_state *old_crtc_state,
3508                                       const struct drm_connector_state *old_conn_state)
3509 {
3510         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3511         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3512         struct intel_dp *intel_dp = &dig_port->dp;
3513         bool is_mst = intel_crtc_has_type(old_crtc_state,
3514                                           INTEL_OUTPUT_DP_MST);
3515         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3516
3517         if (!is_mst) {
3518                 intel_ddi_disable_pipe_clock(old_crtc_state);
3519                 /*
3520                  * Power down sink before disabling the port, otherwise we end
3521                  * up getting interrupts from the sink on detecting link loss.
3522                  */
3523                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3524         }
3525
3526         intel_disable_ddi_buf(encoder, old_crtc_state);
3527
3528         intel_edp_panel_vdd_on(intel_dp);
3529         intel_edp_panel_off(intel_dp);
3530
3531         if (!intel_phy_is_tc(dev_priv, phy) ||
3532             dig_port->tc_mode != TC_PORT_TBT_ALT)
3533                 intel_display_power_put_unchecked(dev_priv,
3534                                                   dig_port->ddi_io_power_domain);
3535
3536         intel_ddi_clk_disable(encoder);
3537 }
3538
3539 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3540                                         const struct intel_crtc_state *old_crtc_state,
3541                                         const struct drm_connector_state *old_conn_state)
3542 {
3543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3544         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3545         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3546
3547         dig_port->set_infoframes(encoder, false,
3548                                  old_crtc_state, old_conn_state);
3549
3550         intel_ddi_disable_pipe_clock(old_crtc_state);
3551
3552         intel_disable_ddi_buf(encoder, old_crtc_state);
3553
3554         intel_display_power_put_unchecked(dev_priv,
3555                                           dig_port->ddi_io_power_domain);
3556
3557         intel_ddi_clk_disable(encoder);
3558
3559         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3560 }
3561
3562 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3563                                    const struct intel_crtc_state *old_crtc_state,
3564                                    const struct drm_connector_state *old_conn_state)
3565 {
3566         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3567
3568         /*
3569          * When called from DP MST code:
3570          * - old_conn_state will be NULL
3571          * - encoder will be the main encoder (ie. mst->primary)
3572          * - the main connector associated with this port
3573          *   won't be active or linked to a crtc
3574          * - old_crtc_state will be the state of the last stream to
3575          *   be deactivated on this port, and it may not be the same
3576          *   stream that was activated last, but each stream
3577          *   should have a state that is identical when it comes to
3578          *   the DP link parameteres
3579          */
3580
3581         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3582                 intel_ddi_post_disable_hdmi(encoder,
3583                                             old_crtc_state, old_conn_state);
3584         else
3585                 intel_ddi_post_disable_dp(encoder,
3586                                           old_crtc_state, old_conn_state);
3587
3588         if (INTEL_GEN(dev_priv) >= 11)
3589                 icl_unmap_plls_to_ports(encoder);
3590 }
3591
3592 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3593                                 const struct intel_crtc_state *old_crtc_state,
3594                                 const struct drm_connector_state *old_conn_state)
3595 {
3596         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3597         u32 val;
3598
3599         /*
3600          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3601          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3602          * step 13 is the correct place for it. Step 18 is where it was
3603          * originally before the BUN.
3604          */
3605         val = I915_READ(FDI_RX_CTL(PIPE_A));
3606         val &= ~FDI_RX_ENABLE;
3607         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3608
3609         intel_disable_ddi_buf(encoder, old_crtc_state);
3610         intel_ddi_clk_disable(encoder);
3611
3612         val = I915_READ(FDI_RX_MISC(PIPE_A));
3613         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3614         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3615         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3616
3617         val = I915_READ(FDI_RX_CTL(PIPE_A));
3618         val &= ~FDI_PCDCLK;
3619         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3620
3621         val = I915_READ(FDI_RX_CTL(PIPE_A));
3622         val &= ~FDI_RX_PLL_ENABLE;
3623         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3624 }
3625
3626 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3627                                 const struct intel_crtc_state *crtc_state,
3628                                 const struct drm_connector_state *conn_state)
3629 {
3630         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3631         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3632         enum port port = encoder->port;
3633
3634         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3635                 intel_dp_stop_link_train(intel_dp);
3636
3637         intel_edp_backlight_on(crtc_state, conn_state);
3638         intel_psr_enable(intel_dp, crtc_state);
3639         intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
3640         intel_edp_drrs_enable(intel_dp, crtc_state);
3641
3642         if (crtc_state->has_audio)
3643                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3644 }
3645
3646 static i915_reg_t
3647 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3648                                enum port port)
3649 {
3650         static const i915_reg_t regs[] = {
3651                 [PORT_A] = CHICKEN_TRANS_EDP,
3652                 [PORT_B] = CHICKEN_TRANS_A,
3653                 [PORT_C] = CHICKEN_TRANS_B,
3654                 [PORT_D] = CHICKEN_TRANS_C,
3655                 [PORT_E] = CHICKEN_TRANS_A,
3656         };
3657
3658         WARN_ON(INTEL_GEN(dev_priv) < 9);
3659
3660         if (WARN_ON(port < PORT_A || port > PORT_E))
3661                 port = PORT_A;
3662
3663         return regs[port];
3664 }
3665
3666 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3667                                   const struct intel_crtc_state *crtc_state,
3668                                   const struct drm_connector_state *conn_state)
3669 {
3670         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3671         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3672         struct drm_connector *connector = conn_state->connector;
3673         enum port port = encoder->port;
3674
3675         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3676                                                crtc_state->hdmi_high_tmds_clock_ratio,
3677                                                crtc_state->hdmi_scrambling))
3678                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3679                           connector->base.id, connector->name);
3680
3681         /* Display WA #1143: skl,kbl,cfl */
3682         if (IS_GEN9_BC(dev_priv)) {
3683                 /*
3684                  * For some reason these chicken bits have been
3685                  * stuffed into a transcoder register, event though
3686                  * the bits affect a specific DDI port rather than
3687                  * a specific transcoder.
3688                  */
3689                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3690                 u32 val;
3691
3692                 val = I915_READ(reg);
3693
3694                 if (port == PORT_E)
3695                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3696                                 DDIE_TRAINING_OVERRIDE_VALUE;
3697                 else
3698                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3699                                 DDI_TRAINING_OVERRIDE_VALUE;
3700
3701                 I915_WRITE(reg, val);
3702                 POSTING_READ(reg);
3703
3704                 udelay(1);
3705
3706                 if (port == PORT_E)
3707                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3708                                  DDIE_TRAINING_OVERRIDE_VALUE);
3709                 else
3710                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3711                                  DDI_TRAINING_OVERRIDE_VALUE);
3712
3713                 I915_WRITE(reg, val);
3714         }
3715
3716         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3717          * are ignored so nothing special needs to be done besides
3718          * enabling the port.
3719          */
3720         I915_WRITE(DDI_BUF_CTL(port),
3721                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3722
3723         if (crtc_state->has_audio)
3724                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3725 }
3726
3727 static void intel_enable_ddi(struct intel_encoder *encoder,
3728                              const struct intel_crtc_state *crtc_state,
3729                              const struct drm_connector_state *conn_state)
3730 {
3731         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3732                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3733         else
3734                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3735
3736         /* Enable hdcp if it's desired */
3737         if (conn_state->content_protection ==
3738             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3739                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3740                                   (u8)conn_state->hdcp_content_type);
3741 }
3742
3743 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3744                                  const struct intel_crtc_state *old_crtc_state,
3745                                  const struct drm_connector_state *old_conn_state)
3746 {
3747         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3748
3749         intel_dp->link_trained = false;
3750
3751         if (old_crtc_state->has_audio)
3752                 intel_audio_codec_disable(encoder,
3753                                           old_crtc_state, old_conn_state);
3754
3755         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3756         intel_psr_disable(intel_dp, old_crtc_state);
3757         intel_edp_backlight_off(old_conn_state);
3758         /* Disable the decompression in DP Sink */
3759         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3760                                               false);
3761 }
3762
3763 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3764                                    const struct intel_crtc_state *old_crtc_state,
3765                                    const struct drm_connector_state *old_conn_state)
3766 {
3767         struct drm_connector *connector = old_conn_state->connector;
3768
3769         if (old_crtc_state->has_audio)
3770                 intel_audio_codec_disable(encoder,
3771                                           old_crtc_state, old_conn_state);
3772
3773         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3774                                                false, false))
3775                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3776                               connector->base.id, connector->name);
3777 }
3778
3779 static void intel_disable_ddi(struct intel_encoder *encoder,
3780                               const struct intel_crtc_state *old_crtc_state,
3781                               const struct drm_connector_state *old_conn_state)
3782 {
3783         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3784
3785         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3786                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3787         else
3788                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3789 }
3790
3791 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3792                                      const struct intel_crtc_state *crtc_state,
3793                                      const struct drm_connector_state *conn_state)
3794 {
3795         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3796
3797         intel_ddi_set_pipe_settings(crtc_state);
3798
3799         intel_psr_update(intel_dp, crtc_state);
3800         intel_edp_drrs_enable(intel_dp, crtc_state);
3801
3802         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3803 }
3804
3805 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3806                                   const struct intel_crtc_state *crtc_state,
3807                                   const struct drm_connector_state *conn_state)
3808 {
3809         struct intel_connector *connector =
3810                                 to_intel_connector(conn_state->connector);
3811         struct intel_hdcp *hdcp = &connector->hdcp;
3812         bool content_protection_type_changed =
3813                         (conn_state->hdcp_content_type != hdcp->content_type &&
3814                          conn_state->content_protection !=
3815                          DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
3816
3817         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3818                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3819
3820         /*
3821          * During the HDCP encryption session if Type change is requested,
3822          * disable the HDCP and reenable it with new TYPE value.
3823          */
3824         if (conn_state->content_protection ==
3825             DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
3826             content_protection_type_changed)
3827                 intel_hdcp_disable(connector);
3828
3829         /*
3830          * Mark the hdcp state as DESIRED after the hdcp disable of type
3831          * change procedure.
3832          */
3833         if (content_protection_type_changed) {
3834                 mutex_lock(&hdcp->mutex);
3835                 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3836                 schedule_work(&hdcp->prop_work);
3837                 mutex_unlock(&hdcp->mutex);
3838         }
3839
3840         if (conn_state->content_protection ==
3841             DRM_MODE_CONTENT_PROTECTION_DESIRED ||
3842             content_protection_type_changed)
3843                 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
3844 }
3845
3846 static void
3847 intel_ddi_update_prepare(struct intel_atomic_state *state,
3848                          struct intel_encoder *encoder,
3849                          struct intel_crtc *crtc)
3850 {
3851         struct intel_crtc_state *crtc_state =
3852                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3853         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3854
3855         WARN_ON(crtc && crtc->active);
3856
3857         intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3858         if (crtc_state && crtc_state->base.active)
3859                 intel_update_active_dpll(state, crtc, encoder);
3860 }
3861
3862 static void
3863 intel_ddi_update_complete(struct intel_atomic_state *state,
3864                           struct intel_encoder *encoder,
3865                           struct intel_crtc *crtc)
3866 {
3867         intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3868 }
3869
3870 static void
3871 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3872                          const struct intel_crtc_state *crtc_state,
3873                          const struct drm_connector_state *conn_state)
3874 {
3875         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3876         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3877         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3878         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3879
3880         if (is_tc_port)
3881                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3882
3883         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3884                 intel_display_power_get(dev_priv,
3885                                         intel_ddi_main_link_aux_domain(dig_port));
3886
3887         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3888                 /*
3889                  * Program the lane count for static/dynamic connections on
3890                  * Type-C ports.  Skip this step for TBT.
3891                  */
3892                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3893         else if (IS_GEN9_LP(dev_priv))
3894                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3895                                                 crtc_state->lane_lat_optim_mask);
3896 }
3897
3898 static void
3899 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3900                            const struct intel_crtc_state *crtc_state,
3901                            const struct drm_connector_state *conn_state)
3902 {
3903         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3904         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3905         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3906         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3907
3908         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3909                 intel_display_power_put_unchecked(dev_priv,
3910                                                   intel_ddi_main_link_aux_domain(dig_port));
3911
3912         if (is_tc_port)
3913                 intel_tc_port_put_link(dig_port);
3914 }
3915
3916 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3917 {
3918         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3919         struct drm_i915_private *dev_priv =
3920                 to_i915(intel_dig_port->base.base.dev);
3921         enum port port = intel_dig_port->base.port;
3922         u32 val;
3923         bool wait = false;
3924
3925         if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
3926                 val = I915_READ(DDI_BUF_CTL(port));
3927                 if (val & DDI_BUF_CTL_ENABLE) {
3928                         val &= ~DDI_BUF_CTL_ENABLE;
3929                         I915_WRITE(DDI_BUF_CTL(port), val);
3930                         wait = true;
3931                 }
3932
3933                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3934                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3935                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3936                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3937                 POSTING_READ(intel_dp->regs.dp_tp_ctl);
3938
3939                 if (wait)
3940                         intel_wait_ddi_buf_idle(dev_priv, port);
3941         }
3942
3943         val = DP_TP_CTL_ENABLE |
3944               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3945         if (intel_dp->link_mst)
3946                 val |= DP_TP_CTL_MODE_MST;
3947         else {
3948                 val |= DP_TP_CTL_MODE_SST;
3949                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3950                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3951         }
3952         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3953         POSTING_READ(intel_dp->regs.dp_tp_ctl);
3954
3955         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3956         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3957         POSTING_READ(DDI_BUF_CTL(port));
3958
3959         udelay(600);
3960 }
3961
3962 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3963                                        enum transcoder cpu_transcoder)
3964 {
3965         if (cpu_transcoder == TRANSCODER_EDP)
3966                 return false;
3967
3968         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3969                 return false;
3970
3971         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3972                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3973 }
3974
3975 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3976                                          struct intel_crtc_state *crtc_state)
3977 {
3978         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3979                 crtc_state->min_voltage_level = 1;
3980         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3981                 crtc_state->min_voltage_level = 2;
3982 }
3983
3984 void intel_ddi_get_config(struct intel_encoder *encoder,
3985                           struct intel_crtc_state *pipe_config)
3986 {
3987         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3988         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3989         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3990         u32 temp, flags = 0;
3991
3992         /* XXX: DSI transcoder paranoia */
3993         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3994                 return;
3995
3996         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3997         if (temp & TRANS_DDI_PHSYNC)
3998                 flags |= DRM_MODE_FLAG_PHSYNC;
3999         else
4000                 flags |= DRM_MODE_FLAG_NHSYNC;
4001         if (temp & TRANS_DDI_PVSYNC)
4002                 flags |= DRM_MODE_FLAG_PVSYNC;
4003         else
4004                 flags |= DRM_MODE_FLAG_NVSYNC;
4005
4006         pipe_config->base.adjusted_mode.flags |= flags;
4007
4008         switch (temp & TRANS_DDI_BPC_MASK) {
4009         case TRANS_DDI_BPC_6:
4010                 pipe_config->pipe_bpp = 18;
4011                 break;
4012         case TRANS_DDI_BPC_8:
4013                 pipe_config->pipe_bpp = 24;
4014                 break;
4015         case TRANS_DDI_BPC_10:
4016                 pipe_config->pipe_bpp = 30;
4017                 break;
4018         case TRANS_DDI_BPC_12:
4019                 pipe_config->pipe_bpp = 36;
4020                 break;
4021         default:
4022                 break;
4023         }
4024
4025         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4026         case TRANS_DDI_MODE_SELECT_HDMI:
4027                 pipe_config->has_hdmi_sink = true;
4028
4029                 pipe_config->infoframes.enable |=
4030                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4031
4032                 if (pipe_config->infoframes.enable)
4033                         pipe_config->has_infoframe = true;
4034
4035                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4036                         pipe_config->hdmi_scrambling = true;
4037                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4038                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4039                 /* fall through */
4040         case TRANS_DDI_MODE_SELECT_DVI:
4041                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4042                 pipe_config->lane_count = 4;
4043                 break;
4044         case TRANS_DDI_MODE_SELECT_FDI:
4045                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4046                 break;
4047         case TRANS_DDI_MODE_SELECT_DP_SST:
4048                 if (encoder->type == INTEL_OUTPUT_EDP)
4049                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4050                 else
4051                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4052                 pipe_config->lane_count =
4053                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4054                 intel_dp_get_m_n(intel_crtc, pipe_config);
4055
4056                 if (INTEL_GEN(dev_priv) >= 11) {
4057                         i915_reg_t dp_tp_ctl;
4058
4059                         if (IS_GEN(dev_priv, 11))
4060                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4061                         else
4062                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4063
4064                         pipe_config->fec_enable =
4065                                 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4066
4067                         DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
4068                                       encoder->base.base.id, encoder->base.name,
4069                                       pipe_config->fec_enable);
4070                 }
4071
4072                 break;
4073         case TRANS_DDI_MODE_SELECT_DP_MST:
4074                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4075                 pipe_config->lane_count =
4076                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4077                 intel_dp_get_m_n(intel_crtc, pipe_config);
4078                 break;
4079         default:
4080                 break;
4081         }
4082
4083         pipe_config->has_audio =
4084                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4085
4086         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4087             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4088                 /*
4089                  * This is a big fat ugly hack.
4090                  *
4091                  * Some machines in UEFI boot mode provide us a VBT that has 18
4092                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4093                  * unknown we fail to light up. Yet the same BIOS boots up with
4094                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4095                  * max, not what it tells us to use.
4096                  *
4097                  * Note: This will still be broken if the eDP panel is not lit
4098                  * up by the BIOS, and thus we can't get the mode at module
4099                  * load.
4100                  */
4101                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4102                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4103                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4104         }
4105
4106         intel_ddi_clock_get(encoder, pipe_config);
4107
4108         if (IS_GEN9_LP(dev_priv))
4109                 pipe_config->lane_lat_optim_mask =
4110                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4111
4112         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4113
4114         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4115
4116         intel_read_infoframe(encoder, pipe_config,
4117                              HDMI_INFOFRAME_TYPE_AVI,
4118                              &pipe_config->infoframes.avi);
4119         intel_read_infoframe(encoder, pipe_config,
4120                              HDMI_INFOFRAME_TYPE_SPD,
4121                              &pipe_config->infoframes.spd);
4122         intel_read_infoframe(encoder, pipe_config,
4123                              HDMI_INFOFRAME_TYPE_VENDOR,
4124                              &pipe_config->infoframes.hdmi);
4125         intel_read_infoframe(encoder, pipe_config,
4126                              HDMI_INFOFRAME_TYPE_DRM,
4127                              &pipe_config->infoframes.drm);
4128 }
4129
4130 static enum intel_output_type
4131 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4132                               struct intel_crtc_state *crtc_state,
4133                               struct drm_connector_state *conn_state)
4134 {
4135         switch (conn_state->connector->connector_type) {
4136         case DRM_MODE_CONNECTOR_HDMIA:
4137                 return INTEL_OUTPUT_HDMI;
4138         case DRM_MODE_CONNECTOR_eDP:
4139                 return INTEL_OUTPUT_EDP;
4140         case DRM_MODE_CONNECTOR_DisplayPort:
4141                 return INTEL_OUTPUT_DP;
4142         default:
4143                 MISSING_CASE(conn_state->connector->connector_type);
4144                 return INTEL_OUTPUT_UNUSED;
4145         }
4146 }
4147
4148 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4149                                     struct intel_crtc_state *pipe_config,
4150                                     struct drm_connector_state *conn_state)
4151 {
4152         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
4153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4154         enum port port = encoder->port;
4155         int ret;
4156
4157         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
4158                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4159
4160         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
4161                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4162         else
4163                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4164         if (ret)
4165                 return ret;
4166
4167         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4168             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4169                 pipe_config->pch_pfit.force_thru =
4170                         pipe_config->pch_pfit.enabled ||
4171                         pipe_config->crc_enabled;
4172
4173         if (IS_GEN9_LP(dev_priv))
4174                 pipe_config->lane_lat_optim_mask =
4175                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4176
4177         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4178
4179         return 0;
4180 }
4181
4182 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4183 {
4184         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4185
4186         intel_dp_encoder_flush_work(encoder);
4187
4188         drm_encoder_cleanup(encoder);
4189         kfree(dig_port);
4190 }
4191
4192 static const struct drm_encoder_funcs intel_ddi_funcs = {
4193         .reset = intel_dp_encoder_reset,
4194         .destroy = intel_ddi_encoder_destroy,
4195 };
4196
4197 static struct intel_connector *
4198 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4199 {
4200         struct intel_connector *connector;
4201         enum port port = intel_dig_port->base.port;
4202
4203         connector = intel_connector_alloc();
4204         if (!connector)
4205                 return NULL;
4206
4207         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4208         intel_dig_port->dp.prepare_link_retrain =
4209                 intel_ddi_prepare_link_retrain;
4210
4211         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4212                 kfree(connector);
4213                 return NULL;
4214         }
4215
4216         return connector;
4217 }
4218
4219 static int modeset_pipe(struct drm_crtc *crtc,
4220                         struct drm_modeset_acquire_ctx *ctx)
4221 {
4222         struct drm_atomic_state *state;
4223         struct drm_crtc_state *crtc_state;
4224         int ret;
4225
4226         state = drm_atomic_state_alloc(crtc->dev);
4227         if (!state)
4228                 return -ENOMEM;
4229
4230         state->acquire_ctx = ctx;
4231
4232         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4233         if (IS_ERR(crtc_state)) {
4234                 ret = PTR_ERR(crtc_state);
4235                 goto out;
4236         }
4237
4238         crtc_state->connectors_changed = true;
4239
4240         ret = drm_atomic_commit(state);
4241 out:
4242         drm_atomic_state_put(state);
4243
4244         return ret;
4245 }
4246
4247 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4248                                  struct drm_modeset_acquire_ctx *ctx)
4249 {
4250         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4251         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4252         struct intel_connector *connector = hdmi->attached_connector;
4253         struct i2c_adapter *adapter =
4254                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4255         struct drm_connector_state *conn_state;
4256         struct intel_crtc_state *crtc_state;
4257         struct intel_crtc *crtc;
4258         u8 config;
4259         int ret;
4260
4261         if (!connector || connector->base.status != connector_status_connected)
4262                 return 0;
4263
4264         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4265                                ctx);
4266         if (ret)
4267                 return ret;
4268
4269         conn_state = connector->base.state;
4270
4271         crtc = to_intel_crtc(conn_state->crtc);
4272         if (!crtc)
4273                 return 0;
4274
4275         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4276         if (ret)
4277                 return ret;
4278
4279         crtc_state = to_intel_crtc_state(crtc->base.state);
4280
4281         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4282
4283         if (!crtc_state->base.active)
4284                 return 0;
4285
4286         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4287             !crtc_state->hdmi_scrambling)
4288                 return 0;
4289
4290         if (conn_state->commit &&
4291             !try_wait_for_completion(&conn_state->commit->hw_done))
4292                 return 0;
4293
4294         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4295         if (ret < 0) {
4296                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4297                 return 0;
4298         }
4299
4300         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4301             crtc_state->hdmi_high_tmds_clock_ratio &&
4302             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4303             crtc_state->hdmi_scrambling)
4304                 return 0;
4305
4306         /*
4307          * HDMI 2.0 says that one should not send scrambled data
4308          * prior to configuring the sink scrambling, and that
4309          * TMDS clock/data transmission should be suspended when
4310          * changing the TMDS clock rate in the sink. So let's
4311          * just do a full modeset here, even though some sinks
4312          * would be perfectly happy if were to just reconfigure
4313          * the SCDC settings on the fly.
4314          */
4315         return modeset_pipe(&crtc->base, ctx);
4316 }
4317
4318 static enum intel_hotplug_state
4319 intel_ddi_hotplug(struct intel_encoder *encoder,
4320                   struct intel_connector *connector,
4321                   bool irq_received)
4322 {
4323         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4324         struct drm_modeset_acquire_ctx ctx;
4325         enum intel_hotplug_state state;
4326         int ret;
4327
4328         state = intel_encoder_hotplug(encoder, connector, irq_received);
4329
4330         drm_modeset_acquire_init(&ctx, 0);
4331
4332         for (;;) {
4333                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4334                         ret = intel_hdmi_reset_link(encoder, &ctx);
4335                 else
4336                         ret = intel_dp_retrain_link(encoder, &ctx);
4337
4338                 if (ret == -EDEADLK) {
4339                         drm_modeset_backoff(&ctx);
4340                         continue;
4341                 }
4342
4343                 break;
4344         }
4345
4346         drm_modeset_drop_locks(&ctx);
4347         drm_modeset_acquire_fini(&ctx);
4348         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4349
4350         /*
4351          * Unpowered type-c dongles can take some time to boot and be
4352          * responsible, so here giving some time to those dongles to power up
4353          * and then retrying the probe.
4354          *
4355          * On many platforms the HDMI live state signal is known to be
4356          * unreliable, so we can't use it to detect if a sink is connected or
4357          * not. Instead we detect if it's connected based on whether we can
4358          * read the EDID or not. That in turn has a problem during disconnect,
4359          * since the HPD interrupt may be raised before the DDC lines get
4360          * disconnected (due to how the required length of DDC vs. HPD
4361          * connector pins are specified) and so we'll still be able to get a
4362          * valid EDID. To solve this schedule another detection cycle if this
4363          * time around we didn't detect any change in the sink's connection
4364          * status.
4365          */
4366         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4367             !dig_port->dp.is_mst)
4368                 state = INTEL_HOTPLUG_RETRY;
4369
4370         return state;
4371 }
4372
4373 static struct intel_connector *
4374 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4375 {
4376         struct intel_connector *connector;
4377         enum port port = intel_dig_port->base.port;
4378
4379         connector = intel_connector_alloc();
4380         if (!connector)
4381                 return NULL;
4382
4383         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4384         intel_hdmi_init_connector(intel_dig_port, connector);
4385
4386         return connector;
4387 }
4388
4389 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4390 {
4391         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4392
4393         if (dport->base.port != PORT_A)
4394                 return false;
4395
4396         if (dport->saved_port_bits & DDI_A_4_LANES)
4397                 return false;
4398
4399         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4400          *                     supported configuration
4401          */
4402         if (IS_GEN9_LP(dev_priv))
4403                 return true;
4404
4405         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4406          *             one who does also have a full A/E split called
4407          *             DDI_F what makes DDI_E useless. However for this
4408          *             case let's trust VBT info.
4409          */
4410         if (IS_CANNONLAKE(dev_priv) &&
4411             !intel_bios_is_port_present(dev_priv, PORT_E))
4412                 return true;
4413
4414         return false;
4415 }
4416
4417 static int
4418 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4419 {
4420         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4421         enum port port = intel_dport->base.port;
4422         int max_lanes = 4;
4423
4424         if (INTEL_GEN(dev_priv) >= 11)
4425                 return max_lanes;
4426
4427         if (port == PORT_A || port == PORT_E) {
4428                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4429                         max_lanes = port == PORT_A ? 4 : 0;
4430                 else
4431                         /* Both A and E share 2 lanes */
4432                         max_lanes = 2;
4433         }
4434
4435         /*
4436          * Some BIOS might fail to set this bit on port A if eDP
4437          * wasn't lit up at boot.  Force this bit set when needed
4438          * so we use the proper lane count for our calculations.
4439          */
4440         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4441                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4442                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4443                 max_lanes = 4;
4444         }
4445
4446         return max_lanes;
4447 }
4448
4449 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4450 {
4451         struct ddi_vbt_port_info *port_info =
4452                 &dev_priv->vbt.ddi_port_info[port];
4453         struct intel_digital_port *intel_dig_port;
4454         struct intel_encoder *intel_encoder;
4455         struct drm_encoder *encoder;
4456         bool init_hdmi, init_dp, init_lspcon = false;
4457         enum pipe pipe;
4458         enum phy phy = intel_port_to_phy(dev_priv, port);
4459
4460         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4461         init_dp = port_info->supports_dp;
4462
4463         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4464                 /*
4465                  * Lspcon device needs to be driven with DP connector
4466                  * with special detection sequence. So make sure DP
4467                  * is initialized before lspcon.
4468                  */
4469                 init_dp = true;
4470                 init_lspcon = true;
4471                 init_hdmi = false;
4472                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4473         }
4474
4475         if (!init_dp && !init_hdmi) {
4476                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4477                               port_name(port));
4478                 return;
4479         }
4480
4481         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4482         if (!intel_dig_port)
4483                 return;
4484
4485         intel_encoder = &intel_dig_port->base;
4486         encoder = &intel_encoder->base;
4487
4488         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4489                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4490
4491         intel_encoder->hotplug = intel_ddi_hotplug;
4492         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4493         intel_encoder->compute_config = intel_ddi_compute_config;
4494         intel_encoder->enable = intel_enable_ddi;
4495         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4496         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4497         intel_encoder->pre_enable = intel_ddi_pre_enable;
4498         intel_encoder->disable = intel_disable_ddi;
4499         intel_encoder->post_disable = intel_ddi_post_disable;
4500         intel_encoder->update_pipe = intel_ddi_update_pipe;
4501         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4502         intel_encoder->get_config = intel_ddi_get_config;
4503         intel_encoder->suspend = intel_dp_encoder_suspend;
4504         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4505         intel_encoder->type = INTEL_OUTPUT_DDI;
4506         intel_encoder->power_domain = intel_port_to_power_domain(port);
4507         intel_encoder->port = port;
4508         intel_encoder->cloneable = 0;
4509         for_each_pipe(dev_priv, pipe)
4510                 intel_encoder->crtc_mask |= BIT(pipe);
4511
4512         if (INTEL_GEN(dev_priv) >= 11)
4513                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4514                         DDI_BUF_PORT_REVERSAL;
4515         else
4516                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4517                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4518         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4519         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4520         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4521
4522         if (intel_phy_is_tc(dev_priv, phy)) {
4523                 bool is_legacy = !port_info->supports_typec_usb &&
4524                                  !port_info->supports_tbt;
4525
4526                 intel_tc_port_init(intel_dig_port, is_legacy);
4527
4528                 intel_encoder->update_prepare = intel_ddi_update_prepare;
4529                 intel_encoder->update_complete = intel_ddi_update_complete;
4530         }
4531
4532         switch (port) {
4533         case PORT_A:
4534                 intel_dig_port->ddi_io_power_domain =
4535                         POWER_DOMAIN_PORT_DDI_A_IO;
4536                 break;
4537         case PORT_B:
4538                 intel_dig_port->ddi_io_power_domain =
4539                         POWER_DOMAIN_PORT_DDI_B_IO;
4540                 break;
4541         case PORT_C:
4542                 intel_dig_port->ddi_io_power_domain =
4543                         POWER_DOMAIN_PORT_DDI_C_IO;
4544                 break;
4545         case PORT_D:
4546                 intel_dig_port->ddi_io_power_domain =
4547                         POWER_DOMAIN_PORT_DDI_D_IO;
4548                 break;
4549         case PORT_E:
4550                 intel_dig_port->ddi_io_power_domain =
4551                         POWER_DOMAIN_PORT_DDI_E_IO;
4552                 break;
4553         case PORT_F:
4554                 intel_dig_port->ddi_io_power_domain =
4555                         POWER_DOMAIN_PORT_DDI_F_IO;
4556                 break;
4557         case PORT_G:
4558                 intel_dig_port->ddi_io_power_domain =
4559                         POWER_DOMAIN_PORT_DDI_G_IO;
4560                 break;
4561         case PORT_H:
4562                 intel_dig_port->ddi_io_power_domain =
4563                         POWER_DOMAIN_PORT_DDI_H_IO;
4564                 break;
4565         case PORT_I:
4566                 intel_dig_port->ddi_io_power_domain =
4567                         POWER_DOMAIN_PORT_DDI_I_IO;
4568                 break;
4569         default:
4570                 MISSING_CASE(port);
4571         }
4572
4573         if (init_dp) {
4574                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4575                         goto err;
4576
4577                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4578         }
4579
4580         /* In theory we don't need the encoder->type check, but leave it just in
4581          * case we have some really bad VBTs... */
4582         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4583                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4584                         goto err;
4585         }
4586
4587         if (init_lspcon) {
4588                 if (lspcon_init(intel_dig_port))
4589                         /* TODO: handle hdmi info frame part */
4590                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4591                                 port_name(port));
4592                 else
4593                         /*
4594                          * LSPCON init faied, but DP init was success, so
4595                          * lets try to drive as DP++ port.
4596                          */
4597                         DRM_ERROR("LSPCON init failed on port %c\n",
4598                                 port_name(port));
4599         }
4600
4601         intel_infoframe_init(intel_dig_port);
4602
4603         return;
4604
4605 err:
4606         drm_encoder_cleanup(encoder);
4607         kfree(intel_dig_port);
4608 }