drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_link_training.h"
  38 #include "intel_dpio_phy.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_sprite.h"
  49 #include "intel_tc.h"
  50 #include "intel_vdsc.h"
  51
  52 struct ddi_buf_trans {
  53         u32 trans1;     /* balance leg enable, de-emph level */
  54         u32 trans2;     /* vref sel, vswing */
  55         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  56 };
  57
  58 static const u8 index_to_dp_signal_levels[] = {
  59         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  60         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  61         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  62         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  63         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  64         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  65         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  66         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  67         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  68         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69 };
  70
  71 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  72  * them for both DP and FDI transports, allowing those ports to
  73  * automatically adapt to HDMI connections as well
  74  */
  75 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  76         { 0x00FFFFFF, 0x0006000E, 0x0 },
  77         { 0x00D75FFF, 0x0005000A, 0x0 },
  78         { 0x00C30FFF, 0x00040006, 0x0 },
  79         { 0x80AAAFFF, 0x000B0000, 0x0 },
  80         { 0x00FFFFFF, 0x0005000A, 0x0 },
  81         { 0x00D75FFF, 0x000C0004, 0x0 },
  82         { 0x80C30FFF, 0x000B0000, 0x0 },
  83         { 0x00FFFFFF, 0x00040006, 0x0 },
  84         { 0x80D75FFF, 0x000B0000, 0x0 },
  85 };
  86
  87 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  88         { 0x00FFFFFF, 0x0007000E, 0x0 },
  89         { 0x00D75FFF, 0x000F000A, 0x0 },
  90         { 0x00C30FFF, 0x00060006, 0x0 },
  91         { 0x00AAAFFF, 0x001E0000, 0x0 },
  92         { 0x00FFFFFF, 0x000F000A, 0x0 },
  93         { 0x00D75FFF, 0x00160004, 0x0 },
  94         { 0x00C30FFF, 0x001E0000, 0x0 },
  95         { 0x00FFFFFF, 0x00060006, 0x0 },
  96         { 0x00D75FFF, 0x001E0000, 0x0 },
  97 };
  98
  99 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 100                                         /* Idx  NT mV d T mV d  db      */
 101         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 102         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 103         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 104         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 105         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 106         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 107         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 108         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 109         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 110         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 111         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 112         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 113 };
 114
 115 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 116         { 0x00FFFFFF, 0x00000012, 0x0 },
 117         { 0x00EBAFFF, 0x00020011, 0x0 },
 118         { 0x00C71FFF, 0x0006000F, 0x0 },
 119         { 0x00AAAFFF, 0x000E000A, 0x0 },
 120         { 0x00FFFFFF, 0x00020011, 0x0 },
 121         { 0x00DB6FFF, 0x0005000F, 0x0 },
 122         { 0x00BEEFFF, 0x000A000C, 0x0 },
 123         { 0x00FFFFFF, 0x0005000F, 0x0 },
 124         { 0x00DB6FFF, 0x000A000C, 0x0 },
 125 };
 126
 127 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 128         { 0x00FFFFFF, 0x0007000E, 0x0 },
 129         { 0x00D75FFF, 0x000E000A, 0x0 },
 130         { 0x00BEFFFF, 0x00140006, 0x0 },
 131         { 0x80B2CFFF, 0x001B0002, 0x0 },
 132         { 0x00FFFFFF, 0x000E000A, 0x0 },
 133         { 0x00DB6FFF, 0x00160005, 0x0 },
 134         { 0x80C71FFF, 0x001A0002, 0x0 },
 135         { 0x00F7DFFF, 0x00180004, 0x0 },
 136         { 0x80D75FFF, 0x001B0002, 0x0 },
 137 };
 138
 139 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 140         { 0x00FFFFFF, 0x0001000E, 0x0 },
 141         { 0x00D75FFF, 0x0004000A, 0x0 },
 142         { 0x00C30FFF, 0x00070006, 0x0 },
 143         { 0x00AAAFFF, 0x000C0000, 0x0 },
 144         { 0x00FFFFFF, 0x0004000A, 0x0 },
 145         { 0x00D75FFF, 0x00090004, 0x0 },
 146         { 0x00C30FFF, 0x000C0000, 0x0 },
 147         { 0x00FFFFFF, 0x00070006, 0x0 },
 148         { 0x00D75FFF, 0x000C0000, 0x0 },
 149 };
 150
 151 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 152                                         /* Idx  NT mV d T mV df db      */
 153         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 154         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 155         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 156         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 157         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 158         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 159         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 160         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 161         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 162         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 163 };
 164
 165 /* Skylake H and S */
 166 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 167         { 0x00002016, 0x000000A0, 0x0 },
 168         { 0x00005012, 0x0000009B, 0x0 },
 169         { 0x00007011, 0x00000088, 0x0 },
 170         { 0x80009010, 0x000000C0, 0x1 },
 171         { 0x00002016, 0x0000009B, 0x0 },
 172         { 0x00005012, 0x00000088, 0x0 },
 173         { 0x80007011, 0x000000C0, 0x1 },
 174         { 0x00002016, 0x000000DF, 0x0 },
 175         { 0x80005012, 0x000000C0, 0x1 },
 176 };
 177
 178 /* Skylake U */
 179 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 180         { 0x0000201B, 0x000000A2, 0x0 },
 181         { 0x00005012, 0x00000088, 0x0 },
 182         { 0x80007011, 0x000000CD, 0x1 },
 183         { 0x80009010, 0x000000C0, 0x1 },
 184         { 0x0000201B, 0x0000009D, 0x0 },
 185         { 0x80005012, 0x000000C0, 0x1 },
 186         { 0x80007011, 0x000000C0, 0x1 },
 187         { 0x00002016, 0x00000088, 0x0 },
 188         { 0x80005012, 0x000000C0, 0x1 },
 189 };
 190
 191 /* Skylake Y */
 192 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 193         { 0x00000018, 0x000000A2, 0x0 },
 194         { 0x00005012, 0x00000088, 0x0 },
 195         { 0x80007011, 0x000000CD, 0x3 },
 196         { 0x80009010, 0x000000C0, 0x3 },
 197         { 0x00000018, 0x0000009D, 0x0 },
 198         { 0x80005012, 0x000000C0, 0x3 },
 199         { 0x80007011, 0x000000C0, 0x3 },
 200         { 0x00000018, 0x00000088, 0x0 },
 201         { 0x80005012, 0x000000C0, 0x3 },
 202 };
 203
 204 /* Kabylake H and S */
 205 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 206         { 0x00002016, 0x000000A0, 0x0 },
 207         { 0x00005012, 0x0000009B, 0x0 },
 208         { 0x00007011, 0x00000088, 0x0 },
 209         { 0x80009010, 0x000000C0, 0x1 },
 210         { 0x00002016, 0x0000009B, 0x0 },
 211         { 0x00005012, 0x00000088, 0x0 },
 212         { 0x80007011, 0x000000C0, 0x1 },
 213         { 0x00002016, 0x00000097, 0x0 },
 214         { 0x80005012, 0x000000C0, 0x1 },
 215 };
 216
 217 /* Kabylake U */
 218 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 219         { 0x0000201B, 0x000000A1, 0x0 },
 220         { 0x00005012, 0x00000088, 0x0 },
 221         { 0x80007011, 0x000000CD, 0x3 },
 222         { 0x80009010, 0x000000C0, 0x3 },
 223         { 0x0000201B, 0x0000009D, 0x0 },
 224         { 0x80005012, 0x000000C0, 0x3 },
 225         { 0x80007011, 0x000000C0, 0x3 },
 226         { 0x00002016, 0x0000004F, 0x0 },
 227         { 0x80005012, 0x000000C0, 0x3 },
 228 };
 229
 230 /* Kabylake Y */
 231 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 232         { 0x00001017, 0x000000A1, 0x0 },
 233         { 0x00005012, 0x00000088, 0x0 },
 234         { 0x80007011, 0x000000CD, 0x3 },
 235         { 0x8000800F, 0x000000C0, 0x3 },
 236         { 0x00001017, 0x0000009D, 0x0 },
 237         { 0x80005012, 0x000000C0, 0x3 },
 238         { 0x80007011, 0x000000C0, 0x3 },
 239         { 0x00001017, 0x0000004C, 0x0 },
 240         { 0x80005012, 0x000000C0, 0x3 },
 241 };
 242
 243 /*
 244  * Skylake/Kabylake H and S
 245  * eDP 1.4 low vswing translation parameters
 246  */
 247 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 248         { 0x00000018, 0x000000A8, 0x0 },
 249         { 0x00004013, 0x000000A9, 0x0 },
 250         { 0x00007011, 0x000000A2, 0x0 },
 251         { 0x00009010, 0x0000009C, 0x0 },
 252         { 0x00000018, 0x000000A9, 0x0 },
 253         { 0x00006013, 0x000000A2, 0x0 },
 254         { 0x00007011, 0x000000A6, 0x0 },
 255         { 0x00000018, 0x000000AB, 0x0 },
 256         { 0x00007013, 0x0000009F, 0x0 },
 257         { 0x00000018, 0x000000DF, 0x0 },
 258 };
 259
 260 /*
 261  * Skylake/Kabylake U
 262  * eDP 1.4 low vswing translation parameters
 263  */
 264 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 265         { 0x00000018, 0x000000A8, 0x0 },
 266         { 0x00004013, 0x000000A9, 0x0 },
 267         { 0x00007011, 0x000000A2, 0x0 },
 268         { 0x00009010, 0x0000009C, 0x0 },
 269         { 0x00000018, 0x000000A9, 0x0 },
 270         { 0x00006013, 0x000000A2, 0x0 },
 271         { 0x00007011, 0x000000A6, 0x0 },
 272         { 0x00002016, 0x000000AB, 0x0 },
 273         { 0x00005013, 0x0000009F, 0x0 },
 274         { 0x00000018, 0x000000DF, 0x0 },
 275 };
 276
 277 /*
 278  * Skylake/Kabylake Y
 279  * eDP 1.4 low vswing translation parameters
 280  */
 281 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 282         { 0x00000018, 0x000000A8, 0x0 },
 283         { 0x00004013, 0x000000AB, 0x0 },
 284         { 0x00007011, 0x000000A4, 0x0 },
 285         { 0x00009010, 0x000000DF, 0x0 },
 286         { 0x00000018, 0x000000AA, 0x0 },
 287         { 0x00006013, 0x000000A4, 0x0 },
 288         { 0x00007011, 0x0000009D, 0x0 },
 289         { 0x00000018, 0x000000A0, 0x0 },
 290         { 0x00006012, 0x000000DF, 0x0 },
 291         { 0x00000018, 0x0000008A, 0x0 },
 292 };
 293
 294 /* Skylake/Kabylake U, H and S */
 295 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 296         { 0x00000018, 0x000000AC, 0x0 },
 297         { 0x00005012, 0x0000009D, 0x0 },
 298         { 0x00007011, 0x00000088, 0x0 },
 299         { 0x00000018, 0x000000A1, 0x0 },
 300         { 0x00000018, 0x00000098, 0x0 },
 301         { 0x00004013, 0x00000088, 0x0 },
 302         { 0x80006012, 0x000000CD, 0x1 },
 303         { 0x00000018, 0x000000DF, 0x0 },
 304         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 305         { 0x80003015, 0x000000C0, 0x1 },
 306         { 0x80000018, 0x000000C0, 0x1 },
 307 };
 308
 309 /* Skylake/Kabylake Y */
 310 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 311         { 0x00000018, 0x000000A1, 0x0 },
 312         { 0x00005012, 0x000000DF, 0x0 },
 313         { 0x80007011, 0x000000CB, 0x3 },
 314         { 0x00000018, 0x000000A4, 0x0 },
 315         { 0x00000018, 0x0000009D, 0x0 },
 316         { 0x00004013, 0x00000080, 0x0 },
 317         { 0x80006013, 0x000000C0, 0x3 },
 318         { 0x00000018, 0x0000008A, 0x0 },
 319         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 320         { 0x80003015, 0x000000C0, 0x3 },
 321         { 0x80000018, 0x000000C0, 0x3 },
 322 };
 323
 324 struct bxt_ddi_buf_trans {
 325         u8 margin;      /* swing value */
 326         u8 scale;       /* scale value */
 327         u8 enable;      /* scale enable */
 328         u8 deemphasis;
 329 };
 330
 331 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 332                                         /* Idx  NT mV diff      db  */
 333         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 334         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 335         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 336         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 337         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 338         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 339         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 340         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 341         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 342         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 343 };
 344
 345 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 346                                         /* Idx  NT mV diff      db  */
 347         { 26, 0, 0, 128, },     /* 0:   200             0   */
 348         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 349         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 350         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 351         { 32, 0, 0, 128, },     /* 4:   250             0   */
 352         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 353         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 354         { 43, 0, 0, 128, },     /* 7:   300             0   */
 355         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 356         { 48, 0, 0, 128, },     /* 9:   300             0   */
 357 };
 358
 359 /* BSpec has 2 recommended values - entries 0 and 8.
 360  * Using the entry with higher vswing.
 361  */
 362 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 363                                         /* Idx  NT mV diff      db  */
 364         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 365         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 366         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 367         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 368         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 369         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 370         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 371         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 372         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 373         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 374 };
 375
 376 struct cnl_ddi_buf_trans {
 377         u8 dw2_swing_sel;
 378         u8 dw7_n_scalar;
 379         u8 dw4_cursor_coeff;
 380         u8 dw4_post_cursor_2;
 381         u8 dw4_post_cursor_1;
 382 };
 383
 384 /* Voltage Swing Programming for VccIO 0.85V for DP */
 385 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 386                                                 /* NT mV Trans mV db    */
 387         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 388         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 389         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 390         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 391         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 392         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 393         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 394         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 395         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 396         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 397 };
 398
 399 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 400 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 401                                                 /* NT mV Trans mV db    */
 402         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 403         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 404         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 405         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 406         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 407         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 408         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 409 };
 410
 411 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 412 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 413                                                 /* NT mV Trans mV db    */
 414         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 415         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 416         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 417         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 418         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 419         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 420         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 421         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 422         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 423 };
 424
 425 /* Voltage Swing Programming for VccIO 0.95V for DP */
 426 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 427                                                 /* NT mV Trans mV db    */
 428         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 429         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 430         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 431         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 432         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 433         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 434         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 435         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 436         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 437         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 438 };
 439
 440 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 441 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 442                                                 /* NT mV Trans mV db    */
 443         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 444         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 445         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 446         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 447         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 448         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 449         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 450         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 451         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 452         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 453         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 454 };
 455
 456 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 457 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 458                                                 /* NT mV Trans mV db    */
 459         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 460         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 461         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 462         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 463         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 464         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 465         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 466         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 467         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 468         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 469 };
 470
 471 /* Voltage Swing Programming for VccIO 1.05V for DP */
 472 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 473                                                 /* NT mV Trans mV db    */
 474         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 475         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 476         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 477         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 478         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 479         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 480         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 481         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 482         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 483         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 484 };
 485
 486 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 487 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 488                                                 /* NT mV Trans mV db    */
 489         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 490         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 491         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 492         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 493         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 494         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 495         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 496         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 497         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 498         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 499         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 503 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 504                                                 /* NT mV Trans mV db    */
 505         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 506         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 507         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 508         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 509         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 510         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 511         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 512         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 513         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 514 };
 515
 516 /* icl_combo_phy_ddi_translations */
 517 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 518                                                 /* NT mV Trans mV db    */
 519         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 520         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 521         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 522         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 523         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 524         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 525         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 526         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 527         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 528         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 529 };
 530
 531 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 532                                                 /* NT mV Trans mV db    */
 533         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 534         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 535         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 536         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 537         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 538         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 539         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 540         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 541         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 542         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 543 };
 544
 545 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 546                                                 /* NT mV Trans mV db    */
 547         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 548         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 549         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 550         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 551         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 552         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 553         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 554         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 555         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 556         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 557 };
 558
 559 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 560                                                 /* NT mV Trans mV db    */
 561         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 562         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 563         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 564         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 565         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 566         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 567         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 568 };
 569
 570 struct icl_mg_phy_ddi_buf_trans {
 571         u32 cri_txdeemph_override_5_0;
 572         u32 cri_txdeemph_override_11_6;
 573         u32 cri_txdeemph_override_17_12;
 574 };
 575
 576 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 577                                 /* Voltage swing  pre-emphasis */
 578         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 579         { 0x0, 0x23, 0x08 },    /* 0              1   */
 580         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 581         { 0x0, 0x00, 0x00 },    /* 0              3   */
 582         { 0x0, 0x23, 0x00 },    /* 1              0   */
 583         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 584         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 585         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 586         { 0x0, 0x33, 0x0C },    /* 2              1   */
 587         { 0x0, 0x00, 0x00 },    /* 3              0   */
 588 };
 589
 590 struct tgl_dkl_phy_ddi_buf_trans {
 591         u32 dkl_vswing_control;
 592         u32 dkl_preshoot_control;
 593         u32 dkl_de_emphasis_control;
 594 };
 595
 596 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
 597                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 598         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 599         { 0x5, 0x0, 0x03 },     /* 0    1       400mV           3.5 dB */
 600         { 0x2, 0x0, 0x0b },     /* 0    2       400mV           6 dB */
 601         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 602         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 603         { 0x2, 0x0, 0x03 },     /* 1    1       600mV           3.5 dB */
 604         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 605         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 606         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 607         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 608 };
 609
 610 static const struct ddi_buf_trans *
 611 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 612 {
 613         if (dev_priv->vbt.edp.low_vswing) {
 614                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 615                 return bdw_ddi_translations_edp;
 616         } else {
 617                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 618                 return bdw_ddi_translations_dp;
 619         }
 620 }
 621
 622 static const struct ddi_buf_trans *
 623 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 624 {
 625         if (IS_SKL_ULX(dev_priv)) {
 626                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 627                 return skl_y_ddi_translations_dp;
 628         } else if (IS_SKL_ULT(dev_priv)) {
 629                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 630                 return skl_u_ddi_translations_dp;
 631         } else {
 632                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 633                 return skl_ddi_translations_dp;
 634         }
 635 }
 636
 637 static const struct ddi_buf_trans *
 638 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 639 {
 640         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 641                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 642                 return kbl_y_ddi_translations_dp;
 643         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 644                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 645                 return kbl_u_ddi_translations_dp;
 646         } else {
 647                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 648                 return kbl_ddi_translations_dp;
 649         }
 650 }
 651
 652 static const struct ddi_buf_trans *
 653 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 654 {
 655         if (dev_priv->vbt.edp.low_vswing) {
 656                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 657                     IS_CFL_ULX(dev_priv)) {
 658                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 659                         return skl_y_ddi_translations_edp;
 660                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 661                            IS_CFL_ULT(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 663                         return skl_u_ddi_translations_edp;
 664                 } else {
 665                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 666                         return skl_ddi_translations_edp;
 667                 }
 668         }
 669
 670         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 671                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 672         else
 673                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 674 }
 675
 676 static const struct ddi_buf_trans *
 677 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 678 {
 679         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 680             IS_CFL_ULX(dev_priv)) {
 681                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 682                 return skl_y_ddi_translations_hdmi;
 683         } else {
 684                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 685                 return skl_ddi_translations_hdmi;
 686         }
 687 }
 688
 689 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 690 {
 691         /* Only DDIA and DDIE can select the 10th register with DP */
 692         if (port == PORT_A || port == PORT_E)
 693                 return min(n_entries, 10);
 694         else
 695                 return min(n_entries, 9);
 696 }
 697
 698 static const struct ddi_buf_trans *
 699 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 700                            enum port port, int *n_entries)
 701 {
 702         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 703                 const struct ddi_buf_trans *ddi_translations =
 704                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 705                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 706                 return ddi_translations;
 707         } else if (IS_SKYLAKE(dev_priv)) {
 708                 const struct ddi_buf_trans *ddi_translations =
 709                         skl_get_buf_trans_dp(dev_priv, n_entries);
 710                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 711                 return ddi_translations;
 712         } else if (IS_BROADWELL(dev_priv)) {
 713                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 714                 return  bdw_ddi_translations_dp;
 715         } else if (IS_HASWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 717                 return hsw_ddi_translations_dp;
 718         }
 719
 720         *n_entries = 0;
 721         return NULL;
 722 }
 723
 724 static const struct ddi_buf_trans *
 725 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 726                             enum port port, int *n_entries)
 727 {
 728         if (IS_GEN9_BC(dev_priv)) {
 729                 const struct ddi_buf_trans *ddi_translations =
 730                         skl_get_buf_trans_edp(dev_priv, n_entries);
 731                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 732                 return ddi_translations;
 733         } else if (IS_BROADWELL(dev_priv)) {
 734                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 735         } else if (IS_HASWELL(dev_priv)) {
 736                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 737                 return hsw_ddi_translations_dp;
 738         }
 739
 740         *n_entries = 0;
 741         return NULL;
 742 }
 743
 744 static const struct ddi_buf_trans *
 745 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 746                             int *n_entries)
 747 {
 748         if (IS_BROADWELL(dev_priv)) {
 749                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 750                 return bdw_ddi_translations_fdi;
 751         } else if (IS_HASWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 753                 return hsw_ddi_translations_fdi;
 754         }
 755
 756         *n_entries = 0;
 757         return NULL;
 758 }
 759
 760 static const struct ddi_buf_trans *
 761 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 762                              int *n_entries)
 763 {
 764         if (IS_GEN9_BC(dev_priv)) {
 765                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 766         } else if (IS_BROADWELL(dev_priv)) {
 767                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 768                 return bdw_ddi_translations_hdmi;
 769         } else if (IS_HASWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 771                 return hsw_ddi_translations_hdmi;
 772         }
 773
 774         *n_entries = 0;
 775         return NULL;
 776 }
 777
 778 static const struct bxt_ddi_buf_trans *
 779 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 780 {
 781         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 782         return bxt_ddi_translations_dp;
 783 }
 784
 785 static const struct bxt_ddi_buf_trans *
 786 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 787 {
 788         if (dev_priv->vbt.edp.low_vswing) {
 789                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 790                 return bxt_ddi_translations_edp;
 791         }
 792
 793         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 794 }
 795
 796 static const struct bxt_ddi_buf_trans *
 797 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 798 {
 799         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 800         return bxt_ddi_translations_hdmi;
 801 }
 802
 803 static const struct cnl_ddi_buf_trans *
 804 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 805 {
 806         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 807
 808         if (voltage == VOLTAGE_INFO_0_85V) {
 809                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 810                 return cnl_ddi_translations_hdmi_0_85V;
 811         } else if (voltage == VOLTAGE_INFO_0_95V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 813                 return cnl_ddi_translations_hdmi_0_95V;
 814         } else if (voltage == VOLTAGE_INFO_1_05V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 816                 return cnl_ddi_translations_hdmi_1_05V;
 817         } else {
 818                 *n_entries = 1; /* shut up gcc */
 819                 MISSING_CASE(voltage);
 820         }
 821         return NULL;
 822 }
 823
 824 static const struct cnl_ddi_buf_trans *
 825 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 826 {
 827         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 828
 829         if (voltage == VOLTAGE_INFO_0_85V) {
 830                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 831                 return cnl_ddi_translations_dp_0_85V;
 832         } else if (voltage == VOLTAGE_INFO_0_95V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 834                 return cnl_ddi_translations_dp_0_95V;
 835         } else if (voltage == VOLTAGE_INFO_1_05V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 837                 return cnl_ddi_translations_dp_1_05V;
 838         } else {
 839                 *n_entries = 1; /* shut up gcc */
 840                 MISSING_CASE(voltage);
 841         }
 842         return NULL;
 843 }
 844
 845 static const struct cnl_ddi_buf_trans *
 846 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 847 {
 848         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 849
 850         if (dev_priv->vbt.edp.low_vswing) {
 851                 if (voltage == VOLTAGE_INFO_0_85V) {
 852                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 853                         return cnl_ddi_translations_edp_0_85V;
 854                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 856                         return cnl_ddi_translations_edp_0_95V;
 857                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 859                         return cnl_ddi_translations_edp_1_05V;
 860                 } else {
 861                         *n_entries = 1; /* shut up gcc */
 862                         MISSING_CASE(voltage);
 863                 }
 864                 return NULL;
 865         } else {
 866                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 867         }
 868 }
 869
 870 static const struct cnl_ddi_buf_trans *
 871 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 872                         int *n_entries)
 873 {
 874         if (type == INTEL_OUTPUT_HDMI) {
 875                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 876                 return icl_combo_phy_ddi_translations_hdmi;
 877         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 878                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 879                 return icl_combo_phy_ddi_translations_edp_hbr3;
 880         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 881                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 882                 return icl_combo_phy_ddi_translations_edp_hbr2;
 883         }
 884
 885         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 886         return icl_combo_phy_ddi_translations_dp_hbr2;
 887 }
 888
 889 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 890 {
 891         int n_entries, level, default_entry;
 892         enum phy phy = intel_port_to_phy(dev_priv, port);
 893
 894         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 895
 896         if (INTEL_GEN(dev_priv) >= 12) {
 897                 if (intel_phy_is_combo(dev_priv, phy))
 898                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 899                                                 0, &n_entries);
 900                 else
 901                         n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
 902                 default_entry = n_entries - 1;
 903         } else if (INTEL_GEN(dev_priv) == 11) {
 904                 if (intel_phy_is_combo(dev_priv, phy))
 905                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 906                                                 0, &n_entries);
 907                 else
 908                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 909                 default_entry = n_entries - 1;
 910         } else if (IS_CANNONLAKE(dev_priv)) {
 911                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 912                 default_entry = n_entries - 1;
 913         } else if (IS_GEN9_LP(dev_priv)) {
 914                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 915                 default_entry = n_entries - 1;
 916         } else if (IS_GEN9_BC(dev_priv)) {
 917                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 918                 default_entry = 8;
 919         } else if (IS_BROADWELL(dev_priv)) {
 920                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 921                 default_entry = 7;
 922         } else if (IS_HASWELL(dev_priv)) {
 923                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 924                 default_entry = 6;
 925         } else {
 926                 WARN(1, "ddi translation table missing\n");
 927                 return 0;
 928         }
 929
 930         /* Choose a good default if VBT is badly populated */
 931         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 932                 level = default_entry;
 933
 934         if (WARN_ON_ONCE(n_entries == 0))
 935                 return 0;
 936         if (WARN_ON_ONCE(level >= n_entries))
 937                 level = n_entries - 1;
 938
 939         return level;
 940 }
 941
 942 /*
 943  * Starting with Haswell, DDI port buffers must be programmed with correct
 944  * values in advance. This function programs the correct values for
 945  * DP/eDP/FDI use cases.
 946  */
 947 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 948                                          const struct intel_crtc_state *crtc_state)
 949 {
 950         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 951         u32 iboost_bit = 0;
 952         int i, n_entries;
 953         enum port port = encoder->port;
 954         const struct ddi_buf_trans *ddi_translations;
 955
 956         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 957                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 958                                                                &n_entries);
 959         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 960                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 961                                                                &n_entries);
 962         else
 963                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 964                                                               &n_entries);
 965
 966         /* If we're boosting the current, set bit 31 of trans1 */
 967         if (IS_GEN9_BC(dev_priv) &&
 968             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 969                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 970
 971         for (i = 0; i < n_entries; i++) {
 972                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 973                            ddi_translations[i].trans1 | iboost_bit);
 974                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 975                            ddi_translations[i].trans2);
 976         }
 977 }
 978
 979 /*
 980  * Starting with Haswell, DDI port buffers must be programmed with correct
 981  * values in advance. This function programs the correct values for
 982  * HDMI/DVI use cases.
 983  */
 984 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 985                                            int level)
 986 {
 987         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 988         u32 iboost_bit = 0;
 989         int n_entries;
 990         enum port port = encoder->port;
 991         const struct ddi_buf_trans *ddi_translations;
 992
 993         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 994
 995         if (WARN_ON_ONCE(!ddi_translations))
 996                 return;
 997         if (WARN_ON_ONCE(level >= n_entries))
 998                 level = n_entries - 1;
 999
1000         /* If we're boosting the current, set bit 31 of trans1 */
1001         if (IS_GEN9_BC(dev_priv) &&
1002             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1003                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1004
1005         /* Entry 9 is for HDMI: */
1006         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1007                    ddi_translations[level].trans1 | iboost_bit);
1008         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1009                    ddi_translations[level].trans2);
1010 }
1011
1012 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1013                                     enum port port)
1014 {
1015         i915_reg_t reg = DDI_BUF_CTL(port);
1016         int i;
1017
1018         for (i = 0; i < 16; i++) {
1019                 udelay(1);
1020                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1021                         return;
1022         }
1023         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1024 }
1025
1026 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1027 {
1028         switch (pll->info->id) {
1029         case DPLL_ID_WRPLL1:
1030                 return PORT_CLK_SEL_WRPLL1;
1031         case DPLL_ID_WRPLL2:
1032                 return PORT_CLK_SEL_WRPLL2;
1033         case DPLL_ID_SPLL:
1034                 return PORT_CLK_SEL_SPLL;
1035         case DPLL_ID_LCPLL_810:
1036                 return PORT_CLK_SEL_LCPLL_810;
1037         case DPLL_ID_LCPLL_1350:
1038                 return PORT_CLK_SEL_LCPLL_1350;
1039         case DPLL_ID_LCPLL_2700:
1040                 return PORT_CLK_SEL_LCPLL_2700;
1041         default:
1042                 MISSING_CASE(pll->info->id);
1043                 return PORT_CLK_SEL_NONE;
1044         }
1045 }
1046
1047 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1048                                   const struct intel_crtc_state *crtc_state)
1049 {
1050         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1051         int clock = crtc_state->port_clock;
1052         const enum intel_dpll_id id = pll->info->id;
1053
1054         switch (id) {
1055         default:
1056                 /*
1057                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1058                  * here, so do warn if this get passed in
1059                  */
1060                 MISSING_CASE(id);
1061                 return DDI_CLK_SEL_NONE;
1062         case DPLL_ID_ICL_TBTPLL:
1063                 switch (clock) {
1064                 case 162000:
1065                         return DDI_CLK_SEL_TBT_162;
1066                 case 270000:
1067                         return DDI_CLK_SEL_TBT_270;
1068                 case 540000:
1069                         return DDI_CLK_SEL_TBT_540;
1070                 case 810000:
1071                         return DDI_CLK_SEL_TBT_810;
1072                 default:
1073                         MISSING_CASE(clock);
1074                         return DDI_CLK_SEL_NONE;
1075                 }
1076         case DPLL_ID_ICL_MGPLL1:
1077         case DPLL_ID_ICL_MGPLL2:
1078         case DPLL_ID_ICL_MGPLL3:
1079         case DPLL_ID_ICL_MGPLL4:
1080         case DPLL_ID_TGL_MGPLL5:
1081         case DPLL_ID_TGL_MGPLL6:
1082                 return DDI_CLK_SEL_MG;
1083         }
1084 }
1085
1086 /* Starting with Haswell, different DDI ports can work in FDI mode for
1087  * connection to the PCH-located connectors. For this, it is necessary to train
1088  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1089  *
1090  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1091  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1092  * DDI A (which is used for eDP)
1093  */
1094
1095 void hsw_fdi_link_train(struct intel_crtc *crtc,
1096                         const struct intel_crtc_state *crtc_state)
1097 {
1098         struct drm_device *dev = crtc->base.dev;
1099         struct drm_i915_private *dev_priv = to_i915(dev);
1100         struct intel_encoder *encoder;
1101         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1102
1103         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1104                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1105                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1106         }
1107
1108         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1109          * mode set "sequence for CRT port" document:
1110          * - TP1 to TP2 time with the default value
1111          * - FDI delay to 90h
1112          *
1113          * WaFDIAutoLinkSetTimingOverrride:hsw
1114          */
1115         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1116                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1117                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1118
1119         /* Enable the PCH Receiver FDI PLL */
1120         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1121                      FDI_RX_PLL_ENABLE |
1122                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1123         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1124         POSTING_READ(FDI_RX_CTL(PIPE_A));
1125         udelay(220);
1126
1127         /* Switch from Rawclk to PCDclk */
1128         rx_ctl_val |= FDI_PCDCLK;
1129         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1130
1131         /* Configure Port Clock Select */
1132         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1133         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1134         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1135
1136         /* Start the training iterating through available voltages and emphasis,
1137          * testing each value twice. */
1138         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1139                 /* Configure DP_TP_CTL with auto-training */
1140                 I915_WRITE(DP_TP_CTL(PORT_E),
1141                                         DP_TP_CTL_FDI_AUTOTRAIN |
1142                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1143                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1144                                         DP_TP_CTL_ENABLE);
1145
1146                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1147                  * DDI E does not support port reversal, the functionality is
1148                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1149                  * port reversal bit */
1150                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1151                            DDI_BUF_CTL_ENABLE |
1152                            ((crtc_state->fdi_lanes - 1) << 1) |
1153                            DDI_BUF_TRANS_SELECT(i / 2));
1154                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1155
1156                 udelay(600);
1157
1158                 /* Program PCH FDI Receiver TU */
1159                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1160
1161                 /* Enable PCH FDI Receiver with auto-training */
1162                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1163                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1164                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1165
1166                 /* Wait for FDI receiver lane calibration */
1167                 udelay(30);
1168
1169                 /* Unset FDI_RX_MISC pwrdn lanes */
1170                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1171                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1172                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1173                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1174
1175                 /* Wait for FDI auto training time */
1176                 udelay(5);
1177
1178                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1179                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1180                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1181                         break;
1182                 }
1183
1184                 /*
1185                  * Leave things enabled even if we failed to train FDI.
1186                  * Results in less fireworks from the state checker.
1187                  */
1188                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1189                         DRM_ERROR("FDI link training failed!\n");
1190                         break;
1191                 }
1192
1193                 rx_ctl_val &= ~FDI_RX_ENABLE;
1194                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1195                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1196
1197                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1198                 temp &= ~DDI_BUF_CTL_ENABLE;
1199                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1200                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1201
1202                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1203                 temp = I915_READ(DP_TP_CTL(PORT_E));
1204                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1205                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1206                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1207                 POSTING_READ(DP_TP_CTL(PORT_E));
1208
1209                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1210
1211                 /* Reset FDI_RX_MISC pwrdn lanes */
1212                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1213                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1214                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1215                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1216                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1217         }
1218
1219         /* Enable normal pixel sending for FDI */
1220         I915_WRITE(DP_TP_CTL(PORT_E),
1221                    DP_TP_CTL_FDI_AUTOTRAIN |
1222                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1223                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1224                    DP_TP_CTL_ENABLE);
1225 }
1226
1227 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1228 {
1229         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1230         struct intel_digital_port *intel_dig_port =
1231                 enc_to_dig_port(&encoder->base);
1232
1233         intel_dp->DP = intel_dig_port->saved_port_bits |
1234                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1235         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1236 }
1237
1238 static struct intel_encoder *
1239 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1240 {
1241         struct drm_device *dev = crtc->base.dev;
1242         struct intel_encoder *encoder, *ret = NULL;
1243         int num_encoders = 0;
1244
1245         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1246                 ret = encoder;
1247                 num_encoders++;
1248         }
1249
1250         if (num_encoders != 1)
1251                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1252                      pipe_name(crtc->pipe));
1253
1254         BUG_ON(ret == NULL);
1255         return ret;
1256 }
1257
1258 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1259                                    i915_reg_t reg)
1260 {
1261         int refclk;
1262         int n, p, r;
1263         u32 wrpll;
1264
1265         wrpll = I915_READ(reg);
1266         switch (wrpll & WRPLL_REF_MASK) {
1267         case WRPLL_REF_SPECIAL_HSW:
1268                 /*
1269                  * muxed-SSC for BDW.
1270                  * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1271                  * for the non-SSC reference frequency.
1272                  */
1273                 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1274                         if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1275                                 refclk = 24;
1276                         else
1277                                 refclk = 135;
1278                         break;
1279                 }
1280                 /* fall through */
1281         case WRPLL_REF_PCH_SSC:
1282                 /*
1283                  * We could calculate spread here, but our checking
1284                  * code only cares about 5% accuracy, and spread is a max of
1285                  * 0.5% downspread.
1286                  */
1287                 refclk = 135;
1288                 break;
1289         case WRPLL_REF_LCPLL:
1290                 refclk = 2700;
1291                 break;
1292         default:
1293                 MISSING_CASE(wrpll);
1294                 return 0;
1295         }
1296
1297         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1298         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1299         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1300
1301         /* Convert to KHz, p & r have a fixed point portion */
1302         return (refclk * n * 100) / (p * r);
1303 }
1304
1305 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1306 {
1307         u32 p0, p1, p2, dco_freq;
1308
1309         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1310         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1311
1312         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1313                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1314         else
1315                 p1 = 1;
1316
1317
1318         switch (p0) {
1319         case DPLL_CFGCR2_PDIV_1:
1320                 p0 = 1;
1321                 break;
1322         case DPLL_CFGCR2_PDIV_2:
1323                 p0 = 2;
1324                 break;
1325         case DPLL_CFGCR2_PDIV_3:
1326                 p0 = 3;
1327                 break;
1328         case DPLL_CFGCR2_PDIV_7:
1329                 p0 = 7;
1330                 break;
1331         }
1332
1333         switch (p2) {
1334         case DPLL_CFGCR2_KDIV_5:
1335                 p2 = 5;
1336                 break;
1337         case DPLL_CFGCR2_KDIV_2:
1338                 p2 = 2;
1339                 break;
1340         case DPLL_CFGCR2_KDIV_3:
1341                 p2 = 3;
1342                 break;
1343         case DPLL_CFGCR2_KDIV_1:
1344                 p2 = 1;
1345                 break;
1346         }
1347
1348         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1349                 * 24 * 1000;
1350
1351         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1352                      * 24 * 1000) / 0x8000;
1353
1354         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1355                 return 0;
1356
1357         return dco_freq / (p0 * p1 * p2 * 5);
1358 }
1359
1360 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1361                         struct intel_dpll_hw_state *pll_state)
1362 {
1363         u32 p0, p1, p2, dco_freq, ref_clock;
1364
1365         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1366         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1367
1368         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1369                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1370                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1371         else
1372                 p1 = 1;
1373
1374
1375         switch (p0) {
1376         case DPLL_CFGCR1_PDIV_2:
1377                 p0 = 2;
1378                 break;
1379         case DPLL_CFGCR1_PDIV_3:
1380                 p0 = 3;
1381                 break;
1382         case DPLL_CFGCR1_PDIV_5:
1383                 p0 = 5;
1384                 break;
1385         case DPLL_CFGCR1_PDIV_7:
1386                 p0 = 7;
1387                 break;
1388         }
1389
1390         switch (p2) {
1391         case DPLL_CFGCR1_KDIV_1:
1392                 p2 = 1;
1393                 break;
1394         case DPLL_CFGCR1_KDIV_2:
1395                 p2 = 2;
1396                 break;
1397         case DPLL_CFGCR1_KDIV_3:
1398                 p2 = 3;
1399                 break;
1400         }
1401
1402         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1403
1404         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1405                 * ref_clock;
1406
1407         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1408                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1409
1410         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1411                 return 0;
1412
1413         return dco_freq / (p0 * p1 * p2 * 5);
1414 }
1415
1416 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1417                                  enum port port)
1418 {
1419         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1420
1421         switch (val) {
1422         case DDI_CLK_SEL_NONE:
1423                 return 0;
1424         case DDI_CLK_SEL_TBT_162:
1425                 return 162000;
1426         case DDI_CLK_SEL_TBT_270:
1427                 return 270000;
1428         case DDI_CLK_SEL_TBT_540:
1429                 return 540000;
1430         case DDI_CLK_SEL_TBT_810:
1431                 return 810000;
1432         default:
1433                 MISSING_CASE(val);
1434                 return 0;
1435         }
1436 }
1437
1438 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1439                                 const struct intel_dpll_hw_state *pll_state)
1440 {
1441         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1442         u64 tmp;
1443
1444         ref_clock = dev_priv->cdclk.hw.ref;
1445
1446         if (INTEL_GEN(dev_priv) >= 12) {
1447                 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
1448                 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
1449                 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
1450
1451                 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
1452                         m2_frac = pll_state->mg_pll_bias &
1453                                   DKL_PLL_BIAS_FBDIV_FRAC_MASK;
1454                         m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
1455                 } else {
1456                         m2_frac = 0;
1457                 }
1458         } else {
1459                 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1460                 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1461
1462                 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
1463                         m2_frac = pll_state->mg_pll_div0 &
1464                                   MG_PLL_DIV0_FBDIV_FRAC_MASK;
1465                         m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
1466                 } else {
1467                         m2_frac = 0;
1468                 }
1469         }
1470
1471         switch (pll_state->mg_clktop2_hsclkctl &
1472                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1473         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1474                 div1 = 2;
1475                 break;
1476         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1477                 div1 = 3;
1478                 break;
1479         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1480                 div1 = 5;
1481                 break;
1482         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1483                 div1 = 7;
1484                 break;
1485         default:
1486                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1487                 return 0;
1488         }
1489
1490         div2 = (pll_state->mg_clktop2_hsclkctl &
1491                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1492                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1493
1494         /* div2 value of 0 is same as 1 means no div */
1495         if (div2 == 0)
1496                 div2 = 1;
1497
1498         /*
1499          * Adjust the original formula to delay the division by 2^22 in order to
1500          * minimize possible rounding errors.
1501          */
1502         tmp = (u64)m1 * m2_int * ref_clock +
1503               (((u64)m1 * m2_frac * ref_clock) >> 22);
1504         tmp = div_u64(tmp, 5 * div1 * div2);
1505
1506         return tmp;
1507 }
1508
1509 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1510 {
1511         int dotclock;
1512
1513         if (pipe_config->has_pch_encoder)
1514                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1515                                                     &pipe_config->fdi_m_n);
1516         else if (intel_crtc_has_dp_encoder(pipe_config))
1517                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1518                                                     &pipe_config->dp_m_n);
1519         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1520                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1521         else
1522                 dotclock = pipe_config->port_clock;
1523
1524         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1525             !intel_crtc_has_dp_encoder(pipe_config))
1526                 dotclock *= 2;
1527
1528         if (pipe_config->pixel_multiplier)
1529                 dotclock /= pipe_config->pixel_multiplier;
1530
1531         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1532 }
1533
1534 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1535                               struct intel_crtc_state *pipe_config)
1536 {
1537         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1538         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1539         enum port port = encoder->port;
1540         enum phy phy = intel_port_to_phy(dev_priv, port);
1541         int link_clock;
1542
1543         if (intel_phy_is_combo(dev_priv, phy)) {
1544                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1545         } else {
1546                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1547                                                 pipe_config->shared_dpll);
1548
1549                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1550                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1551                 else
1552                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1553         }
1554
1555         pipe_config->port_clock = link_clock;
1556
1557         ddi_dotclock_get(pipe_config);
1558 }
1559
1560 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1561                               struct intel_crtc_state *pipe_config)
1562 {
1563         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1564         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1565         int link_clock;
1566
1567         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1569         } else {
1570                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1571
1572                 switch (link_clock) {
1573                 case DPLL_CFGCR0_LINK_RATE_810:
1574                         link_clock = 81000;
1575                         break;
1576                 case DPLL_CFGCR0_LINK_RATE_1080:
1577                         link_clock = 108000;
1578                         break;
1579                 case DPLL_CFGCR0_LINK_RATE_1350:
1580                         link_clock = 135000;
1581                         break;
1582                 case DPLL_CFGCR0_LINK_RATE_1620:
1583                         link_clock = 162000;
1584                         break;
1585                 case DPLL_CFGCR0_LINK_RATE_2160:
1586                         link_clock = 216000;
1587                         break;
1588                 case DPLL_CFGCR0_LINK_RATE_2700:
1589                         link_clock = 270000;
1590                         break;
1591                 case DPLL_CFGCR0_LINK_RATE_3240:
1592                         link_clock = 324000;
1593                         break;
1594                 case DPLL_CFGCR0_LINK_RATE_4050:
1595                         link_clock = 405000;
1596                         break;
1597                 default:
1598                         WARN(1, "Unsupported link rate\n");
1599                         break;
1600                 }
1601                 link_clock *= 2;
1602         }
1603
1604         pipe_config->port_clock = link_clock;
1605
1606         ddi_dotclock_get(pipe_config);
1607 }
1608
1609 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1610                               struct intel_crtc_state *pipe_config)
1611 {
1612         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1613         int link_clock;
1614
1615         /*
1616          * ctrl1 register is already shifted for each pll, just use 0 to get
1617          * the internal shift for each field
1618          */
1619         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1620                 link_clock = skl_calc_wrpll_link(pll_state);
1621         } else {
1622                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1623                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1624
1625                 switch (link_clock) {
1626                 case DPLL_CTRL1_LINK_RATE_810:
1627                         link_clock = 81000;
1628                         break;
1629                 case DPLL_CTRL1_LINK_RATE_1080:
1630                         link_clock = 108000;
1631                         break;
1632                 case DPLL_CTRL1_LINK_RATE_1350:
1633                         link_clock = 135000;
1634                         break;
1635                 case DPLL_CTRL1_LINK_RATE_1620:
1636                         link_clock = 162000;
1637                         break;
1638                 case DPLL_CTRL1_LINK_RATE_2160:
1639                         link_clock = 216000;
1640                         break;
1641                 case DPLL_CTRL1_LINK_RATE_2700:
1642                         link_clock = 270000;
1643                         break;
1644                 default:
1645                         WARN(1, "Unsupported link rate\n");
1646                         break;
1647                 }
1648                 link_clock *= 2;
1649         }
1650
1651         pipe_config->port_clock = link_clock;
1652
1653         ddi_dotclock_get(pipe_config);
1654 }
1655
1656 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1657                               struct intel_crtc_state *pipe_config)
1658 {
1659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1660         int link_clock = 0;
1661         u32 val, pll;
1662
1663         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1664         switch (val & PORT_CLK_SEL_MASK) {
1665         case PORT_CLK_SEL_LCPLL_810:
1666                 link_clock = 81000;
1667                 break;
1668         case PORT_CLK_SEL_LCPLL_1350:
1669                 link_clock = 135000;
1670                 break;
1671         case PORT_CLK_SEL_LCPLL_2700:
1672                 link_clock = 270000;
1673                 break;
1674         case PORT_CLK_SEL_WRPLL1:
1675                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1676                 break;
1677         case PORT_CLK_SEL_WRPLL2:
1678                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1679                 break;
1680         case PORT_CLK_SEL_SPLL:
1681                 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1682                 if (pll == SPLL_FREQ_810MHz)
1683                         link_clock = 81000;
1684                 else if (pll == SPLL_FREQ_1350MHz)
1685                         link_clock = 135000;
1686                 else if (pll == SPLL_FREQ_2700MHz)
1687                         link_clock = 270000;
1688                 else {
1689                         WARN(1, "bad spll freq\n");
1690                         return;
1691                 }
1692                 break;
1693         default:
1694                 WARN(1, "bad port clock sel\n");
1695                 return;
1696         }
1697
1698         pipe_config->port_clock = link_clock * 2;
1699
1700         ddi_dotclock_get(pipe_config);
1701 }
1702
1703 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1704 {
1705         struct dpll clock;
1706
1707         clock.m1 = 2;
1708         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1709         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1710                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1711         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1712         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1713         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1714
1715         return chv_calc_dpll_params(100000, &clock);
1716 }
1717
1718 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1719                               struct intel_crtc_state *pipe_config)
1720 {
1721         pipe_config->port_clock =
1722                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1723
1724         ddi_dotclock_get(pipe_config);
1725 }
1726
1727 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1728                                 struct intel_crtc_state *pipe_config)
1729 {
1730         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1731
1732         if (INTEL_GEN(dev_priv) >= 11)
1733                 icl_ddi_clock_get(encoder, pipe_config);
1734         else if (IS_CANNONLAKE(dev_priv))
1735                 cnl_ddi_clock_get(encoder, pipe_config);
1736         else if (IS_GEN9_LP(dev_priv))
1737                 bxt_ddi_clock_get(encoder, pipe_config);
1738         else if (IS_GEN9_BC(dev_priv))
1739                 skl_ddi_clock_get(encoder, pipe_config);
1740         else if (INTEL_GEN(dev_priv) <= 8)
1741                 hsw_ddi_clock_get(encoder, pipe_config);
1742 }
1743
1744 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1745                           const struct drm_connector_state *conn_state)
1746 {
1747         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1748         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1749         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1750         u32 temp;
1751
1752         if (!intel_crtc_has_dp_encoder(crtc_state))
1753                 return;
1754
1755         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1756
1757         temp = DP_MSA_MISC_SYNC_CLOCK;
1758
1759         switch (crtc_state->pipe_bpp) {
1760         case 18:
1761                 temp |= DP_MSA_MISC_6_BPC;
1762                 break;
1763         case 24:
1764                 temp |= DP_MSA_MISC_8_BPC;
1765                 break;
1766         case 30:
1767                 temp |= DP_MSA_MISC_10_BPC;
1768                 break;
1769         case 36:
1770                 temp |= DP_MSA_MISC_12_BPC;
1771                 break;
1772         default:
1773                 MISSING_CASE(crtc_state->pipe_bpp);
1774                 break;
1775         }
1776
1777         /* nonsense combination */
1778         WARN_ON(crtc_state->limited_color_range &&
1779                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1780
1781         if (crtc_state->limited_color_range)
1782                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1783
1784         /*
1785          * As per DP 1.2 spec section 2.3.4.3 while sending
1786          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1787          * colorspace information.
1788          */
1789         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1790                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1791
1792         /*
1793          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1794          * of Color Encoding Format and Content Color Gamut] while sending
1795          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1796          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1797          */
1798         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1799                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1800
1801         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1802 }
1803
1804 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1805                                     bool state)
1806 {
1807         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1808         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1809         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1810         u32 temp;
1811
1812         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1813         if (state == true)
1814                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1815         else
1816                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1817         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1818 }
1819
1820 /*
1821  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1822  *
1823  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1824  * intel_ddi_config_transcoder_func().
1825  */
1826 static u32
1827 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1828 {
1829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1830         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1831         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1832         enum pipe pipe = crtc->pipe;
1833         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1834         enum port port = encoder->port;
1835         u32 temp;
1836
1837         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1838         temp = TRANS_DDI_FUNC_ENABLE;
1839         if (INTEL_GEN(dev_priv) >= 12)
1840                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1841         else
1842                 temp |= TRANS_DDI_SELECT_PORT(port);
1843
1844         switch (crtc_state->pipe_bpp) {
1845         case 18:
1846                 temp |= TRANS_DDI_BPC_6;
1847                 break;
1848         case 24:
1849                 temp |= TRANS_DDI_BPC_8;
1850                 break;
1851         case 30:
1852                 temp |= TRANS_DDI_BPC_10;
1853                 break;
1854         case 36:
1855                 temp |= TRANS_DDI_BPC_12;
1856                 break;
1857         default:
1858                 BUG();
1859         }
1860
1861         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1862                 temp |= TRANS_DDI_PVSYNC;
1863         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1864                 temp |= TRANS_DDI_PHSYNC;
1865
1866         if (cpu_transcoder == TRANSCODER_EDP) {
1867                 switch (pipe) {
1868                 case PIPE_A:
1869                         /* On Haswell, can only use the always-on power well for
1870                          * eDP when not using the panel fitter, and when not
1871                          * using motion blur mitigation (which we don't
1872                          * support). */
1873                         if (crtc_state->pch_pfit.force_thru)
1874                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1875                         else
1876                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1877                         break;
1878                 case PIPE_B:
1879                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1880                         break;
1881                 case PIPE_C:
1882                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1883                         break;
1884                 default:
1885                         BUG();
1886                         break;
1887                 }
1888         }
1889
1890         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1891                 if (crtc_state->has_hdmi_sink)
1892                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1893                 else
1894                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1895
1896                 if (crtc_state->hdmi_scrambling)
1897                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1898                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1899                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1900         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1901                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1902                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1903         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1904                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1905                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1906
1907                 if (INTEL_GEN(dev_priv) >= 12)
1908                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
1909         } else {
1910                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1911                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1912         }
1913
1914         return temp;
1915 }
1916
1917 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1918 {
1919         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1920         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1921         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1922         u32 temp;
1923
1924         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1925         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1926 }
1927
1928 /*
1929  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1930  * bit.
1931  */
1932 static void
1933 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1934 {
1935         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1936         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1937         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1938         u32 temp;
1939
1940         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1941         temp &= ~TRANS_DDI_FUNC_ENABLE;
1942         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1943 }
1944
1945 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1946 {
1947         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1948         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1949         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1950         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1951         u32 val = I915_READ(reg);
1952
1953         if (INTEL_GEN(dev_priv) >= 12) {
1954                 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1955                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1956         } else {
1957                 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1958                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1959         }
1960         I915_WRITE(reg, val);
1961
1962         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1963             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1964                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1965                 /* Quirk time at 100ms for reliable operation */
1966                 msleep(100);
1967         }
1968 }
1969
1970 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1971                                      bool enable)
1972 {
1973         struct drm_device *dev = intel_encoder->base.dev;
1974         struct drm_i915_private *dev_priv = to_i915(dev);
1975         intel_wakeref_t wakeref;
1976         enum pipe pipe = 0;
1977         int ret = 0;
1978         u32 tmp;
1979
1980         wakeref = intel_display_power_get_if_enabled(dev_priv,
1981                                                      intel_encoder->power_domain);
1982         if (WARN_ON(!wakeref))
1983                 return -ENXIO;
1984
1985         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1986                 ret = -EIO;
1987                 goto out;
1988         }
1989
1990         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1991         if (enable)
1992                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1993         else
1994                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1995         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1996 out:
1997         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1998         return ret;
1999 }
2000
2001 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
2002 {
2003         struct drm_device *dev = intel_connector->base.dev;
2004         struct drm_i915_private *dev_priv = to_i915(dev);
2005         struct intel_encoder *encoder = intel_connector->encoder;
2006         int type = intel_connector->base.connector_type;
2007         enum port port = encoder->port;
2008         enum transcoder cpu_transcoder;
2009         intel_wakeref_t wakeref;
2010         enum pipe pipe = 0;
2011         u32 tmp;
2012         bool ret;
2013
2014         wakeref = intel_display_power_get_if_enabled(dev_priv,
2015                                                      encoder->power_domain);
2016         if (!wakeref)
2017                 return false;
2018
2019         if (!encoder->get_hw_state(encoder, &pipe)) {
2020                 ret = false;
2021                 goto out;
2022         }
2023
2024         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
2025                 cpu_transcoder = TRANSCODER_EDP;
2026         else
2027                 cpu_transcoder = (enum transcoder) pipe;
2028
2029         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2030
2031         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2032         case TRANS_DDI_MODE_SELECT_HDMI:
2033         case TRANS_DDI_MODE_SELECT_DVI:
2034                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2035                 break;
2036
2037         case TRANS_DDI_MODE_SELECT_DP_SST:
2038                 ret = type == DRM_MODE_CONNECTOR_eDP ||
2039                       type == DRM_MODE_CONNECTOR_DisplayPort;
2040                 break;
2041
2042         case TRANS_DDI_MODE_SELECT_DP_MST:
2043                 /* if the transcoder is in MST state then
2044                  * connector isn't connected */
2045                 ret = false;
2046                 break;
2047
2048         case TRANS_DDI_MODE_SELECT_FDI:
2049                 ret = type == DRM_MODE_CONNECTOR_VGA;
2050                 break;
2051
2052         default:
2053                 ret = false;
2054                 break;
2055         }
2056
2057 out:
2058         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2059
2060         return ret;
2061 }
2062
2063 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2064                                         u8 *pipe_mask, bool *is_dp_mst)
2065 {
2066         struct drm_device *dev = encoder->base.dev;
2067         struct drm_i915_private *dev_priv = to_i915(dev);
2068         enum port port = encoder->port;
2069         intel_wakeref_t wakeref;
2070         enum pipe p;
2071         u32 tmp;
2072         u8 mst_pipe_mask;
2073
2074         *pipe_mask = 0;
2075         *is_dp_mst = false;
2076
2077         wakeref = intel_display_power_get_if_enabled(dev_priv,
2078                                                      encoder->power_domain);
2079         if (!wakeref)
2080                 return;
2081
2082         tmp = I915_READ(DDI_BUF_CTL(port));
2083         if (!(tmp & DDI_BUF_CTL_ENABLE))
2084                 goto out;
2085
2086         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
2087                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2088
2089                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2090                 default:
2091                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2092                         /* fallthrough */
2093                 case TRANS_DDI_EDP_INPUT_A_ON:
2094                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2095                         *pipe_mask = BIT(PIPE_A);
2096                         break;
2097                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2098                         *pipe_mask = BIT(PIPE_B);
2099                         break;
2100                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2101                         *pipe_mask = BIT(PIPE_C);
2102                         break;
2103                 }
2104
2105                 goto out;
2106         }
2107
2108         mst_pipe_mask = 0;
2109         for_each_pipe(dev_priv, p) {
2110                 enum transcoder cpu_transcoder = (enum transcoder)p;
2111                 unsigned int port_mask, ddi_select;
2112                 intel_wakeref_t trans_wakeref;
2113
2114                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2115                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2116                 if (!trans_wakeref)
2117                         continue;
2118
2119                 if (INTEL_GEN(dev_priv) >= 12) {
2120                         port_mask = TGL_TRANS_DDI_PORT_MASK;
2121                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2122                 } else {
2123                         port_mask = TRANS_DDI_PORT_MASK;
2124                         ddi_select = TRANS_DDI_SELECT_PORT(port);
2125                 }
2126
2127                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2128                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2129                                         trans_wakeref);
2130
2131                 if ((tmp & port_mask) != ddi_select)
2132                         continue;
2133
2134                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2135                     TRANS_DDI_MODE_SELECT_DP_MST)
2136                         mst_pipe_mask |= BIT(p);
2137
2138                 *pipe_mask |= BIT(p);
2139         }
2140
2141         if (!*pipe_mask)
2142                 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2143                               encoder->base.base.id, encoder->base.name);
2144
2145         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2146                 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2147                               encoder->base.base.id, encoder->base.name,
2148                               *pipe_mask);
2149                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2150         }
2151
2152         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2153                 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2154                               encoder->base.base.id, encoder->base.name,
2155                               *pipe_mask, mst_pipe_mask);
2156         else
2157                 *is_dp_mst = mst_pipe_mask;
2158
2159 out:
2160         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2161                 tmp = I915_READ(BXT_PHY_CTL(port));
2162                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2163                             BXT_PHY_LANE_POWERDOWN_ACK |
2164                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2165                         DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2166                                   "(PHY_CTL %08x)\n", encoder->base.base.id,
2167                                   encoder->base.name, tmp);
2168         }
2169
2170         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2171 }
2172
2173 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2174                             enum pipe *pipe)
2175 {
2176         u8 pipe_mask;
2177         bool is_mst;
2178
2179         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2180
2181         if (is_mst || !pipe_mask)
2182                 return false;
2183
2184         *pipe = ffs(pipe_mask) - 1;
2185
2186         return true;
2187 }
2188
2189 static inline enum intel_display_power_domain
2190 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2191 {
2192         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2193          * DC states enabled at the same time, while for driver initiated AUX
2194          * transfers we need the same AUX IOs to be powered but with DC states
2195          * disabled. Accordingly use the AUX power domain here which leaves DC
2196          * states enabled.
2197          * However, for non-A AUX ports the corresponding non-EDP transcoders
2198          * would have already enabled power well 2 and DC_OFF. This means we can
2199          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2200          * specific AUX_IO reference without powering up any extra wells.
2201          * Note that PSR is enabled only on Port A even though this function
2202          * returns the correct domain for other ports too.
2203          */
2204         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2205                                               intel_aux_power_domain(dig_port);
2206 }
2207
2208 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2209                                         struct intel_crtc_state *crtc_state)
2210 {
2211         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2212         struct intel_digital_port *dig_port;
2213         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2214
2215         /*
2216          * TODO: Add support for MST encoders. Atm, the following should never
2217          * happen since fake-MST encoders don't set their get_power_domains()
2218          * hook.
2219          */
2220         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2221                 return;
2222
2223         dig_port = enc_to_dig_port(&encoder->base);
2224         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2225
2226         /*
2227          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2228          * ports.
2229          */
2230         if (intel_crtc_has_dp_encoder(crtc_state) ||
2231             intel_phy_is_tc(dev_priv, phy))
2232                 intel_display_power_get(dev_priv,
2233                                         intel_ddi_main_link_aux_domain(dig_port));
2234
2235         /*
2236          * VDSC power is needed when DSC is enabled
2237          */
2238         if (crtc_state->dsc.compression_enable)
2239                 intel_display_power_get(dev_priv,
2240                                         intel_dsc_power_domain(crtc_state));
2241 }
2242
2243 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2244 {
2245         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2246         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2247         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2248         enum port port = encoder->port;
2249         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2250
2251         if (cpu_transcoder != TRANSCODER_EDP) {
2252                 if (INTEL_GEN(dev_priv) >= 12)
2253                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2254                                    TGL_TRANS_CLK_SEL_PORT(port));
2255                 else
2256                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2257                                    TRANS_CLK_SEL_PORT(port));
2258         }
2259 }
2260
2261 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2262 {
2263         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2264         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2265
2266         if (cpu_transcoder != TRANSCODER_EDP) {
2267                 if (INTEL_GEN(dev_priv) >= 12)
2268                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2269                                    TGL_TRANS_CLK_SEL_DISABLED);
2270                 else
2271                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2272                                    TRANS_CLK_SEL_DISABLED);
2273         }
2274 }
2275
2276 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2277                                 enum port port, u8 iboost)
2278 {
2279         u32 tmp;
2280
2281         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2282         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2283         if (iboost)
2284                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2285         else
2286                 tmp |= BALANCE_LEG_DISABLE(port);
2287         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2288 }
2289
2290 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2291                                int level, enum intel_output_type type)
2292 {
2293         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2294         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2295         enum port port = encoder->port;
2296         u8 iboost;
2297
2298         if (type == INTEL_OUTPUT_HDMI)
2299                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2300         else
2301                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2302
2303         if (iboost == 0) {
2304                 const struct ddi_buf_trans *ddi_translations;
2305                 int n_entries;
2306
2307                 if (type == INTEL_OUTPUT_HDMI)
2308                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2309                 else if (type == INTEL_OUTPUT_EDP)
2310                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2311                 else
2312                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2313
2314                 if (WARN_ON_ONCE(!ddi_translations))
2315                         return;
2316                 if (WARN_ON_ONCE(level >= n_entries))
2317                         level = n_entries - 1;
2318
2319                 iboost = ddi_translations[level].i_boost;
2320         }
2321
2322         /* Make sure that the requested I_boost is valid */
2323         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2324                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2325                 return;
2326         }
2327
2328         _skl_ddi_set_iboost(dev_priv, port, iboost);
2329
2330         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2331                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2332 }
2333
2334 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2335                                     int level, enum intel_output_type type)
2336 {
2337         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2338         const struct bxt_ddi_buf_trans *ddi_translations;
2339         enum port port = encoder->port;
2340         int n_entries;
2341
2342         if (type == INTEL_OUTPUT_HDMI)
2343                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2344         else if (type == INTEL_OUTPUT_EDP)
2345                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2346         else
2347                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2348
2349         if (WARN_ON_ONCE(!ddi_translations))
2350                 return;
2351         if (WARN_ON_ONCE(level >= n_entries))
2352                 level = n_entries - 1;
2353
2354         bxt_ddi_phy_set_signal_level(dev_priv, port,
2355                                      ddi_translations[level].margin,
2356                                      ddi_translations[level].scale,
2357                                      ddi_translations[level].enable,
2358                                      ddi_translations[level].deemphasis);
2359 }
2360
2361 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2362 {
2363         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2364         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2365         enum port port = encoder->port;
2366         enum phy phy = intel_port_to_phy(dev_priv, port);
2367         int n_entries;
2368
2369         if (INTEL_GEN(dev_priv) >= 12) {
2370                 if (intel_phy_is_combo(dev_priv, phy))
2371                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2372                                                 intel_dp->link_rate, &n_entries);
2373                 else
2374                         n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
2375         } else if (INTEL_GEN(dev_priv) == 11) {
2376                 if (intel_phy_is_combo(dev_priv, phy))
2377                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2378                                                 intel_dp->link_rate, &n_entries);
2379                 else
2380                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2381         } else if (IS_CANNONLAKE(dev_priv)) {
2382                 if (encoder->type == INTEL_OUTPUT_EDP)
2383                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2384                 else
2385                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2386         } else if (IS_GEN9_LP(dev_priv)) {
2387                 if (encoder->type == INTEL_OUTPUT_EDP)
2388                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2389                 else
2390                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2391         } else {
2392                 if (encoder->type == INTEL_OUTPUT_EDP)
2393                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2394                 else
2395                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2396         }
2397
2398         if (WARN_ON(n_entries < 1))
2399                 n_entries = 1;
2400         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2401                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2402
2403         return index_to_dp_signal_levels[n_entries - 1] &
2404                 DP_TRAIN_VOLTAGE_SWING_MASK;
2405 }
2406
2407 /*
2408  * We assume that the full set of pre-emphasis values can be
2409  * used on all DDI platforms. Should that change we need to
2410  * rethink this code.
2411  */
2412 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2413 {
2414         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2415         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2416                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2417         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2418                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2419         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2420                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2421         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2422         default:
2423                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2424         }
2425 }
2426
2427 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2428                                    int level, enum intel_output_type type)
2429 {
2430         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2431         const struct cnl_ddi_buf_trans *ddi_translations;
2432         enum port port = encoder->port;
2433         int n_entries, ln;
2434         u32 val;
2435
2436         if (type == INTEL_OUTPUT_HDMI)
2437                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2438         else if (type == INTEL_OUTPUT_EDP)
2439                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2440         else
2441                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2442
2443         if (WARN_ON_ONCE(!ddi_translations))
2444                 return;
2445         if (WARN_ON_ONCE(level >= n_entries))
2446                 level = n_entries - 1;
2447
2448         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2449         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2450         val &= ~SCALING_MODE_SEL_MASK;
2451         val |= SCALING_MODE_SEL(2);
2452         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2453
2454         /* Program PORT_TX_DW2 */
2455         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2456         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2457                  RCOMP_SCALAR_MASK);
2458         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2459         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2460         /* Rcomp scalar is fixed as 0x98 for every table entry */
2461         val |= RCOMP_SCALAR(0x98);
2462         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2463
2464         /* Program PORT_TX_DW4 */
2465         /* We cannot write to GRP. It would overrite individual loadgen */
2466         for (ln = 0; ln < 4; ln++) {
2467                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2468                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2469                          CURSOR_COEFF_MASK);
2470                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2471                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2472                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2473                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2474         }
2475
2476         /* Program PORT_TX_DW5 */
2477         /* All DW5 values are fixed for every table entry */
2478         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2479         val &= ~RTERM_SELECT_MASK;
2480         val |= RTERM_SELECT(6);
2481         val |= TAP3_DISABLE;
2482         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2483
2484         /* Program PORT_TX_DW7 */
2485         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2486         val &= ~N_SCALAR_MASK;
2487         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2488         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2489 }
2490
2491 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2492                                     int level, enum intel_output_type type)
2493 {
2494         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2495         enum port port = encoder->port;
2496         int width, rate, ln;
2497         u32 val;
2498
2499         if (type == INTEL_OUTPUT_HDMI) {
2500                 width = 4;
2501                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2502         } else {
2503                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2504
2505                 width = intel_dp->lane_count;
2506                 rate = intel_dp->link_rate;
2507         }
2508
2509         /*
2510          * 1. If port type is eDP or DP,
2511          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2512          * else clear to 0b.
2513          */
2514         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2515         if (type != INTEL_OUTPUT_HDMI)
2516                 val |= COMMON_KEEPER_EN;
2517         else
2518                 val &= ~COMMON_KEEPER_EN;
2519         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2520
2521         /* 2. Program loadgen select */
2522         /*
2523          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2524          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2525          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2526          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2527          */
2528         for (ln = 0; ln <= 3; ln++) {
2529                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2530                 val &= ~LOADGEN_SELECT;
2531
2532                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2533                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2534                         val |= LOADGEN_SELECT;
2535                 }
2536                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2537         }
2538
2539         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2540         val = I915_READ(CNL_PORT_CL1CM_DW5);
2541         val |= SUS_CLOCK_CONFIG;
2542         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2543
2544         /* 4. Clear training enable to change swing values */
2545         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2546         val &= ~TX_TRAINING_EN;
2547         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2548
2549         /* 5. Program swing and de-emphasis */
2550         cnl_ddi_vswing_program(encoder, level, type);
2551
2552         /* 6. Set training enable to trigger update */
2553         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2554         val |= TX_TRAINING_EN;
2555         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2556 }
2557
2558 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2559                                         u32 level, enum phy phy, int type,
2560                                         int rate)
2561 {
2562         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2563         u32 n_entries, val;
2564         int ln;
2565
2566         ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2567                                                    &n_entries);
2568         if (!ddi_translations)
2569                 return;
2570
2571         if (level >= n_entries) {
2572                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2573                 level = n_entries - 1;
2574         }
2575
2576         /* Set PORT_TX_DW5 */
2577         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2578         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2579                   TAP2_DISABLE | TAP3_DISABLE);
2580         val |= SCALING_MODE_SEL(0x2);
2581         val |= RTERM_SELECT(0x6);
2582         val |= TAP3_DISABLE;
2583         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2584
2585         /* Program PORT_TX_DW2 */
2586         val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2587         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2588                  RCOMP_SCALAR_MASK);
2589         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2590         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2591         /* Program Rcomp scalar for every table entry */
2592         val |= RCOMP_SCALAR(0x98);
2593         I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2594
2595         /* Program PORT_TX_DW4 */
2596         /* We cannot write to GRP. It would overwrite individual loadgen. */
2597         for (ln = 0; ln <= 3; ln++) {
2598                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2599                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2600                          CURSOR_COEFF_MASK);
2601                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2602                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2603                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2604                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2605         }
2606
2607         /* Program PORT_TX_DW7 */
2608         val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2609         val &= ~N_SCALAR_MASK;
2610         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2611         I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2612 }
2613
2614 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2615                                               u32 level,
2616                                               enum intel_output_type type)
2617 {
2618         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2619         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2620         int width = 0;
2621         int rate = 0;
2622         u32 val;
2623         int ln = 0;
2624
2625         if (type == INTEL_OUTPUT_HDMI) {
2626                 width = 4;
2627                 /* Rate is always < than 6GHz for HDMI */
2628         } else {
2629                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2630
2631                 width = intel_dp->lane_count;
2632                 rate = intel_dp->link_rate;
2633         }
2634
2635         /*
2636          * 1. If port type is eDP or DP,
2637          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2638          * else clear to 0b.
2639          */
2640         val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2641         if (type == INTEL_OUTPUT_HDMI)
2642                 val &= ~COMMON_KEEPER_EN;
2643         else
2644                 val |= COMMON_KEEPER_EN;
2645         I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2646
2647         /* 2. Program loadgen select */
2648         /*
2649          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2650          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2651          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2652          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2653          */
2654         for (ln = 0; ln <= 3; ln++) {
2655                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2656                 val &= ~LOADGEN_SELECT;
2657
2658                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2659                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2660                         val |= LOADGEN_SELECT;
2661                 }
2662                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2663         }
2664
2665         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2666         val = I915_READ(ICL_PORT_CL_DW5(phy));
2667         val |= SUS_CLOCK_CONFIG;
2668         I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2669
2670         /* 4. Clear training enable to change swing values */
2671         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2672         val &= ~TX_TRAINING_EN;
2673         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2674
2675         /* 5. Program swing and de-emphasis */
2676         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2677
2678         /* 6. Set training enable to trigger update */
2679         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2680         val |= TX_TRAINING_EN;
2681         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2682 }
2683
2684 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2685                                            int link_clock,
2686                                            u32 level)
2687 {
2688         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2689         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2690         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2691         u32 n_entries, val;
2692         int ln;
2693
2694         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2695         ddi_translations = icl_mg_phy_ddi_translations;
2696         /* The table does not have values for level 3 and level 9. */
2697         if (level >= n_entries || level == 3 || level == 9) {
2698                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2699                               level, n_entries - 2);
2700                 level = n_entries - 2;
2701         }
2702
2703         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2704         for (ln = 0; ln < 2; ln++) {
2705                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
2706                 val &= ~CRI_USE_FS32;
2707                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
2708
2709                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
2710                 val &= ~CRI_USE_FS32;
2711                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
2712         }
2713
2714         /* Program MG_TX_SWINGCTRL with values from vswing table */
2715         for (ln = 0; ln < 2; ln++) {
2716                 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
2717                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2718                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2719                         ddi_translations[level].cri_txdeemph_override_17_12);
2720                 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
2721
2722                 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
2723                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2724                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2725                         ddi_translations[level].cri_txdeemph_override_17_12);
2726                 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
2727         }
2728
2729         /* Program MG_TX_DRVCTRL with values from vswing table */
2730         for (ln = 0; ln < 2; ln++) {
2731                 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
2732                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2733                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2734                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2735                         ddi_translations[level].cri_txdeemph_override_5_0) |
2736                         CRI_TXDEEMPH_OVERRIDE_11_6(
2737                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2738                         CRI_TXDEEMPH_OVERRIDE_EN;
2739                 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
2740
2741                 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
2742                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2743                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2744                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2745                         ddi_translations[level].cri_txdeemph_override_5_0) |
2746                         CRI_TXDEEMPH_OVERRIDE_11_6(
2747                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2748                         CRI_TXDEEMPH_OVERRIDE_EN;
2749                 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
2750
2751                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2752         }
2753
2754         /*
2755          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2756          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2757          * values from table for which TX1 and TX2 enabled.
2758          */
2759         for (ln = 0; ln < 2; ln++) {
2760                 val = I915_READ(MG_CLKHUB(ln, tc_port));
2761                 if (link_clock < 300000)
2762                         val |= CFG_LOW_RATE_LKREN_EN;
2763                 else
2764                         val &= ~CFG_LOW_RATE_LKREN_EN;
2765                 I915_WRITE(MG_CLKHUB(ln, tc_port), val);
2766         }
2767
2768         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2769         for (ln = 0; ln < 2; ln++) {
2770                 val = I915_READ(MG_TX1_DCC(ln, tc_port));
2771                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2772                 if (link_clock <= 500000) {
2773                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2774                 } else {
2775                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2776                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2777                 }
2778                 I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
2779
2780                 val = I915_READ(MG_TX2_DCC(ln, tc_port));
2781                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2782                 if (link_clock <= 500000) {
2783                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2784                 } else {
2785                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2786                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2787                 }
2788                 I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
2789         }
2790
2791         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2792         for (ln = 0; ln < 2; ln++) {
2793                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
2794                 val |= CRI_CALCINIT;
2795                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
2796
2797                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
2798                 val |= CRI_CALCINIT;
2799                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
2800         }
2801 }
2802
2803 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2804                                     int link_clock,
2805                                     u32 level,
2806                                     enum intel_output_type type)
2807 {
2808         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2809         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2810
2811         if (intel_phy_is_combo(dev_priv, phy))
2812                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2813         else
2814                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2815 }
2816
2817 static void
2818 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2819                                 u32 level)
2820 {
2821         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2822         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2823         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2824         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2825
2826         n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
2827         ddi_translations = tgl_dkl_phy_ddi_translations;
2828
2829         if (level >= n_entries)
2830                 level = n_entries - 1;
2831
2832         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2833                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2834                       DKL_TX_VSWING_CONTROL_MASK);
2835         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2836         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2837         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2838
2839         for (ln = 0; ln < 2; ln++) {
2840                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
2841
2842                 I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);
2843
2844                 /* All the registers are RMW */
2845                 val = I915_READ(DKL_TX_DPCNTL0(tc_port));
2846                 val &= ~dpcnt_mask;
2847                 val |= dpcnt_val;
2848                 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
2849
2850                 val = I915_READ(DKL_TX_DPCNTL1(tc_port));
2851                 val &= ~dpcnt_mask;
2852                 val |= dpcnt_val;
2853                 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
2854
2855                 val = I915_READ(DKL_TX_DPCNTL2(tc_port));
2856                 val &= ~DKL_TX_DP20BITMODE;
2857                 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
2858         }
2859 }
2860
2861 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2862                                     int link_clock,
2863                                     u32 level,
2864                                     enum intel_output_type type)
2865 {
2866         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2867         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2868
2869         if (intel_phy_is_combo(dev_priv, phy))
2870                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2871         else
2872                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2873 }
2874
2875 static u32 translate_signal_level(int signal_levels)
2876 {
2877         int i;
2878
2879         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2880                 if (index_to_dp_signal_levels[i] == signal_levels)
2881                         return i;
2882         }
2883
2884         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2885              signal_levels);
2886
2887         return 0;
2888 }
2889
2890 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2891 {
2892         u8 train_set = intel_dp->train_set[0];
2893         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2894                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2895
2896         return translate_signal_level(signal_levels);
2897 }
2898
2899 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2900 {
2901         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2902         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2903         struct intel_encoder *encoder = &dport->base;
2904         int level = intel_ddi_dp_level(intel_dp);
2905
2906         if (INTEL_GEN(dev_priv) >= 12)
2907                 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2908                                         level, encoder->type);
2909         else if (INTEL_GEN(dev_priv) >= 11)
2910                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2911                                         level, encoder->type);
2912         else if (IS_CANNONLAKE(dev_priv))
2913                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2914         else
2915                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2916
2917         return 0;
2918 }
2919
2920 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2921 {
2922         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2923         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2924         struct intel_encoder *encoder = &dport->base;
2925         int level = intel_ddi_dp_level(intel_dp);
2926
2927         if (IS_GEN9_BC(dev_priv))
2928                 skl_ddi_set_iboost(encoder, level, encoder->type);
2929
2930         return DDI_BUF_TRANS_SELECT(level);
2931 }
2932
2933 static inline
2934 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2935                               enum phy phy)
2936 {
2937         if (intel_phy_is_combo(dev_priv, phy)) {
2938                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2939         } else if (intel_phy_is_tc(dev_priv, phy)) {
2940                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2941                                                         (enum port)phy);
2942
2943                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2944         }
2945
2946         return 0;
2947 }
2948
2949 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2950                                   const struct intel_crtc_state *crtc_state)
2951 {
2952         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2953         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2954         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2955         u32 val;
2956
2957         mutex_lock(&dev_priv->dpll_lock);
2958
2959         val = I915_READ(ICL_DPCLKA_CFGCR0);
2960         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2961
2962         if (intel_phy_is_combo(dev_priv, phy)) {
2963                 /*
2964                  * Even though this register references DDIs, note that we
2965                  * want to pass the PHY rather than the port (DDI).  For
2966                  * ICL, port=phy in all cases so it doesn't matter, but for
2967                  * EHL the bspec notes the following:
2968                  *
2969                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2970                  *   Clock Select chooses the PLL for both DDIA and DDID and
2971                  *   drives port A in all cases."
2972                  */
2973                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2974                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2975                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2976                 POSTING_READ(ICL_DPCLKA_CFGCR0);
2977         }
2978
2979         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2980         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2981
2982         mutex_unlock(&dev_priv->dpll_lock);
2983 }
2984
2985 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2986 {
2987         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2988         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2989         u32 val;
2990
2991         mutex_lock(&dev_priv->dpll_lock);
2992
2993         val = I915_READ(ICL_DPCLKA_CFGCR0);
2994         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2995         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2996
2997         mutex_unlock(&dev_priv->dpll_lock);
2998 }
2999
3000 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3001 {
3002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3003         u32 val;
3004         enum port port;
3005         u32 port_mask;
3006         bool ddi_clk_needed;
3007
3008         /*
3009          * In case of DP MST, we sanitize the primary encoder only, not the
3010          * virtual ones.
3011          */
3012         if (encoder->type == INTEL_OUTPUT_DP_MST)
3013                 return;
3014
3015         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3016                 u8 pipe_mask;
3017                 bool is_mst;
3018
3019                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3020                 /*
3021                  * In the unlikely case that BIOS enables DP in MST mode, just
3022                  * warn since our MST HW readout is incomplete.
3023                  */
3024                 if (WARN_ON(is_mst))
3025                         return;
3026         }
3027
3028         port_mask = BIT(encoder->port);
3029         ddi_clk_needed = encoder->base.crtc;
3030
3031         if (encoder->type == INTEL_OUTPUT_DSI) {
3032                 struct intel_encoder *other_encoder;
3033
3034                 port_mask = intel_dsi_encoder_ports(encoder);
3035                 /*
3036                  * Sanity check that we haven't incorrectly registered another
3037                  * encoder using any of the ports of this DSI encoder.
3038                  */
3039                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3040                         if (other_encoder == encoder)
3041                                 continue;
3042
3043                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
3044                                 return;
3045                 }
3046                 /*
3047                  * For DSI we keep the ddi clocks gated
3048                  * except during enable/disable sequence.
3049                  */
3050                 ddi_clk_needed = false;
3051         }
3052
3053         val = I915_READ(ICL_DPCLKA_CFGCR0);
3054         for_each_port_masked(port, port_mask) {
3055                 enum phy phy = intel_port_to_phy(dev_priv, port);
3056
3057                 bool ddi_clk_ungated = !(val &
3058                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
3059                                                                    phy));
3060
3061                 if (ddi_clk_needed == ddi_clk_ungated)
3062                         continue;
3063
3064                 /*
3065                  * Punt on the case now where clock is gated, but it would
3066                  * be needed by the port. Something else is really broken then.
3067                  */
3068                 if (WARN_ON(ddi_clk_needed))
3069                         continue;
3070
3071                 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
3072                          phy_name(port));
3073                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3074                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3075         }
3076 }
3077
3078 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3079                                  const struct intel_crtc_state *crtc_state)
3080 {
3081         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3082         enum port port = encoder->port;
3083         enum phy phy = intel_port_to_phy(dev_priv, port);
3084         u32 val;
3085         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3086
3087         if (WARN_ON(!pll))
3088                 return;
3089
3090         mutex_lock(&dev_priv->dpll_lock);
3091
3092         if (INTEL_GEN(dev_priv) >= 11) {
3093                 if (!intel_phy_is_combo(dev_priv, phy))
3094                         I915_WRITE(DDI_CLK_SEL(port),
3095                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3096                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3097                         /*
3098                          * MG does not exist but the programming is required
3099                          * to ungate DDIC and DDID
3100                          */
3101                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
3102         } else if (IS_CANNONLAKE(dev_priv)) {
3103                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3104                 val = I915_READ(DPCLKA_CFGCR0);
3105                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3106                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3107                 I915_WRITE(DPCLKA_CFGCR0, val);
3108
3109                 /*
3110                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3111                  * This step and the step before must be done with separate
3112                  * register writes.
3113                  */
3114                 val = I915_READ(DPCLKA_CFGCR0);
3115                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3116                 I915_WRITE(DPCLKA_CFGCR0, val);
3117         } else if (IS_GEN9_BC(dev_priv)) {
3118                 /* DDI -> PLL mapping  */
3119                 val = I915_READ(DPLL_CTRL2);
3120
3121                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3122                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3123                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3124                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3125
3126                 I915_WRITE(DPLL_CTRL2, val);
3127
3128         } else if (INTEL_GEN(dev_priv) < 9) {
3129                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
3130         }
3131
3132         mutex_unlock(&dev_priv->dpll_lock);
3133 }
3134
3135 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3136 {
3137         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3138         enum port port = encoder->port;
3139         enum phy phy = intel_port_to_phy(dev_priv, port);
3140
3141         if (INTEL_GEN(dev_priv) >= 11) {
3142                 if (!intel_phy_is_combo(dev_priv, phy) ||
3143                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3144                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3145         } else if (IS_CANNONLAKE(dev_priv)) {
3146                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3147                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3148         } else if (IS_GEN9_BC(dev_priv)) {
3149                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3150                            DPLL_CTRL2_DDI_CLK_OFF(port));
3151         } else if (INTEL_GEN(dev_priv) < 9) {
3152                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3153         }
3154 }
3155
3156 static void
3157 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
3158 {
3159         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3160         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3161         u32 val, bits;
3162         int ln;
3163
3164         if (tc_port == PORT_TC_NONE)
3165                 return;
3166
3167         bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
3168                MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
3169                MG_DP_MODE_CFG_GAONPWR_GATING;
3170
3171         for (ln = 0; ln < 2; ln++) {
3172                 if (INTEL_GEN(dev_priv) >= 12) {
3173                         I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
3174                         val = I915_READ(DKL_DP_MODE(tc_port));
3175                 } else {
3176                         val = I915_READ(MG_DP_MODE(ln, tc_port));
3177                 }
3178
3179                 if (enable)
3180                         val |= bits;
3181                 else
3182                         val &= ~bits;
3183
3184                 if (INTEL_GEN(dev_priv) >= 12)
3185                         I915_WRITE(DKL_DP_MODE(tc_port), val);
3186                 else
3187                         I915_WRITE(MG_DP_MODE(ln, tc_port), val);
3188         }
3189
3190         if (INTEL_GEN(dev_priv) == 11) {
3191                 bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
3192                        MG_MISC_SUS0_CFG_CL2PWR_GATING |
3193                        MG_MISC_SUS0_CFG_GAONPWR_GATING |
3194                        MG_MISC_SUS0_CFG_TRPWR_GATING |
3195                        MG_MISC_SUS0_CFG_CL1PWR_GATING |
3196                        MG_MISC_SUS0_CFG_DGPWR_GATING;
3197
3198                 val = I915_READ(MG_MISC_SUS0(tc_port));
3199                 if (enable)
3200                         val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
3201                 else
3202                         val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
3203                 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3204         }
3205 }
3206
3207 static void
3208 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
3209                        const struct intel_crtc_state *crtc_state)
3210 {
3211         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3212         enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
3213         u32 ln0, ln1, pin_assignment;
3214         u8 width;
3215
3216         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3217                 return;
3218
3219         if (INTEL_GEN(dev_priv) >= 12) {
3220                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3221                 ln0 = I915_READ(DKL_DP_MODE(tc_port));
3222                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3223                 ln1 = I915_READ(DKL_DP_MODE(tc_port));
3224         } else {
3225                 ln0 = I915_READ(MG_DP_MODE(0, tc_port));
3226                 ln1 = I915_READ(MG_DP_MODE(1, tc_port));
3227         }
3228
3229         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
3230         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3231
3232         /* DPPATC */
3233         pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
3234         width = crtc_state->lane_count;
3235
3236         switch (pin_assignment) {
3237         case 0x0:
3238                 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
3239                 if (width == 1) {
3240                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3241                 } else {
3242                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3243                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3244                 }
3245                 break;
3246         case 0x1:
3247                 if (width == 4) {
3248                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3249                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3250                 }
3251                 break;
3252         case 0x2:
3253                 if (width == 2) {
3254                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3255                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3256                 }
3257                 break;
3258         case 0x3:
3259         case 0x5:
3260                 if (width == 1) {
3261                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3262                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3263                 } else {
3264                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3265                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3266                 }
3267                 break;
3268         case 0x4:
3269         case 0x6:
3270                 if (width == 1) {
3271                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3272                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3273                 } else {
3274                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3275                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3276                 }
3277                 break;
3278         default:
3279                 MISSING_CASE(pin_assignment);
3280         }
3281
3282         if (INTEL_GEN(dev_priv) >= 12) {
3283                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3284                 I915_WRITE(DKL_DP_MODE(tc_port), ln0);
3285                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3286                 I915_WRITE(DKL_DP_MODE(tc_port), ln1);
3287         } else {
3288                 I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
3289                 I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
3290         }
3291 }
3292
3293 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3294                                         const struct intel_crtc_state *crtc_state)
3295 {
3296         if (!crtc_state->fec_enable)
3297                 return;
3298
3299         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3300                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3301 }
3302
3303 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3304                                  const struct intel_crtc_state *crtc_state)
3305 {
3306         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3307         struct intel_dp *intel_dp;
3308         u32 val;
3309
3310         if (!crtc_state->fec_enable)
3311                 return;
3312
3313         intel_dp = enc_to_intel_dp(&encoder->base);
3314         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3315         val |= DP_TP_CTL_FEC_ENABLE;
3316         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3317
3318         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3319                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3320                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3321 }
3322
3323 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3324                                         const struct intel_crtc_state *crtc_state)
3325 {
3326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3327         struct intel_dp *intel_dp;
3328         u32 val;
3329
3330         if (!crtc_state->fec_enable)
3331                 return;
3332
3333         intel_dp = enc_to_intel_dp(&encoder->base);
3334         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3335         val &= ~DP_TP_CTL_FEC_ENABLE;
3336         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3337         POSTING_READ(intel_dp->regs.dp_tp_ctl);
3338 }
3339
3340 static void
3341 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3342 {
3343         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3344         u32 val;
3345
3346         if (!cstate->dc3co_exitline)
3347                 return;
3348
3349         val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3350         val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3351         I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3352 }
3353
3354 static void
3355 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3356 {
3357         u32 val, exit_scanlines;
3358         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3359
3360         if (!cstate->dc3co_exitline)
3361                 return;
3362
3363         exit_scanlines = cstate->dc3co_exitline;
3364         exit_scanlines <<= EXITLINE_SHIFT;
3365         val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3366         val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3367         val |= exit_scanlines;
3368         val |= EXITLINE_ENABLE;
3369         I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3370 }
3371
3372 static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
3373                                               struct intel_crtc_state *cstate)
3374 {
3375         u32 exit_scanlines;
3376         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3377         u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
3378
3379         cstate->dc3co_exitline = 0;
3380
3381         if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
3382                 return;
3383
3384         /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
3385         if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
3386             encoder->port != PORT_A)
3387                 return;
3388
3389         if (!cstate->has_psr2 || !cstate->base.active)
3390                 return;
3391
3392         /*
3393          * DC3CO Exit time 200us B.Spec 49196
3394          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
3395          */
3396         exit_scanlines =
3397                 intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1;
3398
3399         if (WARN_ON(exit_scanlines > crtc_vdisplay))
3400                 return;
3401
3402         cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
3403         DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
3404 }
3405
3406 static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
3407 {
3408         u32 val;
3409         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3410
3411         if (INTEL_GEN(dev_priv) < 12)
3412                 return;
3413
3414         val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
3415
3416         if (val & EXITLINE_ENABLE)
3417                 crtc_state->dc3co_exitline = val & EXITLINE_MASK;
3418 }
3419
3420 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3421                                   const struct intel_crtc_state *crtc_state,
3422                                   const struct drm_connector_state *conn_state)
3423 {
3424         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3425         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3426         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3427         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3428         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3429         int level = intel_ddi_dp_level(intel_dp);
3430         enum transcoder transcoder = crtc_state->cpu_transcoder;
3431
3432         tgl_set_psr2_transcoder_exitline(crtc_state);
3433         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3434                                  crtc_state->lane_count, is_mst);
3435
3436         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3437         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3438
3439         /* 1.a got on intel_atomic_commit_tail() */
3440
3441         /* 2. */
3442         intel_edp_panel_on(intel_dp);
3443
3444         /*
3445          * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
3446          * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
3447          * haswell_crtc_enable()->intel_enable_shared_dpll()
3448          */
3449
3450         /* 4.b */
3451         intel_ddi_clk_select(encoder, crtc_state);
3452
3453         /* 5. */
3454         if (!intel_phy_is_tc(dev_priv, phy) ||
3455             dig_port->tc_mode != TC_PORT_TBT_ALT)
3456                 intel_display_power_get(dev_priv,
3457                                         dig_port->ddi_io_power_domain);
3458
3459         /* 6. */
3460         icl_program_mg_dp_mode(dig_port, crtc_state);
3461
3462         /*
3463          * 7.a - Steps in this function should only be executed over MST
3464          * master, what will be taken in care by MST hook
3465          * intel_mst_pre_enable_dp()
3466          */
3467         intel_ddi_enable_pipe_clock(crtc_state);
3468
3469         /* 7.b */
3470         intel_ddi_config_transcoder_func(crtc_state);
3471
3472         /* 7.d */
3473         icl_phy_set_clock_gating(dig_port, false);
3474
3475         /* 7.e */
3476         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3477                                 encoder->type);
3478
3479         /* 7.f */
3480         if (intel_phy_is_combo(dev_priv, phy)) {
3481                 bool lane_reversal =
3482                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3483
3484                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3485                                                crtc_state->lane_count,
3486                                                lane_reversal);
3487         }
3488
3489         /* 7.g */
3490         intel_ddi_init_dp_buf_reg(encoder);
3491
3492         if (!is_mst)
3493                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3494
3495         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3496         /*
3497          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3498          * in the FEC_CONFIGURATION register to 1 before initiating link
3499          * training
3500          */
3501         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3502         /* 7.c, 7.h, 7.i, 7.j */
3503         intel_dp_start_link_train(intel_dp);
3504
3505         /* 7.k */
3506         if (!is_trans_port_sync_mode(crtc_state))
3507                 intel_dp_stop_link_train(intel_dp);
3508
3509         /*
3510          * TODO: enable clock gating
3511          *
3512          * It is not written in DP enabling sequence but "PHY Clockgating
3513          * programming" states that clock gating should be enabled after the
3514          * link training but doing so causes all the following trainings to fail
3515          * so not enabling it for now.
3516          */
3517
3518         /* 7.l */
3519         intel_ddi_enable_fec(encoder, crtc_state);
3520         intel_dsc_enable(encoder, crtc_state);
3521 }
3522
3523 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3524                                   const struct intel_crtc_state *crtc_state,
3525                                   const struct drm_connector_state *conn_state)
3526 {
3527         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3528         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3529         enum port port = encoder->port;
3530         enum phy phy = intel_port_to_phy(dev_priv, port);
3531         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3532         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3533         int level = intel_ddi_dp_level(intel_dp);
3534
3535         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3536
3537         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3538                                  crtc_state->lane_count, is_mst);
3539
3540         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3541         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3542
3543         intel_edp_panel_on(intel_dp);
3544
3545         intel_ddi_clk_select(encoder, crtc_state);
3546
3547         if (!intel_phy_is_tc(dev_priv, phy) ||
3548             dig_port->tc_mode != TC_PORT_TBT_ALT)
3549                 intel_display_power_get(dev_priv,
3550                                         dig_port->ddi_io_power_domain);
3551
3552         icl_program_mg_dp_mode(dig_port, crtc_state);
3553         icl_phy_set_clock_gating(dig_port, false);
3554
3555         if (INTEL_GEN(dev_priv) >= 11)
3556                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3557                                         level, encoder->type);
3558         else if (IS_CANNONLAKE(dev_priv))
3559                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3560         else if (IS_GEN9_LP(dev_priv))
3561                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3562         else
3563                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3564
3565         if (intel_phy_is_combo(dev_priv, phy)) {
3566                 bool lane_reversal =
3567                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3568
3569                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3570                                                crtc_state->lane_count,
3571                                                lane_reversal);
3572         }
3573
3574         intel_ddi_init_dp_buf_reg(encoder);
3575         if (!is_mst)
3576                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3577         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3578                                               true);
3579         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3580         intel_dp_start_link_train(intel_dp);
3581         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3582             !is_trans_port_sync_mode(crtc_state))
3583                 intel_dp_stop_link_train(intel_dp);
3584
3585         intel_ddi_enable_fec(encoder, crtc_state);
3586
3587         icl_phy_set_clock_gating(dig_port, true);
3588
3589         if (!is_mst)
3590                 intel_ddi_enable_pipe_clock(crtc_state);
3591
3592         intel_dsc_enable(encoder, crtc_state);
3593 }
3594
3595 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3596                                     const struct intel_crtc_state *crtc_state,
3597                                     const struct drm_connector_state *conn_state)
3598 {
3599         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3600
3601         if (INTEL_GEN(dev_priv) >= 12)
3602                 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3603         else
3604                 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3605
3606         /* MST will call a setting of MSA after an allocating of Virtual Channel
3607          * from MST encoder pre_enable callback.
3608          */
3609         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
3610                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3611 }
3612
3613 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3614                                       const struct intel_crtc_state *crtc_state,
3615                                       const struct drm_connector_state *conn_state)
3616 {
3617         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3618         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3619         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3620         enum port port = encoder->port;
3621         int level = intel_ddi_hdmi_level(dev_priv, port);
3622         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3623
3624         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3625         intel_ddi_clk_select(encoder, crtc_state);
3626
3627         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3628
3629         icl_program_mg_dp_mode(dig_port, crtc_state);
3630         icl_phy_set_clock_gating(dig_port, false);
3631
3632         if (INTEL_GEN(dev_priv) >= 12)
3633                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3634                                         level, INTEL_OUTPUT_HDMI);
3635         else if (INTEL_GEN(dev_priv) == 11)
3636                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3637                                         level, INTEL_OUTPUT_HDMI);
3638         else if (IS_CANNONLAKE(dev_priv))
3639                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3640         else if (IS_GEN9_LP(dev_priv))
3641                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3642         else
3643                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3644
3645         icl_phy_set_clock_gating(dig_port, true);
3646
3647         if (IS_GEN9_BC(dev_priv))
3648                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3649
3650         intel_ddi_enable_pipe_clock(crtc_state);
3651
3652         intel_dig_port->set_infoframes(encoder,
3653                                        crtc_state->has_infoframe,
3654                                        crtc_state, conn_state);
3655 }
3656
3657 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3658                                  const struct intel_crtc_state *crtc_state,
3659                                  const struct drm_connector_state *conn_state)
3660 {
3661         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3662         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3663         enum pipe pipe = crtc->pipe;
3664
3665         /*
3666          * When called from DP MST code:
3667          * - conn_state will be NULL
3668          * - encoder will be the main encoder (ie. mst->primary)
3669          * - the main connector associated with this port
3670          *   won't be active or linked to a crtc
3671          * - crtc_state will be the state of the first stream to
3672          *   be activated on this port, and it may not be the same
3673          *   stream that will be deactivated last, but each stream
3674          *   should have a state that is identical when it comes to
3675          *   the DP link parameteres
3676          */
3677
3678         WARN_ON(crtc_state->has_pch_encoder);
3679
3680         if (INTEL_GEN(dev_priv) >= 11)
3681                 icl_map_plls_to_ports(encoder, crtc_state);
3682
3683         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3684
3685         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3686                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3687         } else {
3688                 struct intel_lspcon *lspcon =
3689                                 enc_to_intel_lspcon(&encoder->base);
3690
3691                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3692                 if (lspcon->active) {
3693                         struct intel_digital_port *dig_port =
3694                                         enc_to_dig_port(&encoder->base);
3695
3696                         dig_port->set_infoframes(encoder,
3697                                                  crtc_state->has_infoframe,
3698                                                  crtc_state, conn_state);
3699                 }
3700         }
3701 }
3702
3703 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3704                                   const struct intel_crtc_state *crtc_state)
3705 {
3706         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3707         enum port port = encoder->port;
3708         bool wait = false;
3709         u32 val;
3710
3711         val = I915_READ(DDI_BUF_CTL(port));
3712         if (val & DDI_BUF_CTL_ENABLE) {
3713                 val &= ~DDI_BUF_CTL_ENABLE;
3714                 I915_WRITE(DDI_BUF_CTL(port), val);
3715                 wait = true;
3716         }
3717
3718         if (intel_crtc_has_dp_encoder(crtc_state)) {
3719                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3720
3721                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3722                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3723                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3724                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3725         }
3726
3727         /* Disable FEC in DP Sink */
3728         intel_ddi_disable_fec_state(encoder, crtc_state);
3729
3730         if (wait)
3731                 intel_wait_ddi_buf_idle(dev_priv, port);
3732 }
3733
3734 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3735                                       const struct intel_crtc_state *old_crtc_state,
3736                                       const struct drm_connector_state *old_conn_state)
3737 {
3738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3739         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3740         struct intel_dp *intel_dp = &dig_port->dp;
3741         bool is_mst = intel_crtc_has_type(old_crtc_state,
3742                                           INTEL_OUTPUT_DP_MST);
3743         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3744
3745         if (!is_mst) {
3746                 intel_ddi_disable_pipe_clock(old_crtc_state);
3747                 /*
3748                  * Power down sink before disabling the port, otherwise we end
3749                  * up getting interrupts from the sink on detecting link loss.
3750                  */
3751                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3752         }
3753
3754         intel_disable_ddi_buf(encoder, old_crtc_state);
3755
3756         intel_edp_panel_vdd_on(intel_dp);
3757         intel_edp_panel_off(intel_dp);
3758
3759         if (!intel_phy_is_tc(dev_priv, phy) ||
3760             dig_port->tc_mode != TC_PORT_TBT_ALT)
3761                 intel_display_power_put_unchecked(dev_priv,
3762                                                   dig_port->ddi_io_power_domain);
3763
3764         intel_ddi_clk_disable(encoder);
3765         tgl_clear_psr2_transcoder_exitline(old_crtc_state);
3766 }
3767
3768 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3769                                         const struct intel_crtc_state *old_crtc_state,
3770                                         const struct drm_connector_state *old_conn_state)
3771 {
3772         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3773         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3774         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3775
3776         dig_port->set_infoframes(encoder, false,
3777                                  old_crtc_state, old_conn_state);
3778
3779         intel_ddi_disable_pipe_clock(old_crtc_state);
3780
3781         intel_disable_ddi_buf(encoder, old_crtc_state);
3782
3783         intel_display_power_put_unchecked(dev_priv,
3784                                           dig_port->ddi_io_power_domain);
3785
3786         intel_ddi_clk_disable(encoder);
3787
3788         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3789 }
3790
3791 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3792                                    const struct intel_crtc_state *old_crtc_state,
3793                                    const struct drm_connector_state *old_conn_state)
3794 {
3795         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3796
3797         /*
3798          * When called from DP MST code:
3799          * - old_conn_state will be NULL
3800          * - encoder will be the main encoder (ie. mst->primary)
3801          * - the main connector associated with this port
3802          *   won't be active or linked to a crtc
3803          * - old_crtc_state will be the state of the last stream to
3804          *   be deactivated on this port, and it may not be the same
3805          *   stream that was activated last, but each stream
3806          *   should have a state that is identical when it comes to
3807          *   the DP link parameteres
3808          */
3809
3810         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3811                 intel_ddi_post_disable_hdmi(encoder,
3812                                             old_crtc_state, old_conn_state);
3813         else
3814                 intel_ddi_post_disable_dp(encoder,
3815                                           old_crtc_state, old_conn_state);
3816
3817         if (INTEL_GEN(dev_priv) >= 11)
3818                 icl_unmap_plls_to_ports(encoder);
3819 }
3820
3821 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3822                                 const struct intel_crtc_state *old_crtc_state,
3823                                 const struct drm_connector_state *old_conn_state)
3824 {
3825         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3826         u32 val;
3827
3828         /*
3829          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3830          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3831          * step 13 is the correct place for it. Step 18 is where it was
3832          * originally before the BUN.
3833          */
3834         val = I915_READ(FDI_RX_CTL(PIPE_A));
3835         val &= ~FDI_RX_ENABLE;
3836         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3837
3838         intel_disable_ddi_buf(encoder, old_crtc_state);
3839         intel_ddi_clk_disable(encoder);
3840
3841         val = I915_READ(FDI_RX_MISC(PIPE_A));
3842         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3843         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3844         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3845
3846         val = I915_READ(FDI_RX_CTL(PIPE_A));
3847         val &= ~FDI_PCDCLK;
3848         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3849
3850         val = I915_READ(FDI_RX_CTL(PIPE_A));
3851         val &= ~FDI_RX_PLL_ENABLE;
3852         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3853 }
3854
3855 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3856                                 const struct intel_crtc_state *crtc_state,
3857                                 const struct drm_connector_state *conn_state)
3858 {
3859         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3860         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3861         enum port port = encoder->port;
3862
3863         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3864                 intel_dp_stop_link_train(intel_dp);
3865
3866         intel_edp_backlight_on(crtc_state, conn_state);
3867         intel_psr_enable(intel_dp, crtc_state);
3868         intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3869         intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3870         intel_edp_drrs_enable(intel_dp, crtc_state);
3871
3872         if (crtc_state->has_audio)
3873                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3874 }
3875
3876 static i915_reg_t
3877 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3878                                enum port port)
3879 {
3880         static const enum transcoder trans[] = {
3881                 [PORT_A] = TRANSCODER_EDP,
3882                 [PORT_B] = TRANSCODER_A,
3883                 [PORT_C] = TRANSCODER_B,
3884                 [PORT_D] = TRANSCODER_C,
3885                 [PORT_E] = TRANSCODER_A,
3886         };
3887
3888         WARN_ON(INTEL_GEN(dev_priv) < 9);
3889
3890         if (WARN_ON(port < PORT_A || port > PORT_E))
3891                 port = PORT_A;
3892
3893         return CHICKEN_TRANS(trans[port]);
3894 }
3895
3896 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3897                                   const struct intel_crtc_state *crtc_state,
3898                                   const struct drm_connector_state *conn_state)
3899 {
3900         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3901         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3902         struct drm_connector *connector = conn_state->connector;
3903         enum port port = encoder->port;
3904
3905         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3906                                                crtc_state->hdmi_high_tmds_clock_ratio,
3907                                                crtc_state->hdmi_scrambling))
3908                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3909                           connector->base.id, connector->name);
3910
3911         /* Display WA #1143: skl,kbl,cfl */
3912         if (IS_GEN9_BC(dev_priv)) {
3913                 /*
3914                  * For some reason these chicken bits have been
3915                  * stuffed into a transcoder register, event though
3916                  * the bits affect a specific DDI port rather than
3917                  * a specific transcoder.
3918                  */
3919                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3920                 u32 val;
3921
3922                 val = I915_READ(reg);
3923
3924                 if (port == PORT_E)
3925                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3926                                 DDIE_TRAINING_OVERRIDE_VALUE;
3927                 else
3928                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3929                                 DDI_TRAINING_OVERRIDE_VALUE;
3930
3931                 I915_WRITE(reg, val);
3932                 POSTING_READ(reg);
3933
3934                 udelay(1);
3935
3936                 if (port == PORT_E)
3937                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3938                                  DDIE_TRAINING_OVERRIDE_VALUE);
3939                 else
3940                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3941                                  DDI_TRAINING_OVERRIDE_VALUE);
3942
3943                 I915_WRITE(reg, val);
3944         }
3945
3946         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3947          * are ignored so nothing special needs to be done besides
3948          * enabling the port.
3949          */
3950         I915_WRITE(DDI_BUF_CTL(port),
3951                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3952
3953         if (crtc_state->has_audio)
3954                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3955 }
3956
3957 static void intel_enable_ddi(struct intel_encoder *encoder,
3958                              const struct intel_crtc_state *crtc_state,
3959                              const struct drm_connector_state *conn_state)
3960 {
3961         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3962                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3963         else
3964                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3965
3966         /* Enable hdcp if it's desired */
3967         if (conn_state->content_protection ==
3968             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3969                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3970                                   (u8)conn_state->hdcp_content_type);
3971 }
3972
3973 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3974                                  const struct intel_crtc_state *old_crtc_state,
3975                                  const struct drm_connector_state *old_conn_state)
3976 {
3977         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3978
3979         intel_dp->link_trained = false;
3980
3981         if (old_crtc_state->has_audio)
3982                 intel_audio_codec_disable(encoder,
3983                                           old_crtc_state, old_conn_state);
3984
3985         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3986         intel_psr_disable(intel_dp, old_crtc_state);
3987         intel_edp_backlight_off(old_conn_state);
3988         /* Disable the decompression in DP Sink */
3989         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3990                                               false);
3991 }
3992
3993 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3994                                    const struct intel_crtc_state *old_crtc_state,
3995                                    const struct drm_connector_state *old_conn_state)
3996 {
3997         struct drm_connector *connector = old_conn_state->connector;
3998
3999         if (old_crtc_state->has_audio)
4000                 intel_audio_codec_disable(encoder,
4001                                           old_crtc_state, old_conn_state);
4002
4003         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4004                                                false, false))
4005                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4006                               connector->base.id, connector->name);
4007 }
4008
4009 static void intel_disable_ddi(struct intel_encoder *encoder,
4010                               const struct intel_crtc_state *old_crtc_state,
4011                               const struct drm_connector_state *old_conn_state)
4012 {
4013         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4014
4015         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4016                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
4017         else
4018                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
4019 }
4020
4021 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
4022                                      const struct intel_crtc_state *crtc_state,
4023                                      const struct drm_connector_state *conn_state)
4024 {
4025         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4026
4027         intel_ddi_set_dp_msa(crtc_state, conn_state);
4028
4029         intel_psr_update(intel_dp, crtc_state);
4030         intel_edp_drrs_enable(intel_dp, crtc_state);
4031
4032         intel_panel_update_backlight(encoder, crtc_state, conn_state);
4033 }
4034
4035 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
4036                                   const struct intel_crtc_state *crtc_state,
4037                                   const struct drm_connector_state *conn_state)
4038 {
4039         struct intel_connector *connector =
4040                                 to_intel_connector(conn_state->connector);
4041         struct intel_hdcp *hdcp = &connector->hdcp;
4042         bool content_protection_type_changed =
4043                         (conn_state->hdcp_content_type != hdcp->content_type &&
4044                          conn_state->content_protection !=
4045                          DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
4046
4047         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4048                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
4049
4050         /*
4051          * During the HDCP encryption session if Type change is requested,
4052          * disable the HDCP and reenable it with new TYPE value.
4053          */
4054         if (conn_state->content_protection ==
4055             DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
4056             content_protection_type_changed)
4057                 intel_hdcp_disable(connector);
4058
4059         /*
4060          * Mark the hdcp state as DESIRED after the hdcp disable of type
4061          * change procedure.
4062          */
4063         if (content_protection_type_changed) {
4064                 mutex_lock(&hdcp->mutex);
4065                 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
4066                 schedule_work(&hdcp->prop_work);
4067                 mutex_unlock(&hdcp->mutex);
4068         }
4069
4070         if (conn_state->content_protection ==
4071             DRM_MODE_CONTENT_PROTECTION_DESIRED ||
4072             content_protection_type_changed)
4073                 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
4074 }
4075
4076 static void
4077 intel_ddi_update_prepare(struct intel_atomic_state *state,
4078                          struct intel_encoder *encoder,
4079                          struct intel_crtc *crtc)
4080 {
4081         struct intel_crtc_state *crtc_state =
4082                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4083         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4084
4085         WARN_ON(crtc && crtc->active);
4086
4087         intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
4088         if (crtc_state && crtc_state->base.active)
4089                 intel_update_active_dpll(state, crtc, encoder);
4090 }
4091
4092 static void
4093 intel_ddi_update_complete(struct intel_atomic_state *state,
4094                           struct intel_encoder *encoder,
4095                           struct intel_crtc *crtc)
4096 {
4097         intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
4098 }
4099
4100 static void
4101 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
4102                          const struct intel_crtc_state *crtc_state,
4103                          const struct drm_connector_state *conn_state)
4104 {
4105         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4106         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4107         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4108         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4109
4110         if (is_tc_port)
4111                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4112
4113         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4114                 intel_display_power_get(dev_priv,
4115                                         intel_ddi_main_link_aux_domain(dig_port));
4116
4117         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4118                 /*
4119                  * Program the lane count for static/dynamic connections on
4120                  * Type-C ports.  Skip this step for TBT.
4121                  */
4122                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4123         else if (IS_GEN9_LP(dev_priv))
4124                 bxt_ddi_phy_set_lane_optim_mask(encoder,
4125                                                 crtc_state->lane_lat_optim_mask);
4126 }
4127
4128 static void
4129 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
4130                            const struct intel_crtc_state *crtc_state,
4131                            const struct drm_connector_state *conn_state)
4132 {
4133         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4134         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4135         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4136         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4137
4138         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4139                 intel_display_power_put_unchecked(dev_priv,
4140                                                   intel_ddi_main_link_aux_domain(dig_port));
4141
4142         if (is_tc_port)
4143                 intel_tc_port_put_link(dig_port);
4144 }
4145
4146 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4147 {
4148         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4149         struct drm_i915_private *dev_priv =
4150                 to_i915(intel_dig_port->base.base.dev);
4151         enum port port = intel_dig_port->base.port;
4152         u32 val;
4153         bool wait = false;
4154
4155         if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
4156                 val = I915_READ(DDI_BUF_CTL(port));
4157                 if (val & DDI_BUF_CTL_ENABLE) {
4158                         val &= ~DDI_BUF_CTL_ENABLE;
4159                         I915_WRITE(DDI_BUF_CTL(port), val);
4160                         wait = true;
4161                 }
4162
4163                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
4164                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4165                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
4166                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4167                 POSTING_READ(intel_dp->regs.dp_tp_ctl);
4168
4169                 if (wait)
4170                         intel_wait_ddi_buf_idle(dev_priv, port);
4171         }
4172
4173         val = DP_TP_CTL_ENABLE |
4174               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
4175         if (intel_dp->link_mst)
4176                 val |= DP_TP_CTL_MODE_MST;
4177         else {
4178                 val |= DP_TP_CTL_MODE_SST;
4179                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4180                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4181         }
4182         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4183         POSTING_READ(intel_dp->regs.dp_tp_ctl);
4184
4185         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4186         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
4187         POSTING_READ(DDI_BUF_CTL(port));
4188
4189         udelay(600);
4190 }
4191
4192 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4193                                        enum transcoder cpu_transcoder)
4194 {
4195         if (cpu_transcoder == TRANSCODER_EDP)
4196                 return false;
4197
4198         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4199                 return false;
4200
4201         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
4202                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4203 }
4204
4205 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4206                                          struct intel_crtc_state *crtc_state)
4207 {
4208         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4209                 crtc_state->min_voltage_level = 1;
4210         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4211                 crtc_state->min_voltage_level = 2;
4212 }
4213
4214 void intel_ddi_get_config(struct intel_encoder *encoder,
4215                           struct intel_crtc_state *pipe_config)
4216 {
4217         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4218         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
4219         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4220         u32 temp, flags = 0;
4221
4222         /* XXX: DSI transcoder paranoia */
4223         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
4224                 return;
4225
4226         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
4227         if (temp & TRANS_DDI_PHSYNC)
4228                 flags |= DRM_MODE_FLAG_PHSYNC;
4229         else
4230                 flags |= DRM_MODE_FLAG_NHSYNC;
4231         if (temp & TRANS_DDI_PVSYNC)
4232                 flags |= DRM_MODE_FLAG_PVSYNC;
4233         else
4234                 flags |= DRM_MODE_FLAG_NVSYNC;
4235
4236         pipe_config->base.adjusted_mode.flags |= flags;
4237
4238         switch (temp & TRANS_DDI_BPC_MASK) {
4239         case TRANS_DDI_BPC_6:
4240                 pipe_config->pipe_bpp = 18;
4241                 break;
4242         case TRANS_DDI_BPC_8:
4243                 pipe_config->pipe_bpp = 24;
4244                 break;
4245         case TRANS_DDI_BPC_10:
4246                 pipe_config->pipe_bpp = 30;
4247                 break;
4248         case TRANS_DDI_BPC_12:
4249                 pipe_config->pipe_bpp = 36;
4250                 break;
4251         default:
4252                 break;
4253         }
4254
4255         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4256         case TRANS_DDI_MODE_SELECT_HDMI:
4257                 pipe_config->has_hdmi_sink = true;
4258
4259                 pipe_config->infoframes.enable |=
4260                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4261
4262                 if (pipe_config->infoframes.enable)
4263                         pipe_config->has_infoframe = true;
4264
4265                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4266                         pipe_config->hdmi_scrambling = true;
4267                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4268                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4269                 /* fall through */
4270         case TRANS_DDI_MODE_SELECT_DVI:
4271                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4272                 pipe_config->lane_count = 4;
4273                 break;
4274         case TRANS_DDI_MODE_SELECT_FDI:
4275                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4276                 break;
4277         case TRANS_DDI_MODE_SELECT_DP_SST:
4278                 if (encoder->type == INTEL_OUTPUT_EDP)
4279                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4280                 else
4281                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4282                 pipe_config->lane_count =
4283                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4284                 intel_dp_get_m_n(intel_crtc, pipe_config);
4285
4286                 if (INTEL_GEN(dev_priv) >= 11) {
4287                         i915_reg_t dp_tp_ctl;
4288
4289                         if (IS_GEN(dev_priv, 11))
4290                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4291                         else
4292                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4293
4294                         pipe_config->fec_enable =
4295                                 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4296
4297                         DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
4298                                       encoder->base.base.id, encoder->base.name,
4299                                       pipe_config->fec_enable);
4300                 }
4301
4302                 break;
4303         case TRANS_DDI_MODE_SELECT_DP_MST:
4304                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4305                 pipe_config->lane_count =
4306                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4307                 intel_dp_get_m_n(intel_crtc, pipe_config);
4308                 break;
4309         default:
4310                 break;
4311         }
4312
4313         if (encoder->type == INTEL_OUTPUT_EDP)
4314                 tgl_dc3co_exitline_get_config(pipe_config);
4315
4316         pipe_config->has_audio =
4317                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4318
4319         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4320             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4321                 /*
4322                  * This is a big fat ugly hack.
4323                  *
4324                  * Some machines in UEFI boot mode provide us a VBT that has 18
4325                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4326                  * unknown we fail to light up. Yet the same BIOS boots up with
4327                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4328                  * max, not what it tells us to use.
4329                  *
4330                  * Note: This will still be broken if the eDP panel is not lit
4331                  * up by the BIOS, and thus we can't get the mode at module
4332                  * load.
4333                  */
4334                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4335                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4336                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4337         }
4338
4339         intel_ddi_clock_get(encoder, pipe_config);
4340
4341         if (IS_GEN9_LP(dev_priv))
4342                 pipe_config->lane_lat_optim_mask =
4343                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4344
4345         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4346
4347         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4348
4349         intel_read_infoframe(encoder, pipe_config,
4350                              HDMI_INFOFRAME_TYPE_AVI,
4351                              &pipe_config->infoframes.avi);
4352         intel_read_infoframe(encoder, pipe_config,
4353                              HDMI_INFOFRAME_TYPE_SPD,
4354                              &pipe_config->infoframes.spd);
4355         intel_read_infoframe(encoder, pipe_config,
4356                              HDMI_INFOFRAME_TYPE_VENDOR,
4357                              &pipe_config->infoframes.hdmi);
4358         intel_read_infoframe(encoder, pipe_config,
4359                              HDMI_INFOFRAME_TYPE_DRM,
4360                              &pipe_config->infoframes.drm);
4361 }
4362
4363 static enum intel_output_type
4364 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4365                               struct intel_crtc_state *crtc_state,
4366                               struct drm_connector_state *conn_state)
4367 {
4368         switch (conn_state->connector->connector_type) {
4369         case DRM_MODE_CONNECTOR_HDMIA:
4370                 return INTEL_OUTPUT_HDMI;
4371         case DRM_MODE_CONNECTOR_eDP:
4372                 return INTEL_OUTPUT_EDP;
4373         case DRM_MODE_CONNECTOR_DisplayPort:
4374                 return INTEL_OUTPUT_DP;
4375         default:
4376                 MISSING_CASE(conn_state->connector->connector_type);
4377                 return INTEL_OUTPUT_UNUSED;
4378         }
4379 }
4380
4381 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4382                                     struct intel_crtc_state *pipe_config,
4383                                     struct drm_connector_state *conn_state)
4384 {
4385         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
4386         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4387         enum port port = encoder->port;
4388         int ret;
4389
4390         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
4391                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4392
4393         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4394                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4395         } else {
4396                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4397                 tgl_dc3co_exitline_compute_config(encoder, pipe_config);
4398         }
4399
4400         if (ret)
4401                 return ret;
4402
4403         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4404             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4405                 pipe_config->pch_pfit.force_thru =
4406                         pipe_config->pch_pfit.enabled ||
4407                         pipe_config->crc_enabled;
4408
4409         if (IS_GEN9_LP(dev_priv))
4410                 pipe_config->lane_lat_optim_mask =
4411                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4412
4413         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4414
4415         return 0;
4416 }
4417
4418 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4419 {
4420         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4421
4422         intel_dp_encoder_flush_work(encoder);
4423
4424         drm_encoder_cleanup(encoder);
4425         kfree(dig_port);
4426 }
4427
4428 static const struct drm_encoder_funcs intel_ddi_funcs = {
4429         .reset = intel_dp_encoder_reset,
4430         .destroy = intel_ddi_encoder_destroy,
4431 };
4432
4433 static struct intel_connector *
4434 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4435 {
4436         struct intel_connector *connector;
4437         enum port port = intel_dig_port->base.port;
4438
4439         connector = intel_connector_alloc();
4440         if (!connector)
4441                 return NULL;
4442
4443         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4444         intel_dig_port->dp.prepare_link_retrain =
4445                 intel_ddi_prepare_link_retrain;
4446
4447         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4448                 kfree(connector);
4449                 return NULL;
4450         }
4451
4452         return connector;
4453 }
4454
4455 static int modeset_pipe(struct drm_crtc *crtc,
4456                         struct drm_modeset_acquire_ctx *ctx)
4457 {
4458         struct drm_atomic_state *state;
4459         struct drm_crtc_state *crtc_state;
4460         int ret;
4461
4462         state = drm_atomic_state_alloc(crtc->dev);
4463         if (!state)
4464                 return -ENOMEM;
4465
4466         state->acquire_ctx = ctx;
4467
4468         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4469         if (IS_ERR(crtc_state)) {
4470                 ret = PTR_ERR(crtc_state);
4471                 goto out;
4472         }
4473
4474         crtc_state->connectors_changed = true;
4475
4476         ret = drm_atomic_commit(state);
4477 out:
4478         drm_atomic_state_put(state);
4479
4480         return ret;
4481 }
4482
4483 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4484                                  struct drm_modeset_acquire_ctx *ctx)
4485 {
4486         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4487         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4488         struct intel_connector *connector = hdmi->attached_connector;
4489         struct i2c_adapter *adapter =
4490                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4491         struct drm_connector_state *conn_state;
4492         struct intel_crtc_state *crtc_state;
4493         struct intel_crtc *crtc;
4494         u8 config;
4495         int ret;
4496
4497         if (!connector || connector->base.status != connector_status_connected)
4498                 return 0;
4499
4500         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4501                                ctx);
4502         if (ret)
4503                 return ret;
4504
4505         conn_state = connector->base.state;
4506
4507         crtc = to_intel_crtc(conn_state->crtc);
4508         if (!crtc)
4509                 return 0;
4510
4511         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4512         if (ret)
4513                 return ret;
4514
4515         crtc_state = to_intel_crtc_state(crtc->base.state);
4516
4517         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4518
4519         if (!crtc_state->base.active)
4520                 return 0;
4521
4522         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4523             !crtc_state->hdmi_scrambling)
4524                 return 0;
4525
4526         if (conn_state->commit &&
4527             !try_wait_for_completion(&conn_state->commit->hw_done))
4528                 return 0;
4529
4530         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4531         if (ret < 0) {
4532                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4533                 return 0;
4534         }
4535
4536         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4537             crtc_state->hdmi_high_tmds_clock_ratio &&
4538             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4539             crtc_state->hdmi_scrambling)
4540                 return 0;
4541
4542         /*
4543          * HDMI 2.0 says that one should not send scrambled data
4544          * prior to configuring the sink scrambling, and that
4545          * TMDS clock/data transmission should be suspended when
4546          * changing the TMDS clock rate in the sink. So let's
4547          * just do a full modeset here, even though some sinks
4548          * would be perfectly happy if were to just reconfigure
4549          * the SCDC settings on the fly.
4550          */
4551         return modeset_pipe(&crtc->base, ctx);
4552 }
4553
4554 static enum intel_hotplug_state
4555 intel_ddi_hotplug(struct intel_encoder *encoder,
4556                   struct intel_connector *connector,
4557                   bool irq_received)
4558 {
4559         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4560         struct drm_modeset_acquire_ctx ctx;
4561         enum intel_hotplug_state state;
4562         int ret;
4563
4564         state = intel_encoder_hotplug(encoder, connector, irq_received);
4565
4566         drm_modeset_acquire_init(&ctx, 0);
4567
4568         for (;;) {
4569                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4570                         ret = intel_hdmi_reset_link(encoder, &ctx);
4571                 else
4572                         ret = intel_dp_retrain_link(encoder, &ctx);
4573
4574                 if (ret == -EDEADLK) {
4575                         drm_modeset_backoff(&ctx);
4576                         continue;
4577                 }
4578
4579                 break;
4580         }
4581
4582         drm_modeset_drop_locks(&ctx);
4583         drm_modeset_acquire_fini(&ctx);
4584         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4585
4586         /*
4587          * Unpowered type-c dongles can take some time to boot and be
4588          * responsible, so here giving some time to those dongles to power up
4589          * and then retrying the probe.
4590          *
4591          * On many platforms the HDMI live state signal is known to be
4592          * unreliable, so we can't use it to detect if a sink is connected or
4593          * not. Instead we detect if it's connected based on whether we can
4594          * read the EDID or not. That in turn has a problem during disconnect,
4595          * since the HPD interrupt may be raised before the DDC lines get
4596          * disconnected (due to how the required length of DDC vs. HPD
4597          * connector pins are specified) and so we'll still be able to get a
4598          * valid EDID. To solve this schedule another detection cycle if this
4599          * time around we didn't detect any change in the sink's connection
4600          * status.
4601          */
4602         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4603             !dig_port->dp.is_mst)
4604                 state = INTEL_HOTPLUG_RETRY;
4605
4606         return state;
4607 }
4608
4609 static struct intel_connector *
4610 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4611 {
4612         struct intel_connector *connector;
4613         enum port port = intel_dig_port->base.port;
4614
4615         connector = intel_connector_alloc();
4616         if (!connector)
4617                 return NULL;
4618
4619         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4620         intel_hdmi_init_connector(intel_dig_port, connector);
4621
4622         return connector;
4623 }
4624
4625 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4626 {
4627         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4628
4629         if (dport->base.port != PORT_A)
4630                 return false;
4631
4632         if (dport->saved_port_bits & DDI_A_4_LANES)
4633                 return false;
4634
4635         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4636          *                     supported configuration
4637          */
4638         if (IS_GEN9_LP(dev_priv))
4639                 return true;
4640
4641         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4642          *             one who does also have a full A/E split called
4643          *             DDI_F what makes DDI_E useless. However for this
4644          *             case let's trust VBT info.
4645          */
4646         if (IS_CANNONLAKE(dev_priv) &&
4647             !intel_bios_is_port_present(dev_priv, PORT_E))
4648                 return true;
4649
4650         return false;
4651 }
4652
4653 static int
4654 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4655 {
4656         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4657         enum port port = intel_dport->base.port;
4658         int max_lanes = 4;
4659
4660         if (INTEL_GEN(dev_priv) >= 11)
4661                 return max_lanes;
4662
4663         if (port == PORT_A || port == PORT_E) {
4664                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4665                         max_lanes = port == PORT_A ? 4 : 0;
4666                 else
4667                         /* Both A and E share 2 lanes */
4668                         max_lanes = 2;
4669         }
4670
4671         /*
4672          * Some BIOS might fail to set this bit on port A if eDP
4673          * wasn't lit up at boot.  Force this bit set when needed
4674          * so we use the proper lane count for our calculations.
4675          */
4676         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4677                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4678                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4679                 max_lanes = 4;
4680         }
4681
4682         return max_lanes;
4683 }
4684
4685 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4686 {
4687         struct ddi_vbt_port_info *port_info =
4688                 &dev_priv->vbt.ddi_port_info[port];
4689         struct intel_digital_port *intel_dig_port;
4690         struct intel_encoder *intel_encoder;
4691         struct drm_encoder *encoder;
4692         bool init_hdmi, init_dp, init_lspcon = false;
4693         enum phy phy = intel_port_to_phy(dev_priv, port);
4694
4695         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4696         init_dp = port_info->supports_dp;
4697
4698         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4699                 /*
4700                  * Lspcon device needs to be driven with DP connector
4701                  * with special detection sequence. So make sure DP
4702                  * is initialized before lspcon.
4703                  */
4704                 init_dp = true;
4705                 init_lspcon = true;
4706                 init_hdmi = false;
4707                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4708         }
4709
4710         if (!init_dp && !init_hdmi) {
4711                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4712                               port_name(port));
4713                 return;
4714         }
4715
4716         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4717         if (!intel_dig_port)
4718                 return;
4719
4720         intel_encoder = &intel_dig_port->base;
4721         encoder = &intel_encoder->base;
4722
4723         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4724                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4725
4726         intel_encoder->hotplug = intel_ddi_hotplug;
4727         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4728         intel_encoder->compute_config = intel_ddi_compute_config;
4729         intel_encoder->enable = intel_enable_ddi;
4730         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4731         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4732         intel_encoder->pre_enable = intel_ddi_pre_enable;
4733         intel_encoder->disable = intel_disable_ddi;
4734         intel_encoder->post_disable = intel_ddi_post_disable;
4735         intel_encoder->update_pipe = intel_ddi_update_pipe;
4736         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4737         intel_encoder->get_config = intel_ddi_get_config;
4738         intel_encoder->suspend = intel_dp_encoder_suspend;
4739         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4740         intel_encoder->type = INTEL_OUTPUT_DDI;
4741         intel_encoder->power_domain = intel_port_to_power_domain(port);
4742         intel_encoder->port = port;
4743         intel_encoder->cloneable = 0;
4744         intel_encoder->pipe_mask = ~0;
4745
4746         if (INTEL_GEN(dev_priv) >= 11)
4747                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4748                         DDI_BUF_PORT_REVERSAL;
4749         else
4750                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4751                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4752         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4753         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4754         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4755
4756         if (intel_phy_is_tc(dev_priv, phy)) {
4757                 bool is_legacy = !port_info->supports_typec_usb &&
4758                                  !port_info->supports_tbt;
4759
4760                 intel_tc_port_init(intel_dig_port, is_legacy);
4761
4762                 intel_encoder->update_prepare = intel_ddi_update_prepare;
4763                 intel_encoder->update_complete = intel_ddi_update_complete;
4764         }
4765
4766         WARN_ON(port > PORT_I);
4767         intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4768                                               port - PORT_A;
4769
4770         if (init_dp) {
4771                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4772                         goto err;
4773
4774                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4775         }
4776
4777         /* In theory we don't need the encoder->type check, but leave it just in
4778          * case we have some really bad VBTs... */
4779         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4780                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4781                         goto err;
4782         }
4783
4784         if (init_lspcon) {
4785                 if (lspcon_init(intel_dig_port))
4786                         /* TODO: handle hdmi info frame part */
4787                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4788                                 port_name(port));
4789                 else
4790                         /*
4791                          * LSPCON init faied, but DP init was success, so
4792                          * lets try to drive as DP++ port.
4793                          */
4794                         DRM_ERROR("LSPCON init failed on port %c\n",
4795                                 port_name(port));
4796         }
4797
4798         intel_infoframe_init(intel_dig_port);
4799
4800         return;
4801
4802 err:
4803         drm_encoder_cleanup(encoder);
4804         kfree(intel_dig_port);
4805 }