drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/string_helpers.h>
  29
  30 #include <drm/display/drm_scdc_helper.h>
  31 #include <drm/drm_privacy_screen_consumer.h>
  32
  33 #include "i915_drv.h"
  34 #include "i915_reg.h"
  35 #include "intel_audio.h"
  36 #include "intel_audio_regs.h"
  37 #include "intel_backlight.h"
  38 #include "intel_combo_phy.h"
  39 #include "intel_combo_phy_regs.h"
  40 #include "intel_connector.h"
  41 #include "intel_crtc.h"
  42 #include "intel_cx0_phy.h"
  43 #include "intel_cx0_phy_regs.h"
  44 #include "intel_ddi.h"
  45 #include "intel_ddi_buf_trans.h"
  46 #include "intel_de.h"
  47 #include "intel_display_power.h"
  48 #include "intel_display_types.h"
  49 #include "intel_dkl_phy.h"
  50 #include "intel_dkl_phy_regs.h"
  51 #include "intel_dp.h"
  52 #include "intel_dp_aux.h"
  53 #include "intel_dp_link_training.h"
  54 #include "intel_dp_mst.h"
  55 #include "intel_dpio_phy.h"
  56 #include "intel_dsi.h"
  57 #include "intel_fdi.h"
  58 #include "intel_fifo_underrun.h"
  59 #include "intel_gmbus.h"
  60 #include "intel_hdcp.h"
  61 #include "intel_hdmi.h"
  62 #include "intel_hotplug.h"
  63 #include "intel_hti.h"
  64 #include "intel_lspcon.h"
  65 #include "intel_mg_phy_regs.h"
  66 #include "intel_modeset_lock.h"
  67 #include "intel_pps.h"
  68 #include "intel_psr.h"
  69 #include "intel_quirks.h"
  70 #include "intel_snps_phy.h"
  71 #include "intel_tc.h"
  72 #include "intel_vdsc.h"
  73 #include "intel_vdsc_regs.h"
  74 #include "skl_scaler.h"
  75 #include "skl_universal_plane.h"
  76
  77 static const u8 index_to_dp_signal_levels[] = {
  78         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  79         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  80         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  81         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  82         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  83         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  84         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  85         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  86         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  87         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  88 };
  89
  90 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  91                                 const struct intel_ddi_buf_trans *trans)
  92 {
  93         int level;
  94
  95         level = intel_bios_hdmi_level_shift(encoder->devdata);
  96         if (level < 0)
  97                 level = trans->hdmi_default_entry;
  98
  99         return level;
 100 }
 101
 102 static bool has_buf_trans_select(struct drm_i915_private *i915)
 103 {
 104         return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
 105 }
 106
 107 static bool has_iboost(struct drm_i915_private *i915)
 108 {
 109         return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
 110 }
 111
 112 /*
 113  * Starting with Haswell, DDI port buffers must be programmed with correct
 114  * values in advance. This function programs the correct values for
 115  * DP/eDP/FDI use cases.
 116  */
 117 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 118                                 const struct intel_crtc_state *crtc_state)
 119 {
 120         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 121         u32 iboost_bit = 0;
 122         int i, n_entries;
 123         enum port port = encoder->port;
 124         const struct intel_ddi_buf_trans *trans;
 125
 126         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 127         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 128                 return;
 129
 130         /* If we're boosting the current, set bit 31 of trans1 */
 131         if (has_iboost(dev_priv) &&
 132             intel_bios_dp_boost_level(encoder->devdata))
 133                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 134
 135         for (i = 0; i < n_entries; i++) {
 136                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 137                                trans->entries[i].hsw.trans1 | iboost_bit);
 138                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 139                                trans->entries[i].hsw.trans2);
 140         }
 141 }
 142
 143 /*
 144  * Starting with Haswell, DDI port buffers must be programmed with correct
 145  * values in advance. This function programs the correct values for
 146  * HDMI/DVI use cases.
 147  */
 148 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 149                                          const struct intel_crtc_state *crtc_state)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 152         int level = intel_ddi_level(encoder, crtc_state, 0);
 153         u32 iboost_bit = 0;
 154         int n_entries;
 155         enum port port = encoder->port;
 156         const struct intel_ddi_buf_trans *trans;
 157
 158         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 159         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 160                 return;
 161
 162         /* If we're boosting the current, set bit 31 of trans1 */
 163         if (has_iboost(dev_priv) &&
 164             intel_bios_hdmi_boost_level(encoder->devdata))
 165                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 166
 167         /* Entry 9 is for HDMI: */
 168         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 169                        trans->entries[level].hsw.trans1 | iboost_bit);
 170         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 171                        trans->entries[level].hsw.trans2);
 172 }
 173
 174 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
 175 {
 176         int ret;
 177
 178         /* FIXME: find out why Bspec's 100us timeout is too short */
 179         ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
 180                            XELPDP_PORT_BUF_PHY_IDLE), 10000);
 181         if (ret)
 182                 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 183                         port_name(port));
 184 }
 185
 186 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 187                              enum port port)
 188 {
 189         if (IS_BROXTON(dev_priv)) {
 190                 udelay(16);
 191                 return;
 192         }
 193
 194         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 195                          DDI_BUF_IS_IDLE), 8))
 196                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 197                         port_name(port));
 198 }
 199
 200 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 201                                       enum port port)
 202 {
 203         enum phy phy = intel_port_to_phy(dev_priv, port);
 204         int timeout_us;
 205         int ret;
 206
 207         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 208         if (DISPLAY_VER(dev_priv) < 10) {
 209                 usleep_range(518, 1000);
 210                 return;
 211         }
 212
 213         if (DISPLAY_VER(dev_priv) >= 14) {
 214                 timeout_us = 10000;
 215         } else if (IS_DG2(dev_priv)) {
 216                 timeout_us = 1200;
 217         } else if (DISPLAY_VER(dev_priv) >= 12) {
 218                 if (intel_phy_is_tc(dev_priv, phy))
 219                         timeout_us = 3000;
 220                 else
 221                         timeout_us = 1000;
 222         } else {
 223                 timeout_us = 500;
 224         }
 225
 226         if (DISPLAY_VER(dev_priv) >= 14)
 227                 ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
 228                                 timeout_us, 10, 10);
 229         else
 230                 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
 231                                 timeout_us, 10, 10);
 232
 233         if (ret)
 234                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 235                         port_name(port));
 236 }
 237
 238 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 239 {
 240         switch (pll->info->id) {
 241         case DPLL_ID_WRPLL1:
 242                 return PORT_CLK_SEL_WRPLL1;
 243         case DPLL_ID_WRPLL2:
 244                 return PORT_CLK_SEL_WRPLL2;
 245         case DPLL_ID_SPLL:
 246                 return PORT_CLK_SEL_SPLL;
 247         case DPLL_ID_LCPLL_810:
 248                 return PORT_CLK_SEL_LCPLL_810;
 249         case DPLL_ID_LCPLL_1350:
 250                 return PORT_CLK_SEL_LCPLL_1350;
 251         case DPLL_ID_LCPLL_2700:
 252                 return PORT_CLK_SEL_LCPLL_2700;
 253         default:
 254                 MISSING_CASE(pll->info->id);
 255                 return PORT_CLK_SEL_NONE;
 256         }
 257 }
 258
 259 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 260                                   const struct intel_crtc_state *crtc_state)
 261 {
 262         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 263         int clock = crtc_state->port_clock;
 264         const enum intel_dpll_id id = pll->info->id;
 265
 266         switch (id) {
 267         default:
 268                 /*
 269                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 270                  * here, so do warn if this get passed in
 271                  */
 272                 MISSING_CASE(id);
 273                 return DDI_CLK_SEL_NONE;
 274         case DPLL_ID_ICL_TBTPLL:
 275                 switch (clock) {
 276                 case 162000:
 277                         return DDI_CLK_SEL_TBT_162;
 278                 case 270000:
 279                         return DDI_CLK_SEL_TBT_270;
 280                 case 540000:
 281                         return DDI_CLK_SEL_TBT_540;
 282                 case 810000:
 283                         return DDI_CLK_SEL_TBT_810;
 284                 default:
 285                         MISSING_CASE(clock);
 286                         return DDI_CLK_SEL_NONE;
 287                 }
 288         case DPLL_ID_ICL_MGPLL1:
 289         case DPLL_ID_ICL_MGPLL2:
 290         case DPLL_ID_ICL_MGPLL3:
 291         case DPLL_ID_ICL_MGPLL4:
 292         case DPLL_ID_TGL_MGPLL5:
 293         case DPLL_ID_TGL_MGPLL6:
 294                 return DDI_CLK_SEL_MG;
 295         }
 296 }
 297
 298 static u32 ddi_buf_phy_link_rate(int port_clock)
 299 {
 300         switch (port_clock) {
 301         case 162000:
 302                 return DDI_BUF_PHY_LINK_RATE(0);
 303         case 216000:
 304                 return DDI_BUF_PHY_LINK_RATE(4);
 305         case 243000:
 306                 return DDI_BUF_PHY_LINK_RATE(5);
 307         case 270000:
 308                 return DDI_BUF_PHY_LINK_RATE(1);
 309         case 324000:
 310                 return DDI_BUF_PHY_LINK_RATE(6);
 311         case 432000:
 312                 return DDI_BUF_PHY_LINK_RATE(7);
 313         case 540000:
 314                 return DDI_BUF_PHY_LINK_RATE(2);
 315         case 810000:
 316                 return DDI_BUF_PHY_LINK_RATE(3);
 317         default:
 318                 MISSING_CASE(port_clock);
 319                 return DDI_BUF_PHY_LINK_RATE(0);
 320         }
 321 }
 322
 323 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 324                                       const struct intel_crtc_state *crtc_state)
 325 {
 326         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 327         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 328         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 329         enum phy phy = intel_port_to_phy(i915, encoder->port);
 330
 331         /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
 332         intel_dp->DP = dig_port->saved_port_bits |
 333                 DDI_PORT_WIDTH(crtc_state->lane_count) |
 334                 DDI_BUF_TRANS_SELECT(0);
 335
 336         if (DISPLAY_VER(i915) >= 14) {
 337                 if (intel_dp_is_uhbr(crtc_state))
 338                         intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
 339                 else
 340                         intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
 341         }
 342
 343         if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 344                 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 345                 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
 346                         intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 347         }
 348 }
 349
 350 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 351                                  enum port port)
 352 {
 353         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 354
 355         switch (val) {
 356         case DDI_CLK_SEL_NONE:
 357                 return 0;
 358         case DDI_CLK_SEL_TBT_162:
 359                 return 162000;
 360         case DDI_CLK_SEL_TBT_270:
 361                 return 270000;
 362         case DDI_CLK_SEL_TBT_540:
 363                 return 540000;
 364         case DDI_CLK_SEL_TBT_810:
 365                 return 810000;
 366         default:
 367                 MISSING_CASE(val);
 368                 return 0;
 369         }
 370 }
 371
 372 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 373 {
 374         /* CRT dotclock is determined via other means */
 375         if (pipe_config->has_pch_encoder)
 376                 return;
 377
 378         pipe_config->hw.adjusted_mode.crtc_clock =
 379                 intel_crtc_dotclock(pipe_config);
 380 }
 381
 382 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 383                           const struct drm_connector_state *conn_state)
 384 {
 385         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 386         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 387         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 388         u32 temp;
 389
 390         if (!intel_crtc_has_dp_encoder(crtc_state))
 391                 return;
 392
 393         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 394
 395         temp = DP_MSA_MISC_SYNC_CLOCK;
 396
 397         switch (crtc_state->pipe_bpp) {
 398         case 18:
 399                 temp |= DP_MSA_MISC_6_BPC;
 400                 break;
 401         case 24:
 402                 temp |= DP_MSA_MISC_8_BPC;
 403                 break;
 404         case 30:
 405                 temp |= DP_MSA_MISC_10_BPC;
 406                 break;
 407         case 36:
 408                 temp |= DP_MSA_MISC_12_BPC;
 409                 break;
 410         default:
 411                 MISSING_CASE(crtc_state->pipe_bpp);
 412                 break;
 413         }
 414
 415         /* nonsense combination */
 416         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 417                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 418
 419         if (crtc_state->limited_color_range)
 420                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 421
 422         /*
 423          * As per DP 1.2 spec section 2.3.4.3 while sending
 424          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 425          * colorspace information.
 426          */
 427         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 428                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 429
 430         /*
 431          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 432          * of Color Encoding Format and Content Color Gamut] while sending
 433          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 434          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 435          */
 436         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 437                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 438
 439         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 440 }
 441
 442 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 443 {
 444         if (master_transcoder == TRANSCODER_EDP)
 445                 return 0;
 446         else
 447                 return master_transcoder + 1;
 448 }
 449
 450 static void
 451 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
 452                                 const struct intel_crtc_state *crtc_state)
 453 {
 454         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 455         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 456         u32 val = 0;
 457
 458         if (intel_dp_is_uhbr(crtc_state))
 459                 val = TRANS_DP2_128B132B_CHANNEL_CODING;
 460
 461         intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
 462 }
 463
 464 /*
 465  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 466  *
 467  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 468  * intel_ddi_config_transcoder_func().
 469  */
 470 static u32
 471 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 472                                       const struct intel_crtc_state *crtc_state)
 473 {
 474         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 475         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 476         enum pipe pipe = crtc->pipe;
 477         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 478         enum port port = encoder->port;
 479         u32 temp;
 480
 481         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 482         temp = TRANS_DDI_FUNC_ENABLE;
 483         if (DISPLAY_VER(dev_priv) >= 12)
 484                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 485         else
 486                 temp |= TRANS_DDI_SELECT_PORT(port);
 487
 488         switch (crtc_state->pipe_bpp) {
 489         default:
 490                 MISSING_CASE(crtc_state->pipe_bpp);
 491                 fallthrough;
 492         case 18:
 493                 temp |= TRANS_DDI_BPC_6;
 494                 break;
 495         case 24:
 496                 temp |= TRANS_DDI_BPC_8;
 497                 break;
 498         case 30:
 499                 temp |= TRANS_DDI_BPC_10;
 500                 break;
 501         case 36:
 502                 temp |= TRANS_DDI_BPC_12;
 503                 break;
 504         }
 505
 506         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 507                 temp |= TRANS_DDI_PVSYNC;
 508         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 509                 temp |= TRANS_DDI_PHSYNC;
 510
 511         if (cpu_transcoder == TRANSCODER_EDP) {
 512                 switch (pipe) {
 513                 default:
 514                         MISSING_CASE(pipe);
 515                         fallthrough;
 516                 case PIPE_A:
 517                         /* On Haswell, can only use the always-on power well for
 518                          * eDP when not using the panel fitter, and when not
 519                          * using motion blur mitigation (which we don't
 520                          * support). */
 521                         if (crtc_state->pch_pfit.force_thru)
 522                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 523                         else
 524                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 525                         break;
 526                 case PIPE_B:
 527                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 528                         break;
 529                 case PIPE_C:
 530                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 531                         break;
 532                 }
 533         }
 534
 535         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 536                 if (crtc_state->has_hdmi_sink)
 537                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 538                 else
 539                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 540
 541                 if (crtc_state->hdmi_scrambling)
 542                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 543                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 544                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 545                 if (DISPLAY_VER(dev_priv) >= 14)
 546                         temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
 547         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 548                 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 549                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 550         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 551                 if (intel_dp_is_uhbr(crtc_state))
 552                         temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 553                 else
 554                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 555                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 556
 557                 if (DISPLAY_VER(dev_priv) >= 12) {
 558                         enum transcoder master;
 559
 560                         master = crtc_state->mst_master_transcoder;
 561                         drm_WARN_ON(&dev_priv->drm,
 562                                     master == INVALID_TRANSCODER);
 563                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 564                 }
 565         } else {
 566                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 567                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 568         }
 569
 570         if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 571             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 572                 u8 master_select =
 573                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 574
 575                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 576                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 577         }
 578
 579         return temp;
 580 }
 581
 582 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 583                                       const struct intel_crtc_state *crtc_state)
 584 {
 585         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 587         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 588
 589         if (DISPLAY_VER(dev_priv) >= 11) {
 590                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 591                 u32 ctl2 = 0;
 592
 593                 if (master_transcoder != INVALID_TRANSCODER) {
 594                         u8 master_select =
 595                                 bdw_trans_port_sync_master_select(master_transcoder);
 596
 597                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 598                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 599                 }
 600
 601                 intel_de_write(dev_priv,
 602                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 603         }
 604
 605         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 606                        intel_ddi_transcoder_func_reg_val_get(encoder,
 607                                                              crtc_state));
 608 }
 609
 610 /*
 611  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 612  * bit.
 613  */
 614 static void
 615 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 616                                  const struct intel_crtc_state *crtc_state)
 617 {
 618         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 619         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 620         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 621         u32 ctl;
 622
 623         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 624         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 625         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 626 }
 627
 628 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 629 {
 630         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 632         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 633         u32 ctl;
 634
 635         if (DISPLAY_VER(dev_priv) >= 11)
 636                 intel_de_write(dev_priv,
 637                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 638
 639         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 640
 641         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 642
 643         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 644
 645         if (IS_DISPLAY_VER(dev_priv, 8, 10))
 646                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 647                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 648
 649         if (DISPLAY_VER(dev_priv) >= 12) {
 650                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 651                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 652                                  TRANS_DDI_MODE_SELECT_MASK);
 653                 }
 654         } else {
 655                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 656         }
 657
 658         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 659
 660         if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
 661             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 662                 drm_dbg_kms(&dev_priv->drm,
 663                             "Quirk Increase DDI disabled time\n");
 664                 /* Quirk time at 100ms for reliable operation */
 665                 msleep(100);
 666         }
 667 }
 668
 669 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 670                                enum transcoder cpu_transcoder,
 671                                bool enable, u32 hdcp_mask)
 672 {
 673         struct drm_device *dev = intel_encoder->base.dev;
 674         struct drm_i915_private *dev_priv = to_i915(dev);
 675         intel_wakeref_t wakeref;
 676         int ret = 0;
 677
 678         wakeref = intel_display_power_get_if_enabled(dev_priv,
 679                                                      intel_encoder->power_domain);
 680         if (drm_WARN_ON(dev, !wakeref))
 681                 return -ENXIO;
 682
 683         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 684                      hdcp_mask, enable ? hdcp_mask : 0);
 685         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 686         return ret;
 687 }
 688
 689 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 690 {
 691         struct drm_device *dev = intel_connector->base.dev;
 692         struct drm_i915_private *dev_priv = to_i915(dev);
 693         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 694         int type = intel_connector->base.connector_type;
 695         enum port port = encoder->port;
 696         enum transcoder cpu_transcoder;
 697         intel_wakeref_t wakeref;
 698         enum pipe pipe = 0;
 699         u32 tmp;
 700         bool ret;
 701
 702         wakeref = intel_display_power_get_if_enabled(dev_priv,
 703                                                      encoder->power_domain);
 704         if (!wakeref)
 705                 return false;
 706
 707         if (!encoder->get_hw_state(encoder, &pipe)) {
 708                 ret = false;
 709                 goto out;
 710         }
 711
 712         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 713                 cpu_transcoder = TRANSCODER_EDP;
 714         else
 715                 cpu_transcoder = (enum transcoder) pipe;
 716
 717         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 718
 719         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 720         case TRANS_DDI_MODE_SELECT_HDMI:
 721         case TRANS_DDI_MODE_SELECT_DVI:
 722                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 723                 break;
 724
 725         case TRANS_DDI_MODE_SELECT_DP_SST:
 726                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 727                       type == DRM_MODE_CONNECTOR_DisplayPort;
 728                 break;
 729
 730         case TRANS_DDI_MODE_SELECT_DP_MST:
 731                 /* if the transcoder is in MST state then
 732                  * connector isn't connected */
 733                 ret = false;
 734                 break;
 735
 736         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
 737                 if (HAS_DP20(dev_priv))
 738                         /* 128b/132b */
 739                         ret = false;
 740                 else
 741                         /* FDI */
 742                         ret = type == DRM_MODE_CONNECTOR_VGA;
 743                 break;
 744
 745         default:
 746                 ret = false;
 747                 break;
 748         }
 749
 750 out:
 751         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 752
 753         return ret;
 754 }
 755
 756 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 757                                         u8 *pipe_mask, bool *is_dp_mst)
 758 {
 759         struct drm_device *dev = encoder->base.dev;
 760         struct drm_i915_private *dev_priv = to_i915(dev);
 761         enum port port = encoder->port;
 762         intel_wakeref_t wakeref;
 763         enum pipe p;
 764         u32 tmp;
 765         u8 mst_pipe_mask;
 766
 767         *pipe_mask = 0;
 768         *is_dp_mst = false;
 769
 770         wakeref = intel_display_power_get_if_enabled(dev_priv,
 771                                                      encoder->power_domain);
 772         if (!wakeref)
 773                 return;
 774
 775         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 776         if (!(tmp & DDI_BUF_CTL_ENABLE))
 777                 goto out;
 778
 779         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 780                 tmp = intel_de_read(dev_priv,
 781                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 782
 783                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 784                 default:
 785                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 786                         fallthrough;
 787                 case TRANS_DDI_EDP_INPUT_A_ON:
 788                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 789                         *pipe_mask = BIT(PIPE_A);
 790                         break;
 791                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 792                         *pipe_mask = BIT(PIPE_B);
 793                         break;
 794                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 795                         *pipe_mask = BIT(PIPE_C);
 796                         break;
 797                 }
 798
 799                 goto out;
 800         }
 801
 802         mst_pipe_mask = 0;
 803         for_each_pipe(dev_priv, p) {
 804                 enum transcoder cpu_transcoder = (enum transcoder)p;
 805                 unsigned int port_mask, ddi_select;
 806                 intel_wakeref_t trans_wakeref;
 807
 808                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 809                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 810                 if (!trans_wakeref)
 811                         continue;
 812
 813                 if (DISPLAY_VER(dev_priv) >= 12) {
 814                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 815                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 816                 } else {
 817                         port_mask = TRANS_DDI_PORT_MASK;
 818                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 819                 }
 820
 821                 tmp = intel_de_read(dev_priv,
 822                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 823                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 824                                         trans_wakeref);
 825
 826                 if ((tmp & port_mask) != ddi_select)
 827                         continue;
 828
 829                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
 830                     (HAS_DP20(dev_priv) &&
 831                      (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
 832                         mst_pipe_mask |= BIT(p);
 833
 834                 *pipe_mask |= BIT(p);
 835         }
 836
 837         if (!*pipe_mask)
 838                 drm_dbg_kms(&dev_priv->drm,
 839                             "No pipe for [ENCODER:%d:%s] found\n",
 840                             encoder->base.base.id, encoder->base.name);
 841
 842         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 843                 drm_dbg_kms(&dev_priv->drm,
 844                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 845                             encoder->base.base.id, encoder->base.name,
 846                             *pipe_mask);
 847                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 848         }
 849
 850         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 851                 drm_dbg_kms(&dev_priv->drm,
 852                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 853                             encoder->base.base.id, encoder->base.name,
 854                             *pipe_mask, mst_pipe_mask);
 855         else
 856                 *is_dp_mst = mst_pipe_mask;
 857
 858 out:
 859         if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 860                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 861                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 862                             BXT_PHY_LANE_POWERDOWN_ACK |
 863                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 864                         drm_err(&dev_priv->drm,
 865                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 866                                 encoder->base.base.id, encoder->base.name, tmp);
 867         }
 868
 869         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 870 }
 871
 872 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 873                             enum pipe *pipe)
 874 {
 875         u8 pipe_mask;
 876         bool is_mst;
 877
 878         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 879
 880         if (is_mst || !pipe_mask)
 881                 return false;
 882
 883         *pipe = ffs(pipe_mask) - 1;
 884
 885         return true;
 886 }
 887
 888 static enum intel_display_power_domain
 889 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 890                                const struct intel_crtc_state *crtc_state)
 891 {
 892         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 893         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 894
 895         /*
 896          * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 897          * DC states enabled at the same time, while for driver initiated AUX
 898          * transfers we need the same AUX IOs to be powered but with DC states
 899          * disabled. Accordingly use the AUX_IO_<port> power domain here which
 900          * leaves DC states enabled.
 901          *
 902          * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
 903          * AUX IO to be enabled, but all these require DC_OFF to be enabled as
 904          * well, so we can acquire a wider AUX_<port> power domain reference
 905          * instead of a specific AUX_IO_<port> reference without powering up any
 906          * extra wells.
 907          */
 908         if (intel_encoder_can_psr(&dig_port->base))
 909                 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
 910         else if (DISPLAY_VER(i915) < 14 &&
 911                  (intel_crtc_has_dp_encoder(crtc_state) ||
 912                   intel_phy_is_tc(i915, phy)))
 913                 return intel_aux_power_domain(dig_port);
 914         else
 915                 return POWER_DOMAIN_INVALID;
 916 }
 917
 918 static void
 919 main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
 920                                const struct intel_crtc_state *crtc_state)
 921 {
 922         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 923         enum intel_display_power_domain domain =
 924                 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
 925
 926         drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
 927
 928         if (domain == POWER_DOMAIN_INVALID)
 929                 return;
 930
 931         dig_port->aux_wakeref = intel_display_power_get(i915, domain);
 932 }
 933
 934 static void
 935 main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
 936                                const struct intel_crtc_state *crtc_state)
 937 {
 938         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 939         enum intel_display_power_domain domain =
 940                 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
 941         intel_wakeref_t wf;
 942
 943         wf = fetch_and_zero(&dig_port->aux_wakeref);
 944         if (!wf)
 945                 return;
 946
 947         intel_display_power_put(i915, domain, wf);
 948 }
 949
 950 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 951                                         struct intel_crtc_state *crtc_state)
 952 {
 953         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 954         struct intel_digital_port *dig_port;
 955
 956         /*
 957          * TODO: Add support for MST encoders. Atm, the following should never
 958          * happen since fake-MST encoders don't set their get_power_domains()
 959          * hook.
 960          */
 961         if (drm_WARN_ON(&dev_priv->drm,
 962                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 963                 return;
 964
 965         dig_port = enc_to_dig_port(encoder);
 966
 967         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
 968                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 969                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 970                                                                    dig_port->ddi_io_power_domain);
 971         }
 972
 973         main_link_aux_power_domain_get(dig_port, crtc_state);
 974 }
 975
 976 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
 977                                        const struct intel_crtc_state *crtc_state)
 978 {
 979         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 980         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 981         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 982         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 983         u32 val;
 984
 985         if (cpu_transcoder == TRANSCODER_EDP)
 986                 return;
 987
 988         if (DISPLAY_VER(dev_priv) >= 13)
 989                 val = TGL_TRANS_CLK_SEL_PORT(phy);
 990         else if (DISPLAY_VER(dev_priv) >= 12)
 991                 val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 992         else
 993                 val = TRANS_CLK_SEL_PORT(encoder->port);
 994
 995         intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 996 }
 997
 998 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
 999 {
1000         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1001         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1002         u32 val;
1003
1004         if (cpu_transcoder == TRANSCODER_EDP)
1005                 return;
1006
1007         if (DISPLAY_VER(dev_priv) >= 12)
1008                 val = TGL_TRANS_CLK_SEL_DISABLED;
1009         else
1010                 val = TRANS_CLK_SEL_DISABLED;
1011
1012         intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
1013 }
1014
1015 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1016                                 enum port port, u8 iboost)
1017 {
1018         u32 tmp;
1019
1020         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
1021         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1022         if (iboost)
1023                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1024         else
1025                 tmp |= BALANCE_LEG_DISABLE(port);
1026         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
1027 }
1028
1029 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1030                                const struct intel_crtc_state *crtc_state,
1031                                int level)
1032 {
1033         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1034         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1035         u8 iboost;
1036
1037         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1038                 iboost = intel_bios_hdmi_boost_level(encoder->devdata);
1039         else
1040                 iboost = intel_bios_dp_boost_level(encoder->devdata);
1041
1042         if (iboost == 0) {
1043                 const struct intel_ddi_buf_trans *trans;
1044                 int n_entries;
1045
1046                 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1047                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1048                         return;
1049
1050                 iboost = trans->entries[level].hsw.i_boost;
1051         }
1052
1053         /* Make sure that the requested I_boost is valid */
1054         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1055                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
1056                 return;
1057         }
1058
1059         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
1060
1061         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1062                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1063 }
1064
1065 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1066                                    const struct intel_crtc_state *crtc_state)
1067 {
1068         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1069         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1070         int n_entries;
1071
1072         encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1073
1074         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1075                 n_entries = 1;
1076         if (drm_WARN_ON(&dev_priv->drm,
1077                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1078                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1079
1080         return index_to_dp_signal_levels[n_entries - 1] &
1081                 DP_TRAIN_VOLTAGE_SWING_MASK;
1082 }
1083
1084 /*
1085  * We assume that the full set of pre-emphasis values can be
1086  * used on all DDI platforms. Should that change we need to
1087  * rethink this code.
1088  */
1089 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1090 {
1091         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1092 }
1093
1094 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1095                                         int lane)
1096 {
1097         if (crtc_state->port_clock > 600000)
1098                 return 0;
1099
1100         if (crtc_state->lane_count == 4)
1101                 return lane >= 1 ? LOADGEN_SELECT : 0;
1102         else
1103                 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1104 }
1105
1106 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1107                                          const struct intel_crtc_state *crtc_state)
1108 {
1109         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1110         const struct intel_ddi_buf_trans *trans;
1111         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1112         int n_entries, ln;
1113         u32 val;
1114
1115         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1116         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1117                 return;
1118
1119         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1120                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1121
1122                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1123                 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1124                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1125                              intel_dp->hobl_active ? val : 0);
1126         }
1127
1128         /* Set PORT_TX_DW5 */
1129         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1130         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1131                   TAP2_DISABLE | TAP3_DISABLE);
1132         val |= SCALING_MODE_SEL(0x2);
1133         val |= RTERM_SELECT(0x6);
1134         val |= TAP3_DISABLE;
1135         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1136
1137         /* Program PORT_TX_DW2 */
1138         for (ln = 0; ln < 4; ln++) {
1139                 int level = intel_ddi_level(encoder, crtc_state, ln);
1140
1141                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1142                              SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1143                              SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1144                              SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1145                              RCOMP_SCALAR(0x98));
1146         }
1147
1148         /* Program PORT_TX_DW4 */
1149         /* We cannot write to GRP. It would overwrite individual loadgen. */
1150         for (ln = 0; ln < 4; ln++) {
1151                 int level = intel_ddi_level(encoder, crtc_state, ln);
1152
1153                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1154                              POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1155                              POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1156                              POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1157                              CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1158         }
1159
1160         /* Program PORT_TX_DW7 */
1161         for (ln = 0; ln < 4; ln++) {
1162                 int level = intel_ddi_level(encoder, crtc_state, ln);
1163
1164                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1165                              N_SCALAR_MASK,
1166                              N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1167         }
1168 }
1169
1170 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1171                                             const struct intel_crtc_state *crtc_state)
1172 {
1173         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1174         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1175         u32 val;
1176         int ln;
1177
1178         /*
1179          * 1. If port type is eDP or DP,
1180          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1181          * else clear to 0b.
1182          */
1183         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
1184         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1185                 val &= ~COMMON_KEEPER_EN;
1186         else
1187                 val |= COMMON_KEEPER_EN;
1188         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1189
1190         /* 2. Program loadgen select */
1191         /*
1192          * Program PORT_TX_DW4 depending on Bit rate and used lanes
1193          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1194          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1195          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1196          */
1197         for (ln = 0; ln < 4; ln++) {
1198                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1199                              LOADGEN_SELECT,
1200                              icl_combo_phy_loadgen_select(crtc_state, ln));
1201         }
1202
1203         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1204         intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
1205                      0, SUS_CLOCK_CONFIG);
1206
1207         /* 4. Clear training enable to change swing values */
1208         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1209         val &= ~TX_TRAINING_EN;
1210         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1211
1212         /* 5. Program swing and de-emphasis */
1213         icl_ddi_combo_vswing_program(encoder, crtc_state);
1214
1215         /* 6. Set training enable to trigger update */
1216         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1217         val |= TX_TRAINING_EN;
1218         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1219 }
1220
1221 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1222                                          const struct intel_crtc_state *crtc_state)
1223 {
1224         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1225         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1226         const struct intel_ddi_buf_trans *trans;
1227         int n_entries, ln;
1228
1229         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1230                 return;
1231
1232         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1233         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1234                 return;
1235
1236         for (ln = 0; ln < 2; ln++) {
1237                 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1238                              CRI_USE_FS32, 0);
1239                 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1240                              CRI_USE_FS32, 0);
1241         }
1242
1243         /* Program MG_TX_SWINGCTRL with values from vswing table */
1244         for (ln = 0; ln < 2; ln++) {
1245                 int level;
1246
1247                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1248
1249                 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1250                              CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1251                              CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1252
1253                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1254
1255                 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1256                              CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1257                              CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1258         }
1259
1260         /* Program MG_TX_DRVCTRL with values from vswing table */
1261         for (ln = 0; ln < 2; ln++) {
1262                 int level;
1263
1264                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1265
1266                 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1267                              CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1268                              CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1269                              CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1270                              CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1271                              CRI_TXDEEMPH_OVERRIDE_EN);
1272
1273                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1274
1275                 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1276                              CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1277                              CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1278                              CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1279                              CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1280                              CRI_TXDEEMPH_OVERRIDE_EN);
1281
1282                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1283         }
1284
1285         /*
1286          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1287          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1288          * values from table for which TX1 and TX2 enabled.
1289          */
1290         for (ln = 0; ln < 2; ln++) {
1291                 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1292                              CFG_LOW_RATE_LKREN_EN,
1293                              crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1294         }
1295
1296         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1297         for (ln = 0; ln < 2; ln++) {
1298                 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1299                              CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1300                              CFG_AMI_CK_DIV_OVERRIDE_EN,
1301                              crtc_state->port_clock > 500000 ?
1302                              CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1303                              CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1304
1305                 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1306                              CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1307                              CFG_AMI_CK_DIV_OVERRIDE_EN,
1308                              crtc_state->port_clock > 500000 ?
1309                              CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1310                              CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1311         }
1312
1313         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1314         for (ln = 0; ln < 2; ln++) {
1315                 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1316                              0, CRI_CALCINIT);
1317                 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1318                              0, CRI_CALCINIT);
1319         }
1320 }
1321
1322 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1323                                           const struct intel_crtc_state *crtc_state)
1324 {
1325         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1326         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1327         const struct intel_ddi_buf_trans *trans;
1328         int n_entries, ln;
1329
1330         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1331                 return;
1332
1333         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1334         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1335                 return;
1336
1337         for (ln = 0; ln < 2; ln++) {
1338                 int level;
1339
1340                 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1341
1342                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1343
1344                 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
1345                                   DKL_TX_PRESHOOT_COEFF_MASK |
1346                                   DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1347                                   DKL_TX_VSWING_CONTROL_MASK,
1348                                   DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1349                                   DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1350                                   DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1351
1352                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1353
1354                 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
1355                                   DKL_TX_PRESHOOT_COEFF_MASK |
1356                                   DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1357                                   DKL_TX_VSWING_CONTROL_MASK,
1358                                   DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1359                                   DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1360                                   DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1361
1362                 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1363                                   DKL_TX_DP20BITMODE, 0);
1364
1365                 if (IS_ALDERLAKE_P(dev_priv)) {
1366                         u32 val;
1367
1368                         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1369                                 if (ln == 0) {
1370                                         val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1371                                         val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1372                                 } else {
1373                                         val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1374                                         val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1375                                 }
1376                         } else {
1377                                 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1378                                 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1379                         }
1380
1381                         intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1382                                           DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1383                                           DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1384                                           val);
1385                 }
1386         }
1387 }
1388
1389 static int translate_signal_level(struct intel_dp *intel_dp,
1390                                   u8 signal_levels)
1391 {
1392         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1393         int i;
1394
1395         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1396                 if (index_to_dp_signal_levels[i] == signal_levels)
1397                         return i;
1398         }
1399
1400         drm_WARN(&i915->drm, 1,
1401                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1402                  signal_levels);
1403
1404         return 0;
1405 }
1406
1407 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1408                               const struct intel_crtc_state *crtc_state,
1409                               int lane)
1410 {
1411         u8 train_set = intel_dp->train_set[lane];
1412
1413         if (intel_dp_is_uhbr(crtc_state)) {
1414                 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1415         } else {
1416                 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1417                                                 DP_TRAIN_PRE_EMPHASIS_MASK);
1418
1419                 return translate_signal_level(intel_dp, signal_levels);
1420         }
1421 }
1422
1423 int intel_ddi_level(struct intel_encoder *encoder,
1424                     const struct intel_crtc_state *crtc_state,
1425                     int lane)
1426 {
1427         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1428         const struct intel_ddi_buf_trans *trans;
1429         int level, n_entries;
1430
1431         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1432         if (drm_WARN_ON_ONCE(&i915->drm, !trans))
1433                 return 0;
1434
1435         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1436                 level = intel_ddi_hdmi_level(encoder, trans);
1437         else
1438                 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1439                                            lane);
1440
1441         if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
1442                 level = n_entries - 1;
1443
1444         return level;
1445 }
1446
1447 static void
1448 hsw_set_signal_levels(struct intel_encoder *encoder,
1449                       const struct intel_crtc_state *crtc_state)
1450 {
1451         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1452         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1453         int level = intel_ddi_level(encoder, crtc_state, 0);
1454         enum port port = encoder->port;
1455         u32 signal_levels;
1456
1457         if (has_iboost(dev_priv))
1458                 skl_ddi_set_iboost(encoder, crtc_state, level);
1459
1460         /* HDMI ignores the rest */
1461         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1462                 return;
1463
1464         signal_levels = DDI_BUF_TRANS_SELECT(level);
1465
1466         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1467                     signal_levels);
1468
1469         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1470         intel_dp->DP |= signal_levels;
1471
1472         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1473         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1474 }
1475
1476 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1477                                   u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1478 {
1479         mutex_lock(&i915->display.dpll.lock);
1480
1481         intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1482
1483         /*
1484          * "This step and the step before must be
1485          *  done with separate register writes."
1486          */
1487         intel_de_rmw(i915, reg, clk_off, 0);
1488
1489         mutex_unlock(&i915->display.dpll.lock);
1490 }
1491
1492 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1493                                    u32 clk_off)
1494 {
1495         mutex_lock(&i915->display.dpll.lock);
1496
1497         intel_de_rmw(i915, reg, 0, clk_off);
1498
1499         mutex_unlock(&i915->display.dpll.lock);
1500 }
1501
1502 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1503                                       u32 clk_off)
1504 {
1505         return !(intel_de_read(i915, reg) & clk_off);
1506 }
1507
1508 static struct intel_shared_dpll *
1509 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1510                  u32 clk_sel_mask, u32 clk_sel_shift)
1511 {
1512         enum intel_dpll_id id;
1513
1514         id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1515
1516         return intel_get_shared_dpll_by_id(i915, id);
1517 }
1518
1519 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1520                                   const struct intel_crtc_state *crtc_state)
1521 {
1522         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1523         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1524         enum phy phy = intel_port_to_phy(i915, encoder->port);
1525
1526         if (drm_WARN_ON(&i915->drm, !pll))
1527                 return;
1528
1529         _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1530                               ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1531                               pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1532                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1533 }
1534
1535 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1536 {
1537         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1538         enum phy phy = intel_port_to_phy(i915, encoder->port);
1539
1540         _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1541                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1542 }
1543
1544 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1545 {
1546         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1547         enum phy phy = intel_port_to_phy(i915, encoder->port);
1548
1549         return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1550                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1551 }
1552
1553 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1554 {
1555         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1556         enum phy phy = intel_port_to_phy(i915, encoder->port);
1557
1558         return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1559                                 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1560                                 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1561 }
1562
1563 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1564                                  const struct intel_crtc_state *crtc_state)
1565 {
1566         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1567         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1568         enum phy phy = intel_port_to_phy(i915, encoder->port);
1569
1570         if (drm_WARN_ON(&i915->drm, !pll))
1571                 return;
1572
1573         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1574                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1575                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1576                               RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1577 }
1578
1579 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1580 {
1581         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1582         enum phy phy = intel_port_to_phy(i915, encoder->port);
1583
1584         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1585                                RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1586 }
1587
1588 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1589 {
1590         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1591         enum phy phy = intel_port_to_phy(i915, encoder->port);
1592
1593         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1594                                          RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1595 }
1596
1597 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1598 {
1599         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1600         enum phy phy = intel_port_to_phy(i915, encoder->port);
1601
1602         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1603                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1604                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1605 }
1606
1607 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1608                                  const struct intel_crtc_state *crtc_state)
1609 {
1610         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1611         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1612         enum phy phy = intel_port_to_phy(i915, encoder->port);
1613
1614         if (drm_WARN_ON(&i915->drm, !pll))
1615                 return;
1616
1617         /*
1618          * If we fail this, something went very wrong: first 2 PLLs should be
1619          * used by first 2 phys and last 2 PLLs by last phys
1620          */
1621         if (drm_WARN_ON(&i915->drm,
1622                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1623                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1624                 return;
1625
1626         _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1627                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1628                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1629                               DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1630 }
1631
1632 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1633 {
1634         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1635         enum phy phy = intel_port_to_phy(i915, encoder->port);
1636
1637         _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1638                                DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1639 }
1640
1641 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1642 {
1643         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1644         enum phy phy = intel_port_to_phy(i915, encoder->port);
1645
1646         return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1647                                          DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1648 }
1649
1650 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1651 {
1652         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1653         enum phy phy = intel_port_to_phy(i915, encoder->port);
1654         enum intel_dpll_id id;
1655         u32 val;
1656
1657         val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1658         val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1659         val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1660         id = val;
1661
1662         /*
1663          * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1664          * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1665          * bit for phy C and D.
1666          */
1667         if (phy >= PHY_C)
1668                 id += DPLL_ID_DG1_DPLL2;
1669
1670         return intel_get_shared_dpll_by_id(i915, id);
1671 }
1672
1673 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1674                                        const struct intel_crtc_state *crtc_state)
1675 {
1676         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1677         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1678         enum phy phy = intel_port_to_phy(i915, encoder->port);
1679
1680         if (drm_WARN_ON(&i915->drm, !pll))
1681                 return;
1682
1683         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1684                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1685                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1686                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1687 }
1688
1689 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1690 {
1691         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1692         enum phy phy = intel_port_to_phy(i915, encoder->port);
1693
1694         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1695                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1696 }
1697
1698 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1699 {
1700         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1701         enum phy phy = intel_port_to_phy(i915, encoder->port);
1702
1703         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1704                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1705 }
1706
1707 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1708 {
1709         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1710         enum phy phy = intel_port_to_phy(i915, encoder->port);
1711
1712         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1713                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1714                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1715 }
1716
1717 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1718                                     const struct intel_crtc_state *crtc_state)
1719 {
1720         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1721         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1722         enum port port = encoder->port;
1723
1724         if (drm_WARN_ON(&i915->drm, !pll))
1725                 return;
1726
1727         /*
1728          * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1729          *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1730          */
1731         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1732
1733         icl_ddi_combo_enable_clock(encoder, crtc_state);
1734 }
1735
1736 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1737 {
1738         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1739         enum port port = encoder->port;
1740
1741         icl_ddi_combo_disable_clock(encoder);
1742
1743         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1744 }
1745
1746 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1747 {
1748         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1749         enum port port = encoder->port;
1750         u32 tmp;
1751
1752         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1753
1754         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1755                 return false;
1756
1757         return icl_ddi_combo_is_clock_enabled(encoder);
1758 }
1759
1760 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1761                                     const struct intel_crtc_state *crtc_state)
1762 {
1763         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1764         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1765         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1766         enum port port = encoder->port;
1767
1768         if (drm_WARN_ON(&i915->drm, !pll))
1769                 return;
1770
1771         intel_de_write(i915, DDI_CLK_SEL(port),
1772                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1773
1774         mutex_lock(&i915->display.dpll.lock);
1775
1776         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1777                      ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1778
1779         mutex_unlock(&i915->display.dpll.lock);
1780 }
1781
1782 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1783 {
1784         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1785         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1786         enum port port = encoder->port;
1787
1788         mutex_lock(&i915->display.dpll.lock);
1789
1790         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1791                      0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1792
1793         mutex_unlock(&i915->display.dpll.lock);
1794
1795         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1796 }
1797
1798 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1799 {
1800         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1801         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1802         enum port port = encoder->port;
1803         u32 tmp;
1804
1805         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1806
1807         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1808                 return false;
1809
1810         tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1811
1812         return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1813 }
1814
1815 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1816 {
1817         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1818         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1819         enum port port = encoder->port;
1820         enum intel_dpll_id id;
1821         u32 tmp;
1822
1823         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1824
1825         switch (tmp & DDI_CLK_SEL_MASK) {
1826         case DDI_CLK_SEL_TBT_162:
1827         case DDI_CLK_SEL_TBT_270:
1828         case DDI_CLK_SEL_TBT_540:
1829         case DDI_CLK_SEL_TBT_810:
1830                 id = DPLL_ID_ICL_TBTPLL;
1831                 break;
1832         case DDI_CLK_SEL_MG:
1833                 id = icl_tc_port_to_pll_id(tc_port);
1834                 break;
1835         default:
1836                 MISSING_CASE(tmp);
1837                 fallthrough;
1838         case DDI_CLK_SEL_NONE:
1839                 return NULL;
1840         }
1841
1842         return intel_get_shared_dpll_by_id(i915, id);
1843 }
1844
1845 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1846 {
1847         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1848         enum intel_dpll_id id;
1849
1850         switch (encoder->port) {
1851         case PORT_A:
1852                 id = DPLL_ID_SKL_DPLL0;
1853                 break;
1854         case PORT_B:
1855                 id = DPLL_ID_SKL_DPLL1;
1856                 break;
1857         case PORT_C:
1858                 id = DPLL_ID_SKL_DPLL2;
1859                 break;
1860         default:
1861                 MISSING_CASE(encoder->port);
1862                 return NULL;
1863         }
1864
1865         return intel_get_shared_dpll_by_id(i915, id);
1866 }
1867
1868 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1869                                  const struct intel_crtc_state *crtc_state)
1870 {
1871         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1872         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1873         enum port port = encoder->port;
1874
1875         if (drm_WARN_ON(&i915->drm, !pll))
1876                 return;
1877
1878         mutex_lock(&i915->display.dpll.lock);
1879
1880         intel_de_rmw(i915, DPLL_CTRL2,
1881                      DPLL_CTRL2_DDI_CLK_OFF(port) |
1882                      DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1883                      DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1884                      DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1885
1886         mutex_unlock(&i915->display.dpll.lock);
1887 }
1888
1889 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1890 {
1891         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1892         enum port port = encoder->port;
1893
1894         mutex_lock(&i915->display.dpll.lock);
1895
1896         intel_de_rmw(i915, DPLL_CTRL2,
1897                      0, DPLL_CTRL2_DDI_CLK_OFF(port));
1898
1899         mutex_unlock(&i915->display.dpll.lock);
1900 }
1901
1902 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1903 {
1904         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1905         enum port port = encoder->port;
1906
1907         /*
1908          * FIXME Not sure if the override affects both
1909          * the PLL selection and the CLK_OFF bit.
1910          */
1911         return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1912 }
1913
1914 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1915 {
1916         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1917         enum port port = encoder->port;
1918         enum intel_dpll_id id;
1919         u32 tmp;
1920
1921         tmp = intel_de_read(i915, DPLL_CTRL2);
1922
1923         /*
1924          * FIXME Not sure if the override affects both
1925          * the PLL selection and the CLK_OFF bit.
1926          */
1927         if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1928                 return NULL;
1929
1930         id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1931                 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1932
1933         return intel_get_shared_dpll_by_id(i915, id);
1934 }
1935
1936 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1937                           const struct intel_crtc_state *crtc_state)
1938 {
1939         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1940         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1941         enum port port = encoder->port;
1942
1943         if (drm_WARN_ON(&i915->drm, !pll))
1944                 return;
1945
1946         intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1947 }
1948
1949 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1950 {
1951         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1952         enum port port = encoder->port;
1953
1954         intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1955 }
1956
1957 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1958 {
1959         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1960         enum port port = encoder->port;
1961
1962         return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1963 }
1964
1965 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1966 {
1967         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1968         enum port port = encoder->port;
1969         enum intel_dpll_id id;
1970         u32 tmp;
1971
1972         tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1973
1974         switch (tmp & PORT_CLK_SEL_MASK) {
1975         case PORT_CLK_SEL_WRPLL1:
1976                 id = DPLL_ID_WRPLL1;
1977                 break;
1978         case PORT_CLK_SEL_WRPLL2:
1979                 id = DPLL_ID_WRPLL2;
1980                 break;
1981         case PORT_CLK_SEL_SPLL:
1982                 id = DPLL_ID_SPLL;
1983                 break;
1984         case PORT_CLK_SEL_LCPLL_810:
1985                 id = DPLL_ID_LCPLL_810;
1986                 break;
1987         case PORT_CLK_SEL_LCPLL_1350:
1988                 id = DPLL_ID_LCPLL_1350;
1989                 break;
1990         case PORT_CLK_SEL_LCPLL_2700:
1991                 id = DPLL_ID_LCPLL_2700;
1992                 break;
1993         default:
1994                 MISSING_CASE(tmp);
1995                 fallthrough;
1996         case PORT_CLK_SEL_NONE:
1997                 return NULL;
1998         }
1999
2000         return intel_get_shared_dpll_by_id(i915, id);
2001 }
2002
2003 void intel_ddi_enable_clock(struct intel_encoder *encoder,
2004                             const struct intel_crtc_state *crtc_state)
2005 {
2006         if (encoder->enable_clock)
2007                 encoder->enable_clock(encoder, crtc_state);
2008 }
2009
2010 void intel_ddi_disable_clock(struct intel_encoder *encoder)
2011 {
2012         if (encoder->disable_clock)
2013                 encoder->disable_clock(encoder);
2014 }
2015
2016 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2017 {
2018         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2019         u32 port_mask;
2020         bool ddi_clk_needed;
2021
2022         /*
2023          * In case of DP MST, we sanitize the primary encoder only, not the
2024          * virtual ones.
2025          */
2026         if (encoder->type == INTEL_OUTPUT_DP_MST)
2027                 return;
2028
2029         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2030                 u8 pipe_mask;
2031                 bool is_mst;
2032
2033                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2034                 /*
2035                  * In the unlikely case that BIOS enables DP in MST mode, just
2036                  * warn since our MST HW readout is incomplete.
2037                  */
2038                 if (drm_WARN_ON(&i915->drm, is_mst))
2039                         return;
2040         }
2041
2042         port_mask = BIT(encoder->port);
2043         ddi_clk_needed = encoder->base.crtc;
2044
2045         if (encoder->type == INTEL_OUTPUT_DSI) {
2046                 struct intel_encoder *other_encoder;
2047
2048                 port_mask = intel_dsi_encoder_ports(encoder);
2049                 /*
2050                  * Sanity check that we haven't incorrectly registered another
2051                  * encoder using any of the ports of this DSI encoder.
2052                  */
2053                 for_each_intel_encoder(&i915->drm, other_encoder) {
2054                         if (other_encoder == encoder)
2055                                 continue;
2056
2057                         if (drm_WARN_ON(&i915->drm,
2058                                         port_mask & BIT(other_encoder->port)))
2059                                 return;
2060                 }
2061                 /*
2062                  * For DSI we keep the ddi clocks gated
2063                  * except during enable/disable sequence.
2064                  */
2065                 ddi_clk_needed = false;
2066         }
2067
2068         if (ddi_clk_needed || !encoder->is_clock_enabled ||
2069             !encoder->is_clock_enabled(encoder))
2070                 return;
2071
2072         drm_notice(&i915->drm,
2073                    "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2074                    encoder->base.base.id, encoder->base.name);
2075
2076         encoder->disable_clock(encoder);
2077 }
2078
2079 static void
2080 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2081                        const struct intel_crtc_state *crtc_state)
2082 {
2083         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2084         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2085         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2086         u32 ln0, ln1, pin_assignment;
2087         u8 width;
2088
2089         if (!intel_phy_is_tc(dev_priv, phy) ||
2090             intel_tc_port_in_tbt_alt_mode(dig_port))
2091                 return;
2092
2093         if (DISPLAY_VER(dev_priv) >= 12) {
2094                 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
2095                 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
2096         } else {
2097                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2098                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2099         }
2100
2101         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2102         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2103
2104         /* DPPATC */
2105         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2106         width = crtc_state->lane_count;
2107
2108         switch (pin_assignment) {
2109         case 0x0:
2110                 drm_WARN_ON(&dev_priv->drm,
2111                             !intel_tc_port_in_legacy_mode(dig_port));
2112                 if (width == 1) {
2113                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2114                 } else {
2115                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2116                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2117                 }
2118                 break;
2119         case 0x1:
2120                 if (width == 4) {
2121                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2122                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2123                 }
2124                 break;
2125         case 0x2:
2126                 if (width == 2) {
2127                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2128                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2129                 }
2130                 break;
2131         case 0x3:
2132         case 0x5:
2133                 if (width == 1) {
2134                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2135                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2136                 } else {
2137                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2138                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2139                 }
2140                 break;
2141         case 0x4:
2142         case 0x6:
2143                 if (width == 1) {
2144                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2145                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2146                 } else {
2147                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2148                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2149                 }
2150                 break;
2151         default:
2152                 MISSING_CASE(pin_assignment);
2153         }
2154
2155         if (DISPLAY_VER(dev_priv) >= 12) {
2156                 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
2157                 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
2158         } else {
2159                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2160                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2161         }
2162 }
2163
2164 static enum transcoder
2165 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2166 {
2167         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2168                 return crtc_state->mst_master_transcoder;
2169         else
2170                 return crtc_state->cpu_transcoder;
2171 }
2172
2173 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2174                          const struct intel_crtc_state *crtc_state)
2175 {
2176         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2177
2178         if (DISPLAY_VER(dev_priv) >= 12)
2179                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2180         else
2181                 return DP_TP_CTL(encoder->port);
2182 }
2183
2184 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2185                             const struct intel_crtc_state *crtc_state)
2186 {
2187         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2188
2189         if (DISPLAY_VER(dev_priv) >= 12)
2190                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2191         else
2192                 return DP_TP_STATUS(encoder->port);
2193 }
2194
2195 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2196                                                           const struct intel_crtc_state *crtc_state,
2197                                                           bool enable)
2198 {
2199         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2200
2201         if (!crtc_state->vrr.enable)
2202                 return;
2203
2204         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2205                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2206                 drm_dbg_kms(&i915->drm,
2207                             "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2208                             str_enable_disable(enable));
2209 }
2210
2211 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2212                                         const struct intel_crtc_state *crtc_state)
2213 {
2214         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2215
2216         if (!crtc_state->fec_enable)
2217                 return;
2218
2219         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2220                 drm_dbg_kms(&i915->drm,
2221                             "Failed to set FEC_READY in the sink\n");
2222 }
2223
2224 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2225                                  const struct intel_crtc_state *crtc_state)
2226 {
2227         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2228         struct intel_dp *intel_dp;
2229
2230         if (!crtc_state->fec_enable)
2231                 return;
2232
2233         intel_dp = enc_to_intel_dp(encoder);
2234         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2235                      0, DP_TP_CTL_FEC_ENABLE);
2236 }
2237
2238 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2239                                         const struct intel_crtc_state *crtc_state)
2240 {
2241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2242         struct intel_dp *intel_dp;
2243
2244         if (!crtc_state->fec_enable)
2245                 return;
2246
2247         intel_dp = enc_to_intel_dp(encoder);
2248         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2249                      DP_TP_CTL_FEC_ENABLE, 0);
2250         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2251 }
2252
2253 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2254                                      const struct intel_crtc_state *crtc_state)
2255 {
2256         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2257         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2258         enum phy phy = intel_port_to_phy(i915, encoder->port);
2259
2260         if (intel_phy_is_combo(i915, phy)) {
2261                 bool lane_reversal =
2262                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2263
2264                 intel_combo_phy_power_up_lanes(i915, phy, false,
2265                                                crtc_state->lane_count,
2266                                                lane_reversal);
2267         }
2268 }
2269
2270 /* Splitter enable for eDP MSO is limited to certain pipes. */
2271 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2272 {
2273         if (IS_ALDERLAKE_P(i915))
2274                 return BIT(PIPE_A) | BIT(PIPE_B);
2275         else
2276                 return BIT(PIPE_A);
2277 }
2278
2279 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2280                                      struct intel_crtc_state *pipe_config)
2281 {
2282         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2283         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2284         enum pipe pipe = crtc->pipe;
2285         u32 dss1;
2286
2287         if (!HAS_MSO(i915))
2288                 return;
2289
2290         dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2291
2292         pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2293         if (!pipe_config->splitter.enable)
2294                 return;
2295
2296         if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2297                 pipe_config->splitter.enable = false;
2298                 return;
2299         }
2300
2301         switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2302         default:
2303                 drm_WARN(&i915->drm, true,
2304                          "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2305                 fallthrough;
2306         case SPLITTER_CONFIGURATION_2_SEGMENT:
2307                 pipe_config->splitter.link_count = 2;
2308                 break;
2309         case SPLITTER_CONFIGURATION_4_SEGMENT:
2310                 pipe_config->splitter.link_count = 4;
2311                 break;
2312         }
2313
2314         pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2315 }
2316
2317 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2318 {
2319         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2320         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2321         enum pipe pipe = crtc->pipe;
2322         u32 dss1 = 0;
2323
2324         if (!HAS_MSO(i915))
2325                 return;
2326
2327         if (crtc_state->splitter.enable) {
2328                 dss1 |= SPLITTER_ENABLE;
2329                 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2330                 if (crtc_state->splitter.link_count == 2)
2331                         dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2332                 else
2333                         dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2334         }
2335
2336         intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2337                      SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2338                      OVERLAP_PIXELS_MASK, dss1);
2339 }
2340
2341 static u8 mtl_get_port_width(u8 lane_count)
2342 {
2343         switch (lane_count) {
2344         case 1:
2345                 return 0;
2346         case 2:
2347                 return 1;
2348         case 3:
2349                 return 4;
2350         case 4:
2351                 return 3;
2352         default:
2353                 MISSING_CASE(lane_count);
2354                 return 4;
2355         }
2356 }
2357
2358 static void
2359 mtl_ddi_enable_d2d(struct intel_encoder *encoder)
2360 {
2361         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2362         enum port port = encoder->port;
2363
2364         intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
2365                      XELPDP_PORT_BUF_D2D_LINK_ENABLE);
2366
2367         if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
2368                          XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
2369                 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
2370                         port_name(port));
2371         }
2372 }
2373
2374 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
2375                                      const struct intel_crtc_state *crtc_state)
2376 {
2377         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2378         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2379         enum port port = encoder->port;
2380         u32 val;
2381
2382         val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
2383         val &= ~XELPDP_PORT_WIDTH_MASK;
2384         val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
2385
2386         val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
2387         if (intel_dp_is_uhbr(crtc_state))
2388                 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
2389         else
2390                 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
2391
2392         if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
2393                 val |= XELPDP_PORT_REVERSAL;
2394
2395         intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
2396 }
2397
2398 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
2399 {
2400         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2401         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2402         u32 val;
2403
2404         val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
2405               XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
2406         intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
2407                      XELPDP_PORT_BUF_IO_SELECT_TBT, val);
2408 }
2409
2410 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2411                                   struct intel_encoder *encoder,
2412                                   const struct intel_crtc_state *crtc_state,
2413                                   const struct drm_connector_state *conn_state)
2414 {
2415         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2416         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2417
2418         intel_dp_set_link_params(intel_dp,
2419                                  crtc_state->port_clock,
2420                                  crtc_state->lane_count);
2421
2422         /*
2423          * We only configure what the register value will be here.  Actual
2424          * enabling happens during link training farther down.
2425          */
2426         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2427
2428         /*
2429          * 1. Enable Power Wells
2430          *
2431          * This was handled at the beginning of intel_atomic_commit_tail(),
2432          * before we called down into this function.
2433          */
2434
2435         /* 2. PMdemand was already set */
2436
2437         /* 3. Select Thunderbolt */
2438         mtl_port_buf_ctl_io_selection(encoder);
2439
2440         /* 4. Enable Panel Power if PPS is required */
2441         intel_pps_on(intel_dp);
2442
2443         /* 5. Enable the port PLL */
2444         intel_ddi_enable_clock(encoder, crtc_state);
2445
2446         /*
2447          * 6.a Configure Transcoder Clock Select to direct the Port clock to the
2448          * Transcoder.
2449          */
2450         intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2451
2452         /*
2453          * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
2454          */
2455         intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2456
2457         /*
2458          * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2459          * Transport Select
2460          */
2461         intel_ddi_config_transcoder_func(encoder, crtc_state);
2462
2463         /*
2464          * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2465          */
2466         intel_ddi_mso_configure(crtc_state);
2467
2468         if (!is_mst)
2469                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2470
2471         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2472         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2473         /*
2474          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2475          * in the FEC_CONFIGURATION register to 1 before initiating link
2476          * training
2477          */
2478         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2479
2480         intel_dp_check_frl_training(intel_dp);
2481         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2482
2483         /*
2484          * 6. The rest of the below are substeps under the bspec's "Enable and
2485          * Train Display Port" step.  Note that steps that are specific to
2486          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2487          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2488          * us when active_mst_links==0, so any steps designated for "single
2489          * stream or multi-stream master transcoder" can just be performed
2490          * unconditionally here.
2491          *
2492          * mtl_ddi_prepare_link_retrain() that is called by
2493          * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
2494          * 6.i and 6.j
2495          *
2496          * 6.k Follow DisplayPort specification training sequence (see notes for
2497          *     failure handling)
2498          * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2499          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2500          *     (timeout after 800 us)
2501          */
2502         intel_dp_start_link_train(intel_dp, crtc_state);
2503
2504         /* 6.n Set DP_TP_CTL link training to Normal */
2505         if (!is_trans_port_sync_mode(crtc_state))
2506                 intel_dp_stop_link_train(intel_dp, crtc_state);
2507
2508         /* 6.o Configure and enable FEC if needed */
2509         intel_ddi_enable_fec(encoder, crtc_state);
2510
2511         intel_dsc_dp_pps_write(encoder, crtc_state);
2512 }
2513
2514 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2515                                   struct intel_encoder *encoder,
2516                                   const struct intel_crtc_state *crtc_state,
2517                                   const struct drm_connector_state *conn_state)
2518 {
2519         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2520         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2521         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2522         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2523
2524         intel_dp_set_link_params(intel_dp,
2525                                  crtc_state->port_clock,
2526                                  crtc_state->lane_count);
2527
2528         /*
2529          * We only configure what the register value will be here.  Actual
2530          * enabling happens during link training farther down.
2531          */
2532         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2533
2534         /*
2535          * 1. Enable Power Wells
2536          *
2537          * This was handled at the beginning of intel_atomic_commit_tail(),
2538          * before we called down into this function.
2539          */
2540
2541         /* 2. Enable Panel Power if PPS is required */
2542         intel_pps_on(intel_dp);
2543
2544         /*
2545          * 3. For non-TBT Type-C ports, set FIA lane count
2546          * (DFLEXDPSP.DPX4TXLATC)
2547          *
2548          * This was done before tgl_ddi_pre_enable_dp by
2549          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2550          */
2551
2552         /*
2553          * 4. Enable the port PLL.
2554          *
2555          * The PLL enabling itself was already done before this function by
2556          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2557          * configure the PLL to port mapping here.
2558          */
2559         intel_ddi_enable_clock(encoder, crtc_state);
2560
2561         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2562         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2563                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2564                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2565                                                                    dig_port->ddi_io_power_domain);
2566         }
2567
2568         /* 6. Program DP_MODE */
2569         icl_program_mg_dp_mode(dig_port, crtc_state);
2570
2571         /*
2572          * 7. The rest of the below are substeps under the bspec's "Enable and
2573          * Train Display Port" step.  Note that steps that are specific to
2574          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2575          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2576          * us when active_mst_links==0, so any steps designated for "single
2577          * stream or multi-stream master transcoder" can just be performed
2578          * unconditionally here.
2579          */
2580
2581         /*
2582          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2583          * Transcoder.
2584          */
2585         intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2586
2587         if (HAS_DP20(dev_priv))
2588                 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2589
2590         /*
2591          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2592          * Transport Select
2593          */
2594         intel_ddi_config_transcoder_func(encoder, crtc_state);
2595
2596         /*
2597          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2598          * selected
2599          *
2600          * This will be handled by the intel_dp_start_link_train() farther
2601          * down this function.
2602          */
2603
2604         /* 7.e Configure voltage swing and related IO settings */
2605         encoder->set_signal_levels(encoder, crtc_state);
2606
2607         /*
2608          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2609          * the used lanes of the DDI.
2610          */
2611         intel_ddi_power_up_lanes(encoder, crtc_state);
2612
2613         /*
2614          * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2615          */
2616         intel_ddi_mso_configure(crtc_state);
2617
2618         if (!is_mst)
2619                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2620
2621         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2622         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2623         /*
2624          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2625          * in the FEC_CONFIGURATION register to 1 before initiating link
2626          * training
2627          */
2628         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2629
2630         intel_dp_check_frl_training(intel_dp);
2631         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2632
2633         /*
2634          * 7.i Follow DisplayPort specification training sequence (see notes for
2635          *     failure handling)
2636          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2637          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2638          *     (timeout after 800 us)
2639          */
2640         intel_dp_start_link_train(intel_dp, crtc_state);
2641
2642         /* 7.k Set DP_TP_CTL link training to Normal */
2643         if (!is_trans_port_sync_mode(crtc_state))
2644                 intel_dp_stop_link_train(intel_dp, crtc_state);
2645
2646         /* 7.l Configure and enable FEC if needed */
2647         intel_ddi_enable_fec(encoder, crtc_state);
2648
2649         intel_dsc_dp_pps_write(encoder, crtc_state);
2650 }
2651
2652 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2653                                   struct intel_encoder *encoder,
2654                                   const struct intel_crtc_state *crtc_state,
2655                                   const struct drm_connector_state *conn_state)
2656 {
2657         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2658         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2659         enum port port = encoder->port;
2660         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2661         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2662
2663         if (DISPLAY_VER(dev_priv) < 11)
2664                 drm_WARN_ON(&dev_priv->drm,
2665                             is_mst && (port == PORT_A || port == PORT_E));
2666         else
2667                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2668
2669         intel_dp_set_link_params(intel_dp,
2670                                  crtc_state->port_clock,
2671                                  crtc_state->lane_count);
2672
2673         /*
2674          * We only configure what the register value will be here.  Actual
2675          * enabling happens during link training farther down.
2676          */
2677         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2678
2679         intel_pps_on(intel_dp);
2680
2681         intel_ddi_enable_clock(encoder, crtc_state);
2682
2683         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2684                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2685                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2686                                                                    dig_port->ddi_io_power_domain);
2687         }
2688
2689         icl_program_mg_dp_mode(dig_port, crtc_state);
2690
2691         if (has_buf_trans_select(dev_priv))
2692                 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2693
2694         encoder->set_signal_levels(encoder, crtc_state);
2695
2696         intel_ddi_power_up_lanes(encoder, crtc_state);
2697
2698         if (!is_mst)
2699                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2700         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2701         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2702                                               true);
2703         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2704         intel_dp_start_link_train(intel_dp, crtc_state);
2705         if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2706             !is_trans_port_sync_mode(crtc_state))
2707                 intel_dp_stop_link_train(intel_dp, crtc_state);
2708
2709         intel_ddi_enable_fec(encoder, crtc_state);
2710
2711         if (!is_mst)
2712                 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2713
2714         intel_dsc_dp_pps_write(encoder, crtc_state);
2715 }
2716
2717 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2718                                     struct intel_encoder *encoder,
2719                                     const struct intel_crtc_state *crtc_state,
2720                                     const struct drm_connector_state *conn_state)
2721 {
2722         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2723
2724         if (HAS_DP20(dev_priv))
2725                 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
2726                                             crtc_state);
2727
2728         if (DISPLAY_VER(dev_priv) >= 14)
2729                 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2730         else if (DISPLAY_VER(dev_priv) >= 12)
2731                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2732         else
2733                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2734
2735         /* MST will call a setting of MSA after an allocating of Virtual Channel
2736          * from MST encoder pre_enable callback.
2737          */
2738         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2739                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2740 }
2741
2742 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2743                                       struct intel_encoder *encoder,
2744                                       const struct intel_crtc_state *crtc_state,
2745                                       const struct drm_connector_state *conn_state)
2746 {
2747         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2748         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2749         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2750
2751         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2752         intel_ddi_enable_clock(encoder, crtc_state);
2753
2754         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2755         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2756                                                            dig_port->ddi_io_power_domain);
2757
2758         icl_program_mg_dp_mode(dig_port, crtc_state);
2759
2760         intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2761
2762         dig_port->set_infoframes(encoder,
2763                                  crtc_state->has_infoframe,
2764                                  crtc_state, conn_state);
2765 }
2766
2767 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2768                                  struct intel_encoder *encoder,
2769                                  const struct intel_crtc_state *crtc_state,
2770                                  const struct drm_connector_state *conn_state)
2771 {
2772         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2773         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2774         enum pipe pipe = crtc->pipe;
2775
2776         /*
2777          * When called from DP MST code:
2778          * - conn_state will be NULL
2779          * - encoder will be the main encoder (ie. mst->primary)
2780          * - the main connector associated with this port
2781          *   won't be active or linked to a crtc
2782          * - crtc_state will be the state of the first stream to
2783          *   be activated on this port, and it may not be the same
2784          *   stream that will be deactivated last, but each stream
2785          *   should have a state that is identical when it comes to
2786          *   the DP link parameteres
2787          */
2788
2789         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2790
2791         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2792
2793         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2794                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2795                                           conn_state);
2796         } else {
2797                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2798
2799                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2800                                         conn_state);
2801
2802                 /* FIXME precompute everything properly */
2803                 /* FIXME how do we turn infoframes off again? */
2804                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2805                         dig_port->set_infoframes(encoder,
2806                                                  crtc_state->has_infoframe,
2807                                                  crtc_state, conn_state);
2808         }
2809 }
2810
2811 static void
2812 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
2813 {
2814         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2815         enum port port = encoder->port;
2816
2817         intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
2818                      XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
2819
2820         if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
2821                           XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
2822                 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
2823                         port_name(port));
2824 }
2825
2826 static void mtl_disable_ddi_buf(struct intel_encoder *encoder,
2827                                 const struct intel_crtc_state *crtc_state)
2828 {
2829         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2830         enum port port = encoder->port;
2831         u32 val;
2832
2833         /* 3.b Clear DDI_CTL_DE Enable to 0. */
2834         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2835         if (val & DDI_BUF_CTL_ENABLE) {
2836                 val &= ~DDI_BUF_CTL_ENABLE;
2837                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2838
2839                 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */
2840                 mtl_wait_ddi_buf_idle(dev_priv, port);
2841         }
2842
2843         /* 3.d Disable D2D Link */
2844         mtl_ddi_disable_d2d_link(encoder);
2845
2846         /* 3.e Disable DP_TP_CTL */
2847         if (intel_crtc_has_dp_encoder(crtc_state)) {
2848                 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2849                              DP_TP_CTL_ENABLE, 0);
2850         }
2851 }
2852
2853 static void disable_ddi_buf(struct intel_encoder *encoder,
2854                             const struct intel_crtc_state *crtc_state)
2855 {
2856         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2857         enum port port = encoder->port;
2858         bool wait = false;
2859         u32 val;
2860
2861         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2862         if (val & DDI_BUF_CTL_ENABLE) {
2863                 val &= ~DDI_BUF_CTL_ENABLE;
2864                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2865                 wait = true;
2866         }
2867
2868         if (intel_crtc_has_dp_encoder(crtc_state))
2869                 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2870                              DP_TP_CTL_ENABLE, 0);
2871
2872         /* Disable FEC in DP Sink */
2873         intel_ddi_disable_fec_state(encoder, crtc_state);
2874
2875         if (wait)
2876                 intel_wait_ddi_buf_idle(dev_priv, port);
2877 }
2878
2879 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2880                                   const struct intel_crtc_state *crtc_state)
2881 {
2882         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2883
2884         if (DISPLAY_VER(dev_priv) >= 14) {
2885                 mtl_disable_ddi_buf(encoder, crtc_state);
2886
2887                 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */
2888                 intel_ddi_disable_fec_state(encoder, crtc_state);
2889         } else {
2890                 disable_ddi_buf(encoder, crtc_state);
2891         }
2892 }
2893
2894 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2895                                       struct intel_encoder *encoder,
2896                                       const struct intel_crtc_state *old_crtc_state,
2897                                       const struct drm_connector_state *old_conn_state)
2898 {
2899         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2900         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2901         struct intel_dp *intel_dp = &dig_port->dp;
2902         intel_wakeref_t wakeref;
2903         bool is_mst = intel_crtc_has_type(old_crtc_state,
2904                                           INTEL_OUTPUT_DP_MST);
2905
2906         if (!is_mst)
2907                 intel_dp_set_infoframes(encoder, false,
2908                                         old_crtc_state, old_conn_state);
2909
2910         /*
2911          * Power down sink before disabling the port, otherwise we end
2912          * up getting interrupts from the sink on detecting link loss.
2913          */
2914         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2915
2916         if (DISPLAY_VER(dev_priv) >= 12) {
2917                 if (is_mst) {
2918                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2919
2920                         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
2921                                      TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
2922                                      0);
2923                 }
2924         } else {
2925                 if (!is_mst)
2926                         intel_ddi_disable_transcoder_clock(old_crtc_state);
2927         }
2928
2929         intel_disable_ddi_buf(encoder, old_crtc_state);
2930
2931         /*
2932          * From TGL spec: "If single stream or multi-stream master transcoder:
2933          * Configure Transcoder Clock select to direct no clock to the
2934          * transcoder"
2935          */
2936         if (DISPLAY_VER(dev_priv) >= 12)
2937                 intel_ddi_disable_transcoder_clock(old_crtc_state);
2938
2939         intel_pps_vdd_on(intel_dp);
2940         intel_pps_off(intel_dp);
2941
2942         wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
2943
2944         if (wakeref)
2945                 intel_display_power_put(dev_priv,
2946                                         dig_port->ddi_io_power_domain,
2947                                         wakeref);
2948
2949         intel_ddi_disable_clock(encoder);
2950
2951         /* De-select Thunderbolt */
2952         if (DISPLAY_VER(dev_priv) >= 14)
2953                 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
2954                              XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
2955 }
2956
2957 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2958                                         struct intel_encoder *encoder,
2959                                         const struct intel_crtc_state *old_crtc_state,
2960                                         const struct drm_connector_state *old_conn_state)
2961 {
2962         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2963         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2964         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2965         intel_wakeref_t wakeref;
2966
2967         dig_port->set_infoframes(encoder, false,
2968                                  old_crtc_state, old_conn_state);
2969
2970         if (DISPLAY_VER(dev_priv) < 12)
2971                 intel_ddi_disable_transcoder_clock(old_crtc_state);
2972
2973         intel_disable_ddi_buf(encoder, old_crtc_state);
2974
2975         if (DISPLAY_VER(dev_priv) >= 12)
2976                 intel_ddi_disable_transcoder_clock(old_crtc_state);
2977
2978         wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
2979         if (wakeref)
2980                 intel_display_power_put(dev_priv,
2981                                         dig_port->ddi_io_power_domain,
2982                                         wakeref);
2983
2984         intel_ddi_disable_clock(encoder);
2985
2986         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2987 }
2988
2989 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2990                                    struct intel_encoder *encoder,
2991                                    const struct intel_crtc_state *old_crtc_state,
2992                                    const struct drm_connector_state *old_conn_state)
2993 {
2994         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2995         struct intel_crtc *slave_crtc;
2996
2997         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2998                 intel_crtc_vblank_off(old_crtc_state);
2999
3000                 intel_disable_transcoder(old_crtc_state);
3001
3002                 intel_ddi_disable_transcoder_func(old_crtc_state);
3003
3004                 intel_dsc_disable(old_crtc_state);
3005
3006                 if (DISPLAY_VER(dev_priv) >= 9)
3007                         skl_scaler_disable(old_crtc_state);
3008                 else
3009                         ilk_pfit_disable(old_crtc_state);
3010         }
3011
3012         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
3013                                          intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {
3014                 const struct intel_crtc_state *old_slave_crtc_state =
3015                         intel_atomic_get_old_crtc_state(state, slave_crtc);
3016
3017                 intel_crtc_vblank_off(old_slave_crtc_state);
3018
3019                 intel_dsc_disable(old_slave_crtc_state);
3020                 skl_scaler_disable(old_slave_crtc_state);
3021         }
3022
3023         /*
3024          * When called from DP MST code:
3025          * - old_conn_state will be NULL
3026          * - encoder will be the main encoder (ie. mst->primary)
3027          * - the main connector associated with this port
3028          *   won't be active or linked to a crtc
3029          * - old_crtc_state will be the state of the last stream to
3030          *   be deactivated on this port, and it may not be the same
3031          *   stream that was activated last, but each stream
3032          *   should have a state that is identical when it comes to
3033          *   the DP link parameteres
3034          */
3035
3036         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3037                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3038                                             old_conn_state);
3039         else
3040                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3041                                           old_conn_state);
3042 }
3043
3044 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
3045                                        struct intel_encoder *encoder,
3046                                        const struct intel_crtc_state *old_crtc_state,
3047                                        const struct drm_connector_state *old_conn_state)
3048 {
3049         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3050         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3051         enum phy phy = intel_port_to_phy(i915, encoder->port);
3052         bool is_tc_port = intel_phy_is_tc(i915, phy);
3053
3054         main_link_aux_power_domain_put(dig_port, old_crtc_state);
3055
3056         if (is_tc_port)
3057                 intel_tc_port_put_link(dig_port);
3058 }
3059
3060 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3061                                             struct intel_encoder *encoder,
3062                                             const struct intel_crtc_state *crtc_state)
3063 {
3064         const struct drm_connector_state *conn_state;
3065         struct drm_connector *conn;
3066         int i;
3067
3068         if (!crtc_state->sync_mode_slaves_mask)
3069                 return;
3070
3071         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3072                 struct intel_encoder *slave_encoder =
3073                         to_intel_encoder(conn_state->best_encoder);
3074                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3075                 const struct intel_crtc_state *slave_crtc_state;
3076
3077                 if (!slave_crtc)
3078                         continue;
3079
3080                 slave_crtc_state =
3081                         intel_atomic_get_new_crtc_state(state, slave_crtc);
3082
3083                 if (slave_crtc_state->master_transcoder !=
3084                     crtc_state->cpu_transcoder)
3085                         continue;
3086
3087                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
3088                                          slave_crtc_state);
3089         }
3090
3091         usleep_range(200, 400);
3092
3093         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
3094                                  crtc_state);
3095 }
3096
3097 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3098                                 struct intel_encoder *encoder,
3099                                 const struct intel_crtc_state *crtc_state,
3100                                 const struct drm_connector_state *conn_state)
3101 {
3102         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3103         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3104         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3105         enum port port = encoder->port;
3106
3107         if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
3108                 intel_dp_stop_link_train(intel_dp, crtc_state);
3109
3110         drm_connector_update_privacy_screen(conn_state);
3111         intel_edp_backlight_on(crtc_state, conn_state);
3112
3113         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
3114                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3115
3116         intel_audio_codec_enable(encoder, crtc_state, conn_state);
3117
3118         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3119 }
3120
3121 static i915_reg_t
3122 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3123                                enum port port)
3124 {
3125         static const enum transcoder trans[] = {
3126                 [PORT_A] = TRANSCODER_EDP,
3127                 [PORT_B] = TRANSCODER_A,
3128                 [PORT_C] = TRANSCODER_B,
3129                 [PORT_D] = TRANSCODER_C,
3130                 [PORT_E] = TRANSCODER_A,
3131         };
3132
3133         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
3134
3135         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3136                 port = PORT_A;
3137
3138         return CHICKEN_TRANS(trans[port]);
3139 }
3140
3141 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3142                                   struct intel_encoder *encoder,
3143                                   const struct intel_crtc_state *crtc_state,
3144                                   const struct drm_connector_state *conn_state)
3145 {
3146         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3147         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3148         struct drm_connector *connector = conn_state->connector;
3149         enum port port = encoder->port;
3150         enum phy phy = intel_port_to_phy(dev_priv, port);
3151         u32 buf_ctl;
3152
3153         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3154                                                crtc_state->hdmi_high_tmds_clock_ratio,
3155                                                crtc_state->hdmi_scrambling))
3156                 drm_dbg_kms(&dev_priv->drm,
3157                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3158                             connector->base.id, connector->name);
3159
3160         if (has_buf_trans_select(dev_priv))
3161                 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
3162
3163         /* e. Enable D2D Link for C10/C20 Phy */
3164         if (DISPLAY_VER(dev_priv) >= 14)
3165                 mtl_ddi_enable_d2d(encoder);
3166
3167         encoder->set_signal_levels(encoder, crtc_state);
3168
3169         /* Display WA #1143: skl,kbl,cfl */
3170         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3171                 /*
3172                  * For some reason these chicken bits have been
3173                  * stuffed into a transcoder register, event though
3174                  * the bits affect a specific DDI port rather than
3175                  * a specific transcoder.
3176                  */
3177                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3178                 u32 val;
3179
3180                 val = intel_de_read(dev_priv, reg);
3181
3182                 if (port == PORT_E)
3183                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3184                                 DDIE_TRAINING_OVERRIDE_VALUE;
3185                 else
3186                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3187                                 DDI_TRAINING_OVERRIDE_VALUE;
3188
3189                 intel_de_write(dev_priv, reg, val);
3190                 intel_de_posting_read(dev_priv, reg);
3191
3192                 udelay(1);
3193
3194                 if (port == PORT_E)
3195                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3196                                  DDIE_TRAINING_OVERRIDE_VALUE);
3197                 else
3198                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3199                                  DDI_TRAINING_OVERRIDE_VALUE);
3200
3201                 intel_de_write(dev_priv, reg, val);
3202         }
3203
3204         intel_ddi_power_up_lanes(encoder, crtc_state);
3205
3206         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3207          * are ignored so nothing special needs to be done besides
3208          * enabling the port.
3209          *
3210          * On ADL_P the PHY link rate and lane count must be programmed but
3211          * these are both 0 for HDMI.
3212          *
3213          * But MTL onwards HDMI2.1 is supported and in TMDS mode this
3214          * is filled with lane count, already set in the crtc_state.
3215          * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
3216          */
3217         buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
3218         if (DISPLAY_VER(dev_priv) >= 14) {
3219                 u8  lane_count = mtl_get_port_width(crtc_state->lane_count);
3220                 u32 port_buf = 0;
3221
3222                 port_buf |= XELPDP_PORT_WIDTH(lane_count);
3223
3224                 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
3225                         port_buf |= XELPDP_PORT_REVERSAL;
3226
3227                 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
3228                              XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
3229
3230                 buf_ctl |= DDI_PORT_WIDTH(lane_count);
3231         } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
3232                 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
3233                 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
3234         }
3235
3236         intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
3237
3238         intel_wait_ddi_buf_active(dev_priv, port);
3239
3240         intel_audio_codec_enable(encoder, crtc_state, conn_state);
3241 }
3242
3243 static void intel_enable_ddi(struct intel_atomic_state *state,
3244                              struct intel_encoder *encoder,
3245                              const struct intel_crtc_state *crtc_state,
3246                              const struct drm_connector_state *conn_state)
3247 {
3248         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3249
3250         if (!intel_crtc_is_bigjoiner_slave(crtc_state))
3251                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3252
3253         /* Enable/Disable DP2.0 SDP split config before transcoder */
3254         intel_audio_sdp_split_update(encoder, crtc_state);
3255
3256         intel_enable_transcoder(crtc_state);
3257
3258         intel_crtc_vblank_on(crtc_state);
3259
3260         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3261                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3262         else
3263                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3264
3265         /* Enable hdcp if it's desired */
3266         if (conn_state->content_protection ==
3267             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3268                 intel_hdcp_enable(state, encoder, crtc_state, conn_state);
3269 }
3270
3271 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3272                                  struct intel_encoder *encoder,
3273                                  const struct intel_crtc_state *old_crtc_state,
3274                                  const struct drm_connector_state *old_conn_state)
3275 {
3276         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3277
3278         intel_dp->link_trained = false;
3279
3280         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
3281
3282         intel_psr_disable(intel_dp, old_crtc_state);
3283         intel_edp_backlight_off(old_conn_state);
3284         /* Disable the decompression in DP Sink */
3285         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3286                                               false);
3287         /* Disable Ignore_MSA bit in DP Sink */
3288         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3289                                                       false);
3290 }
3291
3292 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3293                                    struct intel_encoder *encoder,
3294                                    const struct intel_crtc_state *old_crtc_state,
3295                                    const struct drm_connector_state *old_conn_state)
3296 {
3297         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3298         struct drm_connector *connector = old_conn_state->connector;
3299
3300         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
3301
3302         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3303                                                false, false))
3304                 drm_dbg_kms(&i915->drm,
3305                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3306                             connector->base.id, connector->name);
3307 }
3308
3309 static void intel_disable_ddi(struct intel_atomic_state *state,
3310                               struct intel_encoder *encoder,
3311                               const struct intel_crtc_state *old_crtc_state,
3312                               const struct drm_connector_state *old_conn_state)
3313 {
3314         intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder));
3315
3316         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3317
3318         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3319                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3320                                        old_conn_state);
3321         else
3322                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3323                                      old_conn_state);
3324 }
3325
3326 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3327                                      struct intel_encoder *encoder,
3328                                      const struct intel_crtc_state *crtc_state,
3329                                      const struct drm_connector_state *conn_state)
3330 {
3331         intel_ddi_set_dp_msa(crtc_state, conn_state);
3332
3333         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3334
3335         intel_backlight_update(state, encoder, crtc_state, conn_state);
3336         drm_connector_update_privacy_screen(conn_state);
3337 }
3338
3339 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3340                            struct intel_encoder *encoder,
3341                            const struct intel_crtc_state *crtc_state,
3342                            const struct drm_connector_state *conn_state)
3343 {
3344
3345         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3346             !intel_encoder_is_mst(encoder))
3347                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3348                                          conn_state);
3349
3350         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3351 }
3352
3353 void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
3354                                   struct intel_encoder *encoder,
3355                                   struct intel_crtc *crtc)
3356 {
3357         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3358         struct intel_crtc_state *crtc_state =
3359                 intel_atomic_get_new_crtc_state(state, crtc);
3360         struct intel_crtc *slave_crtc;
3361         enum phy phy = intel_port_to_phy(i915, encoder->port);
3362
3363         /* FIXME: Add MTL pll_mgr */
3364         if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy))
3365                 return;
3366
3367         intel_update_active_dpll(state, crtc, encoder);
3368         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
3369                                          intel_crtc_bigjoiner_slave_pipes(crtc_state))
3370                 intel_update_active_dpll(state, slave_crtc, encoder);
3371 }
3372
3373 static void
3374 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3375                          struct intel_encoder *encoder,
3376                          const struct intel_crtc_state *crtc_state,
3377                          const struct drm_connector_state *conn_state)
3378 {
3379         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3380         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3381         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3382         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3383
3384         if (is_tc_port) {
3385                 struct intel_crtc *master_crtc =
3386                         to_intel_crtc(crtc_state->uapi.crtc);
3387
3388                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3389                 intel_ddi_update_active_dpll(state, encoder, master_crtc);
3390         }
3391
3392         main_link_aux_power_domain_get(dig_port, crtc_state);
3393
3394         if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3395                 /*
3396                  * Program the lane count for static/dynamic connections on
3397                  * Type-C ports.  Skip this step for TBT.
3398                  */
3399                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3400         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3401                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3402                                                 crtc_state->lane_lat_optim_mask);
3403 }
3404
3405 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3406 {
3407         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3408         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
3409         int ln;
3410
3411         for (ln = 0; ln < 2; ln++)
3412                 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
3413 }
3414
3415 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3416                                          const struct intel_crtc_state *crtc_state)
3417 {
3418         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3419         struct intel_encoder *encoder = &dig_port->base;
3420         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3421         enum port port = encoder->port;
3422         u32 dp_tp_ctl;
3423
3424         /*
3425          * TODO: To train with only a different voltage swing entry is not
3426          * necessary disable and enable port
3427          */
3428         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3429         if (dp_tp_ctl & DP_TP_CTL_ENABLE)
3430                 mtl_disable_ddi_buf(encoder, crtc_state);
3431
3432         /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
3433         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3434         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3435                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3436         } else {
3437                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3438                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3439                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3440         }
3441         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3442         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3443
3444         /* 6.f Enable D2D Link */
3445         mtl_ddi_enable_d2d(encoder);
3446
3447         /* 6.g Configure voltage swing and related IO settings */
3448         encoder->set_signal_levels(encoder, crtc_state);
3449
3450         /* 6.h Configure PORT_BUF_CTL1 */
3451         mtl_port_buf_ctl_program(encoder, crtc_state);
3452
3453         /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
3454         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3455         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3456         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3457
3458         /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
3459         intel_wait_ddi_buf_active(dev_priv, port);
3460 }
3461
3462 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3463                                            const struct intel_crtc_state *crtc_state)
3464 {
3465         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3466         struct intel_encoder *encoder = &dig_port->base;
3467         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3468         enum port port = encoder->port;
3469         u32 dp_tp_ctl, ddi_buf_ctl;
3470         bool wait = false;
3471
3472         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3473
3474         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3475                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3476                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3477                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3478                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3479                         wait = true;
3480                 }
3481
3482                 dp_tp_ctl &= ~DP_TP_CTL_ENABLE;
3483                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3484                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3485
3486                 if (wait)
3487                         intel_wait_ddi_buf_idle(dev_priv, port);
3488         }
3489
3490         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3491         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3492                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3493         } else {
3494                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3495                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3496                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3497         }
3498         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3499         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3500
3501         if (IS_ALDERLAKE_P(dev_priv) &&
3502             (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3503                 adlp_tbt_to_dp_alt_switch_wa(encoder);
3504
3505         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3506         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3507         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3508
3509         intel_wait_ddi_buf_active(dev_priv, port);
3510 }
3511
3512 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3513                                      const struct intel_crtc_state *crtc_state,
3514                                      u8 dp_train_pat)
3515 {
3516         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3517         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3518         u32 temp;
3519
3520         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3521
3522         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3523         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3524         case DP_TRAINING_PATTERN_DISABLE:
3525                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3526                 break;
3527         case DP_TRAINING_PATTERN_1:
3528                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3529                 break;
3530         case DP_TRAINING_PATTERN_2:
3531                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3532                 break;
3533         case DP_TRAINING_PATTERN_3:
3534                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3535                 break;
3536         case DP_TRAINING_PATTERN_4:
3537                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3538                 break;
3539         }
3540
3541         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3542 }
3543
3544 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3545                                           const struct intel_crtc_state *crtc_state)
3546 {
3547         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3548         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3549         enum port port = encoder->port;
3550
3551         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
3552                      DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
3553
3554         /*
3555          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3556          * reason we need to set idle transmission mode is to work around a HW
3557          * issue where we enable the pipe while not in idle link-training mode.
3558          * In this case there is requirement to wait for a minimum number of
3559          * idle patterns to be sent.
3560          */
3561         if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3562                 return;
3563
3564         if (intel_de_wait_for_set(dev_priv,
3565                                   dp_tp_status_reg(encoder, crtc_state),
3566                                   DP_TP_STATUS_IDLE_DONE, 1))
3567                 drm_err(&dev_priv->drm,
3568                         "Timed out waiting for DP idle patterns\n");
3569 }
3570
3571 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3572                                        enum transcoder cpu_transcoder)
3573 {
3574         if (cpu_transcoder == TRANSCODER_EDP)
3575                 return false;
3576
3577         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3578                 return false;
3579
3580         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3581                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3582 }
3583
3584 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3585                                          struct intel_crtc_state *crtc_state)
3586 {
3587         if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3588                 crtc_state->min_voltage_level = 2;
3589         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3590                 crtc_state->min_voltage_level = 3;
3591         else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3592                 crtc_state->min_voltage_level = 1;
3593 }
3594
3595 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3596                                                      enum transcoder cpu_transcoder)
3597 {
3598         u32 master_select;
3599
3600         if (DISPLAY_VER(dev_priv) >= 11) {
3601                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3602
3603                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3604                         return INVALID_TRANSCODER;
3605
3606                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3607         } else {
3608                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3609
3610                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3611                         return INVALID_TRANSCODER;
3612
3613                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3614         }
3615
3616         if (master_select == 0)
3617                 return TRANSCODER_EDP;
3618         else
3619                 return master_select - 1;
3620 }
3621
3622 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3623 {
3624         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3625         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3626                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3627         enum transcoder cpu_transcoder;
3628
3629         crtc_state->master_transcoder =
3630                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3631
3632         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3633                 enum intel_display_power_domain power_domain;
3634                 intel_wakeref_t trans_wakeref;
3635
3636                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3637                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3638                                                                    power_domain);
3639
3640                 if (!trans_wakeref)
3641                         continue;
3642
3643                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3644                     crtc_state->cpu_transcoder)
3645                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3646
3647                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3648         }
3649
3650         drm_WARN_ON(&dev_priv->drm,
3651                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3652                     crtc_state->sync_mode_slaves_mask);
3653 }
3654
3655 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3656                                     struct intel_crtc_state *pipe_config)
3657 {
3658         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3659         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3660         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3661         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3662         u32 temp, flags = 0;
3663
3664         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3665         if (temp & TRANS_DDI_PHSYNC)
3666                 flags |= DRM_MODE_FLAG_PHSYNC;
3667         else
3668                 flags |= DRM_MODE_FLAG_NHSYNC;
3669         if (temp & TRANS_DDI_PVSYNC)
3670                 flags |= DRM_MODE_FLAG_PVSYNC;
3671         else
3672                 flags |= DRM_MODE_FLAG_NVSYNC;
3673
3674         pipe_config->hw.adjusted_mode.flags |= flags;
3675
3676         switch (temp & TRANS_DDI_BPC_MASK) {
3677         case TRANS_DDI_BPC_6:
3678                 pipe_config->pipe_bpp = 18;
3679                 break;
3680         case TRANS_DDI_BPC_8:
3681                 pipe_config->pipe_bpp = 24;
3682                 break;
3683         case TRANS_DDI_BPC_10:
3684                 pipe_config->pipe_bpp = 30;
3685                 break;
3686         case TRANS_DDI_BPC_12:
3687                 pipe_config->pipe_bpp = 36;
3688                 break;
3689         default:
3690                 break;
3691         }
3692
3693         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3694         case TRANS_DDI_MODE_SELECT_HDMI:
3695                 pipe_config->has_hdmi_sink = true;
3696
3697                 pipe_config->infoframes.enable |=
3698                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3699
3700                 if (pipe_config->infoframes.enable)
3701                         pipe_config->has_infoframe = true;
3702
3703                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3704                         pipe_config->hdmi_scrambling = true;
3705                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3706                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3707                 fallthrough;
3708         case TRANS_DDI_MODE_SELECT_DVI:
3709                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3710                 if (DISPLAY_VER(dev_priv) >= 14)
3711                         pipe_config->lane_count =
3712                                 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3713                 else
3714                         pipe_config->lane_count = 4;
3715                 break;
3716         case TRANS_DDI_MODE_SELECT_DP_SST:
3717                 if (encoder->type == INTEL_OUTPUT_EDP)
3718                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3719                 else
3720                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3721                 pipe_config->lane_count =
3722                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3723
3724                 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3725                                                &pipe_config->dp_m_n);
3726                 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
3727                                                &pipe_config->dp_m2_n2);
3728
3729                 if (DISPLAY_VER(dev_priv) >= 11) {
3730                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3731
3732                         pipe_config->fec_enable =
3733                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3734
3735                         drm_dbg_kms(&dev_priv->drm,
3736                                     "[ENCODER:%d:%s] Fec status: %u\n",
3737                                     encoder->base.base.id, encoder->base.name,
3738                                     pipe_config->fec_enable);
3739                 }
3740
3741                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3742                         pipe_config->infoframes.enable |=
3743                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3744                 else
3745                         pipe_config->infoframes.enable |=
3746                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3747                 break;
3748         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3749                 if (!HAS_DP20(dev_priv)) {
3750                         /* FDI */
3751                         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3752                         break;
3753                 }
3754                 fallthrough; /* 128b/132b */
3755         case TRANS_DDI_MODE_SELECT_DP_MST:
3756                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3757                 pipe_config->lane_count =
3758                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3759
3760                 if (DISPLAY_VER(dev_priv) >= 12)
3761                         pipe_config->mst_master_transcoder =
3762                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3763
3764                 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3765                                                &pipe_config->dp_m_n);
3766
3767                 pipe_config->infoframes.enable |=
3768                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3769                 break;
3770         default:
3771                 break;
3772         }
3773 }
3774
3775 static void intel_ddi_get_config(struct intel_encoder *encoder,
3776                                  struct intel_crtc_state *pipe_config)
3777 {
3778         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3779         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3780
3781         /* XXX: DSI transcoder paranoia */
3782         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3783                 return;
3784
3785         intel_ddi_read_func_ctl(encoder, pipe_config);
3786
3787         intel_ddi_mso_get_config(encoder, pipe_config);
3788
3789         pipe_config->has_audio =
3790                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3791
3792         if (encoder->type == INTEL_OUTPUT_EDP)
3793                 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
3794
3795         ddi_dotclock_get(pipe_config);
3796
3797         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3798                 pipe_config->lane_lat_optim_mask =
3799                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3800
3801         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3802
3803         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3804
3805         intel_read_infoframe(encoder, pipe_config,
3806                              HDMI_INFOFRAME_TYPE_AVI,
3807                              &pipe_config->infoframes.avi);
3808         intel_read_infoframe(encoder, pipe_config,
3809                              HDMI_INFOFRAME_TYPE_SPD,
3810                              &pipe_config->infoframes.spd);
3811         intel_read_infoframe(encoder, pipe_config,
3812                              HDMI_INFOFRAME_TYPE_VENDOR,
3813                              &pipe_config->infoframes.hdmi);
3814         intel_read_infoframe(encoder, pipe_config,
3815                              HDMI_INFOFRAME_TYPE_DRM,
3816                              &pipe_config->infoframes.drm);
3817
3818         if (DISPLAY_VER(dev_priv) >= 8)
3819                 bdw_get_trans_port_sync_config(pipe_config);
3820
3821         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3822         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3823
3824         intel_psr_get_config(encoder, pipe_config);
3825
3826         intel_audio_codec_get_config(encoder, pipe_config);
3827 }
3828
3829 void intel_ddi_get_clock(struct intel_encoder *encoder,
3830                          struct intel_crtc_state *crtc_state,
3831                          struct intel_shared_dpll *pll)
3832 {
3833         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3834         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3835         struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3836         bool pll_active;
3837
3838         if (drm_WARN_ON(&i915->drm, !pll))
3839                 return;
3840
3841         port_dpll->pll = pll;
3842         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3843         drm_WARN_ON(&i915->drm, !pll_active);
3844
3845         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3846
3847         crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3848                                                      &crtc_state->dpll_hw_state);
3849 }
3850
3851 static void mtl_ddi_get_config(struct intel_encoder *encoder,
3852                                struct intel_crtc_state *crtc_state)
3853 {
3854         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3855         enum phy phy = intel_port_to_phy(i915, encoder->port);
3856         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3857
3858         if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
3859                 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
3860         } else if (intel_is_c10phy(i915, phy)) {
3861                 intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
3862                 intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
3863                 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
3864         } else {
3865                 intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
3866                 intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
3867                 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
3868         }
3869
3870         intel_ddi_get_config(encoder, crtc_state);
3871 }
3872
3873 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3874                                 struct intel_crtc_state *crtc_state)
3875 {
3876         intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3877         crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3878
3879         intel_ddi_get_config(encoder, crtc_state);
3880 }
3881
3882 static void adls_ddi_get_config(struct intel_encoder *encoder,
3883                                 struct intel_crtc_state *crtc_state)
3884 {
3885         intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3886         intel_ddi_get_config(encoder, crtc_state);
3887 }
3888
3889 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3890                                struct intel_crtc_state *crtc_state)
3891 {
3892         intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3893         intel_ddi_get_config(encoder, crtc_state);
3894 }
3895
3896 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3897                                struct intel_crtc_state *crtc_state)
3898 {
3899         intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3900         intel_ddi_get_config(encoder, crtc_state);
3901 }
3902
3903 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3904                                      struct intel_crtc_state *crtc_state)
3905 {
3906         intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3907         intel_ddi_get_config(encoder, crtc_state);
3908 }
3909
3910 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
3911 {
3912         return pll->info->id == DPLL_ID_ICL_TBTPLL;
3913 }
3914
3915 static enum icl_port_dpll_id
3916 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
3917                          const struct intel_crtc_state *crtc_state)
3918 {
3919         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3920         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3921
3922         if (drm_WARN_ON(&i915->drm, !pll))
3923                 return ICL_PORT_DPLL_DEFAULT;
3924
3925         if (icl_ddi_tc_pll_is_tbt(pll))
3926                 return ICL_PORT_DPLL_DEFAULT;
3927         else
3928                 return ICL_PORT_DPLL_MG_PHY;
3929 }
3930
3931 enum icl_port_dpll_id
3932 intel_ddi_port_pll_type(struct intel_encoder *encoder,
3933                         const struct intel_crtc_state *crtc_state)
3934 {
3935         if (!encoder->port_pll_type)
3936                 return ICL_PORT_DPLL_DEFAULT;
3937
3938         return encoder->port_pll_type(encoder, crtc_state);
3939 }
3940
3941 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3942                                  struct intel_crtc_state *crtc_state,
3943                                  struct intel_shared_dpll *pll)
3944 {
3945         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3946         enum icl_port_dpll_id port_dpll_id;
3947         struct icl_port_dpll *port_dpll;
3948         bool pll_active;
3949
3950         if (drm_WARN_ON(&i915->drm, !pll))
3951                 return;
3952
3953         if (icl_ddi_tc_pll_is_tbt(pll))
3954                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3955         else
3956                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3957
3958         port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3959
3960         port_dpll->pll = pll;
3961         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3962         drm_WARN_ON(&i915->drm, !pll_active);
3963
3964         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3965
3966         if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
3967                 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3968         else
3969                 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3970                                                              &crtc_state->dpll_hw_state);
3971 }
3972
3973 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3974                                   struct intel_crtc_state *crtc_state)
3975 {
3976         icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3977         intel_ddi_get_config(encoder, crtc_state);
3978 }
3979
3980 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3981                                struct intel_crtc_state *crtc_state)
3982 {
3983         intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3984         intel_ddi_get_config(encoder, crtc_state);
3985 }
3986
3987 static void skl_ddi_get_config(struct intel_encoder *encoder,
3988                                struct intel_crtc_state *crtc_state)
3989 {
3990         intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3991         intel_ddi_get_config(encoder, crtc_state);
3992 }
3993
3994 void hsw_ddi_get_config(struct intel_encoder *encoder,
3995                         struct intel_crtc_state *crtc_state)
3996 {
3997         intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3998         intel_ddi_get_config(encoder, crtc_state);
3999 }
4000
4001 static void intel_ddi_sync_state(struct intel_encoder *encoder,
4002                                  const struct intel_crtc_state *crtc_state)
4003 {
4004         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4005         enum phy phy = intel_port_to_phy(i915, encoder->port);
4006
4007         if (intel_phy_is_tc(i915, phy))
4008                 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
4009                                             crtc_state);
4010
4011         if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
4012                 intel_dp_sync_state(encoder, crtc_state);
4013 }
4014
4015 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4016                                             struct intel_crtc_state *crtc_state)
4017 {
4018         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4019         enum phy phy = intel_port_to_phy(i915, encoder->port);
4020         bool fastset = true;
4021
4022         if (intel_phy_is_tc(i915, phy)) {
4023                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
4024                             encoder->base.base.id, encoder->base.name);
4025                 crtc_state->uapi.mode_changed = true;
4026                 fastset = false;
4027         }
4028
4029         if (intel_crtc_has_dp_encoder(crtc_state) &&
4030             !intel_dp_initial_fastset_check(encoder, crtc_state))
4031                 fastset = false;
4032
4033         return fastset;
4034 }
4035
4036 static enum intel_output_type
4037 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4038                               struct intel_crtc_state *crtc_state,
4039                               struct drm_connector_state *conn_state)
4040 {
4041         switch (conn_state->connector->connector_type) {
4042         case DRM_MODE_CONNECTOR_HDMIA:
4043                 return INTEL_OUTPUT_HDMI;
4044         case DRM_MODE_CONNECTOR_eDP:
4045                 return INTEL_OUTPUT_EDP;
4046         case DRM_MODE_CONNECTOR_DisplayPort:
4047                 return INTEL_OUTPUT_DP;
4048         default:
4049                 MISSING_CASE(conn_state->connector->connector_type);
4050                 return INTEL_OUTPUT_UNUSED;
4051         }
4052 }
4053
4054 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4055                                     struct intel_crtc_state *pipe_config,
4056                                     struct drm_connector_state *conn_state)
4057 {
4058         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4059         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4060         enum port port = encoder->port;
4061         int ret;
4062
4063         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4064                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4065
4066         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4067                 pipe_config->has_hdmi_sink =
4068                         intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state);
4069
4070                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4071         } else {
4072                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4073         }
4074
4075         if (ret)
4076                 return ret;
4077
4078         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4079             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4080                 pipe_config->pch_pfit.force_thru =
4081                         pipe_config->pch_pfit.enabled ||
4082                         pipe_config->crc_enabled;
4083
4084         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4085                 pipe_config->lane_lat_optim_mask =
4086                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4087
4088         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4089
4090         return 0;
4091 }
4092
4093 static bool mode_equal(const struct drm_display_mode *mode1,
4094                        const struct drm_display_mode *mode2)
4095 {
4096         return drm_mode_match(mode1, mode2,
4097                               DRM_MODE_MATCH_TIMINGS |
4098                               DRM_MODE_MATCH_FLAGS |
4099                               DRM_MODE_MATCH_3D_FLAGS) &&
4100                 mode1->clock == mode2->clock; /* we want an exact match */
4101 }
4102
4103 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4104                       const struct intel_link_m_n *m_n_2)
4105 {
4106         return m_n_1->tu == m_n_2->tu &&
4107                 m_n_1->data_m == m_n_2->data_m &&
4108                 m_n_1->data_n == m_n_2->data_n &&
4109                 m_n_1->link_m == m_n_2->link_m &&
4110                 m_n_1->link_n == m_n_2->link_n;
4111 }
4112
4113 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4114                                        const struct intel_crtc_state *crtc_state2)
4115 {
4116         return crtc_state1->hw.active && crtc_state2->hw.active &&
4117                 crtc_state1->output_types == crtc_state2->output_types &&
4118                 crtc_state1->output_format == crtc_state2->output_format &&
4119                 crtc_state1->lane_count == crtc_state2->lane_count &&
4120                 crtc_state1->port_clock == crtc_state2->port_clock &&
4121                 mode_equal(&crtc_state1->hw.adjusted_mode,
4122                            &crtc_state2->hw.adjusted_mode) &&
4123                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4124 }
4125
4126 static u8
4127 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4128                                 int tile_group_id)
4129 {
4130         struct drm_connector *connector;
4131         const struct drm_connector_state *conn_state;
4132         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4133         struct intel_atomic_state *state =
4134                 to_intel_atomic_state(ref_crtc_state->uapi.state);
4135         u8 transcoders = 0;
4136         int i;
4137
4138         /*
4139          * We don't enable port sync on BDW due to missing w/as and
4140          * due to not having adjusted the modeset sequence appropriately.
4141          */
4142         if (DISPLAY_VER(dev_priv) < 9)
4143                 return 0;
4144
4145         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4146                 return 0;
4147
4148         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4149                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4150                 const struct intel_crtc_state *crtc_state;
4151
4152                 if (!crtc)
4153                         continue;
4154
4155                 if (!connector->has_tile ||
4156                     connector->tile_group->id !=
4157                     tile_group_id)
4158                         continue;
4159                 crtc_state = intel_atomic_get_new_crtc_state(state,
4160                                                              crtc);
4161                 if (!crtcs_port_sync_compatible(ref_crtc_state,
4162                                                 crtc_state))
4163                         continue;
4164                 transcoders |= BIT(crtc_state->cpu_transcoder);
4165         }
4166
4167         return transcoders;
4168 }
4169
4170 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4171                                          struct intel_crtc_state *crtc_state,
4172                                          struct drm_connector_state *conn_state)
4173 {
4174         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4175         struct drm_connector *connector = conn_state->connector;
4176         u8 port_sync_transcoders = 0;
4177
4178         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4179                     encoder->base.base.id, encoder->base.name,
4180                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4181
4182         if (connector->has_tile)
4183                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4184                                                                         connector->tile_group->id);
4185
4186         /*
4187          * EDP Transcoders cannot be ensalved
4188          * make them a master always when present
4189          */
4190         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4191                 crtc_state->master_transcoder = TRANSCODER_EDP;
4192         else
4193                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4194
4195         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4196                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4197                 crtc_state->sync_mode_slaves_mask =
4198                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4199         }
4200
4201         return 0;
4202 }
4203
4204 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4205 {
4206         struct drm_i915_private *i915 = to_i915(encoder->dev);
4207         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4208         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
4209
4210         intel_dp_encoder_flush_work(encoder);
4211         if (intel_phy_is_tc(i915, phy))
4212                 intel_tc_port_cleanup(dig_port);
4213         intel_display_power_flush_work(i915);
4214
4215         drm_encoder_cleanup(encoder);
4216         kfree(dig_port->hdcp_port_data.streams);
4217         kfree(dig_port);
4218 }
4219
4220 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4221 {
4222         struct drm_i915_private *i915 = to_i915(encoder->dev);
4223         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4224         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4225         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
4226
4227         intel_dp->reset_link_params = true;
4228
4229         intel_pps_encoder_reset(intel_dp);
4230
4231         if (intel_phy_is_tc(i915, phy))
4232                 intel_tc_port_init_mode(dig_port);
4233 }
4234
4235 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
4236 {
4237         struct intel_encoder *encoder = to_intel_encoder(_encoder);
4238
4239         intel_tc_port_link_reset(enc_to_dig_port(encoder));
4240
4241         return 0;
4242 }
4243
4244 static const struct drm_encoder_funcs intel_ddi_funcs = {
4245         .reset = intel_ddi_encoder_reset,
4246         .destroy = intel_ddi_encoder_destroy,
4247         .late_register = intel_ddi_encoder_late_register,
4248 };
4249
4250 static struct intel_connector *
4251 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4252 {
4253         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4254         struct intel_connector *connector;
4255         enum port port = dig_port->base.port;
4256
4257         connector = intel_connector_alloc();
4258         if (!connector)
4259                 return NULL;
4260
4261         dig_port->dp.output_reg = DDI_BUF_CTL(port);
4262         if (DISPLAY_VER(i915) >= 14)
4263                 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;
4264         else
4265                 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4266         dig_port->dp.set_link_train = intel_ddi_set_link_train;
4267         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4268
4269         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4270         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4271
4272         if (!intel_dp_init_connector(dig_port, connector)) {
4273                 kfree(connector);
4274                 return NULL;
4275         }
4276
4277         if (dig_port->base.type == INTEL_OUTPUT_EDP) {
4278                 struct drm_device *dev = dig_port->base.base.dev;
4279                 struct drm_privacy_screen *privacy_screen;
4280
4281                 privacy_screen = drm_privacy_screen_get(dev->dev, NULL);
4282                 if (!IS_ERR(privacy_screen)) {
4283                         drm_connector_attach_privacy_screen_provider(&connector->base,
4284                                                                      privacy_screen);
4285                 } else if (PTR_ERR(privacy_screen) != -ENODEV) {
4286                         drm_warn(dev, "Error getting privacy-screen\n");
4287                 }
4288         }
4289
4290         return connector;
4291 }
4292
4293 static int modeset_pipe(struct drm_crtc *crtc,
4294                         struct drm_modeset_acquire_ctx *ctx)
4295 {
4296         struct drm_atomic_state *state;
4297         struct drm_crtc_state *crtc_state;
4298         int ret;
4299
4300         state = drm_atomic_state_alloc(crtc->dev);
4301         if (!state)
4302                 return -ENOMEM;
4303
4304         state->acquire_ctx = ctx;
4305         to_intel_atomic_state(state)->internal = true;
4306
4307         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4308         if (IS_ERR(crtc_state)) {
4309                 ret = PTR_ERR(crtc_state);
4310                 goto out;
4311         }
4312
4313         crtc_state->connectors_changed = true;
4314
4315         ret = drm_atomic_commit(state);
4316 out:
4317         drm_atomic_state_put(state);
4318
4319         return ret;
4320 }
4321
4322 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4323                                  struct drm_modeset_acquire_ctx *ctx)
4324 {
4325         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4326         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4327         struct intel_connector *connector = hdmi->attached_connector;
4328         struct i2c_adapter *adapter =
4329                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4330         struct drm_connector_state *conn_state;
4331         struct intel_crtc_state *crtc_state;
4332         struct intel_crtc *crtc;
4333         u8 config;
4334         int ret;
4335
4336         if (!connector || connector->base.status != connector_status_connected)
4337                 return 0;
4338
4339         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4340                                ctx);
4341         if (ret)
4342                 return ret;
4343
4344         conn_state = connector->base.state;
4345
4346         crtc = to_intel_crtc(conn_state->crtc);
4347         if (!crtc)
4348                 return 0;
4349
4350         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4351         if (ret)
4352                 return ret;
4353
4354         crtc_state = to_intel_crtc_state(crtc->base.state);
4355
4356         drm_WARN_ON(&dev_priv->drm,
4357                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4358
4359         if (!crtc_state->hw.active)
4360                 return 0;
4361
4362         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4363             !crtc_state->hdmi_scrambling)
4364                 return 0;
4365
4366         if (conn_state->commit &&
4367             !try_wait_for_completion(&conn_state->commit->hw_done))
4368                 return 0;
4369
4370         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4371         if (ret < 0) {
4372                 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
4373                         connector->base.base.id, connector->base.name, ret);
4374                 return 0;
4375         }
4376
4377         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4378             crtc_state->hdmi_high_tmds_clock_ratio &&
4379             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4380             crtc_state->hdmi_scrambling)
4381                 return 0;
4382
4383         /*
4384          * HDMI 2.0 says that one should not send scrambled data
4385          * prior to configuring the sink scrambling, and that
4386          * TMDS clock/data transmission should be suspended when
4387          * changing the TMDS clock rate in the sink. So let's
4388          * just do a full modeset here, even though some sinks
4389          * would be perfectly happy if were to just reconfigure
4390          * the SCDC settings on the fly.
4391          */
4392         return modeset_pipe(&crtc->base, ctx);
4393 }
4394
4395 static enum intel_hotplug_state
4396 intel_ddi_hotplug(struct intel_encoder *encoder,
4397                   struct intel_connector *connector)
4398 {
4399         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4400         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4401         struct intel_dp *intel_dp = &dig_port->dp;
4402         enum phy phy = intel_port_to_phy(i915, encoder->port);
4403         bool is_tc = intel_phy_is_tc(i915, phy);
4404         struct drm_modeset_acquire_ctx ctx;
4405         enum intel_hotplug_state state;
4406         int ret;
4407
4408         if (intel_dp->compliance.test_active &&
4409             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4410                 intel_dp_phy_test(encoder);
4411                 /* just do the PHY test and nothing else */
4412                 return INTEL_HOTPLUG_UNCHANGED;
4413         }
4414
4415         state = intel_encoder_hotplug(encoder, connector);
4416
4417         if (!intel_tc_port_link_reset(dig_port)) {
4418                 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) {
4419                         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4420                                 ret = intel_hdmi_reset_link(encoder, &ctx);
4421                         else
4422                                 ret = intel_dp_retrain_link(encoder, &ctx);
4423                 }
4424
4425                 drm_WARN_ON(encoder->base.dev, ret);
4426         }
4427
4428         /*
4429          * Unpowered type-c dongles can take some time to boot and be
4430          * responsible, so here giving some time to those dongles to power up
4431          * and then retrying the probe.
4432          *
4433          * On many platforms the HDMI live state signal is known to be
4434          * unreliable, so we can't use it to detect if a sink is connected or
4435          * not. Instead we detect if it's connected based on whether we can
4436          * read the EDID or not. That in turn has a problem during disconnect,
4437          * since the HPD interrupt may be raised before the DDC lines get
4438          * disconnected (due to how the required length of DDC vs. HPD
4439          * connector pins are specified) and so we'll still be able to get a
4440          * valid EDID. To solve this schedule another detection cycle if this
4441          * time around we didn't detect any change in the sink's connection
4442          * status.
4443          *
4444          * Type-c connectors which get their HPD signal deasserted then
4445          * reasserted, without unplugging/replugging the sink from the
4446          * connector, introduce a delay until the AUX channel communication
4447          * becomes functional. Retry the detection for 5 seconds on type-c
4448          * connectors to account for this delay.
4449          */
4450         if (state == INTEL_HOTPLUG_UNCHANGED &&
4451             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4452             !dig_port->dp.is_mst)
4453                 state = INTEL_HOTPLUG_RETRY;
4454
4455         return state;
4456 }
4457
4458 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4459 {
4460         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4461         u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
4462
4463         return intel_de_read(dev_priv, SDEISR) & bit;
4464 }
4465
4466 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4467 {
4468         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4469         u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4470
4471         return intel_de_read(dev_priv, DEISR) & bit;
4472 }
4473
4474 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4475 {
4476         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4477         u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4478
4479         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4480 }
4481
4482 static struct intel_connector *
4483 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4484 {
4485         struct intel_connector *connector;
4486         enum port port = dig_port->base.port;
4487
4488         connector = intel_connector_alloc();
4489         if (!connector)
4490                 return NULL;
4491
4492         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4493         intel_hdmi_init_connector(dig_port, connector);
4494
4495         return connector;
4496 }
4497
4498 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4499 {
4500         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4501
4502         if (dig_port->base.port != PORT_A)
4503                 return false;
4504
4505         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4506                 return false;
4507
4508         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4509          *                     supported configuration
4510          */
4511         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4512                 return true;
4513
4514         return false;
4515 }
4516
4517 static int
4518 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4519 {
4520         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4521         enum port port = dig_port->base.port;
4522         int max_lanes = 4;
4523
4524         if (DISPLAY_VER(dev_priv) >= 11)
4525                 return max_lanes;
4526
4527         if (port == PORT_A || port == PORT_E) {
4528                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4529                         max_lanes = port == PORT_A ? 4 : 0;
4530                 else
4531                         /* Both A and E share 2 lanes */
4532                         max_lanes = 2;
4533         }
4534
4535         /*
4536          * Some BIOS might fail to set this bit on port A if eDP
4537          * wasn't lit up at boot.  Force this bit set when needed
4538          * so we use the proper lane count for our calculations.
4539          */
4540         if (intel_ddi_a_force_4_lanes(dig_port)) {
4541                 drm_dbg_kms(&dev_priv->drm,
4542                             "Forcing DDI_A_4_LANES for port A\n");
4543                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4544                 max_lanes = 4;
4545         }
4546
4547         return max_lanes;
4548 }
4549
4550 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4551                                   enum port port)
4552 {
4553         if (port >= PORT_D_XELPD)
4554                 return HPD_PORT_D + port - PORT_D_XELPD;
4555         else if (port >= PORT_TC1)
4556                 return HPD_PORT_TC1 + port - PORT_TC1;
4557         else
4558                 return HPD_PORT_A + port - PORT_A;
4559 }
4560
4561 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4562                                 enum port port)
4563 {
4564         if (port >= PORT_TC1)
4565                 return HPD_PORT_C + port - PORT_TC1;
4566         else
4567                 return HPD_PORT_A + port - PORT_A;
4568 }
4569
4570 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4571                                 enum port port)
4572 {
4573         if (port >= PORT_TC1)
4574                 return HPD_PORT_TC1 + port - PORT_TC1;
4575         else
4576                 return HPD_PORT_A + port - PORT_A;
4577 }
4578
4579 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4580                                 enum port port)
4581 {
4582         if (HAS_PCH_TGP(dev_priv))
4583                 return tgl_hpd_pin(dev_priv, port);
4584
4585         if (port >= PORT_TC1)
4586                 return HPD_PORT_C + port - PORT_TC1;
4587         else
4588                 return HPD_PORT_A + port - PORT_A;
4589 }
4590
4591 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4592                                 enum port port)
4593 {
4594         if (port >= PORT_C)
4595                 return HPD_PORT_TC1 + port - PORT_C;
4596         else
4597                 return HPD_PORT_A + port - PORT_A;
4598 }
4599
4600 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4601                                 enum port port)
4602 {
4603         if (port == PORT_D)
4604                 return HPD_PORT_A;
4605
4606         if (HAS_PCH_TGP(dev_priv))
4607                 return icl_hpd_pin(dev_priv, port);
4608
4609         return HPD_PORT_A + port - PORT_A;
4610 }
4611
4612 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4613 {
4614         if (HAS_PCH_TGP(dev_priv))
4615                 return icl_hpd_pin(dev_priv, port);
4616
4617         return HPD_PORT_A + port - PORT_A;
4618 }
4619
4620 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4621 {
4622         if (DISPLAY_VER(i915) >= 12)
4623                 return port >= PORT_TC1;
4624         else if (DISPLAY_VER(i915) >= 11)
4625                 return port >= PORT_C;
4626         else
4627                 return false;
4628 }
4629
4630 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4631 {
4632         intel_dp_encoder_suspend(encoder);
4633 }
4634
4635 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder)
4636 {
4637         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4638         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4639
4640         intel_tc_port_suspend(dig_port);
4641 }
4642
4643 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4644 {
4645         intel_dp_encoder_shutdown(encoder);
4646         intel_hdmi_encoder_shutdown(encoder);
4647 }
4648
4649 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
4650 {
4651         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4652         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4653
4654         intel_tc_port_cleanup(dig_port);
4655 }
4656
4657 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4658 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4659
4660 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4661 {
4662         struct intel_digital_port *dig_port;
4663         struct intel_encoder *encoder;
4664         const struct intel_bios_encoder_data *devdata;
4665         bool init_hdmi, init_dp;
4666         enum phy phy = intel_port_to_phy(dev_priv, port);
4667
4668         /*
4669          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4670          * have taken over some of the PHYs and made them unavailable to the
4671          * driver.  In that case we should skip initializing the corresponding
4672          * outputs.
4673          */
4674         if (intel_hti_uses_phy(dev_priv, phy)) {
4675                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4676                             port_name(port), phy_name(phy));
4677                 return;
4678         }
4679
4680         devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4681         if (!devdata) {
4682                 drm_dbg_kms(&dev_priv->drm,
4683                             "VBT says port %c is not present\n",
4684                             port_name(port));
4685                 return;
4686         }
4687
4688         init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4689                 intel_bios_encoder_supports_hdmi(devdata);
4690         init_dp = intel_bios_encoder_supports_dp(devdata);
4691
4692         if (intel_bios_encoder_is_lspcon(devdata)) {
4693                 /*
4694                  * Lspcon device needs to be driven with DP connector
4695                  * with special detection sequence. So make sure DP
4696                  * is initialized before lspcon.
4697                  */
4698                 init_dp = true;
4699                 init_hdmi = false;
4700                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4701                             port_name(port));
4702         }
4703
4704         if (!init_dp && !init_hdmi) {
4705                 drm_dbg_kms(&dev_priv->drm,
4706                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4707                             port_name(port));
4708                 return;
4709         }
4710
4711         if (intel_phy_is_snps(dev_priv, phy) &&
4712             dev_priv->display.snps.phy_failed_calibration & BIT(phy)) {
4713                 drm_dbg_kms(&dev_priv->drm,
4714                             "SNPS PHY %c failed to calibrate, proceeding anyway\n",
4715                             phy_name(phy));
4716         }
4717
4718         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4719         if (!dig_port)
4720                 return;
4721
4722         encoder = &dig_port->base;
4723         encoder->devdata = devdata;
4724
4725         if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4726                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4727                                  DRM_MODE_ENCODER_TMDS,
4728                                  "DDI %c/PHY %c",
4729                                  port_name(port - PORT_D_XELPD + PORT_D),
4730                                  phy_name(phy));
4731         } else if (DISPLAY_VER(dev_priv) >= 12) {
4732                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4733
4734                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4735                                  DRM_MODE_ENCODER_TMDS,
4736                                  "DDI %s%c/PHY %s%c",
4737                                  port >= PORT_TC1 ? "TC" : "",
4738                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4739                                  tc_port != TC_PORT_NONE ? "TC" : "",
4740                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4741         } else if (DISPLAY_VER(dev_priv) >= 11) {
4742                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4743
4744                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4745                                  DRM_MODE_ENCODER_TMDS,
4746                                  "DDI %c%s/PHY %s%c",
4747                                  port_name(port),
4748                                  port >= PORT_C ? " (TC)" : "",
4749                                  tc_port != TC_PORT_NONE ? "TC" : "",
4750                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4751         } else {
4752                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4753                                  DRM_MODE_ENCODER_TMDS,
4754                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4755         }
4756
4757         mutex_init(&dig_port->hdcp_mutex);
4758         dig_port->num_hdcp_streams = 0;
4759
4760         encoder->hotplug = intel_ddi_hotplug;
4761         encoder->compute_output_type = intel_ddi_compute_output_type;
4762         encoder->compute_config = intel_ddi_compute_config;
4763         encoder->compute_config_late = intel_ddi_compute_config_late;
4764         encoder->enable = intel_enable_ddi;
4765         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4766         encoder->pre_enable = intel_ddi_pre_enable;
4767         encoder->disable = intel_disable_ddi;
4768         encoder->post_pll_disable = intel_ddi_post_pll_disable;
4769         encoder->post_disable = intel_ddi_post_disable;
4770         encoder->update_pipe = intel_ddi_update_pipe;
4771         encoder->get_hw_state = intel_ddi_get_hw_state;
4772         encoder->sync_state = intel_ddi_sync_state;
4773         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4774         encoder->suspend = intel_ddi_encoder_suspend;
4775         encoder->shutdown = intel_ddi_encoder_shutdown;
4776         encoder->get_power_domains = intel_ddi_get_power_domains;
4777
4778         encoder->type = INTEL_OUTPUT_DDI;
4779         encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
4780         encoder->port = port;
4781         encoder->cloneable = 0;
4782         encoder->pipe_mask = ~0;
4783
4784         if (DISPLAY_VER(dev_priv) >= 14) {
4785                 encoder->enable_clock = intel_mtl_pll_enable;
4786                 encoder->disable_clock = intel_mtl_pll_disable;
4787                 encoder->port_pll_type = intel_mtl_port_pll_type;
4788                 encoder->get_config = mtl_ddi_get_config;
4789         } else if (IS_DG2(dev_priv)) {
4790                 encoder->enable_clock = intel_mpllb_enable;
4791                 encoder->disable_clock = intel_mpllb_disable;
4792                 encoder->get_config = dg2_ddi_get_config;
4793         } else if (IS_ALDERLAKE_S(dev_priv)) {
4794                 encoder->enable_clock = adls_ddi_enable_clock;
4795                 encoder->disable_clock = adls_ddi_disable_clock;
4796                 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4797                 encoder->get_config = adls_ddi_get_config;
4798         } else if (IS_ROCKETLAKE(dev_priv)) {
4799                 encoder->enable_clock = rkl_ddi_enable_clock;
4800                 encoder->disable_clock = rkl_ddi_disable_clock;
4801                 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4802                 encoder->get_config = rkl_ddi_get_config;
4803         } else if (IS_DG1(dev_priv)) {
4804                 encoder->enable_clock = dg1_ddi_enable_clock;
4805                 encoder->disable_clock = dg1_ddi_disable_clock;
4806                 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4807                 encoder->get_config = dg1_ddi_get_config;
4808         } else if (IS_JSL_EHL(dev_priv)) {
4809                 if (intel_ddi_is_tc(dev_priv, port)) {
4810                         encoder->enable_clock = jsl_ddi_tc_enable_clock;
4811                         encoder->disable_clock = jsl_ddi_tc_disable_clock;
4812                         encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4813                         encoder->port_pll_type = icl_ddi_tc_port_pll_type;
4814                         encoder->get_config = icl_ddi_combo_get_config;
4815                 } else {
4816                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4817                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4818                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4819                         encoder->get_config = icl_ddi_combo_get_config;
4820                 }
4821         } else if (DISPLAY_VER(dev_priv) >= 11) {
4822                 if (intel_ddi_is_tc(dev_priv, port)) {
4823                         encoder->enable_clock = icl_ddi_tc_enable_clock;
4824                         encoder->disable_clock = icl_ddi_tc_disable_clock;
4825                         encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4826                         encoder->port_pll_type = icl_ddi_tc_port_pll_type;
4827                         encoder->get_config = icl_ddi_tc_get_config;
4828                 } else {
4829                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4830                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4831                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4832                         encoder->get_config = icl_ddi_combo_get_config;
4833                 }
4834         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4835                 /* BXT/GLK have fixed PLL->port mapping */
4836                 encoder->get_config = bxt_ddi_get_config;
4837         } else if (DISPLAY_VER(dev_priv) == 9) {
4838                 encoder->enable_clock = skl_ddi_enable_clock;
4839                 encoder->disable_clock = skl_ddi_disable_clock;
4840                 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4841                 encoder->get_config = skl_ddi_get_config;
4842         } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4843                 encoder->enable_clock = hsw_ddi_enable_clock;
4844                 encoder->disable_clock = hsw_ddi_disable_clock;
4845                 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4846                 encoder->get_config = hsw_ddi_get_config;
4847         }
4848
4849         if (DISPLAY_VER(dev_priv) >= 14) {
4850                 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
4851         } else if (IS_DG2(dev_priv)) {
4852                 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
4853         } else if (DISPLAY_VER(dev_priv) >= 12) {
4854                 if (intel_phy_is_combo(dev_priv, phy))
4855                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4856                 else
4857                         encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
4858         } else if (DISPLAY_VER(dev_priv) >= 11) {
4859                 if (intel_phy_is_combo(dev_priv, phy))
4860                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4861                 else
4862                         encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
4863         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4864                 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
4865         } else {
4866                 encoder->set_signal_levels = hsw_set_signal_levels;
4867         }
4868
4869         intel_ddi_buf_trans_init(encoder);
4870
4871         if (DISPLAY_VER(dev_priv) >= 13)
4872                 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4873         else if (IS_DG1(dev_priv))
4874                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4875         else if (IS_ROCKETLAKE(dev_priv))
4876                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4877         else if (DISPLAY_VER(dev_priv) >= 12)
4878                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4879         else if (IS_JSL_EHL(dev_priv))
4880                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4881         else if (DISPLAY_VER(dev_priv) == 11)
4882                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4883         else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4884                 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4885         else
4886                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4887
4888         if (DISPLAY_VER(dev_priv) >= 11)
4889                 dig_port->saved_port_bits =
4890                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4891                         & DDI_BUF_PORT_REVERSAL;
4892         else
4893                 dig_port->saved_port_bits =
4894                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4895                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4896
4897         if (intel_bios_encoder_lane_reversal(devdata))
4898                 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4899
4900         dig_port->dp.output_reg = INVALID_MMIO_REG;
4901         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4902         dig_port->aux_ch = intel_dp_aux_ch(encoder);
4903
4904         if (intel_phy_is_tc(dev_priv, phy)) {
4905                 bool is_legacy =
4906                         !intel_bios_encoder_supports_typec_usb(devdata) &&
4907                         !intel_bios_encoder_supports_tbt(devdata);
4908
4909                 if (!is_legacy && init_hdmi) {
4910                         is_legacy = !init_dp;
4911
4912                         drm_dbg_kms(&dev_priv->drm,
4913                                     "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
4914                                     port_name(port),
4915                                     str_yes_no(init_dp),
4916                                     is_legacy ? "legacy" : "non-legacy");
4917                 }
4918
4919                 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
4920                 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
4921
4922                 if (intel_tc_port_init(dig_port, is_legacy) < 0)
4923                         goto err;
4924         }
4925
4926         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4927         dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
4928
4929         if (DISPLAY_VER(dev_priv) >= 11) {
4930                 if (intel_phy_is_tc(dev_priv, phy))
4931                         dig_port->connected = intel_tc_port_connected;
4932                 else
4933                         dig_port->connected = lpt_digital_port_connected;
4934         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4935                 dig_port->connected = bdw_digital_port_connected;
4936         } else if (DISPLAY_VER(dev_priv) == 9) {
4937                 dig_port->connected = lpt_digital_port_connected;
4938         } else if (IS_BROADWELL(dev_priv)) {
4939                 if (port == PORT_A)
4940                         dig_port->connected = bdw_digital_port_connected;
4941                 else
4942                         dig_port->connected = lpt_digital_port_connected;
4943         } else if (IS_HASWELL(dev_priv)) {
4944                 if (port == PORT_A)
4945                         dig_port->connected = hsw_digital_port_connected;
4946                 else
4947                         dig_port->connected = lpt_digital_port_connected;
4948         }
4949
4950         intel_infoframe_init(dig_port);
4951
4952         if (init_dp) {
4953                 if (!intel_ddi_init_dp_connector(dig_port))
4954                         goto err;
4955
4956                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4957
4958                 if (dig_port->dp.mso_link_count)
4959                         encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4960         }
4961
4962         /*
4963          * In theory we don't need the encoder->type check,
4964          * but leave it just in case we have some really bad VBTs...
4965          */
4966         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4967                 if (!intel_ddi_init_hdmi_connector(dig_port))
4968                         goto err;
4969         }
4970
4971         return;
4972
4973 err:
4974         drm_encoder_cleanup(&encoder->base);
4975         kfree(dig_port);
4976 }