drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_mst.h"
  38 #include "intel_dp_link_training.h"
  39 #include "intel_dpio_phy.h"
  40 #include "intel_dsi.h"
  41 #include "intel_fifo_underrun.h"
  42 #include "intel_gmbus.h"
  43 #include "intel_hdcp.h"
  44 #include "intel_hdmi.h"
  45 #include "intel_hotplug.h"
  46 #include "intel_lspcon.h"
  47 #include "intel_panel.h"
  48 #include "intel_psr.h"
  49 #include "intel_sprite.h"
  50 #include "intel_tc.h"
  51 #include "intel_vdsc.h"
  52
  53 struct ddi_buf_trans {
  54         u32 trans1;     /* balance leg enable, de-emph level */
  55         u32 trans2;     /* vref sel, vswing */
  56         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  57 };
  58
  59 static const u8 index_to_dp_signal_levels[] = {
  60         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  61         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  62         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  63         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  64         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  69         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  70 };
  71
  72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  73  * them for both DP and FDI transports, allowing those ports to
  74  * automatically adapt to HDMI connections as well
  75  */
  76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  77         { 0x00FFFFFF, 0x0006000E, 0x0 },
  78         { 0x00D75FFF, 0x0005000A, 0x0 },
  79         { 0x00C30FFF, 0x00040006, 0x0 },
  80         { 0x80AAAFFF, 0x000B0000, 0x0 },
  81         { 0x00FFFFFF, 0x0005000A, 0x0 },
  82         { 0x00D75FFF, 0x000C0004, 0x0 },
  83         { 0x80C30FFF, 0x000B0000, 0x0 },
  84         { 0x00FFFFFF, 0x00040006, 0x0 },
  85         { 0x80D75FFF, 0x000B0000, 0x0 },
  86 };
  87
  88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  89         { 0x00FFFFFF, 0x0007000E, 0x0 },
  90         { 0x00D75FFF, 0x000F000A, 0x0 },
  91         { 0x00C30FFF, 0x00060006, 0x0 },
  92         { 0x00AAAFFF, 0x001E0000, 0x0 },
  93         { 0x00FFFFFF, 0x000F000A, 0x0 },
  94         { 0x00D75FFF, 0x00160004, 0x0 },
  95         { 0x00C30FFF, 0x001E0000, 0x0 },
  96         { 0x00FFFFFF, 0x00060006, 0x0 },
  97         { 0x00D75FFF, 0x001E0000, 0x0 },
  98 };
  99
 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 101                                         /* Idx  NT mV d T mV d  db      */
 102         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 103         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 104         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 105         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 106         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 107         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 108         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 109         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 110         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 111         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 112         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 113         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 117         { 0x00FFFFFF, 0x00000012, 0x0 },
 118         { 0x00EBAFFF, 0x00020011, 0x0 },
 119         { 0x00C71FFF, 0x0006000F, 0x0 },
 120         { 0x00AAAFFF, 0x000E000A, 0x0 },
 121         { 0x00FFFFFF, 0x00020011, 0x0 },
 122         { 0x00DB6FFF, 0x0005000F, 0x0 },
 123         { 0x00BEEFFF, 0x000A000C, 0x0 },
 124         { 0x00FFFFFF, 0x0005000F, 0x0 },
 125         { 0x00DB6FFF, 0x000A000C, 0x0 },
 126 };
 127
 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 129         { 0x00FFFFFF, 0x0007000E, 0x0 },
 130         { 0x00D75FFF, 0x000E000A, 0x0 },
 131         { 0x00BEFFFF, 0x00140006, 0x0 },
 132         { 0x80B2CFFF, 0x001B0002, 0x0 },
 133         { 0x00FFFFFF, 0x000E000A, 0x0 },
 134         { 0x00DB6FFF, 0x00160005, 0x0 },
 135         { 0x80C71FFF, 0x001A0002, 0x0 },
 136         { 0x00F7DFFF, 0x00180004, 0x0 },
 137         { 0x80D75FFF, 0x001B0002, 0x0 },
 138 };
 139
 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 141         { 0x00FFFFFF, 0x0001000E, 0x0 },
 142         { 0x00D75FFF, 0x0004000A, 0x0 },
 143         { 0x00C30FFF, 0x00070006, 0x0 },
 144         { 0x00AAAFFF, 0x000C0000, 0x0 },
 145         { 0x00FFFFFF, 0x0004000A, 0x0 },
 146         { 0x00D75FFF, 0x00090004, 0x0 },
 147         { 0x00C30FFF, 0x000C0000, 0x0 },
 148         { 0x00FFFFFF, 0x00070006, 0x0 },
 149         { 0x00D75FFF, 0x000C0000, 0x0 },
 150 };
 151
 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 153                                         /* Idx  NT mV d T mV df db      */
 154         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 155         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 156         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 157         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 158         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 159         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 160         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 161         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 162         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 163         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 164 };
 165
 166 /* Skylake H and S */
 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 168         { 0x00002016, 0x000000A0, 0x0 },
 169         { 0x00005012, 0x0000009B, 0x0 },
 170         { 0x00007011, 0x00000088, 0x0 },
 171         { 0x80009010, 0x000000C0, 0x1 },
 172         { 0x00002016, 0x0000009B, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000C0, 0x1 },
 175         { 0x00002016, 0x000000DF, 0x0 },
 176         { 0x80005012, 0x000000C0, 0x1 },
 177 };
 178
 179 /* Skylake U */
 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 181         { 0x0000201B, 0x000000A2, 0x0 },
 182         { 0x00005012, 0x00000088, 0x0 },
 183         { 0x80007011, 0x000000CD, 0x1 },
 184         { 0x80009010, 0x000000C0, 0x1 },
 185         { 0x0000201B, 0x0000009D, 0x0 },
 186         { 0x80005012, 0x000000C0, 0x1 },
 187         { 0x80007011, 0x000000C0, 0x1 },
 188         { 0x00002016, 0x00000088, 0x0 },
 189         { 0x80005012, 0x000000C0, 0x1 },
 190 };
 191
 192 /* Skylake Y */
 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 194         { 0x00000018, 0x000000A2, 0x0 },
 195         { 0x00005012, 0x00000088, 0x0 },
 196         { 0x80007011, 0x000000CD, 0x3 },
 197         { 0x80009010, 0x000000C0, 0x3 },
 198         { 0x00000018, 0x0000009D, 0x0 },
 199         { 0x80005012, 0x000000C0, 0x3 },
 200         { 0x80007011, 0x000000C0, 0x3 },
 201         { 0x00000018, 0x00000088, 0x0 },
 202         { 0x80005012, 0x000000C0, 0x3 },
 203 };
 204
 205 /* Kabylake H and S */
 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 207         { 0x00002016, 0x000000A0, 0x0 },
 208         { 0x00005012, 0x0000009B, 0x0 },
 209         { 0x00007011, 0x00000088, 0x0 },
 210         { 0x80009010, 0x000000C0, 0x1 },
 211         { 0x00002016, 0x0000009B, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000C0, 0x1 },
 214         { 0x00002016, 0x00000097, 0x0 },
 215         { 0x80005012, 0x000000C0, 0x1 },
 216 };
 217
 218 /* Kabylake U */
 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 220         { 0x0000201B, 0x000000A1, 0x0 },
 221         { 0x00005012, 0x00000088, 0x0 },
 222         { 0x80007011, 0x000000CD, 0x3 },
 223         { 0x80009010, 0x000000C0, 0x3 },
 224         { 0x0000201B, 0x0000009D, 0x0 },
 225         { 0x80005012, 0x000000C0, 0x3 },
 226         { 0x80007011, 0x000000C0, 0x3 },
 227         { 0x00002016, 0x0000004F, 0x0 },
 228         { 0x80005012, 0x000000C0, 0x3 },
 229 };
 230
 231 /* Kabylake Y */
 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 233         { 0x00001017, 0x000000A1, 0x0 },
 234         { 0x00005012, 0x00000088, 0x0 },
 235         { 0x80007011, 0x000000CD, 0x3 },
 236         { 0x8000800F, 0x000000C0, 0x3 },
 237         { 0x00001017, 0x0000009D, 0x0 },
 238         { 0x80005012, 0x000000C0, 0x3 },
 239         { 0x80007011, 0x000000C0, 0x3 },
 240         { 0x00001017, 0x0000004C, 0x0 },
 241         { 0x80005012, 0x000000C0, 0x3 },
 242 };
 243
 244 /*
 245  * Skylake/Kabylake H and S
 246  * eDP 1.4 low vswing translation parameters
 247  */
 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 249         { 0x00000018, 0x000000A8, 0x0 },
 250         { 0x00004013, 0x000000A9, 0x0 },
 251         { 0x00007011, 0x000000A2, 0x0 },
 252         { 0x00009010, 0x0000009C, 0x0 },
 253         { 0x00000018, 0x000000A9, 0x0 },
 254         { 0x00006013, 0x000000A2, 0x0 },
 255         { 0x00007011, 0x000000A6, 0x0 },
 256         { 0x00000018, 0x000000AB, 0x0 },
 257         { 0x00007013, 0x0000009F, 0x0 },
 258         { 0x00000018, 0x000000DF, 0x0 },
 259 };
 260
 261 /*
 262  * Skylake/Kabylake U
 263  * eDP 1.4 low vswing translation parameters
 264  */
 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 266         { 0x00000018, 0x000000A8, 0x0 },
 267         { 0x00004013, 0x000000A9, 0x0 },
 268         { 0x00007011, 0x000000A2, 0x0 },
 269         { 0x00009010, 0x0000009C, 0x0 },
 270         { 0x00000018, 0x000000A9, 0x0 },
 271         { 0x00006013, 0x000000A2, 0x0 },
 272         { 0x00007011, 0x000000A6, 0x0 },
 273         { 0x00002016, 0x000000AB, 0x0 },
 274         { 0x00005013, 0x0000009F, 0x0 },
 275         { 0x00000018, 0x000000DF, 0x0 },
 276 };
 277
 278 /*
 279  * Skylake/Kabylake Y
 280  * eDP 1.4 low vswing translation parameters
 281  */
 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 283         { 0x00000018, 0x000000A8, 0x0 },
 284         { 0x00004013, 0x000000AB, 0x0 },
 285         { 0x00007011, 0x000000A4, 0x0 },
 286         { 0x00009010, 0x000000DF, 0x0 },
 287         { 0x00000018, 0x000000AA, 0x0 },
 288         { 0x00006013, 0x000000A4, 0x0 },
 289         { 0x00007011, 0x0000009D, 0x0 },
 290         { 0x00000018, 0x000000A0, 0x0 },
 291         { 0x00006012, 0x000000DF, 0x0 },
 292         { 0x00000018, 0x0000008A, 0x0 },
 293 };
 294
 295 /* Skylake/Kabylake U, H and S */
 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 297         { 0x00000018, 0x000000AC, 0x0 },
 298         { 0x00005012, 0x0000009D, 0x0 },
 299         { 0x00007011, 0x00000088, 0x0 },
 300         { 0x00000018, 0x000000A1, 0x0 },
 301         { 0x00000018, 0x00000098, 0x0 },
 302         { 0x00004013, 0x00000088, 0x0 },
 303         { 0x80006012, 0x000000CD, 0x1 },
 304         { 0x00000018, 0x000000DF, 0x0 },
 305         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 306         { 0x80003015, 0x000000C0, 0x1 },
 307         { 0x80000018, 0x000000C0, 0x1 },
 308 };
 309
 310 /* Skylake/Kabylake Y */
 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 312         { 0x00000018, 0x000000A1, 0x0 },
 313         { 0x00005012, 0x000000DF, 0x0 },
 314         { 0x80007011, 0x000000CB, 0x3 },
 315         { 0x00000018, 0x000000A4, 0x0 },
 316         { 0x00000018, 0x0000009D, 0x0 },
 317         { 0x00004013, 0x00000080, 0x0 },
 318         { 0x80006013, 0x000000C0, 0x3 },
 319         { 0x00000018, 0x0000008A, 0x0 },
 320         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 321         { 0x80003015, 0x000000C0, 0x3 },
 322         { 0x80000018, 0x000000C0, 0x3 },
 323 };
 324
 325 struct bxt_ddi_buf_trans {
 326         u8 margin;      /* swing value */
 327         u8 scale;       /* scale value */
 328         u8 enable;      /* scale enable */
 329         u8 deemphasis;
 330 };
 331
 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 333                                         /* Idx  NT mV diff      db  */
 334         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 335         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 336         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 337         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 338         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 339         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 340         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 341         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 342         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 343         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 344 };
 345
 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 347                                         /* Idx  NT mV diff      db  */
 348         { 26, 0, 0, 128, },     /* 0:   200             0   */
 349         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 350         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 351         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 352         { 32, 0, 0, 128, },     /* 4:   250             0   */
 353         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 354         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 355         { 43, 0, 0, 128, },     /* 7:   300             0   */
 356         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 357         { 48, 0, 0, 128, },     /* 9:   300             0   */
 358 };
 359
 360 /* BSpec has 2 recommended values - entries 0 and 8.
 361  * Using the entry with higher vswing.
 362  */
 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 364                                         /* Idx  NT mV diff      db  */
 365         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 366         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 367         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 368         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 369         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 370         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 371         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 372         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 373         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 374         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 375 };
 376
 377 struct cnl_ddi_buf_trans {
 378         u8 dw2_swing_sel;
 379         u8 dw7_n_scalar;
 380         u8 dw4_cursor_coeff;
 381         u8 dw4_post_cursor_2;
 382         u8 dw4_post_cursor_1;
 383 };
 384
 385 /* Voltage Swing Programming for VccIO 0.85V for DP */
 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 387                                                 /* NT mV Trans mV db    */
 388         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 389         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 390         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 391         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 392         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 393         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 394         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 395         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 396         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 397         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 398 };
 399
 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 402                                                 /* NT mV Trans mV db    */
 403         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 404         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 405         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 406         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 407         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 408         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 409         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 410 };
 411
 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 414                                                 /* NT mV Trans mV db    */
 415         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 416         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 417         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 418         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 419         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 420         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 421         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 422         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 423         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424 };
 425
 426 /* Voltage Swing Programming for VccIO 0.95V for DP */
 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 428                                                 /* NT mV Trans mV db    */
 429         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 430         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 431         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 432         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 433         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 434         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 435         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 436         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 437         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 438         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 439 };
 440
 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 443                                                 /* NT mV Trans mV db    */
 444         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 445         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 446         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 447         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 448         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 449         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 450         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 451         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 452         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 453         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 454         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 455 };
 456
 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 459                                                 /* NT mV Trans mV db    */
 460         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 461         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 462         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 463         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 464         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 465         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 466         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 467         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 468         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 469         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470 };
 471
 472 /* Voltage Swing Programming for VccIO 1.05V for DP */
 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 474                                                 /* NT mV Trans mV db    */
 475         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 476         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 477         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 478         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 479         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 480         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 481         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 482         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 483         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 484         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 485 };
 486
 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 489                                                 /* NT mV Trans mV db    */
 490         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 491         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 492         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 493         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 494         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 495         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 496         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 497         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 498         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 499         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 500         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 501 };
 502
 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 505                                                 /* NT mV Trans mV db    */
 506         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 507         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 508         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 509         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 510         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 511         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 512         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 513         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 514         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 515 };
 516
 517 /* icl_combo_phy_ddi_translations */
 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 519                                                 /* NT mV Trans mV db    */
 520         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 521         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 522         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 523         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 524         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 525         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 526         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 527         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 528         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 529         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 530 };
 531
 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 533                                                 /* NT mV Trans mV db    */
 534         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 535         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 536         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 537         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 538         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 539         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 540         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 541         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 542         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 543         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 544 };
 545
 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 547                                                 /* NT mV Trans mV db    */
 548         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 549         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 550         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 551         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 552         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 553         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 554         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 555         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 556         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 557         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 558 };
 559
 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 561                                                 /* NT mV Trans mV db    */
 562         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 563         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 564         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 565         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 566         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 567         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 568         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 569 };
 570
 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 572                                                 /* NT mV Trans mV db    */
 573         { 0xA, 0x33, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 574         { 0xA, 0x47, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 575         { 0xC, 0x64, 0x30, 0x00, 0x0F },        /* 350   700      6.0   */
 576         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 350   900      8.2   */
 577         { 0xA, 0x46, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 578         { 0xC, 0x64, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 579         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 580         { 0xC, 0x61, 0x3F, 0x00, 0x00 },        /* 650   700      0.6   */
 581         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 600   900      3.5   */
 582         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 583 };
 584
 585 struct icl_mg_phy_ddi_buf_trans {
 586         u32 cri_txdeemph_override_11_6;
 587         u32 cri_txdeemph_override_5_0;
 588         u32 cri_txdeemph_override_17_12;
 589 };
 590
 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
 592                                 /* Voltage swing  pre-emphasis */
 593         { 0x18, 0x00, 0x00 },   /* 0              0   */
 594         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 595         { 0x24, 0x00, 0x0C },   /* 0              2   */
 596         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 597         { 0x21, 0x00, 0x00 },   /* 1              0   */
 598         { 0x2B, 0x00, 0x08 },   /* 1              1   */
 599         { 0x30, 0x00, 0x0F },   /* 1              2   */
 600         { 0x31, 0x00, 0x03 },   /* 2              0   */
 601         { 0x34, 0x00, 0x0B },   /* 2              1   */
 602         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 603 };
 604
 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
 606                                 /* Voltage swing  pre-emphasis */
 607         { 0x18, 0x00, 0x00 },   /* 0              0   */
 608         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 609         { 0x24, 0x00, 0x0C },   /* 0              2   */
 610         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 611         { 0x26, 0x00, 0x00 },   /* 1              0   */
 612         { 0x2C, 0x00, 0x07 },   /* 1              1   */
 613         { 0x33, 0x00, 0x0C },   /* 1              2   */
 614         { 0x2E, 0x00, 0x00 },   /* 2              0   */
 615         { 0x36, 0x00, 0x09 },   /* 2              1   */
 616         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 617 };
 618
 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
 620                                 /* HDMI Preset  VS      Pre-emph */
 621         { 0x1A, 0x0, 0x0 },     /* 1            400mV   0dB */
 622         { 0x20, 0x0, 0x0 },     /* 2            500mV   0dB */
 623         { 0x29, 0x0, 0x0 },     /* 3            650mV   0dB */
 624         { 0x32, 0x0, 0x0 },     /* 4            800mV   0dB */
 625         { 0x3F, 0x0, 0x0 },     /* 5            1000mV  0dB */
 626         { 0x3A, 0x0, 0x5 },     /* 6            Full    -1.5 dB */
 627         { 0x39, 0x0, 0x6 },     /* 7            Full    -1.8 dB */
 628         { 0x38, 0x0, 0x7 },     /* 8            Full    -2 dB */
 629         { 0x37, 0x0, 0x8 },     /* 9            Full    -2.5 dB */
 630         { 0x36, 0x0, 0x9 },     /* 10           Full    -3 dB */
 631 };
 632
 633 struct tgl_dkl_phy_ddi_buf_trans {
 634         u32 dkl_vswing_control;
 635         u32 dkl_preshoot_control;
 636         u32 dkl_de_emphasis_control;
 637 };
 638
 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
 640                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 641         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 642         { 0x5, 0x0, 0x05 },     /* 0    1       400mV           3.5 dB */
 643         { 0x2, 0x0, 0x0B },     /* 0    2       400mV           6 dB */
 644         { 0x0, 0x0, 0x18 },     /* 0    3       400mV           9.5 dB */
 645         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 646         { 0x2, 0x0, 0x08 },     /* 1    1       600mV           3.5 dB */
 647         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 648         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 649         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 650         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 651 };
 652
 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = {
 654                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 655         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 656         { 0x5, 0x0, 0x05 },     /* 0    1       400mV           3.5 dB */
 657         { 0x2, 0x0, 0x0B },     /* 0    2       400mV           6 dB */
 658         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 659         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 660         { 0x2, 0x0, 0x08 },     /* 1    1       600mV           3.5 dB */
 661         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 662         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 663         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 664         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 665 };
 666
 667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
 668                                 /* HDMI Preset  VS      Pre-emph */
 669         { 0x7, 0x0, 0x0 },      /* 1            400mV   0dB */
 670         { 0x6, 0x0, 0x0 },      /* 2            500mV   0dB */
 671         { 0x4, 0x0, 0x0 },      /* 3            650mV   0dB */
 672         { 0x2, 0x0, 0x0 },      /* 4            800mV   0dB */
 673         { 0x0, 0x0, 0x0 },      /* 5            1000mV  0dB */
 674         { 0x0, 0x0, 0x5 },      /* 6            Full    -1.5 dB */
 675         { 0x0, 0x0, 0x6 },      /* 7            Full    -1.8 dB */
 676         { 0x0, 0x0, 0x7 },      /* 8            Full    -2 dB */
 677         { 0x0, 0x0, 0x8 },      /* 9            Full    -2.5 dB */
 678         { 0x0, 0x0, 0xA },      /* 10           Full    -3 dB */
 679 };
 680
 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
 682                                                 /* NT mV Trans mV db    */
 683         { 0xA, 0x32, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 684         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 685         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 686         { 0x6, 0x7D, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 687         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 688         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 689         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 690         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 691         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 692         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 693 };
 694
 695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
 696                                                 /* NT mV Trans mV db    */
 697         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 698         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 699         { 0xC, 0x63, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 700         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 701         { 0xA, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 702         { 0xC, 0x63, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 703         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 704         { 0xC, 0x61, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 705         { 0x6, 0x7B, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 706         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 707 };
 708
 709 /*
 710  * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
 711  * that DisplayPort specification requires
 712  */
 713 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
 714                                                 /* VS   pre-emp */
 715         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    0       */
 716         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    1       */
 717         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    2       */
 718         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    3       */
 719         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    0       */
 720         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    1       */
 721         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    2       */
 722         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 2    0       */
 723         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 2    1       */
 724 };
 725
 726 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
 727 {
 728         return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
 729 }
 730
 731 static const struct ddi_buf_trans *
 732 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 733 {
 734         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 735
 736         if (dev_priv->vbt.edp.low_vswing) {
 737                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 738                 return bdw_ddi_translations_edp;
 739         } else {
 740                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 741                 return bdw_ddi_translations_dp;
 742         }
 743 }
 744
 745 static const struct ddi_buf_trans *
 746 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 747 {
 748         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 749
 750         if (IS_SKL_ULX(dev_priv)) {
 751                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 752                 return skl_y_ddi_translations_dp;
 753         } else if (IS_SKL_ULT(dev_priv)) {
 754                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 755                 return skl_u_ddi_translations_dp;
 756         } else {
 757                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 758                 return skl_ddi_translations_dp;
 759         }
 760 }
 761
 762 static const struct ddi_buf_trans *
 763 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 764 {
 765         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 766
 767         if (IS_KBL_ULX(dev_priv) ||
 768             IS_CFL_ULX(dev_priv) ||
 769             IS_CML_ULX(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 771                 return kbl_y_ddi_translations_dp;
 772         } else if (IS_KBL_ULT(dev_priv) ||
 773                    IS_CFL_ULT(dev_priv) ||
 774                    IS_CML_ULT(dev_priv)) {
 775                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 776                 return kbl_u_ddi_translations_dp;
 777         } else {
 778                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 779                 return kbl_ddi_translations_dp;
 780         }
 781 }
 782
 783 static const struct ddi_buf_trans *
 784 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 785 {
 786         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 787
 788         if (dev_priv->vbt.edp.low_vswing) {
 789                 if (IS_SKL_ULX(dev_priv) ||
 790                     IS_KBL_ULX(dev_priv) ||
 791                     IS_CFL_ULX(dev_priv) ||
 792                     IS_CML_ULX(dev_priv)) {
 793                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 794                         return skl_y_ddi_translations_edp;
 795                 } else if (IS_SKL_ULT(dev_priv) ||
 796                            IS_KBL_ULT(dev_priv) ||
 797                            IS_CFL_ULT(dev_priv) ||
 798                            IS_CML_ULT(dev_priv)) {
 799                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 800                         return skl_u_ddi_translations_edp;
 801                 } else {
 802                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 803                         return skl_ddi_translations_edp;
 804                 }
 805         }
 806
 807         if (IS_KABYLAKE(dev_priv) ||
 808             IS_COFFEELAKE(dev_priv) ||
 809             IS_COMETLAKE(dev_priv))
 810                 return kbl_get_buf_trans_dp(encoder, n_entries);
 811         else
 812                 return skl_get_buf_trans_dp(encoder, n_entries);
 813 }
 814
 815 static const struct ddi_buf_trans *
 816 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 817 {
 818         if (IS_SKL_ULX(dev_priv) ||
 819             IS_KBL_ULX(dev_priv) ||
 820             IS_CFL_ULX(dev_priv) ||
 821             IS_CML_ULX(dev_priv)) {
 822                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 823                 return skl_y_ddi_translations_hdmi;
 824         } else {
 825                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 826                 return skl_ddi_translations_hdmi;
 827         }
 828 }
 829
 830 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 831 {
 832         /* Only DDIA and DDIE can select the 10th register with DP */
 833         if (port == PORT_A || port == PORT_E)
 834                 return min(n_entries, 10);
 835         else
 836                 return min(n_entries, 9);
 837 }
 838
 839 static const struct ddi_buf_trans *
 840 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 841 {
 842         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 843
 844         if (IS_KABYLAKE(dev_priv) ||
 845             IS_COFFEELAKE(dev_priv) ||
 846             IS_COMETLAKE(dev_priv)) {
 847                 const struct ddi_buf_trans *ddi_translations =
 848                         kbl_get_buf_trans_dp(encoder, n_entries);
 849                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 850                 return ddi_translations;
 851         } else if (IS_SKYLAKE(dev_priv)) {
 852                 const struct ddi_buf_trans *ddi_translations =
 853                         skl_get_buf_trans_dp(encoder, n_entries);
 854                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 855                 return ddi_translations;
 856         } else if (IS_BROADWELL(dev_priv)) {
 857                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 858                 return  bdw_ddi_translations_dp;
 859         } else if (IS_HASWELL(dev_priv)) {
 860                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 861                 return hsw_ddi_translations_dp;
 862         }
 863
 864         *n_entries = 0;
 865         return NULL;
 866 }
 867
 868 static const struct ddi_buf_trans *
 869 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 870 {
 871         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 872
 873         if (IS_GEN9_BC(dev_priv)) {
 874                 const struct ddi_buf_trans *ddi_translations =
 875                         skl_get_buf_trans_edp(encoder, n_entries);
 876                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 877                 return ddi_translations;
 878         } else if (IS_BROADWELL(dev_priv)) {
 879                 return bdw_get_buf_trans_edp(encoder, n_entries);
 880         } else if (IS_HASWELL(dev_priv)) {
 881                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 882                 return hsw_ddi_translations_dp;
 883         }
 884
 885         *n_entries = 0;
 886         return NULL;
 887 }
 888
 889 static const struct ddi_buf_trans *
 890 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 891                             int *n_entries)
 892 {
 893         if (IS_BROADWELL(dev_priv)) {
 894                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 895                 return bdw_ddi_translations_fdi;
 896         } else if (IS_HASWELL(dev_priv)) {
 897                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 898                 return hsw_ddi_translations_fdi;
 899         }
 900
 901         *n_entries = 0;
 902         return NULL;
 903 }
 904
 905 static const struct ddi_buf_trans *
 906 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
 907                              int *n_entries)
 908 {
 909         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 910
 911         if (IS_GEN9_BC(dev_priv)) {
 912                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 913         } else if (IS_BROADWELL(dev_priv)) {
 914                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 915                 return bdw_ddi_translations_hdmi;
 916         } else if (IS_HASWELL(dev_priv)) {
 917                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 918                 return hsw_ddi_translations_hdmi;
 919         }
 920
 921         *n_entries = 0;
 922         return NULL;
 923 }
 924
 925 static const struct bxt_ddi_buf_trans *
 926 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 927 {
 928         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 929         return bxt_ddi_translations_dp;
 930 }
 931
 932 static const struct bxt_ddi_buf_trans *
 933 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 934 {
 935         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 936
 937         if (dev_priv->vbt.edp.low_vswing) {
 938                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 939                 return bxt_ddi_translations_edp;
 940         }
 941
 942         return bxt_get_buf_trans_dp(encoder, n_entries);
 943 }
 944
 945 static const struct bxt_ddi_buf_trans *
 946 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
 947 {
 948         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 949         return bxt_ddi_translations_hdmi;
 950 }
 951
 952 static const struct cnl_ddi_buf_trans *
 953 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
 954 {
 955         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 956         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 957
 958         if (voltage == VOLTAGE_INFO_0_85V) {
 959                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 960                 return cnl_ddi_translations_hdmi_0_85V;
 961         } else if (voltage == VOLTAGE_INFO_0_95V) {
 962                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 963                 return cnl_ddi_translations_hdmi_0_95V;
 964         } else if (voltage == VOLTAGE_INFO_1_05V) {
 965                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 966                 return cnl_ddi_translations_hdmi_1_05V;
 967         } else {
 968                 *n_entries = 1; /* shut up gcc */
 969                 MISSING_CASE(voltage);
 970         }
 971         return NULL;
 972 }
 973
 974 static const struct cnl_ddi_buf_trans *
 975 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 976 {
 977         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 978         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 979
 980         if (voltage == VOLTAGE_INFO_0_85V) {
 981                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 982                 return cnl_ddi_translations_dp_0_85V;
 983         } else if (voltage == VOLTAGE_INFO_0_95V) {
 984                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 985                 return cnl_ddi_translations_dp_0_95V;
 986         } else if (voltage == VOLTAGE_INFO_1_05V) {
 987                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 988                 return cnl_ddi_translations_dp_1_05V;
 989         } else {
 990                 *n_entries = 1; /* shut up gcc */
 991                 MISSING_CASE(voltage);
 992         }
 993         return NULL;
 994 }
 995
 996 static const struct cnl_ddi_buf_trans *
 997 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 998 {
 999         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1000         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1001
1002         if (dev_priv->vbt.edp.low_vswing) {
1003                 if (voltage == VOLTAGE_INFO_0_85V) {
1004                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1005                         return cnl_ddi_translations_edp_0_85V;
1006                 } else if (voltage == VOLTAGE_INFO_0_95V) {
1007                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1008                         return cnl_ddi_translations_edp_0_95V;
1009                 } else if (voltage == VOLTAGE_INFO_1_05V) {
1010                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1011                         return cnl_ddi_translations_edp_1_05V;
1012                 } else {
1013                         *n_entries = 1; /* shut up gcc */
1014                         MISSING_CASE(voltage);
1015                 }
1016                 return NULL;
1017         } else {
1018                 return cnl_get_buf_trans_dp(encoder, n_entries);
1019         }
1020 }
1021
1022 static const struct cnl_ddi_buf_trans *
1023 icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1024                         int *n_entries)
1025 {
1026         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1027
1028         if (type == INTEL_OUTPUT_HDMI) {
1029                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1030                 return icl_combo_phy_ddi_translations_hdmi;
1031         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
1032                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1033                 return icl_combo_phy_ddi_translations_edp_hbr3;
1034         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1035                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1036                 return icl_combo_phy_ddi_translations_edp_hbr2;
1037         }
1038
1039         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1040         return icl_combo_phy_ddi_translations_dp_hbr2;
1041 }
1042
1043 static const struct icl_mg_phy_ddi_buf_trans *
1044 icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
1045                      int *n_entries)
1046 {
1047         if (type == INTEL_OUTPUT_HDMI) {
1048                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
1049                 return icl_mg_phy_ddi_translations_hdmi;
1050         } else if (rate > 270000) {
1051                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
1052                 return icl_mg_phy_ddi_translations_hbr2_hbr3;
1053         }
1054
1055         *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
1056         return icl_mg_phy_ddi_translations_rbr_hbr;
1057 }
1058
1059 static const struct cnl_ddi_buf_trans *
1060 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1061                         int *n_entries)
1062 {
1063         if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
1064                 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
1065                 return ehl_combo_phy_ddi_translations_dp;
1066         }
1067
1068         return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
1069 }
1070
1071 static const struct cnl_ddi_buf_trans *
1072 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1073                         int *n_entries)
1074 {
1075         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1076
1077         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
1078                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1079
1080                 if (!intel_dp->hobl_failed && rate <= 540000) {
1081                         /* Same table applies to TGL, RKL and DG1 */
1082                         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
1083                         return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
1084                 }
1085         }
1086
1087         if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
1088                 return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
1089         } else if (rate > 270000) {
1090                 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1091                 return tgl_combo_phy_ddi_translations_dp_hbr2;
1092         }
1093
1094         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1095         return tgl_combo_phy_ddi_translations_dp_hbr;
1096 }
1097
1098 static const struct tgl_dkl_phy_ddi_buf_trans *
1099 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
1100                       int *n_entries)
1101 {
1102         if (type == INTEL_OUTPUT_HDMI) {
1103                 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1104                 return tgl_dkl_phy_hdmi_ddi_trans;
1105         } else if (rate > 270000) {
1106                 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
1107                 return tgl_dkl_phy_dp_ddi_trans_hbr2;
1108         }
1109
1110         *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
1111         return tgl_dkl_phy_dp_ddi_trans;
1112 }
1113
1114 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
1115 {
1116         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1117         int n_entries, level, default_entry;
1118         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1119
1120         if (INTEL_GEN(dev_priv) >= 12) {
1121                 if (intel_phy_is_combo(dev_priv, phy))
1122                         tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1123                                                 0, &n_entries);
1124                 else
1125                         tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1126                                               &n_entries);
1127                 default_entry = n_entries - 1;
1128         } else if (INTEL_GEN(dev_priv) == 11) {
1129                 if (intel_phy_is_combo(dev_priv, phy))
1130                         icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1131                                                 0, &n_entries);
1132                 else
1133                         icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1134                                              &n_entries);
1135                 default_entry = n_entries - 1;
1136         } else if (IS_CANNONLAKE(dev_priv)) {
1137                 cnl_get_buf_trans_hdmi(encoder, &n_entries);
1138                 default_entry = n_entries - 1;
1139         } else if (IS_GEN9_LP(dev_priv)) {
1140                 bxt_get_buf_trans_hdmi(encoder, &n_entries);
1141                 default_entry = n_entries - 1;
1142         } else if (IS_GEN9_BC(dev_priv)) {
1143                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1144                 default_entry = 8;
1145         } else if (IS_BROADWELL(dev_priv)) {
1146                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1147                 default_entry = 7;
1148         } else if (IS_HASWELL(dev_priv)) {
1149                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1150                 default_entry = 6;
1151         } else {
1152                 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1153                 return 0;
1154         }
1155
1156         if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1157                 return 0;
1158
1159         level = intel_bios_hdmi_level_shift(encoder);
1160         if (level < 0)
1161                 level = default_entry;
1162
1163         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1164                 level = n_entries - 1;
1165
1166         return level;
1167 }
1168
1169 /*
1170  * Starting with Haswell, DDI port buffers must be programmed with correct
1171  * values in advance. This function programs the correct values for
1172  * DP/eDP/FDI use cases.
1173  */
1174 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1175                                          const struct intel_crtc_state *crtc_state)
1176 {
1177         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1178         u32 iboost_bit = 0;
1179         int i, n_entries;
1180         enum port port = encoder->port;
1181         const struct ddi_buf_trans *ddi_translations;
1182
1183         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1184                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1185                                                                &n_entries);
1186         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1187                 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
1188                                                                &n_entries);
1189         else
1190                 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
1191                                                               &n_entries);
1192
1193         /* If we're boosting the current, set bit 31 of trans1 */
1194         if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1195                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1196
1197         for (i = 0; i < n_entries; i++) {
1198                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1199                                ddi_translations[i].trans1 | iboost_bit);
1200                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1201                                ddi_translations[i].trans2);
1202         }
1203 }
1204
1205 /*
1206  * Starting with Haswell, DDI port buffers must be programmed with correct
1207  * values in advance. This function programs the correct values for
1208  * HDMI/DVI use cases.
1209  */
1210 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1211                                            int level)
1212 {
1213         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1214         u32 iboost_bit = 0;
1215         int n_entries;
1216         enum port port = encoder->port;
1217         const struct ddi_buf_trans *ddi_translations;
1218
1219         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1220
1221         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1222                 return;
1223         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1224                 level = n_entries - 1;
1225
1226         /* If we're boosting the current, set bit 31 of trans1 */
1227         if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1228                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1229
1230         /* Entry 9 is for HDMI: */
1231         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1232                        ddi_translations[level].trans1 | iboost_bit);
1233         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1234                        ddi_translations[level].trans2);
1235 }
1236
1237 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1238                                     enum port port)
1239 {
1240         if (IS_BROXTON(dev_priv)) {
1241                 udelay(16);
1242                 return;
1243         }
1244
1245         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1246                          DDI_BUF_IS_IDLE), 8))
1247                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
1248                         port_name(port));
1249 }
1250
1251 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
1252                                       enum port port)
1253 {
1254         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
1255         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
1256                 usleep_range(518, 1000);
1257                 return;
1258         }
1259
1260         if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1261                           DDI_BUF_IS_IDLE), 500))
1262                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
1263                         port_name(port));
1264 }
1265
1266 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1267 {
1268         switch (pll->info->id) {
1269         case DPLL_ID_WRPLL1:
1270                 return PORT_CLK_SEL_WRPLL1;
1271         case DPLL_ID_WRPLL2:
1272                 return PORT_CLK_SEL_WRPLL2;
1273         case DPLL_ID_SPLL:
1274                 return PORT_CLK_SEL_SPLL;
1275         case DPLL_ID_LCPLL_810:
1276                 return PORT_CLK_SEL_LCPLL_810;
1277         case DPLL_ID_LCPLL_1350:
1278                 return PORT_CLK_SEL_LCPLL_1350;
1279         case DPLL_ID_LCPLL_2700:
1280                 return PORT_CLK_SEL_LCPLL_2700;
1281         default:
1282                 MISSING_CASE(pll->info->id);
1283                 return PORT_CLK_SEL_NONE;
1284         }
1285 }
1286
1287 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1288                                   const struct intel_crtc_state *crtc_state)
1289 {
1290         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1291         int clock = crtc_state->port_clock;
1292         const enum intel_dpll_id id = pll->info->id;
1293
1294         switch (id) {
1295         default:
1296                 /*
1297                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1298                  * here, so do warn if this get passed in
1299                  */
1300                 MISSING_CASE(id);
1301                 return DDI_CLK_SEL_NONE;
1302         case DPLL_ID_ICL_TBTPLL:
1303                 switch (clock) {
1304                 case 162000:
1305                         return DDI_CLK_SEL_TBT_162;
1306                 case 270000:
1307                         return DDI_CLK_SEL_TBT_270;
1308                 case 540000:
1309                         return DDI_CLK_SEL_TBT_540;
1310                 case 810000:
1311                         return DDI_CLK_SEL_TBT_810;
1312                 default:
1313                         MISSING_CASE(clock);
1314                         return DDI_CLK_SEL_NONE;
1315                 }
1316         case DPLL_ID_ICL_MGPLL1:
1317         case DPLL_ID_ICL_MGPLL2:
1318         case DPLL_ID_ICL_MGPLL3:
1319         case DPLL_ID_ICL_MGPLL4:
1320         case DPLL_ID_TGL_MGPLL5:
1321         case DPLL_ID_TGL_MGPLL6:
1322                 return DDI_CLK_SEL_MG;
1323         }
1324 }
1325
1326 /* Starting with Haswell, different DDI ports can work in FDI mode for
1327  * connection to the PCH-located connectors. For this, it is necessary to train
1328  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1329  *
1330  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1331  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1332  * DDI A (which is used for eDP)
1333  */
1334
1335 void hsw_fdi_link_train(struct intel_encoder *encoder,
1336                         const struct intel_crtc_state *crtc_state)
1337 {
1338         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1339         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1340         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1341
1342         intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1343
1344         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1345          * mode set "sequence for CRT port" document:
1346          * - TP1 to TP2 time with the default value
1347          * - FDI delay to 90h
1348          *
1349          * WaFDIAutoLinkSetTimingOverrride:hsw
1350          */
1351         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1352                        FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1353
1354         /* Enable the PCH Receiver FDI PLL */
1355         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1356                      FDI_RX_PLL_ENABLE |
1357                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1358         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1359         intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1360         udelay(220);
1361
1362         /* Switch from Rawclk to PCDclk */
1363         rx_ctl_val |= FDI_PCDCLK;
1364         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1365
1366         /* Configure Port Clock Select */
1367         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1368         intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1369         drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1370
1371         /* Start the training iterating through available voltages and emphasis,
1372          * testing each value twice. */
1373         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1374                 /* Configure DP_TP_CTL with auto-training */
1375                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1376                                DP_TP_CTL_FDI_AUTOTRAIN |
1377                                DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1378                                DP_TP_CTL_LINK_TRAIN_PAT1 |
1379                                DP_TP_CTL_ENABLE);
1380
1381                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1382                  * DDI E does not support port reversal, the functionality is
1383                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1384                  * port reversal bit */
1385                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1386                                DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1387                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1388
1389                 udelay(600);
1390
1391                 /* Program PCH FDI Receiver TU */
1392                 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1393
1394                 /* Enable PCH FDI Receiver with auto-training */
1395                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1396                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1397                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1398
1399                 /* Wait for FDI receiver lane calibration */
1400                 udelay(30);
1401
1402                 /* Unset FDI_RX_MISC pwrdn lanes */
1403                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1404                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1405                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1406                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1407
1408                 /* Wait for FDI auto training time */
1409                 udelay(5);
1410
1411                 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1412                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1413                         drm_dbg_kms(&dev_priv->drm,
1414                                     "FDI link training done on step %d\n", i);
1415                         break;
1416                 }
1417
1418                 /*
1419                  * Leave things enabled even if we failed to train FDI.
1420                  * Results in less fireworks from the state checker.
1421                  */
1422                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1423                         drm_err(&dev_priv->drm, "FDI link training failed!\n");
1424                         break;
1425                 }
1426
1427                 rx_ctl_val &= ~FDI_RX_ENABLE;
1428                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1429                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1430
1431                 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1432                 temp &= ~DDI_BUF_CTL_ENABLE;
1433                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1434                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1435
1436                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1437                 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1438                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1439                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1440                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1441                 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1442
1443                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1444
1445                 /* Reset FDI_RX_MISC pwrdn lanes */
1446                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1447                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1448                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1449                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1450                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1451         }
1452
1453         /* Enable normal pixel sending for FDI */
1454         intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1455                        DP_TP_CTL_FDI_AUTOTRAIN |
1456                        DP_TP_CTL_LINK_TRAIN_NORMAL |
1457                        DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1458                        DP_TP_CTL_ENABLE);
1459 }
1460
1461 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1462 {
1463         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1464         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1465
1466         intel_dp->DP = dig_port->saved_port_bits |
1467                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1468         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1469 }
1470
1471 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1472                                  enum port port)
1473 {
1474         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1475
1476         switch (val) {
1477         case DDI_CLK_SEL_NONE:
1478                 return 0;
1479         case DDI_CLK_SEL_TBT_162:
1480                 return 162000;
1481         case DDI_CLK_SEL_TBT_270:
1482                 return 270000;
1483         case DDI_CLK_SEL_TBT_540:
1484                 return 540000;
1485         case DDI_CLK_SEL_TBT_810:
1486                 return 810000;
1487         default:
1488                 MISSING_CASE(val);
1489                 return 0;
1490         }
1491 }
1492
1493 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1494 {
1495         int dotclock;
1496
1497         if (pipe_config->has_pch_encoder)
1498                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1499                                                     &pipe_config->fdi_m_n);
1500         else if (intel_crtc_has_dp_encoder(pipe_config))
1501                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1502                                                     &pipe_config->dp_m_n);
1503         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1504                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1505         else
1506                 dotclock = pipe_config->port_clock;
1507
1508         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1509             !intel_crtc_has_dp_encoder(pipe_config))
1510                 dotclock *= 2;
1511
1512         if (pipe_config->pixel_multiplier)
1513                 dotclock /= pipe_config->pixel_multiplier;
1514
1515         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1516 }
1517
1518 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1519                                 struct intel_crtc_state *pipe_config)
1520 {
1521         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1522         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1523
1524         if (intel_phy_is_tc(dev_priv, phy) &&
1525             intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1526             DPLL_ID_ICL_TBTPLL)
1527                 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1528                                                                 encoder->port);
1529         else
1530                 pipe_config->port_clock =
1531                         intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
1532
1533         ddi_dotclock_get(pipe_config);
1534 }
1535
1536 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1537                           const struct drm_connector_state *conn_state)
1538 {
1539         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1540         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1541         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1542         u32 temp;
1543
1544         if (!intel_crtc_has_dp_encoder(crtc_state))
1545                 return;
1546
1547         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1548
1549         temp = DP_MSA_MISC_SYNC_CLOCK;
1550
1551         switch (crtc_state->pipe_bpp) {
1552         case 18:
1553                 temp |= DP_MSA_MISC_6_BPC;
1554                 break;
1555         case 24:
1556                 temp |= DP_MSA_MISC_8_BPC;
1557                 break;
1558         case 30:
1559                 temp |= DP_MSA_MISC_10_BPC;
1560                 break;
1561         case 36:
1562                 temp |= DP_MSA_MISC_12_BPC;
1563                 break;
1564         default:
1565                 MISSING_CASE(crtc_state->pipe_bpp);
1566                 break;
1567         }
1568
1569         /* nonsense combination */
1570         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1571                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1572
1573         if (crtc_state->limited_color_range)
1574                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1575
1576         /*
1577          * As per DP 1.2 spec section 2.3.4.3 while sending
1578          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1579          * colorspace information.
1580          */
1581         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1582                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1583
1584         /*
1585          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1586          * of Color Encoding Format and Content Color Gamut] while sending
1587          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1588          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1589          */
1590         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1591                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1592
1593         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1594 }
1595
1596 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1597 {
1598         if (master_transcoder == TRANSCODER_EDP)
1599                 return 0;
1600         else
1601                 return master_transcoder + 1;
1602 }
1603
1604 /*
1605  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1606  *
1607  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1608  * intel_ddi_config_transcoder_func().
1609  */
1610 static u32
1611 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
1612                                       const struct intel_crtc_state *crtc_state)
1613 {
1614         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1615         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1616         enum pipe pipe = crtc->pipe;
1617         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1618         enum port port = encoder->port;
1619         u32 temp;
1620
1621         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1622         temp = TRANS_DDI_FUNC_ENABLE;
1623         if (INTEL_GEN(dev_priv) >= 12)
1624                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1625         else
1626                 temp |= TRANS_DDI_SELECT_PORT(port);
1627
1628         switch (crtc_state->pipe_bpp) {
1629         case 18:
1630                 temp |= TRANS_DDI_BPC_6;
1631                 break;
1632         case 24:
1633                 temp |= TRANS_DDI_BPC_8;
1634                 break;
1635         case 30:
1636                 temp |= TRANS_DDI_BPC_10;
1637                 break;
1638         case 36:
1639                 temp |= TRANS_DDI_BPC_12;
1640                 break;
1641         default:
1642                 BUG();
1643         }
1644
1645         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1646                 temp |= TRANS_DDI_PVSYNC;
1647         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1648                 temp |= TRANS_DDI_PHSYNC;
1649
1650         if (cpu_transcoder == TRANSCODER_EDP) {
1651                 switch (pipe) {
1652                 case PIPE_A:
1653                         /* On Haswell, can only use the always-on power well for
1654                          * eDP when not using the panel fitter, and when not
1655                          * using motion blur mitigation (which we don't
1656                          * support). */
1657                         if (crtc_state->pch_pfit.force_thru)
1658                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1659                         else
1660                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1661                         break;
1662                 case PIPE_B:
1663                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1664                         break;
1665                 case PIPE_C:
1666                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1667                         break;
1668                 default:
1669                         BUG();
1670                         break;
1671                 }
1672         }
1673
1674         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1675                 if (crtc_state->has_hdmi_sink)
1676                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1677                 else
1678                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1679
1680                 if (crtc_state->hdmi_scrambling)
1681                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1682                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1683                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1684         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1685                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1686                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1687         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1688                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1689                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1690
1691                 if (INTEL_GEN(dev_priv) >= 12) {
1692                         enum transcoder master;
1693
1694                         master = crtc_state->mst_master_transcoder;
1695                         drm_WARN_ON(&dev_priv->drm,
1696                                     master == INVALID_TRANSCODER);
1697                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1698                 }
1699         } else {
1700                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1701                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1702         }
1703
1704         if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1705             crtc_state->master_transcoder != INVALID_TRANSCODER) {
1706                 u8 master_select =
1707                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1708
1709                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1710                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1711         }
1712
1713         return temp;
1714 }
1715
1716 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
1717                                       const struct intel_crtc_state *crtc_state)
1718 {
1719         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1720         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1721         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1722
1723         if (INTEL_GEN(dev_priv) >= 11) {
1724                 enum transcoder master_transcoder = crtc_state->master_transcoder;
1725                 u32 ctl2 = 0;
1726
1727                 if (master_transcoder != INVALID_TRANSCODER) {
1728                         u8 master_select =
1729                                 bdw_trans_port_sync_master_select(master_transcoder);
1730
1731                         ctl2 |= PORT_SYNC_MODE_ENABLE |
1732                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1733                 }
1734
1735                 intel_de_write(dev_priv,
1736                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
1737         }
1738
1739         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
1740                        intel_ddi_transcoder_func_reg_val_get(encoder,
1741                                                              crtc_state));
1742 }
1743
1744 /*
1745  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1746  * bit.
1747  */
1748 static void
1749 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
1750                                  const struct intel_crtc_state *crtc_state)
1751 {
1752         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1753         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1754         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1755         u32 ctl;
1756
1757         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
1758         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1759         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1760 }
1761
1762 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1763 {
1764         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1765         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1766         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1767         u32 ctl;
1768
1769         if (INTEL_GEN(dev_priv) >= 11)
1770                 intel_de_write(dev_priv,
1771                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
1772
1773         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1774
1775         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1776
1777         if (IS_GEN_RANGE(dev_priv, 8, 10))
1778                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
1779                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
1780
1781         if (INTEL_GEN(dev_priv) >= 12) {
1782                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
1783                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
1784                                  TRANS_DDI_MODE_SELECT_MASK);
1785                 }
1786         } else {
1787                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
1788         }
1789
1790         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1791
1792         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1793             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1794                 drm_dbg_kms(&dev_priv->drm,
1795                             "Quirk Increase DDI disabled time\n");
1796                 /* Quirk time at 100ms for reliable operation */
1797                 msleep(100);
1798         }
1799 }
1800
1801 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1802                                      bool enable)
1803 {
1804         struct drm_device *dev = intel_encoder->base.dev;
1805         struct drm_i915_private *dev_priv = to_i915(dev);
1806         intel_wakeref_t wakeref;
1807         enum pipe pipe = 0;
1808         int ret = 0;
1809         u32 tmp;
1810
1811         wakeref = intel_display_power_get_if_enabled(dev_priv,
1812                                                      intel_encoder->power_domain);
1813         if (drm_WARN_ON(dev, !wakeref))
1814                 return -ENXIO;
1815
1816         if (drm_WARN_ON(dev,
1817                         !intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1818                 ret = -EIO;
1819                 goto out;
1820         }
1821
1822         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe));
1823         if (enable)
1824                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1825         else
1826                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1827         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp);
1828 out:
1829         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1830         return ret;
1831 }
1832
1833 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1834 {
1835         struct drm_device *dev = intel_connector->base.dev;
1836         struct drm_i915_private *dev_priv = to_i915(dev);
1837         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1838         int type = intel_connector->base.connector_type;
1839         enum port port = encoder->port;
1840         enum transcoder cpu_transcoder;
1841         intel_wakeref_t wakeref;
1842         enum pipe pipe = 0;
1843         u32 tmp;
1844         bool ret;
1845
1846         wakeref = intel_display_power_get_if_enabled(dev_priv,
1847                                                      encoder->power_domain);
1848         if (!wakeref)
1849                 return false;
1850
1851         if (!encoder->get_hw_state(encoder, &pipe)) {
1852                 ret = false;
1853                 goto out;
1854         }
1855
1856         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
1857                 cpu_transcoder = TRANSCODER_EDP;
1858         else
1859                 cpu_transcoder = (enum transcoder) pipe;
1860
1861         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1862
1863         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1864         case TRANS_DDI_MODE_SELECT_HDMI:
1865         case TRANS_DDI_MODE_SELECT_DVI:
1866                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1867                 break;
1868
1869         case TRANS_DDI_MODE_SELECT_DP_SST:
1870                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1871                       type == DRM_MODE_CONNECTOR_DisplayPort;
1872                 break;
1873
1874         case TRANS_DDI_MODE_SELECT_DP_MST:
1875                 /* if the transcoder is in MST state then
1876                  * connector isn't connected */
1877                 ret = false;
1878                 break;
1879
1880         case TRANS_DDI_MODE_SELECT_FDI:
1881                 ret = type == DRM_MODE_CONNECTOR_VGA;
1882                 break;
1883
1884         default:
1885                 ret = false;
1886                 break;
1887         }
1888
1889 out:
1890         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1891
1892         return ret;
1893 }
1894
1895 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1896                                         u8 *pipe_mask, bool *is_dp_mst)
1897 {
1898         struct drm_device *dev = encoder->base.dev;
1899         struct drm_i915_private *dev_priv = to_i915(dev);
1900         enum port port = encoder->port;
1901         intel_wakeref_t wakeref;
1902         enum pipe p;
1903         u32 tmp;
1904         u8 mst_pipe_mask;
1905
1906         *pipe_mask = 0;
1907         *is_dp_mst = false;
1908
1909         wakeref = intel_display_power_get_if_enabled(dev_priv,
1910                                                      encoder->power_domain);
1911         if (!wakeref)
1912                 return;
1913
1914         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1915         if (!(tmp & DDI_BUF_CTL_ENABLE))
1916                 goto out;
1917
1918         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
1919                 tmp = intel_de_read(dev_priv,
1920                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1921
1922                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1923                 default:
1924                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1925                         /* fallthrough */
1926                 case TRANS_DDI_EDP_INPUT_A_ON:
1927                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1928                         *pipe_mask = BIT(PIPE_A);
1929                         break;
1930                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1931                         *pipe_mask = BIT(PIPE_B);
1932                         break;
1933                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1934                         *pipe_mask = BIT(PIPE_C);
1935                         break;
1936                 }
1937
1938                 goto out;
1939         }
1940
1941         mst_pipe_mask = 0;
1942         for_each_pipe(dev_priv, p) {
1943                 enum transcoder cpu_transcoder = (enum transcoder)p;
1944                 unsigned int port_mask, ddi_select;
1945                 intel_wakeref_t trans_wakeref;
1946
1947                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
1948                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1949                 if (!trans_wakeref)
1950                         continue;
1951
1952                 if (INTEL_GEN(dev_priv) >= 12) {
1953                         port_mask = TGL_TRANS_DDI_PORT_MASK;
1954                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
1955                 } else {
1956                         port_mask = TRANS_DDI_PORT_MASK;
1957                         ddi_select = TRANS_DDI_SELECT_PORT(port);
1958                 }
1959
1960                 tmp = intel_de_read(dev_priv,
1961                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
1962                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
1963                                         trans_wakeref);
1964
1965                 if ((tmp & port_mask) != ddi_select)
1966                         continue;
1967
1968                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1969                     TRANS_DDI_MODE_SELECT_DP_MST)
1970                         mst_pipe_mask |= BIT(p);
1971
1972                 *pipe_mask |= BIT(p);
1973         }
1974
1975         if (!*pipe_mask)
1976                 drm_dbg_kms(&dev_priv->drm,
1977                             "No pipe for [ENCODER:%d:%s] found\n",
1978                             encoder->base.base.id, encoder->base.name);
1979
1980         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1981                 drm_dbg_kms(&dev_priv->drm,
1982                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
1983                             encoder->base.base.id, encoder->base.name,
1984                             *pipe_mask);
1985                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
1986         }
1987
1988         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
1989                 drm_dbg_kms(&dev_priv->drm,
1990                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
1991                             encoder->base.base.id, encoder->base.name,
1992                             *pipe_mask, mst_pipe_mask);
1993         else
1994                 *is_dp_mst = mst_pipe_mask;
1995
1996 out:
1997         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
1998                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
1999                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2000                             BXT_PHY_LANE_POWERDOWN_ACK |
2001                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2002                         drm_err(&dev_priv->drm,
2003                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
2004                                 encoder->base.base.id, encoder->base.name, tmp);
2005         }
2006
2007         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2008 }
2009
2010 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2011                             enum pipe *pipe)
2012 {
2013         u8 pipe_mask;
2014         bool is_mst;
2015
2016         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2017
2018         if (is_mst || !pipe_mask)
2019                 return false;
2020
2021         *pipe = ffs(pipe_mask) - 1;
2022
2023         return true;
2024 }
2025
2026 static enum intel_display_power_domain
2027 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2028 {
2029         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2030          * DC states enabled at the same time, while for driver initiated AUX
2031          * transfers we need the same AUX IOs to be powered but with DC states
2032          * disabled. Accordingly use the AUX power domain here which leaves DC
2033          * states enabled.
2034          * However, for non-A AUX ports the corresponding non-EDP transcoders
2035          * would have already enabled power well 2 and DC_OFF. This means we can
2036          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2037          * specific AUX_IO reference without powering up any extra wells.
2038          * Note that PSR is enabled only on Port A even though this function
2039          * returns the correct domain for other ports too.
2040          */
2041         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2042                                               intel_aux_power_domain(dig_port);
2043 }
2044
2045 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2046                                         struct intel_crtc_state *crtc_state)
2047 {
2048         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2049         struct intel_digital_port *dig_port;
2050         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2051
2052         /*
2053          * TODO: Add support for MST encoders. Atm, the following should never
2054          * happen since fake-MST encoders don't set their get_power_domains()
2055          * hook.
2056          */
2057         if (drm_WARN_ON(&dev_priv->drm,
2058                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2059                 return;
2060
2061         dig_port = enc_to_dig_port(encoder);
2062
2063         if (!intel_phy_is_tc(dev_priv, phy) ||
2064             dig_port->tc_mode != TC_PORT_TBT_ALT)
2065                 intel_display_power_get(dev_priv,
2066                                         dig_port->ddi_io_power_domain);
2067
2068         /*
2069          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2070          * ports.
2071          */
2072         if (intel_crtc_has_dp_encoder(crtc_state) ||
2073             intel_phy_is_tc(dev_priv, phy))
2074                 intel_display_power_get(dev_priv,
2075                                         intel_ddi_main_link_aux_domain(dig_port));
2076
2077         /*
2078          * VDSC power is needed when DSC is enabled
2079          */
2080         if (crtc_state->dsc.compression_enable)
2081                 intel_display_power_get(dev_priv,
2082                                         intel_dsc_power_domain(crtc_state));
2083 }
2084
2085 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
2086                                  const struct intel_crtc_state *crtc_state)
2087 {
2088         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2089         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2090         enum port port = encoder->port;
2091         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2092
2093         if (cpu_transcoder != TRANSCODER_EDP) {
2094                 if (INTEL_GEN(dev_priv) >= 12)
2095                         intel_de_write(dev_priv,
2096                                        TRANS_CLK_SEL(cpu_transcoder),
2097                                        TGL_TRANS_CLK_SEL_PORT(port));
2098                 else
2099                         intel_de_write(dev_priv,
2100                                        TRANS_CLK_SEL(cpu_transcoder),
2101                                        TRANS_CLK_SEL_PORT(port));
2102         }
2103 }
2104
2105 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2106 {
2107         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2108         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2109
2110         if (cpu_transcoder != TRANSCODER_EDP) {
2111                 if (INTEL_GEN(dev_priv) >= 12)
2112                         intel_de_write(dev_priv,
2113                                        TRANS_CLK_SEL(cpu_transcoder),
2114                                        TGL_TRANS_CLK_SEL_DISABLED);
2115                 else
2116                         intel_de_write(dev_priv,
2117                                        TRANS_CLK_SEL(cpu_transcoder),
2118                                        TRANS_CLK_SEL_DISABLED);
2119         }
2120 }
2121
2122 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2123                                 enum port port, u8 iboost)
2124 {
2125         u32 tmp;
2126
2127         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2128         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2129         if (iboost)
2130                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2131         else
2132                 tmp |= BALANCE_LEG_DISABLE(port);
2133         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2134 }
2135
2136 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2137                                int level, enum intel_output_type type)
2138 {
2139         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2140         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2141         u8 iboost;
2142
2143         if (type == INTEL_OUTPUT_HDMI)
2144                 iboost = intel_bios_hdmi_boost_level(encoder);
2145         else
2146                 iboost = intel_bios_dp_boost_level(encoder);
2147
2148         if (iboost == 0) {
2149                 const struct ddi_buf_trans *ddi_translations;
2150                 int n_entries;
2151
2152                 if (type == INTEL_OUTPUT_HDMI)
2153                         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
2154                 else if (type == INTEL_OUTPUT_EDP)
2155                         ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
2156                                                                        &n_entries);
2157                 else
2158                         ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
2159                                                                       &n_entries);
2160
2161                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2162                         return;
2163                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2164                         level = n_entries - 1;
2165
2166                 iboost = ddi_translations[level].i_boost;
2167         }
2168
2169         /* Make sure that the requested I_boost is valid */
2170         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2171                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2172                 return;
2173         }
2174
2175         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
2176
2177         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
2178                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2179 }
2180
2181 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2182                                     int level, enum intel_output_type type)
2183 {
2184         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2185         const struct bxt_ddi_buf_trans *ddi_translations;
2186         enum port port = encoder->port;
2187         int n_entries;
2188
2189         if (type == INTEL_OUTPUT_HDMI)
2190                 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
2191         else if (type == INTEL_OUTPUT_EDP)
2192                 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
2193         else
2194                 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
2195
2196         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2197                 return;
2198         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2199                 level = n_entries - 1;
2200
2201         bxt_ddi_phy_set_signal_level(dev_priv, port,
2202                                      ddi_translations[level].margin,
2203                                      ddi_translations[level].scale,
2204                                      ddi_translations[level].enable,
2205                                      ddi_translations[level].deemphasis);
2206 }
2207
2208 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
2209 {
2210         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2211         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2212         enum port port = encoder->port;
2213         enum phy phy = intel_port_to_phy(dev_priv, port);
2214         int n_entries;
2215
2216         if (INTEL_GEN(dev_priv) >= 12) {
2217                 if (intel_phy_is_combo(dev_priv, phy))
2218                         tgl_get_combo_buf_trans(encoder, encoder->type,
2219                                                 intel_dp->link_rate, &n_entries);
2220                 else
2221                         tgl_get_dkl_buf_trans(encoder, encoder->type,
2222                                               intel_dp->link_rate, &n_entries);
2223         } else if (INTEL_GEN(dev_priv) == 11) {
2224                 if (IS_ELKHARTLAKE(dev_priv))
2225                         ehl_get_combo_buf_trans(encoder, encoder->type,
2226                                                 intel_dp->link_rate, &n_entries);
2227                 else if (intel_phy_is_combo(dev_priv, phy))
2228                         icl_get_combo_buf_trans(encoder, encoder->type,
2229                                                 intel_dp->link_rate, &n_entries);
2230                 else
2231                         icl_get_mg_buf_trans(encoder, encoder->type,
2232                                              intel_dp->link_rate, &n_entries);
2233         } else if (IS_CANNONLAKE(dev_priv)) {
2234                 if (encoder->type == INTEL_OUTPUT_EDP)
2235                         cnl_get_buf_trans_edp(encoder, &n_entries);
2236                 else
2237                         cnl_get_buf_trans_dp(encoder, &n_entries);
2238         } else if (IS_GEN9_LP(dev_priv)) {
2239                 if (encoder->type == INTEL_OUTPUT_EDP)
2240                         bxt_get_buf_trans_edp(encoder, &n_entries);
2241                 else
2242                         bxt_get_buf_trans_dp(encoder, &n_entries);
2243         } else {
2244                 if (encoder->type == INTEL_OUTPUT_EDP)
2245                         intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2246                 else
2247                         intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2248         }
2249
2250         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2251                 n_entries = 1;
2252         if (drm_WARN_ON(&dev_priv->drm,
2253                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2254                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2255
2256         return index_to_dp_signal_levels[n_entries - 1] &
2257                 DP_TRAIN_VOLTAGE_SWING_MASK;
2258 }
2259
2260 /*
2261  * We assume that the full set of pre-emphasis values can be
2262  * used on all DDI platforms. Should that change we need to
2263  * rethink this code.
2264  */
2265 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
2266 {
2267         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2268 }
2269
2270 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2271                                    int level, enum intel_output_type type)
2272 {
2273         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2274         const struct cnl_ddi_buf_trans *ddi_translations;
2275         enum port port = encoder->port;
2276         int n_entries, ln;
2277         u32 val;
2278
2279         if (type == INTEL_OUTPUT_HDMI)
2280                 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
2281         else if (type == INTEL_OUTPUT_EDP)
2282                 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
2283         else
2284                 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
2285
2286         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2287                 return;
2288         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2289                 level = n_entries - 1;
2290
2291         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2292         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2293         val &= ~SCALING_MODE_SEL_MASK;
2294         val |= SCALING_MODE_SEL(2);
2295         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2296
2297         /* Program PORT_TX_DW2 */
2298         val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2299         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2300                  RCOMP_SCALAR_MASK);
2301         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2302         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2303         /* Rcomp scalar is fixed as 0x98 for every table entry */
2304         val |= RCOMP_SCALAR(0x98);
2305         intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2306
2307         /* Program PORT_TX_DW4 */
2308         /* We cannot write to GRP. It would overrite individual loadgen */
2309         for (ln = 0; ln < 4; ln++) {
2310                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2311                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2312                          CURSOR_COEFF_MASK);
2313                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2314                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2315                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2316                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2317         }
2318
2319         /* Program PORT_TX_DW5 */
2320         /* All DW5 values are fixed for every table entry */
2321         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2322         val &= ~RTERM_SELECT_MASK;
2323         val |= RTERM_SELECT(6);
2324         val |= TAP3_DISABLE;
2325         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2326
2327         /* Program PORT_TX_DW7 */
2328         val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2329         val &= ~N_SCALAR_MASK;
2330         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2331         intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2332 }
2333
2334 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2335                                     int level, enum intel_output_type type)
2336 {
2337         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2338         enum port port = encoder->port;
2339         int width, rate, ln;
2340         u32 val;
2341
2342         if (type == INTEL_OUTPUT_HDMI) {
2343                 width = 4;
2344                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2345         } else {
2346                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2347
2348                 width = intel_dp->lane_count;
2349                 rate = intel_dp->link_rate;
2350         }
2351
2352         /*
2353          * 1. If port type is eDP or DP,
2354          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2355          * else clear to 0b.
2356          */
2357         val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2358         if (type != INTEL_OUTPUT_HDMI)
2359                 val |= COMMON_KEEPER_EN;
2360         else
2361                 val &= ~COMMON_KEEPER_EN;
2362         intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2363
2364         /* 2. Program loadgen select */
2365         /*
2366          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2367          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2368          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2369          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2370          */
2371         for (ln = 0; ln <= 3; ln++) {
2372                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2373                 val &= ~LOADGEN_SELECT;
2374
2375                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2376                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2377                         val |= LOADGEN_SELECT;
2378                 }
2379                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2380         }
2381
2382         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2383         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2384         val |= SUS_CLOCK_CONFIG;
2385         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2386
2387         /* 4. Clear training enable to change swing values */
2388         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2389         val &= ~TX_TRAINING_EN;
2390         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2391
2392         /* 5. Program swing and de-emphasis */
2393         cnl_ddi_vswing_program(encoder, level, type);
2394
2395         /* 6. Set training enable to trigger update */
2396         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2397         val |= TX_TRAINING_EN;
2398         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2399 }
2400
2401 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
2402                                          u32 level, int type, int rate)
2403 {
2404         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2405         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2406         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2407         u32 n_entries, val;
2408         int ln;
2409
2410         if (INTEL_GEN(dev_priv) >= 12)
2411                 ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
2412                                                            &n_entries);
2413         else if (IS_ELKHARTLAKE(dev_priv))
2414                 ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
2415                                                            &n_entries);
2416         else
2417                 ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
2418                                                            &n_entries);
2419         if (!ddi_translations)
2420                 return;
2421
2422         if (level >= n_entries) {
2423                 drm_dbg_kms(&dev_priv->drm,
2424                             "DDI translation not found for level %d. Using %d instead.",
2425                             level, n_entries - 1);
2426                 level = n_entries - 1;
2427         }
2428
2429         if (type == INTEL_OUTPUT_EDP) {
2430                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2431
2432                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
2433                 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
2434                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
2435                              intel_dp->hobl_active ? val : 0);
2436         }
2437
2438         /* Set PORT_TX_DW5 */
2439         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2440         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2441                   TAP2_DISABLE | TAP3_DISABLE);
2442         val |= SCALING_MODE_SEL(0x2);
2443         val |= RTERM_SELECT(0x6);
2444         val |= TAP3_DISABLE;
2445         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2446
2447         /* Program PORT_TX_DW2 */
2448         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2449         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2450                  RCOMP_SCALAR_MASK);
2451         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2452         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2453         /* Program Rcomp scalar for every table entry */
2454         val |= RCOMP_SCALAR(0x98);
2455         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2456
2457         /* Program PORT_TX_DW4 */
2458         /* We cannot write to GRP. It would overwrite individual loadgen. */
2459         for (ln = 0; ln <= 3; ln++) {
2460                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2461                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2462                          CURSOR_COEFF_MASK);
2463                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2464                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2465                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2466                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2467         }
2468
2469         /* Program PORT_TX_DW7 */
2470         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2471         val &= ~N_SCALAR_MASK;
2472         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2473         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2474 }
2475
2476 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2477                                               u32 level,
2478                                               enum intel_output_type type)
2479 {
2480         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2481         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2482         int width = 0;
2483         int rate = 0;
2484         u32 val;
2485         int ln = 0;
2486
2487         if (type == INTEL_OUTPUT_HDMI) {
2488                 width = 4;
2489                 /* Rate is always < than 6GHz for HDMI */
2490         } else {
2491                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2492
2493                 width = intel_dp->lane_count;
2494                 rate = intel_dp->link_rate;
2495         }
2496
2497         /*
2498          * 1. If port type is eDP or DP,
2499          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2500          * else clear to 0b.
2501          */
2502         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2503         if (type == INTEL_OUTPUT_HDMI)
2504                 val &= ~COMMON_KEEPER_EN;
2505         else
2506                 val |= COMMON_KEEPER_EN;
2507         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2508
2509         /* 2. Program loadgen select */
2510         /*
2511          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2512          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2513          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2514          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2515          */
2516         for (ln = 0; ln <= 3; ln++) {
2517                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2518                 val &= ~LOADGEN_SELECT;
2519
2520                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2521                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2522                         val |= LOADGEN_SELECT;
2523                 }
2524                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2525         }
2526
2527         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2528         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2529         val |= SUS_CLOCK_CONFIG;
2530         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2531
2532         /* 4. Clear training enable to change swing values */
2533         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2534         val &= ~TX_TRAINING_EN;
2535         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2536
2537         /* 5. Program swing and de-emphasis */
2538         icl_ddi_combo_vswing_program(encoder, level, type, rate);
2539
2540         /* 6. Set training enable to trigger update */
2541         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2542         val |= TX_TRAINING_EN;
2543         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2544 }
2545
2546 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2547                                            int link_clock, u32 level,
2548                                            enum intel_output_type type)
2549 {
2550         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2551         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2552         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2553         u32 n_entries, val;
2554         int ln, rate = 0;
2555
2556         if (type != INTEL_OUTPUT_HDMI) {
2557                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2558
2559                 rate = intel_dp->link_rate;
2560         }
2561
2562         ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
2563                                                 &n_entries);
2564         /* The table does not have values for level 3 and level 9. */
2565         if (level >= n_entries || level == 3 || level == 9) {
2566                 drm_dbg_kms(&dev_priv->drm,
2567                             "DDI translation not found for level %d. Using %d instead.",
2568                             level, n_entries - 2);
2569                 level = n_entries - 2;
2570         }
2571
2572         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2573         for (ln = 0; ln < 2; ln++) {
2574                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2575                 val &= ~CRI_USE_FS32;
2576                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2577
2578                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2579                 val &= ~CRI_USE_FS32;
2580                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2581         }
2582
2583         /* Program MG_TX_SWINGCTRL with values from vswing table */
2584         for (ln = 0; ln < 2; ln++) {
2585                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2586                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2587                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2588                         ddi_translations[level].cri_txdeemph_override_17_12);
2589                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2590
2591                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2592                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2593                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2594                         ddi_translations[level].cri_txdeemph_override_17_12);
2595                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2596         }
2597
2598         /* Program MG_TX_DRVCTRL with values from vswing table */
2599         for (ln = 0; ln < 2; ln++) {
2600                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2601                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2602                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2603                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2604                         ddi_translations[level].cri_txdeemph_override_5_0) |
2605                         CRI_TXDEEMPH_OVERRIDE_11_6(
2606                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2607                         CRI_TXDEEMPH_OVERRIDE_EN;
2608                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2609
2610                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2611                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2612                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2613                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2614                         ddi_translations[level].cri_txdeemph_override_5_0) |
2615                         CRI_TXDEEMPH_OVERRIDE_11_6(
2616                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2617                         CRI_TXDEEMPH_OVERRIDE_EN;
2618                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2619
2620                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2621         }
2622
2623         /*
2624          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2625          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2626          * values from table for which TX1 and TX2 enabled.
2627          */
2628         for (ln = 0; ln < 2; ln++) {
2629                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2630                 if (link_clock < 300000)
2631                         val |= CFG_LOW_RATE_LKREN_EN;
2632                 else
2633                         val &= ~CFG_LOW_RATE_LKREN_EN;
2634                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2635         }
2636
2637         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2638         for (ln = 0; ln < 2; ln++) {
2639                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2640                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2641                 if (link_clock <= 500000) {
2642                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2643                 } else {
2644                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2645                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2646                 }
2647                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2648
2649                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2650                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2651                 if (link_clock <= 500000) {
2652                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2653                 } else {
2654                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2655                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2656                 }
2657                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2658         }
2659
2660         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2661         for (ln = 0; ln < 2; ln++) {
2662                 val = intel_de_read(dev_priv,
2663                                     MG_TX1_PISO_READLOAD(ln, tc_port));
2664                 val |= CRI_CALCINIT;
2665                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2666                                val);
2667
2668                 val = intel_de_read(dev_priv,
2669                                     MG_TX2_PISO_READLOAD(ln, tc_port));
2670                 val |= CRI_CALCINIT;
2671                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2672                                val);
2673         }
2674 }
2675
2676 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2677                                     int link_clock,
2678                                     u32 level,
2679                                     enum intel_output_type type)
2680 {
2681         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2682         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2683
2684         if (intel_phy_is_combo(dev_priv, phy))
2685                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2686         else
2687                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
2688                                                type);
2689 }
2690
2691 static void
2692 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2693                                 u32 level, enum intel_output_type type)
2694 {
2695         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2696         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2697         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2698         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2699         int rate = 0;
2700
2701         if (type == INTEL_OUTPUT_HDMI) {
2702                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2703
2704                 rate = intel_dp->link_rate;
2705         }
2706
2707         ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
2708                                                  &n_entries);
2709
2710         if (level >= n_entries)
2711                 level = n_entries - 1;
2712
2713         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2714                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2715                       DKL_TX_VSWING_CONTROL_MASK);
2716         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2717         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2718         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2719
2720         for (ln = 0; ln < 2; ln++) {
2721                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2722                                HIP_INDEX_VAL(tc_port, ln));
2723
2724                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2725
2726                 /* All the registers are RMW */
2727                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2728                 val &= ~dpcnt_mask;
2729                 val |= dpcnt_val;
2730                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2731
2732                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2733                 val &= ~dpcnt_mask;
2734                 val |= dpcnt_val;
2735                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2736
2737                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2738                 val &= ~DKL_TX_DP20BITMODE;
2739                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2740         }
2741 }
2742
2743 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2744                                     int link_clock,
2745                                     u32 level,
2746                                     enum intel_output_type type)
2747 {
2748         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2749         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2750
2751         if (intel_phy_is_combo(dev_priv, phy))
2752                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2753         else
2754                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
2755 }
2756
2757 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
2758 {
2759         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2760         int i;
2761
2762         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2763                 if (index_to_dp_signal_levels[i] == signal_levels)
2764                         return i;
2765         }
2766
2767         drm_WARN(&i915->drm, 1,
2768                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2769                  signal_levels);
2770
2771         return 0;
2772 }
2773
2774 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2775 {
2776         u8 train_set = intel_dp->train_set[0];
2777         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2778                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2779
2780         return translate_signal_level(intel_dp, signal_levels);
2781 }
2782
2783 static void
2784 tgl_set_signal_levels(struct intel_dp *intel_dp)
2785 {
2786         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2787         int level = intel_ddi_dp_level(intel_dp);
2788
2789         tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2790                                 level, encoder->type);
2791 }
2792
2793 static void
2794 icl_set_signal_levels(struct intel_dp *intel_dp)
2795 {
2796         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2797         int level = intel_ddi_dp_level(intel_dp);
2798
2799         icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2800                                 level, encoder->type);
2801 }
2802
2803 static void
2804 cnl_set_signal_levels(struct intel_dp *intel_dp)
2805 {
2806         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2807         int level = intel_ddi_dp_level(intel_dp);
2808
2809         cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2810 }
2811
2812 static void
2813 bxt_set_signal_levels(struct intel_dp *intel_dp)
2814 {
2815         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2816         int level = intel_ddi_dp_level(intel_dp);
2817
2818         bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2819 }
2820
2821 static void
2822 hsw_set_signal_levels(struct intel_dp *intel_dp)
2823 {
2824         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2825         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2826         int level = intel_ddi_dp_level(intel_dp);
2827         enum port port = encoder->port;
2828         u32 signal_levels;
2829
2830         signal_levels = DDI_BUF_TRANS_SELECT(level);
2831
2832         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
2833                     signal_levels);
2834
2835         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
2836         intel_dp->DP |= signal_levels;
2837
2838         if (IS_GEN9_BC(dev_priv))
2839                 skl_ddi_set_iboost(encoder, level, encoder->type);
2840
2841         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
2842         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
2843 }
2844
2845 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2846                                      enum phy phy)
2847 {
2848         if (intel_phy_is_combo(dev_priv, phy)) {
2849                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2850         } else if (intel_phy_is_tc(dev_priv, phy)) {
2851                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2852                                                         (enum port)phy);
2853
2854                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2855         }
2856
2857         return 0;
2858 }
2859
2860 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2861                                   const struct intel_crtc_state *crtc_state)
2862 {
2863         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2864         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2865         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2866         u32 val;
2867
2868         mutex_lock(&dev_priv->dpll.lock);
2869
2870         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2871         drm_WARN_ON(&dev_priv->drm,
2872                     (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2873
2874         if (intel_phy_is_combo(dev_priv, phy)) {
2875                 /*
2876                  * Even though this register references DDIs, note that we
2877                  * want to pass the PHY rather than the port (DDI).  For
2878                  * ICL, port=phy in all cases so it doesn't matter, but for
2879                  * EHL the bspec notes the following:
2880                  *
2881                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2882                  *   Clock Select chooses the PLL for both DDIA and DDID and
2883                  *   drives port A in all cases."
2884                  */
2885                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2886                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2887                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2888                 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
2889         }
2890
2891         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2892         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2893
2894         mutex_unlock(&dev_priv->dpll.lock);
2895 }
2896
2897 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2898 {
2899         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2900         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2901         u32 val;
2902
2903         mutex_lock(&dev_priv->dpll.lock);
2904
2905         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2906         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2907         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2908
2909         mutex_unlock(&dev_priv->dpll.lock);
2910 }
2911
2912 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
2913                                       u32 port_mask, bool ddi_clk_needed)
2914 {
2915         enum port port;
2916         u32 val;
2917
2918         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2919         for_each_port_masked(port, port_mask) {
2920                 enum phy phy = intel_port_to_phy(dev_priv, port);
2921                 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
2922                                                                    phy);
2923
2924                 if (ddi_clk_needed == !ddi_clk_off)
2925                         continue;
2926
2927                 /*
2928                  * Punt on the case now where clock is gated, but it would
2929                  * be needed by the port. Something else is really broken then.
2930                  */
2931                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
2932                         continue;
2933
2934                 drm_notice(&dev_priv->drm,
2935                            "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2936                            phy_name(phy));
2937                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2938                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2939         }
2940 }
2941
2942 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2943 {
2944         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2945         u32 port_mask;
2946         bool ddi_clk_needed;
2947
2948         /*
2949          * In case of DP MST, we sanitize the primary encoder only, not the
2950          * virtual ones.
2951          */
2952         if (encoder->type == INTEL_OUTPUT_DP_MST)
2953                 return;
2954
2955         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2956                 u8 pipe_mask;
2957                 bool is_mst;
2958
2959                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2960                 /*
2961                  * In the unlikely case that BIOS enables DP in MST mode, just
2962                  * warn since our MST HW readout is incomplete.
2963                  */
2964                 if (drm_WARN_ON(&dev_priv->drm, is_mst))
2965                         return;
2966         }
2967
2968         port_mask = BIT(encoder->port);
2969         ddi_clk_needed = encoder->base.crtc;
2970
2971         if (encoder->type == INTEL_OUTPUT_DSI) {
2972                 struct intel_encoder *other_encoder;
2973
2974                 port_mask = intel_dsi_encoder_ports(encoder);
2975                 /*
2976                  * Sanity check that we haven't incorrectly registered another
2977                  * encoder using any of the ports of this DSI encoder.
2978                  */
2979                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2980                         if (other_encoder == encoder)
2981                                 continue;
2982
2983                         if (drm_WARN_ON(&dev_priv->drm,
2984                                         port_mask & BIT(other_encoder->port)))
2985                                 return;
2986                 }
2987                 /*
2988                  * For DSI we keep the ddi clocks gated
2989                  * except during enable/disable sequence.
2990                  */
2991                 ddi_clk_needed = false;
2992         }
2993
2994         icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
2995 }
2996
2997 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2998                                  const struct intel_crtc_state *crtc_state)
2999 {
3000         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3001         enum port port = encoder->port;
3002         enum phy phy = intel_port_to_phy(dev_priv, port);
3003         u32 val;
3004         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3005
3006         if (drm_WARN_ON(&dev_priv->drm, !pll))
3007                 return;
3008
3009         mutex_lock(&dev_priv->dpll.lock);
3010
3011         if (INTEL_GEN(dev_priv) >= 11) {
3012                 if (!intel_phy_is_combo(dev_priv, phy))
3013                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3014                                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3015                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3016                         /*
3017                          * MG does not exist but the programming is required
3018                          * to ungate DDIC and DDID
3019                          */
3020                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3021                                        DDI_CLK_SEL_MG);
3022         } else if (IS_CANNONLAKE(dev_priv)) {
3023                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3024                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3025                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3026                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3027                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3028
3029                 /*
3030                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3031                  * This step and the step before must be done with separate
3032                  * register writes.
3033                  */
3034                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3035                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3036                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3037         } else if (IS_GEN9_BC(dev_priv)) {
3038                 /* DDI -> PLL mapping  */
3039                 val = intel_de_read(dev_priv, DPLL_CTRL2);
3040
3041                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3042                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3043                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3044                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3045
3046                 intel_de_write(dev_priv, DPLL_CTRL2, val);
3047
3048         } else if (INTEL_GEN(dev_priv) < 9) {
3049                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3050                                hsw_pll_to_ddi_pll_sel(pll));
3051         }
3052
3053         mutex_unlock(&dev_priv->dpll.lock);
3054 }
3055
3056 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3057 {
3058         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3059         enum port port = encoder->port;
3060         enum phy phy = intel_port_to_phy(dev_priv, port);
3061
3062         if (INTEL_GEN(dev_priv) >= 11) {
3063                 if (!intel_phy_is_combo(dev_priv, phy) ||
3064                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3065                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3066                                        DDI_CLK_SEL_NONE);
3067         } else if (IS_CANNONLAKE(dev_priv)) {
3068                 intel_de_write(dev_priv, DPCLKA_CFGCR0,
3069                                intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3070         } else if (IS_GEN9_BC(dev_priv)) {
3071                 intel_de_write(dev_priv, DPLL_CTRL2,
3072                                intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
3073         } else if (INTEL_GEN(dev_priv) < 9) {
3074                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3075                                PORT_CLK_SEL_NONE);
3076         }
3077 }
3078
3079 static void
3080 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
3081                        const struct intel_crtc_state *crtc_state)
3082 {
3083         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3084         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3085         u32 ln0, ln1, pin_assignment;
3086         u8 width;
3087
3088         if (dig_port->tc_mode == TC_PORT_TBT_ALT)
3089                 return;
3090
3091         if (INTEL_GEN(dev_priv) >= 12) {
3092                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3093                                HIP_INDEX_VAL(tc_port, 0x0));
3094                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3095                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3096                                HIP_INDEX_VAL(tc_port, 0x1));
3097                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3098         } else {
3099                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
3100                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
3101         }
3102
3103         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3104         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3105
3106         /* DPPATC */
3107         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
3108         width = crtc_state->lane_count;
3109
3110         switch (pin_assignment) {
3111         case 0x0:
3112                 drm_WARN_ON(&dev_priv->drm,
3113                             dig_port->tc_mode != TC_PORT_LEGACY);
3114                 if (width == 1) {
3115                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3116                 } else {
3117                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3118                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3119                 }
3120                 break;
3121         case 0x1:
3122                 if (width == 4) {
3123                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3124                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3125                 }
3126                 break;
3127         case 0x2:
3128                 if (width == 2) {
3129                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3130                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3131                 }
3132                 break;
3133         case 0x3:
3134         case 0x5:
3135                 if (width == 1) {
3136                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3137                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3138                 } else {
3139                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3140                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3141                 }
3142                 break;
3143         case 0x4:
3144         case 0x6:
3145                 if (width == 1) {
3146                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3147                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3148                 } else {
3149                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3150                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3151                 }
3152                 break;
3153         default:
3154                 MISSING_CASE(pin_assignment);
3155         }
3156
3157         if (INTEL_GEN(dev_priv) >= 12) {
3158                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3159                                HIP_INDEX_VAL(tc_port, 0x0));
3160                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3161                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3162                                HIP_INDEX_VAL(tc_port, 0x1));
3163                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3164         } else {
3165                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3166                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3167         }
3168 }
3169
3170 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3171                                         const struct intel_crtc_state *crtc_state)
3172 {
3173         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3174
3175         if (!crtc_state->fec_enable)
3176                 return;
3177
3178         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3179                 drm_dbg_kms(&i915->drm,
3180                             "Failed to set FEC_READY in the sink\n");
3181 }
3182
3183 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3184                                  const struct intel_crtc_state *crtc_state)
3185 {
3186         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3187         struct intel_dp *intel_dp;
3188         u32 val;
3189
3190         if (!crtc_state->fec_enable)
3191                 return;
3192
3193         intel_dp = enc_to_intel_dp(encoder);
3194         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3195         val |= DP_TP_CTL_FEC_ENABLE;
3196         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3197
3198         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3199                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3200                 drm_err(&dev_priv->drm,
3201                         "Timed out waiting for FEC Enable Status\n");
3202 }
3203
3204 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3205                                         const struct intel_crtc_state *crtc_state)
3206 {
3207         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3208         struct intel_dp *intel_dp;
3209         u32 val;
3210
3211         if (!crtc_state->fec_enable)
3212                 return;
3213
3214         intel_dp = enc_to_intel_dp(encoder);
3215         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3216         val &= ~DP_TP_CTL_FEC_ENABLE;
3217         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3218         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3219 }
3220
3221 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3222                                   struct intel_encoder *encoder,
3223                                   const struct intel_crtc_state *crtc_state,
3224                                   const struct drm_connector_state *conn_state)
3225 {
3226         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3227         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3228         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3229         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3230         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3231         int level = intel_ddi_dp_level(intel_dp);
3232         enum transcoder transcoder = crtc_state->cpu_transcoder;
3233
3234         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3235                                  crtc_state->lane_count, is_mst);
3236
3237         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3238         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3239
3240         /*
3241          * 1. Enable Power Wells
3242          *
3243          * This was handled at the beginning of intel_atomic_commit_tail(),
3244          * before we called down into this function.
3245          */
3246
3247         /* 2. Enable Panel Power if PPS is required */
3248         intel_edp_panel_on(intel_dp);
3249
3250         /*
3251          * 3. For non-TBT Type-C ports, set FIA lane count
3252          * (DFLEXDPSP.DPX4TXLATC)
3253          *
3254          * This was done before tgl_ddi_pre_enable_dp by
3255          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3256          */
3257
3258         /*
3259          * 4. Enable the port PLL.
3260          *
3261          * The PLL enabling itself was already done before this function by
3262          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
3263          * configure the PLL to port mapping here.
3264          */
3265         intel_ddi_clk_select(encoder, crtc_state);
3266
3267         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3268         if (!intel_phy_is_tc(dev_priv, phy) ||
3269             dig_port->tc_mode != TC_PORT_TBT_ALT)
3270                 intel_display_power_get(dev_priv,
3271                                         dig_port->ddi_io_power_domain);
3272
3273         /* 6. Program DP_MODE */
3274         icl_program_mg_dp_mode(dig_port, crtc_state);
3275
3276         /*
3277          * 7. The rest of the below are substeps under the bspec's "Enable and
3278          * Train Display Port" step.  Note that steps that are specific to
3279          * MST will be handled by intel_mst_pre_enable_dp() before/after it
3280          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
3281          * us when active_mst_links==0, so any steps designated for "single
3282          * stream or multi-stream master transcoder" can just be performed
3283          * unconditionally here.
3284          */
3285
3286         /*
3287          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3288          * Transcoder.
3289          */
3290         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3291
3292         /*
3293          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3294          * Transport Select
3295          */
3296         intel_ddi_config_transcoder_func(encoder, crtc_state);
3297
3298         /*
3299          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3300          * selected
3301          *
3302          * This will be handled by the intel_dp_start_link_train() farther
3303          * down this function.
3304          */
3305
3306         /* 7.e Configure voltage swing and related IO settings */
3307         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3308                                 encoder->type);
3309
3310         /*
3311          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3312          * the used lanes of the DDI.
3313          */
3314         if (intel_phy_is_combo(dev_priv, phy)) {
3315                 bool lane_reversal =
3316                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3317
3318                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3319                                                crtc_state->lane_count,
3320                                                lane_reversal);
3321         }
3322
3323         /*
3324          * 7.g Configure and enable DDI_BUF_CTL
3325          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3326          *     after 500 us.
3327          *
3328          * We only configure what the register value will be here.  Actual
3329          * enabling happens during link training farther down.
3330          */
3331         intel_ddi_init_dp_buf_reg(encoder);
3332
3333         if (!is_mst)
3334                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3335
3336         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3337         /*
3338          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3339          * in the FEC_CONFIGURATION register to 1 before initiating link
3340          * training
3341          */
3342         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3343
3344         /*
3345          * 7.i Follow DisplayPort specification training sequence (see notes for
3346          *     failure handling)
3347          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3348          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3349          *     (timeout after 800 us)
3350          */
3351         intel_dp_start_link_train(intel_dp);
3352
3353         /* 7.k Set DP_TP_CTL link training to Normal */
3354         if (!is_trans_port_sync_mode(crtc_state))
3355                 intel_dp_stop_link_train(intel_dp);
3356
3357         /* 7.l Configure and enable FEC if needed */
3358         intel_ddi_enable_fec(encoder, crtc_state);
3359         intel_dsc_enable(encoder, crtc_state);
3360 }
3361
3362 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3363                                   struct intel_encoder *encoder,
3364                                   const struct intel_crtc_state *crtc_state,
3365                                   const struct drm_connector_state *conn_state)
3366 {
3367         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3368         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3369         enum port port = encoder->port;
3370         enum phy phy = intel_port_to_phy(dev_priv, port);
3371         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3372         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3373         int level = intel_ddi_dp_level(intel_dp);
3374
3375         if (INTEL_GEN(dev_priv) < 11)
3376                 drm_WARN_ON(&dev_priv->drm,
3377                             is_mst && (port == PORT_A || port == PORT_E));
3378         else
3379                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3380
3381         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3382                                  crtc_state->lane_count, is_mst);
3383
3384         intel_edp_panel_on(intel_dp);
3385
3386         intel_ddi_clk_select(encoder, crtc_state);
3387
3388         if (!intel_phy_is_tc(dev_priv, phy) ||
3389             dig_port->tc_mode != TC_PORT_TBT_ALT)
3390                 intel_display_power_get(dev_priv,
3391                                         dig_port->ddi_io_power_domain);
3392
3393         icl_program_mg_dp_mode(dig_port, crtc_state);
3394
3395         if (INTEL_GEN(dev_priv) >= 11)
3396                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3397                                         level, encoder->type);
3398         else if (IS_CANNONLAKE(dev_priv))
3399                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3400         else if (IS_GEN9_LP(dev_priv))
3401                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3402         else
3403                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3404
3405         if (intel_phy_is_combo(dev_priv, phy)) {
3406                 bool lane_reversal =
3407                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3408
3409                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3410                                                crtc_state->lane_count,
3411                                                lane_reversal);
3412         }
3413
3414         intel_ddi_init_dp_buf_reg(encoder);
3415         if (!is_mst)
3416                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3417         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3418                                               true);
3419         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3420         intel_dp_start_link_train(intel_dp);
3421         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3422             !is_trans_port_sync_mode(crtc_state))
3423                 intel_dp_stop_link_train(intel_dp);
3424
3425         intel_ddi_enable_fec(encoder, crtc_state);
3426
3427         if (!is_mst)
3428                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3429
3430         intel_dsc_enable(encoder, crtc_state);
3431 }
3432
3433 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3434                                     struct intel_encoder *encoder,
3435                                     const struct intel_crtc_state *crtc_state,
3436                                     const struct drm_connector_state *conn_state)
3437 {
3438         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3439
3440         if (INTEL_GEN(dev_priv) >= 12)
3441                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3442         else
3443                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3444
3445         /* MST will call a setting of MSA after an allocating of Virtual Channel
3446          * from MST encoder pre_enable callback.
3447          */
3448         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3449                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3450
3451                 intel_dp_set_m_n(crtc_state, M1_N1);
3452         }
3453 }
3454
3455 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3456                                       struct intel_encoder *encoder,
3457                                       const struct intel_crtc_state *crtc_state,
3458                                       const struct drm_connector_state *conn_state)
3459 {
3460         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3461         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3462         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3463         int level = intel_ddi_hdmi_level(encoder);
3464
3465         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3466         intel_ddi_clk_select(encoder, crtc_state);
3467
3468         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3469
3470         icl_program_mg_dp_mode(dig_port, crtc_state);
3471
3472         if (INTEL_GEN(dev_priv) >= 12)
3473                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3474                                         level, INTEL_OUTPUT_HDMI);
3475         else if (INTEL_GEN(dev_priv) == 11)
3476                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3477                                         level, INTEL_OUTPUT_HDMI);
3478         else if (IS_CANNONLAKE(dev_priv))
3479                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3480         else if (IS_GEN9_LP(dev_priv))
3481                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3482         else
3483                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3484
3485         if (IS_GEN9_BC(dev_priv))
3486                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3487
3488         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3489
3490         dig_port->set_infoframes(encoder,
3491                                  crtc_state->has_infoframe,
3492                                  crtc_state, conn_state);
3493 }
3494
3495 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3496                                  struct intel_encoder *encoder,
3497                                  const struct intel_crtc_state *crtc_state,
3498                                  const struct drm_connector_state *conn_state)
3499 {
3500         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3501         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3502         enum pipe pipe = crtc->pipe;
3503
3504         /*
3505          * When called from DP MST code:
3506          * - conn_state will be NULL
3507          * - encoder will be the main encoder (ie. mst->primary)
3508          * - the main connector associated with this port
3509          *   won't be active or linked to a crtc
3510          * - crtc_state will be the state of the first stream to
3511          *   be activated on this port, and it may not be the same
3512          *   stream that will be deactivated last, but each stream
3513          *   should have a state that is identical when it comes to
3514          *   the DP link parameteres
3515          */
3516
3517         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3518
3519         if (INTEL_GEN(dev_priv) >= 11)
3520                 icl_map_plls_to_ports(encoder, crtc_state);
3521
3522         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3523
3524         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3525                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3526                                           conn_state);
3527         } else {
3528                 struct intel_lspcon *lspcon =
3529                                 enc_to_intel_lspcon(encoder);
3530
3531                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3532                                         conn_state);
3533                 if (lspcon->active) {
3534                         struct intel_digital_port *dig_port =
3535                                         enc_to_dig_port(encoder);
3536
3537                         dig_port->set_infoframes(encoder,
3538                                                  crtc_state->has_infoframe,
3539                                                  crtc_state, conn_state);
3540                 }
3541         }
3542 }
3543
3544 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3545                                   const struct intel_crtc_state *crtc_state)
3546 {
3547         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3548         enum port port = encoder->port;
3549         bool wait = false;
3550         u32 val;
3551
3552         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3553         if (val & DDI_BUF_CTL_ENABLE) {
3554                 val &= ~DDI_BUF_CTL_ENABLE;
3555                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3556                 wait = true;
3557         }
3558
3559         if (intel_crtc_has_dp_encoder(crtc_state)) {
3560                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3561
3562                 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3563                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3564                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3565                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3566         }
3567
3568         /* Disable FEC in DP Sink */
3569         intel_ddi_disable_fec_state(encoder, crtc_state);
3570
3571         if (wait)
3572                 intel_wait_ddi_buf_idle(dev_priv, port);
3573 }
3574
3575 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3576                                       struct intel_encoder *encoder,
3577                                       const struct intel_crtc_state *old_crtc_state,
3578                                       const struct drm_connector_state *old_conn_state)
3579 {
3580         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3581         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3582         struct intel_dp *intel_dp = &dig_port->dp;
3583         bool is_mst = intel_crtc_has_type(old_crtc_state,
3584                                           INTEL_OUTPUT_DP_MST);
3585         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3586
3587         if (!is_mst)
3588                 intel_dp_set_infoframes(encoder, false,
3589                                         old_crtc_state, old_conn_state);
3590
3591         /*
3592          * Power down sink before disabling the port, otherwise we end
3593          * up getting interrupts from the sink on detecting link loss.
3594          */
3595         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3596
3597         if (INTEL_GEN(dev_priv) >= 12) {
3598                 if (is_mst) {
3599                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3600                         u32 val;
3601
3602                         val = intel_de_read(dev_priv,
3603                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
3604                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
3605                                  TRANS_DDI_MODE_SELECT_MASK);
3606                         intel_de_write(dev_priv,
3607                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
3608                                        val);
3609                 }
3610         } else {
3611                 if (!is_mst)
3612                         intel_ddi_disable_pipe_clock(old_crtc_state);
3613         }
3614
3615         intel_disable_ddi_buf(encoder, old_crtc_state);
3616
3617         /*
3618          * From TGL spec: "If single stream or multi-stream master transcoder:
3619          * Configure Transcoder Clock select to direct no clock to the
3620          * transcoder"
3621          */
3622         if (INTEL_GEN(dev_priv) >= 12)
3623                 intel_ddi_disable_pipe_clock(old_crtc_state);
3624
3625         intel_edp_panel_vdd_on(intel_dp);
3626         intel_edp_panel_off(intel_dp);
3627
3628         if (!intel_phy_is_tc(dev_priv, phy) ||
3629             dig_port->tc_mode != TC_PORT_TBT_ALT)
3630                 intel_display_power_put_unchecked(dev_priv,
3631                                                   dig_port->ddi_io_power_domain);
3632
3633         intel_ddi_clk_disable(encoder);
3634 }
3635
3636 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3637                                         struct intel_encoder *encoder,
3638                                         const struct intel_crtc_state *old_crtc_state,
3639                                         const struct drm_connector_state *old_conn_state)
3640 {
3641         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3642         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3643         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3644
3645         dig_port->set_infoframes(encoder, false,
3646                                  old_crtc_state, old_conn_state);
3647
3648         intel_ddi_disable_pipe_clock(old_crtc_state);
3649
3650         intel_disable_ddi_buf(encoder, old_crtc_state);
3651
3652         intel_display_power_put_unchecked(dev_priv,
3653                                           dig_port->ddi_io_power_domain);
3654
3655         intel_ddi_clk_disable(encoder);
3656
3657         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3658 }
3659
3660 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3661                                    struct intel_encoder *encoder,
3662                                    const struct intel_crtc_state *old_crtc_state,
3663                                    const struct drm_connector_state *old_conn_state)
3664 {
3665         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3666         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3667         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3668         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3669
3670         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3671                 intel_crtc_vblank_off(old_crtc_state);
3672
3673                 intel_disable_pipe(old_crtc_state);
3674
3675                 intel_ddi_disable_transcoder_func(old_crtc_state);
3676
3677                 intel_dsc_disable(old_crtc_state);
3678
3679                 if (INTEL_GEN(dev_priv) >= 9)
3680                         skl_scaler_disable(old_crtc_state);
3681                 else
3682                         ilk_pfit_disable(old_crtc_state);
3683         }
3684
3685         /*
3686          * When called from DP MST code:
3687          * - old_conn_state will be NULL
3688          * - encoder will be the main encoder (ie. mst->primary)
3689          * - the main connector associated with this port
3690          *   won't be active or linked to a crtc
3691          * - old_crtc_state will be the state of the last stream to
3692          *   be deactivated on this port, and it may not be the same
3693          *   stream that was activated last, but each stream
3694          *   should have a state that is identical when it comes to
3695          *   the DP link parameteres
3696          */
3697
3698         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3699                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3700                                             old_conn_state);
3701         else
3702                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3703                                           old_conn_state);
3704
3705         if (INTEL_GEN(dev_priv) >= 11)
3706                 icl_unmap_plls_to_ports(encoder);
3707
3708         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3709                 intel_display_power_put_unchecked(dev_priv,
3710                                                   intel_ddi_main_link_aux_domain(dig_port));
3711
3712         if (is_tc_port)
3713                 intel_tc_port_put_link(dig_port);
3714 }
3715
3716 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
3717                                 struct intel_encoder *encoder,
3718                                 const struct intel_crtc_state *old_crtc_state,
3719                                 const struct drm_connector_state *old_conn_state)
3720 {
3721         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3722         u32 val;
3723
3724         /*
3725          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3726          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3727          * step 13 is the correct place for it. Step 18 is where it was
3728          * originally before the BUN.
3729          */
3730         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3731         val &= ~FDI_RX_ENABLE;
3732         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3733
3734         intel_disable_ddi_buf(encoder, old_crtc_state);
3735         intel_ddi_clk_disable(encoder);
3736
3737         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3738         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3739         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3740         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3741
3742         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3743         val &= ~FDI_PCDCLK;
3744         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3745
3746         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3747         val &= ~FDI_RX_PLL_ENABLE;
3748         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3749 }
3750
3751 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3752                                             struct intel_encoder *encoder,
3753                                             const struct intel_crtc_state *crtc_state)
3754 {
3755         const struct drm_connector_state *conn_state;
3756         struct drm_connector *conn;
3757         int i;
3758
3759         if (!crtc_state->sync_mode_slaves_mask)
3760                 return;
3761
3762         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3763                 struct intel_encoder *slave_encoder =
3764                         to_intel_encoder(conn_state->best_encoder);
3765                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3766                 const struct intel_crtc_state *slave_crtc_state;
3767
3768                 if (!slave_crtc)
3769                         continue;
3770
3771                 slave_crtc_state =
3772                         intel_atomic_get_new_crtc_state(state, slave_crtc);
3773
3774                 if (slave_crtc_state->master_transcoder !=
3775                     crtc_state->cpu_transcoder)
3776                         continue;
3777
3778                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
3779         }
3780
3781         usleep_range(200, 400);
3782
3783         intel_dp_stop_link_train(enc_to_intel_dp(encoder));
3784 }
3785
3786 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3787                                 struct intel_encoder *encoder,
3788                                 const struct intel_crtc_state *crtc_state,
3789                                 const struct drm_connector_state *conn_state)
3790 {
3791         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3792         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3793         enum port port = encoder->port;
3794
3795         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3796                 intel_dp_stop_link_train(intel_dp);
3797
3798         intel_edp_backlight_on(crtc_state, conn_state);
3799         intel_psr_enable(intel_dp, crtc_state, conn_state);
3800         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3801         intel_edp_drrs_enable(intel_dp, crtc_state);
3802
3803         if (crtc_state->has_audio)
3804                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3805
3806         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3807 }
3808
3809 static i915_reg_t
3810 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3811                                enum port port)
3812 {
3813         static const enum transcoder trans[] = {
3814                 [PORT_A] = TRANSCODER_EDP,
3815                 [PORT_B] = TRANSCODER_A,
3816                 [PORT_C] = TRANSCODER_B,
3817                 [PORT_D] = TRANSCODER_C,
3818                 [PORT_E] = TRANSCODER_A,
3819         };
3820
3821         drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
3822
3823         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3824                 port = PORT_A;
3825
3826         return CHICKEN_TRANS(trans[port]);
3827 }
3828
3829 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3830                                   struct intel_encoder *encoder,
3831                                   const struct intel_crtc_state *crtc_state,
3832                                   const struct drm_connector_state *conn_state)
3833 {
3834         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3835         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3836         struct drm_connector *connector = conn_state->connector;
3837         enum port port = encoder->port;
3838
3839         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3840                                                crtc_state->hdmi_high_tmds_clock_ratio,
3841                                                crtc_state->hdmi_scrambling))
3842                 drm_dbg_kms(&dev_priv->drm,
3843                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3844                             connector->base.id, connector->name);
3845
3846         /* Display WA #1143: skl,kbl,cfl */
3847         if (IS_GEN9_BC(dev_priv)) {
3848                 /*
3849                  * For some reason these chicken bits have been
3850                  * stuffed into a transcoder register, event though
3851                  * the bits affect a specific DDI port rather than
3852                  * a specific transcoder.
3853                  */
3854                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3855                 u32 val;
3856
3857                 val = intel_de_read(dev_priv, reg);
3858
3859                 if (port == PORT_E)
3860                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3861                                 DDIE_TRAINING_OVERRIDE_VALUE;
3862                 else
3863                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3864                                 DDI_TRAINING_OVERRIDE_VALUE;
3865
3866                 intel_de_write(dev_priv, reg, val);
3867                 intel_de_posting_read(dev_priv, reg);
3868
3869                 udelay(1);
3870
3871                 if (port == PORT_E)
3872                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3873                                  DDIE_TRAINING_OVERRIDE_VALUE);
3874                 else
3875                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3876                                  DDI_TRAINING_OVERRIDE_VALUE);
3877
3878                 intel_de_write(dev_priv, reg, val);
3879         }
3880
3881         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3882          * are ignored so nothing special needs to be done besides
3883          * enabling the port.
3884          */
3885         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3886                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3887
3888         if (crtc_state->has_audio)
3889                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3890 }
3891
3892 static void intel_enable_ddi(struct intel_atomic_state *state,
3893                              struct intel_encoder *encoder,
3894                              const struct intel_crtc_state *crtc_state,
3895                              const struct drm_connector_state *conn_state)
3896 {
3897         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3898
3899         intel_ddi_enable_transcoder_func(encoder, crtc_state);
3900
3901         intel_enable_pipe(crtc_state);
3902
3903         intel_crtc_vblank_on(crtc_state);
3904
3905         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3906                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3907         else
3908                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3909
3910         /* Enable hdcp if it's desired */
3911         if (conn_state->content_protection ==
3912             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3913                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3914                                   crtc_state->cpu_transcoder,
3915                                   (u8)conn_state->hdcp_content_type);
3916 }
3917
3918 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3919                                  struct intel_encoder *encoder,
3920                                  const struct intel_crtc_state *old_crtc_state,
3921                                  const struct drm_connector_state *old_conn_state)
3922 {
3923         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3924
3925         intel_dp->link_trained = false;
3926
3927         if (old_crtc_state->has_audio)
3928                 intel_audio_codec_disable(encoder,
3929                                           old_crtc_state, old_conn_state);
3930
3931         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3932         intel_psr_disable(intel_dp, old_crtc_state);
3933         intel_edp_backlight_off(old_conn_state);
3934         /* Disable the decompression in DP Sink */
3935         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3936                                               false);
3937 }
3938
3939 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3940                                    struct intel_encoder *encoder,
3941                                    const struct intel_crtc_state *old_crtc_state,
3942                                    const struct drm_connector_state *old_conn_state)
3943 {
3944         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3945         struct drm_connector *connector = old_conn_state->connector;
3946
3947         if (old_crtc_state->has_audio)
3948                 intel_audio_codec_disable(encoder,
3949                                           old_crtc_state, old_conn_state);
3950
3951         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3952                                                false, false))
3953                 drm_dbg_kms(&i915->drm,
3954                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3955                             connector->base.id, connector->name);
3956 }
3957
3958 static void intel_disable_ddi(struct intel_atomic_state *state,
3959                               struct intel_encoder *encoder,
3960                               const struct intel_crtc_state *old_crtc_state,
3961                               const struct drm_connector_state *old_conn_state)
3962 {
3963         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3964
3965         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3966                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3967                                        old_conn_state);
3968         else
3969                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3970                                      old_conn_state);
3971 }
3972
3973 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3974                                      struct intel_encoder *encoder,
3975                                      const struct intel_crtc_state *crtc_state,
3976                                      const struct drm_connector_state *conn_state)
3977 {
3978         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3979
3980         intel_ddi_set_dp_msa(crtc_state, conn_state);
3981
3982         intel_psr_update(intel_dp, crtc_state, conn_state);
3983         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3984         intel_edp_drrs_enable(intel_dp, crtc_state);
3985
3986         intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
3987 }
3988
3989 static void intel_ddi_update_pipe(struct intel_atomic_state *state,
3990                                   struct intel_encoder *encoder,
3991                                   const struct intel_crtc_state *crtc_state,
3992                                   const struct drm_connector_state *conn_state)
3993 {
3994
3995         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3996                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3997                                          conn_state);
3998
3999         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
4000 }
4001
4002 static void
4003 intel_ddi_update_prepare(struct intel_atomic_state *state,
4004                          struct intel_encoder *encoder,
4005                          struct intel_crtc *crtc)
4006 {
4007         struct intel_crtc_state *crtc_state =
4008                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4009         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4010
4011         drm_WARN_ON(state->base.dev, crtc && crtc->active);
4012
4013         intel_tc_port_get_link(enc_to_dig_port(encoder),
4014                                required_lanes);
4015         if (crtc_state && crtc_state->hw.active)
4016                 intel_update_active_dpll(state, crtc, encoder);
4017 }
4018
4019 static void
4020 intel_ddi_update_complete(struct intel_atomic_state *state,
4021                           struct intel_encoder *encoder,
4022                           struct intel_crtc *crtc)
4023 {
4024         intel_tc_port_put_link(enc_to_dig_port(encoder));
4025 }
4026
4027 static void
4028 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
4029                          struct intel_encoder *encoder,
4030                          const struct intel_crtc_state *crtc_state,
4031                          const struct drm_connector_state *conn_state)
4032 {
4033         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4034         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4035         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4036         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4037
4038         if (is_tc_port)
4039                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4040
4041         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4042                 intel_display_power_get(dev_priv,
4043                                         intel_ddi_main_link_aux_domain(dig_port));
4044
4045         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4046                 /*
4047                  * Program the lane count for static/dynamic connections on
4048                  * Type-C ports.  Skip this step for TBT.
4049                  */
4050                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4051         else if (IS_GEN9_LP(dev_priv))
4052                 bxt_ddi_phy_set_lane_optim_mask(encoder,
4053                                                 crtc_state->lane_lat_optim_mask);
4054 }
4055
4056 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4057 {
4058         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4059         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4060         enum port port = dig_port->base.port;
4061         u32 dp_tp_ctl, ddi_buf_ctl;
4062         bool wait = false;
4063
4064         dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4065
4066         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4067                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
4068                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4069                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
4070                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4071                         wait = true;
4072                 }
4073
4074                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4075                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4076                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4077                 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4078
4079                 if (wait)
4080                         intel_wait_ddi_buf_idle(dev_priv, port);
4081         }
4082
4083         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
4084         if (intel_dp->link_mst)
4085                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4086         else {
4087                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4088                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4089                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4090         }
4091         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4092         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4093
4094         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4095         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
4096         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
4097
4098         intel_wait_ddi_buf_active(dev_priv, port);
4099 }
4100
4101 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
4102                                      u8 dp_train_pat)
4103 {
4104         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4105         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
4106         u32 temp;
4107
4108         temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4109
4110         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4111         switch (dp_train_pat & train_pat_mask) {
4112         case DP_TRAINING_PATTERN_DISABLE:
4113                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
4114                 break;
4115         case DP_TRAINING_PATTERN_1:
4116                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
4117                 break;
4118         case DP_TRAINING_PATTERN_2:
4119                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
4120                 break;
4121         case DP_TRAINING_PATTERN_3:
4122                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
4123                 break;
4124         case DP_TRAINING_PATTERN_4:
4125                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
4126                 break;
4127         }
4128
4129         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
4130 }
4131
4132 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
4133 {
4134         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4135         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4136         enum port port = encoder->port;
4137         u32 val;
4138
4139         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4140         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4141         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4142         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4143
4144         /*
4145          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4146          * reason we need to set idle transmission mode is to work around a HW
4147          * issue where we enable the pipe while not in idle link-training mode.
4148          * In this case there is requirement to wait for a minimum number of
4149          * idle patterns to be sent.
4150          */
4151         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4152                 return;
4153
4154         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4155                                   DP_TP_STATUS_IDLE_DONE, 1))
4156                 drm_err(&dev_priv->drm,
4157                         "Timed out waiting for DP idle patterns\n");
4158 }
4159
4160 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4161                                        enum transcoder cpu_transcoder)
4162 {
4163         if (cpu_transcoder == TRANSCODER_EDP)
4164                 return false;
4165
4166         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4167                 return false;
4168
4169         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
4170                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4171 }
4172
4173 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4174                                          struct intel_crtc_state *crtc_state)
4175 {
4176         if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
4177                 crtc_state->min_voltage_level = 2;
4178         else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
4179                 crtc_state->min_voltage_level = 3;
4180         else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4181                 crtc_state->min_voltage_level = 1;
4182         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4183                 crtc_state->min_voltage_level = 2;
4184 }
4185
4186 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
4187                                                      enum transcoder cpu_transcoder)
4188 {
4189         u32 master_select;
4190
4191         if (INTEL_GEN(dev_priv) >= 11) {
4192                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4193
4194                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4195                         return INVALID_TRANSCODER;
4196
4197                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4198         } else {
4199                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4200
4201                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4202                         return INVALID_TRANSCODER;
4203
4204                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4205         }
4206
4207         if (master_select == 0)
4208                 return TRANSCODER_EDP;
4209         else
4210                 return master_select - 1;
4211 }
4212
4213 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4214 {
4215         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4216         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4217                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4218         enum transcoder cpu_transcoder;
4219
4220         crtc_state->master_transcoder =
4221                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4222
4223         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4224                 enum intel_display_power_domain power_domain;
4225                 intel_wakeref_t trans_wakeref;
4226
4227                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4228                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4229                                                                    power_domain);
4230
4231                 if (!trans_wakeref)
4232                         continue;
4233
4234                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4235                     crtc_state->cpu_transcoder)
4236                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4237
4238                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4239         }
4240
4241         drm_WARN_ON(&dev_priv->drm,
4242                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
4243                     crtc_state->sync_mode_slaves_mask);
4244 }
4245
4246 void intel_ddi_get_config(struct intel_encoder *encoder,
4247                           struct intel_crtc_state *pipe_config)
4248 {
4249         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4250         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4251         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4252         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4253         u32 temp, flags = 0;
4254
4255         /* XXX: DSI transcoder paranoia */
4256         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4257                 return;
4258
4259         intel_dsc_get_config(encoder, pipe_config);
4260
4261         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4262         if (temp & TRANS_DDI_PHSYNC)
4263                 flags |= DRM_MODE_FLAG_PHSYNC;
4264         else
4265                 flags |= DRM_MODE_FLAG_NHSYNC;
4266         if (temp & TRANS_DDI_PVSYNC)
4267                 flags |= DRM_MODE_FLAG_PVSYNC;
4268         else
4269                 flags |= DRM_MODE_FLAG_NVSYNC;
4270
4271         pipe_config->hw.adjusted_mode.flags |= flags;
4272
4273         switch (temp & TRANS_DDI_BPC_MASK) {
4274         case TRANS_DDI_BPC_6:
4275                 pipe_config->pipe_bpp = 18;
4276                 break;
4277         case TRANS_DDI_BPC_8:
4278                 pipe_config->pipe_bpp = 24;
4279                 break;
4280         case TRANS_DDI_BPC_10:
4281                 pipe_config->pipe_bpp = 30;
4282                 break;
4283         case TRANS_DDI_BPC_12:
4284                 pipe_config->pipe_bpp = 36;
4285                 break;
4286         default:
4287                 break;
4288         }
4289
4290         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4291         case TRANS_DDI_MODE_SELECT_HDMI:
4292                 pipe_config->has_hdmi_sink = true;
4293
4294                 pipe_config->infoframes.enable |=
4295                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4296
4297                 if (pipe_config->infoframes.enable)
4298                         pipe_config->has_infoframe = true;
4299
4300                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4301                         pipe_config->hdmi_scrambling = true;
4302                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4303                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4304                 /* fall through */
4305         case TRANS_DDI_MODE_SELECT_DVI:
4306                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4307                 pipe_config->lane_count = 4;
4308                 break;
4309         case TRANS_DDI_MODE_SELECT_FDI:
4310                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4311                 break;
4312         case TRANS_DDI_MODE_SELECT_DP_SST:
4313                 if (encoder->type == INTEL_OUTPUT_EDP)
4314                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4315                 else
4316                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4317                 pipe_config->lane_count =
4318                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4319                 intel_dp_get_m_n(intel_crtc, pipe_config);
4320
4321                 if (INTEL_GEN(dev_priv) >= 11) {
4322                         i915_reg_t dp_tp_ctl;
4323
4324                         if (IS_GEN(dev_priv, 11))
4325                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4326                         else
4327                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4328
4329                         pipe_config->fec_enable =
4330                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4331
4332                         drm_dbg_kms(&dev_priv->drm,
4333                                     "[ENCODER:%d:%s] Fec status: %u\n",
4334                                     encoder->base.base.id, encoder->base.name,
4335                                     pipe_config->fec_enable);
4336                 }
4337
4338                 pipe_config->infoframes.enable |=
4339                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4340
4341                 break;
4342         case TRANS_DDI_MODE_SELECT_DP_MST:
4343                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4344                 pipe_config->lane_count =
4345                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4346
4347                 if (INTEL_GEN(dev_priv) >= 12)
4348                         pipe_config->mst_master_transcoder =
4349                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4350
4351                 intel_dp_get_m_n(intel_crtc, pipe_config);
4352
4353                 pipe_config->infoframes.enable |=
4354                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4355                 break;
4356         default:
4357                 break;
4358         }
4359
4360         if (INTEL_GEN(dev_priv) >= 12) {
4361                 enum transcoder transcoder =
4362                         intel_dp_mst_is_slave_trans(pipe_config) ?
4363                         pipe_config->mst_master_transcoder :
4364                         pipe_config->cpu_transcoder;
4365
4366                 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
4367                 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
4368         }
4369
4370         pipe_config->has_audio =
4371                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4372
4373         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4374             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4375                 /*
4376                  * This is a big fat ugly hack.
4377                  *
4378                  * Some machines in UEFI boot mode provide us a VBT that has 18
4379                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4380                  * unknown we fail to light up. Yet the same BIOS boots up with
4381                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4382                  * max, not what it tells us to use.
4383                  *
4384                  * Note: This will still be broken if the eDP panel is not lit
4385                  * up by the BIOS, and thus we can't get the mode at module
4386                  * load.
4387                  */
4388                 drm_dbg_kms(&dev_priv->drm,
4389                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4390                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4391                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4392         }
4393
4394         intel_ddi_clock_get(encoder, pipe_config);
4395
4396         if (IS_GEN9_LP(dev_priv))
4397                 pipe_config->lane_lat_optim_mask =
4398                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4399
4400         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4401
4402         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4403
4404         intel_read_infoframe(encoder, pipe_config,
4405                              HDMI_INFOFRAME_TYPE_AVI,
4406                              &pipe_config->infoframes.avi);
4407         intel_read_infoframe(encoder, pipe_config,
4408                              HDMI_INFOFRAME_TYPE_SPD,
4409                              &pipe_config->infoframes.spd);
4410         intel_read_infoframe(encoder, pipe_config,
4411                              HDMI_INFOFRAME_TYPE_VENDOR,
4412                              &pipe_config->infoframes.hdmi);
4413         intel_read_infoframe(encoder, pipe_config,
4414                              HDMI_INFOFRAME_TYPE_DRM,
4415                              &pipe_config->infoframes.drm);
4416
4417         if (INTEL_GEN(dev_priv) >= 8)
4418                 bdw_get_trans_port_sync_config(pipe_config);
4419
4420         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4421         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4422 }
4423
4424 static enum intel_output_type
4425 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4426                               struct intel_crtc_state *crtc_state,
4427                               struct drm_connector_state *conn_state)
4428 {
4429         switch (conn_state->connector->connector_type) {
4430         case DRM_MODE_CONNECTOR_HDMIA:
4431                 return INTEL_OUTPUT_HDMI;
4432         case DRM_MODE_CONNECTOR_eDP:
4433                 return INTEL_OUTPUT_EDP;
4434         case DRM_MODE_CONNECTOR_DisplayPort:
4435                 return INTEL_OUTPUT_DP;
4436         default:
4437                 MISSING_CASE(conn_state->connector->connector_type);
4438                 return INTEL_OUTPUT_UNUSED;
4439         }
4440 }
4441
4442 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4443                                     struct intel_crtc_state *pipe_config,
4444                                     struct drm_connector_state *conn_state)
4445 {
4446         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4447         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4448         enum port port = encoder->port;
4449         int ret;
4450
4451         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4452                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4453
4454         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4455                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4456         } else {
4457                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4458         }
4459
4460         if (ret)
4461                 return ret;
4462
4463         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4464             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4465                 pipe_config->pch_pfit.force_thru =
4466                         pipe_config->pch_pfit.enabled ||
4467                         pipe_config->crc_enabled;
4468
4469         if (IS_GEN9_LP(dev_priv))
4470                 pipe_config->lane_lat_optim_mask =
4471                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4472
4473         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4474
4475         return 0;
4476 }
4477
4478 static bool mode_equal(const struct drm_display_mode *mode1,
4479                        const struct drm_display_mode *mode2)
4480 {
4481         return drm_mode_match(mode1, mode2,
4482                               DRM_MODE_MATCH_TIMINGS |
4483                               DRM_MODE_MATCH_FLAGS |
4484                               DRM_MODE_MATCH_3D_FLAGS) &&
4485                 mode1->clock == mode2->clock; /* we want an exact match */
4486 }
4487
4488 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4489                       const struct intel_link_m_n *m_n_2)
4490 {
4491         return m_n_1->tu == m_n_2->tu &&
4492                 m_n_1->gmch_m == m_n_2->gmch_m &&
4493                 m_n_1->gmch_n == m_n_2->gmch_n &&
4494                 m_n_1->link_m == m_n_2->link_m &&
4495                 m_n_1->link_n == m_n_2->link_n;
4496 }
4497
4498 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4499                                        const struct intel_crtc_state *crtc_state2)
4500 {
4501         return crtc_state1->hw.active && crtc_state2->hw.active &&
4502                 crtc_state1->output_types == crtc_state2->output_types &&
4503                 crtc_state1->output_format == crtc_state2->output_format &&
4504                 crtc_state1->lane_count == crtc_state2->lane_count &&
4505                 crtc_state1->port_clock == crtc_state2->port_clock &&
4506                 mode_equal(&crtc_state1->hw.adjusted_mode,
4507                            &crtc_state2->hw.adjusted_mode) &&
4508                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4509 }
4510
4511 static u8
4512 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4513                                 int tile_group_id)
4514 {
4515         struct drm_connector *connector;
4516         const struct drm_connector_state *conn_state;
4517         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4518         struct intel_atomic_state *state =
4519                 to_intel_atomic_state(ref_crtc_state->uapi.state);
4520         u8 transcoders = 0;
4521         int i;
4522
4523         /*
4524          * We don't enable port sync on BDW due to missing w/as and
4525          * due to not having adjusted the modeset sequence appropriately.
4526          */
4527         if (INTEL_GEN(dev_priv) < 9)
4528                 return 0;
4529
4530         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4531                 return 0;
4532
4533         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4534                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4535                 const struct intel_crtc_state *crtc_state;
4536
4537                 if (!crtc)
4538                         continue;
4539
4540                 if (!connector->has_tile ||
4541                     connector->tile_group->id !=
4542                     tile_group_id)
4543                         continue;
4544                 crtc_state = intel_atomic_get_new_crtc_state(state,
4545                                                              crtc);
4546                 if (!crtcs_port_sync_compatible(ref_crtc_state,
4547                                                 crtc_state))
4548                         continue;
4549                 transcoders |= BIT(crtc_state->cpu_transcoder);
4550         }
4551
4552         return transcoders;
4553 }
4554
4555 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4556                                          struct intel_crtc_state *crtc_state,
4557                                          struct drm_connector_state *conn_state)
4558 {
4559         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4560         struct drm_connector *connector = conn_state->connector;
4561         u8 port_sync_transcoders = 0;
4562
4563         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4564                     encoder->base.base.id, encoder->base.name,
4565                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4566
4567         if (connector->has_tile)
4568                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4569                                                                         connector->tile_group->id);
4570
4571         /*
4572          * EDP Transcoders cannot be ensalved
4573          * make them a master always when present
4574          */
4575         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4576                 crtc_state->master_transcoder = TRANSCODER_EDP;
4577         else
4578                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4579
4580         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4581                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4582                 crtc_state->sync_mode_slaves_mask =
4583                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4584         }
4585
4586         return 0;
4587 }
4588
4589 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4590 {
4591         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4592
4593         intel_dp_encoder_flush_work(encoder);
4594
4595         drm_encoder_cleanup(encoder);
4596         kfree(dig_port);
4597 }
4598
4599 static const struct drm_encoder_funcs intel_ddi_funcs = {
4600         .reset = intel_dp_encoder_reset,
4601         .destroy = intel_ddi_encoder_destroy,
4602 };
4603
4604 static struct intel_connector *
4605 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4606 {
4607         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4608         struct intel_connector *connector;
4609         enum port port = dig_port->base.port;
4610
4611         connector = intel_connector_alloc();
4612         if (!connector)
4613                 return NULL;
4614
4615         dig_port->dp.output_reg = DDI_BUF_CTL(port);
4616         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4617         dig_port->dp.set_link_train = intel_ddi_set_link_train;
4618         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4619
4620         if (INTEL_GEN(dev_priv) >= 12)
4621                 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4622         else if (INTEL_GEN(dev_priv) >= 11)
4623                 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4624         else if (IS_CANNONLAKE(dev_priv))
4625                 dig_port->dp.set_signal_levels = cnl_set_signal_levels;
4626         else if (IS_GEN9_LP(dev_priv))
4627                 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4628         else
4629                 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4630
4631         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4632         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4633
4634         if (INTEL_GEN(dev_priv) < 12) {
4635                 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
4636                 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
4637         }
4638
4639         if (!intel_dp_init_connector(dig_port, connector)) {
4640                 kfree(connector);
4641                 return NULL;
4642         }
4643
4644         return connector;
4645 }
4646
4647 static int modeset_pipe(struct drm_crtc *crtc,
4648                         struct drm_modeset_acquire_ctx *ctx)
4649 {
4650         struct drm_atomic_state *state;
4651         struct drm_crtc_state *crtc_state;
4652         int ret;
4653
4654         state = drm_atomic_state_alloc(crtc->dev);
4655         if (!state)
4656                 return -ENOMEM;
4657
4658         state->acquire_ctx = ctx;
4659
4660         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4661         if (IS_ERR(crtc_state)) {
4662                 ret = PTR_ERR(crtc_state);
4663                 goto out;
4664         }
4665
4666         crtc_state->connectors_changed = true;
4667
4668         ret = drm_atomic_commit(state);
4669 out:
4670         drm_atomic_state_put(state);
4671
4672         return ret;
4673 }
4674
4675 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4676                                  struct drm_modeset_acquire_ctx *ctx)
4677 {
4678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4679         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4680         struct intel_connector *connector = hdmi->attached_connector;
4681         struct i2c_adapter *adapter =
4682                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4683         struct drm_connector_state *conn_state;
4684         struct intel_crtc_state *crtc_state;
4685         struct intel_crtc *crtc;
4686         u8 config;
4687         int ret;
4688
4689         if (!connector || connector->base.status != connector_status_connected)
4690                 return 0;
4691
4692         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4693                                ctx);
4694         if (ret)
4695                 return ret;
4696
4697         conn_state = connector->base.state;
4698
4699         crtc = to_intel_crtc(conn_state->crtc);
4700         if (!crtc)
4701                 return 0;
4702
4703         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4704         if (ret)
4705                 return ret;
4706
4707         crtc_state = to_intel_crtc_state(crtc->base.state);
4708
4709         drm_WARN_ON(&dev_priv->drm,
4710                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4711
4712         if (!crtc_state->hw.active)
4713                 return 0;
4714
4715         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4716             !crtc_state->hdmi_scrambling)
4717                 return 0;
4718
4719         if (conn_state->commit &&
4720             !try_wait_for_completion(&conn_state->commit->hw_done))
4721                 return 0;
4722
4723         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4724         if (ret < 0) {
4725                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4726                         ret);
4727                 return 0;
4728         }
4729
4730         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4731             crtc_state->hdmi_high_tmds_clock_ratio &&
4732             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4733             crtc_state->hdmi_scrambling)
4734                 return 0;
4735
4736         /*
4737          * HDMI 2.0 says that one should not send scrambled data
4738          * prior to configuring the sink scrambling, and that
4739          * TMDS clock/data transmission should be suspended when
4740          * changing the TMDS clock rate in the sink. So let's
4741          * just do a full modeset here, even though some sinks
4742          * would be perfectly happy if were to just reconfigure
4743          * the SCDC settings on the fly.
4744          */
4745         return modeset_pipe(&crtc->base, ctx);
4746 }
4747
4748 static enum intel_hotplug_state
4749 intel_ddi_hotplug(struct intel_encoder *encoder,
4750                   struct intel_connector *connector)
4751 {
4752         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4753         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4754         enum phy phy = intel_port_to_phy(i915, encoder->port);
4755         bool is_tc = intel_phy_is_tc(i915, phy);
4756         struct drm_modeset_acquire_ctx ctx;
4757         enum intel_hotplug_state state;
4758         int ret;
4759
4760         state = intel_encoder_hotplug(encoder, connector);
4761
4762         drm_modeset_acquire_init(&ctx, 0);
4763
4764         for (;;) {
4765                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4766                         ret = intel_hdmi_reset_link(encoder, &ctx);
4767                 else
4768                         ret = intel_dp_retrain_link(encoder, &ctx);
4769
4770                 if (ret == -EDEADLK) {
4771                         drm_modeset_backoff(&ctx);
4772                         continue;
4773                 }
4774
4775                 break;
4776         }
4777
4778         drm_modeset_drop_locks(&ctx);
4779         drm_modeset_acquire_fini(&ctx);
4780         drm_WARN(encoder->base.dev, ret,
4781                  "Acquiring modeset locks failed with %i\n", ret);
4782
4783         /*
4784          * Unpowered type-c dongles can take some time to boot and be
4785          * responsible, so here giving some time to those dongles to power up
4786          * and then retrying the probe.
4787          *
4788          * On many platforms the HDMI live state signal is known to be
4789          * unreliable, so we can't use it to detect if a sink is connected or
4790          * not. Instead we detect if it's connected based on whether we can
4791          * read the EDID or not. That in turn has a problem during disconnect,
4792          * since the HPD interrupt may be raised before the DDC lines get
4793          * disconnected (due to how the required length of DDC vs. HPD
4794          * connector pins are specified) and so we'll still be able to get a
4795          * valid EDID. To solve this schedule another detection cycle if this
4796          * time around we didn't detect any change in the sink's connection
4797          * status.
4798          *
4799          * Type-c connectors which get their HPD signal deasserted then
4800          * reasserted, without unplugging/replugging the sink from the
4801          * connector, introduce a delay until the AUX channel communication
4802          * becomes functional. Retry the detection for 5 seconds on type-c
4803          * connectors to account for this delay.
4804          */
4805         if (state == INTEL_HOTPLUG_UNCHANGED &&
4806             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4807             !dig_port->dp.is_mst)
4808                 state = INTEL_HOTPLUG_RETRY;
4809
4810         return state;
4811 }
4812
4813 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4814 {
4815         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4816         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4817
4818         return intel_de_read(dev_priv, SDEISR) & bit;
4819 }
4820
4821 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4822 {
4823         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4824         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4825
4826         return intel_de_read(dev_priv, DEISR) & bit;
4827 }
4828
4829 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4830 {
4831         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4832         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4833
4834         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4835 }
4836
4837 static struct intel_connector *
4838 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4839 {
4840         struct intel_connector *connector;
4841         enum port port = dig_port->base.port;
4842
4843         connector = intel_connector_alloc();
4844         if (!connector)
4845                 return NULL;
4846
4847         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4848         intel_hdmi_init_connector(dig_port, connector);
4849
4850         return connector;
4851 }
4852
4853 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4854 {
4855         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4856
4857         if (dig_port->base.port != PORT_A)
4858                 return false;
4859
4860         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4861                 return false;
4862
4863         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4864          *                     supported configuration
4865          */
4866         if (IS_GEN9_LP(dev_priv))
4867                 return true;
4868
4869         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4870          *             one who does also have a full A/E split called
4871          *             DDI_F what makes DDI_E useless. However for this
4872          *             case let's trust VBT info.
4873          */
4874         if (IS_CANNONLAKE(dev_priv) &&
4875             !intel_bios_is_port_present(dev_priv, PORT_E))
4876                 return true;
4877
4878         return false;
4879 }
4880
4881 static int
4882 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4883 {
4884         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4885         enum port port = dig_port->base.port;
4886         int max_lanes = 4;
4887
4888         if (INTEL_GEN(dev_priv) >= 11)
4889                 return max_lanes;
4890
4891         if (port == PORT_A || port == PORT_E) {
4892                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4893                         max_lanes = port == PORT_A ? 4 : 0;
4894                 else
4895                         /* Both A and E share 2 lanes */
4896                         max_lanes = 2;
4897         }
4898
4899         /*
4900          * Some BIOS might fail to set this bit on port A if eDP
4901          * wasn't lit up at boot.  Force this bit set when needed
4902          * so we use the proper lane count for our calculations.
4903          */
4904         if (intel_ddi_a_force_4_lanes(dig_port)) {
4905                 drm_dbg_kms(&dev_priv->drm,
4906                             "Forcing DDI_A_4_LANES for port A\n");
4907                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4908                 max_lanes = 4;
4909         }
4910
4911         return max_lanes;
4912 }
4913
4914 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4915 {
4916         struct intel_digital_port *dig_port;
4917         struct intel_encoder *encoder;
4918         bool init_hdmi, init_dp, init_lspcon = false;
4919         enum phy phy = intel_port_to_phy(dev_priv, port);
4920
4921         init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
4922                 intel_bios_port_supports_hdmi(dev_priv, port);
4923         init_dp = intel_bios_port_supports_dp(dev_priv, port);
4924
4925         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4926                 /*
4927                  * Lspcon device needs to be driven with DP connector
4928                  * with special detection sequence. So make sure DP
4929                  * is initialized before lspcon.
4930                  */
4931                 init_dp = true;
4932                 init_lspcon = true;
4933                 init_hdmi = false;
4934                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4935                             port_name(port));
4936         }
4937
4938         if (!init_dp && !init_hdmi) {
4939                 drm_dbg_kms(&dev_priv->drm,
4940                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4941                             port_name(port));
4942                 return;
4943         }
4944
4945         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4946         if (!dig_port)
4947                 return;
4948
4949         encoder = &dig_port->base;
4950
4951         drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4952                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4953
4954         encoder->hotplug = intel_ddi_hotplug;
4955         encoder->compute_output_type = intel_ddi_compute_output_type;
4956         encoder->compute_config = intel_ddi_compute_config;
4957         encoder->compute_config_late = intel_ddi_compute_config_late;
4958         encoder->enable = intel_enable_ddi;
4959         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4960         encoder->pre_enable = intel_ddi_pre_enable;
4961         encoder->disable = intel_disable_ddi;
4962         encoder->post_disable = intel_ddi_post_disable;
4963         encoder->update_pipe = intel_ddi_update_pipe;
4964         encoder->get_hw_state = intel_ddi_get_hw_state;
4965         encoder->get_config = intel_ddi_get_config;
4966         encoder->suspend = intel_dp_encoder_suspend;
4967         encoder->get_power_domains = intel_ddi_get_power_domains;
4968
4969         encoder->type = INTEL_OUTPUT_DDI;
4970         encoder->power_domain = intel_port_to_power_domain(port);
4971         encoder->port = port;
4972         encoder->cloneable = 0;
4973         encoder->pipe_mask = ~0;
4974
4975         if (INTEL_GEN(dev_priv) >= 11)
4976                 dig_port->saved_port_bits =
4977                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4978                         & DDI_BUF_PORT_REVERSAL;
4979         else
4980                 dig_port->saved_port_bits =
4981                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4982                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4983
4984         dig_port->dp.output_reg = INVALID_MMIO_REG;
4985         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4986         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4987
4988         if (intel_phy_is_tc(dev_priv, phy)) {
4989                 bool is_legacy =
4990                         !intel_bios_port_supports_typec_usb(dev_priv, port) &&
4991                         !intel_bios_port_supports_tbt(dev_priv, port);
4992
4993                 intel_tc_port_init(dig_port, is_legacy);
4994
4995                 encoder->update_prepare = intel_ddi_update_prepare;
4996                 encoder->update_complete = intel_ddi_update_complete;
4997         }
4998
4999         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5000         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
5001                                               port - PORT_A;
5002
5003         if (init_dp) {
5004                 if (!intel_ddi_init_dp_connector(dig_port))
5005                         goto err;
5006
5007                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5008         }
5009
5010         /* In theory we don't need the encoder->type check, but leave it just in
5011          * case we have some really bad VBTs... */
5012         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5013                 if (!intel_ddi_init_hdmi_connector(dig_port))
5014                         goto err;
5015         }
5016
5017         if (init_lspcon) {
5018                 if (lspcon_init(dig_port))
5019                         /* TODO: handle hdmi info frame part */
5020                         drm_dbg_kms(&dev_priv->drm,
5021                                     "LSPCON init success on port %c\n",
5022                                     port_name(port));
5023                 else
5024                         /*
5025                          * LSPCON init faied, but DP init was success, so
5026                          * lets try to drive as DP++ port.
5027                          */
5028                         drm_err(&dev_priv->drm,
5029                                 "LSPCON init failed on port %c\n",
5030                                 port_name(port));
5031         }
5032
5033         if (INTEL_GEN(dev_priv) >= 11) {
5034                 if (intel_phy_is_tc(dev_priv, phy))
5035                         dig_port->connected = intel_tc_port_connected;
5036                 else
5037                         dig_port->connected = lpt_digital_port_connected;
5038         } else if (INTEL_GEN(dev_priv) >= 8) {
5039                 if (port == PORT_A || IS_GEN9_LP(dev_priv))
5040                         dig_port->connected = bdw_digital_port_connected;
5041                 else
5042                         dig_port->connected = lpt_digital_port_connected;
5043         } else {
5044                 if (port == PORT_A)
5045                         dig_port->connected = hsw_digital_port_connected;
5046                 else
5047                         dig_port->connected = lpt_digital_port_connected;
5048         }
5049
5050         intel_infoframe_init(dig_port);
5051
5052         return;
5053
5054 err:
5055         drm_encoder_cleanup(&encoder->base);
5056         kfree(dig_port);
5057 }