drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_mst.h"
  38 #include "intel_dp_link_training.h"
  39 #include "intel_dpio_phy.h"
  40 #include "intel_dsi.h"
  41 #include "intel_fifo_underrun.h"
  42 #include "intel_gmbus.h"
  43 #include "intel_hdcp.h"
  44 #include "intel_hdmi.h"
  45 #include "intel_hotplug.h"
  46 #include "intel_lspcon.h"
  47 #include "intel_panel.h"
  48 #include "intel_psr.h"
  49 #include "intel_sprite.h"
  50 #include "intel_tc.h"
  51 #include "intel_vdsc.h"
  52
  53 struct ddi_buf_trans {
  54         u32 trans1;     /* balance leg enable, de-emph level */
  55         u32 trans2;     /* vref sel, vswing */
  56         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  57 };
  58
  59 static const u8 index_to_dp_signal_levels[] = {
  60         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  61         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  62         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  63         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  64         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  69         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  70 };
  71
  72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  73  * them for both DP and FDI transports, allowing those ports to
  74  * automatically adapt to HDMI connections as well
  75  */
  76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  77         { 0x00FFFFFF, 0x0006000E, 0x0 },
  78         { 0x00D75FFF, 0x0005000A, 0x0 },
  79         { 0x00C30FFF, 0x00040006, 0x0 },
  80         { 0x80AAAFFF, 0x000B0000, 0x0 },
  81         { 0x00FFFFFF, 0x0005000A, 0x0 },
  82         { 0x00D75FFF, 0x000C0004, 0x0 },
  83         { 0x80C30FFF, 0x000B0000, 0x0 },
  84         { 0x00FFFFFF, 0x00040006, 0x0 },
  85         { 0x80D75FFF, 0x000B0000, 0x0 },
  86 };
  87
  88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  89         { 0x00FFFFFF, 0x0007000E, 0x0 },
  90         { 0x00D75FFF, 0x000F000A, 0x0 },
  91         { 0x00C30FFF, 0x00060006, 0x0 },
  92         { 0x00AAAFFF, 0x001E0000, 0x0 },
  93         { 0x00FFFFFF, 0x000F000A, 0x0 },
  94         { 0x00D75FFF, 0x00160004, 0x0 },
  95         { 0x00C30FFF, 0x001E0000, 0x0 },
  96         { 0x00FFFFFF, 0x00060006, 0x0 },
  97         { 0x00D75FFF, 0x001E0000, 0x0 },
  98 };
  99
 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 101                                         /* Idx  NT mV d T mV d  db      */
 102         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 103         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 104         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 105         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 106         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 107         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 108         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 109         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 110         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 111         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 112         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 113         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 117         { 0x00FFFFFF, 0x00000012, 0x0 },
 118         { 0x00EBAFFF, 0x00020011, 0x0 },
 119         { 0x00C71FFF, 0x0006000F, 0x0 },
 120         { 0x00AAAFFF, 0x000E000A, 0x0 },
 121         { 0x00FFFFFF, 0x00020011, 0x0 },
 122         { 0x00DB6FFF, 0x0005000F, 0x0 },
 123         { 0x00BEEFFF, 0x000A000C, 0x0 },
 124         { 0x00FFFFFF, 0x0005000F, 0x0 },
 125         { 0x00DB6FFF, 0x000A000C, 0x0 },
 126 };
 127
 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 129         { 0x00FFFFFF, 0x0007000E, 0x0 },
 130         { 0x00D75FFF, 0x000E000A, 0x0 },
 131         { 0x00BEFFFF, 0x00140006, 0x0 },
 132         { 0x80B2CFFF, 0x001B0002, 0x0 },
 133         { 0x00FFFFFF, 0x000E000A, 0x0 },
 134         { 0x00DB6FFF, 0x00160005, 0x0 },
 135         { 0x80C71FFF, 0x001A0002, 0x0 },
 136         { 0x00F7DFFF, 0x00180004, 0x0 },
 137         { 0x80D75FFF, 0x001B0002, 0x0 },
 138 };
 139
 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 141         { 0x00FFFFFF, 0x0001000E, 0x0 },
 142         { 0x00D75FFF, 0x0004000A, 0x0 },
 143         { 0x00C30FFF, 0x00070006, 0x0 },
 144         { 0x00AAAFFF, 0x000C0000, 0x0 },
 145         { 0x00FFFFFF, 0x0004000A, 0x0 },
 146         { 0x00D75FFF, 0x00090004, 0x0 },
 147         { 0x00C30FFF, 0x000C0000, 0x0 },
 148         { 0x00FFFFFF, 0x00070006, 0x0 },
 149         { 0x00D75FFF, 0x000C0000, 0x0 },
 150 };
 151
 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 153                                         /* Idx  NT mV d T mV df db      */
 154         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 155         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 156         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 157         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 158         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 159         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 160         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 161         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 162         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 163         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 164 };
 165
 166 /* Skylake H and S */
 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 168         { 0x00002016, 0x000000A0, 0x0 },
 169         { 0x00005012, 0x0000009B, 0x0 },
 170         { 0x00007011, 0x00000088, 0x0 },
 171         { 0x80009010, 0x000000C0, 0x1 },
 172         { 0x00002016, 0x0000009B, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000C0, 0x1 },
 175         { 0x00002016, 0x000000DF, 0x0 },
 176         { 0x80005012, 0x000000C0, 0x1 },
 177 };
 178
 179 /* Skylake U */
 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 181         { 0x0000201B, 0x000000A2, 0x0 },
 182         { 0x00005012, 0x00000088, 0x0 },
 183         { 0x80007011, 0x000000CD, 0x1 },
 184         { 0x80009010, 0x000000C0, 0x1 },
 185         { 0x0000201B, 0x0000009D, 0x0 },
 186         { 0x80005012, 0x000000C0, 0x1 },
 187         { 0x80007011, 0x000000C0, 0x1 },
 188         { 0x00002016, 0x00000088, 0x0 },
 189         { 0x80005012, 0x000000C0, 0x1 },
 190 };
 191
 192 /* Skylake Y */
 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 194         { 0x00000018, 0x000000A2, 0x0 },
 195         { 0x00005012, 0x00000088, 0x0 },
 196         { 0x80007011, 0x000000CD, 0x3 },
 197         { 0x80009010, 0x000000C0, 0x3 },
 198         { 0x00000018, 0x0000009D, 0x0 },
 199         { 0x80005012, 0x000000C0, 0x3 },
 200         { 0x80007011, 0x000000C0, 0x3 },
 201         { 0x00000018, 0x00000088, 0x0 },
 202         { 0x80005012, 0x000000C0, 0x3 },
 203 };
 204
 205 /* Kabylake H and S */
 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 207         { 0x00002016, 0x000000A0, 0x0 },
 208         { 0x00005012, 0x0000009B, 0x0 },
 209         { 0x00007011, 0x00000088, 0x0 },
 210         { 0x80009010, 0x000000C0, 0x1 },
 211         { 0x00002016, 0x0000009B, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000C0, 0x1 },
 214         { 0x00002016, 0x00000097, 0x0 },
 215         { 0x80005012, 0x000000C0, 0x1 },
 216 };
 217
 218 /* Kabylake U */
 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 220         { 0x0000201B, 0x000000A1, 0x0 },
 221         { 0x00005012, 0x00000088, 0x0 },
 222         { 0x80007011, 0x000000CD, 0x3 },
 223         { 0x80009010, 0x000000C0, 0x3 },
 224         { 0x0000201B, 0x0000009D, 0x0 },
 225         { 0x80005012, 0x000000C0, 0x3 },
 226         { 0x80007011, 0x000000C0, 0x3 },
 227         { 0x00002016, 0x0000004F, 0x0 },
 228         { 0x80005012, 0x000000C0, 0x3 },
 229 };
 230
 231 /* Kabylake Y */
 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 233         { 0x00001017, 0x000000A1, 0x0 },
 234         { 0x00005012, 0x00000088, 0x0 },
 235         { 0x80007011, 0x000000CD, 0x3 },
 236         { 0x8000800F, 0x000000C0, 0x3 },
 237         { 0x00001017, 0x0000009D, 0x0 },
 238         { 0x80005012, 0x000000C0, 0x3 },
 239         { 0x80007011, 0x000000C0, 0x3 },
 240         { 0x00001017, 0x0000004C, 0x0 },
 241         { 0x80005012, 0x000000C0, 0x3 },
 242 };
 243
 244 /*
 245  * Skylake/Kabylake H and S
 246  * eDP 1.4 low vswing translation parameters
 247  */
 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 249         { 0x00000018, 0x000000A8, 0x0 },
 250         { 0x00004013, 0x000000A9, 0x0 },
 251         { 0x00007011, 0x000000A2, 0x0 },
 252         { 0x00009010, 0x0000009C, 0x0 },
 253         { 0x00000018, 0x000000A9, 0x0 },
 254         { 0x00006013, 0x000000A2, 0x0 },
 255         { 0x00007011, 0x000000A6, 0x0 },
 256         { 0x00000018, 0x000000AB, 0x0 },
 257         { 0x00007013, 0x0000009F, 0x0 },
 258         { 0x00000018, 0x000000DF, 0x0 },
 259 };
 260
 261 /*
 262  * Skylake/Kabylake U
 263  * eDP 1.4 low vswing translation parameters
 264  */
 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 266         { 0x00000018, 0x000000A8, 0x0 },
 267         { 0x00004013, 0x000000A9, 0x0 },
 268         { 0x00007011, 0x000000A2, 0x0 },
 269         { 0x00009010, 0x0000009C, 0x0 },
 270         { 0x00000018, 0x000000A9, 0x0 },
 271         { 0x00006013, 0x000000A2, 0x0 },
 272         { 0x00007011, 0x000000A6, 0x0 },
 273         { 0x00002016, 0x000000AB, 0x0 },
 274         { 0x00005013, 0x0000009F, 0x0 },
 275         { 0x00000018, 0x000000DF, 0x0 },
 276 };
 277
 278 /*
 279  * Skylake/Kabylake Y
 280  * eDP 1.4 low vswing translation parameters
 281  */
 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 283         { 0x00000018, 0x000000A8, 0x0 },
 284         { 0x00004013, 0x000000AB, 0x0 },
 285         { 0x00007011, 0x000000A4, 0x0 },
 286         { 0x00009010, 0x000000DF, 0x0 },
 287         { 0x00000018, 0x000000AA, 0x0 },
 288         { 0x00006013, 0x000000A4, 0x0 },
 289         { 0x00007011, 0x0000009D, 0x0 },
 290         { 0x00000018, 0x000000A0, 0x0 },
 291         { 0x00006012, 0x000000DF, 0x0 },
 292         { 0x00000018, 0x0000008A, 0x0 },
 293 };
 294
 295 /* Skylake/Kabylake U, H and S */
 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 297         { 0x00000018, 0x000000AC, 0x0 },
 298         { 0x00005012, 0x0000009D, 0x0 },
 299         { 0x00007011, 0x00000088, 0x0 },
 300         { 0x00000018, 0x000000A1, 0x0 },
 301         { 0x00000018, 0x00000098, 0x0 },
 302         { 0x00004013, 0x00000088, 0x0 },
 303         { 0x80006012, 0x000000CD, 0x1 },
 304         { 0x00000018, 0x000000DF, 0x0 },
 305         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 306         { 0x80003015, 0x000000C0, 0x1 },
 307         { 0x80000018, 0x000000C0, 0x1 },
 308 };
 309
 310 /* Skylake/Kabylake Y */
 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 312         { 0x00000018, 0x000000A1, 0x0 },
 313         { 0x00005012, 0x000000DF, 0x0 },
 314         { 0x80007011, 0x000000CB, 0x3 },
 315         { 0x00000018, 0x000000A4, 0x0 },
 316         { 0x00000018, 0x0000009D, 0x0 },
 317         { 0x00004013, 0x00000080, 0x0 },
 318         { 0x80006013, 0x000000C0, 0x3 },
 319         { 0x00000018, 0x0000008A, 0x0 },
 320         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 321         { 0x80003015, 0x000000C0, 0x3 },
 322         { 0x80000018, 0x000000C0, 0x3 },
 323 };
 324
 325 struct bxt_ddi_buf_trans {
 326         u8 margin;      /* swing value */
 327         u8 scale;       /* scale value */
 328         u8 enable;      /* scale enable */
 329         u8 deemphasis;
 330 };
 331
 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 333                                         /* Idx  NT mV diff      db  */
 334         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 335         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 336         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 337         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 338         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 339         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 340         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 341         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 342         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 343         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 344 };
 345
 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 347                                         /* Idx  NT mV diff      db  */
 348         { 26, 0, 0, 128, },     /* 0:   200             0   */
 349         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 350         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 351         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 352         { 32, 0, 0, 128, },     /* 4:   250             0   */
 353         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 354         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 355         { 43, 0, 0, 128, },     /* 7:   300             0   */
 356         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 357         { 48, 0, 0, 128, },     /* 9:   300             0   */
 358 };
 359
 360 /* BSpec has 2 recommended values - entries 0 and 8.
 361  * Using the entry with higher vswing.
 362  */
 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 364                                         /* Idx  NT mV diff      db  */
 365         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 366         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 367         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 368         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 369         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 370         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 371         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 372         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 373         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 374         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 375 };
 376
 377 struct cnl_ddi_buf_trans {
 378         u8 dw2_swing_sel;
 379         u8 dw7_n_scalar;
 380         u8 dw4_cursor_coeff;
 381         u8 dw4_post_cursor_2;
 382         u8 dw4_post_cursor_1;
 383 };
 384
 385 /* Voltage Swing Programming for VccIO 0.85V for DP */
 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 387                                                 /* NT mV Trans mV db    */
 388         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 389         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 390         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 391         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 392         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 393         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 394         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 395         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 396         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 397         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 398 };
 399
 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 402                                                 /* NT mV Trans mV db    */
 403         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 404         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 405         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 406         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 407         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 408         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 409         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 410 };
 411
 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 414                                                 /* NT mV Trans mV db    */
 415         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 416         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 417         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 418         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 419         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 420         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 421         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 422         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 423         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424 };
 425
 426 /* Voltage Swing Programming for VccIO 0.95V for DP */
 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 428                                                 /* NT mV Trans mV db    */
 429         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 430         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 431         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 432         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 433         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 434         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 435         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 436         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 437         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 438         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 439 };
 440
 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 443                                                 /* NT mV Trans mV db    */
 444         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 445         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 446         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 447         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 448         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 449         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 450         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 451         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 452         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 453         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 454         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 455 };
 456
 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 459                                                 /* NT mV Trans mV db    */
 460         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 461         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 462         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 463         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 464         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 465         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 466         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 467         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 468         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 469         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470 };
 471
 472 /* Voltage Swing Programming for VccIO 1.05V for DP */
 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 474                                                 /* NT mV Trans mV db    */
 475         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 476         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 477         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 478         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 479         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 480         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 481         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 482         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 483         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 484         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 485 };
 486
 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 489                                                 /* NT mV Trans mV db    */
 490         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 491         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 492         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 493         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 494         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 495         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 496         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 497         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 498         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 499         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 500         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 501 };
 502
 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 505                                                 /* NT mV Trans mV db    */
 506         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 507         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 508         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 509         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 510         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 511         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 512         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 513         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 514         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 515 };
 516
 517 /* icl_combo_phy_ddi_translations */
 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 519                                                 /* NT mV Trans mV db    */
 520         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 521         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 522         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 523         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 524         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 525         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 526         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 527         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 528         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 529         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 530 };
 531
 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 533                                                 /* NT mV Trans mV db    */
 534         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 535         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 536         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 537         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 538         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 539         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 540         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 541         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 542         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 543         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 544 };
 545
 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 547                                                 /* NT mV Trans mV db    */
 548         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 549         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 550         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 551         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 552         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 553         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 554         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 555         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 556         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 557         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 558 };
 559
 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 561                                                 /* NT mV Trans mV db    */
 562         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 563         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 564         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 565         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 566         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 567         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 568         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 569 };
 570
 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 572                                                 /* NT mV Trans mV db    */
 573         { 0xA, 0x33, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 574         { 0xA, 0x47, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 575         { 0xC, 0x64, 0x30, 0x00, 0x0F },        /* 350   700      6.0   */
 576         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 350   900      8.2   */
 577         { 0xA, 0x46, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 578         { 0xC, 0x64, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 579         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 580         { 0xC, 0x61, 0x3F, 0x00, 0x00 },        /* 650   700      0.6   */
 581         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 600   900      3.5   */
 582         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 583 };
 584
 585 struct icl_mg_phy_ddi_buf_trans {
 586         u32 cri_txdeemph_override_11_6;
 587         u32 cri_txdeemph_override_5_0;
 588         u32 cri_txdeemph_override_17_12;
 589 };
 590
 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
 592                                 /* Voltage swing  pre-emphasis */
 593         { 0x18, 0x00, 0x00 },   /* 0              0   */
 594         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 595         { 0x24, 0x00, 0x0C },   /* 0              2   */
 596         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 597         { 0x21, 0x00, 0x00 },   /* 1              0   */
 598         { 0x2B, 0x00, 0x08 },   /* 1              1   */
 599         { 0x30, 0x00, 0x0F },   /* 1              2   */
 600         { 0x31, 0x00, 0x03 },   /* 2              0   */
 601         { 0x34, 0x00, 0x0B },   /* 2              1   */
 602         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 603 };
 604
 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
 606                                 /* Voltage swing  pre-emphasis */
 607         { 0x18, 0x00, 0x00 },   /* 0              0   */
 608         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 609         { 0x24, 0x00, 0x0C },   /* 0              2   */
 610         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 611         { 0x26, 0x00, 0x00 },   /* 1              0   */
 612         { 0x2C, 0x00, 0x07 },   /* 1              1   */
 613         { 0x33, 0x00, 0x0C },   /* 1              2   */
 614         { 0x2E, 0x00, 0x00 },   /* 2              0   */
 615         { 0x36, 0x00, 0x09 },   /* 2              1   */
 616         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 617 };
 618
 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
 620                                 /* HDMI Preset  VS      Pre-emph */
 621         { 0x1A, 0x0, 0x0 },     /* 1            400mV   0dB */
 622         { 0x20, 0x0, 0x0 },     /* 2            500mV   0dB */
 623         { 0x29, 0x0, 0x0 },     /* 3            650mV   0dB */
 624         { 0x32, 0x0, 0x0 },     /* 4            800mV   0dB */
 625         { 0x3F, 0x0, 0x0 },     /* 5            1000mV  0dB */
 626         { 0x3A, 0x0, 0x5 },     /* 6            Full    -1.5 dB */
 627         { 0x39, 0x0, 0x6 },     /* 7            Full    -1.8 dB */
 628         { 0x38, 0x0, 0x7 },     /* 8            Full    -2 dB */
 629         { 0x37, 0x0, 0x8 },     /* 9            Full    -2.5 dB */
 630         { 0x36, 0x0, 0x9 },     /* 10           Full    -3 dB */
 631 };
 632
 633 struct tgl_dkl_phy_ddi_buf_trans {
 634         u32 dkl_vswing_control;
 635         u32 dkl_preshoot_control;
 636         u32 dkl_de_emphasis_control;
 637 };
 638
 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
 640                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 641         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 642         { 0x5, 0x0, 0x03 },     /* 0    1       400mV           3.5 dB */
 643         { 0x2, 0x0, 0x0b },     /* 0    2       400mV           6 dB */
 644         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 645         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 646         { 0x2, 0x0, 0x03 },     /* 1    1       600mV           3.5 dB */
 647         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 648         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 649         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 650         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 651 };
 652
 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
 654                                 /* HDMI Preset  VS      Pre-emph */
 655         { 0x7, 0x0, 0x0 },      /* 1            400mV   0dB */
 656         { 0x6, 0x0, 0x0 },      /* 2            500mV   0dB */
 657         { 0x4, 0x0, 0x0 },      /* 3            650mV   0dB */
 658         { 0x2, 0x0, 0x0 },      /* 4            800mV   0dB */
 659         { 0x0, 0x0, 0x0 },      /* 5            1000mV  0dB */
 660         { 0x0, 0x0, 0x5 },      /* 6            Full    -1.5 dB */
 661         { 0x0, 0x0, 0x6 },      /* 7            Full    -1.8 dB */
 662         { 0x0, 0x0, 0x7 },      /* 8            Full    -2 dB */
 663         { 0x0, 0x0, 0x8 },      /* 9            Full    -2.5 dB */
 664         { 0x0, 0x0, 0xA },      /* 10           Full    -3 dB */
 665 };
 666
 667 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
 668                                                 /* NT mV Trans mV db    */
 669         { 0xA, 0x32, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 670         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 671         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 672         { 0x6, 0x7D, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 673         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 674         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 675         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 676         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 677         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 678         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 679 };
 680
 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
 682                                                 /* NT mV Trans mV db    */
 683         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 684         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 685         { 0xC, 0x63, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 686         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 687         { 0xA, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 688         { 0xC, 0x63, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 689         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 690         { 0xC, 0x61, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 691         { 0x6, 0x7B, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 692         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 693 };
 694
 695 static const struct ddi_buf_trans *
 696 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 697 {
 698         if (dev_priv->vbt.edp.low_vswing) {
 699                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 700                 return bdw_ddi_translations_edp;
 701         } else {
 702                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 703                 return bdw_ddi_translations_dp;
 704         }
 705 }
 706
 707 static const struct ddi_buf_trans *
 708 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 709 {
 710         if (IS_SKL_ULX(dev_priv)) {
 711                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 712                 return skl_y_ddi_translations_dp;
 713         } else if (IS_SKL_ULT(dev_priv)) {
 714                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 715                 return skl_u_ddi_translations_dp;
 716         } else {
 717                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 718                 return skl_ddi_translations_dp;
 719         }
 720 }
 721
 722 static const struct ddi_buf_trans *
 723 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 724 {
 725         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 726                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 727                 return kbl_y_ddi_translations_dp;
 728         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 729                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 730                 return kbl_u_ddi_translations_dp;
 731         } else {
 732                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 733                 return kbl_ddi_translations_dp;
 734         }
 735 }
 736
 737 static const struct ddi_buf_trans *
 738 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 739 {
 740         if (dev_priv->vbt.edp.low_vswing) {
 741                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 742                     IS_CFL_ULX(dev_priv)) {
 743                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 744                         return skl_y_ddi_translations_edp;
 745                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 746                            IS_CFL_ULT(dev_priv)) {
 747                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 748                         return skl_u_ddi_translations_edp;
 749                 } else {
 750                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 751                         return skl_ddi_translations_edp;
 752                 }
 753         }
 754
 755         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 756                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 757         else
 758                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 759 }
 760
 761 static const struct ddi_buf_trans *
 762 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 763 {
 764         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 765             IS_CFL_ULX(dev_priv)) {
 766                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 767                 return skl_y_ddi_translations_hdmi;
 768         } else {
 769                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 770                 return skl_ddi_translations_hdmi;
 771         }
 772 }
 773
 774 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 775 {
 776         /* Only DDIA and DDIE can select the 10th register with DP */
 777         if (port == PORT_A || port == PORT_E)
 778                 return min(n_entries, 10);
 779         else
 780                 return min(n_entries, 9);
 781 }
 782
 783 static const struct ddi_buf_trans *
 784 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 785                            enum port port, int *n_entries)
 786 {
 787         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 788                 const struct ddi_buf_trans *ddi_translations =
 789                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 790                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 791                 return ddi_translations;
 792         } else if (IS_SKYLAKE(dev_priv)) {
 793                 const struct ddi_buf_trans *ddi_translations =
 794                         skl_get_buf_trans_dp(dev_priv, n_entries);
 795                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 796                 return ddi_translations;
 797         } else if (IS_BROADWELL(dev_priv)) {
 798                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 799                 return  bdw_ddi_translations_dp;
 800         } else if (IS_HASWELL(dev_priv)) {
 801                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 802                 return hsw_ddi_translations_dp;
 803         }
 804
 805         *n_entries = 0;
 806         return NULL;
 807 }
 808
 809 static const struct ddi_buf_trans *
 810 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 811                             enum port port, int *n_entries)
 812 {
 813         if (IS_GEN9_BC(dev_priv)) {
 814                 const struct ddi_buf_trans *ddi_translations =
 815                         skl_get_buf_trans_edp(dev_priv, n_entries);
 816                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 817                 return ddi_translations;
 818         } else if (IS_BROADWELL(dev_priv)) {
 819                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 820         } else if (IS_HASWELL(dev_priv)) {
 821                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 822                 return hsw_ddi_translations_dp;
 823         }
 824
 825         *n_entries = 0;
 826         return NULL;
 827 }
 828
 829 static const struct ddi_buf_trans *
 830 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 831                             int *n_entries)
 832 {
 833         if (IS_BROADWELL(dev_priv)) {
 834                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 835                 return bdw_ddi_translations_fdi;
 836         } else if (IS_HASWELL(dev_priv)) {
 837                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 838                 return hsw_ddi_translations_fdi;
 839         }
 840
 841         *n_entries = 0;
 842         return NULL;
 843 }
 844
 845 static const struct ddi_buf_trans *
 846 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 847                              int *n_entries)
 848 {
 849         if (IS_GEN9_BC(dev_priv)) {
 850                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 851         } else if (IS_BROADWELL(dev_priv)) {
 852                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 853                 return bdw_ddi_translations_hdmi;
 854         } else if (IS_HASWELL(dev_priv)) {
 855                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 856                 return hsw_ddi_translations_hdmi;
 857         }
 858
 859         *n_entries = 0;
 860         return NULL;
 861 }
 862
 863 static const struct bxt_ddi_buf_trans *
 864 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 865 {
 866         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 867         return bxt_ddi_translations_dp;
 868 }
 869
 870 static const struct bxt_ddi_buf_trans *
 871 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 872 {
 873         if (dev_priv->vbt.edp.low_vswing) {
 874                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 875                 return bxt_ddi_translations_edp;
 876         }
 877
 878         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 879 }
 880
 881 static const struct bxt_ddi_buf_trans *
 882 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 883 {
 884         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 885         return bxt_ddi_translations_hdmi;
 886 }
 887
 888 static const struct cnl_ddi_buf_trans *
 889 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 890 {
 891         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 892
 893         if (voltage == VOLTAGE_INFO_0_85V) {
 894                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 895                 return cnl_ddi_translations_hdmi_0_85V;
 896         } else if (voltage == VOLTAGE_INFO_0_95V) {
 897                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 898                 return cnl_ddi_translations_hdmi_0_95V;
 899         } else if (voltage == VOLTAGE_INFO_1_05V) {
 900                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 901                 return cnl_ddi_translations_hdmi_1_05V;
 902         } else {
 903                 *n_entries = 1; /* shut up gcc */
 904                 MISSING_CASE(voltage);
 905         }
 906         return NULL;
 907 }
 908
 909 static const struct cnl_ddi_buf_trans *
 910 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 911 {
 912         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 913
 914         if (voltage == VOLTAGE_INFO_0_85V) {
 915                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 916                 return cnl_ddi_translations_dp_0_85V;
 917         } else if (voltage == VOLTAGE_INFO_0_95V) {
 918                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 919                 return cnl_ddi_translations_dp_0_95V;
 920         } else if (voltage == VOLTAGE_INFO_1_05V) {
 921                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 922                 return cnl_ddi_translations_dp_1_05V;
 923         } else {
 924                 *n_entries = 1; /* shut up gcc */
 925                 MISSING_CASE(voltage);
 926         }
 927         return NULL;
 928 }
 929
 930 static const struct cnl_ddi_buf_trans *
 931 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 932 {
 933         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 934
 935         if (dev_priv->vbt.edp.low_vswing) {
 936                 if (voltage == VOLTAGE_INFO_0_85V) {
 937                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 938                         return cnl_ddi_translations_edp_0_85V;
 939                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 940                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 941                         return cnl_ddi_translations_edp_0_95V;
 942                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 943                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 944                         return cnl_ddi_translations_edp_1_05V;
 945                 } else {
 946                         *n_entries = 1; /* shut up gcc */
 947                         MISSING_CASE(voltage);
 948                 }
 949                 return NULL;
 950         } else {
 951                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 952         }
 953 }
 954
 955 static const struct cnl_ddi_buf_trans *
 956 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 957                         int *n_entries)
 958 {
 959         if (type == INTEL_OUTPUT_HDMI) {
 960                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 961                 return icl_combo_phy_ddi_translations_hdmi;
 962         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 963                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 964                 return icl_combo_phy_ddi_translations_edp_hbr3;
 965         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 966                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 967                 return icl_combo_phy_ddi_translations_edp_hbr2;
 968         }
 969
 970         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 971         return icl_combo_phy_ddi_translations_dp_hbr2;
 972 }
 973
 974 static const struct icl_mg_phy_ddi_buf_trans *
 975 icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 976                      int *n_entries)
 977 {
 978         if (type == INTEL_OUTPUT_HDMI) {
 979                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
 980                 return icl_mg_phy_ddi_translations_hdmi;
 981         } else if (rate > 270000) {
 982                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
 983                 return icl_mg_phy_ddi_translations_hbr2_hbr3;
 984         }
 985
 986         *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
 987         return icl_mg_phy_ddi_translations_rbr_hbr;
 988 }
 989
 990 static const struct cnl_ddi_buf_trans *
 991 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 992                         int *n_entries)
 993 {
 994         if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
 995                 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
 996                 return ehl_combo_phy_ddi_translations_dp;
 997         }
 998
 999         return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
1000 }
1001
1002 static const struct cnl_ddi_buf_trans *
1003 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
1004                         int *n_entries)
1005 {
1006         if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
1007                 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
1008         } else if (rate > 270000) {
1009                 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1010                 return tgl_combo_phy_ddi_translations_dp_hbr2;
1011         }
1012
1013         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1014         return tgl_combo_phy_ddi_translations_dp_hbr;
1015 }
1016
1017 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
1018 {
1019         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1020         int n_entries, level, default_entry;
1021         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1022
1023         if (INTEL_GEN(dev_priv) >= 12) {
1024                 if (intel_phy_is_combo(dev_priv, phy))
1025                         tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
1026                                                 0, &n_entries);
1027                 else
1028                         n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1029                 default_entry = n_entries - 1;
1030         } else if (INTEL_GEN(dev_priv) == 11) {
1031                 if (intel_phy_is_combo(dev_priv, phy))
1032                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
1033                                                 0, &n_entries);
1034                 else
1035                         icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
1036                                              &n_entries);
1037                 default_entry = n_entries - 1;
1038         } else if (IS_CANNONLAKE(dev_priv)) {
1039                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1040                 default_entry = n_entries - 1;
1041         } else if (IS_GEN9_LP(dev_priv)) {
1042                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1043                 default_entry = n_entries - 1;
1044         } else if (IS_GEN9_BC(dev_priv)) {
1045                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1046                 default_entry = 8;
1047         } else if (IS_BROADWELL(dev_priv)) {
1048                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1049                 default_entry = 7;
1050         } else if (IS_HASWELL(dev_priv)) {
1051                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1052                 default_entry = 6;
1053         } else {
1054                 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1055                 return 0;
1056         }
1057
1058         if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1059                 return 0;
1060
1061         level = intel_bios_hdmi_level_shift(encoder);
1062         if (level < 0)
1063                 level = default_entry;
1064
1065         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1066                 level = n_entries - 1;
1067
1068         return level;
1069 }
1070
1071 /*
1072  * Starting with Haswell, DDI port buffers must be programmed with correct
1073  * values in advance. This function programs the correct values for
1074  * DP/eDP/FDI use cases.
1075  */
1076 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1077                                          const struct intel_crtc_state *crtc_state)
1078 {
1079         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1080         u32 iboost_bit = 0;
1081         int i, n_entries;
1082         enum port port = encoder->port;
1083         const struct ddi_buf_trans *ddi_translations;
1084
1085         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1086                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1087                                                                &n_entries);
1088         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1089                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
1090                                                                &n_entries);
1091         else
1092                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
1093                                                               &n_entries);
1094
1095         /* If we're boosting the current, set bit 31 of trans1 */
1096         if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1097                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1098
1099         for (i = 0; i < n_entries; i++) {
1100                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1101                                ddi_translations[i].trans1 | iboost_bit);
1102                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1103                                ddi_translations[i].trans2);
1104         }
1105 }
1106
1107 /*
1108  * Starting with Haswell, DDI port buffers must be programmed with correct
1109  * values in advance. This function programs the correct values for
1110  * HDMI/DVI use cases.
1111  */
1112 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1113                                            int level)
1114 {
1115         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1116         u32 iboost_bit = 0;
1117         int n_entries;
1118         enum port port = encoder->port;
1119         const struct ddi_buf_trans *ddi_translations;
1120
1121         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1122
1123         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1124                 return;
1125         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1126                 level = n_entries - 1;
1127
1128         /* If we're boosting the current, set bit 31 of trans1 */
1129         if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1130                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1131
1132         /* Entry 9 is for HDMI: */
1133         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1134                        ddi_translations[level].trans1 | iboost_bit);
1135         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1136                        ddi_translations[level].trans2);
1137 }
1138
1139 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1140                                     enum port port)
1141 {
1142         i915_reg_t reg = DDI_BUF_CTL(port);
1143         int i;
1144
1145         for (i = 0; i < 16; i++) {
1146                 udelay(1);
1147                 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
1148                         return;
1149         }
1150         drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
1151                 port_name(port));
1152 }
1153
1154 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1155 {
1156         switch (pll->info->id) {
1157         case DPLL_ID_WRPLL1:
1158                 return PORT_CLK_SEL_WRPLL1;
1159         case DPLL_ID_WRPLL2:
1160                 return PORT_CLK_SEL_WRPLL2;
1161         case DPLL_ID_SPLL:
1162                 return PORT_CLK_SEL_SPLL;
1163         case DPLL_ID_LCPLL_810:
1164                 return PORT_CLK_SEL_LCPLL_810;
1165         case DPLL_ID_LCPLL_1350:
1166                 return PORT_CLK_SEL_LCPLL_1350;
1167         case DPLL_ID_LCPLL_2700:
1168                 return PORT_CLK_SEL_LCPLL_2700;
1169         default:
1170                 MISSING_CASE(pll->info->id);
1171                 return PORT_CLK_SEL_NONE;
1172         }
1173 }
1174
1175 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1176                                   const struct intel_crtc_state *crtc_state)
1177 {
1178         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1179         int clock = crtc_state->port_clock;
1180         const enum intel_dpll_id id = pll->info->id;
1181
1182         switch (id) {
1183         default:
1184                 /*
1185                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1186                  * here, so do warn if this get passed in
1187                  */
1188                 MISSING_CASE(id);
1189                 return DDI_CLK_SEL_NONE;
1190         case DPLL_ID_ICL_TBTPLL:
1191                 switch (clock) {
1192                 case 162000:
1193                         return DDI_CLK_SEL_TBT_162;
1194                 case 270000:
1195                         return DDI_CLK_SEL_TBT_270;
1196                 case 540000:
1197                         return DDI_CLK_SEL_TBT_540;
1198                 case 810000:
1199                         return DDI_CLK_SEL_TBT_810;
1200                 default:
1201                         MISSING_CASE(clock);
1202                         return DDI_CLK_SEL_NONE;
1203                 }
1204         case DPLL_ID_ICL_MGPLL1:
1205         case DPLL_ID_ICL_MGPLL2:
1206         case DPLL_ID_ICL_MGPLL3:
1207         case DPLL_ID_ICL_MGPLL4:
1208         case DPLL_ID_TGL_MGPLL5:
1209         case DPLL_ID_TGL_MGPLL6:
1210                 return DDI_CLK_SEL_MG;
1211         }
1212 }
1213
1214 /* Starting with Haswell, different DDI ports can work in FDI mode for
1215  * connection to the PCH-located connectors. For this, it is necessary to train
1216  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1217  *
1218  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1219  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1220  * DDI A (which is used for eDP)
1221  */
1222
1223 void hsw_fdi_link_train(struct intel_encoder *encoder,
1224                         const struct intel_crtc_state *crtc_state)
1225 {
1226         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1227         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1228         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1229
1230         intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1231
1232         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1233          * mode set "sequence for CRT port" document:
1234          * - TP1 to TP2 time with the default value
1235          * - FDI delay to 90h
1236          *
1237          * WaFDIAutoLinkSetTimingOverrride:hsw
1238          */
1239         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1240                        FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1241
1242         /* Enable the PCH Receiver FDI PLL */
1243         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1244                      FDI_RX_PLL_ENABLE |
1245                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1246         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1247         intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1248         udelay(220);
1249
1250         /* Switch from Rawclk to PCDclk */
1251         rx_ctl_val |= FDI_PCDCLK;
1252         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1253
1254         /* Configure Port Clock Select */
1255         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1256         intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1257         drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1258
1259         /* Start the training iterating through available voltages and emphasis,
1260          * testing each value twice. */
1261         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1262                 /* Configure DP_TP_CTL with auto-training */
1263                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1264                                DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE);
1265
1266                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1267                  * DDI E does not support port reversal, the functionality is
1268                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1269                  * port reversal bit */
1270                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1271                                DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1272                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1273
1274                 udelay(600);
1275
1276                 /* Program PCH FDI Receiver TU */
1277                 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1278
1279                 /* Enable PCH FDI Receiver with auto-training */
1280                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1281                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1282                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1283
1284                 /* Wait for FDI receiver lane calibration */
1285                 udelay(30);
1286
1287                 /* Unset FDI_RX_MISC pwrdn lanes */
1288                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1289                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1290                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1291                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1292
1293                 /* Wait for FDI auto training time */
1294                 udelay(5);
1295
1296                 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1297                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1298                         drm_dbg_kms(&dev_priv->drm,
1299                                     "FDI link training done on step %d\n", i);
1300                         break;
1301                 }
1302
1303                 /*
1304                  * Leave things enabled even if we failed to train FDI.
1305                  * Results in less fireworks from the state checker.
1306                  */
1307                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1308                         drm_err(&dev_priv->drm, "FDI link training failed!\n");
1309                         break;
1310                 }
1311
1312                 rx_ctl_val &= ~FDI_RX_ENABLE;
1313                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1314                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1315
1316                 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1317                 temp &= ~DDI_BUF_CTL_ENABLE;
1318                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1319                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1320
1321                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1322                 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1323                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1324                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1325                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1326                 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1327
1328                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1329
1330                 /* Reset FDI_RX_MISC pwrdn lanes */
1331                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1332                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1333                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1334                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1335                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1336         }
1337
1338         /* Enable normal pixel sending for FDI */
1339         intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1340                        DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE);
1341 }
1342
1343 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1344 {
1345         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1346         struct intel_digital_port *intel_dig_port =
1347                 enc_to_dig_port(encoder);
1348
1349         intel_dp->DP = intel_dig_port->saved_port_bits |
1350                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1351         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1352 }
1353
1354 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1355                                  enum port port)
1356 {
1357         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1358
1359         switch (val) {
1360         case DDI_CLK_SEL_NONE:
1361                 return 0;
1362         case DDI_CLK_SEL_TBT_162:
1363                 return 162000;
1364         case DDI_CLK_SEL_TBT_270:
1365                 return 270000;
1366         case DDI_CLK_SEL_TBT_540:
1367                 return 540000;
1368         case DDI_CLK_SEL_TBT_810:
1369                 return 810000;
1370         default:
1371                 MISSING_CASE(val);
1372                 return 0;
1373         }
1374 }
1375
1376 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1377 {
1378         int dotclock;
1379
1380         if (pipe_config->has_pch_encoder)
1381                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1382                                                     &pipe_config->fdi_m_n);
1383         else if (intel_crtc_has_dp_encoder(pipe_config))
1384                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1385                                                     &pipe_config->dp_m_n);
1386         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1387                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1388         else
1389                 dotclock = pipe_config->port_clock;
1390
1391         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1392             !intel_crtc_has_dp_encoder(pipe_config))
1393                 dotclock *= 2;
1394
1395         if (pipe_config->pixel_multiplier)
1396                 dotclock /= pipe_config->pixel_multiplier;
1397
1398         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1399 }
1400
1401 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1402                                 struct intel_crtc_state *pipe_config)
1403 {
1404         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1405         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1406
1407         if (intel_phy_is_tc(dev_priv, phy) &&
1408             intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1409             DPLL_ID_ICL_TBTPLL)
1410                 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1411                                                                 encoder->port);
1412         else
1413                 pipe_config->port_clock =
1414                         intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
1415
1416         ddi_dotclock_get(pipe_config);
1417 }
1418
1419 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1420                           const struct drm_connector_state *conn_state)
1421 {
1422         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1424         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1425         u32 temp;
1426
1427         if (!intel_crtc_has_dp_encoder(crtc_state))
1428                 return;
1429
1430         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1431
1432         temp = DP_MSA_MISC_SYNC_CLOCK;
1433
1434         switch (crtc_state->pipe_bpp) {
1435         case 18:
1436                 temp |= DP_MSA_MISC_6_BPC;
1437                 break;
1438         case 24:
1439                 temp |= DP_MSA_MISC_8_BPC;
1440                 break;
1441         case 30:
1442                 temp |= DP_MSA_MISC_10_BPC;
1443                 break;
1444         case 36:
1445                 temp |= DP_MSA_MISC_12_BPC;
1446                 break;
1447         default:
1448                 MISSING_CASE(crtc_state->pipe_bpp);
1449                 break;
1450         }
1451
1452         /* nonsense combination */
1453         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1454                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1455
1456         if (crtc_state->limited_color_range)
1457                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1458
1459         /*
1460          * As per DP 1.2 spec section 2.3.4.3 while sending
1461          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1462          * colorspace information.
1463          */
1464         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1465                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1466
1467         /*
1468          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1469          * of Color Encoding Format and Content Color Gamut] while sending
1470          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1471          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1472          */
1473         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1474                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1475
1476         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1477 }
1478
1479 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1480 {
1481         if (master_transcoder == TRANSCODER_EDP)
1482                 return 0;
1483         else
1484                 return master_transcoder + 1;
1485 }
1486
1487 /*
1488  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1489  *
1490  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1491  * intel_ddi_config_transcoder_func().
1492  */
1493 static u32
1494 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
1495                                       const struct intel_crtc_state *crtc_state)
1496 {
1497         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1498         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1499         enum pipe pipe = crtc->pipe;
1500         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1501         enum port port = encoder->port;
1502         u32 temp;
1503
1504         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1505         temp = TRANS_DDI_FUNC_ENABLE;
1506         if (INTEL_GEN(dev_priv) >= 12)
1507                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1508         else
1509                 temp |= TRANS_DDI_SELECT_PORT(port);
1510
1511         switch (crtc_state->pipe_bpp) {
1512         case 18:
1513                 temp |= TRANS_DDI_BPC_6;
1514                 break;
1515         case 24:
1516                 temp |= TRANS_DDI_BPC_8;
1517                 break;
1518         case 30:
1519                 temp |= TRANS_DDI_BPC_10;
1520                 break;
1521         case 36:
1522                 temp |= TRANS_DDI_BPC_12;
1523                 break;
1524         default:
1525                 BUG();
1526         }
1527
1528         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1529                 temp |= TRANS_DDI_PVSYNC;
1530         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1531                 temp |= TRANS_DDI_PHSYNC;
1532
1533         if (cpu_transcoder == TRANSCODER_EDP) {
1534                 switch (pipe) {
1535                 case PIPE_A:
1536                         /* On Haswell, can only use the always-on power well for
1537                          * eDP when not using the panel fitter, and when not
1538                          * using motion blur mitigation (which we don't
1539                          * support). */
1540                         if (crtc_state->pch_pfit.force_thru)
1541                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1542                         else
1543                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1544                         break;
1545                 case PIPE_B:
1546                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1547                         break;
1548                 case PIPE_C:
1549                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1550                         break;
1551                 default:
1552                         BUG();
1553                         break;
1554                 }
1555         }
1556
1557         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1558                 if (crtc_state->has_hdmi_sink)
1559                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1560                 else
1561                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1562
1563                 if (crtc_state->hdmi_scrambling)
1564                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1565                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1566                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1567         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1568                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1569                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1570         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1571                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1572                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1573
1574                 if (INTEL_GEN(dev_priv) >= 12) {
1575                         enum transcoder master;
1576
1577                         master = crtc_state->mst_master_transcoder;
1578                         drm_WARN_ON(&dev_priv->drm,
1579                                     master == INVALID_TRANSCODER);
1580                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1581                 }
1582         } else {
1583                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1584                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1585         }
1586
1587         if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1588             crtc_state->master_transcoder != INVALID_TRANSCODER) {
1589                 u8 master_select =
1590                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1591
1592                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1593                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1594         }
1595
1596         return temp;
1597 }
1598
1599 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
1600                                       const struct intel_crtc_state *crtc_state)
1601 {
1602         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1603         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1604         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1605         u32 ctl;
1606
1607         if (INTEL_GEN(dev_priv) >= 11) {
1608                 enum transcoder master_transcoder = crtc_state->master_transcoder;
1609                 u32 ctl2 = 0;
1610
1611                 if (master_transcoder != INVALID_TRANSCODER) {
1612                         u8 master_select =
1613                                 bdw_trans_port_sync_master_select(master_transcoder);
1614
1615                         ctl2 |= PORT_SYNC_MODE_ENABLE |
1616                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1617                 }
1618
1619                 intel_de_write(dev_priv,
1620                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
1621         }
1622
1623         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
1624         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1625                 ctl |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1626         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1627 }
1628
1629 /*
1630  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1631  * bit.
1632  */
1633 static void
1634 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
1635                                  const struct intel_crtc_state *crtc_state)
1636 {
1637         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1638         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1639         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1640         u32 ctl;
1641
1642         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
1643         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1644         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1645 }
1646
1647 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1648 {
1649         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1650         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1651         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1652         u32 ctl;
1653
1654         if (INTEL_GEN(dev_priv) >= 11)
1655                 intel_de_write(dev_priv,
1656                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
1657
1658         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1659
1660         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1661
1662         if (IS_GEN_RANGE(dev_priv, 8, 10))
1663                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
1664                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
1665
1666         if (INTEL_GEN(dev_priv) >= 12) {
1667                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
1668                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
1669                                  TRANS_DDI_MODE_SELECT_MASK);
1670                 }
1671         } else {
1672                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
1673         }
1674
1675         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1676
1677         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1678             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1679                 drm_dbg_kms(&dev_priv->drm,
1680                             "Quirk Increase DDI disabled time\n");
1681                 /* Quirk time at 100ms for reliable operation */
1682                 msleep(100);
1683         }
1684 }
1685
1686 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1687                                      bool enable)
1688 {
1689         struct drm_device *dev = intel_encoder->base.dev;
1690         struct drm_i915_private *dev_priv = to_i915(dev);
1691         intel_wakeref_t wakeref;
1692         enum pipe pipe = 0;
1693         int ret = 0;
1694         u32 tmp;
1695
1696         wakeref = intel_display_power_get_if_enabled(dev_priv,
1697                                                      intel_encoder->power_domain);
1698         if (drm_WARN_ON(dev, !wakeref))
1699                 return -ENXIO;
1700
1701         if (drm_WARN_ON(dev,
1702                         !intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1703                 ret = -EIO;
1704                 goto out;
1705         }
1706
1707         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe));
1708         if (enable)
1709                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1710         else
1711                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1712         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp);
1713 out:
1714         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1715         return ret;
1716 }
1717
1718 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1719 {
1720         struct drm_device *dev = intel_connector->base.dev;
1721         struct drm_i915_private *dev_priv = to_i915(dev);
1722         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1723         int type = intel_connector->base.connector_type;
1724         enum port port = encoder->port;
1725         enum transcoder cpu_transcoder;
1726         intel_wakeref_t wakeref;
1727         enum pipe pipe = 0;
1728         u32 tmp;
1729         bool ret;
1730
1731         wakeref = intel_display_power_get_if_enabled(dev_priv,
1732                                                      encoder->power_domain);
1733         if (!wakeref)
1734                 return false;
1735
1736         if (!encoder->get_hw_state(encoder, &pipe)) {
1737                 ret = false;
1738                 goto out;
1739         }
1740
1741         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
1742                 cpu_transcoder = TRANSCODER_EDP;
1743         else
1744                 cpu_transcoder = (enum transcoder) pipe;
1745
1746         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1747
1748         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1749         case TRANS_DDI_MODE_SELECT_HDMI:
1750         case TRANS_DDI_MODE_SELECT_DVI:
1751                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1752                 break;
1753
1754         case TRANS_DDI_MODE_SELECT_DP_SST:
1755                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1756                       type == DRM_MODE_CONNECTOR_DisplayPort;
1757                 break;
1758
1759         case TRANS_DDI_MODE_SELECT_DP_MST:
1760                 /* if the transcoder is in MST state then
1761                  * connector isn't connected */
1762                 ret = false;
1763                 break;
1764
1765         case TRANS_DDI_MODE_SELECT_FDI:
1766                 ret = type == DRM_MODE_CONNECTOR_VGA;
1767                 break;
1768
1769         default:
1770                 ret = false;
1771                 break;
1772         }
1773
1774 out:
1775         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1776
1777         return ret;
1778 }
1779
1780 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1781                                         u8 *pipe_mask, bool *is_dp_mst)
1782 {
1783         struct drm_device *dev = encoder->base.dev;
1784         struct drm_i915_private *dev_priv = to_i915(dev);
1785         enum port port = encoder->port;
1786         intel_wakeref_t wakeref;
1787         enum pipe p;
1788         u32 tmp;
1789         u8 mst_pipe_mask;
1790
1791         *pipe_mask = 0;
1792         *is_dp_mst = false;
1793
1794         wakeref = intel_display_power_get_if_enabled(dev_priv,
1795                                                      encoder->power_domain);
1796         if (!wakeref)
1797                 return;
1798
1799         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1800         if (!(tmp & DDI_BUF_CTL_ENABLE))
1801                 goto out;
1802
1803         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
1804                 tmp = intel_de_read(dev_priv,
1805                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1806
1807                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1808                 default:
1809                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1810                         /* fallthrough */
1811                 case TRANS_DDI_EDP_INPUT_A_ON:
1812                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1813                         *pipe_mask = BIT(PIPE_A);
1814                         break;
1815                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1816                         *pipe_mask = BIT(PIPE_B);
1817                         break;
1818                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1819                         *pipe_mask = BIT(PIPE_C);
1820                         break;
1821                 }
1822
1823                 goto out;
1824         }
1825
1826         mst_pipe_mask = 0;
1827         for_each_pipe(dev_priv, p) {
1828                 enum transcoder cpu_transcoder = (enum transcoder)p;
1829                 unsigned int port_mask, ddi_select;
1830                 intel_wakeref_t trans_wakeref;
1831
1832                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
1833                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1834                 if (!trans_wakeref)
1835                         continue;
1836
1837                 if (INTEL_GEN(dev_priv) >= 12) {
1838                         port_mask = TGL_TRANS_DDI_PORT_MASK;
1839                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
1840                 } else {
1841                         port_mask = TRANS_DDI_PORT_MASK;
1842                         ddi_select = TRANS_DDI_SELECT_PORT(port);
1843                 }
1844
1845                 tmp = intel_de_read(dev_priv,
1846                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
1847                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
1848                                         trans_wakeref);
1849
1850                 if ((tmp & port_mask) != ddi_select)
1851                         continue;
1852
1853                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1854                     TRANS_DDI_MODE_SELECT_DP_MST)
1855                         mst_pipe_mask |= BIT(p);
1856
1857                 *pipe_mask |= BIT(p);
1858         }
1859
1860         if (!*pipe_mask)
1861                 drm_dbg_kms(&dev_priv->drm,
1862                             "No pipe for [ENCODER:%d:%s] found\n",
1863                             encoder->base.base.id, encoder->base.name);
1864
1865         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1866                 drm_dbg_kms(&dev_priv->drm,
1867                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
1868                             encoder->base.base.id, encoder->base.name,
1869                             *pipe_mask);
1870                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
1871         }
1872
1873         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
1874                 drm_dbg_kms(&dev_priv->drm,
1875                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
1876                             encoder->base.base.id, encoder->base.name,
1877                             *pipe_mask, mst_pipe_mask);
1878         else
1879                 *is_dp_mst = mst_pipe_mask;
1880
1881 out:
1882         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
1883                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
1884                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1885                             BXT_PHY_LANE_POWERDOWN_ACK |
1886                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1887                         drm_err(&dev_priv->drm,
1888                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
1889                                 encoder->base.base.id, encoder->base.name, tmp);
1890         }
1891
1892         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1893 }
1894
1895 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1896                             enum pipe *pipe)
1897 {
1898         u8 pipe_mask;
1899         bool is_mst;
1900
1901         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
1902
1903         if (is_mst || !pipe_mask)
1904                 return false;
1905
1906         *pipe = ffs(pipe_mask) - 1;
1907
1908         return true;
1909 }
1910
1911 static enum intel_display_power_domain
1912 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
1913 {
1914         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
1915          * DC states enabled at the same time, while for driver initiated AUX
1916          * transfers we need the same AUX IOs to be powered but with DC states
1917          * disabled. Accordingly use the AUX power domain here which leaves DC
1918          * states enabled.
1919          * However, for non-A AUX ports the corresponding non-EDP transcoders
1920          * would have already enabled power well 2 and DC_OFF. This means we can
1921          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
1922          * specific AUX_IO reference without powering up any extra wells.
1923          * Note that PSR is enabled only on Port A even though this function
1924          * returns the correct domain for other ports too.
1925          */
1926         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
1927                                               intel_aux_power_domain(dig_port);
1928 }
1929
1930 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
1931                                         struct intel_crtc_state *crtc_state)
1932 {
1933         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1934         struct intel_digital_port *dig_port;
1935         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1936
1937         /*
1938          * TODO: Add support for MST encoders. Atm, the following should never
1939          * happen since fake-MST encoders don't set their get_power_domains()
1940          * hook.
1941          */
1942         if (drm_WARN_ON(&dev_priv->drm,
1943                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
1944                 return;
1945
1946         dig_port = enc_to_dig_port(encoder);
1947
1948         if (!intel_phy_is_tc(dev_priv, phy) ||
1949             dig_port->tc_mode != TC_PORT_TBT_ALT)
1950                 intel_display_power_get(dev_priv,
1951                                         dig_port->ddi_io_power_domain);
1952
1953         /*
1954          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
1955          * ports.
1956          */
1957         if (intel_crtc_has_dp_encoder(crtc_state) ||
1958             intel_phy_is_tc(dev_priv, phy))
1959                 intel_display_power_get(dev_priv,
1960                                         intel_ddi_main_link_aux_domain(dig_port));
1961
1962         /*
1963          * VDSC power is needed when DSC is enabled
1964          */
1965         if (crtc_state->dsc.compression_enable)
1966                 intel_display_power_get(dev_priv,
1967                                         intel_dsc_power_domain(crtc_state));
1968 }
1969
1970 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
1971                                  const struct intel_crtc_state *crtc_state)
1972 {
1973         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1974         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1975         enum port port = encoder->port;
1976         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1977
1978         if (cpu_transcoder != TRANSCODER_EDP) {
1979                 if (INTEL_GEN(dev_priv) >= 12)
1980                         intel_de_write(dev_priv,
1981                                        TRANS_CLK_SEL(cpu_transcoder),
1982                                        TGL_TRANS_CLK_SEL_PORT(port));
1983                 else
1984                         intel_de_write(dev_priv,
1985                                        TRANS_CLK_SEL(cpu_transcoder),
1986                                        TRANS_CLK_SEL_PORT(port));
1987         }
1988 }
1989
1990 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1991 {
1992         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1993         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1994
1995         if (cpu_transcoder != TRANSCODER_EDP) {
1996                 if (INTEL_GEN(dev_priv) >= 12)
1997                         intel_de_write(dev_priv,
1998                                        TRANS_CLK_SEL(cpu_transcoder),
1999                                        TGL_TRANS_CLK_SEL_DISABLED);
2000                 else
2001                         intel_de_write(dev_priv,
2002                                        TRANS_CLK_SEL(cpu_transcoder),
2003                                        TRANS_CLK_SEL_DISABLED);
2004         }
2005 }
2006
2007 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2008                                 enum port port, u8 iboost)
2009 {
2010         u32 tmp;
2011
2012         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2013         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2014         if (iboost)
2015                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2016         else
2017                 tmp |= BALANCE_LEG_DISABLE(port);
2018         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2019 }
2020
2021 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2022                                int level, enum intel_output_type type)
2023 {
2024         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2025         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2026         enum port port = encoder->port;
2027         u8 iboost;
2028
2029         if (type == INTEL_OUTPUT_HDMI)
2030                 iboost = intel_bios_hdmi_boost_level(encoder);
2031         else
2032                 iboost = intel_bios_dp_boost_level(encoder);
2033
2034         if (iboost == 0) {
2035                 const struct ddi_buf_trans *ddi_translations;
2036                 int n_entries;
2037
2038                 if (type == INTEL_OUTPUT_HDMI)
2039                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2040                 else if (type == INTEL_OUTPUT_EDP)
2041                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2042                 else
2043                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2044
2045                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2046                         return;
2047                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2048                         level = n_entries - 1;
2049
2050                 iboost = ddi_translations[level].i_boost;
2051         }
2052
2053         /* Make sure that the requested I_boost is valid */
2054         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2055                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2056                 return;
2057         }
2058
2059         _skl_ddi_set_iboost(dev_priv, port, iboost);
2060
2061         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2062                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2063 }
2064
2065 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2066                                     int level, enum intel_output_type type)
2067 {
2068         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2069         const struct bxt_ddi_buf_trans *ddi_translations;
2070         enum port port = encoder->port;
2071         int n_entries;
2072
2073         if (type == INTEL_OUTPUT_HDMI)
2074                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2075         else if (type == INTEL_OUTPUT_EDP)
2076                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2077         else
2078                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2079
2080         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2081                 return;
2082         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2083                 level = n_entries - 1;
2084
2085         bxt_ddi_phy_set_signal_level(dev_priv, port,
2086                                      ddi_translations[level].margin,
2087                                      ddi_translations[level].scale,
2088                                      ddi_translations[level].enable,
2089                                      ddi_translations[level].deemphasis);
2090 }
2091
2092 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2093 {
2094         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2095         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2096         enum port port = encoder->port;
2097         enum phy phy = intel_port_to_phy(dev_priv, port);
2098         int n_entries;
2099
2100         if (INTEL_GEN(dev_priv) >= 12) {
2101                 if (intel_phy_is_combo(dev_priv, phy))
2102                         tgl_get_combo_buf_trans(dev_priv, encoder->type,
2103                                                 intel_dp->link_rate, &n_entries);
2104                 else
2105                         n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2106         } else if (INTEL_GEN(dev_priv) == 11) {
2107                 if (IS_ELKHARTLAKE(dev_priv))
2108                         ehl_get_combo_buf_trans(dev_priv, encoder->type,
2109                                                 intel_dp->link_rate, &n_entries);
2110                 else if (intel_phy_is_combo(dev_priv, phy))
2111                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2112                                                 intel_dp->link_rate, &n_entries);
2113                 else
2114                         icl_get_mg_buf_trans(dev_priv, encoder->type,
2115                                              intel_dp->link_rate, &n_entries);
2116         } else if (IS_CANNONLAKE(dev_priv)) {
2117                 if (encoder->type == INTEL_OUTPUT_EDP)
2118                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2119                 else
2120                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2121         } else if (IS_GEN9_LP(dev_priv)) {
2122                 if (encoder->type == INTEL_OUTPUT_EDP)
2123                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2124                 else
2125                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2126         } else {
2127                 if (encoder->type == INTEL_OUTPUT_EDP)
2128                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2129                 else
2130                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2131         }
2132
2133         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2134                 n_entries = 1;
2135         if (drm_WARN_ON(&dev_priv->drm,
2136                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2137                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2138
2139         return index_to_dp_signal_levels[n_entries - 1] &
2140                 DP_TRAIN_VOLTAGE_SWING_MASK;
2141 }
2142
2143 /*
2144  * We assume that the full set of pre-emphasis values can be
2145  * used on all DDI platforms. Should that change we need to
2146  * rethink this code.
2147  */
2148 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2149 {
2150         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2151         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2152                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2153         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2154                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2155         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2156                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2157         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2158         default:
2159                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2160         }
2161 }
2162
2163 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2164                                    int level, enum intel_output_type type)
2165 {
2166         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2167         const struct cnl_ddi_buf_trans *ddi_translations;
2168         enum port port = encoder->port;
2169         int n_entries, ln;
2170         u32 val;
2171
2172         if (type == INTEL_OUTPUT_HDMI)
2173                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2174         else if (type == INTEL_OUTPUT_EDP)
2175                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2176         else
2177                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2178
2179         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2180                 return;
2181         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2182                 level = n_entries - 1;
2183
2184         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2185         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2186         val &= ~SCALING_MODE_SEL_MASK;
2187         val |= SCALING_MODE_SEL(2);
2188         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2189
2190         /* Program PORT_TX_DW2 */
2191         val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2192         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2193                  RCOMP_SCALAR_MASK);
2194         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2195         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2196         /* Rcomp scalar is fixed as 0x98 for every table entry */
2197         val |= RCOMP_SCALAR(0x98);
2198         intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2199
2200         /* Program PORT_TX_DW4 */
2201         /* We cannot write to GRP. It would overrite individual loadgen */
2202         for (ln = 0; ln < 4; ln++) {
2203                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2204                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2205                          CURSOR_COEFF_MASK);
2206                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2207                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2208                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2209                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2210         }
2211
2212         /* Program PORT_TX_DW5 */
2213         /* All DW5 values are fixed for every table entry */
2214         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2215         val &= ~RTERM_SELECT_MASK;
2216         val |= RTERM_SELECT(6);
2217         val |= TAP3_DISABLE;
2218         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2219
2220         /* Program PORT_TX_DW7 */
2221         val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2222         val &= ~N_SCALAR_MASK;
2223         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2224         intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2225 }
2226
2227 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2228                                     int level, enum intel_output_type type)
2229 {
2230         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2231         enum port port = encoder->port;
2232         int width, rate, ln;
2233         u32 val;
2234
2235         if (type == INTEL_OUTPUT_HDMI) {
2236                 width = 4;
2237                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2238         } else {
2239                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2240
2241                 width = intel_dp->lane_count;
2242                 rate = intel_dp->link_rate;
2243         }
2244
2245         /*
2246          * 1. If port type is eDP or DP,
2247          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2248          * else clear to 0b.
2249          */
2250         val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2251         if (type != INTEL_OUTPUT_HDMI)
2252                 val |= COMMON_KEEPER_EN;
2253         else
2254                 val &= ~COMMON_KEEPER_EN;
2255         intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2256
2257         /* 2. Program loadgen select */
2258         /*
2259          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2260          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2261          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2262          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2263          */
2264         for (ln = 0; ln <= 3; ln++) {
2265                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2266                 val &= ~LOADGEN_SELECT;
2267
2268                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2269                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2270                         val |= LOADGEN_SELECT;
2271                 }
2272                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2273         }
2274
2275         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2276         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2277         val |= SUS_CLOCK_CONFIG;
2278         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2279
2280         /* 4. Clear training enable to change swing values */
2281         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2282         val &= ~TX_TRAINING_EN;
2283         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2284
2285         /* 5. Program swing and de-emphasis */
2286         cnl_ddi_vswing_program(encoder, level, type);
2287
2288         /* 6. Set training enable to trigger update */
2289         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2290         val |= TX_TRAINING_EN;
2291         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2292 }
2293
2294 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2295                                         u32 level, enum phy phy, int type,
2296                                         int rate)
2297 {
2298         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2299         u32 n_entries, val;
2300         int ln;
2301
2302         if (INTEL_GEN(dev_priv) >= 12)
2303                 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
2304                                                            &n_entries);
2305         else if (IS_ELKHARTLAKE(dev_priv))
2306                 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
2307                                                            &n_entries);
2308         else
2309                 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2310                                                            &n_entries);
2311         if (!ddi_translations)
2312                 return;
2313
2314         if (level >= n_entries) {
2315                 drm_dbg_kms(&dev_priv->drm,
2316                             "DDI translation not found for level %d. Using %d instead.",
2317                             level, n_entries - 1);
2318                 level = n_entries - 1;
2319         }
2320
2321         /* Set PORT_TX_DW5 */
2322         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2323         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2324                   TAP2_DISABLE | TAP3_DISABLE);
2325         val |= SCALING_MODE_SEL(0x2);
2326         val |= RTERM_SELECT(0x6);
2327         val |= TAP3_DISABLE;
2328         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2329
2330         /* Program PORT_TX_DW2 */
2331         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2332         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2333                  RCOMP_SCALAR_MASK);
2334         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2335         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2336         /* Program Rcomp scalar for every table entry */
2337         val |= RCOMP_SCALAR(0x98);
2338         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2339
2340         /* Program PORT_TX_DW4 */
2341         /* We cannot write to GRP. It would overwrite individual loadgen. */
2342         for (ln = 0; ln <= 3; ln++) {
2343                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2344                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2345                          CURSOR_COEFF_MASK);
2346                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2347                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2348                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2349                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2350         }
2351
2352         /* Program PORT_TX_DW7 */
2353         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2354         val &= ~N_SCALAR_MASK;
2355         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2356         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2357 }
2358
2359 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2360                                               u32 level,
2361                                               enum intel_output_type type)
2362 {
2363         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2364         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2365         int width = 0;
2366         int rate = 0;
2367         u32 val;
2368         int ln = 0;
2369
2370         if (type == INTEL_OUTPUT_HDMI) {
2371                 width = 4;
2372                 /* Rate is always < than 6GHz for HDMI */
2373         } else {
2374                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2375
2376                 width = intel_dp->lane_count;
2377                 rate = intel_dp->link_rate;
2378         }
2379
2380         /*
2381          * 1. If port type is eDP or DP,
2382          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2383          * else clear to 0b.
2384          */
2385         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2386         if (type == INTEL_OUTPUT_HDMI)
2387                 val &= ~COMMON_KEEPER_EN;
2388         else
2389                 val |= COMMON_KEEPER_EN;
2390         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2391
2392         /* 2. Program loadgen select */
2393         /*
2394          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2395          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2396          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2397          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2398          */
2399         for (ln = 0; ln <= 3; ln++) {
2400                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2401                 val &= ~LOADGEN_SELECT;
2402
2403                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2404                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2405                         val |= LOADGEN_SELECT;
2406                 }
2407                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2408         }
2409
2410         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2411         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2412         val |= SUS_CLOCK_CONFIG;
2413         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2414
2415         /* 4. Clear training enable to change swing values */
2416         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2417         val &= ~TX_TRAINING_EN;
2418         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2419
2420         /* 5. Program swing and de-emphasis */
2421         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2422
2423         /* 6. Set training enable to trigger update */
2424         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2425         val |= TX_TRAINING_EN;
2426         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2427 }
2428
2429 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2430                                            int link_clock, u32 level,
2431                                            enum intel_output_type type)
2432 {
2433         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2434         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2435         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2436         u32 n_entries, val;
2437         int ln, rate = 0;
2438
2439         if (type != INTEL_OUTPUT_HDMI) {
2440                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2441
2442                 rate = intel_dp->link_rate;
2443         }
2444
2445         ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate,
2446                                                 &n_entries);
2447         /* The table does not have values for level 3 and level 9. */
2448         if (level >= n_entries || level == 3 || level == 9) {
2449                 drm_dbg_kms(&dev_priv->drm,
2450                             "DDI translation not found for level %d. Using %d instead.",
2451                             level, n_entries - 2);
2452                 level = n_entries - 2;
2453         }
2454
2455         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2456         for (ln = 0; ln < 2; ln++) {
2457                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2458                 val &= ~CRI_USE_FS32;
2459                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2460
2461                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2462                 val &= ~CRI_USE_FS32;
2463                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2464         }
2465
2466         /* Program MG_TX_SWINGCTRL with values from vswing table */
2467         for (ln = 0; ln < 2; ln++) {
2468                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2469                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2470                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2471                         ddi_translations[level].cri_txdeemph_override_17_12);
2472                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2473
2474                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2475                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2476                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2477                         ddi_translations[level].cri_txdeemph_override_17_12);
2478                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2479         }
2480
2481         /* Program MG_TX_DRVCTRL with values from vswing table */
2482         for (ln = 0; ln < 2; ln++) {
2483                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2484                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2485                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2486                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2487                         ddi_translations[level].cri_txdeemph_override_5_0) |
2488                         CRI_TXDEEMPH_OVERRIDE_11_6(
2489                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2490                         CRI_TXDEEMPH_OVERRIDE_EN;
2491                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2492
2493                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2494                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2495                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2496                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2497                         ddi_translations[level].cri_txdeemph_override_5_0) |
2498                         CRI_TXDEEMPH_OVERRIDE_11_6(
2499                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2500                         CRI_TXDEEMPH_OVERRIDE_EN;
2501                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2502
2503                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2504         }
2505
2506         /*
2507          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2508          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2509          * values from table for which TX1 and TX2 enabled.
2510          */
2511         for (ln = 0; ln < 2; ln++) {
2512                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2513                 if (link_clock < 300000)
2514                         val |= CFG_LOW_RATE_LKREN_EN;
2515                 else
2516                         val &= ~CFG_LOW_RATE_LKREN_EN;
2517                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2518         }
2519
2520         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2521         for (ln = 0; ln < 2; ln++) {
2522                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2523                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2524                 if (link_clock <= 500000) {
2525                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2526                 } else {
2527                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2528                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2529                 }
2530                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2531
2532                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2533                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2534                 if (link_clock <= 500000) {
2535                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2536                 } else {
2537                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2538                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2539                 }
2540                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2541         }
2542
2543         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2544         for (ln = 0; ln < 2; ln++) {
2545                 val = intel_de_read(dev_priv,
2546                                     MG_TX1_PISO_READLOAD(ln, tc_port));
2547                 val |= CRI_CALCINIT;
2548                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2549                                val);
2550
2551                 val = intel_de_read(dev_priv,
2552                                     MG_TX2_PISO_READLOAD(ln, tc_port));
2553                 val |= CRI_CALCINIT;
2554                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2555                                val);
2556         }
2557 }
2558
2559 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2560                                     int link_clock,
2561                                     u32 level,
2562                                     enum intel_output_type type)
2563 {
2564         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2565         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2566
2567         if (intel_phy_is_combo(dev_priv, phy))
2568                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2569         else
2570                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
2571                                                type);
2572 }
2573
2574 static void
2575 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2576                                 u32 level)
2577 {
2578         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2579         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2580         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2581         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2582
2583         if (encoder->type == INTEL_OUTPUT_HDMI) {
2584                 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
2585                 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
2586         } else {
2587                 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2588                 ddi_translations = tgl_dkl_phy_dp_ddi_trans;
2589         }
2590
2591         if (level >= n_entries)
2592                 level = n_entries - 1;
2593
2594         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2595                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2596                       DKL_TX_VSWING_CONTROL_MASK);
2597         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2598         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2599         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2600
2601         for (ln = 0; ln < 2; ln++) {
2602                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2603                                HIP_INDEX_VAL(tc_port, ln));
2604
2605                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2606
2607                 /* All the registers are RMW */
2608                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2609                 val &= ~dpcnt_mask;
2610                 val |= dpcnt_val;
2611                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2612
2613                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2614                 val &= ~dpcnt_mask;
2615                 val |= dpcnt_val;
2616                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2617
2618                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2619                 val &= ~DKL_TX_DP20BITMODE;
2620                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2621         }
2622 }
2623
2624 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2625                                     int link_clock,
2626                                     u32 level,
2627                                     enum intel_output_type type)
2628 {
2629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2630         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2631
2632         if (intel_phy_is_combo(dev_priv, phy))
2633                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2634         else
2635                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2636 }
2637
2638 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
2639 {
2640         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2641         int i;
2642
2643         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2644                 if (index_to_dp_signal_levels[i] == signal_levels)
2645                         return i;
2646         }
2647
2648         drm_WARN(&i915->drm, 1,
2649                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2650                  signal_levels);
2651
2652         return 0;
2653 }
2654
2655 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2656 {
2657         u8 train_set = intel_dp->train_set[0];
2658         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2659                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2660
2661         return translate_signal_level(intel_dp, signal_levels);
2662 }
2663
2664 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2665 {
2666         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2667         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2668         struct intel_encoder *encoder = &dport->base;
2669         int level = intel_ddi_dp_level(intel_dp);
2670
2671         if (INTEL_GEN(dev_priv) >= 12)
2672                 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2673                                         level, encoder->type);
2674         else if (INTEL_GEN(dev_priv) >= 11)
2675                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2676                                         level, encoder->type);
2677         else if (IS_CANNONLAKE(dev_priv))
2678                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2679         else
2680                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2681
2682         return 0;
2683 }
2684
2685 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2686 {
2687         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2688         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2689         struct intel_encoder *encoder = &dport->base;
2690         int level = intel_ddi_dp_level(intel_dp);
2691
2692         if (IS_GEN9_BC(dev_priv))
2693                 skl_ddi_set_iboost(encoder, level, encoder->type);
2694
2695         return DDI_BUF_TRANS_SELECT(level);
2696 }
2697
2698 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2699                                      enum phy phy)
2700 {
2701         if (intel_phy_is_combo(dev_priv, phy)) {
2702                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2703         } else if (intel_phy_is_tc(dev_priv, phy)) {
2704                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2705                                                         (enum port)phy);
2706
2707                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2708         }
2709
2710         return 0;
2711 }
2712
2713 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2714                                   const struct intel_crtc_state *crtc_state)
2715 {
2716         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2717         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2718         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2719         u32 val;
2720
2721         mutex_lock(&dev_priv->dpll.lock);
2722
2723         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2724         drm_WARN_ON(&dev_priv->drm,
2725                     (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2726
2727         if (intel_phy_is_combo(dev_priv, phy)) {
2728                 /*
2729                  * Even though this register references DDIs, note that we
2730                  * want to pass the PHY rather than the port (DDI).  For
2731                  * ICL, port=phy in all cases so it doesn't matter, but for
2732                  * EHL the bspec notes the following:
2733                  *
2734                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2735                  *   Clock Select chooses the PLL for both DDIA and DDID and
2736                  *   drives port A in all cases."
2737                  */
2738                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2739                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2740                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2741                 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
2742         }
2743
2744         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2745         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2746
2747         mutex_unlock(&dev_priv->dpll.lock);
2748 }
2749
2750 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2751 {
2752         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2753         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2754         u32 val;
2755
2756         mutex_lock(&dev_priv->dpll.lock);
2757
2758         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2759         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2760         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2761
2762         mutex_unlock(&dev_priv->dpll.lock);
2763 }
2764
2765 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
2766                                       u32 port_mask, bool ddi_clk_needed)
2767 {
2768         enum port port;
2769         u32 val;
2770
2771         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2772         for_each_port_masked(port, port_mask) {
2773                 enum phy phy = intel_port_to_phy(dev_priv, port);
2774                 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
2775                                                                    phy);
2776
2777                 if (ddi_clk_needed == !ddi_clk_off)
2778                         continue;
2779
2780                 /*
2781                  * Punt on the case now where clock is gated, but it would
2782                  * be needed by the port. Something else is really broken then.
2783                  */
2784                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
2785                         continue;
2786
2787                 drm_notice(&dev_priv->drm,
2788                            "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2789                            phy_name(phy));
2790                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2791                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2792         }
2793 }
2794
2795 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2796 {
2797         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2798         u32 port_mask;
2799         bool ddi_clk_needed;
2800
2801         /*
2802          * In case of DP MST, we sanitize the primary encoder only, not the
2803          * virtual ones.
2804          */
2805         if (encoder->type == INTEL_OUTPUT_DP_MST)
2806                 return;
2807
2808         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2809                 u8 pipe_mask;
2810                 bool is_mst;
2811
2812                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2813                 /*
2814                  * In the unlikely case that BIOS enables DP in MST mode, just
2815                  * warn since our MST HW readout is incomplete.
2816                  */
2817                 if (drm_WARN_ON(&dev_priv->drm, is_mst))
2818                         return;
2819         }
2820
2821         port_mask = BIT(encoder->port);
2822         ddi_clk_needed = encoder->base.crtc;
2823
2824         if (encoder->type == INTEL_OUTPUT_DSI) {
2825                 struct intel_encoder *other_encoder;
2826
2827                 port_mask = intel_dsi_encoder_ports(encoder);
2828                 /*
2829                  * Sanity check that we haven't incorrectly registered another
2830                  * encoder using any of the ports of this DSI encoder.
2831                  */
2832                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2833                         if (other_encoder == encoder)
2834                                 continue;
2835
2836                         if (drm_WARN_ON(&dev_priv->drm,
2837                                         port_mask & BIT(other_encoder->port)))
2838                                 return;
2839                 }
2840                 /*
2841                  * For DSI we keep the ddi clocks gated
2842                  * except during enable/disable sequence.
2843                  */
2844                 ddi_clk_needed = false;
2845         }
2846
2847         icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
2848 }
2849
2850 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2851                                  const struct intel_crtc_state *crtc_state)
2852 {
2853         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2854         enum port port = encoder->port;
2855         enum phy phy = intel_port_to_phy(dev_priv, port);
2856         u32 val;
2857         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2858
2859         if (drm_WARN_ON(&dev_priv->drm, !pll))
2860                 return;
2861
2862         mutex_lock(&dev_priv->dpll.lock);
2863
2864         if (INTEL_GEN(dev_priv) >= 11) {
2865                 if (!intel_phy_is_combo(dev_priv, phy))
2866                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2867                                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2868                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2869                         /*
2870                          * MG does not exist but the programming is required
2871                          * to ungate DDIC and DDID
2872                          */
2873                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2874                                        DDI_CLK_SEL_MG);
2875         } else if (IS_CANNONLAKE(dev_priv)) {
2876                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2877                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
2878                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2879                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2880                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
2881
2882                 /*
2883                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2884                  * This step and the step before must be done with separate
2885                  * register writes.
2886                  */
2887                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
2888                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2889                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
2890         } else if (IS_GEN9_BC(dev_priv)) {
2891                 /* DDI -> PLL mapping  */
2892                 val = intel_de_read(dev_priv, DPLL_CTRL2);
2893
2894                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2895                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2896                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2897                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2898
2899                 intel_de_write(dev_priv, DPLL_CTRL2, val);
2900
2901         } else if (INTEL_GEN(dev_priv) < 9) {
2902                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
2903                                hsw_pll_to_ddi_pll_sel(pll));
2904         }
2905
2906         mutex_unlock(&dev_priv->dpll.lock);
2907 }
2908
2909 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2910 {
2911         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2912         enum port port = encoder->port;
2913         enum phy phy = intel_port_to_phy(dev_priv, port);
2914
2915         if (INTEL_GEN(dev_priv) >= 11) {
2916                 if (!intel_phy_is_combo(dev_priv, phy) ||
2917                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
2918                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2919                                        DDI_CLK_SEL_NONE);
2920         } else if (IS_CANNONLAKE(dev_priv)) {
2921                 intel_de_write(dev_priv, DPCLKA_CFGCR0,
2922                                intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2923         } else if (IS_GEN9_BC(dev_priv)) {
2924                 intel_de_write(dev_priv, DPLL_CTRL2,
2925                                intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
2926         } else if (INTEL_GEN(dev_priv) < 9) {
2927                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
2928                                PORT_CLK_SEL_NONE);
2929         }
2930 }
2931
2932 static void
2933 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
2934                        const struct intel_crtc_state *crtc_state)
2935 {
2936         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2937         enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
2938         u32 ln0, ln1, pin_assignment;
2939         u8 width;
2940
2941         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
2942                 return;
2943
2944         if (INTEL_GEN(dev_priv) >= 12) {
2945                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2946                                HIP_INDEX_VAL(tc_port, 0x0));
2947                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2948                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2949                                HIP_INDEX_VAL(tc_port, 0x1));
2950                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2951         } else {
2952                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2953                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2954         }
2955
2956         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
2957         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2958
2959         /* DPPATC */
2960         pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
2961         width = crtc_state->lane_count;
2962
2963         switch (pin_assignment) {
2964         case 0x0:
2965                 drm_WARN_ON(&dev_priv->drm,
2966                             intel_dig_port->tc_mode != TC_PORT_LEGACY);
2967                 if (width == 1) {
2968                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2969                 } else {
2970                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2971                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2972                 }
2973                 break;
2974         case 0x1:
2975                 if (width == 4) {
2976                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2977                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2978                 }
2979                 break;
2980         case 0x2:
2981                 if (width == 2) {
2982                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2983                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2984                 }
2985                 break;
2986         case 0x3:
2987         case 0x5:
2988                 if (width == 1) {
2989                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2990                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2991                 } else {
2992                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2993                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2994                 }
2995                 break;
2996         case 0x4:
2997         case 0x6:
2998                 if (width == 1) {
2999                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3000                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3001                 } else {
3002                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3003                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3004                 }
3005                 break;
3006         default:
3007                 MISSING_CASE(pin_assignment);
3008         }
3009
3010         if (INTEL_GEN(dev_priv) >= 12) {
3011                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3012                                HIP_INDEX_VAL(tc_port, 0x0));
3013                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3014                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3015                                HIP_INDEX_VAL(tc_port, 0x1));
3016                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3017         } else {
3018                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3019                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3020         }
3021 }
3022
3023 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3024                                         const struct intel_crtc_state *crtc_state)
3025 {
3026         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3027
3028         if (!crtc_state->fec_enable)
3029                 return;
3030
3031         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3032                 drm_dbg_kms(&i915->drm,
3033                             "Failed to set FEC_READY in the sink\n");
3034 }
3035
3036 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3037                                  const struct intel_crtc_state *crtc_state)
3038 {
3039         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3040         struct intel_dp *intel_dp;
3041         u32 val;
3042
3043         if (!crtc_state->fec_enable)
3044                 return;
3045
3046         intel_dp = enc_to_intel_dp(encoder);
3047         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3048         val |= DP_TP_CTL_FEC_ENABLE;
3049         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3050
3051         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3052                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3053                 drm_err(&dev_priv->drm,
3054                         "Timed out waiting for FEC Enable Status\n");
3055 }
3056
3057 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3058                                         const struct intel_crtc_state *crtc_state)
3059 {
3060         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3061         struct intel_dp *intel_dp;
3062         u32 val;
3063
3064         if (!crtc_state->fec_enable)
3065                 return;
3066
3067         intel_dp = enc_to_intel_dp(encoder);
3068         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3069         val &= ~DP_TP_CTL_FEC_ENABLE;
3070         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3071         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3072 }
3073
3074 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3075                                   struct intel_encoder *encoder,
3076                                   const struct intel_crtc_state *crtc_state,
3077                                   const struct drm_connector_state *conn_state)
3078 {
3079         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3080         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3081         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3082         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3083         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3084         int level = intel_ddi_dp_level(intel_dp);
3085         enum transcoder transcoder = crtc_state->cpu_transcoder;
3086
3087         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3088                                  crtc_state->lane_count, is_mst);
3089
3090         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3091         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3092
3093         /*
3094          * 1. Enable Power Wells
3095          *
3096          * This was handled at the beginning of intel_atomic_commit_tail(),
3097          * before we called down into this function.
3098          */
3099
3100         /* 2. Enable Panel Power if PPS is required */
3101         intel_edp_panel_on(intel_dp);
3102
3103         /*
3104          * 3. For non-TBT Type-C ports, set FIA lane count
3105          * (DFLEXDPSP.DPX4TXLATC)
3106          *
3107          * This was done before tgl_ddi_pre_enable_dp by
3108          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3109          */
3110
3111         /*
3112          * 4. Enable the port PLL.
3113          *
3114          * The PLL enabling itself was already done before this function by
3115          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
3116          * configure the PLL to port mapping here.
3117          */
3118         intel_ddi_clk_select(encoder, crtc_state);
3119
3120         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3121         if (!intel_phy_is_tc(dev_priv, phy) ||
3122             dig_port->tc_mode != TC_PORT_TBT_ALT)
3123                 intel_display_power_get(dev_priv,
3124                                         dig_port->ddi_io_power_domain);
3125
3126         /* 6. Program DP_MODE */
3127         icl_program_mg_dp_mode(dig_port, crtc_state);
3128
3129         /*
3130          * 7. The rest of the below are substeps under the bspec's "Enable and
3131          * Train Display Port" step.  Note that steps that are specific to
3132          * MST will be handled by intel_mst_pre_enable_dp() before/after it
3133          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
3134          * us when active_mst_links==0, so any steps designated for "single
3135          * stream or multi-stream master transcoder" can just be performed
3136          * unconditionally here.
3137          */
3138
3139         /*
3140          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3141          * Transcoder.
3142          */
3143         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3144
3145         /*
3146          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3147          * Transport Select
3148          */
3149         intel_ddi_config_transcoder_func(encoder, crtc_state);
3150
3151         /*
3152          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3153          * selected
3154          *
3155          * This will be handled by the intel_dp_start_link_train() farther
3156          * down this function.
3157          */
3158
3159         /* 7.e Configure voltage swing and related IO settings */
3160         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3161                                 encoder->type);
3162
3163         /*
3164          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3165          * the used lanes of the DDI.
3166          */
3167         if (intel_phy_is_combo(dev_priv, phy)) {
3168                 bool lane_reversal =
3169                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3170
3171                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3172                                                crtc_state->lane_count,
3173                                                lane_reversal);
3174         }
3175
3176         /*
3177          * 7.g Configure and enable DDI_BUF_CTL
3178          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3179          *     after 500 us.
3180          *
3181          * We only configure what the register value will be here.  Actual
3182          * enabling happens during link training farther down.
3183          */
3184         intel_ddi_init_dp_buf_reg(encoder);
3185
3186         if (!is_mst)
3187                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3188
3189         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3190         /*
3191          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3192          * in the FEC_CONFIGURATION register to 1 before initiating link
3193          * training
3194          */
3195         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3196
3197         /*
3198          * 7.i Follow DisplayPort specification training sequence (see notes for
3199          *     failure handling)
3200          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3201          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3202          *     (timeout after 800 us)
3203          */
3204         intel_dp_start_link_train(intel_dp);
3205
3206         /* 7.k Set DP_TP_CTL link training to Normal */
3207         if (!is_trans_port_sync_mode(crtc_state))
3208                 intel_dp_stop_link_train(intel_dp);
3209
3210         /* 7.l Configure and enable FEC if needed */
3211         intel_ddi_enable_fec(encoder, crtc_state);
3212         intel_dsc_enable(encoder, crtc_state);
3213 }
3214
3215 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3216                                   struct intel_encoder *encoder,
3217                                   const struct intel_crtc_state *crtc_state,
3218                                   const struct drm_connector_state *conn_state)
3219 {
3220         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3221         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3222         enum port port = encoder->port;
3223         enum phy phy = intel_port_to_phy(dev_priv, port);
3224         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3225         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3226         int level = intel_ddi_dp_level(intel_dp);
3227
3228         if (INTEL_GEN(dev_priv) < 11)
3229                 drm_WARN_ON(&dev_priv->drm,
3230                             is_mst && (port == PORT_A || port == PORT_E));
3231         else
3232                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3233
3234         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3235                                  crtc_state->lane_count, is_mst);
3236
3237         intel_edp_panel_on(intel_dp);
3238
3239         intel_ddi_clk_select(encoder, crtc_state);
3240
3241         if (!intel_phy_is_tc(dev_priv, phy) ||
3242             dig_port->tc_mode != TC_PORT_TBT_ALT)
3243                 intel_display_power_get(dev_priv,
3244                                         dig_port->ddi_io_power_domain);
3245
3246         icl_program_mg_dp_mode(dig_port, crtc_state);
3247
3248         if (INTEL_GEN(dev_priv) >= 11)
3249                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3250                                         level, encoder->type);
3251         else if (IS_CANNONLAKE(dev_priv))
3252                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3253         else if (IS_GEN9_LP(dev_priv))
3254                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3255         else
3256                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3257
3258         if (intel_phy_is_combo(dev_priv, phy)) {
3259                 bool lane_reversal =
3260                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3261
3262                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3263                                                crtc_state->lane_count,
3264                                                lane_reversal);
3265         }
3266
3267         intel_ddi_init_dp_buf_reg(encoder);
3268         if (!is_mst)
3269                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3270         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3271                                               true);
3272         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3273         intel_dp_start_link_train(intel_dp);
3274         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3275             !is_trans_port_sync_mode(crtc_state))
3276                 intel_dp_stop_link_train(intel_dp);
3277
3278         intel_ddi_enable_fec(encoder, crtc_state);
3279
3280         if (!is_mst)
3281                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3282
3283         intel_dsc_enable(encoder, crtc_state);
3284 }
3285
3286 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3287                                     struct intel_encoder *encoder,
3288                                     const struct intel_crtc_state *crtc_state,
3289                                     const struct drm_connector_state *conn_state)
3290 {
3291         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3292
3293         if (INTEL_GEN(dev_priv) >= 12)
3294                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3295         else
3296                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3297
3298         /* MST will call a setting of MSA after an allocating of Virtual Channel
3299          * from MST encoder pre_enable callback.
3300          */
3301         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3302                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3303
3304                 intel_dp_set_m_n(crtc_state, M1_N1);
3305         }
3306 }
3307
3308 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3309                                       struct intel_encoder *encoder,
3310                                       const struct intel_crtc_state *crtc_state,
3311                                       const struct drm_connector_state *conn_state)
3312 {
3313         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3314         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3315         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3316         int level = intel_ddi_hdmi_level(encoder);
3317         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3318
3319         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3320         intel_ddi_clk_select(encoder, crtc_state);
3321
3322         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3323
3324         icl_program_mg_dp_mode(dig_port, crtc_state);
3325
3326         if (INTEL_GEN(dev_priv) >= 12)
3327                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3328                                         level, INTEL_OUTPUT_HDMI);
3329         else if (INTEL_GEN(dev_priv) == 11)
3330                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3331                                         level, INTEL_OUTPUT_HDMI);
3332         else if (IS_CANNONLAKE(dev_priv))
3333                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3334         else if (IS_GEN9_LP(dev_priv))
3335                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3336         else
3337                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3338
3339         if (IS_GEN9_BC(dev_priv))
3340                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3341
3342         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3343
3344         intel_dig_port->set_infoframes(encoder,
3345                                        crtc_state->has_infoframe,
3346                                        crtc_state, conn_state);
3347 }
3348
3349 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3350                                  struct intel_encoder *encoder,
3351                                  const struct intel_crtc_state *crtc_state,
3352                                  const struct drm_connector_state *conn_state)
3353 {
3354         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3355         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3356         enum pipe pipe = crtc->pipe;
3357
3358         /*
3359          * When called from DP MST code:
3360          * - conn_state will be NULL
3361          * - encoder will be the main encoder (ie. mst->primary)
3362          * - the main connector associated with this port
3363          *   won't be active or linked to a crtc
3364          * - crtc_state will be the state of the first stream to
3365          *   be activated on this port, and it may not be the same
3366          *   stream that will be deactivated last, but each stream
3367          *   should have a state that is identical when it comes to
3368          *   the DP link parameteres
3369          */
3370
3371         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3372
3373         if (INTEL_GEN(dev_priv) >= 11)
3374                 icl_map_plls_to_ports(encoder, crtc_state);
3375
3376         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3377
3378         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3379                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3380                                           conn_state);
3381         } else {
3382                 struct intel_lspcon *lspcon =
3383                                 enc_to_intel_lspcon(encoder);
3384
3385                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3386                                         conn_state);
3387                 if (lspcon->active) {
3388                         struct intel_digital_port *dig_port =
3389                                         enc_to_dig_port(encoder);
3390
3391                         dig_port->set_infoframes(encoder,
3392                                                  crtc_state->has_infoframe,
3393                                                  crtc_state, conn_state);
3394                 }
3395         }
3396 }
3397
3398 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3399                                   const struct intel_crtc_state *crtc_state)
3400 {
3401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3402         enum port port = encoder->port;
3403         bool wait = false;
3404         u32 val;
3405
3406         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3407         if (val & DDI_BUF_CTL_ENABLE) {
3408                 val &= ~DDI_BUF_CTL_ENABLE;
3409                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3410                 wait = true;
3411         }
3412
3413         if (intel_crtc_has_dp_encoder(crtc_state)) {
3414                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3415
3416                 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3417                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3418                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3419                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3420         }
3421
3422         /* Disable FEC in DP Sink */
3423         intel_ddi_disable_fec_state(encoder, crtc_state);
3424
3425         if (wait)
3426                 intel_wait_ddi_buf_idle(dev_priv, port);
3427 }
3428
3429 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3430                                       struct intel_encoder *encoder,
3431                                       const struct intel_crtc_state *old_crtc_state,
3432                                       const struct drm_connector_state *old_conn_state)
3433 {
3434         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3435         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3436         struct intel_dp *intel_dp = &dig_port->dp;
3437         bool is_mst = intel_crtc_has_type(old_crtc_state,
3438                                           INTEL_OUTPUT_DP_MST);
3439         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3440
3441         /*
3442          * Power down sink before disabling the port, otherwise we end
3443          * up getting interrupts from the sink on detecting link loss.
3444          */
3445         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3446
3447         if (INTEL_GEN(dev_priv) >= 12) {
3448                 if (is_mst) {
3449                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3450                         u32 val;
3451
3452                         val = intel_de_read(dev_priv,
3453                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
3454                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
3455                                  TRANS_DDI_MODE_SELECT_MASK);
3456                         intel_de_write(dev_priv,
3457                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
3458                                        val);
3459                 }
3460         } else {
3461                 if (!is_mst)
3462                         intel_ddi_disable_pipe_clock(old_crtc_state);
3463         }
3464
3465         intel_disable_ddi_buf(encoder, old_crtc_state);
3466
3467         /*
3468          * From TGL spec: "If single stream or multi-stream master transcoder:
3469          * Configure Transcoder Clock select to direct no clock to the
3470          * transcoder"
3471          */
3472         if (INTEL_GEN(dev_priv) >= 12)
3473                 intel_ddi_disable_pipe_clock(old_crtc_state);
3474
3475         intel_edp_panel_vdd_on(intel_dp);
3476         intel_edp_panel_off(intel_dp);
3477
3478         if (!intel_phy_is_tc(dev_priv, phy) ||
3479             dig_port->tc_mode != TC_PORT_TBT_ALT)
3480                 intel_display_power_put_unchecked(dev_priv,
3481                                                   dig_port->ddi_io_power_domain);
3482
3483         intel_ddi_clk_disable(encoder);
3484 }
3485
3486 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3487                                         struct intel_encoder *encoder,
3488                                         const struct intel_crtc_state *old_crtc_state,
3489                                         const struct drm_connector_state *old_conn_state)
3490 {
3491         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3492         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3493         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3494
3495         dig_port->set_infoframes(encoder, false,
3496                                  old_crtc_state, old_conn_state);
3497
3498         intel_ddi_disable_pipe_clock(old_crtc_state);
3499
3500         intel_disable_ddi_buf(encoder, old_crtc_state);
3501
3502         intel_display_power_put_unchecked(dev_priv,
3503                                           dig_port->ddi_io_power_domain);
3504
3505         intel_ddi_clk_disable(encoder);
3506
3507         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3508 }
3509
3510 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3511                                    struct intel_encoder *encoder,
3512                                    const struct intel_crtc_state *old_crtc_state,
3513                                    const struct drm_connector_state *old_conn_state)
3514 {
3515         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3516         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3517         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3518         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3519
3520         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3521                 intel_crtc_vblank_off(old_crtc_state);
3522
3523                 intel_disable_pipe(old_crtc_state);
3524
3525                 intel_ddi_disable_transcoder_func(old_crtc_state);
3526
3527                 intel_dsc_disable(old_crtc_state);
3528
3529                 if (INTEL_GEN(dev_priv) >= 9)
3530                         skl_scaler_disable(old_crtc_state);
3531                 else
3532                         ilk_pfit_disable(old_crtc_state);
3533         }
3534
3535         /*
3536          * When called from DP MST code:
3537          * - old_conn_state will be NULL
3538          * - encoder will be the main encoder (ie. mst->primary)
3539          * - the main connector associated with this port
3540          *   won't be active or linked to a crtc
3541          * - old_crtc_state will be the state of the last stream to
3542          *   be deactivated on this port, and it may not be the same
3543          *   stream that was activated last, but each stream
3544          *   should have a state that is identical when it comes to
3545          *   the DP link parameteres
3546          */
3547
3548         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3549                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3550                                             old_conn_state);
3551         else
3552                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3553                                           old_conn_state);
3554
3555         if (INTEL_GEN(dev_priv) >= 11)
3556                 icl_unmap_plls_to_ports(encoder);
3557
3558         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3559                 intel_display_power_put_unchecked(dev_priv,
3560                                                   intel_ddi_main_link_aux_domain(dig_port));
3561
3562         if (is_tc_port)
3563                 intel_tc_port_put_link(dig_port);
3564 }
3565
3566 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
3567                                 struct intel_encoder *encoder,
3568                                 const struct intel_crtc_state *old_crtc_state,
3569                                 const struct drm_connector_state *old_conn_state)
3570 {
3571         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3572         u32 val;
3573
3574         /*
3575          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3576          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3577          * step 13 is the correct place for it. Step 18 is where it was
3578          * originally before the BUN.
3579          */
3580         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3581         val &= ~FDI_RX_ENABLE;
3582         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3583
3584         intel_disable_ddi_buf(encoder, old_crtc_state);
3585         intel_ddi_clk_disable(encoder);
3586
3587         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3588         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3589         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3590         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3591
3592         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3593         val &= ~FDI_PCDCLK;
3594         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3595
3596         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3597         val &= ~FDI_RX_PLL_ENABLE;
3598         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3599 }
3600
3601 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3602                                             struct intel_encoder *encoder,
3603                                             const struct intel_crtc_state *crtc_state)
3604 {
3605         const struct drm_connector_state *conn_state;
3606         struct drm_connector *conn;
3607         int i;
3608
3609         if (!crtc_state->sync_mode_slaves_mask)
3610                 return;
3611
3612         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3613                 struct intel_encoder *slave_encoder =
3614                         to_intel_encoder(conn_state->best_encoder);
3615                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3616                 const struct intel_crtc_state *slave_crtc_state;
3617
3618                 if (!slave_crtc)
3619                         continue;
3620
3621                 slave_crtc_state =
3622                         intel_atomic_get_new_crtc_state(state, slave_crtc);
3623
3624                 if (slave_crtc_state->master_transcoder !=
3625                     crtc_state->cpu_transcoder)
3626                         continue;
3627
3628                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
3629         }
3630
3631         usleep_range(200, 400);
3632
3633         intel_dp_stop_link_train(enc_to_intel_dp(encoder));
3634 }
3635
3636 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3637                                 struct intel_encoder *encoder,
3638                                 const struct intel_crtc_state *crtc_state,
3639                                 const struct drm_connector_state *conn_state)
3640 {
3641         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3642         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3643         enum port port = encoder->port;
3644
3645         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3646                 intel_dp_stop_link_train(intel_dp);
3647
3648         intel_edp_backlight_on(crtc_state, conn_state);
3649         intel_psr_enable(intel_dp, crtc_state);
3650         intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3651         intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3652         intel_edp_drrs_enable(intel_dp, crtc_state);
3653
3654         if (crtc_state->has_audio)
3655                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3656
3657         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3658 }
3659
3660 static i915_reg_t
3661 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3662                                enum port port)
3663 {
3664         static const enum transcoder trans[] = {
3665                 [PORT_A] = TRANSCODER_EDP,
3666                 [PORT_B] = TRANSCODER_A,
3667                 [PORT_C] = TRANSCODER_B,
3668                 [PORT_D] = TRANSCODER_C,
3669                 [PORT_E] = TRANSCODER_A,
3670         };
3671
3672         drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
3673
3674         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3675                 port = PORT_A;
3676
3677         return CHICKEN_TRANS(trans[port]);
3678 }
3679
3680 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3681                                   struct intel_encoder *encoder,
3682                                   const struct intel_crtc_state *crtc_state,
3683                                   const struct drm_connector_state *conn_state)
3684 {
3685         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3686         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3687         struct drm_connector *connector = conn_state->connector;
3688         enum port port = encoder->port;
3689
3690         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3691                                                crtc_state->hdmi_high_tmds_clock_ratio,
3692                                                crtc_state->hdmi_scrambling))
3693                 drm_dbg_kms(&dev_priv->drm,
3694                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3695                             connector->base.id, connector->name);
3696
3697         /* Display WA #1143: skl,kbl,cfl */
3698         if (IS_GEN9_BC(dev_priv)) {
3699                 /*
3700                  * For some reason these chicken bits have been
3701                  * stuffed into a transcoder register, event though
3702                  * the bits affect a specific DDI port rather than
3703                  * a specific transcoder.
3704                  */
3705                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3706                 u32 val;
3707
3708                 val = intel_de_read(dev_priv, reg);
3709
3710                 if (port == PORT_E)
3711                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3712                                 DDIE_TRAINING_OVERRIDE_VALUE;
3713                 else
3714                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3715                                 DDI_TRAINING_OVERRIDE_VALUE;
3716
3717                 intel_de_write(dev_priv, reg, val);
3718                 intel_de_posting_read(dev_priv, reg);
3719
3720                 udelay(1);
3721
3722                 if (port == PORT_E)
3723                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3724                                  DDIE_TRAINING_OVERRIDE_VALUE);
3725                 else
3726                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3727                                  DDI_TRAINING_OVERRIDE_VALUE);
3728
3729                 intel_de_write(dev_priv, reg, val);
3730         }
3731
3732         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3733          * are ignored so nothing special needs to be done besides
3734          * enabling the port.
3735          */
3736         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3737                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3738
3739         if (crtc_state->has_audio)
3740                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3741 }
3742
3743 static void intel_enable_ddi(struct intel_atomic_state *state,
3744                              struct intel_encoder *encoder,
3745                              const struct intel_crtc_state *crtc_state,
3746                              const struct drm_connector_state *conn_state)
3747 {
3748         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3749
3750         intel_ddi_enable_transcoder_func(encoder, crtc_state);
3751
3752         intel_enable_pipe(crtc_state);
3753
3754         intel_crtc_vblank_on(crtc_state);
3755
3756         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3757                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3758         else
3759                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3760
3761         /* Enable hdcp if it's desired */
3762         if (conn_state->content_protection ==
3763             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3764                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3765                                   crtc_state->cpu_transcoder,
3766                                   (u8)conn_state->hdcp_content_type);
3767 }
3768
3769 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3770                                  struct intel_encoder *encoder,
3771                                  const struct intel_crtc_state *old_crtc_state,
3772                                  const struct drm_connector_state *old_conn_state)
3773 {
3774         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3775
3776         intel_dp->link_trained = false;
3777
3778         if (old_crtc_state->has_audio)
3779                 intel_audio_codec_disable(encoder,
3780                                           old_crtc_state, old_conn_state);
3781
3782         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3783         intel_psr_disable(intel_dp, old_crtc_state);
3784         intel_edp_backlight_off(old_conn_state);
3785         /* Disable the decompression in DP Sink */
3786         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3787                                               false);
3788 }
3789
3790 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3791                                    struct intel_encoder *encoder,
3792                                    const struct intel_crtc_state *old_crtc_state,
3793                                    const struct drm_connector_state *old_conn_state)
3794 {
3795         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3796         struct drm_connector *connector = old_conn_state->connector;
3797
3798         if (old_crtc_state->has_audio)
3799                 intel_audio_codec_disable(encoder,
3800                                           old_crtc_state, old_conn_state);
3801
3802         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3803                                                false, false))
3804                 drm_dbg_kms(&i915->drm,
3805                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3806                             connector->base.id, connector->name);
3807 }
3808
3809 static void intel_disable_ddi(struct intel_atomic_state *state,
3810                               struct intel_encoder *encoder,
3811                               const struct intel_crtc_state *old_crtc_state,
3812                               const struct drm_connector_state *old_conn_state)
3813 {
3814         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3815
3816         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3817                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3818                                        old_conn_state);
3819         else
3820                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3821                                      old_conn_state);
3822 }
3823
3824 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3825                                      struct intel_encoder *encoder,
3826                                      const struct intel_crtc_state *crtc_state,
3827                                      const struct drm_connector_state *conn_state)
3828 {
3829         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3830
3831         intel_ddi_set_dp_msa(crtc_state, conn_state);
3832
3833         intel_psr_update(intel_dp, crtc_state);
3834         intel_edp_drrs_enable(intel_dp, crtc_state);
3835
3836         intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
3837 }
3838
3839 static void intel_ddi_update_pipe(struct intel_atomic_state *state,
3840                                   struct intel_encoder *encoder,
3841                                   const struct intel_crtc_state *crtc_state,
3842                                   const struct drm_connector_state *conn_state)
3843 {
3844
3845         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3846                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3847                                          conn_state);
3848
3849         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3850 }
3851
3852 static void
3853 intel_ddi_update_prepare(struct intel_atomic_state *state,
3854                          struct intel_encoder *encoder,
3855                          struct intel_crtc *crtc)
3856 {
3857         struct intel_crtc_state *crtc_state =
3858                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3859         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3860
3861         drm_WARN_ON(state->base.dev, crtc && crtc->active);
3862
3863         intel_tc_port_get_link(enc_to_dig_port(encoder),
3864                                required_lanes);
3865         if (crtc_state && crtc_state->hw.active)
3866                 intel_update_active_dpll(state, crtc, encoder);
3867 }
3868
3869 static void
3870 intel_ddi_update_complete(struct intel_atomic_state *state,
3871                           struct intel_encoder *encoder,
3872                           struct intel_crtc *crtc)
3873 {
3874         intel_tc_port_put_link(enc_to_dig_port(encoder));
3875 }
3876
3877 static void
3878 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3879                          struct intel_encoder *encoder,
3880                          const struct intel_crtc_state *crtc_state,
3881                          const struct drm_connector_state *conn_state)
3882 {
3883         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3884         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3885         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3886         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3887
3888         if (is_tc_port)
3889                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3890
3891         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3892                 intel_display_power_get(dev_priv,
3893                                         intel_ddi_main_link_aux_domain(dig_port));
3894
3895         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3896                 /*
3897                  * Program the lane count for static/dynamic connections on
3898                  * Type-C ports.  Skip this step for TBT.
3899                  */
3900                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3901         else if (IS_GEN9_LP(dev_priv))
3902                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3903                                                 crtc_state->lane_lat_optim_mask);
3904 }
3905
3906 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3907 {
3908         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3909         struct drm_i915_private *dev_priv =
3910                 to_i915(intel_dig_port->base.base.dev);
3911         enum port port = intel_dig_port->base.port;
3912         u32 dp_tp_ctl, ddi_buf_ctl;
3913         bool wait = false;
3914
3915         dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3916
3917         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3918                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3919                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3920                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3921                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3922                         wait = true;
3923                 }
3924
3925                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3926                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3927                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
3928                 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3929
3930                 if (wait)
3931                         intel_wait_ddi_buf_idle(dev_priv, port);
3932         }
3933
3934         dp_tp_ctl = DP_TP_CTL_ENABLE |
3935                     DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3936         if (intel_dp->link_mst)
3937                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3938         else {
3939                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3940                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3941                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3942         }
3943         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
3944         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3945
3946         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3947         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3948         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3949
3950         udelay(600);
3951 }
3952
3953 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3954                                      u8 dp_train_pat)
3955 {
3956         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3957         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3958         enum port port = dp_to_dig_port(intel_dp)->base.port;
3959         u32 temp;
3960
3961         temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3962
3963         if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3964                 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3965         else
3966                 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3967
3968         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3969         switch (dp_train_pat & train_pat_mask) {
3970         case DP_TRAINING_PATTERN_DISABLE:
3971                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3972                 break;
3973         case DP_TRAINING_PATTERN_1:
3974                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3975                 break;
3976         case DP_TRAINING_PATTERN_2:
3977                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3978                 break;
3979         case DP_TRAINING_PATTERN_3:
3980                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3981                 break;
3982         case DP_TRAINING_PATTERN_4:
3983                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3984                 break;
3985         }
3986
3987         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
3988
3989         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3990         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3991 }
3992
3993 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3994                                        enum transcoder cpu_transcoder)
3995 {
3996         if (cpu_transcoder == TRANSCODER_EDP)
3997                 return false;
3998
3999         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4000                 return false;
4001
4002         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
4003                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4004 }
4005
4006 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4007                                          struct intel_crtc_state *crtc_state)
4008 {
4009         if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
4010                 crtc_state->min_voltage_level = 2;
4011         else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
4012                 crtc_state->min_voltage_level = 3;
4013         else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4014                 crtc_state->min_voltage_level = 1;
4015         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4016                 crtc_state->min_voltage_level = 2;
4017 }
4018
4019 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
4020                                                      enum transcoder cpu_transcoder)
4021 {
4022         u32 master_select;
4023
4024         if (INTEL_GEN(dev_priv) >= 11) {
4025                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4026
4027                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4028                         return INVALID_TRANSCODER;
4029
4030                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4031         } else {
4032                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4033
4034                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4035                         return INVALID_TRANSCODER;
4036
4037                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4038         }
4039
4040         if (master_select == 0)
4041                 return TRANSCODER_EDP;
4042         else
4043                 return master_select - 1;
4044 }
4045
4046 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4047 {
4048         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4049         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4050                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4051         enum transcoder cpu_transcoder;
4052
4053         crtc_state->master_transcoder =
4054                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4055
4056         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4057                 enum intel_display_power_domain power_domain;
4058                 intel_wakeref_t trans_wakeref;
4059
4060                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4061                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4062                                                                    power_domain);
4063
4064                 if (!trans_wakeref)
4065                         continue;
4066
4067                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4068                     crtc_state->cpu_transcoder)
4069                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4070
4071                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4072         }
4073
4074         drm_WARN_ON(&dev_priv->drm,
4075                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
4076                     crtc_state->sync_mode_slaves_mask);
4077 }
4078
4079 void intel_ddi_get_config(struct intel_encoder *encoder,
4080                           struct intel_crtc_state *pipe_config)
4081 {
4082         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4083         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4084         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4085         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4086         u32 temp, flags = 0;
4087
4088         /* XXX: DSI transcoder paranoia */
4089         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4090                 return;
4091
4092         if (INTEL_GEN(dev_priv) >= 12) {
4093                 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);
4094                 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);
4095         }
4096
4097         intel_dsc_get_config(encoder, pipe_config);
4098
4099         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4100         if (temp & TRANS_DDI_PHSYNC)
4101                 flags |= DRM_MODE_FLAG_PHSYNC;
4102         else
4103                 flags |= DRM_MODE_FLAG_NHSYNC;
4104         if (temp & TRANS_DDI_PVSYNC)
4105                 flags |= DRM_MODE_FLAG_PVSYNC;
4106         else
4107                 flags |= DRM_MODE_FLAG_NVSYNC;
4108
4109         pipe_config->hw.adjusted_mode.flags |= flags;
4110
4111         switch (temp & TRANS_DDI_BPC_MASK) {
4112         case TRANS_DDI_BPC_6:
4113                 pipe_config->pipe_bpp = 18;
4114                 break;
4115         case TRANS_DDI_BPC_8:
4116                 pipe_config->pipe_bpp = 24;
4117                 break;
4118         case TRANS_DDI_BPC_10:
4119                 pipe_config->pipe_bpp = 30;
4120                 break;
4121         case TRANS_DDI_BPC_12:
4122                 pipe_config->pipe_bpp = 36;
4123                 break;
4124         default:
4125                 break;
4126         }
4127
4128         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4129         case TRANS_DDI_MODE_SELECT_HDMI:
4130                 pipe_config->has_hdmi_sink = true;
4131
4132                 pipe_config->infoframes.enable |=
4133                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4134
4135                 if (pipe_config->infoframes.enable)
4136                         pipe_config->has_infoframe = true;
4137
4138                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4139                         pipe_config->hdmi_scrambling = true;
4140                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4141                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4142                 /* fall through */
4143         case TRANS_DDI_MODE_SELECT_DVI:
4144                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4145                 pipe_config->lane_count = 4;
4146                 break;
4147         case TRANS_DDI_MODE_SELECT_FDI:
4148                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4149                 break;
4150         case TRANS_DDI_MODE_SELECT_DP_SST:
4151                 if (encoder->type == INTEL_OUTPUT_EDP)
4152                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4153                 else
4154                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4155                 pipe_config->lane_count =
4156                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4157                 intel_dp_get_m_n(intel_crtc, pipe_config);
4158
4159                 if (INTEL_GEN(dev_priv) >= 11) {
4160                         i915_reg_t dp_tp_ctl;
4161
4162                         if (IS_GEN(dev_priv, 11))
4163                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4164                         else
4165                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4166
4167                         pipe_config->fec_enable =
4168                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4169
4170                         drm_dbg_kms(&dev_priv->drm,
4171                                     "[ENCODER:%d:%s] Fec status: %u\n",
4172                                     encoder->base.base.id, encoder->base.name,
4173                                     pipe_config->fec_enable);
4174                 }
4175
4176                 break;
4177         case TRANS_DDI_MODE_SELECT_DP_MST:
4178                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4179                 pipe_config->lane_count =
4180                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4181
4182                 if (INTEL_GEN(dev_priv) >= 12)
4183                         pipe_config->mst_master_transcoder =
4184                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4185
4186                 intel_dp_get_m_n(intel_crtc, pipe_config);
4187                 break;
4188         default:
4189                 break;
4190         }
4191
4192         pipe_config->has_audio =
4193                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4194
4195         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4196             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4197                 /*
4198                  * This is a big fat ugly hack.
4199                  *
4200                  * Some machines in UEFI boot mode provide us a VBT that has 18
4201                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4202                  * unknown we fail to light up. Yet the same BIOS boots up with
4203                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4204                  * max, not what it tells us to use.
4205                  *
4206                  * Note: This will still be broken if the eDP panel is not lit
4207                  * up by the BIOS, and thus we can't get the mode at module
4208                  * load.
4209                  */
4210                 drm_dbg_kms(&dev_priv->drm,
4211                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4212                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4213                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4214         }
4215
4216         intel_ddi_clock_get(encoder, pipe_config);
4217
4218         if (IS_GEN9_LP(dev_priv))
4219                 pipe_config->lane_lat_optim_mask =
4220                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4221
4222         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4223
4224         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4225
4226         intel_read_infoframe(encoder, pipe_config,
4227                              HDMI_INFOFRAME_TYPE_AVI,
4228                              &pipe_config->infoframes.avi);
4229         intel_read_infoframe(encoder, pipe_config,
4230                              HDMI_INFOFRAME_TYPE_SPD,
4231                              &pipe_config->infoframes.spd);
4232         intel_read_infoframe(encoder, pipe_config,
4233                              HDMI_INFOFRAME_TYPE_VENDOR,
4234                              &pipe_config->infoframes.hdmi);
4235         intel_read_infoframe(encoder, pipe_config,
4236                              HDMI_INFOFRAME_TYPE_DRM,
4237                              &pipe_config->infoframes.drm);
4238
4239         if (INTEL_GEN(dev_priv) >= 8)
4240                 bdw_get_trans_port_sync_config(pipe_config);
4241 }
4242
4243 static enum intel_output_type
4244 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4245                               struct intel_crtc_state *crtc_state,
4246                               struct drm_connector_state *conn_state)
4247 {
4248         switch (conn_state->connector->connector_type) {
4249         case DRM_MODE_CONNECTOR_HDMIA:
4250                 return INTEL_OUTPUT_HDMI;
4251         case DRM_MODE_CONNECTOR_eDP:
4252                 return INTEL_OUTPUT_EDP;
4253         case DRM_MODE_CONNECTOR_DisplayPort:
4254                 return INTEL_OUTPUT_DP;
4255         default:
4256                 MISSING_CASE(conn_state->connector->connector_type);
4257                 return INTEL_OUTPUT_UNUSED;
4258         }
4259 }
4260
4261 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4262                                     struct intel_crtc_state *pipe_config,
4263                                     struct drm_connector_state *conn_state)
4264 {
4265         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4266         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4267         enum port port = encoder->port;
4268         int ret;
4269
4270         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4271                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4272
4273         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4274                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4275         } else {
4276                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4277         }
4278
4279         if (ret)
4280                 return ret;
4281
4282         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4283             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4284                 pipe_config->pch_pfit.force_thru =
4285                         pipe_config->pch_pfit.enabled ||
4286                         pipe_config->crc_enabled;
4287
4288         if (IS_GEN9_LP(dev_priv))
4289                 pipe_config->lane_lat_optim_mask =
4290                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4291
4292         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4293
4294         return 0;
4295 }
4296
4297 static bool mode_equal(const struct drm_display_mode *mode1,
4298                        const struct drm_display_mode *mode2)
4299 {
4300         return drm_mode_match(mode1, mode2,
4301                               DRM_MODE_MATCH_TIMINGS |
4302                               DRM_MODE_MATCH_FLAGS |
4303                               DRM_MODE_MATCH_3D_FLAGS) &&
4304                 mode1->clock == mode2->clock; /* we want an exact match */
4305 }
4306
4307 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4308                       const struct intel_link_m_n *m_n_2)
4309 {
4310         return m_n_1->tu == m_n_2->tu &&
4311                 m_n_1->gmch_m == m_n_2->gmch_m &&
4312                 m_n_1->gmch_n == m_n_2->gmch_n &&
4313                 m_n_1->link_m == m_n_2->link_m &&
4314                 m_n_1->link_n == m_n_2->link_n;
4315 }
4316
4317 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4318                                        const struct intel_crtc_state *crtc_state2)
4319 {
4320         return crtc_state1->hw.active && crtc_state2->hw.active &&
4321                 crtc_state1->output_types == crtc_state2->output_types &&
4322                 crtc_state1->output_format == crtc_state2->output_format &&
4323                 crtc_state1->lane_count == crtc_state2->lane_count &&
4324                 crtc_state1->port_clock == crtc_state2->port_clock &&
4325                 mode_equal(&crtc_state1->hw.adjusted_mode,
4326                            &crtc_state2->hw.adjusted_mode) &&
4327                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4328 }
4329
4330 static u8
4331 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4332                                 int tile_group_id)
4333 {
4334         struct drm_connector *connector;
4335         const struct drm_connector_state *conn_state;
4336         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4337         struct intel_atomic_state *state =
4338                 to_intel_atomic_state(ref_crtc_state->uapi.state);
4339         u8 transcoders = 0;
4340         int i;
4341
4342         /*
4343          * We don't enable port sync on BDW due to missing w/as and
4344          * due to not having adjusted the modeset sequence appropriately.
4345          */
4346         if (INTEL_GEN(dev_priv) < 9)
4347                 return 0;
4348
4349         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4350                 return 0;
4351
4352         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4353                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4354                 const struct intel_crtc_state *crtc_state;
4355
4356                 if (!crtc)
4357                         continue;
4358
4359                 if (!connector->has_tile ||
4360                     connector->tile_group->id !=
4361                     tile_group_id)
4362                         continue;
4363                 crtc_state = intel_atomic_get_new_crtc_state(state,
4364                                                              crtc);
4365                 if (!crtcs_port_sync_compatible(ref_crtc_state,
4366                                                 crtc_state))
4367                         continue;
4368                 transcoders |= BIT(crtc_state->cpu_transcoder);
4369         }
4370
4371         return transcoders;
4372 }
4373
4374 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4375                                          struct intel_crtc_state *crtc_state,
4376                                          struct drm_connector_state *conn_state)
4377 {
4378         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4379         struct drm_connector *connector = conn_state->connector;
4380         u8 port_sync_transcoders = 0;
4381
4382         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4383                     encoder->base.base.id, encoder->base.name,
4384                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4385
4386         if (connector->has_tile)
4387                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4388                                                                         connector->tile_group->id);
4389
4390         /*
4391          * EDP Transcoders cannot be ensalved
4392          * make them a master always when present
4393          */
4394         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4395                 crtc_state->master_transcoder = TRANSCODER_EDP;
4396         else
4397                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4398
4399         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4400                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4401                 crtc_state->sync_mode_slaves_mask =
4402                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4403         }
4404
4405         return 0;
4406 }
4407
4408 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4409 {
4410         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4411
4412         intel_dp_encoder_flush_work(encoder);
4413
4414         drm_encoder_cleanup(encoder);
4415         kfree(dig_port);
4416 }
4417
4418 static const struct drm_encoder_funcs intel_ddi_funcs = {
4419         .reset = intel_dp_encoder_reset,
4420         .destroy = intel_ddi_encoder_destroy,
4421 };
4422
4423 static struct intel_connector *
4424 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4425 {
4426         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
4427         struct intel_connector *connector;
4428         enum port port = intel_dig_port->base.port;
4429
4430         connector = intel_connector_alloc();
4431         if (!connector)
4432                 return NULL;
4433
4434         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4435         intel_dig_port->dp.prepare_link_retrain =
4436                 intel_ddi_prepare_link_retrain;
4437         intel_dig_port->dp.set_link_train = intel_ddi_set_link_train;
4438
4439         if (INTEL_GEN(dev_priv) < 12) {
4440                 intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
4441                 intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
4442         }
4443
4444         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4445                 kfree(connector);
4446                 return NULL;
4447         }
4448
4449         return connector;
4450 }
4451
4452 static int modeset_pipe(struct drm_crtc *crtc,
4453                         struct drm_modeset_acquire_ctx *ctx)
4454 {
4455         struct drm_atomic_state *state;
4456         struct drm_crtc_state *crtc_state;
4457         int ret;
4458
4459         state = drm_atomic_state_alloc(crtc->dev);
4460         if (!state)
4461                 return -ENOMEM;
4462
4463         state->acquire_ctx = ctx;
4464
4465         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4466         if (IS_ERR(crtc_state)) {
4467                 ret = PTR_ERR(crtc_state);
4468                 goto out;
4469         }
4470
4471         crtc_state->connectors_changed = true;
4472
4473         ret = drm_atomic_commit(state);
4474 out:
4475         drm_atomic_state_put(state);
4476
4477         return ret;
4478 }
4479
4480 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4481                                  struct drm_modeset_acquire_ctx *ctx)
4482 {
4483         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4484         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4485         struct intel_connector *connector = hdmi->attached_connector;
4486         struct i2c_adapter *adapter =
4487                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4488         struct drm_connector_state *conn_state;
4489         struct intel_crtc_state *crtc_state;
4490         struct intel_crtc *crtc;
4491         u8 config;
4492         int ret;
4493
4494         if (!connector || connector->base.status != connector_status_connected)
4495                 return 0;
4496
4497         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4498                                ctx);
4499         if (ret)
4500                 return ret;
4501
4502         conn_state = connector->base.state;
4503
4504         crtc = to_intel_crtc(conn_state->crtc);
4505         if (!crtc)
4506                 return 0;
4507
4508         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4509         if (ret)
4510                 return ret;
4511
4512         crtc_state = to_intel_crtc_state(crtc->base.state);
4513
4514         drm_WARN_ON(&dev_priv->drm,
4515                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4516
4517         if (!crtc_state->hw.active)
4518                 return 0;
4519
4520         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4521             !crtc_state->hdmi_scrambling)
4522                 return 0;
4523
4524         if (conn_state->commit &&
4525             !try_wait_for_completion(&conn_state->commit->hw_done))
4526                 return 0;
4527
4528         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4529         if (ret < 0) {
4530                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4531                         ret);
4532                 return 0;
4533         }
4534
4535         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4536             crtc_state->hdmi_high_tmds_clock_ratio &&
4537             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4538             crtc_state->hdmi_scrambling)
4539                 return 0;
4540
4541         /*
4542          * HDMI 2.0 says that one should not send scrambled data
4543          * prior to configuring the sink scrambling, and that
4544          * TMDS clock/data transmission should be suspended when
4545          * changing the TMDS clock rate in the sink. So let's
4546          * just do a full modeset here, even though some sinks
4547          * would be perfectly happy if were to just reconfigure
4548          * the SCDC settings on the fly.
4549          */
4550         return modeset_pipe(&crtc->base, ctx);
4551 }
4552
4553 static enum intel_hotplug_state
4554 intel_ddi_hotplug(struct intel_encoder *encoder,
4555                   struct intel_connector *connector)
4556 {
4557         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4558         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4559         enum phy phy = intel_port_to_phy(i915, encoder->port);
4560         bool is_tc = intel_phy_is_tc(i915, phy);
4561         struct drm_modeset_acquire_ctx ctx;
4562         enum intel_hotplug_state state;
4563         int ret;
4564
4565         state = intel_encoder_hotplug(encoder, connector);
4566
4567         drm_modeset_acquire_init(&ctx, 0);
4568
4569         for (;;) {
4570                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4571                         ret = intel_hdmi_reset_link(encoder, &ctx);
4572                 else
4573                         ret = intel_dp_retrain_link(encoder, &ctx);
4574
4575                 if (ret == -EDEADLK) {
4576                         drm_modeset_backoff(&ctx);
4577                         continue;
4578                 }
4579
4580                 break;
4581         }
4582
4583         drm_modeset_drop_locks(&ctx);
4584         drm_modeset_acquire_fini(&ctx);
4585         drm_WARN(encoder->base.dev, ret,
4586                  "Acquiring modeset locks failed with %i\n", ret);
4587
4588         /*
4589          * Unpowered type-c dongles can take some time to boot and be
4590          * responsible, so here giving some time to those dongles to power up
4591          * and then retrying the probe.
4592          *
4593          * On many platforms the HDMI live state signal is known to be
4594          * unreliable, so we can't use it to detect if a sink is connected or
4595          * not. Instead we detect if it's connected based on whether we can
4596          * read the EDID or not. That in turn has a problem during disconnect,
4597          * since the HPD interrupt may be raised before the DDC lines get
4598          * disconnected (due to how the required length of DDC vs. HPD
4599          * connector pins are specified) and so we'll still be able to get a
4600          * valid EDID. To solve this schedule another detection cycle if this
4601          * time around we didn't detect any change in the sink's connection
4602          * status.
4603          *
4604          * Type-c connectors which get their HPD signal deasserted then
4605          * reasserted, without unplugging/replugging the sink from the
4606          * connector, introduce a delay until the AUX channel communication
4607          * becomes functional. Retry the detection for 5 seconds on type-c
4608          * connectors to account for this delay.
4609          */
4610         if (state == INTEL_HOTPLUG_UNCHANGED &&
4611             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4612             !dig_port->dp.is_mst)
4613                 state = INTEL_HOTPLUG_RETRY;
4614
4615         return state;
4616 }
4617
4618 static struct intel_connector *
4619 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4620 {
4621         struct intel_connector *connector;
4622         enum port port = intel_dig_port->base.port;
4623
4624         connector = intel_connector_alloc();
4625         if (!connector)
4626                 return NULL;
4627
4628         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4629         intel_hdmi_init_connector(intel_dig_port, connector);
4630
4631         return connector;
4632 }
4633
4634 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4635 {
4636         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4637
4638         if (dport->base.port != PORT_A)
4639                 return false;
4640
4641         if (dport->saved_port_bits & DDI_A_4_LANES)
4642                 return false;
4643
4644         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4645          *                     supported configuration
4646          */
4647         if (IS_GEN9_LP(dev_priv))
4648                 return true;
4649
4650         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4651          *             one who does also have a full A/E split called
4652          *             DDI_F what makes DDI_E useless. However for this
4653          *             case let's trust VBT info.
4654          */
4655         if (IS_CANNONLAKE(dev_priv) &&
4656             !intel_bios_is_port_present(dev_priv, PORT_E))
4657                 return true;
4658
4659         return false;
4660 }
4661
4662 static int
4663 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4664 {
4665         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4666         enum port port = intel_dport->base.port;
4667         int max_lanes = 4;
4668
4669         if (INTEL_GEN(dev_priv) >= 11)
4670                 return max_lanes;
4671
4672         if (port == PORT_A || port == PORT_E) {
4673                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4674                         max_lanes = port == PORT_A ? 4 : 0;
4675                 else
4676                         /* Both A and E share 2 lanes */
4677                         max_lanes = 2;
4678         }
4679
4680         /*
4681          * Some BIOS might fail to set this bit on port A if eDP
4682          * wasn't lit up at boot.  Force this bit set when needed
4683          * so we use the proper lane count for our calculations.
4684          */
4685         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4686                 drm_dbg_kms(&dev_priv->drm,
4687                             "Forcing DDI_A_4_LANES for port A\n");
4688                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4689                 max_lanes = 4;
4690         }
4691
4692         return max_lanes;
4693 }
4694
4695 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4696 {
4697         struct intel_digital_port *intel_dig_port;
4698         struct intel_encoder *encoder;
4699         bool init_hdmi, init_dp, init_lspcon = false;
4700         enum phy phy = intel_port_to_phy(dev_priv, port);
4701
4702         init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
4703                 intel_bios_port_supports_hdmi(dev_priv, port);
4704         init_dp = intel_bios_port_supports_dp(dev_priv, port);
4705
4706         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4707                 /*
4708                  * Lspcon device needs to be driven with DP connector
4709                  * with special detection sequence. So make sure DP
4710                  * is initialized before lspcon.
4711                  */
4712                 init_dp = true;
4713                 init_lspcon = true;
4714                 init_hdmi = false;
4715                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4716                             port_name(port));
4717         }
4718
4719         if (!init_dp && !init_hdmi) {
4720                 drm_dbg_kms(&dev_priv->drm,
4721                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4722                             port_name(port));
4723                 return;
4724         }
4725
4726         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4727         if (!intel_dig_port)
4728                 return;
4729
4730         encoder = &intel_dig_port->base;
4731
4732         drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4733                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4734
4735         encoder->hotplug = intel_ddi_hotplug;
4736         encoder->compute_output_type = intel_ddi_compute_output_type;
4737         encoder->compute_config = intel_ddi_compute_config;
4738         encoder->compute_config_late = intel_ddi_compute_config_late;
4739         encoder->enable = intel_enable_ddi;
4740         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4741         encoder->pre_enable = intel_ddi_pre_enable;
4742         encoder->disable = intel_disable_ddi;
4743         encoder->post_disable = intel_ddi_post_disable;
4744         encoder->update_pipe = intel_ddi_update_pipe;
4745         encoder->get_hw_state = intel_ddi_get_hw_state;
4746         encoder->get_config = intel_ddi_get_config;
4747         encoder->suspend = intel_dp_encoder_suspend;
4748         encoder->get_power_domains = intel_ddi_get_power_domains;
4749
4750         encoder->type = INTEL_OUTPUT_DDI;
4751         encoder->power_domain = intel_port_to_power_domain(port);
4752         encoder->port = port;
4753         encoder->cloneable = 0;
4754         encoder->pipe_mask = ~0;
4755
4756         if (INTEL_GEN(dev_priv) >= 11)
4757                 intel_dig_port->saved_port_bits = intel_de_read(dev_priv,
4758                                                                 DDI_BUF_CTL(port)) &
4759                         DDI_BUF_PORT_REVERSAL;
4760         else
4761                 intel_dig_port->saved_port_bits = intel_de_read(dev_priv,
4762                                                                 DDI_BUF_CTL(port)) &
4763                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4764
4765         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4766         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4767         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4768
4769         if (intel_phy_is_tc(dev_priv, phy)) {
4770                 bool is_legacy =
4771                         !intel_bios_port_supports_typec_usb(dev_priv, port) &&
4772                         !intel_bios_port_supports_tbt(dev_priv, port);
4773
4774                 intel_tc_port_init(intel_dig_port, is_legacy);
4775
4776                 encoder->update_prepare = intel_ddi_update_prepare;
4777                 encoder->update_complete = intel_ddi_update_complete;
4778         }
4779
4780         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4781         intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4782                                               port - PORT_A;
4783
4784         if (init_dp) {
4785                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4786                         goto err;
4787
4788                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4789         }
4790
4791         /* In theory we don't need the encoder->type check, but leave it just in
4792          * case we have some really bad VBTs... */
4793         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4794                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4795                         goto err;
4796         }
4797
4798         if (init_lspcon) {
4799                 if (lspcon_init(intel_dig_port))
4800                         /* TODO: handle hdmi info frame part */
4801                         drm_dbg_kms(&dev_priv->drm,
4802                                     "LSPCON init success on port %c\n",
4803                                     port_name(port));
4804                 else
4805                         /*
4806                          * LSPCON init faied, but DP init was success, so
4807                          * lets try to drive as DP++ port.
4808                          */
4809                         drm_err(&dev_priv->drm,
4810                                 "LSPCON init failed on port %c\n",
4811                                 port_name(port));
4812         }
4813
4814         intel_infoframe_init(intel_dig_port);
4815
4816         return;
4817
4818 err:
4819         drm_encoder_cleanup(&encoder->base);
4820         kfree(intel_dig_port);
4821 }