drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_mst.h"
  38 #include "intel_dp_link_training.h"
  39 #include "intel_dpio_phy.h"
  40 #include "intel_dsi.h"
  41 #include "intel_fifo_underrun.h"
  42 #include "intel_gmbus.h"
  43 #include "intel_hdcp.h"
  44 #include "intel_hdmi.h"
  45 #include "intel_hotplug.h"
  46 #include "intel_lspcon.h"
  47 #include "intel_panel.h"
  48 #include "intel_psr.h"
  49 #include "intel_sprite.h"
  50 #include "intel_tc.h"
  51 #include "intel_vdsc.h"
  52
  53 struct ddi_buf_trans {
  54         u32 trans1;     /* balance leg enable, de-emph level */
  55         u32 trans2;     /* vref sel, vswing */
  56         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  57 };
  58
  59 static const u8 index_to_dp_signal_levels[] = {
  60         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  61         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  62         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  63         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  64         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  69         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  70 };
  71
  72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  73  * them for both DP and FDI transports, allowing those ports to
  74  * automatically adapt to HDMI connections as well
  75  */
  76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  77         { 0x00FFFFFF, 0x0006000E, 0x0 },
  78         { 0x00D75FFF, 0x0005000A, 0x0 },
  79         { 0x00C30FFF, 0x00040006, 0x0 },
  80         { 0x80AAAFFF, 0x000B0000, 0x0 },
  81         { 0x00FFFFFF, 0x0005000A, 0x0 },
  82         { 0x00D75FFF, 0x000C0004, 0x0 },
  83         { 0x80C30FFF, 0x000B0000, 0x0 },
  84         { 0x00FFFFFF, 0x00040006, 0x0 },
  85         { 0x80D75FFF, 0x000B0000, 0x0 },
  86 };
  87
  88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  89         { 0x00FFFFFF, 0x0007000E, 0x0 },
  90         { 0x00D75FFF, 0x000F000A, 0x0 },
  91         { 0x00C30FFF, 0x00060006, 0x0 },
  92         { 0x00AAAFFF, 0x001E0000, 0x0 },
  93         { 0x00FFFFFF, 0x000F000A, 0x0 },
  94         { 0x00D75FFF, 0x00160004, 0x0 },
  95         { 0x00C30FFF, 0x001E0000, 0x0 },
  96         { 0x00FFFFFF, 0x00060006, 0x0 },
  97         { 0x00D75FFF, 0x001E0000, 0x0 },
  98 };
  99
 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 101                                         /* Idx  NT mV d T mV d  db      */
 102         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 103         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 104         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 105         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 106         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 107         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 108         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 109         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 110         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 111         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 112         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 113         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 117         { 0x00FFFFFF, 0x00000012, 0x0 },
 118         { 0x00EBAFFF, 0x00020011, 0x0 },
 119         { 0x00C71FFF, 0x0006000F, 0x0 },
 120         { 0x00AAAFFF, 0x000E000A, 0x0 },
 121         { 0x00FFFFFF, 0x00020011, 0x0 },
 122         { 0x00DB6FFF, 0x0005000F, 0x0 },
 123         { 0x00BEEFFF, 0x000A000C, 0x0 },
 124         { 0x00FFFFFF, 0x0005000F, 0x0 },
 125         { 0x00DB6FFF, 0x000A000C, 0x0 },
 126 };
 127
 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 129         { 0x00FFFFFF, 0x0007000E, 0x0 },
 130         { 0x00D75FFF, 0x000E000A, 0x0 },
 131         { 0x00BEFFFF, 0x00140006, 0x0 },
 132         { 0x80B2CFFF, 0x001B0002, 0x0 },
 133         { 0x00FFFFFF, 0x000E000A, 0x0 },
 134         { 0x00DB6FFF, 0x00160005, 0x0 },
 135         { 0x80C71FFF, 0x001A0002, 0x0 },
 136         { 0x00F7DFFF, 0x00180004, 0x0 },
 137         { 0x80D75FFF, 0x001B0002, 0x0 },
 138 };
 139
 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 141         { 0x00FFFFFF, 0x0001000E, 0x0 },
 142         { 0x00D75FFF, 0x0004000A, 0x0 },
 143         { 0x00C30FFF, 0x00070006, 0x0 },
 144         { 0x00AAAFFF, 0x000C0000, 0x0 },
 145         { 0x00FFFFFF, 0x0004000A, 0x0 },
 146         { 0x00D75FFF, 0x00090004, 0x0 },
 147         { 0x00C30FFF, 0x000C0000, 0x0 },
 148         { 0x00FFFFFF, 0x00070006, 0x0 },
 149         { 0x00D75FFF, 0x000C0000, 0x0 },
 150 };
 151
 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 153                                         /* Idx  NT mV d T mV df db      */
 154         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 155         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 156         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 157         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 158         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 159         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 160         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 161         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 162         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 163         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 164 };
 165
 166 /* Skylake H and S */
 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 168         { 0x00002016, 0x000000A0, 0x0 },
 169         { 0x00005012, 0x0000009B, 0x0 },
 170         { 0x00007011, 0x00000088, 0x0 },
 171         { 0x80009010, 0x000000C0, 0x1 },
 172         { 0x00002016, 0x0000009B, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000C0, 0x1 },
 175         { 0x00002016, 0x000000DF, 0x0 },
 176         { 0x80005012, 0x000000C0, 0x1 },
 177 };
 178
 179 /* Skylake U */
 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 181         { 0x0000201B, 0x000000A2, 0x0 },
 182         { 0x00005012, 0x00000088, 0x0 },
 183         { 0x80007011, 0x000000CD, 0x1 },
 184         { 0x80009010, 0x000000C0, 0x1 },
 185         { 0x0000201B, 0x0000009D, 0x0 },
 186         { 0x80005012, 0x000000C0, 0x1 },
 187         { 0x80007011, 0x000000C0, 0x1 },
 188         { 0x00002016, 0x00000088, 0x0 },
 189         { 0x80005012, 0x000000C0, 0x1 },
 190 };
 191
 192 /* Skylake Y */
 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 194         { 0x00000018, 0x000000A2, 0x0 },
 195         { 0x00005012, 0x00000088, 0x0 },
 196         { 0x80007011, 0x000000CD, 0x3 },
 197         { 0x80009010, 0x000000C0, 0x3 },
 198         { 0x00000018, 0x0000009D, 0x0 },
 199         { 0x80005012, 0x000000C0, 0x3 },
 200         { 0x80007011, 0x000000C0, 0x3 },
 201         { 0x00000018, 0x00000088, 0x0 },
 202         { 0x80005012, 0x000000C0, 0x3 },
 203 };
 204
 205 /* Kabylake H and S */
 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 207         { 0x00002016, 0x000000A0, 0x0 },
 208         { 0x00005012, 0x0000009B, 0x0 },
 209         { 0x00007011, 0x00000088, 0x0 },
 210         { 0x80009010, 0x000000C0, 0x1 },
 211         { 0x00002016, 0x0000009B, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000C0, 0x1 },
 214         { 0x00002016, 0x00000097, 0x0 },
 215         { 0x80005012, 0x000000C0, 0x1 },
 216 };
 217
 218 /* Kabylake U */
 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 220         { 0x0000201B, 0x000000A1, 0x0 },
 221         { 0x00005012, 0x00000088, 0x0 },
 222         { 0x80007011, 0x000000CD, 0x3 },
 223         { 0x80009010, 0x000000C0, 0x3 },
 224         { 0x0000201B, 0x0000009D, 0x0 },
 225         { 0x80005012, 0x000000C0, 0x3 },
 226         { 0x80007011, 0x000000C0, 0x3 },
 227         { 0x00002016, 0x0000004F, 0x0 },
 228         { 0x80005012, 0x000000C0, 0x3 },
 229 };
 230
 231 /* Kabylake Y */
 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 233         { 0x00001017, 0x000000A1, 0x0 },
 234         { 0x00005012, 0x00000088, 0x0 },
 235         { 0x80007011, 0x000000CD, 0x3 },
 236         { 0x8000800F, 0x000000C0, 0x3 },
 237         { 0x00001017, 0x0000009D, 0x0 },
 238         { 0x80005012, 0x000000C0, 0x3 },
 239         { 0x80007011, 0x000000C0, 0x3 },
 240         { 0x00001017, 0x0000004C, 0x0 },
 241         { 0x80005012, 0x000000C0, 0x3 },
 242 };
 243
 244 /*
 245  * Skylake/Kabylake H and S
 246  * eDP 1.4 low vswing translation parameters
 247  */
 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 249         { 0x00000018, 0x000000A8, 0x0 },
 250         { 0x00004013, 0x000000A9, 0x0 },
 251         { 0x00007011, 0x000000A2, 0x0 },
 252         { 0x00009010, 0x0000009C, 0x0 },
 253         { 0x00000018, 0x000000A9, 0x0 },
 254         { 0x00006013, 0x000000A2, 0x0 },
 255         { 0x00007011, 0x000000A6, 0x0 },
 256         { 0x00000018, 0x000000AB, 0x0 },
 257         { 0x00007013, 0x0000009F, 0x0 },
 258         { 0x00000018, 0x000000DF, 0x0 },
 259 };
 260
 261 /*
 262  * Skylake/Kabylake U
 263  * eDP 1.4 low vswing translation parameters
 264  */
 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 266         { 0x00000018, 0x000000A8, 0x0 },
 267         { 0x00004013, 0x000000A9, 0x0 },
 268         { 0x00007011, 0x000000A2, 0x0 },
 269         { 0x00009010, 0x0000009C, 0x0 },
 270         { 0x00000018, 0x000000A9, 0x0 },
 271         { 0x00006013, 0x000000A2, 0x0 },
 272         { 0x00007011, 0x000000A6, 0x0 },
 273         { 0x00002016, 0x000000AB, 0x0 },
 274         { 0x00005013, 0x0000009F, 0x0 },
 275         { 0x00000018, 0x000000DF, 0x0 },
 276 };
 277
 278 /*
 279  * Skylake/Kabylake Y
 280  * eDP 1.4 low vswing translation parameters
 281  */
 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 283         { 0x00000018, 0x000000A8, 0x0 },
 284         { 0x00004013, 0x000000AB, 0x0 },
 285         { 0x00007011, 0x000000A4, 0x0 },
 286         { 0x00009010, 0x000000DF, 0x0 },
 287         { 0x00000018, 0x000000AA, 0x0 },
 288         { 0x00006013, 0x000000A4, 0x0 },
 289         { 0x00007011, 0x0000009D, 0x0 },
 290         { 0x00000018, 0x000000A0, 0x0 },
 291         { 0x00006012, 0x000000DF, 0x0 },
 292         { 0x00000018, 0x0000008A, 0x0 },
 293 };
 294
 295 /* Skylake/Kabylake U, H and S */
 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 297         { 0x00000018, 0x000000AC, 0x0 },
 298         { 0x00005012, 0x0000009D, 0x0 },
 299         { 0x00007011, 0x00000088, 0x0 },
 300         { 0x00000018, 0x000000A1, 0x0 },
 301         { 0x00000018, 0x00000098, 0x0 },
 302         { 0x00004013, 0x00000088, 0x0 },
 303         { 0x80006012, 0x000000CD, 0x1 },
 304         { 0x00000018, 0x000000DF, 0x0 },
 305         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 306         { 0x80003015, 0x000000C0, 0x1 },
 307         { 0x80000018, 0x000000C0, 0x1 },
 308 };
 309
 310 /* Skylake/Kabylake Y */
 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 312         { 0x00000018, 0x000000A1, 0x0 },
 313         { 0x00005012, 0x000000DF, 0x0 },
 314         { 0x80007011, 0x000000CB, 0x3 },
 315         { 0x00000018, 0x000000A4, 0x0 },
 316         { 0x00000018, 0x0000009D, 0x0 },
 317         { 0x00004013, 0x00000080, 0x0 },
 318         { 0x80006013, 0x000000C0, 0x3 },
 319         { 0x00000018, 0x0000008A, 0x0 },
 320         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 321         { 0x80003015, 0x000000C0, 0x3 },
 322         { 0x80000018, 0x000000C0, 0x3 },
 323 };
 324
 325 struct bxt_ddi_buf_trans {
 326         u8 margin;      /* swing value */
 327         u8 scale;       /* scale value */
 328         u8 enable;      /* scale enable */
 329         u8 deemphasis;
 330 };
 331
 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 333                                         /* Idx  NT mV diff      db  */
 334         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 335         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 336         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 337         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 338         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 339         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 340         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 341         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 342         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 343         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 344 };
 345
 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 347                                         /* Idx  NT mV diff      db  */
 348         { 26, 0, 0, 128, },     /* 0:   200             0   */
 349         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 350         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 351         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 352         { 32, 0, 0, 128, },     /* 4:   250             0   */
 353         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 354         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 355         { 43, 0, 0, 128, },     /* 7:   300             0   */
 356         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 357         { 48, 0, 0, 128, },     /* 9:   300             0   */
 358 };
 359
 360 /* BSpec has 2 recommended values - entries 0 and 8.
 361  * Using the entry with higher vswing.
 362  */
 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 364                                         /* Idx  NT mV diff      db  */
 365         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 366         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 367         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 368         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 369         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 370         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 371         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 372         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 373         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 374         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 375 };
 376
 377 struct cnl_ddi_buf_trans {
 378         u8 dw2_swing_sel;
 379         u8 dw7_n_scalar;
 380         u8 dw4_cursor_coeff;
 381         u8 dw4_post_cursor_2;
 382         u8 dw4_post_cursor_1;
 383 };
 384
 385 /* Voltage Swing Programming for VccIO 0.85V for DP */
 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 387                                                 /* NT mV Trans mV db    */
 388         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 389         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 390         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 391         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 392         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 393         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 394         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 395         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 396         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 397         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 398 };
 399
 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 402                                                 /* NT mV Trans mV db    */
 403         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 404         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 405         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 406         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 407         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 408         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 409         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 410 };
 411
 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 414                                                 /* NT mV Trans mV db    */
 415         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 416         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 417         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 418         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 419         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 420         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 421         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 422         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 423         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424 };
 425
 426 /* Voltage Swing Programming for VccIO 0.95V for DP */
 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 428                                                 /* NT mV Trans mV db    */
 429         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 430         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 431         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 432         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 433         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 434         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 435         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 436         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 437         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 438         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 439 };
 440
 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 443                                                 /* NT mV Trans mV db    */
 444         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 445         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 446         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 447         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 448         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 449         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 450         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 451         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 452         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 453         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 454         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 455 };
 456
 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 459                                                 /* NT mV Trans mV db    */
 460         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 461         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 462         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 463         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 464         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 465         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 466         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 467         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 468         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 469         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470 };
 471
 472 /* Voltage Swing Programming for VccIO 1.05V for DP */
 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 474                                                 /* NT mV Trans mV db    */
 475         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 476         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 477         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 478         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 479         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 480         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 481         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 482         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 483         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 484         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 485 };
 486
 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 489                                                 /* NT mV Trans mV db    */
 490         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 491         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 492         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 493         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 494         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 495         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 496         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 497         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 498         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 499         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 500         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 501 };
 502
 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 505                                                 /* NT mV Trans mV db    */
 506         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 507         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 508         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 509         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 510         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 511         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 512         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 513         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 514         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 515 };
 516
 517 /* icl_combo_phy_ddi_translations */
 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 519                                                 /* NT mV Trans mV db    */
 520         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 521         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 522         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 523         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 524         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 525         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 526         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 527         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 528         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 529         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 530 };
 531
 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 533                                                 /* NT mV Trans mV db    */
 534         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 535         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 536         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 537         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 538         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 539         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 540         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 541         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 542         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 543         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 544 };
 545
 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 547                                                 /* NT mV Trans mV db    */
 548         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 549         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 550         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 551         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 552         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 553         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 554         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 555         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 556         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 557         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 558 };
 559
 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 561                                                 /* NT mV Trans mV db    */
 562         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 563         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 564         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 565         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 566         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 567         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 568         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 569 };
 570
 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 572                                                 /* NT mV Trans mV db    */
 573         { 0xA, 0x33, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 574         { 0xA, 0x47, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 575         { 0xC, 0x64, 0x30, 0x00, 0x0F },        /* 350   700      6.0   */
 576         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 350   900      8.2   */
 577         { 0xA, 0x46, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 578         { 0xC, 0x64, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 579         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 580         { 0xC, 0x61, 0x3F, 0x00, 0x00 },        /* 650   700      0.6   */
 581         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 600   900      3.5   */
 582         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 583 };
 584
 585 struct icl_mg_phy_ddi_buf_trans {
 586         u32 cri_txdeemph_override_11_6;
 587         u32 cri_txdeemph_override_5_0;
 588         u32 cri_txdeemph_override_17_12;
 589 };
 590
 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
 592                                 /* Voltage swing  pre-emphasis */
 593         { 0x18, 0x00, 0x00 },   /* 0              0   */
 594         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 595         { 0x24, 0x00, 0x0C },   /* 0              2   */
 596         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 597         { 0x21, 0x00, 0x00 },   /* 1              0   */
 598         { 0x2B, 0x00, 0x08 },   /* 1              1   */
 599         { 0x30, 0x00, 0x0F },   /* 1              2   */
 600         { 0x31, 0x00, 0x03 },   /* 2              0   */
 601         { 0x34, 0x00, 0x0B },   /* 2              1   */
 602         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 603 };
 604
 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
 606                                 /* Voltage swing  pre-emphasis */
 607         { 0x18, 0x00, 0x00 },   /* 0              0   */
 608         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 609         { 0x24, 0x00, 0x0C },   /* 0              2   */
 610         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 611         { 0x26, 0x00, 0x00 },   /* 1              0   */
 612         { 0x2C, 0x00, 0x07 },   /* 1              1   */
 613         { 0x33, 0x00, 0x0C },   /* 1              2   */
 614         { 0x2E, 0x00, 0x00 },   /* 2              0   */
 615         { 0x36, 0x00, 0x09 },   /* 2              1   */
 616         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 617 };
 618
 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
 620                                 /* HDMI Preset  VS      Pre-emph */
 621         { 0x1A, 0x0, 0x0 },     /* 1            400mV   0dB */
 622         { 0x20, 0x0, 0x0 },     /* 2            500mV   0dB */
 623         { 0x29, 0x0, 0x0 },     /* 3            650mV   0dB */
 624         { 0x32, 0x0, 0x0 },     /* 4            800mV   0dB */
 625         { 0x3F, 0x0, 0x0 },     /* 5            1000mV  0dB */
 626         { 0x3A, 0x0, 0x5 },     /* 6            Full    -1.5 dB */
 627         { 0x39, 0x0, 0x6 },     /* 7            Full    -1.8 dB */
 628         { 0x38, 0x0, 0x7 },     /* 8            Full    -2 dB */
 629         { 0x37, 0x0, 0x8 },     /* 9            Full    -2.5 dB */
 630         { 0x36, 0x0, 0x9 },     /* 10           Full    -3 dB */
 631 };
 632
 633 struct tgl_dkl_phy_ddi_buf_trans {
 634         u32 dkl_vswing_control;
 635         u32 dkl_preshoot_control;
 636         u32 dkl_de_emphasis_control;
 637 };
 638
 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
 640                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 641         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 642         { 0x5, 0x0, 0x03 },     /* 0    1       400mV           3.5 dB */
 643         { 0x2, 0x0, 0x0b },     /* 0    2       400mV           6 dB */
 644         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 645         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 646         { 0x2, 0x0, 0x03 },     /* 1    1       600mV           3.5 dB */
 647         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 648         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 649         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 650         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 651 };
 652
 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
 654                                 /* HDMI Preset  VS      Pre-emph */
 655         { 0x7, 0x0, 0x0 },      /* 1            400mV   0dB */
 656         { 0x6, 0x0, 0x0 },      /* 2            500mV   0dB */
 657         { 0x4, 0x0, 0x0 },      /* 3            650mV   0dB */
 658         { 0x2, 0x0, 0x0 },      /* 4            800mV   0dB */
 659         { 0x0, 0x0, 0x0 },      /* 5            1000mV  0dB */
 660         { 0x0, 0x0, 0x5 },      /* 6            Full    -1.5 dB */
 661         { 0x0, 0x0, 0x6 },      /* 7            Full    -1.8 dB */
 662         { 0x0, 0x0, 0x7 },      /* 8            Full    -2 dB */
 663         { 0x0, 0x0, 0x8 },      /* 9            Full    -2.5 dB */
 664         { 0x0, 0x0, 0xA },      /* 10           Full    -3 dB */
 665 };
 666
 667 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
 668                                                 /* NT mV Trans mV db    */
 669         { 0xA, 0x32, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 670         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 671         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 672         { 0x6, 0x7D, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 673         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 674         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 675         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 676         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 677         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 678         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 679 };
 680
 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
 682                                                 /* NT mV Trans mV db    */
 683         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 684         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 685         { 0xC, 0x63, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 686         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 687         { 0xA, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 688         { 0xC, 0x63, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 689         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 690         { 0xC, 0x61, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 691         { 0x6, 0x7B, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 692         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 693 };
 694
 695 static const struct ddi_buf_trans *
 696 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 697 {
 698         if (dev_priv->vbt.edp.low_vswing) {
 699                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 700                 return bdw_ddi_translations_edp;
 701         } else {
 702                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 703                 return bdw_ddi_translations_dp;
 704         }
 705 }
 706
 707 static const struct ddi_buf_trans *
 708 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 709 {
 710         if (IS_SKL_ULX(dev_priv)) {
 711                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 712                 return skl_y_ddi_translations_dp;
 713         } else if (IS_SKL_ULT(dev_priv)) {
 714                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 715                 return skl_u_ddi_translations_dp;
 716         } else {
 717                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 718                 return skl_ddi_translations_dp;
 719         }
 720 }
 721
 722 static const struct ddi_buf_trans *
 723 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 724 {
 725         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 726                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 727                 return kbl_y_ddi_translations_dp;
 728         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 729                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 730                 return kbl_u_ddi_translations_dp;
 731         } else {
 732                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 733                 return kbl_ddi_translations_dp;
 734         }
 735 }
 736
 737 static const struct ddi_buf_trans *
 738 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 739 {
 740         if (dev_priv->vbt.edp.low_vswing) {
 741                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 742                     IS_CFL_ULX(dev_priv)) {
 743                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 744                         return skl_y_ddi_translations_edp;
 745                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 746                            IS_CFL_ULT(dev_priv)) {
 747                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 748                         return skl_u_ddi_translations_edp;
 749                 } else {
 750                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 751                         return skl_ddi_translations_edp;
 752                 }
 753         }
 754
 755         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 756                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 757         else
 758                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 759 }
 760
 761 static const struct ddi_buf_trans *
 762 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 763 {
 764         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 765             IS_CFL_ULX(dev_priv)) {
 766                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 767                 return skl_y_ddi_translations_hdmi;
 768         } else {
 769                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 770                 return skl_ddi_translations_hdmi;
 771         }
 772 }
 773
 774 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 775 {
 776         /* Only DDIA and DDIE can select the 10th register with DP */
 777         if (port == PORT_A || port == PORT_E)
 778                 return min(n_entries, 10);
 779         else
 780                 return min(n_entries, 9);
 781 }
 782
 783 static const struct ddi_buf_trans *
 784 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 785                            enum port port, int *n_entries)
 786 {
 787         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 788                 const struct ddi_buf_trans *ddi_translations =
 789                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 790                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 791                 return ddi_translations;
 792         } else if (IS_SKYLAKE(dev_priv)) {
 793                 const struct ddi_buf_trans *ddi_translations =
 794                         skl_get_buf_trans_dp(dev_priv, n_entries);
 795                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 796                 return ddi_translations;
 797         } else if (IS_BROADWELL(dev_priv)) {
 798                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 799                 return  bdw_ddi_translations_dp;
 800         } else if (IS_HASWELL(dev_priv)) {
 801                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 802                 return hsw_ddi_translations_dp;
 803         }
 804
 805         *n_entries = 0;
 806         return NULL;
 807 }
 808
 809 static const struct ddi_buf_trans *
 810 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 811                             enum port port, int *n_entries)
 812 {
 813         if (IS_GEN9_BC(dev_priv)) {
 814                 const struct ddi_buf_trans *ddi_translations =
 815                         skl_get_buf_trans_edp(dev_priv, n_entries);
 816                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 817                 return ddi_translations;
 818         } else if (IS_BROADWELL(dev_priv)) {
 819                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 820         } else if (IS_HASWELL(dev_priv)) {
 821                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 822                 return hsw_ddi_translations_dp;
 823         }
 824
 825         *n_entries = 0;
 826         return NULL;
 827 }
 828
 829 static const struct ddi_buf_trans *
 830 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 831                             int *n_entries)
 832 {
 833         if (IS_BROADWELL(dev_priv)) {
 834                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 835                 return bdw_ddi_translations_fdi;
 836         } else if (IS_HASWELL(dev_priv)) {
 837                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 838                 return hsw_ddi_translations_fdi;
 839         }
 840
 841         *n_entries = 0;
 842         return NULL;
 843 }
 844
 845 static const struct ddi_buf_trans *
 846 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 847                              int *n_entries)
 848 {
 849         if (IS_GEN9_BC(dev_priv)) {
 850                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 851         } else if (IS_BROADWELL(dev_priv)) {
 852                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 853                 return bdw_ddi_translations_hdmi;
 854         } else if (IS_HASWELL(dev_priv)) {
 855                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 856                 return hsw_ddi_translations_hdmi;
 857         }
 858
 859         *n_entries = 0;
 860         return NULL;
 861 }
 862
 863 static const struct bxt_ddi_buf_trans *
 864 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 865 {
 866         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 867         return bxt_ddi_translations_dp;
 868 }
 869
 870 static const struct bxt_ddi_buf_trans *
 871 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 872 {
 873         if (dev_priv->vbt.edp.low_vswing) {
 874                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 875                 return bxt_ddi_translations_edp;
 876         }
 877
 878         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 879 }
 880
 881 static const struct bxt_ddi_buf_trans *
 882 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 883 {
 884         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 885         return bxt_ddi_translations_hdmi;
 886 }
 887
 888 static const struct cnl_ddi_buf_trans *
 889 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 890 {
 891         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 892
 893         if (voltage == VOLTAGE_INFO_0_85V) {
 894                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 895                 return cnl_ddi_translations_hdmi_0_85V;
 896         } else if (voltage == VOLTAGE_INFO_0_95V) {
 897                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 898                 return cnl_ddi_translations_hdmi_0_95V;
 899         } else if (voltage == VOLTAGE_INFO_1_05V) {
 900                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 901                 return cnl_ddi_translations_hdmi_1_05V;
 902         } else {
 903                 *n_entries = 1; /* shut up gcc */
 904                 MISSING_CASE(voltage);
 905         }
 906         return NULL;
 907 }
 908
 909 static const struct cnl_ddi_buf_trans *
 910 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 911 {
 912         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 913
 914         if (voltage == VOLTAGE_INFO_0_85V) {
 915                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 916                 return cnl_ddi_translations_dp_0_85V;
 917         } else if (voltage == VOLTAGE_INFO_0_95V) {
 918                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 919                 return cnl_ddi_translations_dp_0_95V;
 920         } else if (voltage == VOLTAGE_INFO_1_05V) {
 921                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 922                 return cnl_ddi_translations_dp_1_05V;
 923         } else {
 924                 *n_entries = 1; /* shut up gcc */
 925                 MISSING_CASE(voltage);
 926         }
 927         return NULL;
 928 }
 929
 930 static const struct cnl_ddi_buf_trans *
 931 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 932 {
 933         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 934
 935         if (dev_priv->vbt.edp.low_vswing) {
 936                 if (voltage == VOLTAGE_INFO_0_85V) {
 937                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 938                         return cnl_ddi_translations_edp_0_85V;
 939                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 940                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 941                         return cnl_ddi_translations_edp_0_95V;
 942                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 943                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 944                         return cnl_ddi_translations_edp_1_05V;
 945                 } else {
 946                         *n_entries = 1; /* shut up gcc */
 947                         MISSING_CASE(voltage);
 948                 }
 949                 return NULL;
 950         } else {
 951                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 952         }
 953 }
 954
 955 static const struct cnl_ddi_buf_trans *
 956 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 957                         int *n_entries)
 958 {
 959         if (type == INTEL_OUTPUT_HDMI) {
 960                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 961                 return icl_combo_phy_ddi_translations_hdmi;
 962         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 963                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 964                 return icl_combo_phy_ddi_translations_edp_hbr3;
 965         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 966                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 967                 return icl_combo_phy_ddi_translations_edp_hbr2;
 968         }
 969
 970         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 971         return icl_combo_phy_ddi_translations_dp_hbr2;
 972 }
 973
 974 static const struct icl_mg_phy_ddi_buf_trans *
 975 icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 976                      int *n_entries)
 977 {
 978         if (type == INTEL_OUTPUT_HDMI) {
 979                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
 980                 return icl_mg_phy_ddi_translations_hdmi;
 981         } else if (rate > 270000) {
 982                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
 983                 return icl_mg_phy_ddi_translations_hbr2_hbr3;
 984         }
 985
 986         *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
 987         return icl_mg_phy_ddi_translations_rbr_hbr;
 988 }
 989
 990 static const struct cnl_ddi_buf_trans *
 991 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 992                         int *n_entries)
 993 {
 994         if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
 995                 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
 996                 return ehl_combo_phy_ddi_translations_dp;
 997         }
 998
 999         return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
1000 }
1001
1002 static const struct cnl_ddi_buf_trans *
1003 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
1004                         int *n_entries)
1005 {
1006         if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
1007                 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
1008         } else if (rate > 270000) {
1009                 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1010                 return tgl_combo_phy_ddi_translations_dp_hbr2;
1011         }
1012
1013         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1014         return tgl_combo_phy_ddi_translations_dp_hbr;
1015 }
1016
1017 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
1018 {
1019         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1020         int n_entries, level, default_entry;
1021         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1022
1023         if (INTEL_GEN(dev_priv) >= 12) {
1024                 if (intel_phy_is_combo(dev_priv, phy))
1025                         tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
1026                                                 0, &n_entries);
1027                 else
1028                         n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1029                 default_entry = n_entries - 1;
1030         } else if (INTEL_GEN(dev_priv) == 11) {
1031                 if (intel_phy_is_combo(dev_priv, phy))
1032                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
1033                                                 0, &n_entries);
1034                 else
1035                         icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0,
1036                                              &n_entries);
1037                 default_entry = n_entries - 1;
1038         } else if (IS_CANNONLAKE(dev_priv)) {
1039                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1040                 default_entry = n_entries - 1;
1041         } else if (IS_GEN9_LP(dev_priv)) {
1042                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1043                 default_entry = n_entries - 1;
1044         } else if (IS_GEN9_BC(dev_priv)) {
1045                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1046                 default_entry = 8;
1047         } else if (IS_BROADWELL(dev_priv)) {
1048                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1049                 default_entry = 7;
1050         } else if (IS_HASWELL(dev_priv)) {
1051                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1052                 default_entry = 6;
1053         } else {
1054                 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1055                 return 0;
1056         }
1057
1058         if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1059                 return 0;
1060
1061         level = intel_bios_hdmi_level_shift(encoder);
1062         if (level < 0)
1063                 level = default_entry;
1064
1065         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1066                 level = n_entries - 1;
1067
1068         return level;
1069 }
1070
1071 /*
1072  * Starting with Haswell, DDI port buffers must be programmed with correct
1073  * values in advance. This function programs the correct values for
1074  * DP/eDP/FDI use cases.
1075  */
1076 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1077                                          const struct intel_crtc_state *crtc_state)
1078 {
1079         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1080         u32 iboost_bit = 0;
1081         int i, n_entries;
1082         enum port port = encoder->port;
1083         const struct ddi_buf_trans *ddi_translations;
1084
1085         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1086                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1087                                                                &n_entries);
1088         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1089                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
1090                                                                &n_entries);
1091         else
1092                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
1093                                                               &n_entries);
1094
1095         /* If we're boosting the current, set bit 31 of trans1 */
1096         if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1097                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1098
1099         for (i = 0; i < n_entries; i++) {
1100                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1101                                ddi_translations[i].trans1 | iboost_bit);
1102                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1103                                ddi_translations[i].trans2);
1104         }
1105 }
1106
1107 /*
1108  * Starting with Haswell, DDI port buffers must be programmed with correct
1109  * values in advance. This function programs the correct values for
1110  * HDMI/DVI use cases.
1111  */
1112 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1113                                            int level)
1114 {
1115         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1116         u32 iboost_bit = 0;
1117         int n_entries;
1118         enum port port = encoder->port;
1119         const struct ddi_buf_trans *ddi_translations;
1120
1121         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1122
1123         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1124                 return;
1125         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1126                 level = n_entries - 1;
1127
1128         /* If we're boosting the current, set bit 31 of trans1 */
1129         if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1130                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1131
1132         /* Entry 9 is for HDMI: */
1133         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1134                        ddi_translations[level].trans1 | iboost_bit);
1135         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1136                        ddi_translations[level].trans2);
1137 }
1138
1139 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1140                                     enum port port)
1141 {
1142         i915_reg_t reg = DDI_BUF_CTL(port);
1143         int i;
1144
1145         for (i = 0; i < 16; i++) {
1146                 udelay(1);
1147                 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
1148                         return;
1149         }
1150         drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
1151                 port_name(port));
1152 }
1153
1154 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1155 {
1156         switch (pll->info->id) {
1157         case DPLL_ID_WRPLL1:
1158                 return PORT_CLK_SEL_WRPLL1;
1159         case DPLL_ID_WRPLL2:
1160                 return PORT_CLK_SEL_WRPLL2;
1161         case DPLL_ID_SPLL:
1162                 return PORT_CLK_SEL_SPLL;
1163         case DPLL_ID_LCPLL_810:
1164                 return PORT_CLK_SEL_LCPLL_810;
1165         case DPLL_ID_LCPLL_1350:
1166                 return PORT_CLK_SEL_LCPLL_1350;
1167         case DPLL_ID_LCPLL_2700:
1168                 return PORT_CLK_SEL_LCPLL_2700;
1169         default:
1170                 MISSING_CASE(pll->info->id);
1171                 return PORT_CLK_SEL_NONE;
1172         }
1173 }
1174
1175 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1176                                   const struct intel_crtc_state *crtc_state)
1177 {
1178         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1179         int clock = crtc_state->port_clock;
1180         const enum intel_dpll_id id = pll->info->id;
1181
1182         switch (id) {
1183         default:
1184                 /*
1185                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1186                  * here, so do warn if this get passed in
1187                  */
1188                 MISSING_CASE(id);
1189                 return DDI_CLK_SEL_NONE;
1190         case DPLL_ID_ICL_TBTPLL:
1191                 switch (clock) {
1192                 case 162000:
1193                         return DDI_CLK_SEL_TBT_162;
1194                 case 270000:
1195                         return DDI_CLK_SEL_TBT_270;
1196                 case 540000:
1197                         return DDI_CLK_SEL_TBT_540;
1198                 case 810000:
1199                         return DDI_CLK_SEL_TBT_810;
1200                 default:
1201                         MISSING_CASE(clock);
1202                         return DDI_CLK_SEL_NONE;
1203                 }
1204         case DPLL_ID_ICL_MGPLL1:
1205         case DPLL_ID_ICL_MGPLL2:
1206         case DPLL_ID_ICL_MGPLL3:
1207         case DPLL_ID_ICL_MGPLL4:
1208         case DPLL_ID_TGL_MGPLL5:
1209         case DPLL_ID_TGL_MGPLL6:
1210                 return DDI_CLK_SEL_MG;
1211         }
1212 }
1213
1214 /* Starting with Haswell, different DDI ports can work in FDI mode for
1215  * connection to the PCH-located connectors. For this, it is necessary to train
1216  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1217  *
1218  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1219  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1220  * DDI A (which is used for eDP)
1221  */
1222
1223 void hsw_fdi_link_train(struct intel_encoder *encoder,
1224                         const struct intel_crtc_state *crtc_state)
1225 {
1226         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1227         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1228         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1229
1230         intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1231
1232         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1233          * mode set "sequence for CRT port" document:
1234          * - TP1 to TP2 time with the default value
1235          * - FDI delay to 90h
1236          *
1237          * WaFDIAutoLinkSetTimingOverrride:hsw
1238          */
1239         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1240                        FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1241
1242         /* Enable the PCH Receiver FDI PLL */
1243         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1244                      FDI_RX_PLL_ENABLE |
1245                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1246         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1247         intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1248         udelay(220);
1249
1250         /* Switch from Rawclk to PCDclk */
1251         rx_ctl_val |= FDI_PCDCLK;
1252         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1253
1254         /* Configure Port Clock Select */
1255         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1256         intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1257         drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1258
1259         /* Start the training iterating through available voltages and emphasis,
1260          * testing each value twice. */
1261         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1262                 /* Configure DP_TP_CTL with auto-training */
1263                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1264                                DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE);
1265
1266                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1267                  * DDI E does not support port reversal, the functionality is
1268                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1269                  * port reversal bit */
1270                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1271                                DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1272                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1273
1274                 udelay(600);
1275
1276                 /* Program PCH FDI Receiver TU */
1277                 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1278
1279                 /* Enable PCH FDI Receiver with auto-training */
1280                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1281                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1282                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1283
1284                 /* Wait for FDI receiver lane calibration */
1285                 udelay(30);
1286
1287                 /* Unset FDI_RX_MISC pwrdn lanes */
1288                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1289                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1290                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1291                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1292
1293                 /* Wait for FDI auto training time */
1294                 udelay(5);
1295
1296                 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1297                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1298                         drm_dbg_kms(&dev_priv->drm,
1299                                     "FDI link training done on step %d\n", i);
1300                         break;
1301                 }
1302
1303                 /*
1304                  * Leave things enabled even if we failed to train FDI.
1305                  * Results in less fireworks from the state checker.
1306                  */
1307                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1308                         drm_err(&dev_priv->drm, "FDI link training failed!\n");
1309                         break;
1310                 }
1311
1312                 rx_ctl_val &= ~FDI_RX_ENABLE;
1313                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1314                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1315
1316                 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1317                 temp &= ~DDI_BUF_CTL_ENABLE;
1318                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1319                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1320
1321                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1322                 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1323                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1324                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1325                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1326                 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1327
1328                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1329
1330                 /* Reset FDI_RX_MISC pwrdn lanes */
1331                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1332                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1333                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1334                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1335                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1336         }
1337
1338         /* Enable normal pixel sending for FDI */
1339         intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1340                        DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE);
1341 }
1342
1343 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1344 {
1345         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1346         struct intel_digital_port *intel_dig_port =
1347                 enc_to_dig_port(encoder);
1348
1349         intel_dp->DP = intel_dig_port->saved_port_bits |
1350                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1351         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1352 }
1353
1354 static struct intel_encoder *
1355 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1356 {
1357         struct drm_device *dev = crtc->base.dev;
1358         struct intel_encoder *encoder, *ret = NULL;
1359         int num_encoders = 0;
1360
1361         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1362                 ret = encoder;
1363                 num_encoders++;
1364         }
1365
1366         if (num_encoders != 1)
1367                 drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n",
1368                          num_encoders,
1369                          pipe_name(crtc->pipe));
1370
1371         BUG_ON(ret == NULL);
1372         return ret;
1373 }
1374
1375 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1376                                  enum port port)
1377 {
1378         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1379
1380         switch (val) {
1381         case DDI_CLK_SEL_NONE:
1382                 return 0;
1383         case DDI_CLK_SEL_TBT_162:
1384                 return 162000;
1385         case DDI_CLK_SEL_TBT_270:
1386                 return 270000;
1387         case DDI_CLK_SEL_TBT_540:
1388                 return 540000;
1389         case DDI_CLK_SEL_TBT_810:
1390                 return 810000;
1391         default:
1392                 MISSING_CASE(val);
1393                 return 0;
1394         }
1395 }
1396
1397 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1398 {
1399         int dotclock;
1400
1401         if (pipe_config->has_pch_encoder)
1402                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1403                                                     &pipe_config->fdi_m_n);
1404         else if (intel_crtc_has_dp_encoder(pipe_config))
1405                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1406                                                     &pipe_config->dp_m_n);
1407         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1408                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1409         else
1410                 dotclock = pipe_config->port_clock;
1411
1412         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1413             !intel_crtc_has_dp_encoder(pipe_config))
1414                 dotclock *= 2;
1415
1416         if (pipe_config->pixel_multiplier)
1417                 dotclock /= pipe_config->pixel_multiplier;
1418
1419         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1420 }
1421
1422 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1423                                 struct intel_crtc_state *pipe_config)
1424 {
1425         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1426         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1427
1428         if (intel_phy_is_tc(dev_priv, phy) &&
1429             intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1430             DPLL_ID_ICL_TBTPLL)
1431                 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1432                                                                 encoder->port);
1433         else
1434                 pipe_config->port_clock =
1435                         intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
1436
1437         ddi_dotclock_get(pipe_config);
1438 }
1439
1440 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1441                           const struct drm_connector_state *conn_state)
1442 {
1443         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1444         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1445         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1446         u32 temp;
1447
1448         if (!intel_crtc_has_dp_encoder(crtc_state))
1449                 return;
1450
1451         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1452
1453         temp = DP_MSA_MISC_SYNC_CLOCK;
1454
1455         switch (crtc_state->pipe_bpp) {
1456         case 18:
1457                 temp |= DP_MSA_MISC_6_BPC;
1458                 break;
1459         case 24:
1460                 temp |= DP_MSA_MISC_8_BPC;
1461                 break;
1462         case 30:
1463                 temp |= DP_MSA_MISC_10_BPC;
1464                 break;
1465         case 36:
1466                 temp |= DP_MSA_MISC_12_BPC;
1467                 break;
1468         default:
1469                 MISSING_CASE(crtc_state->pipe_bpp);
1470                 break;
1471         }
1472
1473         /* nonsense combination */
1474         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1475                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1476
1477         if (crtc_state->limited_color_range)
1478                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1479
1480         /*
1481          * As per DP 1.2 spec section 2.3.4.3 while sending
1482          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1483          * colorspace information.
1484          */
1485         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1486                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1487
1488         /*
1489          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1490          * of Color Encoding Format and Content Color Gamut] while sending
1491          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1492          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1493          */
1494         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1495                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1496
1497         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1498 }
1499
1500 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1501 {
1502         if (master_transcoder == TRANSCODER_EDP)
1503                 return 0;
1504         else
1505                 return master_transcoder + 1;
1506 }
1507
1508 /*
1509  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1510  *
1511  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1512  * intel_ddi_config_transcoder_func().
1513  */
1514 static u32
1515 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1516 {
1517         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1518         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1519         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1520         enum pipe pipe = crtc->pipe;
1521         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1522         enum port port = encoder->port;
1523         u32 temp;
1524
1525         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1526         temp = TRANS_DDI_FUNC_ENABLE;
1527         if (INTEL_GEN(dev_priv) >= 12)
1528                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1529         else
1530                 temp |= TRANS_DDI_SELECT_PORT(port);
1531
1532         switch (crtc_state->pipe_bpp) {
1533         case 18:
1534                 temp |= TRANS_DDI_BPC_6;
1535                 break;
1536         case 24:
1537                 temp |= TRANS_DDI_BPC_8;
1538                 break;
1539         case 30:
1540                 temp |= TRANS_DDI_BPC_10;
1541                 break;
1542         case 36:
1543                 temp |= TRANS_DDI_BPC_12;
1544                 break;
1545         default:
1546                 BUG();
1547         }
1548
1549         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1550                 temp |= TRANS_DDI_PVSYNC;
1551         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1552                 temp |= TRANS_DDI_PHSYNC;
1553
1554         if (cpu_transcoder == TRANSCODER_EDP) {
1555                 switch (pipe) {
1556                 case PIPE_A:
1557                         /* On Haswell, can only use the always-on power well for
1558                          * eDP when not using the panel fitter, and when not
1559                          * using motion blur mitigation (which we don't
1560                          * support). */
1561                         if (crtc_state->pch_pfit.force_thru)
1562                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1563                         else
1564                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1565                         break;
1566                 case PIPE_B:
1567                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1568                         break;
1569                 case PIPE_C:
1570                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1571                         break;
1572                 default:
1573                         BUG();
1574                         break;
1575                 }
1576         }
1577
1578         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1579                 if (crtc_state->has_hdmi_sink)
1580                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1581                 else
1582                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1583
1584                 if (crtc_state->hdmi_scrambling)
1585                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1586                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1587                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1588         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1589                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1590                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1591         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1592                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1593                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1594
1595                 if (INTEL_GEN(dev_priv) >= 12) {
1596                         enum transcoder master;
1597
1598                         master = crtc_state->mst_master_transcoder;
1599                         drm_WARN_ON(&dev_priv->drm,
1600                                     master == INVALID_TRANSCODER);
1601                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1602                 }
1603         } else {
1604                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1605                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1606         }
1607
1608         if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1609             crtc_state->master_transcoder != INVALID_TRANSCODER) {
1610                 u8 master_select =
1611                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1612
1613                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1614                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1615         }
1616
1617         return temp;
1618 }
1619
1620 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1621 {
1622         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1623         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1624         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1625         u32 ctl;
1626
1627         if (INTEL_GEN(dev_priv) >= 11) {
1628                 enum transcoder master_transcoder = crtc_state->master_transcoder;
1629                 u32 ctl2 = 0;
1630
1631                 if (master_transcoder != INVALID_TRANSCODER) {
1632                         u8 master_select =
1633                                 bdw_trans_port_sync_master_select(master_transcoder);
1634
1635                         ctl2 |= PORT_SYNC_MODE_ENABLE |
1636                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1637                 }
1638
1639                 intel_de_write(dev_priv,
1640                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
1641         }
1642
1643         ctl = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1644         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1645                 ctl |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1646         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1647 }
1648
1649 /*
1650  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1651  * bit.
1652  */
1653 static void
1654 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1655 {
1656         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1658         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1659         u32 ctl;
1660
1661         ctl = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1662         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1663         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1664 }
1665
1666 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1667 {
1668         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1669         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1670         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1671         u32 ctl;
1672
1673         if (INTEL_GEN(dev_priv) >= 11)
1674                 intel_de_write(dev_priv,
1675                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
1676
1677         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1678
1679         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1680
1681         if (IS_GEN_RANGE(dev_priv, 8, 10))
1682                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
1683                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
1684
1685         if (INTEL_GEN(dev_priv) >= 12) {
1686                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
1687                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
1688                                  TRANS_DDI_MODE_SELECT_MASK);
1689                 }
1690         } else {
1691                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
1692         }
1693
1694         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1695
1696         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1697             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1698                 drm_dbg_kms(&dev_priv->drm,
1699                             "Quirk Increase DDI disabled time\n");
1700                 /* Quirk time at 100ms for reliable operation */
1701                 msleep(100);
1702         }
1703 }
1704
1705 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1706                                      bool enable)
1707 {
1708         struct drm_device *dev = intel_encoder->base.dev;
1709         struct drm_i915_private *dev_priv = to_i915(dev);
1710         intel_wakeref_t wakeref;
1711         enum pipe pipe = 0;
1712         int ret = 0;
1713         u32 tmp;
1714
1715         wakeref = intel_display_power_get_if_enabled(dev_priv,
1716                                                      intel_encoder->power_domain);
1717         if (drm_WARN_ON(dev, !wakeref))
1718                 return -ENXIO;
1719
1720         if (drm_WARN_ON(dev,
1721                         !intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1722                 ret = -EIO;
1723                 goto out;
1724         }
1725
1726         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe));
1727         if (enable)
1728                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1729         else
1730                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1731         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp);
1732 out:
1733         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1734         return ret;
1735 }
1736
1737 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1738 {
1739         struct drm_device *dev = intel_connector->base.dev;
1740         struct drm_i915_private *dev_priv = to_i915(dev);
1741         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1742         int type = intel_connector->base.connector_type;
1743         enum port port = encoder->port;
1744         enum transcoder cpu_transcoder;
1745         intel_wakeref_t wakeref;
1746         enum pipe pipe = 0;
1747         u32 tmp;
1748         bool ret;
1749
1750         wakeref = intel_display_power_get_if_enabled(dev_priv,
1751                                                      encoder->power_domain);
1752         if (!wakeref)
1753                 return false;
1754
1755         if (!encoder->get_hw_state(encoder, &pipe)) {
1756                 ret = false;
1757                 goto out;
1758         }
1759
1760         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
1761                 cpu_transcoder = TRANSCODER_EDP;
1762         else
1763                 cpu_transcoder = (enum transcoder) pipe;
1764
1765         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1766
1767         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1768         case TRANS_DDI_MODE_SELECT_HDMI:
1769         case TRANS_DDI_MODE_SELECT_DVI:
1770                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1771                 break;
1772
1773         case TRANS_DDI_MODE_SELECT_DP_SST:
1774                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1775                       type == DRM_MODE_CONNECTOR_DisplayPort;
1776                 break;
1777
1778         case TRANS_DDI_MODE_SELECT_DP_MST:
1779                 /* if the transcoder is in MST state then
1780                  * connector isn't connected */
1781                 ret = false;
1782                 break;
1783
1784         case TRANS_DDI_MODE_SELECT_FDI:
1785                 ret = type == DRM_MODE_CONNECTOR_VGA;
1786                 break;
1787
1788         default:
1789                 ret = false;
1790                 break;
1791         }
1792
1793 out:
1794         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1795
1796         return ret;
1797 }
1798
1799 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1800                                         u8 *pipe_mask, bool *is_dp_mst)
1801 {
1802         struct drm_device *dev = encoder->base.dev;
1803         struct drm_i915_private *dev_priv = to_i915(dev);
1804         enum port port = encoder->port;
1805         intel_wakeref_t wakeref;
1806         enum pipe p;
1807         u32 tmp;
1808         u8 mst_pipe_mask;
1809
1810         *pipe_mask = 0;
1811         *is_dp_mst = false;
1812
1813         wakeref = intel_display_power_get_if_enabled(dev_priv,
1814                                                      encoder->power_domain);
1815         if (!wakeref)
1816                 return;
1817
1818         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1819         if (!(tmp & DDI_BUF_CTL_ENABLE))
1820                 goto out;
1821
1822         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
1823                 tmp = intel_de_read(dev_priv,
1824                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1825
1826                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1827                 default:
1828                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1829                         /* fallthrough */
1830                 case TRANS_DDI_EDP_INPUT_A_ON:
1831                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1832                         *pipe_mask = BIT(PIPE_A);
1833                         break;
1834                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1835                         *pipe_mask = BIT(PIPE_B);
1836                         break;
1837                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1838                         *pipe_mask = BIT(PIPE_C);
1839                         break;
1840                 }
1841
1842                 goto out;
1843         }
1844
1845         mst_pipe_mask = 0;
1846         for_each_pipe(dev_priv, p) {
1847                 enum transcoder cpu_transcoder = (enum transcoder)p;
1848                 unsigned int port_mask, ddi_select;
1849                 intel_wakeref_t trans_wakeref;
1850
1851                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
1852                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1853                 if (!trans_wakeref)
1854                         continue;
1855
1856                 if (INTEL_GEN(dev_priv) >= 12) {
1857                         port_mask = TGL_TRANS_DDI_PORT_MASK;
1858                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
1859                 } else {
1860                         port_mask = TRANS_DDI_PORT_MASK;
1861                         ddi_select = TRANS_DDI_SELECT_PORT(port);
1862                 }
1863
1864                 tmp = intel_de_read(dev_priv,
1865                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
1866                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
1867                                         trans_wakeref);
1868
1869                 if ((tmp & port_mask) != ddi_select)
1870                         continue;
1871
1872                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1873                     TRANS_DDI_MODE_SELECT_DP_MST)
1874                         mst_pipe_mask |= BIT(p);
1875
1876                 *pipe_mask |= BIT(p);
1877         }
1878
1879         if (!*pipe_mask)
1880                 drm_dbg_kms(&dev_priv->drm,
1881                             "No pipe for [ENCODER:%d:%s] found\n",
1882                             encoder->base.base.id, encoder->base.name);
1883
1884         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1885                 drm_dbg_kms(&dev_priv->drm,
1886                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
1887                             encoder->base.base.id, encoder->base.name,
1888                             *pipe_mask);
1889                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
1890         }
1891
1892         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
1893                 drm_dbg_kms(&dev_priv->drm,
1894                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
1895                             encoder->base.base.id, encoder->base.name,
1896                             *pipe_mask, mst_pipe_mask);
1897         else
1898                 *is_dp_mst = mst_pipe_mask;
1899
1900 out:
1901         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
1902                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
1903                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1904                             BXT_PHY_LANE_POWERDOWN_ACK |
1905                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1906                         drm_err(&dev_priv->drm,
1907                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
1908                                 encoder->base.base.id, encoder->base.name, tmp);
1909         }
1910
1911         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1912 }
1913
1914 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1915                             enum pipe *pipe)
1916 {
1917         u8 pipe_mask;
1918         bool is_mst;
1919
1920         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
1921
1922         if (is_mst || !pipe_mask)
1923                 return false;
1924
1925         *pipe = ffs(pipe_mask) - 1;
1926
1927         return true;
1928 }
1929
1930 static inline enum intel_display_power_domain
1931 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
1932 {
1933         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
1934          * DC states enabled at the same time, while for driver initiated AUX
1935          * transfers we need the same AUX IOs to be powered but with DC states
1936          * disabled. Accordingly use the AUX power domain here which leaves DC
1937          * states enabled.
1938          * However, for non-A AUX ports the corresponding non-EDP transcoders
1939          * would have already enabled power well 2 and DC_OFF. This means we can
1940          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
1941          * specific AUX_IO reference without powering up any extra wells.
1942          * Note that PSR is enabled only on Port A even though this function
1943          * returns the correct domain for other ports too.
1944          */
1945         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
1946                                               intel_aux_power_domain(dig_port);
1947 }
1948
1949 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
1950                                         struct intel_crtc_state *crtc_state)
1951 {
1952         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1953         struct intel_digital_port *dig_port;
1954         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1955
1956         /*
1957          * TODO: Add support for MST encoders. Atm, the following should never
1958          * happen since fake-MST encoders don't set their get_power_domains()
1959          * hook.
1960          */
1961         if (drm_WARN_ON(&dev_priv->drm,
1962                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
1963                 return;
1964
1965         dig_port = enc_to_dig_port(encoder);
1966
1967         if (!intel_phy_is_tc(dev_priv, phy) ||
1968             dig_port->tc_mode != TC_PORT_TBT_ALT)
1969                 intel_display_power_get(dev_priv,
1970                                         dig_port->ddi_io_power_domain);
1971
1972         /*
1973          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
1974          * ports.
1975          */
1976         if (intel_crtc_has_dp_encoder(crtc_state) ||
1977             intel_phy_is_tc(dev_priv, phy))
1978                 intel_display_power_get(dev_priv,
1979                                         intel_ddi_main_link_aux_domain(dig_port));
1980
1981         /*
1982          * VDSC power is needed when DSC is enabled
1983          */
1984         if (crtc_state->dsc.compression_enable)
1985                 intel_display_power_get(dev_priv,
1986                                         intel_dsc_power_domain(crtc_state));
1987 }
1988
1989 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
1990                                  const struct intel_crtc_state *crtc_state)
1991 {
1992         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1993         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1994         enum port port = encoder->port;
1995         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1996
1997         if (cpu_transcoder != TRANSCODER_EDP) {
1998                 if (INTEL_GEN(dev_priv) >= 12)
1999                         intel_de_write(dev_priv,
2000                                        TRANS_CLK_SEL(cpu_transcoder),
2001                                        TGL_TRANS_CLK_SEL_PORT(port));
2002                 else
2003                         intel_de_write(dev_priv,
2004                                        TRANS_CLK_SEL(cpu_transcoder),
2005                                        TRANS_CLK_SEL_PORT(port));
2006         }
2007 }
2008
2009 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2010 {
2011         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2012         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2013
2014         if (cpu_transcoder != TRANSCODER_EDP) {
2015                 if (INTEL_GEN(dev_priv) >= 12)
2016                         intel_de_write(dev_priv,
2017                                        TRANS_CLK_SEL(cpu_transcoder),
2018                                        TGL_TRANS_CLK_SEL_DISABLED);
2019                 else
2020                         intel_de_write(dev_priv,
2021                                        TRANS_CLK_SEL(cpu_transcoder),
2022                                        TRANS_CLK_SEL_DISABLED);
2023         }
2024 }
2025
2026 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2027                                 enum port port, u8 iboost)
2028 {
2029         u32 tmp;
2030
2031         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2032         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2033         if (iboost)
2034                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2035         else
2036                 tmp |= BALANCE_LEG_DISABLE(port);
2037         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2038 }
2039
2040 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2041                                int level, enum intel_output_type type)
2042 {
2043         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2045         enum port port = encoder->port;
2046         u8 iboost;
2047
2048         if (type == INTEL_OUTPUT_HDMI)
2049                 iboost = intel_bios_hdmi_boost_level(encoder);
2050         else
2051                 iboost = intel_bios_dp_boost_level(encoder);
2052
2053         if (iboost == 0) {
2054                 const struct ddi_buf_trans *ddi_translations;
2055                 int n_entries;
2056
2057                 if (type == INTEL_OUTPUT_HDMI)
2058                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2059                 else if (type == INTEL_OUTPUT_EDP)
2060                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2061                 else
2062                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2063
2064                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2065                         return;
2066                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2067                         level = n_entries - 1;
2068
2069                 iboost = ddi_translations[level].i_boost;
2070         }
2071
2072         /* Make sure that the requested I_boost is valid */
2073         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2074                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2075                 return;
2076         }
2077
2078         _skl_ddi_set_iboost(dev_priv, port, iboost);
2079
2080         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2081                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2082 }
2083
2084 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2085                                     int level, enum intel_output_type type)
2086 {
2087         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2088         const struct bxt_ddi_buf_trans *ddi_translations;
2089         enum port port = encoder->port;
2090         int n_entries;
2091
2092         if (type == INTEL_OUTPUT_HDMI)
2093                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2094         else if (type == INTEL_OUTPUT_EDP)
2095                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2096         else
2097                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2098
2099         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2100                 return;
2101         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2102                 level = n_entries - 1;
2103
2104         bxt_ddi_phy_set_signal_level(dev_priv, port,
2105                                      ddi_translations[level].margin,
2106                                      ddi_translations[level].scale,
2107                                      ddi_translations[level].enable,
2108                                      ddi_translations[level].deemphasis);
2109 }
2110
2111 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2112 {
2113         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2114         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2115         enum port port = encoder->port;
2116         enum phy phy = intel_port_to_phy(dev_priv, port);
2117         int n_entries;
2118
2119         if (INTEL_GEN(dev_priv) >= 12) {
2120                 if (intel_phy_is_combo(dev_priv, phy))
2121                         tgl_get_combo_buf_trans(dev_priv, encoder->type,
2122                                                 intel_dp->link_rate, &n_entries);
2123                 else
2124                         n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2125         } else if (INTEL_GEN(dev_priv) == 11) {
2126                 if (IS_ELKHARTLAKE(dev_priv))
2127                         ehl_get_combo_buf_trans(dev_priv, encoder->type,
2128                                                 intel_dp->link_rate, &n_entries);
2129                 else if (intel_phy_is_combo(dev_priv, phy))
2130                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2131                                                 intel_dp->link_rate, &n_entries);
2132                 else
2133                         icl_get_mg_buf_trans(dev_priv, encoder->type,
2134                                              intel_dp->link_rate, &n_entries);
2135         } else if (IS_CANNONLAKE(dev_priv)) {
2136                 if (encoder->type == INTEL_OUTPUT_EDP)
2137                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2138                 else
2139                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2140         } else if (IS_GEN9_LP(dev_priv)) {
2141                 if (encoder->type == INTEL_OUTPUT_EDP)
2142                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2143                 else
2144                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2145         } else {
2146                 if (encoder->type == INTEL_OUTPUT_EDP)
2147                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2148                 else
2149                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2150         }
2151
2152         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2153                 n_entries = 1;
2154         if (drm_WARN_ON(&dev_priv->drm,
2155                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2156                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2157
2158         return index_to_dp_signal_levels[n_entries - 1] &
2159                 DP_TRAIN_VOLTAGE_SWING_MASK;
2160 }
2161
2162 /*
2163  * We assume that the full set of pre-emphasis values can be
2164  * used on all DDI platforms. Should that change we need to
2165  * rethink this code.
2166  */
2167 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2168 {
2169         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2170         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2171                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2172         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2173                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2174         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2175                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2176         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2177         default:
2178                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2179         }
2180 }
2181
2182 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2183                                    int level, enum intel_output_type type)
2184 {
2185         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2186         const struct cnl_ddi_buf_trans *ddi_translations;
2187         enum port port = encoder->port;
2188         int n_entries, ln;
2189         u32 val;
2190
2191         if (type == INTEL_OUTPUT_HDMI)
2192                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2193         else if (type == INTEL_OUTPUT_EDP)
2194                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2195         else
2196                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2197
2198         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2199                 return;
2200         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2201                 level = n_entries - 1;
2202
2203         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2204         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2205         val &= ~SCALING_MODE_SEL_MASK;
2206         val |= SCALING_MODE_SEL(2);
2207         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2208
2209         /* Program PORT_TX_DW2 */
2210         val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2211         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2212                  RCOMP_SCALAR_MASK);
2213         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2214         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2215         /* Rcomp scalar is fixed as 0x98 for every table entry */
2216         val |= RCOMP_SCALAR(0x98);
2217         intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2218
2219         /* Program PORT_TX_DW4 */
2220         /* We cannot write to GRP. It would overrite individual loadgen */
2221         for (ln = 0; ln < 4; ln++) {
2222                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2223                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2224                          CURSOR_COEFF_MASK);
2225                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2226                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2227                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2228                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2229         }
2230
2231         /* Program PORT_TX_DW5 */
2232         /* All DW5 values are fixed for every table entry */
2233         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2234         val &= ~RTERM_SELECT_MASK;
2235         val |= RTERM_SELECT(6);
2236         val |= TAP3_DISABLE;
2237         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2238
2239         /* Program PORT_TX_DW7 */
2240         val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2241         val &= ~N_SCALAR_MASK;
2242         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2243         intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2244 }
2245
2246 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2247                                     int level, enum intel_output_type type)
2248 {
2249         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2250         enum port port = encoder->port;
2251         int width, rate, ln;
2252         u32 val;
2253
2254         if (type == INTEL_OUTPUT_HDMI) {
2255                 width = 4;
2256                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2257         } else {
2258                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2259
2260                 width = intel_dp->lane_count;
2261                 rate = intel_dp->link_rate;
2262         }
2263
2264         /*
2265          * 1. If port type is eDP or DP,
2266          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2267          * else clear to 0b.
2268          */
2269         val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2270         if (type != INTEL_OUTPUT_HDMI)
2271                 val |= COMMON_KEEPER_EN;
2272         else
2273                 val &= ~COMMON_KEEPER_EN;
2274         intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2275
2276         /* 2. Program loadgen select */
2277         /*
2278          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2279          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2280          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2281          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2282          */
2283         for (ln = 0; ln <= 3; ln++) {
2284                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2285                 val &= ~LOADGEN_SELECT;
2286
2287                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2288                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2289                         val |= LOADGEN_SELECT;
2290                 }
2291                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2292         }
2293
2294         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2295         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2296         val |= SUS_CLOCK_CONFIG;
2297         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2298
2299         /* 4. Clear training enable to change swing values */
2300         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2301         val &= ~TX_TRAINING_EN;
2302         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2303
2304         /* 5. Program swing and de-emphasis */
2305         cnl_ddi_vswing_program(encoder, level, type);
2306
2307         /* 6. Set training enable to trigger update */
2308         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2309         val |= TX_TRAINING_EN;
2310         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2311 }
2312
2313 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2314                                         u32 level, enum phy phy, int type,
2315                                         int rate)
2316 {
2317         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2318         u32 n_entries, val;
2319         int ln;
2320
2321         if (INTEL_GEN(dev_priv) >= 12)
2322                 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
2323                                                            &n_entries);
2324         else if (IS_ELKHARTLAKE(dev_priv))
2325                 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
2326                                                            &n_entries);
2327         else
2328                 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2329                                                            &n_entries);
2330         if (!ddi_translations)
2331                 return;
2332
2333         if (level >= n_entries) {
2334                 drm_dbg_kms(&dev_priv->drm,
2335                             "DDI translation not found for level %d. Using %d instead.",
2336                             level, n_entries - 1);
2337                 level = n_entries - 1;
2338         }
2339
2340         /* Set PORT_TX_DW5 */
2341         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2342         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2343                   TAP2_DISABLE | TAP3_DISABLE);
2344         val |= SCALING_MODE_SEL(0x2);
2345         val |= RTERM_SELECT(0x6);
2346         val |= TAP3_DISABLE;
2347         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2348
2349         /* Program PORT_TX_DW2 */
2350         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2351         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2352                  RCOMP_SCALAR_MASK);
2353         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2354         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2355         /* Program Rcomp scalar for every table entry */
2356         val |= RCOMP_SCALAR(0x98);
2357         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2358
2359         /* Program PORT_TX_DW4 */
2360         /* We cannot write to GRP. It would overwrite individual loadgen. */
2361         for (ln = 0; ln <= 3; ln++) {
2362                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2363                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2364                          CURSOR_COEFF_MASK);
2365                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2366                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2367                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2368                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2369         }
2370
2371         /* Program PORT_TX_DW7 */
2372         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2373         val &= ~N_SCALAR_MASK;
2374         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2375         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2376 }
2377
2378 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2379                                               u32 level,
2380                                               enum intel_output_type type)
2381 {
2382         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2383         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2384         int width = 0;
2385         int rate = 0;
2386         u32 val;
2387         int ln = 0;
2388
2389         if (type == INTEL_OUTPUT_HDMI) {
2390                 width = 4;
2391                 /* Rate is always < than 6GHz for HDMI */
2392         } else {
2393                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2394
2395                 width = intel_dp->lane_count;
2396                 rate = intel_dp->link_rate;
2397         }
2398
2399         /*
2400          * 1. If port type is eDP or DP,
2401          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2402          * else clear to 0b.
2403          */
2404         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2405         if (type == INTEL_OUTPUT_HDMI)
2406                 val &= ~COMMON_KEEPER_EN;
2407         else
2408                 val |= COMMON_KEEPER_EN;
2409         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2410
2411         /* 2. Program loadgen select */
2412         /*
2413          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2414          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2415          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2416          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2417          */
2418         for (ln = 0; ln <= 3; ln++) {
2419                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2420                 val &= ~LOADGEN_SELECT;
2421
2422                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2423                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2424                         val |= LOADGEN_SELECT;
2425                 }
2426                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2427         }
2428
2429         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2430         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2431         val |= SUS_CLOCK_CONFIG;
2432         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2433
2434         /* 4. Clear training enable to change swing values */
2435         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2436         val &= ~TX_TRAINING_EN;
2437         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2438
2439         /* 5. Program swing and de-emphasis */
2440         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2441
2442         /* 6. Set training enable to trigger update */
2443         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2444         val |= TX_TRAINING_EN;
2445         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2446 }
2447
2448 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2449                                            int link_clock, u32 level,
2450                                            enum intel_output_type type)
2451 {
2452         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2453         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2454         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2455         u32 n_entries, val;
2456         int ln, rate = 0;
2457
2458         if (type != INTEL_OUTPUT_HDMI) {
2459                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2460
2461                 rate = intel_dp->link_rate;
2462         }
2463
2464         ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate,
2465                                                 &n_entries);
2466         /* The table does not have values for level 3 and level 9. */
2467         if (level >= n_entries || level == 3 || level == 9) {
2468                 drm_dbg_kms(&dev_priv->drm,
2469                             "DDI translation not found for level %d. Using %d instead.",
2470                             level, n_entries - 2);
2471                 level = n_entries - 2;
2472         }
2473
2474         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2475         for (ln = 0; ln < 2; ln++) {
2476                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2477                 val &= ~CRI_USE_FS32;
2478                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2479
2480                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2481                 val &= ~CRI_USE_FS32;
2482                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2483         }
2484
2485         /* Program MG_TX_SWINGCTRL with values from vswing table */
2486         for (ln = 0; ln < 2; ln++) {
2487                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2488                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2489                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2490                         ddi_translations[level].cri_txdeemph_override_17_12);
2491                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2492
2493                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2494                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2495                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2496                         ddi_translations[level].cri_txdeemph_override_17_12);
2497                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2498         }
2499
2500         /* Program MG_TX_DRVCTRL with values from vswing table */
2501         for (ln = 0; ln < 2; ln++) {
2502                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2503                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2504                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2505                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2506                         ddi_translations[level].cri_txdeemph_override_5_0) |
2507                         CRI_TXDEEMPH_OVERRIDE_11_6(
2508                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2509                         CRI_TXDEEMPH_OVERRIDE_EN;
2510                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2511
2512                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2513                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2514                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2515                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2516                         ddi_translations[level].cri_txdeemph_override_5_0) |
2517                         CRI_TXDEEMPH_OVERRIDE_11_6(
2518                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2519                         CRI_TXDEEMPH_OVERRIDE_EN;
2520                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2521
2522                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2523         }
2524
2525         /*
2526          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2527          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2528          * values from table for which TX1 and TX2 enabled.
2529          */
2530         for (ln = 0; ln < 2; ln++) {
2531                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2532                 if (link_clock < 300000)
2533                         val |= CFG_LOW_RATE_LKREN_EN;
2534                 else
2535                         val &= ~CFG_LOW_RATE_LKREN_EN;
2536                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2537         }
2538
2539         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2540         for (ln = 0; ln < 2; ln++) {
2541                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2542                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2543                 if (link_clock <= 500000) {
2544                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2545                 } else {
2546                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2547                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2548                 }
2549                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2550
2551                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2552                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2553                 if (link_clock <= 500000) {
2554                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2555                 } else {
2556                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2557                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2558                 }
2559                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2560         }
2561
2562         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2563         for (ln = 0; ln < 2; ln++) {
2564                 val = intel_de_read(dev_priv,
2565                                     MG_TX1_PISO_READLOAD(ln, tc_port));
2566                 val |= CRI_CALCINIT;
2567                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2568                                val);
2569
2570                 val = intel_de_read(dev_priv,
2571                                     MG_TX2_PISO_READLOAD(ln, tc_port));
2572                 val |= CRI_CALCINIT;
2573                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2574                                val);
2575         }
2576 }
2577
2578 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2579                                     int link_clock,
2580                                     u32 level,
2581                                     enum intel_output_type type)
2582 {
2583         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2584         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2585
2586         if (intel_phy_is_combo(dev_priv, phy))
2587                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2588         else
2589                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
2590                                                type);
2591 }
2592
2593 static void
2594 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2595                                 u32 level)
2596 {
2597         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2598         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2599         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2600         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2601
2602         if (encoder->type == INTEL_OUTPUT_HDMI) {
2603                 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
2604                 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
2605         } else {
2606                 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2607                 ddi_translations = tgl_dkl_phy_dp_ddi_trans;
2608         }
2609
2610         if (level >= n_entries)
2611                 level = n_entries - 1;
2612
2613         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2614                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2615                       DKL_TX_VSWING_CONTROL_MASK);
2616         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2617         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2618         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2619
2620         for (ln = 0; ln < 2; ln++) {
2621                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2622                                HIP_INDEX_VAL(tc_port, ln));
2623
2624                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2625
2626                 /* All the registers are RMW */
2627                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2628                 val &= ~dpcnt_mask;
2629                 val |= dpcnt_val;
2630                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2631
2632                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2633                 val &= ~dpcnt_mask;
2634                 val |= dpcnt_val;
2635                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2636
2637                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2638                 val &= ~DKL_TX_DP20BITMODE;
2639                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2640         }
2641 }
2642
2643 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2644                                     int link_clock,
2645                                     u32 level,
2646                                     enum intel_output_type type)
2647 {
2648         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2649         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2650
2651         if (intel_phy_is_combo(dev_priv, phy))
2652                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2653         else
2654                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2655 }
2656
2657 static u32 translate_signal_level(int signal_levels)
2658 {
2659         int i;
2660
2661         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2662                 if (index_to_dp_signal_levels[i] == signal_levels)
2663                         return i;
2664         }
2665
2666         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2667              signal_levels);
2668
2669         return 0;
2670 }
2671
2672 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2673 {
2674         u8 train_set = intel_dp->train_set[0];
2675         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2676                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2677
2678         return translate_signal_level(signal_levels);
2679 }
2680
2681 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2682 {
2683         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2684         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2685         struct intel_encoder *encoder = &dport->base;
2686         int level = intel_ddi_dp_level(intel_dp);
2687
2688         if (INTEL_GEN(dev_priv) >= 12)
2689                 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2690                                         level, encoder->type);
2691         else if (INTEL_GEN(dev_priv) >= 11)
2692                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2693                                         level, encoder->type);
2694         else if (IS_CANNONLAKE(dev_priv))
2695                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2696         else
2697                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2698
2699         return 0;
2700 }
2701
2702 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2703 {
2704         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2705         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2706         struct intel_encoder *encoder = &dport->base;
2707         int level = intel_ddi_dp_level(intel_dp);
2708
2709         if (IS_GEN9_BC(dev_priv))
2710                 skl_ddi_set_iboost(encoder, level, encoder->type);
2711
2712         return DDI_BUF_TRANS_SELECT(level);
2713 }
2714
2715 static inline
2716 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2717                               enum phy phy)
2718 {
2719         if (intel_phy_is_combo(dev_priv, phy)) {
2720                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2721         } else if (intel_phy_is_tc(dev_priv, phy)) {
2722                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2723                                                         (enum port)phy);
2724
2725                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2726         }
2727
2728         return 0;
2729 }
2730
2731 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2732                                   const struct intel_crtc_state *crtc_state)
2733 {
2734         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2735         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2736         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2737         u32 val;
2738
2739         mutex_lock(&dev_priv->dpll.lock);
2740
2741         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2742         drm_WARN_ON(&dev_priv->drm,
2743                     (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2744
2745         if (intel_phy_is_combo(dev_priv, phy)) {
2746                 /*
2747                  * Even though this register references DDIs, note that we
2748                  * want to pass the PHY rather than the port (DDI).  For
2749                  * ICL, port=phy in all cases so it doesn't matter, but for
2750                  * EHL the bspec notes the following:
2751                  *
2752                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2753                  *   Clock Select chooses the PLL for both DDIA and DDID and
2754                  *   drives port A in all cases."
2755                  */
2756                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2757                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2758                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2759                 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
2760         }
2761
2762         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2763         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2764
2765         mutex_unlock(&dev_priv->dpll.lock);
2766 }
2767
2768 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2769 {
2770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2771         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2772         u32 val;
2773
2774         mutex_lock(&dev_priv->dpll.lock);
2775
2776         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2777         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2778         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2779
2780         mutex_unlock(&dev_priv->dpll.lock);
2781 }
2782
2783 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
2784                                       u32 port_mask, bool ddi_clk_needed)
2785 {
2786         enum port port;
2787         u32 val;
2788
2789         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2790         for_each_port_masked(port, port_mask) {
2791                 enum phy phy = intel_port_to_phy(dev_priv, port);
2792                 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
2793                                                                    phy);
2794
2795                 if (ddi_clk_needed == !ddi_clk_off)
2796                         continue;
2797
2798                 /*
2799                  * Punt on the case now where clock is gated, but it would
2800                  * be needed by the port. Something else is really broken then.
2801                  */
2802                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
2803                         continue;
2804
2805                 drm_notice(&dev_priv->drm,
2806                            "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2807                            phy_name(phy));
2808                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2809                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2810         }
2811 }
2812
2813 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2814 {
2815         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2816         u32 port_mask;
2817         bool ddi_clk_needed;
2818
2819         /*
2820          * In case of DP MST, we sanitize the primary encoder only, not the
2821          * virtual ones.
2822          */
2823         if (encoder->type == INTEL_OUTPUT_DP_MST)
2824                 return;
2825
2826         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2827                 u8 pipe_mask;
2828                 bool is_mst;
2829
2830                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2831                 /*
2832                  * In the unlikely case that BIOS enables DP in MST mode, just
2833                  * warn since our MST HW readout is incomplete.
2834                  */
2835                 if (drm_WARN_ON(&dev_priv->drm, is_mst))
2836                         return;
2837         }
2838
2839         port_mask = BIT(encoder->port);
2840         ddi_clk_needed = encoder->base.crtc;
2841
2842         if (encoder->type == INTEL_OUTPUT_DSI) {
2843                 struct intel_encoder *other_encoder;
2844
2845                 port_mask = intel_dsi_encoder_ports(encoder);
2846                 /*
2847                  * Sanity check that we haven't incorrectly registered another
2848                  * encoder using any of the ports of this DSI encoder.
2849                  */
2850                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2851                         if (other_encoder == encoder)
2852                                 continue;
2853
2854                         if (drm_WARN_ON(&dev_priv->drm,
2855                                         port_mask & BIT(other_encoder->port)))
2856                                 return;
2857                 }
2858                 /*
2859                  * For DSI we keep the ddi clocks gated
2860                  * except during enable/disable sequence.
2861                  */
2862                 ddi_clk_needed = false;
2863         }
2864
2865         icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
2866 }
2867
2868 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2869                                  const struct intel_crtc_state *crtc_state)
2870 {
2871         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2872         enum port port = encoder->port;
2873         enum phy phy = intel_port_to_phy(dev_priv, port);
2874         u32 val;
2875         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2876
2877         if (drm_WARN_ON(&dev_priv->drm, !pll))
2878                 return;
2879
2880         mutex_lock(&dev_priv->dpll.lock);
2881
2882         if (INTEL_GEN(dev_priv) >= 11) {
2883                 if (!intel_phy_is_combo(dev_priv, phy))
2884                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2885                                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2886                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2887                         /*
2888                          * MG does not exist but the programming is required
2889                          * to ungate DDIC and DDID
2890                          */
2891                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2892                                        DDI_CLK_SEL_MG);
2893         } else if (IS_CANNONLAKE(dev_priv)) {
2894                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2895                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
2896                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2897                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2898                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
2899
2900                 /*
2901                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2902                  * This step and the step before must be done with separate
2903                  * register writes.
2904                  */
2905                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
2906                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2907                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
2908         } else if (IS_GEN9_BC(dev_priv)) {
2909                 /* DDI -> PLL mapping  */
2910                 val = intel_de_read(dev_priv, DPLL_CTRL2);
2911
2912                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2913                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2914                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2915                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2916
2917                 intel_de_write(dev_priv, DPLL_CTRL2, val);
2918
2919         } else if (INTEL_GEN(dev_priv) < 9) {
2920                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
2921                                hsw_pll_to_ddi_pll_sel(pll));
2922         }
2923
2924         mutex_unlock(&dev_priv->dpll.lock);
2925 }
2926
2927 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2928 {
2929         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2930         enum port port = encoder->port;
2931         enum phy phy = intel_port_to_phy(dev_priv, port);
2932
2933         if (INTEL_GEN(dev_priv) >= 11) {
2934                 if (!intel_phy_is_combo(dev_priv, phy) ||
2935                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
2936                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2937                                        DDI_CLK_SEL_NONE);
2938         } else if (IS_CANNONLAKE(dev_priv)) {
2939                 intel_de_write(dev_priv, DPCLKA_CFGCR0,
2940                                intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2941         } else if (IS_GEN9_BC(dev_priv)) {
2942                 intel_de_write(dev_priv, DPLL_CTRL2,
2943                                intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
2944         } else if (INTEL_GEN(dev_priv) < 9) {
2945                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
2946                                PORT_CLK_SEL_NONE);
2947         }
2948 }
2949
2950 static void
2951 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
2952                        const struct intel_crtc_state *crtc_state)
2953 {
2954         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2955         enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
2956         u32 ln0, ln1, pin_assignment;
2957         u8 width;
2958
2959         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
2960                 return;
2961
2962         if (INTEL_GEN(dev_priv) >= 12) {
2963                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2964                                HIP_INDEX_VAL(tc_port, 0x0));
2965                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2966                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2967                                HIP_INDEX_VAL(tc_port, 0x1));
2968                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2969         } else {
2970                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2971                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2972         }
2973
2974         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
2975         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2976
2977         /* DPPATC */
2978         pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
2979         width = crtc_state->lane_count;
2980
2981         switch (pin_assignment) {
2982         case 0x0:
2983                 drm_WARN_ON(&dev_priv->drm,
2984                             intel_dig_port->tc_mode != TC_PORT_LEGACY);
2985                 if (width == 1) {
2986                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2987                 } else {
2988                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2989                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2990                 }
2991                 break;
2992         case 0x1:
2993                 if (width == 4) {
2994                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2995                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2996                 }
2997                 break;
2998         case 0x2:
2999                 if (width == 2) {
3000                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3001                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3002                 }
3003                 break;
3004         case 0x3:
3005         case 0x5:
3006                 if (width == 1) {
3007                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3008                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3009                 } else {
3010                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3011                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3012                 }
3013                 break;
3014         case 0x4:
3015         case 0x6:
3016                 if (width == 1) {
3017                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3018                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3019                 } else {
3020                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3021                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3022                 }
3023                 break;
3024         default:
3025                 MISSING_CASE(pin_assignment);
3026         }
3027
3028         if (INTEL_GEN(dev_priv) >= 12) {
3029                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3030                                HIP_INDEX_VAL(tc_port, 0x0));
3031                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3032                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3033                                HIP_INDEX_VAL(tc_port, 0x1));
3034                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3035         } else {
3036                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3037                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3038         }
3039 }
3040
3041 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3042                                         const struct intel_crtc_state *crtc_state)
3043 {
3044         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3045
3046         if (!crtc_state->fec_enable)
3047                 return;
3048
3049         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3050                 drm_dbg_kms(&i915->drm,
3051                             "Failed to set FEC_READY in the sink\n");
3052 }
3053
3054 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3055                                  const struct intel_crtc_state *crtc_state)
3056 {
3057         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3058         struct intel_dp *intel_dp;
3059         u32 val;
3060
3061         if (!crtc_state->fec_enable)
3062                 return;
3063
3064         intel_dp = enc_to_intel_dp(encoder);
3065         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3066         val |= DP_TP_CTL_FEC_ENABLE;
3067         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3068
3069         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3070                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3071                 drm_err(&dev_priv->drm,
3072                         "Timed out waiting for FEC Enable Status\n");
3073 }
3074
3075 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3076                                         const struct intel_crtc_state *crtc_state)
3077 {
3078         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3079         struct intel_dp *intel_dp;
3080         u32 val;
3081
3082         if (!crtc_state->fec_enable)
3083                 return;
3084
3085         intel_dp = enc_to_intel_dp(encoder);
3086         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3087         val &= ~DP_TP_CTL_FEC_ENABLE;
3088         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3089         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3090 }
3091
3092 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3093                                   struct intel_encoder *encoder,
3094                                   const struct intel_crtc_state *crtc_state,
3095                                   const struct drm_connector_state *conn_state)
3096 {
3097         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3098         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3099         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3100         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3101         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3102         int level = intel_ddi_dp_level(intel_dp);
3103         enum transcoder transcoder = crtc_state->cpu_transcoder;
3104
3105         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3106                                  crtc_state->lane_count, is_mst);
3107
3108         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3109         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3110
3111         /*
3112          * 1. Enable Power Wells
3113          *
3114          * This was handled at the beginning of intel_atomic_commit_tail(),
3115          * before we called down into this function.
3116          */
3117
3118         /* 2. Enable Panel Power if PPS is required */
3119         intel_edp_panel_on(intel_dp);
3120
3121         /*
3122          * 3. For non-TBT Type-C ports, set FIA lane count
3123          * (DFLEXDPSP.DPX4TXLATC)
3124          *
3125          * This was done before tgl_ddi_pre_enable_dp by
3126          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3127          */
3128
3129         /*
3130          * 4. Enable the port PLL.
3131          *
3132          * The PLL enabling itself was already done before this function by
3133          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
3134          * configure the PLL to port mapping here.
3135          */
3136         intel_ddi_clk_select(encoder, crtc_state);
3137
3138         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3139         if (!intel_phy_is_tc(dev_priv, phy) ||
3140             dig_port->tc_mode != TC_PORT_TBT_ALT)
3141                 intel_display_power_get(dev_priv,
3142                                         dig_port->ddi_io_power_domain);
3143
3144         /* 6. Program DP_MODE */
3145         icl_program_mg_dp_mode(dig_port, crtc_state);
3146
3147         /*
3148          * 7. The rest of the below are substeps under the bspec's "Enable and
3149          * Train Display Port" step.  Note that steps that are specific to
3150          * MST will be handled by intel_mst_pre_enable_dp() before/after it
3151          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
3152          * us when active_mst_links==0, so any steps designated for "single
3153          * stream or multi-stream master transcoder" can just be performed
3154          * unconditionally here.
3155          */
3156
3157         /*
3158          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3159          * Transcoder.
3160          */
3161         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3162
3163         /*
3164          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3165          * Transport Select
3166          */
3167         intel_ddi_config_transcoder_func(crtc_state);
3168
3169         /*
3170          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3171          * selected
3172          *
3173          * This will be handled by the intel_dp_start_link_train() farther
3174          * down this function.
3175          */
3176
3177         /* 7.e Configure voltage swing and related IO settings */
3178         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3179                                 encoder->type);
3180
3181         /*
3182          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3183          * the used lanes of the DDI.
3184          */
3185         if (intel_phy_is_combo(dev_priv, phy)) {
3186                 bool lane_reversal =
3187                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3188
3189                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3190                                                crtc_state->lane_count,
3191                                                lane_reversal);
3192         }
3193
3194         /*
3195          * 7.g Configure and enable DDI_BUF_CTL
3196          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3197          *     after 500 us.
3198          *
3199          * We only configure what the register value will be here.  Actual
3200          * enabling happens during link training farther down.
3201          */
3202         intel_ddi_init_dp_buf_reg(encoder);
3203
3204         if (!is_mst)
3205                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3206
3207         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3208         /*
3209          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3210          * in the FEC_CONFIGURATION register to 1 before initiating link
3211          * training
3212          */
3213         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3214
3215         /*
3216          * 7.i Follow DisplayPort specification training sequence (see notes for
3217          *     failure handling)
3218          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3219          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3220          *     (timeout after 800 us)
3221          */
3222         intel_dp_start_link_train(intel_dp);
3223
3224         /* 7.k Set DP_TP_CTL link training to Normal */
3225         if (!is_trans_port_sync_mode(crtc_state))
3226                 intel_dp_stop_link_train(intel_dp);
3227
3228         /* 7.l Configure and enable FEC if needed */
3229         intel_ddi_enable_fec(encoder, crtc_state);
3230         intel_dsc_enable(encoder, crtc_state);
3231 }
3232
3233 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3234                                   struct intel_encoder *encoder,
3235                                   const struct intel_crtc_state *crtc_state,
3236                                   const struct drm_connector_state *conn_state)
3237 {
3238         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3239         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3240         enum port port = encoder->port;
3241         enum phy phy = intel_port_to_phy(dev_priv, port);
3242         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3243         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3244         int level = intel_ddi_dp_level(intel_dp);
3245
3246         if (INTEL_GEN(dev_priv) < 11)
3247                 drm_WARN_ON(&dev_priv->drm,
3248                             is_mst && (port == PORT_A || port == PORT_E));
3249         else
3250                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3251
3252         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3253                                  crtc_state->lane_count, is_mst);
3254
3255         intel_edp_panel_on(intel_dp);
3256
3257         intel_ddi_clk_select(encoder, crtc_state);
3258
3259         if (!intel_phy_is_tc(dev_priv, phy) ||
3260             dig_port->tc_mode != TC_PORT_TBT_ALT)
3261                 intel_display_power_get(dev_priv,
3262                                         dig_port->ddi_io_power_domain);
3263
3264         icl_program_mg_dp_mode(dig_port, crtc_state);
3265
3266         if (INTEL_GEN(dev_priv) >= 11)
3267                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3268                                         level, encoder->type);
3269         else if (IS_CANNONLAKE(dev_priv))
3270                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3271         else if (IS_GEN9_LP(dev_priv))
3272                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3273         else
3274                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3275
3276         if (intel_phy_is_combo(dev_priv, phy)) {
3277                 bool lane_reversal =
3278                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3279
3280                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3281                                                crtc_state->lane_count,
3282                                                lane_reversal);
3283         }
3284
3285         intel_ddi_init_dp_buf_reg(encoder);
3286         if (!is_mst)
3287                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3288         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3289                                               true);
3290         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3291         intel_dp_start_link_train(intel_dp);
3292         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3293             !is_trans_port_sync_mode(crtc_state))
3294                 intel_dp_stop_link_train(intel_dp);
3295
3296         intel_ddi_enable_fec(encoder, crtc_state);
3297
3298         if (!is_mst)
3299                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3300
3301         intel_dsc_enable(encoder, crtc_state);
3302 }
3303
3304 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3305                                     struct intel_encoder *encoder,
3306                                     const struct intel_crtc_state *crtc_state,
3307                                     const struct drm_connector_state *conn_state)
3308 {
3309         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3310
3311         if (INTEL_GEN(dev_priv) >= 12)
3312                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3313         else
3314                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3315
3316         /* MST will call a setting of MSA after an allocating of Virtual Channel
3317          * from MST encoder pre_enable callback.
3318          */
3319         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3320                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3321
3322                 intel_dp_set_m_n(crtc_state, M1_N1);
3323         }
3324 }
3325
3326 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3327                                       struct intel_encoder *encoder,
3328                                       const struct intel_crtc_state *crtc_state,
3329                                       const struct drm_connector_state *conn_state)
3330 {
3331         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3332         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3333         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3334         int level = intel_ddi_hdmi_level(encoder);
3335         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3336
3337         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3338         intel_ddi_clk_select(encoder, crtc_state);
3339
3340         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3341
3342         icl_program_mg_dp_mode(dig_port, crtc_state);
3343
3344         if (INTEL_GEN(dev_priv) >= 12)
3345                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3346                                         level, INTEL_OUTPUT_HDMI);
3347         else if (INTEL_GEN(dev_priv) == 11)
3348                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3349                                         level, INTEL_OUTPUT_HDMI);
3350         else if (IS_CANNONLAKE(dev_priv))
3351                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3352         else if (IS_GEN9_LP(dev_priv))
3353                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3354         else
3355                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3356
3357         if (IS_GEN9_BC(dev_priv))
3358                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3359
3360         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3361
3362         intel_dig_port->set_infoframes(encoder,
3363                                        crtc_state->has_infoframe,
3364                                        crtc_state, conn_state);
3365 }
3366
3367 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3368                                  struct intel_encoder *encoder,
3369                                  const struct intel_crtc_state *crtc_state,
3370                                  const struct drm_connector_state *conn_state)
3371 {
3372         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3373         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3374         enum pipe pipe = crtc->pipe;
3375
3376         /*
3377          * When called from DP MST code:
3378          * - conn_state will be NULL
3379          * - encoder will be the main encoder (ie. mst->primary)
3380          * - the main connector associated with this port
3381          *   won't be active or linked to a crtc
3382          * - crtc_state will be the state of the first stream to
3383          *   be activated on this port, and it may not be the same
3384          *   stream that will be deactivated last, but each stream
3385          *   should have a state that is identical when it comes to
3386          *   the DP link parameteres
3387          */
3388
3389         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3390
3391         if (INTEL_GEN(dev_priv) >= 11)
3392                 icl_map_plls_to_ports(encoder, crtc_state);
3393
3394         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3395
3396         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3397                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3398                                           conn_state);
3399         } else {
3400                 struct intel_lspcon *lspcon =
3401                                 enc_to_intel_lspcon(encoder);
3402
3403                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3404                                         conn_state);
3405                 if (lspcon->active) {
3406                         struct intel_digital_port *dig_port =
3407                                         enc_to_dig_port(encoder);
3408
3409                         dig_port->set_infoframes(encoder,
3410                                                  crtc_state->has_infoframe,
3411                                                  crtc_state, conn_state);
3412                 }
3413         }
3414 }
3415
3416 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3417                                   const struct intel_crtc_state *crtc_state)
3418 {
3419         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3420         enum port port = encoder->port;
3421         bool wait = false;
3422         u32 val;
3423
3424         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3425         if (val & DDI_BUF_CTL_ENABLE) {
3426                 val &= ~DDI_BUF_CTL_ENABLE;
3427                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3428                 wait = true;
3429         }
3430
3431         if (intel_crtc_has_dp_encoder(crtc_state)) {
3432                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3433
3434                 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3435                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3436                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3437                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3438         }
3439
3440         /* Disable FEC in DP Sink */
3441         intel_ddi_disable_fec_state(encoder, crtc_state);
3442
3443         if (wait)
3444                 intel_wait_ddi_buf_idle(dev_priv, port);
3445 }
3446
3447 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3448                                       struct intel_encoder *encoder,
3449                                       const struct intel_crtc_state *old_crtc_state,
3450                                       const struct drm_connector_state *old_conn_state)
3451 {
3452         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3453         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3454         struct intel_dp *intel_dp = &dig_port->dp;
3455         bool is_mst = intel_crtc_has_type(old_crtc_state,
3456                                           INTEL_OUTPUT_DP_MST);
3457         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3458
3459         /*
3460          * Power down sink before disabling the port, otherwise we end
3461          * up getting interrupts from the sink on detecting link loss.
3462          */
3463         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3464
3465         if (INTEL_GEN(dev_priv) >= 12) {
3466                 if (is_mst) {
3467                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3468                         u32 val;
3469
3470                         val = intel_de_read(dev_priv,
3471                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
3472                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
3473                                  TRANS_DDI_MODE_SELECT_MASK);
3474                         intel_de_write(dev_priv,
3475                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
3476                                        val);
3477                 }
3478         } else {
3479                 if (!is_mst)
3480                         intel_ddi_disable_pipe_clock(old_crtc_state);
3481         }
3482
3483         intel_disable_ddi_buf(encoder, old_crtc_state);
3484
3485         /*
3486          * From TGL spec: "If single stream or multi-stream master transcoder:
3487          * Configure Transcoder Clock select to direct no clock to the
3488          * transcoder"
3489          */
3490         if (INTEL_GEN(dev_priv) >= 12)
3491                 intel_ddi_disable_pipe_clock(old_crtc_state);
3492
3493         intel_edp_panel_vdd_on(intel_dp);
3494         intel_edp_panel_off(intel_dp);
3495
3496         if (!intel_phy_is_tc(dev_priv, phy) ||
3497             dig_port->tc_mode != TC_PORT_TBT_ALT)
3498                 intel_display_power_put_unchecked(dev_priv,
3499                                                   dig_port->ddi_io_power_domain);
3500
3501         intel_ddi_clk_disable(encoder);
3502 }
3503
3504 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3505                                         struct intel_encoder *encoder,
3506                                         const struct intel_crtc_state *old_crtc_state,
3507                                         const struct drm_connector_state *old_conn_state)
3508 {
3509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3510         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3511         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3512
3513         dig_port->set_infoframes(encoder, false,
3514                                  old_crtc_state, old_conn_state);
3515
3516         intel_ddi_disable_pipe_clock(old_crtc_state);
3517
3518         intel_disable_ddi_buf(encoder, old_crtc_state);
3519
3520         intel_display_power_put_unchecked(dev_priv,
3521                                           dig_port->ddi_io_power_domain);
3522
3523         intel_ddi_clk_disable(encoder);
3524
3525         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3526 }
3527
3528 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3529                                    struct intel_encoder *encoder,
3530                                    const struct intel_crtc_state *old_crtc_state,
3531                                    const struct drm_connector_state *old_conn_state)
3532 {
3533         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3534         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3535         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3536         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3537
3538         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3539                 intel_crtc_vblank_off(old_crtc_state);
3540
3541                 intel_disable_pipe(old_crtc_state);
3542
3543                 intel_ddi_disable_transcoder_func(old_crtc_state);
3544
3545                 intel_dsc_disable(old_crtc_state);
3546
3547                 if (INTEL_GEN(dev_priv) >= 9)
3548                         skl_scaler_disable(old_crtc_state);
3549                 else
3550                         ilk_pfit_disable(old_crtc_state);
3551         }
3552
3553         /*
3554          * When called from DP MST code:
3555          * - old_conn_state will be NULL
3556          * - encoder will be the main encoder (ie. mst->primary)
3557          * - the main connector associated with this port
3558          *   won't be active or linked to a crtc
3559          * - old_crtc_state will be the state of the last stream to
3560          *   be deactivated on this port, and it may not be the same
3561          *   stream that was activated last, but each stream
3562          *   should have a state that is identical when it comes to
3563          *   the DP link parameteres
3564          */
3565
3566         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3567                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3568                                             old_conn_state);
3569         else
3570                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3571                                           old_conn_state);
3572
3573         if (INTEL_GEN(dev_priv) >= 11)
3574                 icl_unmap_plls_to_ports(encoder);
3575
3576         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3577                 intel_display_power_put_unchecked(dev_priv,
3578                                                   intel_ddi_main_link_aux_domain(dig_port));
3579
3580         if (is_tc_port)
3581                 intel_tc_port_put_link(dig_port);
3582 }
3583
3584 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
3585                                 struct intel_encoder *encoder,
3586                                 const struct intel_crtc_state *old_crtc_state,
3587                                 const struct drm_connector_state *old_conn_state)
3588 {
3589         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3590         u32 val;
3591
3592         /*
3593          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3594          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3595          * step 13 is the correct place for it. Step 18 is where it was
3596          * originally before the BUN.
3597          */
3598         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3599         val &= ~FDI_RX_ENABLE;
3600         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3601
3602         intel_disable_ddi_buf(encoder, old_crtc_state);
3603         intel_ddi_clk_disable(encoder);
3604
3605         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3606         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3607         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3608         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3609
3610         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3611         val &= ~FDI_PCDCLK;
3612         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3613
3614         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3615         val &= ~FDI_RX_PLL_ENABLE;
3616         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3617 }
3618
3619 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3620                                             struct intel_encoder *encoder,
3621                                             const struct intel_crtc_state *crtc_state)
3622 {
3623         const struct drm_connector_state *conn_state;
3624         struct drm_connector *conn;
3625         int i;
3626
3627         if (!crtc_state->sync_mode_slaves_mask)
3628                 return;
3629
3630         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3631                 struct intel_encoder *slave_encoder =
3632                         to_intel_encoder(conn_state->best_encoder);
3633                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3634                 const struct intel_crtc_state *slave_crtc_state;
3635
3636                 if (!slave_crtc)
3637                         continue;
3638
3639                 slave_crtc_state =
3640                         intel_atomic_get_new_crtc_state(state, slave_crtc);
3641
3642                 if (slave_crtc_state->master_transcoder !=
3643                     crtc_state->cpu_transcoder)
3644                         continue;
3645
3646                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
3647         }
3648
3649         usleep_range(200, 400);
3650
3651         intel_dp_stop_link_train(enc_to_intel_dp(encoder));
3652 }
3653
3654 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3655                                 struct intel_encoder *encoder,
3656                                 const struct intel_crtc_state *crtc_state,
3657                                 const struct drm_connector_state *conn_state)
3658 {
3659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3660         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3661         enum port port = encoder->port;
3662
3663         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3664                 intel_dp_stop_link_train(intel_dp);
3665
3666         intel_edp_backlight_on(crtc_state, conn_state);
3667         intel_psr_enable(intel_dp, crtc_state);
3668         intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3669         intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3670         intel_edp_drrs_enable(intel_dp, crtc_state);
3671
3672         if (crtc_state->has_audio)
3673                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3674
3675         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3676 }
3677
3678 static i915_reg_t
3679 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3680                                enum port port)
3681 {
3682         static const enum transcoder trans[] = {
3683                 [PORT_A] = TRANSCODER_EDP,
3684                 [PORT_B] = TRANSCODER_A,
3685                 [PORT_C] = TRANSCODER_B,
3686                 [PORT_D] = TRANSCODER_C,
3687                 [PORT_E] = TRANSCODER_A,
3688         };
3689
3690         drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
3691
3692         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3693                 port = PORT_A;
3694
3695         return CHICKEN_TRANS(trans[port]);
3696 }
3697
3698 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3699                                   struct intel_encoder *encoder,
3700                                   const struct intel_crtc_state *crtc_state,
3701                                   const struct drm_connector_state *conn_state)
3702 {
3703         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3704         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3705         struct drm_connector *connector = conn_state->connector;
3706         enum port port = encoder->port;
3707
3708         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3709                                                crtc_state->hdmi_high_tmds_clock_ratio,
3710                                                crtc_state->hdmi_scrambling))
3711                 drm_dbg_kms(&dev_priv->drm,
3712                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3713                             connector->base.id, connector->name);
3714
3715         /* Display WA #1143: skl,kbl,cfl */
3716         if (IS_GEN9_BC(dev_priv)) {
3717                 /*
3718                  * For some reason these chicken bits have been
3719                  * stuffed into a transcoder register, event though
3720                  * the bits affect a specific DDI port rather than
3721                  * a specific transcoder.
3722                  */
3723                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3724                 u32 val;
3725
3726                 val = intel_de_read(dev_priv, reg);
3727
3728                 if (port == PORT_E)
3729                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3730                                 DDIE_TRAINING_OVERRIDE_VALUE;
3731                 else
3732                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3733                                 DDI_TRAINING_OVERRIDE_VALUE;
3734
3735                 intel_de_write(dev_priv, reg, val);
3736                 intel_de_posting_read(dev_priv, reg);
3737
3738                 udelay(1);
3739
3740                 if (port == PORT_E)
3741                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3742                                  DDIE_TRAINING_OVERRIDE_VALUE);
3743                 else
3744                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3745                                  DDI_TRAINING_OVERRIDE_VALUE);
3746
3747                 intel_de_write(dev_priv, reg, val);
3748         }
3749
3750         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3751          * are ignored so nothing special needs to be done besides
3752          * enabling the port.
3753          */
3754         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3755                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3756
3757         if (crtc_state->has_audio)
3758                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3759 }
3760
3761 static void intel_enable_ddi(struct intel_atomic_state *state,
3762                              struct intel_encoder *encoder,
3763                              const struct intel_crtc_state *crtc_state,
3764                              const struct drm_connector_state *conn_state)
3765 {
3766         WARN_ON(crtc_state->has_pch_encoder);
3767
3768         intel_ddi_enable_transcoder_func(crtc_state);
3769
3770         intel_enable_pipe(crtc_state);
3771
3772         intel_crtc_vblank_on(crtc_state);
3773
3774         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3775                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3776         else
3777                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3778
3779         /* Enable hdcp if it's desired */
3780         if (conn_state->content_protection ==
3781             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3782                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3783                                   crtc_state->cpu_transcoder,
3784                                   (u8)conn_state->hdcp_content_type);
3785 }
3786
3787 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3788                                  struct intel_encoder *encoder,
3789                                  const struct intel_crtc_state *old_crtc_state,
3790                                  const struct drm_connector_state *old_conn_state)
3791 {
3792         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3793
3794         intel_dp->link_trained = false;
3795
3796         if (old_crtc_state->has_audio)
3797                 intel_audio_codec_disable(encoder,
3798                                           old_crtc_state, old_conn_state);
3799
3800         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3801         intel_psr_disable(intel_dp, old_crtc_state);
3802         intel_edp_backlight_off(old_conn_state);
3803         /* Disable the decompression in DP Sink */
3804         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3805                                               false);
3806 }
3807
3808 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3809                                    struct intel_encoder *encoder,
3810                                    const struct intel_crtc_state *old_crtc_state,
3811                                    const struct drm_connector_state *old_conn_state)
3812 {
3813         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3814         struct drm_connector *connector = old_conn_state->connector;
3815
3816         if (old_crtc_state->has_audio)
3817                 intel_audio_codec_disable(encoder,
3818                                           old_crtc_state, old_conn_state);
3819
3820         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3821                                                false, false))
3822                 drm_dbg_kms(&i915->drm,
3823                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3824                             connector->base.id, connector->name);
3825 }
3826
3827 static void intel_disable_ddi(struct intel_atomic_state *state,
3828                               struct intel_encoder *encoder,
3829                               const struct intel_crtc_state *old_crtc_state,
3830                               const struct drm_connector_state *old_conn_state)
3831 {
3832         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3833
3834         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3835                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3836                                        old_conn_state);
3837         else
3838                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3839                                      old_conn_state);
3840 }
3841
3842 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3843                                      struct intel_encoder *encoder,
3844                                      const struct intel_crtc_state *crtc_state,
3845                                      const struct drm_connector_state *conn_state)
3846 {
3847         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3848
3849         intel_ddi_set_dp_msa(crtc_state, conn_state);
3850
3851         intel_psr_update(intel_dp, crtc_state);
3852         intel_edp_drrs_enable(intel_dp, crtc_state);
3853
3854         intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
3855 }
3856
3857 static void intel_ddi_update_pipe(struct intel_atomic_state *state,
3858                                   struct intel_encoder *encoder,
3859                                   const struct intel_crtc_state *crtc_state,
3860                                   const struct drm_connector_state *conn_state)
3861 {
3862
3863         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3864                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3865                                          conn_state);
3866
3867         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3868 }
3869
3870 static void
3871 intel_ddi_update_prepare(struct intel_atomic_state *state,
3872                          struct intel_encoder *encoder,
3873                          struct intel_crtc *crtc)
3874 {
3875         struct intel_crtc_state *crtc_state =
3876                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3877         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3878
3879         WARN_ON(crtc && crtc->active);
3880
3881         intel_tc_port_get_link(enc_to_dig_port(encoder),
3882                                required_lanes);
3883         if (crtc_state && crtc_state->hw.active)
3884                 intel_update_active_dpll(state, crtc, encoder);
3885 }
3886
3887 static void
3888 intel_ddi_update_complete(struct intel_atomic_state *state,
3889                           struct intel_encoder *encoder,
3890                           struct intel_crtc *crtc)
3891 {
3892         intel_tc_port_put_link(enc_to_dig_port(encoder));
3893 }
3894
3895 static void
3896 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3897                          struct intel_encoder *encoder,
3898                          const struct intel_crtc_state *crtc_state,
3899                          const struct drm_connector_state *conn_state)
3900 {
3901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3902         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3903         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3904         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3905
3906         if (is_tc_port)
3907                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3908
3909         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3910                 intel_display_power_get(dev_priv,
3911                                         intel_ddi_main_link_aux_domain(dig_port));
3912
3913         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3914                 /*
3915                  * Program the lane count for static/dynamic connections on
3916                  * Type-C ports.  Skip this step for TBT.
3917                  */
3918                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3919         else if (IS_GEN9_LP(dev_priv))
3920                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3921                                                 crtc_state->lane_lat_optim_mask);
3922 }
3923
3924 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3925 {
3926         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3927         struct drm_i915_private *dev_priv =
3928                 to_i915(intel_dig_port->base.base.dev);
3929         enum port port = intel_dig_port->base.port;
3930         u32 dp_tp_ctl, ddi_buf_ctl;
3931         bool wait = false;
3932
3933         dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3934
3935         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3936                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3937                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3938                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3939                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3940                         wait = true;
3941                 }
3942
3943                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3944                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3945                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
3946                 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3947
3948                 if (wait)
3949                         intel_wait_ddi_buf_idle(dev_priv, port);
3950         }
3951
3952         dp_tp_ctl = DP_TP_CTL_ENABLE |
3953                     DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3954         if (intel_dp->link_mst)
3955                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3956         else {
3957                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3958                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3959                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3960         }
3961         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
3962         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3963
3964         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3965         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3966         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3967
3968         udelay(600);
3969 }
3970
3971 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3972                                        enum transcoder cpu_transcoder)
3973 {
3974         if (cpu_transcoder == TRANSCODER_EDP)
3975                 return false;
3976
3977         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3978                 return false;
3979
3980         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3981                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3982 }
3983
3984 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3985                                          struct intel_crtc_state *crtc_state)
3986 {
3987         if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3988                 crtc_state->min_voltage_level = 2;
3989         else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
3990                 crtc_state->min_voltage_level = 3;
3991         else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3992                 crtc_state->min_voltage_level = 1;
3993         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3994                 crtc_state->min_voltage_level = 2;
3995 }
3996
3997 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3998                                                      enum transcoder cpu_transcoder)
3999 {
4000         u32 master_select;
4001
4002         if (INTEL_GEN(dev_priv) >= 11) {
4003                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4004
4005                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4006                         return INVALID_TRANSCODER;
4007
4008                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4009         } else {
4010                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4011
4012                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4013                         return INVALID_TRANSCODER;
4014
4015                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4016         }
4017
4018         if (master_select == 0)
4019                 return TRANSCODER_EDP;
4020         else
4021                 return master_select - 1;
4022 }
4023
4024 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4025 {
4026         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4027         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4028                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4029         enum transcoder cpu_transcoder;
4030
4031         crtc_state->master_transcoder =
4032                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4033
4034         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4035                 enum intel_display_power_domain power_domain;
4036                 intel_wakeref_t trans_wakeref;
4037
4038                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4039                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4040                                                                    power_domain);
4041
4042                 if (!trans_wakeref)
4043                         continue;
4044
4045                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4046                     crtc_state->cpu_transcoder)
4047                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4048
4049                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4050         }
4051
4052         drm_WARN_ON(&dev_priv->drm,
4053                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
4054                     crtc_state->sync_mode_slaves_mask);
4055 }
4056
4057 void intel_ddi_get_config(struct intel_encoder *encoder,
4058                           struct intel_crtc_state *pipe_config)
4059 {
4060         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4061         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4062         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4063         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4064         u32 temp, flags = 0;
4065
4066         /* XXX: DSI transcoder paranoia */
4067         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4068                 return;
4069
4070         if (INTEL_GEN(dev_priv) >= 12) {
4071                 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);
4072                 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);
4073         }
4074
4075         intel_dsc_get_config(encoder, pipe_config);
4076
4077         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4078         if (temp & TRANS_DDI_PHSYNC)
4079                 flags |= DRM_MODE_FLAG_PHSYNC;
4080         else
4081                 flags |= DRM_MODE_FLAG_NHSYNC;
4082         if (temp & TRANS_DDI_PVSYNC)
4083                 flags |= DRM_MODE_FLAG_PVSYNC;
4084         else
4085                 flags |= DRM_MODE_FLAG_NVSYNC;
4086
4087         pipe_config->hw.adjusted_mode.flags |= flags;
4088
4089         switch (temp & TRANS_DDI_BPC_MASK) {
4090         case TRANS_DDI_BPC_6:
4091                 pipe_config->pipe_bpp = 18;
4092                 break;
4093         case TRANS_DDI_BPC_8:
4094                 pipe_config->pipe_bpp = 24;
4095                 break;
4096         case TRANS_DDI_BPC_10:
4097                 pipe_config->pipe_bpp = 30;
4098                 break;
4099         case TRANS_DDI_BPC_12:
4100                 pipe_config->pipe_bpp = 36;
4101                 break;
4102         default:
4103                 break;
4104         }
4105
4106         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4107         case TRANS_DDI_MODE_SELECT_HDMI:
4108                 pipe_config->has_hdmi_sink = true;
4109
4110                 pipe_config->infoframes.enable |=
4111                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4112
4113                 if (pipe_config->infoframes.enable)
4114                         pipe_config->has_infoframe = true;
4115
4116                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4117                         pipe_config->hdmi_scrambling = true;
4118                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4119                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4120                 /* fall through */
4121         case TRANS_DDI_MODE_SELECT_DVI:
4122                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4123                 pipe_config->lane_count = 4;
4124                 break;
4125         case TRANS_DDI_MODE_SELECT_FDI:
4126                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4127                 break;
4128         case TRANS_DDI_MODE_SELECT_DP_SST:
4129                 if (encoder->type == INTEL_OUTPUT_EDP)
4130                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4131                 else
4132                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4133                 pipe_config->lane_count =
4134                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4135                 intel_dp_get_m_n(intel_crtc, pipe_config);
4136
4137                 if (INTEL_GEN(dev_priv) >= 11) {
4138                         i915_reg_t dp_tp_ctl;
4139
4140                         if (IS_GEN(dev_priv, 11))
4141                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4142                         else
4143                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4144
4145                         pipe_config->fec_enable =
4146                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4147
4148                         drm_dbg_kms(&dev_priv->drm,
4149                                     "[ENCODER:%d:%s] Fec status: %u\n",
4150                                     encoder->base.base.id, encoder->base.name,
4151                                     pipe_config->fec_enable);
4152                 }
4153
4154                 break;
4155         case TRANS_DDI_MODE_SELECT_DP_MST:
4156                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4157                 pipe_config->lane_count =
4158                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4159
4160                 if (INTEL_GEN(dev_priv) >= 12)
4161                         pipe_config->mst_master_transcoder =
4162                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4163
4164                 intel_dp_get_m_n(intel_crtc, pipe_config);
4165                 break;
4166         default:
4167                 break;
4168         }
4169
4170         pipe_config->has_audio =
4171                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4172
4173         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4174             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4175                 /*
4176                  * This is a big fat ugly hack.
4177                  *
4178                  * Some machines in UEFI boot mode provide us a VBT that has 18
4179                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4180                  * unknown we fail to light up. Yet the same BIOS boots up with
4181                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4182                  * max, not what it tells us to use.
4183                  *
4184                  * Note: This will still be broken if the eDP panel is not lit
4185                  * up by the BIOS, and thus we can't get the mode at module
4186                  * load.
4187                  */
4188                 drm_dbg_kms(&dev_priv->drm,
4189                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4190                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4191                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4192         }
4193
4194         intel_ddi_clock_get(encoder, pipe_config);
4195
4196         if (IS_GEN9_LP(dev_priv))
4197                 pipe_config->lane_lat_optim_mask =
4198                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4199
4200         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4201
4202         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4203
4204         intel_read_infoframe(encoder, pipe_config,
4205                              HDMI_INFOFRAME_TYPE_AVI,
4206                              &pipe_config->infoframes.avi);
4207         intel_read_infoframe(encoder, pipe_config,
4208                              HDMI_INFOFRAME_TYPE_SPD,
4209                              &pipe_config->infoframes.spd);
4210         intel_read_infoframe(encoder, pipe_config,
4211                              HDMI_INFOFRAME_TYPE_VENDOR,
4212                              &pipe_config->infoframes.hdmi);
4213         intel_read_infoframe(encoder, pipe_config,
4214                              HDMI_INFOFRAME_TYPE_DRM,
4215                              &pipe_config->infoframes.drm);
4216
4217         if (INTEL_GEN(dev_priv) >= 8)
4218                 bdw_get_trans_port_sync_config(pipe_config);
4219 }
4220
4221 static enum intel_output_type
4222 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4223                               struct intel_crtc_state *crtc_state,
4224                               struct drm_connector_state *conn_state)
4225 {
4226         switch (conn_state->connector->connector_type) {
4227         case DRM_MODE_CONNECTOR_HDMIA:
4228                 return INTEL_OUTPUT_HDMI;
4229         case DRM_MODE_CONNECTOR_eDP:
4230                 return INTEL_OUTPUT_EDP;
4231         case DRM_MODE_CONNECTOR_DisplayPort:
4232                 return INTEL_OUTPUT_DP;
4233         default:
4234                 MISSING_CASE(conn_state->connector->connector_type);
4235                 return INTEL_OUTPUT_UNUSED;
4236         }
4237 }
4238
4239 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4240                                     struct intel_crtc_state *pipe_config,
4241                                     struct drm_connector_state *conn_state)
4242 {
4243         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4245         enum port port = encoder->port;
4246         int ret;
4247
4248         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4249                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4250
4251         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4252                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4253         } else {
4254                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4255         }
4256
4257         if (ret)
4258                 return ret;
4259
4260         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4261             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4262                 pipe_config->pch_pfit.force_thru =
4263                         pipe_config->pch_pfit.enabled ||
4264                         pipe_config->crc_enabled;
4265
4266         if (IS_GEN9_LP(dev_priv))
4267                 pipe_config->lane_lat_optim_mask =
4268                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4269
4270         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4271
4272         return 0;
4273 }
4274
4275 static bool mode_equal(const struct drm_display_mode *mode1,
4276                        const struct drm_display_mode *mode2)
4277 {
4278         return drm_mode_match(mode1, mode2,
4279                               DRM_MODE_MATCH_TIMINGS |
4280                               DRM_MODE_MATCH_FLAGS |
4281                               DRM_MODE_MATCH_3D_FLAGS) &&
4282                 mode1->clock == mode2->clock; /* we want an exact match */
4283 }
4284
4285 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4286                       const struct intel_link_m_n *m_n_2)
4287 {
4288         return m_n_1->tu == m_n_2->tu &&
4289                 m_n_1->gmch_m == m_n_2->gmch_m &&
4290                 m_n_1->gmch_n == m_n_2->gmch_n &&
4291                 m_n_1->link_m == m_n_2->link_m &&
4292                 m_n_1->link_n == m_n_2->link_n;
4293 }
4294
4295 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4296                                        const struct intel_crtc_state *crtc_state2)
4297 {
4298         return crtc_state1->hw.active && crtc_state2->hw.active &&
4299                 crtc_state1->output_types == crtc_state2->output_types &&
4300                 crtc_state1->output_format == crtc_state2->output_format &&
4301                 crtc_state1->lane_count == crtc_state2->lane_count &&
4302                 crtc_state1->port_clock == crtc_state2->port_clock &&
4303                 mode_equal(&crtc_state1->hw.adjusted_mode,
4304                            &crtc_state2->hw.adjusted_mode) &&
4305                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4306 }
4307
4308 static u8
4309 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4310                                 int tile_group_id)
4311 {
4312         struct drm_connector *connector;
4313         const struct drm_connector_state *conn_state;
4314         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4315         struct intel_atomic_state *state =
4316                 to_intel_atomic_state(ref_crtc_state->uapi.state);
4317         u8 transcoders = 0;
4318         int i;
4319
4320         /*
4321          * We don't enable port sync on BDW due to missing w/as and
4322          * due to not having adjusted the modeset sequence appropriately.
4323          */
4324         if (INTEL_GEN(dev_priv) < 9)
4325                 return 0;
4326
4327         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4328                 return 0;
4329
4330         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4331                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4332                 const struct intel_crtc_state *crtc_state;
4333
4334                 if (!crtc)
4335                         continue;
4336
4337                 if (!connector->has_tile ||
4338                     connector->tile_group->id !=
4339                     tile_group_id)
4340                         continue;
4341                 crtc_state = intel_atomic_get_new_crtc_state(state,
4342                                                              crtc);
4343                 if (!crtcs_port_sync_compatible(ref_crtc_state,
4344                                                 crtc_state))
4345                         continue;
4346                 transcoders |= BIT(crtc_state->cpu_transcoder);
4347         }
4348
4349         return transcoders;
4350 }
4351
4352 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4353                                          struct intel_crtc_state *crtc_state,
4354                                          struct drm_connector_state *conn_state)
4355 {
4356         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4357         struct drm_connector *connector = conn_state->connector;
4358         u8 port_sync_transcoders = 0;
4359
4360         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4361                     encoder->base.base.id, encoder->base.name,
4362                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4363
4364         if (connector->has_tile)
4365                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4366                                                                         connector->tile_group->id);
4367
4368         /*
4369          * EDP Transcoders cannot be ensalved
4370          * make them a master always when present
4371          */
4372         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4373                 crtc_state->master_transcoder = TRANSCODER_EDP;
4374         else
4375                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4376
4377         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4378                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4379                 crtc_state->sync_mode_slaves_mask =
4380                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4381         }
4382
4383         return 0;
4384 }
4385
4386 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4387 {
4388         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4389
4390         intel_dp_encoder_flush_work(encoder);
4391
4392         drm_encoder_cleanup(encoder);
4393         kfree(dig_port);
4394 }
4395
4396 static const struct drm_encoder_funcs intel_ddi_funcs = {
4397         .reset = intel_dp_encoder_reset,
4398         .destroy = intel_ddi_encoder_destroy,
4399 };
4400
4401 static struct intel_connector *
4402 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4403 {
4404         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
4405         struct intel_connector *connector;
4406         enum port port = intel_dig_port->base.port;
4407
4408         connector = intel_connector_alloc();
4409         if (!connector)
4410                 return NULL;
4411
4412         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4413         intel_dig_port->dp.prepare_link_retrain =
4414                 intel_ddi_prepare_link_retrain;
4415         if (INTEL_GEN(dev_priv) < 12) {
4416                 intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
4417                 intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
4418         }
4419
4420         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4421                 kfree(connector);
4422                 return NULL;
4423         }
4424
4425         return connector;
4426 }
4427
4428 static int modeset_pipe(struct drm_crtc *crtc,
4429                         struct drm_modeset_acquire_ctx *ctx)
4430 {
4431         struct drm_atomic_state *state;
4432         struct drm_crtc_state *crtc_state;
4433         int ret;
4434
4435         state = drm_atomic_state_alloc(crtc->dev);
4436         if (!state)
4437                 return -ENOMEM;
4438
4439         state->acquire_ctx = ctx;
4440
4441         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4442         if (IS_ERR(crtc_state)) {
4443                 ret = PTR_ERR(crtc_state);
4444                 goto out;
4445         }
4446
4447         crtc_state->connectors_changed = true;
4448
4449         ret = drm_atomic_commit(state);
4450 out:
4451         drm_atomic_state_put(state);
4452
4453         return ret;
4454 }
4455
4456 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4457                                  struct drm_modeset_acquire_ctx *ctx)
4458 {
4459         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4460         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4461         struct intel_connector *connector = hdmi->attached_connector;
4462         struct i2c_adapter *adapter =
4463                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4464         struct drm_connector_state *conn_state;
4465         struct intel_crtc_state *crtc_state;
4466         struct intel_crtc *crtc;
4467         u8 config;
4468         int ret;
4469
4470         if (!connector || connector->base.status != connector_status_connected)
4471                 return 0;
4472
4473         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4474                                ctx);
4475         if (ret)
4476                 return ret;
4477
4478         conn_state = connector->base.state;
4479
4480         crtc = to_intel_crtc(conn_state->crtc);
4481         if (!crtc)
4482                 return 0;
4483
4484         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4485         if (ret)
4486                 return ret;
4487
4488         crtc_state = to_intel_crtc_state(crtc->base.state);
4489
4490         drm_WARN_ON(&dev_priv->drm,
4491                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4492
4493         if (!crtc_state->hw.active)
4494                 return 0;
4495
4496         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4497             !crtc_state->hdmi_scrambling)
4498                 return 0;
4499
4500         if (conn_state->commit &&
4501             !try_wait_for_completion(&conn_state->commit->hw_done))
4502                 return 0;
4503
4504         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4505         if (ret < 0) {
4506                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4507                         ret);
4508                 return 0;
4509         }
4510
4511         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4512             crtc_state->hdmi_high_tmds_clock_ratio &&
4513             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4514             crtc_state->hdmi_scrambling)
4515                 return 0;
4516
4517         /*
4518          * HDMI 2.0 says that one should not send scrambled data
4519          * prior to configuring the sink scrambling, and that
4520          * TMDS clock/data transmission should be suspended when
4521          * changing the TMDS clock rate in the sink. So let's
4522          * just do a full modeset here, even though some sinks
4523          * would be perfectly happy if were to just reconfigure
4524          * the SCDC settings on the fly.
4525          */
4526         return modeset_pipe(&crtc->base, ctx);
4527 }
4528
4529 static enum intel_hotplug_state
4530 intel_ddi_hotplug(struct intel_encoder *encoder,
4531                   struct intel_connector *connector)
4532 {
4533         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4534         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4535         enum phy phy = intel_port_to_phy(i915, encoder->port);
4536         bool is_tc = intel_phy_is_tc(i915, phy);
4537         struct drm_modeset_acquire_ctx ctx;
4538         enum intel_hotplug_state state;
4539         int ret;
4540
4541         state = intel_encoder_hotplug(encoder, connector);
4542
4543         drm_modeset_acquire_init(&ctx, 0);
4544
4545         for (;;) {
4546                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4547                         ret = intel_hdmi_reset_link(encoder, &ctx);
4548                 else
4549                         ret = intel_dp_retrain_link(encoder, &ctx);
4550
4551                 if (ret == -EDEADLK) {
4552                         drm_modeset_backoff(&ctx);
4553                         continue;
4554                 }
4555
4556                 break;
4557         }
4558
4559         drm_modeset_drop_locks(&ctx);
4560         drm_modeset_acquire_fini(&ctx);
4561         drm_WARN(encoder->base.dev, ret,
4562                  "Acquiring modeset locks failed with %i\n", ret);
4563
4564         /*
4565          * Unpowered type-c dongles can take some time to boot and be
4566          * responsible, so here giving some time to those dongles to power up
4567          * and then retrying the probe.
4568          *
4569          * On many platforms the HDMI live state signal is known to be
4570          * unreliable, so we can't use it to detect if a sink is connected or
4571          * not. Instead we detect if it's connected based on whether we can
4572          * read the EDID or not. That in turn has a problem during disconnect,
4573          * since the HPD interrupt may be raised before the DDC lines get
4574          * disconnected (due to how the required length of DDC vs. HPD
4575          * connector pins are specified) and so we'll still be able to get a
4576          * valid EDID. To solve this schedule another detection cycle if this
4577          * time around we didn't detect any change in the sink's connection
4578          * status.
4579          *
4580          * Type-c connectors which get their HPD signal deasserted then
4581          * reasserted, without unplugging/replugging the sink from the
4582          * connector, introduce a delay until the AUX channel communication
4583          * becomes functional. Retry the detection for 5 seconds on type-c
4584          * connectors to account for this delay.
4585          */
4586         if (state == INTEL_HOTPLUG_UNCHANGED &&
4587             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4588             !dig_port->dp.is_mst)
4589                 state = INTEL_HOTPLUG_RETRY;
4590
4591         return state;
4592 }
4593
4594 static struct intel_connector *
4595 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4596 {
4597         struct intel_connector *connector;
4598         enum port port = intel_dig_port->base.port;
4599
4600         connector = intel_connector_alloc();
4601         if (!connector)
4602                 return NULL;
4603
4604         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4605         intel_hdmi_init_connector(intel_dig_port, connector);
4606
4607         return connector;
4608 }
4609
4610 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4611 {
4612         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4613
4614         if (dport->base.port != PORT_A)
4615                 return false;
4616
4617         if (dport->saved_port_bits & DDI_A_4_LANES)
4618                 return false;
4619
4620         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4621          *                     supported configuration
4622          */
4623         if (IS_GEN9_LP(dev_priv))
4624                 return true;
4625
4626         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4627          *             one who does also have a full A/E split called
4628          *             DDI_F what makes DDI_E useless. However for this
4629          *             case let's trust VBT info.
4630          */
4631         if (IS_CANNONLAKE(dev_priv) &&
4632             !intel_bios_is_port_present(dev_priv, PORT_E))
4633                 return true;
4634
4635         return false;
4636 }
4637
4638 static int
4639 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4640 {
4641         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4642         enum port port = intel_dport->base.port;
4643         int max_lanes = 4;
4644
4645         if (INTEL_GEN(dev_priv) >= 11)
4646                 return max_lanes;
4647
4648         if (port == PORT_A || port == PORT_E) {
4649                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4650                         max_lanes = port == PORT_A ? 4 : 0;
4651                 else
4652                         /* Both A and E share 2 lanes */
4653                         max_lanes = 2;
4654         }
4655
4656         /*
4657          * Some BIOS might fail to set this bit on port A if eDP
4658          * wasn't lit up at boot.  Force this bit set when needed
4659          * so we use the proper lane count for our calculations.
4660          */
4661         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4662                 drm_dbg_kms(&dev_priv->drm,
4663                             "Forcing DDI_A_4_LANES for port A\n");
4664                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4665                 max_lanes = 4;
4666         }
4667
4668         return max_lanes;
4669 }
4670
4671 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4672 {
4673         struct intel_digital_port *intel_dig_port;
4674         struct intel_encoder *encoder;
4675         bool init_hdmi, init_dp, init_lspcon = false;
4676         enum phy phy = intel_port_to_phy(dev_priv, port);
4677
4678         init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
4679                 intel_bios_port_supports_hdmi(dev_priv, port);
4680         init_dp = intel_bios_port_supports_dp(dev_priv, port);
4681
4682         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4683                 /*
4684                  * Lspcon device needs to be driven with DP connector
4685                  * with special detection sequence. So make sure DP
4686                  * is initialized before lspcon.
4687                  */
4688                 init_dp = true;
4689                 init_lspcon = true;
4690                 init_hdmi = false;
4691                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4692                             port_name(port));
4693         }
4694
4695         if (!init_dp && !init_hdmi) {
4696                 drm_dbg_kms(&dev_priv->drm,
4697                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4698                             port_name(port));
4699                 return;
4700         }
4701
4702         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4703         if (!intel_dig_port)
4704                 return;
4705
4706         encoder = &intel_dig_port->base;
4707
4708         drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4709                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4710
4711         encoder->hotplug = intel_ddi_hotplug;
4712         encoder->compute_output_type = intel_ddi_compute_output_type;
4713         encoder->compute_config = intel_ddi_compute_config;
4714         encoder->compute_config_late = intel_ddi_compute_config_late;
4715         encoder->enable = intel_enable_ddi;
4716         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4717         encoder->pre_enable = intel_ddi_pre_enable;
4718         encoder->disable = intel_disable_ddi;
4719         encoder->post_disable = intel_ddi_post_disable;
4720         encoder->update_pipe = intel_ddi_update_pipe;
4721         encoder->get_hw_state = intel_ddi_get_hw_state;
4722         encoder->get_config = intel_ddi_get_config;
4723         encoder->suspend = intel_dp_encoder_suspend;
4724         encoder->get_power_domains = intel_ddi_get_power_domains;
4725
4726         encoder->type = INTEL_OUTPUT_DDI;
4727         encoder->power_domain = intel_port_to_power_domain(port);
4728         encoder->port = port;
4729         encoder->cloneable = 0;
4730         encoder->pipe_mask = ~0;
4731
4732         if (INTEL_GEN(dev_priv) >= 11)
4733                 intel_dig_port->saved_port_bits = intel_de_read(dev_priv,
4734                                                                 DDI_BUF_CTL(port)) &
4735                         DDI_BUF_PORT_REVERSAL;
4736         else
4737                 intel_dig_port->saved_port_bits = intel_de_read(dev_priv,
4738                                                                 DDI_BUF_CTL(port)) &
4739                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4740
4741         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4742         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4743         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4744
4745         if (intel_phy_is_tc(dev_priv, phy)) {
4746                 bool is_legacy =
4747                         !intel_bios_port_supports_typec_usb(dev_priv, port) &&
4748                         !intel_bios_port_supports_tbt(dev_priv, port);
4749
4750                 intel_tc_port_init(intel_dig_port, is_legacy);
4751
4752                 encoder->update_prepare = intel_ddi_update_prepare;
4753                 encoder->update_complete = intel_ddi_update_complete;
4754         }
4755
4756         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4757         intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4758                                               port - PORT_A;
4759
4760         if (init_dp) {
4761                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4762                         goto err;
4763
4764                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4765         }
4766
4767         /* In theory we don't need the encoder->type check, but leave it just in
4768          * case we have some really bad VBTs... */
4769         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4770                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4771                         goto err;
4772         }
4773
4774         if (init_lspcon) {
4775                 if (lspcon_init(intel_dig_port))
4776                         /* TODO: handle hdmi info frame part */
4777                         drm_dbg_kms(&dev_priv->drm,
4778                                     "LSPCON init success on port %c\n",
4779                                     port_name(port));
4780                 else
4781                         /*
4782                          * LSPCON init faied, but DP init was success, so
4783                          * lets try to drive as DP++ port.
4784                          */
4785                         drm_err(&dev_priv->drm,
4786                                 "LSPCON init failed on port %c\n",
4787                                 port_name(port));
4788         }
4789
4790         intel_infoframe_init(intel_dig_port);
4791
4792         return;
4793
4794 err:
4795         drm_encoder_cleanup(&encoder->base);
4796         kfree(intel_dig_port);
4797 }