drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_audio.h"
  33 #include "intel_combo_phy.h"
  34 #include "intel_connector.h"
  35 #include "intel_ddi.h"
  36 #include "intel_display_types.h"
  37 #include "intel_dp.h"
  38 #include "intel_dp_mst.h"
  39 #include "intel_dp_link_training.h"
  40 #include "intel_dpio_phy.h"
  41 #include "intel_dsi.h"
  42 #include "intel_fifo_underrun.h"
  43 #include "intel_gmbus.h"
  44 #include "intel_hdcp.h"
  45 #include "intel_hdmi.h"
  46 #include "intel_hotplug.h"
  47 #include "intel_lspcon.h"
  48 #include "intel_panel.h"
  49 #include "intel_psr.h"
  50 #include "intel_sprite.h"
  51 #include "intel_tc.h"
  52 #include "intel_vdsc.h"
  53
  54 struct ddi_buf_trans {
  55         u32 trans1;     /* balance leg enable, de-emph level */
  56         u32 trans2;     /* vref sel, vswing */
  57         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  58 };
  59
  60 static const u8 index_to_dp_signal_levels[] = {
  61         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  62         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  63         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  64         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  65         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  66         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  67         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  68         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  70         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  71 };
  72
  73 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  74  * them for both DP and FDI transports, allowing those ports to
  75  * automatically adapt to HDMI connections as well
  76  */
  77 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  78         { 0x00FFFFFF, 0x0006000E, 0x0 },
  79         { 0x00D75FFF, 0x0005000A, 0x0 },
  80         { 0x00C30FFF, 0x00040006, 0x0 },
  81         { 0x80AAAFFF, 0x000B0000, 0x0 },
  82         { 0x00FFFFFF, 0x0005000A, 0x0 },
  83         { 0x00D75FFF, 0x000C0004, 0x0 },
  84         { 0x80C30FFF, 0x000B0000, 0x0 },
  85         { 0x00FFFFFF, 0x00040006, 0x0 },
  86         { 0x80D75FFF, 0x000B0000, 0x0 },
  87 };
  88
  89 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  90         { 0x00FFFFFF, 0x0007000E, 0x0 },
  91         { 0x00D75FFF, 0x000F000A, 0x0 },
  92         { 0x00C30FFF, 0x00060006, 0x0 },
  93         { 0x00AAAFFF, 0x001E0000, 0x0 },
  94         { 0x00FFFFFF, 0x000F000A, 0x0 },
  95         { 0x00D75FFF, 0x00160004, 0x0 },
  96         { 0x00C30FFF, 0x001E0000, 0x0 },
  97         { 0x00FFFFFF, 0x00060006, 0x0 },
  98         { 0x00D75FFF, 0x001E0000, 0x0 },
  99 };
 100
 101 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 102                                         /* Idx  NT mV d T mV d  db      */
 103         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 104         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 105         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 106         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 107         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 108         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 109         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 110         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 111         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 112         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 113         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 114         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 118         { 0x00FFFFFF, 0x00000012, 0x0 },
 119         { 0x00EBAFFF, 0x00020011, 0x0 },
 120         { 0x00C71FFF, 0x0006000F, 0x0 },
 121         { 0x00AAAFFF, 0x000E000A, 0x0 },
 122         { 0x00FFFFFF, 0x00020011, 0x0 },
 123         { 0x00DB6FFF, 0x0005000F, 0x0 },
 124         { 0x00BEEFFF, 0x000A000C, 0x0 },
 125         { 0x00FFFFFF, 0x0005000F, 0x0 },
 126         { 0x00DB6FFF, 0x000A000C, 0x0 },
 127 };
 128
 129 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 130         { 0x00FFFFFF, 0x0007000E, 0x0 },
 131         { 0x00D75FFF, 0x000E000A, 0x0 },
 132         { 0x00BEFFFF, 0x00140006, 0x0 },
 133         { 0x80B2CFFF, 0x001B0002, 0x0 },
 134         { 0x00FFFFFF, 0x000E000A, 0x0 },
 135         { 0x00DB6FFF, 0x00160005, 0x0 },
 136         { 0x80C71FFF, 0x001A0002, 0x0 },
 137         { 0x00F7DFFF, 0x00180004, 0x0 },
 138         { 0x80D75FFF, 0x001B0002, 0x0 },
 139 };
 140
 141 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 142         { 0x00FFFFFF, 0x0001000E, 0x0 },
 143         { 0x00D75FFF, 0x0004000A, 0x0 },
 144         { 0x00C30FFF, 0x00070006, 0x0 },
 145         { 0x00AAAFFF, 0x000C0000, 0x0 },
 146         { 0x00FFFFFF, 0x0004000A, 0x0 },
 147         { 0x00D75FFF, 0x00090004, 0x0 },
 148         { 0x00C30FFF, 0x000C0000, 0x0 },
 149         { 0x00FFFFFF, 0x00070006, 0x0 },
 150         { 0x00D75FFF, 0x000C0000, 0x0 },
 151 };
 152
 153 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 154                                         /* Idx  NT mV d T mV df db      */
 155         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 156         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 157         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 158         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 159         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 160         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 161         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 162         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 163         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 164         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 165 };
 166
 167 /* Skylake H and S */
 168 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 169         { 0x00002016, 0x000000A0, 0x0 },
 170         { 0x00005012, 0x0000009B, 0x0 },
 171         { 0x00007011, 0x00000088, 0x0 },
 172         { 0x80009010, 0x000000C0, 0x1 },
 173         { 0x00002016, 0x0000009B, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000C0, 0x1 },
 176         { 0x00002016, 0x000000DF, 0x0 },
 177         { 0x80005012, 0x000000C0, 0x1 },
 178 };
 179
 180 /* Skylake U */
 181 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 182         { 0x0000201B, 0x000000A2, 0x0 },
 183         { 0x00005012, 0x00000088, 0x0 },
 184         { 0x80007011, 0x000000CD, 0x1 },
 185         { 0x80009010, 0x000000C0, 0x1 },
 186         { 0x0000201B, 0x0000009D, 0x0 },
 187         { 0x80005012, 0x000000C0, 0x1 },
 188         { 0x80007011, 0x000000C0, 0x1 },
 189         { 0x00002016, 0x00000088, 0x0 },
 190         { 0x80005012, 0x000000C0, 0x1 },
 191 };
 192
 193 /* Skylake Y */
 194 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 195         { 0x00000018, 0x000000A2, 0x0 },
 196         { 0x00005012, 0x00000088, 0x0 },
 197         { 0x80007011, 0x000000CD, 0x3 },
 198         { 0x80009010, 0x000000C0, 0x3 },
 199         { 0x00000018, 0x0000009D, 0x0 },
 200         { 0x80005012, 0x000000C0, 0x3 },
 201         { 0x80007011, 0x000000C0, 0x3 },
 202         { 0x00000018, 0x00000088, 0x0 },
 203         { 0x80005012, 0x000000C0, 0x3 },
 204 };
 205
 206 /* Kabylake H and S */
 207 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 208         { 0x00002016, 0x000000A0, 0x0 },
 209         { 0x00005012, 0x0000009B, 0x0 },
 210         { 0x00007011, 0x00000088, 0x0 },
 211         { 0x80009010, 0x000000C0, 0x1 },
 212         { 0x00002016, 0x0000009B, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000C0, 0x1 },
 215         { 0x00002016, 0x00000097, 0x0 },
 216         { 0x80005012, 0x000000C0, 0x1 },
 217 };
 218
 219 /* Kabylake U */
 220 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 221         { 0x0000201B, 0x000000A1, 0x0 },
 222         { 0x00005012, 0x00000088, 0x0 },
 223         { 0x80007011, 0x000000CD, 0x3 },
 224         { 0x80009010, 0x000000C0, 0x3 },
 225         { 0x0000201B, 0x0000009D, 0x0 },
 226         { 0x80005012, 0x000000C0, 0x3 },
 227         { 0x80007011, 0x000000C0, 0x3 },
 228         { 0x00002016, 0x0000004F, 0x0 },
 229         { 0x80005012, 0x000000C0, 0x3 },
 230 };
 231
 232 /* Kabylake Y */
 233 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 234         { 0x00001017, 0x000000A1, 0x0 },
 235         { 0x00005012, 0x00000088, 0x0 },
 236         { 0x80007011, 0x000000CD, 0x3 },
 237         { 0x8000800F, 0x000000C0, 0x3 },
 238         { 0x00001017, 0x0000009D, 0x0 },
 239         { 0x80005012, 0x000000C0, 0x3 },
 240         { 0x80007011, 0x000000C0, 0x3 },
 241         { 0x00001017, 0x0000004C, 0x0 },
 242         { 0x80005012, 0x000000C0, 0x3 },
 243 };
 244
 245 /*
 246  * Skylake/Kabylake H and S
 247  * eDP 1.4 low vswing translation parameters
 248  */
 249 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 250         { 0x00000018, 0x000000A8, 0x0 },
 251         { 0x00004013, 0x000000A9, 0x0 },
 252         { 0x00007011, 0x000000A2, 0x0 },
 253         { 0x00009010, 0x0000009C, 0x0 },
 254         { 0x00000018, 0x000000A9, 0x0 },
 255         { 0x00006013, 0x000000A2, 0x0 },
 256         { 0x00007011, 0x000000A6, 0x0 },
 257         { 0x00000018, 0x000000AB, 0x0 },
 258         { 0x00007013, 0x0000009F, 0x0 },
 259         { 0x00000018, 0x000000DF, 0x0 },
 260 };
 261
 262 /*
 263  * Skylake/Kabylake U
 264  * eDP 1.4 low vswing translation parameters
 265  */
 266 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 267         { 0x00000018, 0x000000A8, 0x0 },
 268         { 0x00004013, 0x000000A9, 0x0 },
 269         { 0x00007011, 0x000000A2, 0x0 },
 270         { 0x00009010, 0x0000009C, 0x0 },
 271         { 0x00000018, 0x000000A9, 0x0 },
 272         { 0x00006013, 0x000000A2, 0x0 },
 273         { 0x00007011, 0x000000A6, 0x0 },
 274         { 0x00002016, 0x000000AB, 0x0 },
 275         { 0x00005013, 0x0000009F, 0x0 },
 276         { 0x00000018, 0x000000DF, 0x0 },
 277 };
 278
 279 /*
 280  * Skylake/Kabylake Y
 281  * eDP 1.4 low vswing translation parameters
 282  */
 283 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 284         { 0x00000018, 0x000000A8, 0x0 },
 285         { 0x00004013, 0x000000AB, 0x0 },
 286         { 0x00007011, 0x000000A4, 0x0 },
 287         { 0x00009010, 0x000000DF, 0x0 },
 288         { 0x00000018, 0x000000AA, 0x0 },
 289         { 0x00006013, 0x000000A4, 0x0 },
 290         { 0x00007011, 0x0000009D, 0x0 },
 291         { 0x00000018, 0x000000A0, 0x0 },
 292         { 0x00006012, 0x000000DF, 0x0 },
 293         { 0x00000018, 0x0000008A, 0x0 },
 294 };
 295
 296 /* Skylake/Kabylake U, H and S */
 297 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 298         { 0x00000018, 0x000000AC, 0x0 },
 299         { 0x00005012, 0x0000009D, 0x0 },
 300         { 0x00007011, 0x00000088, 0x0 },
 301         { 0x00000018, 0x000000A1, 0x0 },
 302         { 0x00000018, 0x00000098, 0x0 },
 303         { 0x00004013, 0x00000088, 0x0 },
 304         { 0x80006012, 0x000000CD, 0x1 },
 305         { 0x00000018, 0x000000DF, 0x0 },
 306         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 307         { 0x80003015, 0x000000C0, 0x1 },
 308         { 0x80000018, 0x000000C0, 0x1 },
 309 };
 310
 311 /* Skylake/Kabylake Y */
 312 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 313         { 0x00000018, 0x000000A1, 0x0 },
 314         { 0x00005012, 0x000000DF, 0x0 },
 315         { 0x80007011, 0x000000CB, 0x3 },
 316         { 0x00000018, 0x000000A4, 0x0 },
 317         { 0x00000018, 0x0000009D, 0x0 },
 318         { 0x00004013, 0x00000080, 0x0 },
 319         { 0x80006013, 0x000000C0, 0x3 },
 320         { 0x00000018, 0x0000008A, 0x0 },
 321         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 322         { 0x80003015, 0x000000C0, 0x3 },
 323         { 0x80000018, 0x000000C0, 0x3 },
 324 };
 325
 326 struct bxt_ddi_buf_trans {
 327         u8 margin;      /* swing value */
 328         u8 scale;       /* scale value */
 329         u8 enable;      /* scale enable */
 330         u8 deemphasis;
 331 };
 332
 333 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 334                                         /* Idx  NT mV diff      db  */
 335         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 336         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 337         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 338         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 339         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 340         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 341         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 342         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 343         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 344         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 345 };
 346
 347 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 348                                         /* Idx  NT mV diff      db  */
 349         { 26, 0, 0, 128, },     /* 0:   200             0   */
 350         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 351         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 352         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 353         { 32, 0, 0, 128, },     /* 4:   250             0   */
 354         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 355         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 356         { 43, 0, 0, 128, },     /* 7:   300             0   */
 357         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 358         { 48, 0, 0, 128, },     /* 9:   300             0   */
 359 };
 360
 361 /* BSpec has 2 recommended values - entries 0 and 8.
 362  * Using the entry with higher vswing.
 363  */
 364 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 365                                         /* Idx  NT mV diff      db  */
 366         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 367         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 368         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 369         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 370         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 371         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 372         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 373         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 374         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 375         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 376 };
 377
 378 struct cnl_ddi_buf_trans {
 379         u8 dw2_swing_sel;
 380         u8 dw7_n_scalar;
 381         u8 dw4_cursor_coeff;
 382         u8 dw4_post_cursor_2;
 383         u8 dw4_post_cursor_1;
 384 };
 385
 386 /* Voltage Swing Programming for VccIO 0.85V for DP */
 387 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 388                                                 /* NT mV Trans mV db    */
 389         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 390         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 391         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 392         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 393         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 394         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 395         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 396         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 397         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 398         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 399 };
 400
 401 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 402 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 403                                                 /* NT mV Trans mV db    */
 404         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 405         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 406         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 407         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 408         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 409         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 410         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 411 };
 412
 413 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 414 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 415                                                 /* NT mV Trans mV db    */
 416         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 417         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 418         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 419         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 420         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 421         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 422         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 423         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 424         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 425 };
 426
 427 /* Voltage Swing Programming for VccIO 0.95V for DP */
 428 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 429                                                 /* NT mV Trans mV db    */
 430         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 431         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 432         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 433         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 434         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 435         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 436         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 437         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 438         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 439         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 440 };
 441
 442 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 443 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 444                                                 /* NT mV Trans mV db    */
 445         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 446         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 447         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 448         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 449         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 450         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 451         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 452         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 453         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 454         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 455         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 456 };
 457
 458 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 459 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 460                                                 /* NT mV Trans mV db    */
 461         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 462         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 463         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 464         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 465         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 466         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 467         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 468         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 469         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 470         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 471 };
 472
 473 /* Voltage Swing Programming for VccIO 1.05V for DP */
 474 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 475                                                 /* NT mV Trans mV db    */
 476         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 477         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 478         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 479         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 480         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 481         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 482         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 483         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 484         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 485         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 486 };
 487
 488 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 489 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 490                                                 /* NT mV Trans mV db    */
 491         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 492         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 493         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 494         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 495         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 496         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 497         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 498         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 499         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 500         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 501         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 502 };
 503
 504 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 505 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 506                                                 /* NT mV Trans mV db    */
 507         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 508         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 509         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 510         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 511         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 512         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 513         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 514         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 515         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 516 };
 517
 518 /* icl_combo_phy_ddi_translations */
 519 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 520                                                 /* NT mV Trans mV db    */
 521         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 522         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 523         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 524         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 525         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 526         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 527         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 528         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 529         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 530         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 531 };
 532
 533 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 534                                                 /* NT mV Trans mV db    */
 535         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 536         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 537         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 538         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 539         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 540         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 541         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 542         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 543         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 544         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 545 };
 546
 547 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 548                                                 /* NT mV Trans mV db    */
 549         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 550         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 551         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 552         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 553         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 554         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 555         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 556         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 557         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 558         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 559 };
 560
 561 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 562                                                 /* NT mV Trans mV db    */
 563         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 564         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 565         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 566         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 567         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 568         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 569         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 570 };
 571
 572 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 573                                                 /* NT mV Trans mV db    */
 574         { 0xA, 0x33, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 575         { 0xA, 0x47, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 576         { 0xC, 0x64, 0x34, 0x00, 0x0B },        /* 350   700      6.0   */
 577         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 350   900      8.2   */
 578         { 0xA, 0x46, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 579         { 0xC, 0x64, 0x38, 0x00, 0x07 },        /* 500   700      2.9   */
 580         { 0x6, 0x7F, 0x32, 0x00, 0x0D },        /* 500   900      5.1   */
 581         { 0xC, 0x61, 0x3F, 0x00, 0x00 },        /* 650   700      0.6   */
 582         { 0x6, 0x7F, 0x38, 0x00, 0x07 },        /* 600   900      3.5   */
 583         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 584 };
 585
 586 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
 587                                                 /* NT mV Trans mV db    */
 588         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 589         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 590         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 591         { 0xA, 0x35, 0x36, 0x00, 0x09 },        /* 200   350      4.9   */
 592         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 593         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 594         { 0xA, 0x35, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 595         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 596         { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 597         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 598 };
 599
 600 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
 601                                                 /* NT mV Trans mV db    */
 602         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 603         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   250      1.9   */
 604         { 0x1, 0x7F, 0x3D, 0x00, 0x02 },        /* 200   300      3.5   */
 605         { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 200   350      4.9   */
 606         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 607         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   300      1.6   */
 608         { 0xA, 0x35, 0x3A, 0x00, 0x05 },        /* 250   350      2.9   */
 609         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 610         { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 611         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 612 };
 613
 614 struct icl_mg_phy_ddi_buf_trans {
 615         u32 cri_txdeemph_override_11_6;
 616         u32 cri_txdeemph_override_5_0;
 617         u32 cri_txdeemph_override_17_12;
 618 };
 619
 620 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
 621                                 /* Voltage swing  pre-emphasis */
 622         { 0x18, 0x00, 0x00 },   /* 0              0   */
 623         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 624         { 0x24, 0x00, 0x0C },   /* 0              2   */
 625         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 626         { 0x21, 0x00, 0x00 },   /* 1              0   */
 627         { 0x2B, 0x00, 0x08 },   /* 1              1   */
 628         { 0x30, 0x00, 0x0F },   /* 1              2   */
 629         { 0x31, 0x00, 0x03 },   /* 2              0   */
 630         { 0x34, 0x00, 0x0B },   /* 2              1   */
 631         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 632 };
 633
 634 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
 635                                 /* Voltage swing  pre-emphasis */
 636         { 0x18, 0x00, 0x00 },   /* 0              0   */
 637         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 638         { 0x24, 0x00, 0x0C },   /* 0              2   */
 639         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 640         { 0x26, 0x00, 0x00 },   /* 1              0   */
 641         { 0x2C, 0x00, 0x07 },   /* 1              1   */
 642         { 0x33, 0x00, 0x0C },   /* 1              2   */
 643         { 0x2E, 0x00, 0x00 },   /* 2              0   */
 644         { 0x36, 0x00, 0x09 },   /* 2              1   */
 645         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 646 };
 647
 648 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
 649                                 /* HDMI Preset  VS      Pre-emph */
 650         { 0x1A, 0x0, 0x0 },     /* 1            400mV   0dB */
 651         { 0x20, 0x0, 0x0 },     /* 2            500mV   0dB */
 652         { 0x29, 0x0, 0x0 },     /* 3            650mV   0dB */
 653         { 0x32, 0x0, 0x0 },     /* 4            800mV   0dB */
 654         { 0x3F, 0x0, 0x0 },     /* 5            1000mV  0dB */
 655         { 0x3A, 0x0, 0x5 },     /* 6            Full    -1.5 dB */
 656         { 0x39, 0x0, 0x6 },     /* 7            Full    -1.8 dB */
 657         { 0x38, 0x0, 0x7 },     /* 8            Full    -2 dB */
 658         { 0x37, 0x0, 0x8 },     /* 9            Full    -2.5 dB */
 659         { 0x36, 0x0, 0x9 },     /* 10           Full    -3 dB */
 660 };
 661
 662 struct tgl_dkl_phy_ddi_buf_trans {
 663         u32 dkl_vswing_control;
 664         u32 dkl_preshoot_control;
 665         u32 dkl_de_emphasis_control;
 666 };
 667
 668 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
 669                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 670         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 671         { 0x5, 0x0, 0x05 },     /* 0    1       400mV           3.5 dB */
 672         { 0x2, 0x0, 0x0B },     /* 0    2       400mV           6 dB */
 673         { 0x0, 0x0, 0x18 },     /* 0    3       400mV           9.5 dB */
 674         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 675         { 0x2, 0x0, 0x08 },     /* 1    1       600mV           3.5 dB */
 676         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 677         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 678         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 679         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 680 };
 681
 682 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = {
 683                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 684         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 685         { 0x5, 0x0, 0x05 },     /* 0    1       400mV           3.5 dB */
 686         { 0x2, 0x0, 0x0B },     /* 0    2       400mV           6 dB */
 687         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 688         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 689         { 0x2, 0x0, 0x08 },     /* 1    1       600mV           3.5 dB */
 690         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 691         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 692         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 693         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 694 };
 695
 696 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
 697                                 /* HDMI Preset  VS      Pre-emph */
 698         { 0x7, 0x0, 0x0 },      /* 1            400mV   0dB */
 699         { 0x6, 0x0, 0x0 },      /* 2            500mV   0dB */
 700         { 0x4, 0x0, 0x0 },      /* 3            650mV   0dB */
 701         { 0x2, 0x0, 0x0 },      /* 4            800mV   0dB */
 702         { 0x0, 0x0, 0x0 },      /* 5            1000mV  0dB */
 703         { 0x0, 0x0, 0x5 },      /* 6            Full    -1.5 dB */
 704         { 0x0, 0x0, 0x6 },      /* 7            Full    -1.8 dB */
 705         { 0x0, 0x0, 0x7 },      /* 8            Full    -2 dB */
 706         { 0x0, 0x0, 0x8 },      /* 9            Full    -2.5 dB */
 707         { 0x0, 0x0, 0xA },      /* 10           Full    -3 dB */
 708 };
 709
 710 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
 711                                                 /* NT mV Trans mV db    */
 712         { 0xA, 0x32, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 713         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 714         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 715         { 0x6, 0x7D, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 716         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 717         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 718         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 719         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 720         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 721         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 722 };
 723
 724 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
 725                                                 /* NT mV Trans mV db    */
 726         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 727         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 728         { 0xC, 0x63, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 729         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 730         { 0xA, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 731         { 0xC, 0x63, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 732         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 733         { 0xC, 0x61, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 734         { 0x6, 0x7B, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 735         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 736 };
 737
 738 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
 739                                                 /* NT mV Trans mV db    */
 740         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 741         { 0xA, 0x4F, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 742         { 0xC, 0x60, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 743         { 0xC, 0x7F, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 744         { 0xC, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 745         { 0xC, 0x6F, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 746         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 500   900      5.1   */
 747         { 0x6, 0x60, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 748         { 0x6, 0x7F, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 749         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 750 };
 751
 752 /*
 753  * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
 754  * that DisplayPort specification requires
 755  */
 756 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
 757                                                 /* VS   pre-emp */
 758         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    0       */
 759         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    1       */
 760         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    2       */
 761         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    3       */
 762         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    0       */
 763         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    1       */
 764         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    2       */
 765         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 2    0       */
 766         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 2    1       */
 767 };
 768
 769 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[] = {
 770                                                 /* NT mV Trans mV db    */
 771         { 0xA, 0x2F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 772         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 773         { 0xC, 0x63, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 774         { 0x6, 0x7D, 0x2A, 0x00, 0x15 },        /* 350   900      8.2   */
 775         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 776         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 777         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 778         { 0xC, 0x6E, 0x3E, 0x00, 0x01 },        /* 650   700      0.6   */
 779         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 780         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 781 };
 782
 783 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
 784                                                 /* NT mV Trans mV db    */
 785         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 786         { 0xA, 0x50, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 787         { 0xC, 0x61, 0x33, 0x00, 0x0C },        /* 350   700      6.0   */
 788         { 0x6, 0x7F, 0x2E, 0x00, 0x11 },        /* 350   900      8.2   */
 789         { 0xA, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 790         { 0xC, 0x5F, 0x38, 0x00, 0x07 },        /* 500   700      2.9   */
 791         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 792         { 0xC, 0x5F, 0x3F, 0x00, 0x00 },        /* 650   700      0.6   */
 793         { 0x6, 0x7E, 0x36, 0x00, 0x09 },        /* 600   900      3.5   */
 794         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 795 };
 796
 797 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
 798 {
 799         return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
 800 }
 801
 802 static const struct ddi_buf_trans *
 803 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 804 {
 805         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 806
 807         if (dev_priv->vbt.edp.low_vswing) {
 808                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 809                 return bdw_ddi_translations_edp;
 810         } else {
 811                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 812                 return bdw_ddi_translations_dp;
 813         }
 814 }
 815
 816 static const struct ddi_buf_trans *
 817 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 818 {
 819         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 820
 821         if (IS_SKL_ULX(dev_priv)) {
 822                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 823                 return skl_y_ddi_translations_dp;
 824         } else if (IS_SKL_ULT(dev_priv)) {
 825                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 826                 return skl_u_ddi_translations_dp;
 827         } else {
 828                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 829                 return skl_ddi_translations_dp;
 830         }
 831 }
 832
 833 static const struct ddi_buf_trans *
 834 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 835 {
 836         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 837
 838         if (IS_KBL_ULX(dev_priv) ||
 839             IS_CFL_ULX(dev_priv) ||
 840             IS_CML_ULX(dev_priv)) {
 841                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 842                 return kbl_y_ddi_translations_dp;
 843         } else if (IS_KBL_ULT(dev_priv) ||
 844                    IS_CFL_ULT(dev_priv) ||
 845                    IS_CML_ULT(dev_priv)) {
 846                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 847                 return kbl_u_ddi_translations_dp;
 848         } else {
 849                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 850                 return kbl_ddi_translations_dp;
 851         }
 852 }
 853
 854 static const struct ddi_buf_trans *
 855 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 856 {
 857         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 858
 859         if (dev_priv->vbt.edp.low_vswing) {
 860                 if (IS_SKL_ULX(dev_priv) ||
 861                     IS_KBL_ULX(dev_priv) ||
 862                     IS_CFL_ULX(dev_priv) ||
 863                     IS_CML_ULX(dev_priv)) {
 864                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 865                         return skl_y_ddi_translations_edp;
 866                 } else if (IS_SKL_ULT(dev_priv) ||
 867                            IS_KBL_ULT(dev_priv) ||
 868                            IS_CFL_ULT(dev_priv) ||
 869                            IS_CML_ULT(dev_priv)) {
 870                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 871                         return skl_u_ddi_translations_edp;
 872                 } else {
 873                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 874                         return skl_ddi_translations_edp;
 875                 }
 876         }
 877
 878         if (IS_KABYLAKE(dev_priv) ||
 879             IS_COFFEELAKE(dev_priv) ||
 880             IS_COMETLAKE(dev_priv))
 881                 return kbl_get_buf_trans_dp(encoder, n_entries);
 882         else
 883                 return skl_get_buf_trans_dp(encoder, n_entries);
 884 }
 885
 886 static const struct ddi_buf_trans *
 887 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 888 {
 889         if (IS_SKL_ULX(dev_priv) ||
 890             IS_KBL_ULX(dev_priv) ||
 891             IS_CFL_ULX(dev_priv) ||
 892             IS_CML_ULX(dev_priv)) {
 893                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 894                 return skl_y_ddi_translations_hdmi;
 895         } else {
 896                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 897                 return skl_ddi_translations_hdmi;
 898         }
 899 }
 900
 901 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 902 {
 903         /* Only DDIA and DDIE can select the 10th register with DP */
 904         if (port == PORT_A || port == PORT_E)
 905                 return min(n_entries, 10);
 906         else
 907                 return min(n_entries, 9);
 908 }
 909
 910 static const struct ddi_buf_trans *
 911 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 912 {
 913         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 914
 915         if (IS_KABYLAKE(dev_priv) ||
 916             IS_COFFEELAKE(dev_priv) ||
 917             IS_COMETLAKE(dev_priv)) {
 918                 const struct ddi_buf_trans *ddi_translations =
 919                         kbl_get_buf_trans_dp(encoder, n_entries);
 920                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 921                 return ddi_translations;
 922         } else if (IS_SKYLAKE(dev_priv)) {
 923                 const struct ddi_buf_trans *ddi_translations =
 924                         skl_get_buf_trans_dp(encoder, n_entries);
 925                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 926                 return ddi_translations;
 927         } else if (IS_BROADWELL(dev_priv)) {
 928                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 929                 return  bdw_ddi_translations_dp;
 930         } else if (IS_HASWELL(dev_priv)) {
 931                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 932                 return hsw_ddi_translations_dp;
 933         }
 934
 935         *n_entries = 0;
 936         return NULL;
 937 }
 938
 939 static const struct ddi_buf_trans *
 940 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 943
 944         if (IS_GEN9_BC(dev_priv)) {
 945                 const struct ddi_buf_trans *ddi_translations =
 946                         skl_get_buf_trans_edp(encoder, n_entries);
 947                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 948                 return ddi_translations;
 949         } else if (IS_BROADWELL(dev_priv)) {
 950                 return bdw_get_buf_trans_edp(encoder, n_entries);
 951         } else if (IS_HASWELL(dev_priv)) {
 952                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 953                 return hsw_ddi_translations_dp;
 954         }
 955
 956         *n_entries = 0;
 957         return NULL;
 958 }
 959
 960 static const struct ddi_buf_trans *
 961 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 962                             int *n_entries)
 963 {
 964         if (IS_BROADWELL(dev_priv)) {
 965                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 966                 return bdw_ddi_translations_fdi;
 967         } else if (IS_HASWELL(dev_priv)) {
 968                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 969                 return hsw_ddi_translations_fdi;
 970         }
 971
 972         *n_entries = 0;
 973         return NULL;
 974 }
 975
 976 static const struct ddi_buf_trans *
 977 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
 978                              int *n_entries)
 979 {
 980         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 981
 982         if (IS_GEN9_BC(dev_priv)) {
 983                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 984         } else if (IS_BROADWELL(dev_priv)) {
 985                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 986                 return bdw_ddi_translations_hdmi;
 987         } else if (IS_HASWELL(dev_priv)) {
 988                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 989                 return hsw_ddi_translations_hdmi;
 990         }
 991
 992         *n_entries = 0;
 993         return NULL;
 994 }
 995
 996 static const struct bxt_ddi_buf_trans *
 997 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 998 {
 999         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1000         return bxt_ddi_translations_dp;
1001 }
1002
1003 static const struct bxt_ddi_buf_trans *
1004 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
1005 {
1006         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1007
1008         if (dev_priv->vbt.edp.low_vswing) {
1009                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1010                 return bxt_ddi_translations_edp;
1011         }
1012
1013         return bxt_get_buf_trans_dp(encoder, n_entries);
1014 }
1015
1016 static const struct bxt_ddi_buf_trans *
1017 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
1018 {
1019         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1020         return bxt_ddi_translations_hdmi;
1021 }
1022
1023 static const struct cnl_ddi_buf_trans *
1024 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
1025 {
1026         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1027         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1028
1029         if (voltage == VOLTAGE_INFO_0_85V) {
1030                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1031                 return cnl_ddi_translations_hdmi_0_85V;
1032         } else if (voltage == VOLTAGE_INFO_0_95V) {
1033                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1034                 return cnl_ddi_translations_hdmi_0_95V;
1035         } else if (voltage == VOLTAGE_INFO_1_05V) {
1036                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1037                 return cnl_ddi_translations_hdmi_1_05V;
1038         } else {
1039                 *n_entries = 1; /* shut up gcc */
1040                 MISSING_CASE(voltage);
1041         }
1042         return NULL;
1043 }
1044
1045 static const struct cnl_ddi_buf_trans *
1046 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
1047 {
1048         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1049         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1050
1051         if (voltage == VOLTAGE_INFO_0_85V) {
1052                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1053                 return cnl_ddi_translations_dp_0_85V;
1054         } else if (voltage == VOLTAGE_INFO_0_95V) {
1055                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1056                 return cnl_ddi_translations_dp_0_95V;
1057         } else if (voltage == VOLTAGE_INFO_1_05V) {
1058                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1059                 return cnl_ddi_translations_dp_1_05V;
1060         } else {
1061                 *n_entries = 1; /* shut up gcc */
1062                 MISSING_CASE(voltage);
1063         }
1064         return NULL;
1065 }
1066
1067 static const struct cnl_ddi_buf_trans *
1068 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
1069 {
1070         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1071         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1072
1073         if (dev_priv->vbt.edp.low_vswing) {
1074                 if (voltage == VOLTAGE_INFO_0_85V) {
1075                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1076                         return cnl_ddi_translations_edp_0_85V;
1077                 } else if (voltage == VOLTAGE_INFO_0_95V) {
1078                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1079                         return cnl_ddi_translations_edp_0_95V;
1080                 } else if (voltage == VOLTAGE_INFO_1_05V) {
1081                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1082                         return cnl_ddi_translations_edp_1_05V;
1083                 } else {
1084                         *n_entries = 1; /* shut up gcc */
1085                         MISSING_CASE(voltage);
1086                 }
1087                 return NULL;
1088         } else {
1089                 return cnl_get_buf_trans_dp(encoder, n_entries);
1090         }
1091 }
1092
1093 static const struct cnl_ddi_buf_trans *
1094 icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1095                              const struct intel_crtc_state *crtc_state,
1096                              int *n_entries)
1097 {
1098         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1099         return icl_combo_phy_ddi_translations_hdmi;
1100 }
1101
1102 static const struct cnl_ddi_buf_trans *
1103 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1104                            const struct intel_crtc_state *crtc_state,
1105                            int *n_entries)
1106 {
1107         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1108         return icl_combo_phy_ddi_translations_dp_hbr2;
1109 }
1110
1111 static const struct cnl_ddi_buf_trans *
1112 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1113                             const struct intel_crtc_state *crtc_state,
1114                             int *n_entries)
1115 {
1116         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1117
1118         if (crtc_state->port_clock > 540000) {
1119                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1120                 return icl_combo_phy_ddi_translations_edp_hbr3;
1121         } else if (dev_priv->vbt.edp.low_vswing) {
1122                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1123                 return icl_combo_phy_ddi_translations_edp_hbr2;
1124         }
1125
1126         return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1127 }
1128
1129 static const struct cnl_ddi_buf_trans *
1130 icl_get_combo_buf_trans(struct intel_encoder *encoder,
1131                         const struct intel_crtc_state *crtc_state,
1132                         int *n_entries)
1133 {
1134         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1135                 return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1136         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1137                 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1138         else
1139                 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1140 }
1141
1142 static const struct icl_mg_phy_ddi_buf_trans *
1143 icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
1144                           const struct intel_crtc_state *crtc_state,
1145                           int *n_entries)
1146 {
1147         *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
1148         return icl_mg_phy_ddi_translations_hdmi;
1149 }
1150
1151 static const struct icl_mg_phy_ddi_buf_trans *
1152 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1153                         const struct intel_crtc_state *crtc_state,
1154                         int *n_entries)
1155 {
1156         if (crtc_state->port_clock > 270000) {
1157                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
1158                 return icl_mg_phy_ddi_translations_hbr2_hbr3;
1159         } else {
1160                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
1161                 return icl_mg_phy_ddi_translations_rbr_hbr;
1162         }
1163 }
1164
1165 static const struct icl_mg_phy_ddi_buf_trans *
1166 icl_get_mg_buf_trans(struct intel_encoder *encoder,
1167                      const struct intel_crtc_state *crtc_state,
1168                      int *n_entries)
1169 {
1170         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1171                 return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
1172         else
1173                 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1174 }
1175
1176 static const struct cnl_ddi_buf_trans *
1177 ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1178                              const struct intel_crtc_state *crtc_state,
1179                              int *n_entries)
1180 {
1181         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1182         return icl_combo_phy_ddi_translations_hdmi;
1183 }
1184
1185 static const struct cnl_ddi_buf_trans *
1186 ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1187                            const struct intel_crtc_state *crtc_state,
1188                            int *n_entries)
1189 {
1190         *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
1191         return ehl_combo_phy_ddi_translations_dp;
1192 }
1193
1194 static const struct cnl_ddi_buf_trans *
1195 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1196                             const struct intel_crtc_state *crtc_state,
1197                             int *n_entries)
1198 {
1199         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1200
1201         if (dev_priv->vbt.edp.low_vswing) {
1202                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1203                 return icl_combo_phy_ddi_translations_edp_hbr2;
1204         }
1205
1206         return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1207 }
1208
1209 static const struct cnl_ddi_buf_trans *
1210 ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1211                         const struct intel_crtc_state *crtc_state,
1212                         int *n_entries)
1213 {
1214         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1215                 return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1216         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1217                 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1218         else
1219                 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1220 }
1221
1222 static const struct cnl_ddi_buf_trans *
1223 jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1224                              const struct intel_crtc_state *crtc_state,
1225                              int *n_entries)
1226 {
1227         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1228         return icl_combo_phy_ddi_translations_hdmi;
1229 }
1230
1231 static const struct cnl_ddi_buf_trans *
1232 jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1233                            const struct intel_crtc_state *crtc_state,
1234                            int *n_entries)
1235 {
1236         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1237         return icl_combo_phy_ddi_translations_dp_hbr2;
1238 }
1239
1240 static const struct cnl_ddi_buf_trans *
1241 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1242                             const struct intel_crtc_state *crtc_state,
1243                             int *n_entries)
1244 {
1245         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1246
1247         if (dev_priv->vbt.edp.low_vswing) {
1248                 if (crtc_state->port_clock > 270000) {
1249                         *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
1250                         return jsl_combo_phy_ddi_translations_edp_hbr2;
1251                 } else {
1252                         *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
1253                         return jsl_combo_phy_ddi_translations_edp_hbr;
1254                 }
1255         }
1256
1257         return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1258 }
1259
1260 static const struct cnl_ddi_buf_trans *
1261 jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1262                         const struct intel_crtc_state *crtc_state,
1263                         int *n_entries)
1264 {
1265         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1266                 return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1267         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1268                 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1269         else
1270                 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1271 }
1272
1273 static const struct cnl_ddi_buf_trans *
1274 tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1275                              const struct intel_crtc_state *crtc_state,
1276                              int *n_entries)
1277 {
1278         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1279         return icl_combo_phy_ddi_translations_hdmi;
1280 }
1281
1282 static const struct cnl_ddi_buf_trans *
1283 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1284                            const struct intel_crtc_state *crtc_state,
1285                            int *n_entries)
1286 {
1287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1288
1289         if (crtc_state->port_clock > 270000) {
1290                 if (IS_ROCKETLAKE(dev_priv)) {
1291                         *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3);
1292                         return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3;
1293                 } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1294                         *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
1295                         return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
1296                 } else {
1297                         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1298                         return tgl_combo_phy_ddi_translations_dp_hbr2;
1299                 }
1300         } else {
1301                 if (IS_ROCKETLAKE(dev_priv)) {
1302                         *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr);
1303                         return rkl_combo_phy_ddi_translations_dp_hbr;
1304                 } else {
1305                         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1306                         return tgl_combo_phy_ddi_translations_dp_hbr;
1307                 }
1308         }
1309 }
1310
1311 static const struct cnl_ddi_buf_trans *
1312 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1313                             const struct intel_crtc_state *crtc_state,
1314                             int *n_entries)
1315 {
1316         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1317         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1318
1319         if (crtc_state->port_clock > 540000) {
1320                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1321                 return icl_combo_phy_ddi_translations_edp_hbr3;
1322         } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
1323                 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
1324                 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
1325         } else if (dev_priv->vbt.edp.low_vswing) {
1326                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1327                 return icl_combo_phy_ddi_translations_edp_hbr2;
1328         }
1329
1330         return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1331 }
1332
1333 static const struct cnl_ddi_buf_trans *
1334 tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1335                         const struct intel_crtc_state *crtc_state,
1336                         int *n_entries)
1337 {
1338         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1339                 return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1340         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1341                 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1342         else
1343                 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1344 }
1345
1346 static const struct tgl_dkl_phy_ddi_buf_trans *
1347 tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
1348                            const struct intel_crtc_state *crtc_state,
1349                            int *n_entries)
1350 {
1351         *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1352         return tgl_dkl_phy_hdmi_ddi_trans;
1353 }
1354
1355 static const struct tgl_dkl_phy_ddi_buf_trans *
1356 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1357                          const struct intel_crtc_state *crtc_state,
1358                          int *n_entries)
1359 {
1360         if (crtc_state->port_clock > 270000) {
1361                 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
1362                 return tgl_dkl_phy_dp_ddi_trans_hbr2;
1363         } else {
1364                 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
1365                 return tgl_dkl_phy_dp_ddi_trans;
1366         }
1367 }
1368
1369 static const struct tgl_dkl_phy_ddi_buf_trans *
1370 tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1371                       const struct intel_crtc_state *crtc_state,
1372                       int *n_entries)
1373 {
1374         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1375                 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
1376         else
1377                 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1378 }
1379
1380 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
1381                                 const struct intel_crtc_state *crtc_state)
1382 {
1383         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1384         int n_entries, level, default_entry;
1385         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1386
1387         if (INTEL_GEN(dev_priv) >= 12) {
1388                 if (intel_phy_is_combo(dev_priv, phy))
1389                         tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1390                 else
1391                         tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1392                 default_entry = n_entries - 1;
1393         } else if (INTEL_GEN(dev_priv) == 11) {
1394                 if (intel_phy_is_combo(dev_priv, phy))
1395                         icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1396                 else
1397                         icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1398                 default_entry = n_entries - 1;
1399         } else if (IS_CANNONLAKE(dev_priv)) {
1400                 cnl_get_buf_trans_hdmi(encoder, &n_entries);
1401                 default_entry = n_entries - 1;
1402         } else if (IS_GEN9_LP(dev_priv)) {
1403                 bxt_get_buf_trans_hdmi(encoder, &n_entries);
1404                 default_entry = n_entries - 1;
1405         } else if (IS_GEN9_BC(dev_priv)) {
1406                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1407                 default_entry = 8;
1408         } else if (IS_BROADWELL(dev_priv)) {
1409                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1410                 default_entry = 7;
1411         } else if (IS_HASWELL(dev_priv)) {
1412                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1413                 default_entry = 6;
1414         } else {
1415                 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1416                 return 0;
1417         }
1418
1419         if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1420                 return 0;
1421
1422         level = intel_bios_hdmi_level_shift(encoder);
1423         if (level < 0)
1424                 level = default_entry;
1425
1426         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1427                 level = n_entries - 1;
1428
1429         return level;
1430 }
1431
1432 /*
1433  * Starting with Haswell, DDI port buffers must be programmed with correct
1434  * values in advance. This function programs the correct values for
1435  * DP/eDP/FDI use cases.
1436  */
1437 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1438                                          const struct intel_crtc_state *crtc_state)
1439 {
1440         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1441         u32 iboost_bit = 0;
1442         int i, n_entries;
1443         enum port port = encoder->port;
1444         const struct ddi_buf_trans *ddi_translations;
1445
1446         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1447                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1448                                                                &n_entries);
1449         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1450                 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
1451                                                                &n_entries);
1452         else
1453                 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
1454                                                               &n_entries);
1455
1456         /* If we're boosting the current, set bit 31 of trans1 */
1457         if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1458                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1459
1460         for (i = 0; i < n_entries; i++) {
1461                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1462                                ddi_translations[i].trans1 | iboost_bit);
1463                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1464                                ddi_translations[i].trans2);
1465         }
1466 }
1467
1468 /*
1469  * Starting with Haswell, DDI port buffers must be programmed with correct
1470  * values in advance. This function programs the correct values for
1471  * HDMI/DVI use cases.
1472  */
1473 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1474                                            int level)
1475 {
1476         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1477         u32 iboost_bit = 0;
1478         int n_entries;
1479         enum port port = encoder->port;
1480         const struct ddi_buf_trans *ddi_translations;
1481
1482         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1483
1484         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1485                 return;
1486         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1487                 level = n_entries - 1;
1488
1489         /* If we're boosting the current, set bit 31 of trans1 */
1490         if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1491                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1492
1493         /* Entry 9 is for HDMI: */
1494         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1495                        ddi_translations[level].trans1 | iboost_bit);
1496         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1497                        ddi_translations[level].trans2);
1498 }
1499
1500 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1501                                     enum port port)
1502 {
1503         if (IS_BROXTON(dev_priv)) {
1504                 udelay(16);
1505                 return;
1506         }
1507
1508         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1509                          DDI_BUF_IS_IDLE), 8))
1510                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
1511                         port_name(port));
1512 }
1513
1514 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
1515                                       enum port port)
1516 {
1517         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
1518         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
1519                 usleep_range(518, 1000);
1520                 return;
1521         }
1522
1523         if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1524                           DDI_BUF_IS_IDLE), 500))
1525                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
1526                         port_name(port));
1527 }
1528
1529 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1530 {
1531         switch (pll->info->id) {
1532         case DPLL_ID_WRPLL1:
1533                 return PORT_CLK_SEL_WRPLL1;
1534         case DPLL_ID_WRPLL2:
1535                 return PORT_CLK_SEL_WRPLL2;
1536         case DPLL_ID_SPLL:
1537                 return PORT_CLK_SEL_SPLL;
1538         case DPLL_ID_LCPLL_810:
1539                 return PORT_CLK_SEL_LCPLL_810;
1540         case DPLL_ID_LCPLL_1350:
1541                 return PORT_CLK_SEL_LCPLL_1350;
1542         case DPLL_ID_LCPLL_2700:
1543                 return PORT_CLK_SEL_LCPLL_2700;
1544         default:
1545                 MISSING_CASE(pll->info->id);
1546                 return PORT_CLK_SEL_NONE;
1547         }
1548 }
1549
1550 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1551                                   const struct intel_crtc_state *crtc_state)
1552 {
1553         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1554         int clock = crtc_state->port_clock;
1555         const enum intel_dpll_id id = pll->info->id;
1556
1557         switch (id) {
1558         default:
1559                 /*
1560                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1561                  * here, so do warn if this get passed in
1562                  */
1563                 MISSING_CASE(id);
1564                 return DDI_CLK_SEL_NONE;
1565         case DPLL_ID_ICL_TBTPLL:
1566                 switch (clock) {
1567                 case 162000:
1568                         return DDI_CLK_SEL_TBT_162;
1569                 case 270000:
1570                         return DDI_CLK_SEL_TBT_270;
1571                 case 540000:
1572                         return DDI_CLK_SEL_TBT_540;
1573                 case 810000:
1574                         return DDI_CLK_SEL_TBT_810;
1575                 default:
1576                         MISSING_CASE(clock);
1577                         return DDI_CLK_SEL_NONE;
1578                 }
1579         case DPLL_ID_ICL_MGPLL1:
1580         case DPLL_ID_ICL_MGPLL2:
1581         case DPLL_ID_ICL_MGPLL3:
1582         case DPLL_ID_ICL_MGPLL4:
1583         case DPLL_ID_TGL_MGPLL5:
1584         case DPLL_ID_TGL_MGPLL6:
1585                 return DDI_CLK_SEL_MG;
1586         }
1587 }
1588
1589 /* Starting with Haswell, different DDI ports can work in FDI mode for
1590  * connection to the PCH-located connectors. For this, it is necessary to train
1591  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1592  *
1593  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1594  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1595  * DDI A (which is used for eDP)
1596  */
1597
1598 void hsw_fdi_link_train(struct intel_encoder *encoder,
1599                         const struct intel_crtc_state *crtc_state)
1600 {
1601         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1602         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1603         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1604
1605         intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1606
1607         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1608          * mode set "sequence for CRT port" document:
1609          * - TP1 to TP2 time with the default value
1610          * - FDI delay to 90h
1611          *
1612          * WaFDIAutoLinkSetTimingOverrride:hsw
1613          */
1614         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1615                        FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1616
1617         /* Enable the PCH Receiver FDI PLL */
1618         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1619                      FDI_RX_PLL_ENABLE |
1620                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1621         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1622         intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1623         udelay(220);
1624
1625         /* Switch from Rawclk to PCDclk */
1626         rx_ctl_val |= FDI_PCDCLK;
1627         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1628
1629         /* Configure Port Clock Select */
1630         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1631         intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1632         drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1633
1634         /* Start the training iterating through available voltages and emphasis,
1635          * testing each value twice. */
1636         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1637                 /* Configure DP_TP_CTL with auto-training */
1638                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1639                                DP_TP_CTL_FDI_AUTOTRAIN |
1640                                DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1641                                DP_TP_CTL_LINK_TRAIN_PAT1 |
1642                                DP_TP_CTL_ENABLE);
1643
1644                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1645                  * DDI E does not support port reversal, the functionality is
1646                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1647                  * port reversal bit */
1648                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1649                                DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1650                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1651
1652                 udelay(600);
1653
1654                 /* Program PCH FDI Receiver TU */
1655                 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1656
1657                 /* Enable PCH FDI Receiver with auto-training */
1658                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1659                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1660                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1661
1662                 /* Wait for FDI receiver lane calibration */
1663                 udelay(30);
1664
1665                 /* Unset FDI_RX_MISC pwrdn lanes */
1666                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1667                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1668                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1669                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1670
1671                 /* Wait for FDI auto training time */
1672                 udelay(5);
1673
1674                 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1675                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1676                         drm_dbg_kms(&dev_priv->drm,
1677                                     "FDI link training done on step %d\n", i);
1678                         break;
1679                 }
1680
1681                 /*
1682                  * Leave things enabled even if we failed to train FDI.
1683                  * Results in less fireworks from the state checker.
1684                  */
1685                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1686                         drm_err(&dev_priv->drm, "FDI link training failed!\n");
1687                         break;
1688                 }
1689
1690                 rx_ctl_val &= ~FDI_RX_ENABLE;
1691                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1692                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1693
1694                 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1695                 temp &= ~DDI_BUF_CTL_ENABLE;
1696                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1697                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1698
1699                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1700                 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1701                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1702                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1703                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1704                 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1705
1706                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1707
1708                 /* Reset FDI_RX_MISC pwrdn lanes */
1709                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1710                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1711                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1712                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1713                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1714         }
1715
1716         /* Enable normal pixel sending for FDI */
1717         intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1718                        DP_TP_CTL_FDI_AUTOTRAIN |
1719                        DP_TP_CTL_LINK_TRAIN_NORMAL |
1720                        DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1721                        DP_TP_CTL_ENABLE);
1722 }
1723
1724 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
1725                                       const struct intel_crtc_state *crtc_state)
1726 {
1727         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1728         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1729
1730         intel_dp->DP = dig_port->saved_port_bits |
1731                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1732         intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
1733 }
1734
1735 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1736                                  enum port port)
1737 {
1738         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1739
1740         switch (val) {
1741         case DDI_CLK_SEL_NONE:
1742                 return 0;
1743         case DDI_CLK_SEL_TBT_162:
1744                 return 162000;
1745         case DDI_CLK_SEL_TBT_270:
1746                 return 270000;
1747         case DDI_CLK_SEL_TBT_540:
1748                 return 540000;
1749         case DDI_CLK_SEL_TBT_810:
1750                 return 810000;
1751         default:
1752                 MISSING_CASE(val);
1753                 return 0;
1754         }
1755 }
1756
1757 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1758 {
1759         int dotclock;
1760
1761         if (pipe_config->has_pch_encoder)
1762                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1763                                                     &pipe_config->fdi_m_n);
1764         else if (intel_crtc_has_dp_encoder(pipe_config))
1765                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1766                                                     &pipe_config->dp_m_n);
1767         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1768                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1769         else
1770                 dotclock = pipe_config->port_clock;
1771
1772         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1773             !intel_crtc_has_dp_encoder(pipe_config))
1774                 dotclock *= 2;
1775
1776         if (pipe_config->pixel_multiplier)
1777                 dotclock /= pipe_config->pixel_multiplier;
1778
1779         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1780 }
1781
1782 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1783                                 struct intel_crtc_state *pipe_config)
1784 {
1785         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1786         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1787
1788         if (intel_phy_is_tc(dev_priv, phy) &&
1789             intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1790             DPLL_ID_ICL_TBTPLL)
1791                 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1792                                                                 encoder->port);
1793         else
1794                 pipe_config->port_clock =
1795                         intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll,
1796                                             &pipe_config->dpll_hw_state);
1797
1798         ddi_dotclock_get(pipe_config);
1799 }
1800
1801 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1802                           const struct drm_connector_state *conn_state)
1803 {
1804         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1805         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1806         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1807         u32 temp;
1808
1809         if (!intel_crtc_has_dp_encoder(crtc_state))
1810                 return;
1811
1812         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1813
1814         temp = DP_MSA_MISC_SYNC_CLOCK;
1815
1816         switch (crtc_state->pipe_bpp) {
1817         case 18:
1818                 temp |= DP_MSA_MISC_6_BPC;
1819                 break;
1820         case 24:
1821                 temp |= DP_MSA_MISC_8_BPC;
1822                 break;
1823         case 30:
1824                 temp |= DP_MSA_MISC_10_BPC;
1825                 break;
1826         case 36:
1827                 temp |= DP_MSA_MISC_12_BPC;
1828                 break;
1829         default:
1830                 MISSING_CASE(crtc_state->pipe_bpp);
1831                 break;
1832         }
1833
1834         /* nonsense combination */
1835         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1836                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1837
1838         if (crtc_state->limited_color_range)
1839                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1840
1841         /*
1842          * As per DP 1.2 spec section 2.3.4.3 while sending
1843          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1844          * colorspace information.
1845          */
1846         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1847                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1848
1849         /*
1850          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1851          * of Color Encoding Format and Content Color Gamut] while sending
1852          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1853          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1854          */
1855         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1856                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1857
1858         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1859 }
1860
1861 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1862 {
1863         if (master_transcoder == TRANSCODER_EDP)
1864                 return 0;
1865         else
1866                 return master_transcoder + 1;
1867 }
1868
1869 /*
1870  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1871  *
1872  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1873  * intel_ddi_config_transcoder_func().
1874  */
1875 static u32
1876 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
1877                                       const struct intel_crtc_state *crtc_state)
1878 {
1879         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1880         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1881         enum pipe pipe = crtc->pipe;
1882         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1883         enum port port = encoder->port;
1884         u32 temp;
1885
1886         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1887         temp = TRANS_DDI_FUNC_ENABLE;
1888         if (INTEL_GEN(dev_priv) >= 12)
1889                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1890         else
1891                 temp |= TRANS_DDI_SELECT_PORT(port);
1892
1893         switch (crtc_state->pipe_bpp) {
1894         case 18:
1895                 temp |= TRANS_DDI_BPC_6;
1896                 break;
1897         case 24:
1898                 temp |= TRANS_DDI_BPC_8;
1899                 break;
1900         case 30:
1901                 temp |= TRANS_DDI_BPC_10;
1902                 break;
1903         case 36:
1904                 temp |= TRANS_DDI_BPC_12;
1905                 break;
1906         default:
1907                 BUG();
1908         }
1909
1910         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1911                 temp |= TRANS_DDI_PVSYNC;
1912         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1913                 temp |= TRANS_DDI_PHSYNC;
1914
1915         if (cpu_transcoder == TRANSCODER_EDP) {
1916                 switch (pipe) {
1917                 case PIPE_A:
1918                         /* On Haswell, can only use the always-on power well for
1919                          * eDP when not using the panel fitter, and when not
1920                          * using motion blur mitigation (which we don't
1921                          * support). */
1922                         if (crtc_state->pch_pfit.force_thru)
1923                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1924                         else
1925                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1926                         break;
1927                 case PIPE_B:
1928                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1929                         break;
1930                 case PIPE_C:
1931                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1932                         break;
1933                 default:
1934                         BUG();
1935                         break;
1936                 }
1937         }
1938
1939         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1940                 if (crtc_state->has_hdmi_sink)
1941                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1942                 else
1943                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1944
1945                 if (crtc_state->hdmi_scrambling)
1946                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1947                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1948                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1949         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1950                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1951                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1952         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1953                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1954                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1955
1956                 if (INTEL_GEN(dev_priv) >= 12) {
1957                         enum transcoder master;
1958
1959                         master = crtc_state->mst_master_transcoder;
1960                         drm_WARN_ON(&dev_priv->drm,
1961                                     master == INVALID_TRANSCODER);
1962                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1963                 }
1964         } else {
1965                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1966                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1967         }
1968
1969         if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1970             crtc_state->master_transcoder != INVALID_TRANSCODER) {
1971                 u8 master_select =
1972                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1973
1974                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1975                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1976         }
1977
1978         return temp;
1979 }
1980
1981 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
1982                                       const struct intel_crtc_state *crtc_state)
1983 {
1984         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1985         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1986         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1987
1988         if (INTEL_GEN(dev_priv) >= 11) {
1989                 enum transcoder master_transcoder = crtc_state->master_transcoder;
1990                 u32 ctl2 = 0;
1991
1992                 if (master_transcoder != INVALID_TRANSCODER) {
1993                         u8 master_select =
1994                                 bdw_trans_port_sync_master_select(master_transcoder);
1995
1996                         ctl2 |= PORT_SYNC_MODE_ENABLE |
1997                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1998                 }
1999
2000                 intel_de_write(dev_priv,
2001                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
2002         }
2003
2004         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
2005                        intel_ddi_transcoder_func_reg_val_get(encoder,
2006                                                              crtc_state));
2007 }
2008
2009 /*
2010  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
2011  * bit.
2012  */
2013 static void
2014 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
2015                                  const struct intel_crtc_state *crtc_state)
2016 {
2017         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2018         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2019         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2020         u32 ctl;
2021
2022         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
2023         ctl &= ~TRANS_DDI_FUNC_ENABLE;
2024         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
2025 }
2026
2027 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
2028 {
2029         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2030         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2031         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2032         u32 ctl;
2033
2034         if (INTEL_GEN(dev_priv) >= 11)
2035                 intel_de_write(dev_priv,
2036                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
2037
2038         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
2039
2040         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
2041
2042         ctl &= ~TRANS_DDI_FUNC_ENABLE;
2043
2044         if (IS_GEN_RANGE(dev_priv, 8, 10))
2045                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
2046                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
2047
2048         if (INTEL_GEN(dev_priv) >= 12) {
2049                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
2050                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
2051                                  TRANS_DDI_MODE_SELECT_MASK);
2052                 }
2053         } else {
2054                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
2055         }
2056
2057         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
2058
2059         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
2060             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2061                 drm_dbg_kms(&dev_priv->drm,
2062                             "Quirk Increase DDI disabled time\n");
2063                 /* Quirk time at 100ms for reliable operation */
2064                 msleep(100);
2065         }
2066 }
2067
2068 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
2069                                      enum transcoder cpu_transcoder,
2070                                      bool enable)
2071 {
2072         struct drm_device *dev = intel_encoder->base.dev;
2073         struct drm_i915_private *dev_priv = to_i915(dev);
2074         intel_wakeref_t wakeref;
2075         int ret = 0;
2076         u32 tmp;
2077
2078         wakeref = intel_display_power_get_if_enabled(dev_priv,
2079                                                      intel_encoder->power_domain);
2080         if (drm_WARN_ON(dev, !wakeref))
2081                 return -ENXIO;
2082
2083         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
2084         if (enable)
2085                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
2086         else
2087                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
2088         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
2089         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2090         return ret;
2091 }
2092
2093 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
2094 {
2095         struct drm_device *dev = intel_connector->base.dev;
2096         struct drm_i915_private *dev_priv = to_i915(dev);
2097         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
2098         int type = intel_connector->base.connector_type;
2099         enum port port = encoder->port;
2100         enum transcoder cpu_transcoder;
2101         intel_wakeref_t wakeref;
2102         enum pipe pipe = 0;
2103         u32 tmp;
2104         bool ret;
2105
2106         wakeref = intel_display_power_get_if_enabled(dev_priv,
2107                                                      encoder->power_domain);
2108         if (!wakeref)
2109                 return false;
2110
2111         if (!encoder->get_hw_state(encoder, &pipe)) {
2112                 ret = false;
2113                 goto out;
2114         }
2115
2116         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
2117                 cpu_transcoder = TRANSCODER_EDP;
2118         else
2119                 cpu_transcoder = (enum transcoder) pipe;
2120
2121         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
2122
2123         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2124         case TRANS_DDI_MODE_SELECT_HDMI:
2125         case TRANS_DDI_MODE_SELECT_DVI:
2126                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2127                 break;
2128
2129         case TRANS_DDI_MODE_SELECT_DP_SST:
2130                 ret = type == DRM_MODE_CONNECTOR_eDP ||
2131                       type == DRM_MODE_CONNECTOR_DisplayPort;
2132                 break;
2133
2134         case TRANS_DDI_MODE_SELECT_DP_MST:
2135                 /* if the transcoder is in MST state then
2136                  * connector isn't connected */
2137                 ret = false;
2138                 break;
2139
2140         case TRANS_DDI_MODE_SELECT_FDI:
2141                 ret = type == DRM_MODE_CONNECTOR_VGA;
2142                 break;
2143
2144         default:
2145                 ret = false;
2146                 break;
2147         }
2148
2149 out:
2150         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2151
2152         return ret;
2153 }
2154
2155 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2156                                         u8 *pipe_mask, bool *is_dp_mst)
2157 {
2158         struct drm_device *dev = encoder->base.dev;
2159         struct drm_i915_private *dev_priv = to_i915(dev);
2160         enum port port = encoder->port;
2161         intel_wakeref_t wakeref;
2162         enum pipe p;
2163         u32 tmp;
2164         u8 mst_pipe_mask;
2165
2166         *pipe_mask = 0;
2167         *is_dp_mst = false;
2168
2169         wakeref = intel_display_power_get_if_enabled(dev_priv,
2170                                                      encoder->power_domain);
2171         if (!wakeref)
2172                 return;
2173
2174         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2175         if (!(tmp & DDI_BUF_CTL_ENABLE))
2176                 goto out;
2177
2178         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
2179                 tmp = intel_de_read(dev_priv,
2180                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2181
2182                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2183                 default:
2184                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2185                         fallthrough;
2186                 case TRANS_DDI_EDP_INPUT_A_ON:
2187                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2188                         *pipe_mask = BIT(PIPE_A);
2189                         break;
2190                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2191                         *pipe_mask = BIT(PIPE_B);
2192                         break;
2193                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2194                         *pipe_mask = BIT(PIPE_C);
2195                         break;
2196                 }
2197
2198                 goto out;
2199         }
2200
2201         mst_pipe_mask = 0;
2202         for_each_pipe(dev_priv, p) {
2203                 enum transcoder cpu_transcoder = (enum transcoder)p;
2204                 unsigned int port_mask, ddi_select;
2205                 intel_wakeref_t trans_wakeref;
2206
2207                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2208                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2209                 if (!trans_wakeref)
2210                         continue;
2211
2212                 if (INTEL_GEN(dev_priv) >= 12) {
2213                         port_mask = TGL_TRANS_DDI_PORT_MASK;
2214                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2215                 } else {
2216                         port_mask = TRANS_DDI_PORT_MASK;
2217                         ddi_select = TRANS_DDI_SELECT_PORT(port);
2218                 }
2219
2220                 tmp = intel_de_read(dev_priv,
2221                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
2222                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2223                                         trans_wakeref);
2224
2225                 if ((tmp & port_mask) != ddi_select)
2226                         continue;
2227
2228                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2229                     TRANS_DDI_MODE_SELECT_DP_MST)
2230                         mst_pipe_mask |= BIT(p);
2231
2232                 *pipe_mask |= BIT(p);
2233         }
2234
2235         if (!*pipe_mask)
2236                 drm_dbg_kms(&dev_priv->drm,
2237                             "No pipe for [ENCODER:%d:%s] found\n",
2238                             encoder->base.base.id, encoder->base.name);
2239
2240         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2241                 drm_dbg_kms(&dev_priv->drm,
2242                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2243                             encoder->base.base.id, encoder->base.name,
2244                             *pipe_mask);
2245                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2246         }
2247
2248         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2249                 drm_dbg_kms(&dev_priv->drm,
2250                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2251                             encoder->base.base.id, encoder->base.name,
2252                             *pipe_mask, mst_pipe_mask);
2253         else
2254                 *is_dp_mst = mst_pipe_mask;
2255
2256 out:
2257         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2258                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
2259                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2260                             BXT_PHY_LANE_POWERDOWN_ACK |
2261                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2262                         drm_err(&dev_priv->drm,
2263                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
2264                                 encoder->base.base.id, encoder->base.name, tmp);
2265         }
2266
2267         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2268 }
2269
2270 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2271                             enum pipe *pipe)
2272 {
2273         u8 pipe_mask;
2274         bool is_mst;
2275
2276         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2277
2278         if (is_mst || !pipe_mask)
2279                 return false;
2280
2281         *pipe = ffs(pipe_mask) - 1;
2282
2283         return true;
2284 }
2285
2286 static enum intel_display_power_domain
2287 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2288 {
2289         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2290          * DC states enabled at the same time, while for driver initiated AUX
2291          * transfers we need the same AUX IOs to be powered but with DC states
2292          * disabled. Accordingly use the AUX power domain here which leaves DC
2293          * states enabled.
2294          * However, for non-A AUX ports the corresponding non-EDP transcoders
2295          * would have already enabled power well 2 and DC_OFF. This means we can
2296          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2297          * specific AUX_IO reference without powering up any extra wells.
2298          * Note that PSR is enabled only on Port A even though this function
2299          * returns the correct domain for other ports too.
2300          */
2301         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2302                                               intel_aux_power_domain(dig_port);
2303 }
2304
2305 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2306                                         struct intel_crtc_state *crtc_state)
2307 {
2308         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2309         struct intel_digital_port *dig_port;
2310         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2311
2312         /*
2313          * TODO: Add support for MST encoders. Atm, the following should never
2314          * happen since fake-MST encoders don't set their get_power_domains()
2315          * hook.
2316          */
2317         if (drm_WARN_ON(&dev_priv->drm,
2318                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2319                 return;
2320
2321         dig_port = enc_to_dig_port(encoder);
2322
2323         if (!intel_phy_is_tc(dev_priv, phy) ||
2324             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2325                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2326                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2327                                                                    dig_port->ddi_io_power_domain);
2328         }
2329
2330         /*
2331          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2332          * ports.
2333          */
2334         if (intel_crtc_has_dp_encoder(crtc_state) ||
2335             intel_phy_is_tc(dev_priv, phy)) {
2336                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
2337                 dig_port->aux_wakeref =
2338                         intel_display_power_get(dev_priv,
2339                                                 intel_ddi_main_link_aux_domain(dig_port));
2340         }
2341 }
2342
2343 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
2344                                  const struct intel_crtc_state *crtc_state)
2345 {
2346         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2347         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2348         enum port port = encoder->port;
2349         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2350
2351         if (cpu_transcoder != TRANSCODER_EDP) {
2352                 if (INTEL_GEN(dev_priv) >= 12)
2353                         intel_de_write(dev_priv,
2354                                        TRANS_CLK_SEL(cpu_transcoder),
2355                                        TGL_TRANS_CLK_SEL_PORT(port));
2356                 else
2357                         intel_de_write(dev_priv,
2358                                        TRANS_CLK_SEL(cpu_transcoder),
2359                                        TRANS_CLK_SEL_PORT(port));
2360         }
2361 }
2362
2363 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2364 {
2365         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2366         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2367
2368         if (cpu_transcoder != TRANSCODER_EDP) {
2369                 if (INTEL_GEN(dev_priv) >= 12)
2370                         intel_de_write(dev_priv,
2371                                        TRANS_CLK_SEL(cpu_transcoder),
2372                                        TGL_TRANS_CLK_SEL_DISABLED);
2373                 else
2374                         intel_de_write(dev_priv,
2375                                        TRANS_CLK_SEL(cpu_transcoder),
2376                                        TRANS_CLK_SEL_DISABLED);
2377         }
2378 }
2379
2380 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2381                                 enum port port, u8 iboost)
2382 {
2383         u32 tmp;
2384
2385         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2386         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2387         if (iboost)
2388                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2389         else
2390                 tmp |= BALANCE_LEG_DISABLE(port);
2391         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2392 }
2393
2394 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2395                                const struct intel_crtc_state *crtc_state,
2396                                int level)
2397 {
2398         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2399         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2400         u8 iboost;
2401
2402         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2403                 iboost = intel_bios_hdmi_boost_level(encoder);
2404         else
2405                 iboost = intel_bios_dp_boost_level(encoder);
2406
2407         if (iboost == 0) {
2408                 const struct ddi_buf_trans *ddi_translations;
2409                 int n_entries;
2410
2411                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2412                         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
2413                 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2414                         ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2415                 else
2416                         ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2417
2418                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2419                         return;
2420                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2421                         level = n_entries - 1;
2422
2423                 iboost = ddi_translations[level].i_boost;
2424         }
2425
2426         /* Make sure that the requested I_boost is valid */
2427         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2428                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2429                 return;
2430         }
2431
2432         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
2433
2434         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
2435                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2436 }
2437
2438 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2439                                     const struct intel_crtc_state *crtc_state,
2440                                     int level)
2441 {
2442         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2443         const struct bxt_ddi_buf_trans *ddi_translations;
2444         enum port port = encoder->port;
2445         int n_entries;
2446
2447         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2448                 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
2449         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2450                 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
2451         else
2452                 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
2453
2454         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2455                 return;
2456         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2457                 level = n_entries - 1;
2458
2459         bxt_ddi_phy_set_signal_level(dev_priv, port,
2460                                      ddi_translations[level].margin,
2461                                      ddi_translations[level].scale,
2462                                      ddi_translations[level].enable,
2463                                      ddi_translations[level].deemphasis);
2464 }
2465
2466 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
2467                                    const struct intel_crtc_state *crtc_state)
2468 {
2469         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2470         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2471         enum port port = encoder->port;
2472         enum phy phy = intel_port_to_phy(dev_priv, port);
2473         int n_entries;
2474
2475         if (INTEL_GEN(dev_priv) >= 12) {
2476                 if (intel_phy_is_combo(dev_priv, phy))
2477                         tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2478                 else
2479                         tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
2480         } else if (INTEL_GEN(dev_priv) == 11) {
2481                 if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
2482                         jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2483                 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
2484                         ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2485                 else if (intel_phy_is_combo(dev_priv, phy))
2486                         icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2487                 else
2488                         icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
2489         } else if (IS_CANNONLAKE(dev_priv)) {
2490                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2491                         cnl_get_buf_trans_edp(encoder, &n_entries);
2492                 else
2493                         cnl_get_buf_trans_dp(encoder, &n_entries);
2494         } else if (IS_GEN9_LP(dev_priv)) {
2495                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2496                         bxt_get_buf_trans_edp(encoder, &n_entries);
2497                 else
2498                         bxt_get_buf_trans_dp(encoder, &n_entries);
2499         } else {
2500                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2501                         intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2502                 else
2503                         intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2504         }
2505
2506         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2507                 n_entries = 1;
2508         if (drm_WARN_ON(&dev_priv->drm,
2509                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2510                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2511
2512         return index_to_dp_signal_levels[n_entries - 1] &
2513                 DP_TRAIN_VOLTAGE_SWING_MASK;
2514 }
2515
2516 /*
2517  * We assume that the full set of pre-emphasis values can be
2518  * used on all DDI platforms. Should that change we need to
2519  * rethink this code.
2520  */
2521 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
2522 {
2523         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2524 }
2525
2526 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2527                                    const struct intel_crtc_state *crtc_state,
2528                                    int level)
2529 {
2530         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2531         const struct cnl_ddi_buf_trans *ddi_translations;
2532         enum port port = encoder->port;
2533         int n_entries, ln;
2534         u32 val;
2535
2536         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2537                 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
2538         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2539                 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
2540         else
2541                 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
2542
2543         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2544                 return;
2545         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2546                 level = n_entries - 1;
2547
2548         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2549         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2550         val &= ~SCALING_MODE_SEL_MASK;
2551         val |= SCALING_MODE_SEL(2);
2552         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2553
2554         /* Program PORT_TX_DW2 */
2555         val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2556         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2557                  RCOMP_SCALAR_MASK);
2558         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2559         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2560         /* Rcomp scalar is fixed as 0x98 for every table entry */
2561         val |= RCOMP_SCALAR(0x98);
2562         intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2563
2564         /* Program PORT_TX_DW4 */
2565         /* We cannot write to GRP. It would overrite individual loadgen */
2566         for (ln = 0; ln < 4; ln++) {
2567                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2568                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2569                          CURSOR_COEFF_MASK);
2570                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2571                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2572                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2573                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2574         }
2575
2576         /* Program PORT_TX_DW5 */
2577         /* All DW5 values are fixed for every table entry */
2578         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2579         val &= ~RTERM_SELECT_MASK;
2580         val |= RTERM_SELECT(6);
2581         val |= TAP3_DISABLE;
2582         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2583
2584         /* Program PORT_TX_DW7 */
2585         val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2586         val &= ~N_SCALAR_MASK;
2587         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2588         intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2589 }
2590
2591 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2592                                     const struct intel_crtc_state *crtc_state,
2593                                     int level)
2594 {
2595         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2596         enum port port = encoder->port;
2597         int width, rate, ln;
2598         u32 val;
2599
2600         width = crtc_state->lane_count;
2601         rate = crtc_state->port_clock;
2602
2603         /*
2604          * 1. If port type is eDP or DP,
2605          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2606          * else clear to 0b.
2607          */
2608         val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2609         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2610                 val &= ~COMMON_KEEPER_EN;
2611         else
2612                 val |= COMMON_KEEPER_EN;
2613         intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2614
2615         /* 2. Program loadgen select */
2616         /*
2617          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2618          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2619          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2620          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2621          */
2622         for (ln = 0; ln <= 3; ln++) {
2623                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2624                 val &= ~LOADGEN_SELECT;
2625
2626                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2627                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2628                         val |= LOADGEN_SELECT;
2629                 }
2630                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2631         }
2632
2633         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2634         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2635         val |= SUS_CLOCK_CONFIG;
2636         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2637
2638         /* 4. Clear training enable to change swing values */
2639         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2640         val &= ~TX_TRAINING_EN;
2641         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2642
2643         /* 5. Program swing and de-emphasis */
2644         cnl_ddi_vswing_program(encoder, crtc_state, level);
2645
2646         /* 6. Set training enable to trigger update */
2647         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2648         val |= TX_TRAINING_EN;
2649         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2650 }
2651
2652 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
2653                                          const struct intel_crtc_state *crtc_state,
2654                                          int level)
2655 {
2656         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2657         const struct cnl_ddi_buf_trans *ddi_translations;
2658         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2659         int n_entries, ln;
2660         u32 val;
2661
2662         if (INTEL_GEN(dev_priv) >= 12)
2663                 ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2664         else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
2665                 ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2666         else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
2667                 ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2668         else
2669                 ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2670         if (!ddi_translations)
2671                 return;
2672
2673         if (level >= n_entries) {
2674                 drm_dbg_kms(&dev_priv->drm,
2675                             "DDI translation not found for level %d. Using %d instead.",
2676                             level, n_entries - 1);
2677                 level = n_entries - 1;
2678         }
2679
2680         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
2681                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2682
2683                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
2684                 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
2685                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
2686                              intel_dp->hobl_active ? val : 0);
2687         }
2688
2689         /* Set PORT_TX_DW5 */
2690         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2691         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2692                   TAP2_DISABLE | TAP3_DISABLE);
2693         val |= SCALING_MODE_SEL(0x2);
2694         val |= RTERM_SELECT(0x6);
2695         val |= TAP3_DISABLE;
2696         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2697
2698         /* Program PORT_TX_DW2 */
2699         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2700         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2701                  RCOMP_SCALAR_MASK);
2702         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2703         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2704         /* Program Rcomp scalar for every table entry */
2705         val |= RCOMP_SCALAR(0x98);
2706         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2707
2708         /* Program PORT_TX_DW4 */
2709         /* We cannot write to GRP. It would overwrite individual loadgen. */
2710         for (ln = 0; ln <= 3; ln++) {
2711                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2712                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2713                          CURSOR_COEFF_MASK);
2714                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2715                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2716                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2717                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2718         }
2719
2720         /* Program PORT_TX_DW7 */
2721         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2722         val &= ~N_SCALAR_MASK;
2723         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2724         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2725 }
2726
2727 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2728                                               const struct intel_crtc_state *crtc_state,
2729                                               int level)
2730 {
2731         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2732         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2733         int width, rate, ln;
2734         u32 val;
2735
2736         width = crtc_state->lane_count;
2737         rate = crtc_state->port_clock;
2738
2739         /*
2740          * 1. If port type is eDP or DP,
2741          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2742          * else clear to 0b.
2743          */
2744         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2745         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2746                 val &= ~COMMON_KEEPER_EN;
2747         else
2748                 val |= COMMON_KEEPER_EN;
2749         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2750
2751         /* 2. Program loadgen select */
2752         /*
2753          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2754          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2755          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2756          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2757          */
2758         for (ln = 0; ln <= 3; ln++) {
2759                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2760                 val &= ~LOADGEN_SELECT;
2761
2762                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2763                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2764                         val |= LOADGEN_SELECT;
2765                 }
2766                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2767         }
2768
2769         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2770         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2771         val |= SUS_CLOCK_CONFIG;
2772         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2773
2774         /* 4. Clear training enable to change swing values */
2775         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2776         val &= ~TX_TRAINING_EN;
2777         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2778
2779         /* 5. Program swing and de-emphasis */
2780         icl_ddi_combo_vswing_program(encoder, crtc_state, level);
2781
2782         /* 6. Set training enable to trigger update */
2783         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2784         val |= TX_TRAINING_EN;
2785         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2786 }
2787
2788 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2789                                            const struct intel_crtc_state *crtc_state,
2790                                            int level)
2791 {
2792         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2793         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2794         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2795         int n_entries, ln;
2796         u32 val;
2797
2798         ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
2799         /* The table does not have values for level 3 and level 9. */
2800         if (level >= n_entries || level == 3 || level == 9) {
2801                 drm_dbg_kms(&dev_priv->drm,
2802                             "DDI translation not found for level %d. Using %d instead.",
2803                             level, n_entries - 2);
2804                 level = n_entries - 2;
2805         }
2806
2807         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2808         for (ln = 0; ln < 2; ln++) {
2809                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2810                 val &= ~CRI_USE_FS32;
2811                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2812
2813                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2814                 val &= ~CRI_USE_FS32;
2815                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2816         }
2817
2818         /* Program MG_TX_SWINGCTRL with values from vswing table */
2819         for (ln = 0; ln < 2; ln++) {
2820                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2821                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2822                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2823                         ddi_translations[level].cri_txdeemph_override_17_12);
2824                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2825
2826                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2827                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2828                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2829                         ddi_translations[level].cri_txdeemph_override_17_12);
2830                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2831         }
2832
2833         /* Program MG_TX_DRVCTRL with values from vswing table */
2834         for (ln = 0; ln < 2; ln++) {
2835                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2836                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2837                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2838                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2839                         ddi_translations[level].cri_txdeemph_override_5_0) |
2840                         CRI_TXDEEMPH_OVERRIDE_11_6(
2841                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2842                         CRI_TXDEEMPH_OVERRIDE_EN;
2843                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2844
2845                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2846                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2847                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2848                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2849                         ddi_translations[level].cri_txdeemph_override_5_0) |
2850                         CRI_TXDEEMPH_OVERRIDE_11_6(
2851                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2852                         CRI_TXDEEMPH_OVERRIDE_EN;
2853                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2854
2855                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2856         }
2857
2858         /*
2859          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2860          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2861          * values from table for which TX1 and TX2 enabled.
2862          */
2863         for (ln = 0; ln < 2; ln++) {
2864                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2865                 if (crtc_state->port_clock < 300000)
2866                         val |= CFG_LOW_RATE_LKREN_EN;
2867                 else
2868                         val &= ~CFG_LOW_RATE_LKREN_EN;
2869                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2870         }
2871
2872         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2873         for (ln = 0; ln < 2; ln++) {
2874                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2875                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2876                 if (crtc_state->port_clock <= 500000) {
2877                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2878                 } else {
2879                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2880                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2881                 }
2882                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2883
2884                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2885                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2886                 if (crtc_state->port_clock <= 500000) {
2887                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2888                 } else {
2889                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2890                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2891                 }
2892                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2893         }
2894
2895         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2896         for (ln = 0; ln < 2; ln++) {
2897                 val = intel_de_read(dev_priv,
2898                                     MG_TX1_PISO_READLOAD(ln, tc_port));
2899                 val |= CRI_CALCINIT;
2900                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2901                                val);
2902
2903                 val = intel_de_read(dev_priv,
2904                                     MG_TX2_PISO_READLOAD(ln, tc_port));
2905                 val |= CRI_CALCINIT;
2906                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2907                                val);
2908         }
2909 }
2910
2911 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2912                                     const struct intel_crtc_state *crtc_state,
2913                                     int level)
2914 {
2915         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2916         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2917
2918         if (intel_phy_is_combo(dev_priv, phy))
2919                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2920         else
2921                 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2922 }
2923
2924 static void
2925 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2926                                 const struct intel_crtc_state *crtc_state,
2927                                 int level)
2928 {
2929         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2930         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2931         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2932         u32 val, dpcnt_mask, dpcnt_val;
2933         int n_entries, ln;
2934
2935         ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
2936
2937         if (level >= n_entries)
2938                 level = n_entries - 1;
2939
2940         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2941                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2942                       DKL_TX_VSWING_CONTROL_MASK);
2943         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2944         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2945         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2946
2947         for (ln = 0; ln < 2; ln++) {
2948                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2949                                HIP_INDEX_VAL(tc_port, ln));
2950
2951                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2952
2953                 /* All the registers are RMW */
2954                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2955                 val &= ~dpcnt_mask;
2956                 val |= dpcnt_val;
2957                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2958
2959                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2960                 val &= ~dpcnt_mask;
2961                 val |= dpcnt_val;
2962                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2963
2964                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2965                 val &= ~DKL_TX_DP20BITMODE;
2966                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2967         }
2968 }
2969
2970 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2971                                     const struct intel_crtc_state *crtc_state,
2972                                     int level)
2973 {
2974         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2975         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2976
2977         if (intel_phy_is_combo(dev_priv, phy))
2978                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2979         else
2980                 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2981 }
2982
2983 static int translate_signal_level(struct intel_dp *intel_dp,
2984                                   u8 signal_levels)
2985 {
2986         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2987         int i;
2988
2989         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2990                 if (index_to_dp_signal_levels[i] == signal_levels)
2991                         return i;
2992         }
2993
2994         drm_WARN(&i915->drm, 1,
2995                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2996                  signal_levels);
2997
2998         return 0;
2999 }
3000
3001 static int intel_ddi_dp_level(struct intel_dp *intel_dp)
3002 {
3003         u8 train_set = intel_dp->train_set[0];
3004         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3005                                         DP_TRAIN_PRE_EMPHASIS_MASK);
3006
3007         return translate_signal_level(intel_dp, signal_levels);
3008 }
3009
3010 static void
3011 tgl_set_signal_levels(struct intel_dp *intel_dp,
3012                       const struct intel_crtc_state *crtc_state)
3013 {
3014         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3015         int level = intel_ddi_dp_level(intel_dp);
3016
3017         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3018 }
3019
3020 static void
3021 icl_set_signal_levels(struct intel_dp *intel_dp,
3022                       const struct intel_crtc_state *crtc_state)
3023 {
3024         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3025         int level = intel_ddi_dp_level(intel_dp);
3026
3027         icl_ddi_vswing_sequence(encoder, crtc_state, level);
3028 }
3029
3030 static void
3031 cnl_set_signal_levels(struct intel_dp *intel_dp,
3032                       const struct intel_crtc_state *crtc_state)
3033 {
3034         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3035         int level = intel_ddi_dp_level(intel_dp);
3036
3037         cnl_ddi_vswing_sequence(encoder, crtc_state, level);
3038 }
3039
3040 static void
3041 bxt_set_signal_levels(struct intel_dp *intel_dp,
3042                       const struct intel_crtc_state *crtc_state)
3043 {
3044         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3045         int level = intel_ddi_dp_level(intel_dp);
3046
3047         bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3048 }
3049
3050 static void
3051 hsw_set_signal_levels(struct intel_dp *intel_dp,
3052                       const struct intel_crtc_state *crtc_state)
3053 {
3054         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3055         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3056         int level = intel_ddi_dp_level(intel_dp);
3057         enum port port = encoder->port;
3058         u32 signal_levels;
3059
3060         signal_levels = DDI_BUF_TRANS_SELECT(level);
3061
3062         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3063                     signal_levels);
3064
3065         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
3066         intel_dp->DP |= signal_levels;
3067
3068         if (IS_GEN9_BC(dev_priv))
3069                 skl_ddi_set_iboost(encoder, crtc_state, level);
3070
3071         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3072         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3073 }
3074
3075 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
3076                                      enum phy phy)
3077 {
3078         if (IS_ROCKETLAKE(dev_priv)) {
3079                 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3080         } else if (intel_phy_is_combo(dev_priv, phy)) {
3081                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3082         } else if (intel_phy_is_tc(dev_priv, phy)) {
3083                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
3084                                                         (enum port)phy);
3085
3086                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
3087         }
3088
3089         return 0;
3090 }
3091
3092 static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
3093                                   const struct intel_crtc_state *crtc_state)
3094 {
3095         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3096         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3097         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3098         u32 val;
3099
3100         /*
3101          * If we fail this, something went very wrong: first 2 PLLs should be
3102          * used by first 2 phys and last 2 PLLs by last phys
3103          */
3104         if (drm_WARN_ON(&dev_priv->drm,
3105                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
3106                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
3107                 return;
3108
3109         mutex_lock(&dev_priv->dpll.lock);
3110
3111         val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
3112         drm_WARN_ON(&dev_priv->drm,
3113                     (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
3114
3115         val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
3116         val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
3117         intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
3118         intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
3119
3120         val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3121         intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
3122
3123         mutex_unlock(&dev_priv->dpll.lock);
3124 }
3125
3126 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
3127                                   const struct intel_crtc_state *crtc_state)
3128 {
3129         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3130         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3131         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3132         u32 val;
3133
3134         mutex_lock(&dev_priv->dpll.lock);
3135
3136         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
3137         drm_WARN_ON(&dev_priv->drm,
3138                     (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
3139
3140         if (intel_phy_is_combo(dev_priv, phy)) {
3141                 u32 mask, sel;
3142
3143                 if (IS_ROCKETLAKE(dev_priv)) {
3144                         mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
3145                         sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
3146                 } else {
3147                         mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
3148                         sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
3149                 }
3150
3151                 /*
3152                  * Even though this register references DDIs, note that we
3153                  * want to pass the PHY rather than the port (DDI).  For
3154                  * ICL, port=phy in all cases so it doesn't matter, but for
3155                  * EHL the bspec notes the following:
3156                  *
3157                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
3158                  *   Clock Select chooses the PLL for both DDIA and DDID and
3159                  *   drives port A in all cases."
3160                  */
3161                 val &= ~mask;
3162                 val |= sel;
3163                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3164                 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
3165         }
3166
3167         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3168         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3169
3170         mutex_unlock(&dev_priv->dpll.lock);
3171 }
3172
3173 static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
3174 {
3175         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3176         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3177
3178         mutex_lock(&dev_priv->dpll.lock);
3179
3180         intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
3181                      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
3182
3183         mutex_unlock(&dev_priv->dpll.lock);
3184 }
3185
3186 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
3187 {
3188         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3189         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3190         u32 val;
3191
3192         mutex_lock(&dev_priv->dpll.lock);
3193
3194         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
3195         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3196         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3197
3198         mutex_unlock(&dev_priv->dpll.lock);
3199 }
3200
3201 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
3202                                       u32 port_mask, bool ddi_clk_needed)
3203 {
3204         enum port port;
3205         u32 val;
3206
3207         for_each_port_masked(port, port_mask) {
3208                 enum phy phy = intel_port_to_phy(dev_priv, port);
3209                 bool ddi_clk_off;
3210
3211                 val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
3212                 ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3213
3214                 if (ddi_clk_needed == !ddi_clk_off)
3215                         continue;
3216
3217                 /*
3218                  * Punt on the case now where clock is gated, but it would
3219                  * be needed by the port. Something else is really broken then.
3220                  */
3221                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
3222                         continue;
3223
3224                 drm_notice(&dev_priv->drm,
3225                            "PHY %c is disabled with an ungated DDI clock, gate it\n",
3226                            phy_name(phy));
3227                 val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3228                 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
3229         }
3230 }
3231
3232 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
3233                                       u32 port_mask, bool ddi_clk_needed)
3234 {
3235         enum port port;
3236         u32 val;
3237
3238         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
3239         for_each_port_masked(port, port_mask) {
3240                 enum phy phy = intel_port_to_phy(dev_priv, port);
3241                 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
3242                                                                    phy);
3243
3244                 if (ddi_clk_needed == !ddi_clk_off)
3245                         continue;
3246
3247                 /*
3248                  * Punt on the case now where clock is gated, but it would
3249                  * be needed by the port. Something else is really broken then.
3250                  */
3251                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
3252                         continue;
3253
3254                 drm_notice(&dev_priv->drm,
3255                            "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
3256                            phy_name(phy));
3257                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3258                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3259         }
3260 }
3261
3262 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3263 {
3264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3265         u32 port_mask;
3266         bool ddi_clk_needed;
3267
3268         /*
3269          * In case of DP MST, we sanitize the primary encoder only, not the
3270          * virtual ones.
3271          */
3272         if (encoder->type == INTEL_OUTPUT_DP_MST)
3273                 return;
3274
3275         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3276                 u8 pipe_mask;
3277                 bool is_mst;
3278
3279                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3280                 /*
3281                  * In the unlikely case that BIOS enables DP in MST mode, just
3282                  * warn since our MST HW readout is incomplete.
3283                  */
3284                 if (drm_WARN_ON(&dev_priv->drm, is_mst))
3285                         return;
3286         }
3287
3288         port_mask = BIT(encoder->port);
3289         ddi_clk_needed = encoder->base.crtc;
3290
3291         if (encoder->type == INTEL_OUTPUT_DSI) {
3292                 struct intel_encoder *other_encoder;
3293
3294                 port_mask = intel_dsi_encoder_ports(encoder);
3295                 /*
3296                  * Sanity check that we haven't incorrectly registered another
3297                  * encoder using any of the ports of this DSI encoder.
3298                  */
3299                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3300                         if (other_encoder == encoder)
3301                                 continue;
3302
3303                         if (drm_WARN_ON(&dev_priv->drm,
3304                                         port_mask & BIT(other_encoder->port)))
3305                                 return;
3306                 }
3307                 /*
3308                  * For DSI we keep the ddi clocks gated
3309                  * except during enable/disable sequence.
3310                  */
3311                 ddi_clk_needed = false;
3312         }
3313
3314         if (IS_DG1(dev_priv))
3315                 dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3316         else
3317                 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3318 }
3319
3320 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3321                                  const struct intel_crtc_state *crtc_state)
3322 {
3323         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3324         enum port port = encoder->port;
3325         enum phy phy = intel_port_to_phy(dev_priv, port);
3326         u32 val;
3327         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3328
3329         if (drm_WARN_ON(&dev_priv->drm, !pll))
3330                 return;
3331
3332         mutex_lock(&dev_priv->dpll.lock);
3333
3334         if (INTEL_GEN(dev_priv) >= 11) {
3335                 if (!intel_phy_is_combo(dev_priv, phy))
3336                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3337                                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3338                 else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)
3339                         /*
3340                          * MG does not exist but the programming is required
3341                          * to ungate DDIC and DDID
3342                          */
3343                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3344                                        DDI_CLK_SEL_MG);
3345         } else if (IS_CANNONLAKE(dev_priv)) {
3346                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3347                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3348                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3349                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3350                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3351
3352                 /*
3353                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3354                  * This step and the step before must be done with separate
3355                  * register writes.
3356                  */
3357                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3358                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3359                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3360         } else if (IS_GEN9_BC(dev_priv)) {
3361                 /* DDI -> PLL mapping  */
3362                 val = intel_de_read(dev_priv, DPLL_CTRL2);
3363
3364                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3365                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3366                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3367                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3368
3369                 intel_de_write(dev_priv, DPLL_CTRL2, val);
3370
3371         } else if (INTEL_GEN(dev_priv) < 9) {
3372                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3373                                hsw_pll_to_ddi_pll_sel(pll));
3374         }
3375
3376         mutex_unlock(&dev_priv->dpll.lock);
3377 }
3378
3379 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3380 {
3381         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3382         enum port port = encoder->port;
3383         enum phy phy = intel_port_to_phy(dev_priv, port);
3384
3385         if (INTEL_GEN(dev_priv) >= 11) {
3386                 if (!intel_phy_is_combo(dev_priv, phy) ||
3387                     (IS_JSL_EHL(dev_priv) && port >= PORT_C))
3388                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3389                                        DDI_CLK_SEL_NONE);
3390         } else if (IS_CANNONLAKE(dev_priv)) {
3391                 intel_de_write(dev_priv, DPCLKA_CFGCR0,
3392                                intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3393         } else if (IS_GEN9_BC(dev_priv)) {
3394                 intel_de_write(dev_priv, DPLL_CTRL2,
3395                                intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
3396         } else if (INTEL_GEN(dev_priv) < 9) {
3397                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3398                                PORT_CLK_SEL_NONE);
3399         }
3400 }
3401
3402 static void
3403 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
3404                        const struct intel_crtc_state *crtc_state)
3405 {
3406         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3407         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3408         u32 ln0, ln1, pin_assignment;
3409         u8 width;
3410
3411         if (dig_port->tc_mode == TC_PORT_TBT_ALT)
3412                 return;
3413
3414         if (INTEL_GEN(dev_priv) >= 12) {
3415                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3416                                HIP_INDEX_VAL(tc_port, 0x0));
3417                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3418                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3419                                HIP_INDEX_VAL(tc_port, 0x1));
3420                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3421         } else {
3422                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
3423                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
3424         }
3425
3426         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3427         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3428
3429         /* DPPATC */
3430         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
3431         width = crtc_state->lane_count;
3432
3433         switch (pin_assignment) {
3434         case 0x0:
3435                 drm_WARN_ON(&dev_priv->drm,
3436                             dig_port->tc_mode != TC_PORT_LEGACY);
3437                 if (width == 1) {
3438                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3439                 } else {
3440                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3441                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3442                 }
3443                 break;
3444         case 0x1:
3445                 if (width == 4) {
3446                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3447                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3448                 }
3449                 break;
3450         case 0x2:
3451                 if (width == 2) {
3452                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3453                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3454                 }
3455                 break;
3456         case 0x3:
3457         case 0x5:
3458                 if (width == 1) {
3459                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3460                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3461                 } else {
3462                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3463                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3464                 }
3465                 break;
3466         case 0x4:
3467         case 0x6:
3468                 if (width == 1) {
3469                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3470                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3471                 } else {
3472                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3473                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3474                 }
3475                 break;
3476         default:
3477                 MISSING_CASE(pin_assignment);
3478         }
3479
3480         if (INTEL_GEN(dev_priv) >= 12) {
3481                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3482                                HIP_INDEX_VAL(tc_port, 0x0));
3483                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3484                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3485                                HIP_INDEX_VAL(tc_port, 0x1));
3486                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3487         } else {
3488                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3489                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3490         }
3491 }
3492
3493 static enum transcoder
3494 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
3495 {
3496         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
3497                 return crtc_state->mst_master_transcoder;
3498         else
3499                 return crtc_state->cpu_transcoder;
3500 }
3501
3502 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
3503                          const struct intel_crtc_state *crtc_state)
3504 {
3505         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3506
3507         if (INTEL_GEN(dev_priv) >= 12)
3508                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
3509         else
3510                 return DP_TP_CTL(encoder->port);
3511 }
3512
3513 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
3514                             const struct intel_crtc_state *crtc_state)
3515 {
3516         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3517
3518         if (INTEL_GEN(dev_priv) >= 12)
3519                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
3520         else
3521                 return DP_TP_STATUS(encoder->port);
3522 }
3523
3524 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3525                                         const struct intel_crtc_state *crtc_state)
3526 {
3527         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3528
3529         if (!crtc_state->fec_enable)
3530                 return;
3531
3532         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3533                 drm_dbg_kms(&i915->drm,
3534                             "Failed to set FEC_READY in the sink\n");
3535 }
3536
3537 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3538                                  const struct intel_crtc_state *crtc_state)
3539 {
3540         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3541         struct intel_dp *intel_dp;
3542         u32 val;
3543
3544         if (!crtc_state->fec_enable)
3545                 return;
3546
3547         intel_dp = enc_to_intel_dp(encoder);
3548         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3549         val |= DP_TP_CTL_FEC_ENABLE;
3550         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3551 }
3552
3553 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3554                                         const struct intel_crtc_state *crtc_state)
3555 {
3556         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3557         struct intel_dp *intel_dp;
3558         u32 val;
3559
3560         if (!crtc_state->fec_enable)
3561                 return;
3562
3563         intel_dp = enc_to_intel_dp(encoder);
3564         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3565         val &= ~DP_TP_CTL_FEC_ENABLE;
3566         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3567         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3568 }
3569
3570 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3571                                   struct intel_encoder *encoder,
3572                                   const struct intel_crtc_state *crtc_state,
3573                                   const struct drm_connector_state *conn_state)
3574 {
3575         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3576         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3577         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3578         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3579         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3580         int level = intel_ddi_dp_level(intel_dp);
3581
3582         intel_dp_set_link_params(intel_dp,
3583                                  crtc_state->port_clock,
3584                                  crtc_state->lane_count);
3585
3586         /*
3587          * 1. Enable Power Wells
3588          *
3589          * This was handled at the beginning of intel_atomic_commit_tail(),
3590          * before we called down into this function.
3591          */
3592
3593         /* 2. Enable Panel Power if PPS is required */
3594         intel_edp_panel_on(intel_dp);
3595
3596         /*
3597          * 3. For non-TBT Type-C ports, set FIA lane count
3598          * (DFLEXDPSP.DPX4TXLATC)
3599          *
3600          * This was done before tgl_ddi_pre_enable_dp by
3601          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3602          */
3603
3604         /*
3605          * 4. Enable the port PLL.
3606          *
3607          * The PLL enabling itself was already done before this function by
3608          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
3609          * configure the PLL to port mapping here.
3610          */
3611         intel_ddi_clk_select(encoder, crtc_state);
3612
3613         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3614         if (!intel_phy_is_tc(dev_priv, phy) ||
3615             dig_port->tc_mode != TC_PORT_TBT_ALT) {
3616                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
3617                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
3618                                                                    dig_port->ddi_io_power_domain);
3619         }
3620
3621         /* 6. Program DP_MODE */
3622         icl_program_mg_dp_mode(dig_port, crtc_state);
3623
3624         /*
3625          * 7. The rest of the below are substeps under the bspec's "Enable and
3626          * Train Display Port" step.  Note that steps that are specific to
3627          * MST will be handled by intel_mst_pre_enable_dp() before/after it
3628          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
3629          * us when active_mst_links==0, so any steps designated for "single
3630          * stream or multi-stream master transcoder" can just be performed
3631          * unconditionally here.
3632          */
3633
3634         /*
3635          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3636          * Transcoder.
3637          */
3638         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3639
3640         /*
3641          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3642          * Transport Select
3643          */
3644         intel_ddi_config_transcoder_func(encoder, crtc_state);
3645
3646         /*
3647          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3648          * selected
3649          *
3650          * This will be handled by the intel_dp_start_link_train() farther
3651          * down this function.
3652          */
3653
3654         /* 7.e Configure voltage swing and related IO settings */
3655         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3656
3657         /*
3658          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3659          * the used lanes of the DDI.
3660          */
3661         if (intel_phy_is_combo(dev_priv, phy)) {
3662                 bool lane_reversal =
3663                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3664
3665                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3666                                                crtc_state->lane_count,
3667                                                lane_reversal);
3668         }
3669
3670         /*
3671          * 7.g Configure and enable DDI_BUF_CTL
3672          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3673          *     after 500 us.
3674          *
3675          * We only configure what the register value will be here.  Actual
3676          * enabling happens during link training farther down.
3677          */
3678         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
3679
3680         if (!is_mst)
3681                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
3682
3683         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3684         /*
3685          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3686          * in the FEC_CONFIGURATION register to 1 before initiating link
3687          * training
3688          */
3689         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3690
3691         /*
3692          * 7.i Follow DisplayPort specification training sequence (see notes for
3693          *     failure handling)
3694          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3695          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3696          *     (timeout after 800 us)
3697          */
3698         intel_dp_start_link_train(intel_dp, crtc_state);
3699
3700         /* 7.k Set DP_TP_CTL link training to Normal */
3701         if (!is_trans_port_sync_mode(crtc_state))
3702                 intel_dp_stop_link_train(intel_dp, crtc_state);
3703
3704         /* 7.l Configure and enable FEC if needed */
3705         intel_ddi_enable_fec(encoder, crtc_state);
3706         if (!crtc_state->bigjoiner)
3707                 intel_dsc_enable(encoder, crtc_state);
3708 }
3709
3710 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3711                                   struct intel_encoder *encoder,
3712                                   const struct intel_crtc_state *crtc_state,
3713                                   const struct drm_connector_state *conn_state)
3714 {
3715         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3716         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3717         enum port port = encoder->port;
3718         enum phy phy = intel_port_to_phy(dev_priv, port);
3719         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3720         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3721         int level = intel_ddi_dp_level(intel_dp);
3722
3723         if (INTEL_GEN(dev_priv) < 11)
3724                 drm_WARN_ON(&dev_priv->drm,
3725                             is_mst && (port == PORT_A || port == PORT_E));
3726         else
3727                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3728
3729         intel_dp_set_link_params(intel_dp,
3730                                  crtc_state->port_clock,
3731                                  crtc_state->lane_count);
3732
3733         intel_edp_panel_on(intel_dp);
3734
3735         intel_ddi_clk_select(encoder, crtc_state);
3736
3737         if (!intel_phy_is_tc(dev_priv, phy) ||
3738             dig_port->tc_mode != TC_PORT_TBT_ALT) {
3739                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
3740                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
3741                                                                    dig_port->ddi_io_power_domain);
3742         }
3743
3744         icl_program_mg_dp_mode(dig_port, crtc_state);
3745
3746         if (INTEL_GEN(dev_priv) >= 11)
3747                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
3748         else if (IS_CANNONLAKE(dev_priv))
3749                 cnl_ddi_vswing_sequence(encoder, crtc_state, level);
3750         else if (IS_GEN9_LP(dev_priv))
3751                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3752         else
3753                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3754
3755         if (intel_phy_is_combo(dev_priv, phy)) {
3756                 bool lane_reversal =
3757                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3758
3759                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3760                                                crtc_state->lane_count,
3761                                                lane_reversal);
3762         }
3763
3764         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
3765         if (!is_mst)
3766                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
3767         intel_dp_configure_protocol_converter(intel_dp);
3768         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3769                                               true);
3770         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3771         intel_dp_start_link_train(intel_dp, crtc_state);
3772         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3773             !is_trans_port_sync_mode(crtc_state))
3774                 intel_dp_stop_link_train(intel_dp, crtc_state);
3775
3776         intel_ddi_enable_fec(encoder, crtc_state);
3777
3778         if (!is_mst)
3779                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3780
3781         if (!crtc_state->bigjoiner)
3782                 intel_dsc_enable(encoder, crtc_state);
3783 }
3784
3785 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3786                                     struct intel_encoder *encoder,
3787                                     const struct intel_crtc_state *crtc_state,
3788                                     const struct drm_connector_state *conn_state)
3789 {
3790         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3791
3792         if (INTEL_GEN(dev_priv) >= 12)
3793                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3794         else
3795                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3796
3797         /* MST will call a setting of MSA after an allocating of Virtual Channel
3798          * from MST encoder pre_enable callback.
3799          */
3800         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3801                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3802
3803                 intel_dp_set_m_n(crtc_state, M1_N1);
3804         }
3805 }
3806
3807 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3808                                       struct intel_encoder *encoder,
3809                                       const struct intel_crtc_state *crtc_state,
3810                                       const struct drm_connector_state *conn_state)
3811 {
3812         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3813         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3814         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3815         int level = intel_ddi_hdmi_level(encoder, crtc_state);
3816
3817         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3818         intel_ddi_clk_select(encoder, crtc_state);
3819
3820         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
3821         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
3822                                                            dig_port->ddi_io_power_domain);
3823
3824         icl_program_mg_dp_mode(dig_port, crtc_state);
3825
3826         if (INTEL_GEN(dev_priv) >= 12)
3827                 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3828         else if (INTEL_GEN(dev_priv) == 11)
3829                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
3830         else if (IS_CANNONLAKE(dev_priv))
3831                 cnl_ddi_vswing_sequence(encoder, crtc_state, level);
3832         else if (IS_GEN9_LP(dev_priv))
3833                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3834         else
3835                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3836
3837         if (IS_GEN9_BC(dev_priv))
3838                 skl_ddi_set_iboost(encoder, crtc_state, level);
3839
3840         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3841
3842         dig_port->set_infoframes(encoder,
3843                                  crtc_state->has_infoframe,
3844                                  crtc_state, conn_state);
3845 }
3846
3847 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3848                                  struct intel_encoder *encoder,
3849                                  const struct intel_crtc_state *crtc_state,
3850                                  const struct drm_connector_state *conn_state)
3851 {
3852         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3853         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3854         enum pipe pipe = crtc->pipe;
3855
3856         /*
3857          * When called from DP MST code:
3858          * - conn_state will be NULL
3859          * - encoder will be the main encoder (ie. mst->primary)
3860          * - the main connector associated with this port
3861          *   won't be active or linked to a crtc
3862          * - crtc_state will be the state of the first stream to
3863          *   be activated on this port, and it may not be the same
3864          *   stream that will be deactivated last, but each stream
3865          *   should have a state that is identical when it comes to
3866          *   the DP link parameteres
3867          */
3868
3869         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3870
3871         if (IS_DG1(dev_priv))
3872                 dg1_map_plls_to_ports(encoder, crtc_state);
3873         else if (INTEL_GEN(dev_priv) >= 11)
3874                 icl_map_plls_to_ports(encoder, crtc_state);
3875
3876         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3877
3878         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3879                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3880                                           conn_state);
3881         } else {
3882                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3883
3884                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3885                                         conn_state);
3886
3887                 /* FIXME precompute everything properly */
3888                 /* FIXME how do we turn infoframes off again? */
3889                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3890                         dig_port->set_infoframes(encoder,
3891                                                  crtc_state->has_infoframe,
3892                                                  crtc_state, conn_state);
3893         }
3894 }
3895
3896 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3897                                   const struct intel_crtc_state *crtc_state)
3898 {
3899         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3900         enum port port = encoder->port;
3901         bool wait = false;
3902         u32 val;
3903
3904         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3905         if (val & DDI_BUF_CTL_ENABLE) {
3906                 val &= ~DDI_BUF_CTL_ENABLE;
3907                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3908                 wait = true;
3909         }
3910
3911         if (intel_crtc_has_dp_encoder(crtc_state)) {
3912                 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3913                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3914                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3915                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3916         }
3917
3918         /* Disable FEC in DP Sink */
3919         intel_ddi_disable_fec_state(encoder, crtc_state);
3920
3921         if (wait)
3922                 intel_wait_ddi_buf_idle(dev_priv, port);
3923 }
3924
3925 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3926                                       struct intel_encoder *encoder,
3927                                       const struct intel_crtc_state *old_crtc_state,
3928                                       const struct drm_connector_state *old_conn_state)
3929 {
3930         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3931         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3932         struct intel_dp *intel_dp = &dig_port->dp;
3933         bool is_mst = intel_crtc_has_type(old_crtc_state,
3934                                           INTEL_OUTPUT_DP_MST);
3935         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3936
3937         if (!is_mst)
3938                 intel_dp_set_infoframes(encoder, false,
3939                                         old_crtc_state, old_conn_state);
3940
3941         /*
3942          * Power down sink before disabling the port, otherwise we end
3943          * up getting interrupts from the sink on detecting link loss.
3944          */
3945         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3946
3947         if (INTEL_GEN(dev_priv) >= 12) {
3948                 if (is_mst) {
3949                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3950                         u32 val;
3951
3952                         val = intel_de_read(dev_priv,
3953                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
3954                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
3955                                  TRANS_DDI_MODE_SELECT_MASK);
3956                         intel_de_write(dev_priv,
3957                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
3958                                        val);
3959                 }
3960         } else {
3961                 if (!is_mst)
3962                         intel_ddi_disable_pipe_clock(old_crtc_state);
3963         }
3964
3965         intel_disable_ddi_buf(encoder, old_crtc_state);
3966
3967         /*
3968          * From TGL spec: "If single stream or multi-stream master transcoder:
3969          * Configure Transcoder Clock select to direct no clock to the
3970          * transcoder"
3971          */
3972         if (INTEL_GEN(dev_priv) >= 12)
3973                 intel_ddi_disable_pipe_clock(old_crtc_state);
3974
3975         intel_edp_panel_vdd_on(intel_dp);
3976         intel_edp_panel_off(intel_dp);
3977
3978         if (!intel_phy_is_tc(dev_priv, phy) ||
3979             dig_port->tc_mode != TC_PORT_TBT_ALT)
3980                 intel_display_power_put(dev_priv,
3981                                         dig_port->ddi_io_power_domain,
3982                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
3983
3984         intel_ddi_clk_disable(encoder);
3985 }
3986
3987 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3988                                         struct intel_encoder *encoder,
3989                                         const struct intel_crtc_state *old_crtc_state,
3990                                         const struct drm_connector_state *old_conn_state)
3991 {
3992         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3993         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3994         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3995
3996         dig_port->set_infoframes(encoder, false,
3997                                  old_crtc_state, old_conn_state);
3998
3999         intel_ddi_disable_pipe_clock(old_crtc_state);
4000
4001         intel_disable_ddi_buf(encoder, old_crtc_state);
4002
4003         intel_display_power_put(dev_priv,
4004                                 dig_port->ddi_io_power_domain,
4005                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
4006
4007         intel_ddi_clk_disable(encoder);
4008
4009         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
4010 }
4011
4012 static void intel_ddi_post_disable(struct intel_atomic_state *state,
4013                                    struct intel_encoder *encoder,
4014                                    const struct intel_crtc_state *old_crtc_state,
4015                                    const struct drm_connector_state *old_conn_state)
4016 {
4017         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4018         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4019         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4020         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4021
4022         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
4023                 intel_crtc_vblank_off(old_crtc_state);
4024
4025                 intel_disable_pipe(old_crtc_state);
4026
4027                 intel_ddi_disable_transcoder_func(old_crtc_state);
4028
4029                 intel_dsc_disable(old_crtc_state);
4030
4031                 if (INTEL_GEN(dev_priv) >= 9)
4032                         skl_scaler_disable(old_crtc_state);
4033                 else
4034                         ilk_pfit_disable(old_crtc_state);
4035         }
4036
4037         if (old_crtc_state->bigjoiner_linked_crtc) {
4038                 struct intel_atomic_state *state =
4039                         to_intel_atomic_state(old_crtc_state->uapi.state);
4040                 struct intel_crtc *slave =
4041                         old_crtc_state->bigjoiner_linked_crtc;
4042                 const struct intel_crtc_state *old_slave_crtc_state =
4043                         intel_atomic_get_old_crtc_state(state, slave);
4044
4045                 intel_crtc_vblank_off(old_slave_crtc_state);
4046                 trace_intel_pipe_disable(slave);
4047
4048                 intel_dsc_disable(old_slave_crtc_state);
4049                 skl_scaler_disable(old_slave_crtc_state);
4050         }
4051
4052         /*
4053          * When called from DP MST code:
4054          * - old_conn_state will be NULL
4055          * - encoder will be the main encoder (ie. mst->primary)
4056          * - the main connector associated with this port
4057          *   won't be active or linked to a crtc
4058          * - old_crtc_state will be the state of the last stream to
4059          *   be deactivated on this port, and it may not be the same
4060          *   stream that was activated last, but each stream
4061          *   should have a state that is identical when it comes to
4062          *   the DP link parameteres
4063          */
4064
4065         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4066                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
4067                                             old_conn_state);
4068         else
4069                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
4070                                           old_conn_state);
4071
4072         if (IS_DG1(dev_priv))
4073                 dg1_unmap_plls_to_ports(encoder);
4074         else if (INTEL_GEN(dev_priv) >= 11)
4075                 icl_unmap_plls_to_ports(encoder);
4076
4077         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
4078                 intel_display_power_put(dev_priv,
4079                                         intel_ddi_main_link_aux_domain(dig_port),
4080                                         fetch_and_zero(&dig_port->aux_wakeref));
4081
4082         if (is_tc_port)
4083                 intel_tc_port_put_link(dig_port);
4084 }
4085
4086 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
4087                                 struct intel_encoder *encoder,
4088                                 const struct intel_crtc_state *old_crtc_state,
4089                                 const struct drm_connector_state *old_conn_state)
4090 {
4091         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4092         u32 val;
4093
4094         /*
4095          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
4096          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
4097          * step 13 is the correct place for it. Step 18 is where it was
4098          * originally before the BUN.
4099          */
4100         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
4101         val &= ~FDI_RX_ENABLE;
4102         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
4103
4104         intel_disable_ddi_buf(encoder, old_crtc_state);
4105         intel_ddi_clk_disable(encoder);
4106
4107         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
4108         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
4109         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
4110         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
4111
4112         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
4113         val &= ~FDI_PCDCLK;
4114         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
4115
4116         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
4117         val &= ~FDI_RX_PLL_ENABLE;
4118         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
4119 }
4120
4121 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
4122                                             struct intel_encoder *encoder,
4123                                             const struct intel_crtc_state *crtc_state)
4124 {
4125         const struct drm_connector_state *conn_state;
4126         struct drm_connector *conn;
4127         int i;
4128
4129         if (!crtc_state->sync_mode_slaves_mask)
4130                 return;
4131
4132         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
4133                 struct intel_encoder *slave_encoder =
4134                         to_intel_encoder(conn_state->best_encoder);
4135                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
4136                 const struct intel_crtc_state *slave_crtc_state;
4137
4138                 if (!slave_crtc)
4139                         continue;
4140
4141                 slave_crtc_state =
4142                         intel_atomic_get_new_crtc_state(state, slave_crtc);
4143
4144                 if (slave_crtc_state->master_transcoder !=
4145                     crtc_state->cpu_transcoder)
4146                         continue;
4147
4148                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
4149                                          slave_crtc_state);
4150         }
4151
4152         usleep_range(200, 400);
4153
4154         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
4155                                  crtc_state);
4156 }
4157
4158 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
4159                                 struct intel_encoder *encoder,
4160                                 const struct intel_crtc_state *crtc_state,
4161                                 const struct drm_connector_state *conn_state)
4162 {
4163         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4164         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4165         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4166         enum port port = encoder->port;
4167
4168         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
4169                 intel_dp_stop_link_train(intel_dp, crtc_state);
4170
4171         intel_edp_backlight_on(crtc_state, conn_state);
4172         intel_psr_enable(intel_dp, crtc_state, conn_state);
4173
4174         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
4175                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
4176
4177         intel_edp_drrs_enable(intel_dp, crtc_state);
4178
4179         if (crtc_state->has_audio)
4180                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
4181
4182         trans_port_sync_stop_link_train(state, encoder, crtc_state);
4183 }
4184
4185 static i915_reg_t
4186 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
4187                                enum port port)
4188 {
4189         static const enum transcoder trans[] = {
4190                 [PORT_A] = TRANSCODER_EDP,
4191                 [PORT_B] = TRANSCODER_A,
4192                 [PORT_C] = TRANSCODER_B,
4193                 [PORT_D] = TRANSCODER_C,
4194                 [PORT_E] = TRANSCODER_A,
4195         };
4196
4197         drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
4198
4199         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
4200                 port = PORT_A;
4201
4202         return CHICKEN_TRANS(trans[port]);
4203 }
4204
4205 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
4206                                   struct intel_encoder *encoder,
4207                                   const struct intel_crtc_state *crtc_state,
4208                                   const struct drm_connector_state *conn_state)
4209 {
4210         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4211         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4212         struct drm_connector *connector = conn_state->connector;
4213         enum port port = encoder->port;
4214
4215         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4216                                                crtc_state->hdmi_high_tmds_clock_ratio,
4217                                                crtc_state->hdmi_scrambling))
4218                 drm_dbg_kms(&dev_priv->drm,
4219                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
4220                             connector->base.id, connector->name);
4221
4222         /* Display WA #1143: skl,kbl,cfl */
4223         if (IS_GEN9_BC(dev_priv)) {
4224                 /*
4225                  * For some reason these chicken bits have been
4226                  * stuffed into a transcoder register, event though
4227                  * the bits affect a specific DDI port rather than
4228                  * a specific transcoder.
4229                  */
4230                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
4231                 u32 val;
4232
4233                 val = intel_de_read(dev_priv, reg);
4234
4235                 if (port == PORT_E)
4236                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
4237                                 DDIE_TRAINING_OVERRIDE_VALUE;
4238                 else
4239                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
4240                                 DDI_TRAINING_OVERRIDE_VALUE;
4241
4242                 intel_de_write(dev_priv, reg, val);
4243                 intel_de_posting_read(dev_priv, reg);
4244
4245                 udelay(1);
4246
4247                 if (port == PORT_E)
4248                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
4249                                  DDIE_TRAINING_OVERRIDE_VALUE);
4250                 else
4251                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
4252                                  DDI_TRAINING_OVERRIDE_VALUE);
4253
4254                 intel_de_write(dev_priv, reg, val);
4255         }
4256
4257         /* In HDMI/DVI mode, the port width, and swing/emphasis values
4258          * are ignored so nothing special needs to be done besides
4259          * enabling the port.
4260          */
4261         intel_de_write(dev_priv, DDI_BUF_CTL(port),
4262                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
4263
4264         if (crtc_state->has_audio)
4265                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
4266 }
4267
4268 static void intel_enable_ddi(struct intel_atomic_state *state,
4269                              struct intel_encoder *encoder,
4270                              const struct intel_crtc_state *crtc_state,
4271                              const struct drm_connector_state *conn_state)
4272 {
4273         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
4274
4275         if (!crtc_state->bigjoiner_slave)
4276                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
4277
4278         intel_enable_pipe(crtc_state);
4279
4280         intel_crtc_vblank_on(crtc_state);
4281
4282         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4283                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
4284         else
4285                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
4286
4287         /* Enable hdcp if it's desired */
4288         if (conn_state->content_protection ==
4289             DRM_MODE_CONTENT_PROTECTION_DESIRED)
4290                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
4291                                   crtc_state->cpu_transcoder,
4292                                   (u8)conn_state->hdcp_content_type);
4293 }
4294
4295 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
4296                                  struct intel_encoder *encoder,
4297                                  const struct intel_crtc_state *old_crtc_state,
4298                                  const struct drm_connector_state *old_conn_state)
4299 {
4300         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4301
4302         intel_dp->link_trained = false;
4303
4304         if (old_crtc_state->has_audio)
4305                 intel_audio_codec_disable(encoder,
4306                                           old_crtc_state, old_conn_state);
4307
4308         intel_edp_drrs_disable(intel_dp, old_crtc_state);
4309         intel_psr_disable(intel_dp, old_crtc_state);
4310         intel_edp_backlight_off(old_conn_state);
4311         /* Disable the decompression in DP Sink */
4312         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
4313                                               false);
4314 }
4315
4316 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
4317                                    struct intel_encoder *encoder,
4318                                    const struct intel_crtc_state *old_crtc_state,
4319                                    const struct drm_connector_state *old_conn_state)
4320 {
4321         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4322         struct drm_connector *connector = old_conn_state->connector;
4323
4324         if (old_crtc_state->has_audio)
4325                 intel_audio_codec_disable(encoder,
4326                                           old_crtc_state, old_conn_state);
4327
4328         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4329                                                false, false))
4330                 drm_dbg_kms(&i915->drm,
4331                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4332                             connector->base.id, connector->name);
4333 }
4334
4335 static void intel_disable_ddi(struct intel_atomic_state *state,
4336                               struct intel_encoder *encoder,
4337                               const struct intel_crtc_state *old_crtc_state,
4338                               const struct drm_connector_state *old_conn_state)
4339 {
4340         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4341
4342         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4343                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
4344                                        old_conn_state);
4345         else
4346                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
4347                                      old_conn_state);
4348 }
4349
4350 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
4351                                      struct intel_encoder *encoder,
4352                                      const struct intel_crtc_state *crtc_state,
4353                                      const struct drm_connector_state *conn_state)
4354 {
4355         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4356
4357         intel_ddi_set_dp_msa(crtc_state, conn_state);
4358
4359         intel_psr_update(intel_dp, crtc_state, conn_state);
4360         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
4361         intel_edp_drrs_update(intel_dp, crtc_state);
4362
4363         intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
4364 }
4365
4366 void intel_ddi_update_pipe(struct intel_atomic_state *state,
4367                            struct intel_encoder *encoder,
4368                            const struct intel_crtc_state *crtc_state,
4369                            const struct drm_connector_state *conn_state)
4370 {
4371
4372         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
4373             !intel_encoder_is_mst(encoder))
4374                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
4375                                          conn_state);
4376
4377         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
4378 }
4379
4380 static void
4381 intel_ddi_update_prepare(struct intel_atomic_state *state,
4382                          struct intel_encoder *encoder,
4383                          struct intel_crtc *crtc)
4384 {
4385         struct intel_crtc_state *crtc_state =
4386                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4387         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4388
4389         drm_WARN_ON(state->base.dev, crtc && crtc->active);
4390
4391         intel_tc_port_get_link(enc_to_dig_port(encoder),
4392                                required_lanes);
4393         if (crtc_state && crtc_state->hw.active)
4394                 intel_update_active_dpll(state, crtc, encoder);
4395 }
4396
4397 static void
4398 intel_ddi_update_complete(struct intel_atomic_state *state,
4399                           struct intel_encoder *encoder,
4400                           struct intel_crtc *crtc)
4401 {
4402         intel_tc_port_put_link(enc_to_dig_port(encoder));
4403 }
4404
4405 static void
4406 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
4407                          struct intel_encoder *encoder,
4408                          const struct intel_crtc_state *crtc_state,
4409                          const struct drm_connector_state *conn_state)
4410 {
4411         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4412         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4413         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4414         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4415
4416         if (is_tc_port)
4417                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4418
4419         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
4420                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
4421                 dig_port->aux_wakeref =
4422                         intel_display_power_get(dev_priv,
4423                                                 intel_ddi_main_link_aux_domain(dig_port));
4424         }
4425
4426         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4427                 /*
4428                  * Program the lane count for static/dynamic connections on
4429                  * Type-C ports.  Skip this step for TBT.
4430                  */
4431                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4432         else if (IS_GEN9_LP(dev_priv))
4433                 bxt_ddi_phy_set_lane_optim_mask(encoder,
4434                                                 crtc_state->lane_lat_optim_mask);
4435 }
4436
4437 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
4438                                            const struct intel_crtc_state *crtc_state)
4439 {
4440         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4441         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4442         enum port port = encoder->port;
4443         u32 dp_tp_ctl, ddi_buf_ctl;
4444         bool wait = false;
4445
4446         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4447
4448         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4449                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
4450                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4451                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
4452                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4453                         wait = true;
4454                 }
4455
4456                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4457                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4458                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
4459                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4460
4461                 if (wait)
4462                         intel_wait_ddi_buf_idle(dev_priv, port);
4463         }
4464
4465         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
4466         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
4467                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4468         } else {
4469                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4470                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4471                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4472         }
4473         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
4474         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4475
4476         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4477         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
4478         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
4479
4480         intel_wait_ddi_buf_active(dev_priv, port);
4481 }
4482
4483 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
4484                                      const struct intel_crtc_state *crtc_state,
4485                                      u8 dp_train_pat)
4486 {
4487         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4488         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4489         u32 temp;
4490
4491         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4492
4493         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4494         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
4495         case DP_TRAINING_PATTERN_DISABLE:
4496                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
4497                 break;
4498         case DP_TRAINING_PATTERN_1:
4499                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
4500                 break;
4501         case DP_TRAINING_PATTERN_2:
4502                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
4503                 break;
4504         case DP_TRAINING_PATTERN_3:
4505                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
4506                 break;
4507         case DP_TRAINING_PATTERN_4:
4508                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
4509                 break;
4510         }
4511
4512         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
4513 }
4514
4515 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
4516                                           const struct intel_crtc_state *crtc_state)
4517 {
4518         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4519         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4520         enum port port = encoder->port;
4521         u32 val;
4522
4523         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4524         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4525         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4526         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
4527
4528         /*
4529          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4530          * reason we need to set idle transmission mode is to work around a HW
4531          * issue where we enable the pipe while not in idle link-training mode.
4532          * In this case there is requirement to wait for a minimum number of
4533          * idle patterns to be sent.
4534          */
4535         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4536                 return;
4537
4538         if (intel_de_wait_for_set(dev_priv,
4539                                   dp_tp_status_reg(encoder, crtc_state),
4540                                   DP_TP_STATUS_IDLE_DONE, 1))
4541                 drm_err(&dev_priv->drm,
4542                         "Timed out waiting for DP idle patterns\n");
4543 }
4544
4545 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4546                                        enum transcoder cpu_transcoder)
4547 {
4548         if (cpu_transcoder == TRANSCODER_EDP)
4549                 return false;
4550
4551         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4552                 return false;
4553
4554         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
4555                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4556 }
4557
4558 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4559                                          struct intel_crtc_state *crtc_state)
4560 {
4561         if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
4562                 crtc_state->min_voltage_level = 2;
4563         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
4564                 crtc_state->min_voltage_level = 3;
4565         else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4566                 crtc_state->min_voltage_level = 1;
4567         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4568                 crtc_state->min_voltage_level = 2;
4569 }
4570
4571 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
4572                                                      enum transcoder cpu_transcoder)
4573 {
4574         u32 master_select;
4575
4576         if (INTEL_GEN(dev_priv) >= 11) {
4577                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4578
4579                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4580                         return INVALID_TRANSCODER;
4581
4582                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4583         } else {
4584                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4585
4586                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4587                         return INVALID_TRANSCODER;
4588
4589                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4590         }
4591
4592         if (master_select == 0)
4593                 return TRANSCODER_EDP;
4594         else
4595                 return master_select - 1;
4596 }
4597
4598 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4599 {
4600         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4601         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4602                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4603         enum transcoder cpu_transcoder;
4604
4605         crtc_state->master_transcoder =
4606                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4607
4608         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4609                 enum intel_display_power_domain power_domain;
4610                 intel_wakeref_t trans_wakeref;
4611
4612                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4613                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4614                                                                    power_domain);
4615
4616                 if (!trans_wakeref)
4617                         continue;
4618
4619                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4620                     crtc_state->cpu_transcoder)
4621                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4622
4623                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4624         }
4625
4626         drm_WARN_ON(&dev_priv->drm,
4627                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
4628                     crtc_state->sync_mode_slaves_mask);
4629 }
4630
4631 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
4632                                     struct intel_crtc_state *pipe_config)
4633 {
4634         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4635         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4636         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4637         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4638         u32 temp, flags = 0;
4639
4640         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4641         if (temp & TRANS_DDI_PHSYNC)
4642                 flags |= DRM_MODE_FLAG_PHSYNC;
4643         else
4644                 flags |= DRM_MODE_FLAG_NHSYNC;
4645         if (temp & TRANS_DDI_PVSYNC)
4646                 flags |= DRM_MODE_FLAG_PVSYNC;
4647         else
4648                 flags |= DRM_MODE_FLAG_NVSYNC;
4649
4650         pipe_config->hw.adjusted_mode.flags |= flags;
4651
4652         switch (temp & TRANS_DDI_BPC_MASK) {
4653         case TRANS_DDI_BPC_6:
4654                 pipe_config->pipe_bpp = 18;
4655                 break;
4656         case TRANS_DDI_BPC_8:
4657                 pipe_config->pipe_bpp = 24;
4658                 break;
4659         case TRANS_DDI_BPC_10:
4660                 pipe_config->pipe_bpp = 30;
4661                 break;
4662         case TRANS_DDI_BPC_12:
4663                 pipe_config->pipe_bpp = 36;
4664                 break;
4665         default:
4666                 break;
4667         }
4668
4669         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4670         case TRANS_DDI_MODE_SELECT_HDMI:
4671                 pipe_config->has_hdmi_sink = true;
4672
4673                 pipe_config->infoframes.enable |=
4674                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4675
4676                 if (pipe_config->infoframes.enable)
4677                         pipe_config->has_infoframe = true;
4678
4679                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4680                         pipe_config->hdmi_scrambling = true;
4681                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4682                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4683                 fallthrough;
4684         case TRANS_DDI_MODE_SELECT_DVI:
4685                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4686                 pipe_config->lane_count = 4;
4687                 break;
4688         case TRANS_DDI_MODE_SELECT_FDI:
4689                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4690                 break;
4691         case TRANS_DDI_MODE_SELECT_DP_SST:
4692                 if (encoder->type == INTEL_OUTPUT_EDP)
4693                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4694                 else
4695                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4696                 pipe_config->lane_count =
4697                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4698                 intel_dp_get_m_n(intel_crtc, pipe_config);
4699
4700                 if (INTEL_GEN(dev_priv) >= 11) {
4701                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
4702
4703                         pipe_config->fec_enable =
4704                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4705
4706                         drm_dbg_kms(&dev_priv->drm,
4707                                     "[ENCODER:%d:%s] Fec status: %u\n",
4708                                     encoder->base.base.id, encoder->base.name,
4709                                     pipe_config->fec_enable);
4710                 }
4711
4712                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
4713                         pipe_config->infoframes.enable |=
4714                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
4715                 else
4716                         pipe_config->infoframes.enable |=
4717                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4718                 break;
4719         case TRANS_DDI_MODE_SELECT_DP_MST:
4720                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4721                 pipe_config->lane_count =
4722                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4723
4724                 if (INTEL_GEN(dev_priv) >= 12)
4725                         pipe_config->mst_master_transcoder =
4726                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4727
4728                 intel_dp_get_m_n(intel_crtc, pipe_config);
4729
4730                 pipe_config->infoframes.enable |=
4731                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4732                 break;
4733         default:
4734                 break;
4735         }
4736 }
4737
4738 void intel_ddi_get_config(struct intel_encoder *encoder,
4739                           struct intel_crtc_state *pipe_config)
4740 {
4741         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4742         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4743
4744         /* XXX: DSI transcoder paranoia */
4745         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4746                 return;
4747
4748         if (pipe_config->bigjoiner_slave) {
4749                 /* read out pipe settings from master */
4750                 enum transcoder save = pipe_config->cpu_transcoder;
4751
4752                 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
4753                 WARN_ON(pipe_config->output_types);
4754                 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
4755                 intel_ddi_read_func_ctl(encoder, pipe_config);
4756                 pipe_config->cpu_transcoder = save;
4757         } else {
4758                 intel_ddi_read_func_ctl(encoder, pipe_config);
4759         }
4760
4761         pipe_config->has_audio =
4762                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4763
4764         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4765             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4766                 /*
4767                  * This is a big fat ugly hack.
4768                  *
4769                  * Some machines in UEFI boot mode provide us a VBT that has 18
4770                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4771                  * unknown we fail to light up. Yet the same BIOS boots up with
4772                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4773                  * max, not what it tells us to use.
4774                  *
4775                  * Note: This will still be broken if the eDP panel is not lit
4776                  * up by the BIOS, and thus we can't get the mode at module
4777                  * load.
4778                  */
4779                 drm_dbg_kms(&dev_priv->drm,
4780                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4781                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4782                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4783         }
4784
4785         if (!pipe_config->bigjoiner_slave)
4786                 intel_ddi_clock_get(encoder, pipe_config);
4787
4788         if (IS_GEN9_LP(dev_priv))
4789                 pipe_config->lane_lat_optim_mask =
4790                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4791
4792         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4793
4794         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4795
4796         intel_read_infoframe(encoder, pipe_config,
4797                              HDMI_INFOFRAME_TYPE_AVI,
4798                              &pipe_config->infoframes.avi);
4799         intel_read_infoframe(encoder, pipe_config,
4800                              HDMI_INFOFRAME_TYPE_SPD,
4801                              &pipe_config->infoframes.spd);
4802         intel_read_infoframe(encoder, pipe_config,
4803                              HDMI_INFOFRAME_TYPE_VENDOR,
4804                              &pipe_config->infoframes.hdmi);
4805         intel_read_infoframe(encoder, pipe_config,
4806                              HDMI_INFOFRAME_TYPE_DRM,
4807                              &pipe_config->infoframes.drm);
4808
4809         if (INTEL_GEN(dev_priv) >= 8)
4810                 bdw_get_trans_port_sync_config(pipe_config);
4811
4812         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4813         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4814 }
4815
4816 static void intel_ddi_sync_state(struct intel_encoder *encoder,
4817                                  const struct intel_crtc_state *crtc_state)
4818 {
4819         if (intel_crtc_has_dp_encoder(crtc_state))
4820                 intel_dp_sync_state(encoder, crtc_state);
4821 }
4822
4823 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4824                                             struct intel_crtc_state *crtc_state)
4825 {
4826         if (intel_crtc_has_dp_encoder(crtc_state))
4827                 return intel_dp_initial_fastset_check(encoder, crtc_state);
4828
4829         return true;
4830 }
4831
4832 static enum intel_output_type
4833 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4834                               struct intel_crtc_state *crtc_state,
4835                               struct drm_connector_state *conn_state)
4836 {
4837         switch (conn_state->connector->connector_type) {
4838         case DRM_MODE_CONNECTOR_HDMIA:
4839                 return INTEL_OUTPUT_HDMI;
4840         case DRM_MODE_CONNECTOR_eDP:
4841                 return INTEL_OUTPUT_EDP;
4842         case DRM_MODE_CONNECTOR_DisplayPort:
4843                 return INTEL_OUTPUT_DP;
4844         default:
4845                 MISSING_CASE(conn_state->connector->connector_type);
4846                 return INTEL_OUTPUT_UNUSED;
4847         }
4848 }
4849
4850 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4851                                     struct intel_crtc_state *pipe_config,
4852                                     struct drm_connector_state *conn_state)
4853 {
4854         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4855         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4856         enum port port = encoder->port;
4857         int ret;
4858
4859         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4860                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4861
4862         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4863                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4864         } else {
4865                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4866         }
4867
4868         if (ret)
4869                 return ret;
4870
4871         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4872             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4873                 pipe_config->pch_pfit.force_thru =
4874                         pipe_config->pch_pfit.enabled ||
4875                         pipe_config->crc_enabled;
4876
4877         if (IS_GEN9_LP(dev_priv))
4878                 pipe_config->lane_lat_optim_mask =
4879                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4880
4881         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4882
4883         return 0;
4884 }
4885
4886 static bool mode_equal(const struct drm_display_mode *mode1,
4887                        const struct drm_display_mode *mode2)
4888 {
4889         return drm_mode_match(mode1, mode2,
4890                               DRM_MODE_MATCH_TIMINGS |
4891                               DRM_MODE_MATCH_FLAGS |
4892                               DRM_MODE_MATCH_3D_FLAGS) &&
4893                 mode1->clock == mode2->clock; /* we want an exact match */
4894 }
4895
4896 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4897                       const struct intel_link_m_n *m_n_2)
4898 {
4899         return m_n_1->tu == m_n_2->tu &&
4900                 m_n_1->gmch_m == m_n_2->gmch_m &&
4901                 m_n_1->gmch_n == m_n_2->gmch_n &&
4902                 m_n_1->link_m == m_n_2->link_m &&
4903                 m_n_1->link_n == m_n_2->link_n;
4904 }
4905
4906 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4907                                        const struct intel_crtc_state *crtc_state2)
4908 {
4909         return crtc_state1->hw.active && crtc_state2->hw.active &&
4910                 crtc_state1->output_types == crtc_state2->output_types &&
4911                 crtc_state1->output_format == crtc_state2->output_format &&
4912                 crtc_state1->lane_count == crtc_state2->lane_count &&
4913                 crtc_state1->port_clock == crtc_state2->port_clock &&
4914                 mode_equal(&crtc_state1->hw.adjusted_mode,
4915                            &crtc_state2->hw.adjusted_mode) &&
4916                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4917 }
4918
4919 static u8
4920 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4921                                 int tile_group_id)
4922 {
4923         struct drm_connector *connector;
4924         const struct drm_connector_state *conn_state;
4925         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4926         struct intel_atomic_state *state =
4927                 to_intel_atomic_state(ref_crtc_state->uapi.state);
4928         u8 transcoders = 0;
4929         int i;
4930
4931         /*
4932          * We don't enable port sync on BDW due to missing w/as and
4933          * due to not having adjusted the modeset sequence appropriately.
4934          */
4935         if (INTEL_GEN(dev_priv) < 9)
4936                 return 0;
4937
4938         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4939                 return 0;
4940
4941         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4942                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4943                 const struct intel_crtc_state *crtc_state;
4944
4945                 if (!crtc)
4946                         continue;
4947
4948                 if (!connector->has_tile ||
4949                     connector->tile_group->id !=
4950                     tile_group_id)
4951                         continue;
4952                 crtc_state = intel_atomic_get_new_crtc_state(state,
4953                                                              crtc);
4954                 if (!crtcs_port_sync_compatible(ref_crtc_state,
4955                                                 crtc_state))
4956                         continue;
4957                 transcoders |= BIT(crtc_state->cpu_transcoder);
4958         }
4959
4960         return transcoders;
4961 }
4962
4963 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4964                                          struct intel_crtc_state *crtc_state,
4965                                          struct drm_connector_state *conn_state)
4966 {
4967         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4968         struct drm_connector *connector = conn_state->connector;
4969         u8 port_sync_transcoders = 0;
4970
4971         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4972                     encoder->base.base.id, encoder->base.name,
4973                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4974
4975         if (connector->has_tile)
4976                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4977                                                                         connector->tile_group->id);
4978
4979         /*
4980          * EDP Transcoders cannot be ensalved
4981          * make them a master always when present
4982          */
4983         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4984                 crtc_state->master_transcoder = TRANSCODER_EDP;
4985         else
4986                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4987
4988         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4989                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4990                 crtc_state->sync_mode_slaves_mask =
4991                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4992         }
4993
4994         return 0;
4995 }
4996
4997 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4998 {
4999         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5000
5001         intel_dp_encoder_flush_work(encoder);
5002
5003         drm_encoder_cleanup(encoder);
5004         kfree(dig_port);
5005 }
5006
5007 static const struct drm_encoder_funcs intel_ddi_funcs = {
5008         .reset = intel_dp_encoder_reset,
5009         .destroy = intel_ddi_encoder_destroy,
5010 };
5011
5012 static struct intel_connector *
5013 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
5014 {
5015         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
5016         struct intel_connector *connector;
5017         enum port port = dig_port->base.port;
5018
5019         connector = intel_connector_alloc();
5020         if (!connector)
5021                 return NULL;
5022
5023         dig_port->dp.output_reg = DDI_BUF_CTL(port);
5024         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
5025         dig_port->dp.set_link_train = intel_ddi_set_link_train;
5026         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
5027
5028         if (INTEL_GEN(dev_priv) >= 12)
5029                 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
5030         else if (INTEL_GEN(dev_priv) >= 11)
5031                 dig_port->dp.set_signal_levels = icl_set_signal_levels;
5032         else if (IS_CANNONLAKE(dev_priv))
5033                 dig_port->dp.set_signal_levels = cnl_set_signal_levels;
5034         else if (IS_GEN9_LP(dev_priv))
5035                 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
5036         else
5037                 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
5038
5039         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
5040         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
5041
5042         if (!intel_dp_init_connector(dig_port, connector)) {
5043                 kfree(connector);
5044                 return NULL;
5045         }
5046
5047         return connector;
5048 }
5049
5050 static int modeset_pipe(struct drm_crtc *crtc,
5051                         struct drm_modeset_acquire_ctx *ctx)
5052 {
5053         struct drm_atomic_state *state;
5054         struct drm_crtc_state *crtc_state;
5055         int ret;
5056
5057         state = drm_atomic_state_alloc(crtc->dev);
5058         if (!state)
5059                 return -ENOMEM;
5060
5061         state->acquire_ctx = ctx;
5062
5063         crtc_state = drm_atomic_get_crtc_state(state, crtc);
5064         if (IS_ERR(crtc_state)) {
5065                 ret = PTR_ERR(crtc_state);
5066                 goto out;
5067         }
5068
5069         crtc_state->connectors_changed = true;
5070
5071         ret = drm_atomic_commit(state);
5072 out:
5073         drm_atomic_state_put(state);
5074
5075         return ret;
5076 }
5077
5078 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
5079                                  struct drm_modeset_acquire_ctx *ctx)
5080 {
5081         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5082         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
5083         struct intel_connector *connector = hdmi->attached_connector;
5084         struct i2c_adapter *adapter =
5085                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
5086         struct drm_connector_state *conn_state;
5087         struct intel_crtc_state *crtc_state;
5088         struct intel_crtc *crtc;
5089         u8 config;
5090         int ret;
5091
5092         if (!connector || connector->base.status != connector_status_connected)
5093                 return 0;
5094
5095         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5096                                ctx);
5097         if (ret)
5098                 return ret;
5099
5100         conn_state = connector->base.state;
5101
5102         crtc = to_intel_crtc(conn_state->crtc);
5103         if (!crtc)
5104                 return 0;
5105
5106         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5107         if (ret)
5108                 return ret;
5109
5110         crtc_state = to_intel_crtc_state(crtc->base.state);
5111
5112         drm_WARN_ON(&dev_priv->drm,
5113                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
5114
5115         if (!crtc_state->hw.active)
5116                 return 0;
5117
5118         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
5119             !crtc_state->hdmi_scrambling)
5120                 return 0;
5121
5122         if (conn_state->commit &&
5123             !try_wait_for_completion(&conn_state->commit->hw_done))
5124                 return 0;
5125
5126         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
5127         if (ret < 0) {
5128                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
5129                         ret);
5130                 return 0;
5131         }
5132
5133         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
5134             crtc_state->hdmi_high_tmds_clock_ratio &&
5135             !!(config & SCDC_SCRAMBLING_ENABLE) ==
5136             crtc_state->hdmi_scrambling)
5137                 return 0;
5138
5139         /*
5140          * HDMI 2.0 says that one should not send scrambled data
5141          * prior to configuring the sink scrambling, and that
5142          * TMDS clock/data transmission should be suspended when
5143          * changing the TMDS clock rate in the sink. So let's
5144          * just do a full modeset here, even though some sinks
5145          * would be perfectly happy if were to just reconfigure
5146          * the SCDC settings on the fly.
5147          */
5148         return modeset_pipe(&crtc->base, ctx);
5149 }
5150
5151 static enum intel_hotplug_state
5152 intel_ddi_hotplug(struct intel_encoder *encoder,
5153                   struct intel_connector *connector)
5154 {
5155         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5156         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5157         enum phy phy = intel_port_to_phy(i915, encoder->port);
5158         bool is_tc = intel_phy_is_tc(i915, phy);
5159         struct drm_modeset_acquire_ctx ctx;
5160         enum intel_hotplug_state state;
5161         int ret;
5162
5163         state = intel_encoder_hotplug(encoder, connector);
5164
5165         drm_modeset_acquire_init(&ctx, 0);
5166
5167         for (;;) {
5168                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
5169                         ret = intel_hdmi_reset_link(encoder, &ctx);
5170                 else
5171                         ret = intel_dp_retrain_link(encoder, &ctx);
5172
5173                 if (ret == -EDEADLK) {
5174                         drm_modeset_backoff(&ctx);
5175                         continue;
5176                 }
5177
5178                 break;
5179         }
5180
5181         drm_modeset_drop_locks(&ctx);
5182         drm_modeset_acquire_fini(&ctx);
5183         drm_WARN(encoder->base.dev, ret,
5184                  "Acquiring modeset locks failed with %i\n", ret);
5185
5186         /*
5187          * Unpowered type-c dongles can take some time to boot and be
5188          * responsible, so here giving some time to those dongles to power up
5189          * and then retrying the probe.
5190          *
5191          * On many platforms the HDMI live state signal is known to be
5192          * unreliable, so we can't use it to detect if a sink is connected or
5193          * not. Instead we detect if it's connected based on whether we can
5194          * read the EDID or not. That in turn has a problem during disconnect,
5195          * since the HPD interrupt may be raised before the DDC lines get
5196          * disconnected (due to how the required length of DDC vs. HPD
5197          * connector pins are specified) and so we'll still be able to get a
5198          * valid EDID. To solve this schedule another detection cycle if this
5199          * time around we didn't detect any change in the sink's connection
5200          * status.
5201          *
5202          * Type-c connectors which get their HPD signal deasserted then
5203          * reasserted, without unplugging/replugging the sink from the
5204          * connector, introduce a delay until the AUX channel communication
5205          * becomes functional. Retry the detection for 5 seconds on type-c
5206          * connectors to account for this delay.
5207          */
5208         if (state == INTEL_HOTPLUG_UNCHANGED &&
5209             connector->hotplug_retries < (is_tc ? 5 : 1) &&
5210             !dig_port->dp.is_mst)
5211                 state = INTEL_HOTPLUG_RETRY;
5212
5213         return state;
5214 }
5215
5216 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
5217 {
5218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5219         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
5220
5221         return intel_de_read(dev_priv, SDEISR) & bit;
5222 }
5223
5224 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
5225 {
5226         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5227         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
5228
5229         return intel_de_read(dev_priv, DEISR) & bit;
5230 }
5231
5232 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5233 {
5234         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5235         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
5236
5237         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
5238 }
5239
5240 static struct intel_connector *
5241 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
5242 {
5243         struct intel_connector *connector;
5244         enum port port = dig_port->base.port;
5245
5246         connector = intel_connector_alloc();
5247         if (!connector)
5248                 return NULL;
5249
5250         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
5251         intel_hdmi_init_connector(dig_port, connector);
5252
5253         return connector;
5254 }
5255
5256 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
5257 {
5258         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
5259
5260         if (dig_port->base.port != PORT_A)
5261                 return false;
5262
5263         if (dig_port->saved_port_bits & DDI_A_4_LANES)
5264                 return false;
5265
5266         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
5267          *                     supported configuration
5268          */
5269         if (IS_GEN9_LP(dev_priv))
5270                 return true;
5271
5272         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
5273          *             one who does also have a full A/E split called
5274          *             DDI_F what makes DDI_E useless. However for this
5275          *             case let's trust VBT info.
5276          */
5277         if (IS_CANNONLAKE(dev_priv) &&
5278             !intel_bios_is_port_present(dev_priv, PORT_E))
5279                 return true;
5280
5281         return false;
5282 }
5283
5284 static int
5285 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
5286 {
5287         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
5288         enum port port = dig_port->base.port;
5289         int max_lanes = 4;
5290
5291         if (INTEL_GEN(dev_priv) >= 11)
5292                 return max_lanes;
5293
5294         if (port == PORT_A || port == PORT_E) {
5295                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
5296                         max_lanes = port == PORT_A ? 4 : 0;
5297                 else
5298                         /* Both A and E share 2 lanes */
5299                         max_lanes = 2;
5300         }
5301
5302         /*
5303          * Some BIOS might fail to set this bit on port A if eDP
5304          * wasn't lit up at boot.  Force this bit set when needed
5305          * so we use the proper lane count for our calculations.
5306          */
5307         if (intel_ddi_a_force_4_lanes(dig_port)) {
5308                 drm_dbg_kms(&dev_priv->drm,
5309                             "Forcing DDI_A_4_LANES for port A\n");
5310                 dig_port->saved_port_bits |= DDI_A_4_LANES;
5311                 max_lanes = 4;
5312         }
5313
5314         return max_lanes;
5315 }
5316
5317 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
5318 {
5319         return i915->hti_state & HDPORT_ENABLED &&
5320                 (i915->hti_state & HDPORT_PHY_USED_DP(phy) ||
5321                  i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
5322 }
5323
5324 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
5325                                 enum port port)
5326 {
5327         if (port >= PORT_TC1)
5328                 return HPD_PORT_C + port - PORT_TC1;
5329         else
5330                 return HPD_PORT_A + port - PORT_A;
5331 }
5332
5333 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
5334                                 enum port port)
5335 {
5336         if (port >= PORT_TC1)
5337                 return HPD_PORT_TC1 + port - PORT_TC1;
5338         else
5339                 return HPD_PORT_A + port - PORT_A;
5340 }
5341
5342 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
5343                                 enum port port)
5344 {
5345         if (HAS_PCH_TGP(dev_priv))
5346                 return tgl_hpd_pin(dev_priv, port);
5347
5348         if (port >= PORT_TC1)
5349                 return HPD_PORT_C + port - PORT_TC1;
5350         else
5351                 return HPD_PORT_A + port - PORT_A;
5352 }
5353
5354 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
5355                                 enum port port)
5356 {
5357         if (port >= PORT_C)
5358                 return HPD_PORT_TC1 + port - PORT_C;
5359         else
5360                 return HPD_PORT_A + port - PORT_A;
5361 }
5362
5363 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
5364                                 enum port port)
5365 {
5366         if (port == PORT_D)
5367                 return HPD_PORT_A;
5368
5369         if (HAS_PCH_MCC(dev_priv))
5370                 return icl_hpd_pin(dev_priv, port);
5371
5372         return HPD_PORT_A + port - PORT_A;
5373 }
5374
5375 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
5376                                 enum port port)
5377 {
5378         if (port == PORT_F)
5379                 return HPD_PORT_E;
5380
5381         return HPD_PORT_A + port - PORT_A;
5382 }
5383
5384 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
5385 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5386
5387 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
5388 {
5389         struct intel_digital_port *dig_port;
5390         struct intel_encoder *encoder;
5391         bool init_hdmi, init_dp;
5392         enum phy phy = intel_port_to_phy(dev_priv, port);
5393
5394         /*
5395          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
5396          * have taken over some of the PHYs and made them unavailable to the
5397          * driver.  In that case we should skip initializing the corresponding
5398          * outputs.
5399          */
5400         if (hti_uses_phy(dev_priv, phy)) {
5401                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
5402                             port_name(port), phy_name(phy));
5403                 return;
5404         }
5405
5406         init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
5407                 intel_bios_port_supports_hdmi(dev_priv, port);
5408         init_dp = intel_bios_port_supports_dp(dev_priv, port);
5409
5410         if (intel_bios_is_lspcon_present(dev_priv, port)) {
5411                 /*
5412                  * Lspcon device needs to be driven with DP connector
5413                  * with special detection sequence. So make sure DP
5414                  * is initialized before lspcon.
5415                  */
5416                 init_dp = true;
5417                 init_hdmi = false;
5418                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
5419                             port_name(port));
5420         }
5421
5422         if (!init_dp && !init_hdmi) {
5423                 drm_dbg_kms(&dev_priv->drm,
5424                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
5425                             port_name(port));
5426                 return;
5427         }
5428
5429         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
5430         if (!dig_port)
5431                 return;
5432
5433         encoder = &dig_port->base;
5434
5435         if (INTEL_GEN(dev_priv) >= 12) {
5436                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5437
5438                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5439                                  DRM_MODE_ENCODER_TMDS,
5440                                  "DDI %s%c/PHY %s%c",
5441                                  port >= PORT_TC1 ? "TC" : "",
5442                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
5443                                  tc_port != TC_PORT_NONE ? "TC" : "",
5444                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5445         } else if (INTEL_GEN(dev_priv) >= 11) {
5446                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5447
5448                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5449                                  DRM_MODE_ENCODER_TMDS,
5450                                  "DDI %c%s/PHY %s%c",
5451                                  port_name(port),
5452                                  port >= PORT_C ? " (TC)" : "",
5453                                  tc_port != TC_PORT_NONE ? "TC" : "",
5454                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5455         } else {
5456                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5457                                  DRM_MODE_ENCODER_TMDS,
5458                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
5459         }
5460
5461         mutex_init(&dig_port->hdcp_mutex);
5462         dig_port->num_hdcp_streams = 0;
5463
5464         encoder->hotplug = intel_ddi_hotplug;
5465         encoder->compute_output_type = intel_ddi_compute_output_type;
5466         encoder->compute_config = intel_ddi_compute_config;
5467         encoder->compute_config_late = intel_ddi_compute_config_late;
5468         encoder->enable = intel_enable_ddi;
5469         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5470         encoder->pre_enable = intel_ddi_pre_enable;
5471         encoder->disable = intel_disable_ddi;
5472         encoder->post_disable = intel_ddi_post_disable;
5473         encoder->update_pipe = intel_ddi_update_pipe;
5474         encoder->get_hw_state = intel_ddi_get_hw_state;
5475         encoder->get_config = intel_ddi_get_config;
5476         encoder->sync_state = intel_ddi_sync_state;
5477         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
5478         encoder->suspend = intel_dp_encoder_suspend;
5479         encoder->shutdown = intel_dp_encoder_shutdown;
5480         encoder->get_power_domains = intel_ddi_get_power_domains;
5481
5482         encoder->type = INTEL_OUTPUT_DDI;
5483         encoder->power_domain = intel_port_to_power_domain(port);
5484         encoder->port = port;
5485         encoder->cloneable = 0;
5486         encoder->pipe_mask = ~0;
5487
5488         if (IS_DG1(dev_priv))
5489                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
5490         else if (IS_ROCKETLAKE(dev_priv))
5491                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
5492         else if (INTEL_GEN(dev_priv) >= 12)
5493                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
5494         else if (IS_JSL_EHL(dev_priv))
5495                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
5496         else if (IS_GEN(dev_priv, 11))
5497                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
5498         else if (IS_GEN(dev_priv, 10))
5499                 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
5500         else
5501                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
5502
5503         if (INTEL_GEN(dev_priv) >= 11)
5504                 dig_port->saved_port_bits =
5505                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
5506                         & DDI_BUF_PORT_REVERSAL;
5507         else
5508                 dig_port->saved_port_bits =
5509                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
5510                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
5511
5512         dig_port->dp.output_reg = INVALID_MMIO_REG;
5513         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5514         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
5515
5516         if (intel_phy_is_tc(dev_priv, phy)) {
5517                 bool is_legacy =
5518                         !intel_bios_port_supports_typec_usb(dev_priv, port) &&
5519                         !intel_bios_port_supports_tbt(dev_priv, port);
5520
5521                 intel_tc_port_init(dig_port, is_legacy);
5522
5523                 encoder->update_prepare = intel_ddi_update_prepare;
5524                 encoder->update_complete = intel_ddi_update_complete;
5525         }
5526
5527         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5528         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
5529                                               port - PORT_A;
5530
5531         if (init_dp) {
5532                 if (!intel_ddi_init_dp_connector(dig_port))
5533                         goto err;
5534
5535                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5536         }
5537
5538         /* In theory we don't need the encoder->type check, but leave it just in
5539          * case we have some really bad VBTs... */
5540         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5541                 if (!intel_ddi_init_hdmi_connector(dig_port))
5542                         goto err;
5543         }
5544
5545         if (INTEL_GEN(dev_priv) >= 11) {
5546                 if (intel_phy_is_tc(dev_priv, phy))
5547                         dig_port->connected = intel_tc_port_connected;
5548                 else
5549                         dig_port->connected = lpt_digital_port_connected;
5550         } else if (INTEL_GEN(dev_priv) >= 8) {
5551                 if (port == PORT_A || IS_GEN9_LP(dev_priv))
5552                         dig_port->connected = bdw_digital_port_connected;
5553                 else
5554                         dig_port->connected = lpt_digital_port_connected;
5555         } else {
5556                 if (port == PORT_A)
5557                         dig_port->connected = hsw_digital_port_connected;
5558                 else
5559                         dig_port->connected = lpt_digital_port_connected;
5560         }
5561
5562         intel_infoframe_init(dig_port);
5563
5564         return;
5565
5566 err:
5567         drm_encoder_cleanup(&encoder->base);
5568         kfree(dig_port);
5569 }