drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_mst.h"
  38 #include "intel_dp_link_training.h"
  39 #include "intel_dpio_phy.h"
  40 #include "intel_dsi.h"
  41 #include "intel_fifo_underrun.h"
  42 #include "intel_gmbus.h"
  43 #include "intel_hdcp.h"
  44 #include "intel_hdmi.h"
  45 #include "intel_hotplug.h"
  46 #include "intel_lspcon.h"
  47 #include "intel_panel.h"
  48 #include "intel_psr.h"
  49 #include "intel_sprite.h"
  50 #include "intel_tc.h"
  51 #include "intel_vdsc.h"
  52
  53 struct ddi_buf_trans {
  54         u32 trans1;     /* balance leg enable, de-emph level */
  55         u32 trans2;     /* vref sel, vswing */
  56         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  57 };
  58
  59 static const u8 index_to_dp_signal_levels[] = {
  60         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  61         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  62         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  63         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  64         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  69         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  70 };
  71
  72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  73  * them for both DP and FDI transports, allowing those ports to
  74  * automatically adapt to HDMI connections as well
  75  */
  76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  77         { 0x00FFFFFF, 0x0006000E, 0x0 },
  78         { 0x00D75FFF, 0x0005000A, 0x0 },
  79         { 0x00C30FFF, 0x00040006, 0x0 },
  80         { 0x80AAAFFF, 0x000B0000, 0x0 },
  81         { 0x00FFFFFF, 0x0005000A, 0x0 },
  82         { 0x00D75FFF, 0x000C0004, 0x0 },
  83         { 0x80C30FFF, 0x000B0000, 0x0 },
  84         { 0x00FFFFFF, 0x00040006, 0x0 },
  85         { 0x80D75FFF, 0x000B0000, 0x0 },
  86 };
  87
  88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  89         { 0x00FFFFFF, 0x0007000E, 0x0 },
  90         { 0x00D75FFF, 0x000F000A, 0x0 },
  91         { 0x00C30FFF, 0x00060006, 0x0 },
  92         { 0x00AAAFFF, 0x001E0000, 0x0 },
  93         { 0x00FFFFFF, 0x000F000A, 0x0 },
  94         { 0x00D75FFF, 0x00160004, 0x0 },
  95         { 0x00C30FFF, 0x001E0000, 0x0 },
  96         { 0x00FFFFFF, 0x00060006, 0x0 },
  97         { 0x00D75FFF, 0x001E0000, 0x0 },
  98 };
  99
 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 101                                         /* Idx  NT mV d T mV d  db      */
 102         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 103         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 104         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 105         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 106         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 107         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 108         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 109         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 110         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 111         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 112         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 113         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 117         { 0x00FFFFFF, 0x00000012, 0x0 },
 118         { 0x00EBAFFF, 0x00020011, 0x0 },
 119         { 0x00C71FFF, 0x0006000F, 0x0 },
 120         { 0x00AAAFFF, 0x000E000A, 0x0 },
 121         { 0x00FFFFFF, 0x00020011, 0x0 },
 122         { 0x00DB6FFF, 0x0005000F, 0x0 },
 123         { 0x00BEEFFF, 0x000A000C, 0x0 },
 124         { 0x00FFFFFF, 0x0005000F, 0x0 },
 125         { 0x00DB6FFF, 0x000A000C, 0x0 },
 126 };
 127
 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 129         { 0x00FFFFFF, 0x0007000E, 0x0 },
 130         { 0x00D75FFF, 0x000E000A, 0x0 },
 131         { 0x00BEFFFF, 0x00140006, 0x0 },
 132         { 0x80B2CFFF, 0x001B0002, 0x0 },
 133         { 0x00FFFFFF, 0x000E000A, 0x0 },
 134         { 0x00DB6FFF, 0x00160005, 0x0 },
 135         { 0x80C71FFF, 0x001A0002, 0x0 },
 136         { 0x00F7DFFF, 0x00180004, 0x0 },
 137         { 0x80D75FFF, 0x001B0002, 0x0 },
 138 };
 139
 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 141         { 0x00FFFFFF, 0x0001000E, 0x0 },
 142         { 0x00D75FFF, 0x0004000A, 0x0 },
 143         { 0x00C30FFF, 0x00070006, 0x0 },
 144         { 0x00AAAFFF, 0x000C0000, 0x0 },
 145         { 0x00FFFFFF, 0x0004000A, 0x0 },
 146         { 0x00D75FFF, 0x00090004, 0x0 },
 147         { 0x00C30FFF, 0x000C0000, 0x0 },
 148         { 0x00FFFFFF, 0x00070006, 0x0 },
 149         { 0x00D75FFF, 0x000C0000, 0x0 },
 150 };
 151
 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 153                                         /* Idx  NT mV d T mV df db      */
 154         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 155         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 156         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 157         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 158         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 159         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 160         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 161         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 162         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 163         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 164 };
 165
 166 /* Skylake H and S */
 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 168         { 0x00002016, 0x000000A0, 0x0 },
 169         { 0x00005012, 0x0000009B, 0x0 },
 170         { 0x00007011, 0x00000088, 0x0 },
 171         { 0x80009010, 0x000000C0, 0x1 },
 172         { 0x00002016, 0x0000009B, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000C0, 0x1 },
 175         { 0x00002016, 0x000000DF, 0x0 },
 176         { 0x80005012, 0x000000C0, 0x1 },
 177 };
 178
 179 /* Skylake U */
 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 181         { 0x0000201B, 0x000000A2, 0x0 },
 182         { 0x00005012, 0x00000088, 0x0 },
 183         { 0x80007011, 0x000000CD, 0x1 },
 184         { 0x80009010, 0x000000C0, 0x1 },
 185         { 0x0000201B, 0x0000009D, 0x0 },
 186         { 0x80005012, 0x000000C0, 0x1 },
 187         { 0x80007011, 0x000000C0, 0x1 },
 188         { 0x00002016, 0x00000088, 0x0 },
 189         { 0x80005012, 0x000000C0, 0x1 },
 190 };
 191
 192 /* Skylake Y */
 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 194         { 0x00000018, 0x000000A2, 0x0 },
 195         { 0x00005012, 0x00000088, 0x0 },
 196         { 0x80007011, 0x000000CD, 0x3 },
 197         { 0x80009010, 0x000000C0, 0x3 },
 198         { 0x00000018, 0x0000009D, 0x0 },
 199         { 0x80005012, 0x000000C0, 0x3 },
 200         { 0x80007011, 0x000000C0, 0x3 },
 201         { 0x00000018, 0x00000088, 0x0 },
 202         { 0x80005012, 0x000000C0, 0x3 },
 203 };
 204
 205 /* Kabylake H and S */
 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 207         { 0x00002016, 0x000000A0, 0x0 },
 208         { 0x00005012, 0x0000009B, 0x0 },
 209         { 0x00007011, 0x00000088, 0x0 },
 210         { 0x80009010, 0x000000C0, 0x1 },
 211         { 0x00002016, 0x0000009B, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000C0, 0x1 },
 214         { 0x00002016, 0x00000097, 0x0 },
 215         { 0x80005012, 0x000000C0, 0x1 },
 216 };
 217
 218 /* Kabylake U */
 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 220         { 0x0000201B, 0x000000A1, 0x0 },
 221         { 0x00005012, 0x00000088, 0x0 },
 222         { 0x80007011, 0x000000CD, 0x3 },
 223         { 0x80009010, 0x000000C0, 0x3 },
 224         { 0x0000201B, 0x0000009D, 0x0 },
 225         { 0x80005012, 0x000000C0, 0x3 },
 226         { 0x80007011, 0x000000C0, 0x3 },
 227         { 0x00002016, 0x0000004F, 0x0 },
 228         { 0x80005012, 0x000000C0, 0x3 },
 229 };
 230
 231 /* Kabylake Y */
 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 233         { 0x00001017, 0x000000A1, 0x0 },
 234         { 0x00005012, 0x00000088, 0x0 },
 235         { 0x80007011, 0x000000CD, 0x3 },
 236         { 0x8000800F, 0x000000C0, 0x3 },
 237         { 0x00001017, 0x0000009D, 0x0 },
 238         { 0x80005012, 0x000000C0, 0x3 },
 239         { 0x80007011, 0x000000C0, 0x3 },
 240         { 0x00001017, 0x0000004C, 0x0 },
 241         { 0x80005012, 0x000000C0, 0x3 },
 242 };
 243
 244 /*
 245  * Skylake/Kabylake H and S
 246  * eDP 1.4 low vswing translation parameters
 247  */
 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 249         { 0x00000018, 0x000000A8, 0x0 },
 250         { 0x00004013, 0x000000A9, 0x0 },
 251         { 0x00007011, 0x000000A2, 0x0 },
 252         { 0x00009010, 0x0000009C, 0x0 },
 253         { 0x00000018, 0x000000A9, 0x0 },
 254         { 0x00006013, 0x000000A2, 0x0 },
 255         { 0x00007011, 0x000000A6, 0x0 },
 256         { 0x00000018, 0x000000AB, 0x0 },
 257         { 0x00007013, 0x0000009F, 0x0 },
 258         { 0x00000018, 0x000000DF, 0x0 },
 259 };
 260
 261 /*
 262  * Skylake/Kabylake U
 263  * eDP 1.4 low vswing translation parameters
 264  */
 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 266         { 0x00000018, 0x000000A8, 0x0 },
 267         { 0x00004013, 0x000000A9, 0x0 },
 268         { 0x00007011, 0x000000A2, 0x0 },
 269         { 0x00009010, 0x0000009C, 0x0 },
 270         { 0x00000018, 0x000000A9, 0x0 },
 271         { 0x00006013, 0x000000A2, 0x0 },
 272         { 0x00007011, 0x000000A6, 0x0 },
 273         { 0x00002016, 0x000000AB, 0x0 },
 274         { 0x00005013, 0x0000009F, 0x0 },
 275         { 0x00000018, 0x000000DF, 0x0 },
 276 };
 277
 278 /*
 279  * Skylake/Kabylake Y
 280  * eDP 1.4 low vswing translation parameters
 281  */
 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 283         { 0x00000018, 0x000000A8, 0x0 },
 284         { 0x00004013, 0x000000AB, 0x0 },
 285         { 0x00007011, 0x000000A4, 0x0 },
 286         { 0x00009010, 0x000000DF, 0x0 },
 287         { 0x00000018, 0x000000AA, 0x0 },
 288         { 0x00006013, 0x000000A4, 0x0 },
 289         { 0x00007011, 0x0000009D, 0x0 },
 290         { 0x00000018, 0x000000A0, 0x0 },
 291         { 0x00006012, 0x000000DF, 0x0 },
 292         { 0x00000018, 0x0000008A, 0x0 },
 293 };
 294
 295 /* Skylake/Kabylake U, H and S */
 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 297         { 0x00000018, 0x000000AC, 0x0 },
 298         { 0x00005012, 0x0000009D, 0x0 },
 299         { 0x00007011, 0x00000088, 0x0 },
 300         { 0x00000018, 0x000000A1, 0x0 },
 301         { 0x00000018, 0x00000098, 0x0 },
 302         { 0x00004013, 0x00000088, 0x0 },
 303         { 0x80006012, 0x000000CD, 0x1 },
 304         { 0x00000018, 0x000000DF, 0x0 },
 305         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 306         { 0x80003015, 0x000000C0, 0x1 },
 307         { 0x80000018, 0x000000C0, 0x1 },
 308 };
 309
 310 /* Skylake/Kabylake Y */
 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 312         { 0x00000018, 0x000000A1, 0x0 },
 313         { 0x00005012, 0x000000DF, 0x0 },
 314         { 0x80007011, 0x000000CB, 0x3 },
 315         { 0x00000018, 0x000000A4, 0x0 },
 316         { 0x00000018, 0x0000009D, 0x0 },
 317         { 0x00004013, 0x00000080, 0x0 },
 318         { 0x80006013, 0x000000C0, 0x3 },
 319         { 0x00000018, 0x0000008A, 0x0 },
 320         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 321         { 0x80003015, 0x000000C0, 0x3 },
 322         { 0x80000018, 0x000000C0, 0x3 },
 323 };
 324
 325 struct bxt_ddi_buf_trans {
 326         u8 margin;      /* swing value */
 327         u8 scale;       /* scale value */
 328         u8 enable;      /* scale enable */
 329         u8 deemphasis;
 330 };
 331
 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 333                                         /* Idx  NT mV diff      db  */
 334         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 335         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 336         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 337         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 338         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 339         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 340         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 341         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 342         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 343         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 344 };
 345
 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 347                                         /* Idx  NT mV diff      db  */
 348         { 26, 0, 0, 128, },     /* 0:   200             0   */
 349         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 350         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 351         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 352         { 32, 0, 0, 128, },     /* 4:   250             0   */
 353         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 354         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 355         { 43, 0, 0, 128, },     /* 7:   300             0   */
 356         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 357         { 48, 0, 0, 128, },     /* 9:   300             0   */
 358 };
 359
 360 /* BSpec has 2 recommended values - entries 0 and 8.
 361  * Using the entry with higher vswing.
 362  */
 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 364                                         /* Idx  NT mV diff      db  */
 365         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 366         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 367         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 368         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 369         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 370         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 371         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 372         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 373         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 374         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 375 };
 376
 377 struct cnl_ddi_buf_trans {
 378         u8 dw2_swing_sel;
 379         u8 dw7_n_scalar;
 380         u8 dw4_cursor_coeff;
 381         u8 dw4_post_cursor_2;
 382         u8 dw4_post_cursor_1;
 383 };
 384
 385 /* Voltage Swing Programming for VccIO 0.85V for DP */
 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 387                                                 /* NT mV Trans mV db    */
 388         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 389         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 390         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 391         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 392         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 393         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 394         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 395         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 396         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 397         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 398 };
 399
 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 402                                                 /* NT mV Trans mV db    */
 403         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 404         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 405         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 406         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 407         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 408         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 409         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 410 };
 411
 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 414                                                 /* NT mV Trans mV db    */
 415         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 416         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 417         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 418         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 419         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 420         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 421         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 422         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 423         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424 };
 425
 426 /* Voltage Swing Programming for VccIO 0.95V for DP */
 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 428                                                 /* NT mV Trans mV db    */
 429         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 430         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 431         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 432         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 433         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 434         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 435         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 436         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 437         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 438         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 439 };
 440
 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 443                                                 /* NT mV Trans mV db    */
 444         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 445         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 446         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 447         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 448         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 449         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 450         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 451         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 452         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 453         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 454         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 455 };
 456
 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 459                                                 /* NT mV Trans mV db    */
 460         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 461         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 462         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 463         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 464         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 465         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 466         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 467         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 468         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 469         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470 };
 471
 472 /* Voltage Swing Programming for VccIO 1.05V for DP */
 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 474                                                 /* NT mV Trans mV db    */
 475         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 476         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 477         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 478         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 479         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 480         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 481         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 482         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 483         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 484         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 485 };
 486
 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 489                                                 /* NT mV Trans mV db    */
 490         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 491         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 492         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 493         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 494         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 495         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 496         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 497         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 498         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 499         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 500         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 501 };
 502
 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 505                                                 /* NT mV Trans mV db    */
 506         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 507         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 508         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 509         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 510         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 511         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 512         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 513         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 514         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 515 };
 516
 517 /* icl_combo_phy_ddi_translations */
 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 519                                                 /* NT mV Trans mV db    */
 520         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 521         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 522         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 523         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 524         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 525         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 526         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 527         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 528         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 529         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 530 };
 531
 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 533                                                 /* NT mV Trans mV db    */
 534         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 535         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 536         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 537         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 538         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 539         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 540         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 541         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 542         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 543         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 544 };
 545
 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 547                                                 /* NT mV Trans mV db    */
 548         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 549         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 550         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 551         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 552         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 553         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 554         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 555         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 556         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 557         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 558 };
 559
 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 561                                                 /* NT mV Trans mV db    */
 562         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 563         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 564         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 565         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 566         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 567         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 568         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 569 };
 570
 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_hbr2_hbr3[] = {
 572                                                 /* NT mV Trans mV db    */
 573         { 0xA, 0x33, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 574         { 0xA, 0x47, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 575         { 0xC, 0x64, 0x30, 0x00, 0x0F },        /* 350   700      6.0   */
 576         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 350   900      8.2   */
 577         { 0xA, 0x46, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 578         { 0xC, 0x64, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 579         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 580         { 0xC, 0x61, 0x3F, 0x00, 0x00 },        /* 650   700      0.6   */
 581         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 600   900      3.5   */
 582         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 583 };
 584
 585 struct icl_mg_phy_ddi_buf_trans {
 586         u32 cri_txdeemph_override_5_0;
 587         u32 cri_txdeemph_override_11_6;
 588         u32 cri_txdeemph_override_17_12;
 589 };
 590
 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 592                                 /* Voltage swing  pre-emphasis */
 593         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 594         { 0x0, 0x23, 0x08 },    /* 0              1   */
 595         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 596         { 0x0, 0x00, 0x00 },    /* 0              3   */
 597         { 0x0, 0x23, 0x00 },    /* 1              0   */
 598         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 599         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 600         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 601         { 0x0, 0x33, 0x0C },    /* 2              1   */
 602         { 0x0, 0x00, 0x00 },    /* 3              0   */
 603 };
 604
 605 struct tgl_dkl_phy_ddi_buf_trans {
 606         u32 dkl_vswing_control;
 607         u32 dkl_preshoot_control;
 608         u32 dkl_de_emphasis_control;
 609 };
 610
 611 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
 612                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 613         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 614         { 0x5, 0x0, 0x03 },     /* 0    1       400mV           3.5 dB */
 615         { 0x2, 0x0, 0x0b },     /* 0    2       400mV           6 dB */
 616         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 617         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 618         { 0x2, 0x0, 0x03 },     /* 1    1       600mV           3.5 dB */
 619         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 620         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 621         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 622         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 623 };
 624
 625 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
 626                                 /* HDMI Preset  VS      Pre-emph */
 627         { 0x7, 0x0, 0x0 },      /* 1            400mV   0dB */
 628         { 0x6, 0x0, 0x0 },      /* 2            500mV   0dB */
 629         { 0x4, 0x0, 0x0 },      /* 3            650mV   0dB */
 630         { 0x2, 0x0, 0x0 },      /* 4            800mV   0dB */
 631         { 0x0, 0x0, 0x0 },      /* 5            1000mV  0dB */
 632         { 0x0, 0x0, 0x5 },      /* 6            Full    -1.5 dB */
 633         { 0x0, 0x0, 0x6 },      /* 7            Full    -1.8 dB */
 634         { 0x0, 0x0, 0x7 },      /* 8            Full    -2 dB */
 635         { 0x0, 0x0, 0x8 },      /* 9            Full    -2.5 dB */
 636         { 0x0, 0x0, 0xA },      /* 10           Full    -3 dB */
 637 };
 638
 639 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
 640                                                 /* NT mV Trans mV db    */
 641         { 0xA, 0x32, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 642         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 643         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 644         { 0x6, 0x7D, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 645         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 646         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 647         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 648         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 649         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 650         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 651 };
 652
 653 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
 654                                                 /* NT mV Trans mV db    */
 655         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 656         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 657         { 0xC, 0x63, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 658         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 659         { 0xA, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 660         { 0xC, 0x63, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 661         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 662         { 0xC, 0x61, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 663         { 0x6, 0x7B, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 664         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 665 };
 666
 667 static const struct ddi_buf_trans *
 668 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 669 {
 670         if (dev_priv->vbt.edp.low_vswing) {
 671                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 672                 return bdw_ddi_translations_edp;
 673         } else {
 674                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 675                 return bdw_ddi_translations_dp;
 676         }
 677 }
 678
 679 static const struct ddi_buf_trans *
 680 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 681 {
 682         if (IS_SKL_ULX(dev_priv)) {
 683                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 684                 return skl_y_ddi_translations_dp;
 685         } else if (IS_SKL_ULT(dev_priv)) {
 686                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 687                 return skl_u_ddi_translations_dp;
 688         } else {
 689                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 690                 return skl_ddi_translations_dp;
 691         }
 692 }
 693
 694 static const struct ddi_buf_trans *
 695 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 696 {
 697         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 698                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 699                 return kbl_y_ddi_translations_dp;
 700         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 701                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 702                 return kbl_u_ddi_translations_dp;
 703         } else {
 704                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 705                 return kbl_ddi_translations_dp;
 706         }
 707 }
 708
 709 static const struct ddi_buf_trans *
 710 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 711 {
 712         if (dev_priv->vbt.edp.low_vswing) {
 713                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 714                     IS_CFL_ULX(dev_priv)) {
 715                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 716                         return skl_y_ddi_translations_edp;
 717                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 718                            IS_CFL_ULT(dev_priv)) {
 719                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 720                         return skl_u_ddi_translations_edp;
 721                 } else {
 722                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 723                         return skl_ddi_translations_edp;
 724                 }
 725         }
 726
 727         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 728                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 729         else
 730                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 731 }
 732
 733 static const struct ddi_buf_trans *
 734 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 735 {
 736         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 737             IS_CFL_ULX(dev_priv)) {
 738                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 739                 return skl_y_ddi_translations_hdmi;
 740         } else {
 741                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 742                 return skl_ddi_translations_hdmi;
 743         }
 744 }
 745
 746 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 747 {
 748         /* Only DDIA and DDIE can select the 10th register with DP */
 749         if (port == PORT_A || port == PORT_E)
 750                 return min(n_entries, 10);
 751         else
 752                 return min(n_entries, 9);
 753 }
 754
 755 static const struct ddi_buf_trans *
 756 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 757                            enum port port, int *n_entries)
 758 {
 759         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 760                 const struct ddi_buf_trans *ddi_translations =
 761                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 762                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 763                 return ddi_translations;
 764         } else if (IS_SKYLAKE(dev_priv)) {
 765                 const struct ddi_buf_trans *ddi_translations =
 766                         skl_get_buf_trans_dp(dev_priv, n_entries);
 767                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 768                 return ddi_translations;
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 771                 return  bdw_ddi_translations_dp;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 774                 return hsw_ddi_translations_dp;
 775         }
 776
 777         *n_entries = 0;
 778         return NULL;
 779 }
 780
 781 static const struct ddi_buf_trans *
 782 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 783                             enum port port, int *n_entries)
 784 {
 785         if (IS_GEN9_BC(dev_priv)) {
 786                 const struct ddi_buf_trans *ddi_translations =
 787                         skl_get_buf_trans_edp(dev_priv, n_entries);
 788                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 789                 return ddi_translations;
 790         } else if (IS_BROADWELL(dev_priv)) {
 791                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 792         } else if (IS_HASWELL(dev_priv)) {
 793                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 794                 return hsw_ddi_translations_dp;
 795         }
 796
 797         *n_entries = 0;
 798         return NULL;
 799 }
 800
 801 static const struct ddi_buf_trans *
 802 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 803                             int *n_entries)
 804 {
 805         if (IS_BROADWELL(dev_priv)) {
 806                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 807                 return bdw_ddi_translations_fdi;
 808         } else if (IS_HASWELL(dev_priv)) {
 809                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 810                 return hsw_ddi_translations_fdi;
 811         }
 812
 813         *n_entries = 0;
 814         return NULL;
 815 }
 816
 817 static const struct ddi_buf_trans *
 818 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 819                              int *n_entries)
 820 {
 821         if (IS_GEN9_BC(dev_priv)) {
 822                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 823         } else if (IS_BROADWELL(dev_priv)) {
 824                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 825                 return bdw_ddi_translations_hdmi;
 826         } else if (IS_HASWELL(dev_priv)) {
 827                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 828                 return hsw_ddi_translations_hdmi;
 829         }
 830
 831         *n_entries = 0;
 832         return NULL;
 833 }
 834
 835 static const struct bxt_ddi_buf_trans *
 836 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 837 {
 838         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 839         return bxt_ddi_translations_dp;
 840 }
 841
 842 static const struct bxt_ddi_buf_trans *
 843 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 844 {
 845         if (dev_priv->vbt.edp.low_vswing) {
 846                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 847                 return bxt_ddi_translations_edp;
 848         }
 849
 850         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 851 }
 852
 853 static const struct bxt_ddi_buf_trans *
 854 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 855 {
 856         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 857         return bxt_ddi_translations_hdmi;
 858 }
 859
 860 static const struct cnl_ddi_buf_trans *
 861 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 862 {
 863         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 864
 865         if (voltage == VOLTAGE_INFO_0_85V) {
 866                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 867                 return cnl_ddi_translations_hdmi_0_85V;
 868         } else if (voltage == VOLTAGE_INFO_0_95V) {
 869                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 870                 return cnl_ddi_translations_hdmi_0_95V;
 871         } else if (voltage == VOLTAGE_INFO_1_05V) {
 872                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 873                 return cnl_ddi_translations_hdmi_1_05V;
 874         } else {
 875                 *n_entries = 1; /* shut up gcc */
 876                 MISSING_CASE(voltage);
 877         }
 878         return NULL;
 879 }
 880
 881 static const struct cnl_ddi_buf_trans *
 882 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 883 {
 884         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 885
 886         if (voltage == VOLTAGE_INFO_0_85V) {
 887                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 888                 return cnl_ddi_translations_dp_0_85V;
 889         } else if (voltage == VOLTAGE_INFO_0_95V) {
 890                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 891                 return cnl_ddi_translations_dp_0_95V;
 892         } else if (voltage == VOLTAGE_INFO_1_05V) {
 893                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 894                 return cnl_ddi_translations_dp_1_05V;
 895         } else {
 896                 *n_entries = 1; /* shut up gcc */
 897                 MISSING_CASE(voltage);
 898         }
 899         return NULL;
 900 }
 901
 902 static const struct cnl_ddi_buf_trans *
 903 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 904 {
 905         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 906
 907         if (dev_priv->vbt.edp.low_vswing) {
 908                 if (voltage == VOLTAGE_INFO_0_85V) {
 909                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 910                         return cnl_ddi_translations_edp_0_85V;
 911                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 912                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 913                         return cnl_ddi_translations_edp_0_95V;
 914                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 915                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 916                         return cnl_ddi_translations_edp_1_05V;
 917                 } else {
 918                         *n_entries = 1; /* shut up gcc */
 919                         MISSING_CASE(voltage);
 920                 }
 921                 return NULL;
 922         } else {
 923                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 924         }
 925 }
 926
 927 static const struct cnl_ddi_buf_trans *
 928 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 929                         int *n_entries)
 930 {
 931         if (type == INTEL_OUTPUT_HDMI) {
 932                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 933                 return icl_combo_phy_ddi_translations_hdmi;
 934         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 935                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 936                 return icl_combo_phy_ddi_translations_edp_hbr3;
 937         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 938                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 939                 return icl_combo_phy_ddi_translations_edp_hbr2;
 940         }
 941
 942         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 943         return icl_combo_phy_ddi_translations_dp_hbr2;
 944 }
 945
 946 static const struct cnl_ddi_buf_trans *
 947 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 948                         int *n_entries)
 949 {
 950         if (type == INTEL_OUTPUT_DP && rate > 270000) {
 951                 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
 952                 return ehl_combo_phy_ddi_translations_hbr2_hbr3;
 953         }
 954
 955         return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
 956 }
 957
 958 static const struct cnl_ddi_buf_trans *
 959 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 960                         int *n_entries)
 961 {
 962         if (type != INTEL_OUTPUT_DP) {
 963                 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
 964         } else if (rate > 270000) {
 965                 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
 966                 return tgl_combo_phy_ddi_translations_dp_hbr2;
 967         }
 968
 969         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
 970         return tgl_combo_phy_ddi_translations_dp_hbr;
 971 }
 972
 973 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
 974 {
 975         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 976         int n_entries, level, default_entry;
 977         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 978
 979         if (INTEL_GEN(dev_priv) >= 12) {
 980                 if (intel_phy_is_combo(dev_priv, phy))
 981                         tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 982                                                 0, &n_entries);
 983                 else
 984                         n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
 985                 default_entry = n_entries - 1;
 986         } else if (INTEL_GEN(dev_priv) == 11) {
 987                 if (intel_phy_is_combo(dev_priv, phy))
 988                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 989                                                 0, &n_entries);
 990                 else
 991                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 992                 default_entry = n_entries - 1;
 993         } else if (IS_CANNONLAKE(dev_priv)) {
 994                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 995                 default_entry = n_entries - 1;
 996         } else if (IS_GEN9_LP(dev_priv)) {
 997                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 998                 default_entry = n_entries - 1;
 999         } else if (IS_GEN9_BC(dev_priv)) {
1000                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1001                 default_entry = 8;
1002         } else if (IS_BROADWELL(dev_priv)) {
1003                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1004                 default_entry = 7;
1005         } else if (IS_HASWELL(dev_priv)) {
1006                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1007                 default_entry = 6;
1008         } else {
1009                 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1010                 return 0;
1011         }
1012
1013         if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1014                 return 0;
1015
1016         level = intel_bios_hdmi_level_shift(encoder);
1017         if (level < 0)
1018                 level = default_entry;
1019
1020         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1021                 level = n_entries - 1;
1022
1023         return level;
1024 }
1025
1026 /*
1027  * Starting with Haswell, DDI port buffers must be programmed with correct
1028  * values in advance. This function programs the correct values for
1029  * DP/eDP/FDI use cases.
1030  */
1031 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1032                                          const struct intel_crtc_state *crtc_state)
1033 {
1034         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1035         u32 iboost_bit = 0;
1036         int i, n_entries;
1037         enum port port = encoder->port;
1038         const struct ddi_buf_trans *ddi_translations;
1039
1040         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1041                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1042                                                                &n_entries);
1043         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1044                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
1045                                                                &n_entries);
1046         else
1047                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
1048                                                               &n_entries);
1049
1050         /* If we're boosting the current, set bit 31 of trans1 */
1051         if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1052                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1053
1054         for (i = 0; i < n_entries; i++) {
1055                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1056                                ddi_translations[i].trans1 | iboost_bit);
1057                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1058                                ddi_translations[i].trans2);
1059         }
1060 }
1061
1062 /*
1063  * Starting with Haswell, DDI port buffers must be programmed with correct
1064  * values in advance. This function programs the correct values for
1065  * HDMI/DVI use cases.
1066  */
1067 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1068                                            int level)
1069 {
1070         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1071         u32 iboost_bit = 0;
1072         int n_entries;
1073         enum port port = encoder->port;
1074         const struct ddi_buf_trans *ddi_translations;
1075
1076         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1077
1078         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1079                 return;
1080         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1081                 level = n_entries - 1;
1082
1083         /* If we're boosting the current, set bit 31 of trans1 */
1084         if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1085                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1086
1087         /* Entry 9 is for HDMI: */
1088         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1089                        ddi_translations[level].trans1 | iboost_bit);
1090         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1091                        ddi_translations[level].trans2);
1092 }
1093
1094 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1095                                     enum port port)
1096 {
1097         i915_reg_t reg = DDI_BUF_CTL(port);
1098         int i;
1099
1100         for (i = 0; i < 16; i++) {
1101                 udelay(1);
1102                 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
1103                         return;
1104         }
1105         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1106 }
1107
1108 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1109 {
1110         switch (pll->info->id) {
1111         case DPLL_ID_WRPLL1:
1112                 return PORT_CLK_SEL_WRPLL1;
1113         case DPLL_ID_WRPLL2:
1114                 return PORT_CLK_SEL_WRPLL2;
1115         case DPLL_ID_SPLL:
1116                 return PORT_CLK_SEL_SPLL;
1117         case DPLL_ID_LCPLL_810:
1118                 return PORT_CLK_SEL_LCPLL_810;
1119         case DPLL_ID_LCPLL_1350:
1120                 return PORT_CLK_SEL_LCPLL_1350;
1121         case DPLL_ID_LCPLL_2700:
1122                 return PORT_CLK_SEL_LCPLL_2700;
1123         default:
1124                 MISSING_CASE(pll->info->id);
1125                 return PORT_CLK_SEL_NONE;
1126         }
1127 }
1128
1129 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1130                                   const struct intel_crtc_state *crtc_state)
1131 {
1132         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1133         int clock = crtc_state->port_clock;
1134         const enum intel_dpll_id id = pll->info->id;
1135
1136         switch (id) {
1137         default:
1138                 /*
1139                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1140                  * here, so do warn if this get passed in
1141                  */
1142                 MISSING_CASE(id);
1143                 return DDI_CLK_SEL_NONE;
1144         case DPLL_ID_ICL_TBTPLL:
1145                 switch (clock) {
1146                 case 162000:
1147                         return DDI_CLK_SEL_TBT_162;
1148                 case 270000:
1149                         return DDI_CLK_SEL_TBT_270;
1150                 case 540000:
1151                         return DDI_CLK_SEL_TBT_540;
1152                 case 810000:
1153                         return DDI_CLK_SEL_TBT_810;
1154                 default:
1155                         MISSING_CASE(clock);
1156                         return DDI_CLK_SEL_NONE;
1157                 }
1158         case DPLL_ID_ICL_MGPLL1:
1159         case DPLL_ID_ICL_MGPLL2:
1160         case DPLL_ID_ICL_MGPLL3:
1161         case DPLL_ID_ICL_MGPLL4:
1162         case DPLL_ID_TGL_MGPLL5:
1163         case DPLL_ID_TGL_MGPLL6:
1164                 return DDI_CLK_SEL_MG;
1165         }
1166 }
1167
1168 /* Starting with Haswell, different DDI ports can work in FDI mode for
1169  * connection to the PCH-located connectors. For this, it is necessary to train
1170  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1171  *
1172  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1173  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1174  * DDI A (which is used for eDP)
1175  */
1176
1177 void hsw_fdi_link_train(struct intel_encoder *encoder,
1178                         const struct intel_crtc_state *crtc_state)
1179 {
1180         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1181         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1182         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1183
1184         intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1185
1186         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1187          * mode set "sequence for CRT port" document:
1188          * - TP1 to TP2 time with the default value
1189          * - FDI delay to 90h
1190          *
1191          * WaFDIAutoLinkSetTimingOverrride:hsw
1192          */
1193         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1194                        FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1195
1196         /* Enable the PCH Receiver FDI PLL */
1197         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1198                      FDI_RX_PLL_ENABLE |
1199                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1200         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1201         intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1202         udelay(220);
1203
1204         /* Switch from Rawclk to PCDclk */
1205         rx_ctl_val |= FDI_PCDCLK;
1206         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207
1208         /* Configure Port Clock Select */
1209         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1210         intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1211         drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1212
1213         /* Start the training iterating through available voltages and emphasis,
1214          * testing each value twice. */
1215         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1216                 /* Configure DP_TP_CTL with auto-training */
1217                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1218                                DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE);
1219
1220                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1221                  * DDI E does not support port reversal, the functionality is
1222                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1223                  * port reversal bit */
1224                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1225                                DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1226                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1227
1228                 udelay(600);
1229
1230                 /* Program PCH FDI Receiver TU */
1231                 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1232
1233                 /* Enable PCH FDI Receiver with auto-training */
1234                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1235                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1236                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1237
1238                 /* Wait for FDI receiver lane calibration */
1239                 udelay(30);
1240
1241                 /* Unset FDI_RX_MISC pwrdn lanes */
1242                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1243                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1244                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1245                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1246
1247                 /* Wait for FDI auto training time */
1248                 udelay(5);
1249
1250                 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1251                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1252                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1253                         break;
1254                 }
1255
1256                 /*
1257                  * Leave things enabled even if we failed to train FDI.
1258                  * Results in less fireworks from the state checker.
1259                  */
1260                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1261                         DRM_ERROR("FDI link training failed!\n");
1262                         break;
1263                 }
1264
1265                 rx_ctl_val &= ~FDI_RX_ENABLE;
1266                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1267                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1268
1269                 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1270                 temp &= ~DDI_BUF_CTL_ENABLE;
1271                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1272                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1273
1274                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1275                 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1276                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1277                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1278                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1279                 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1280
1281                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1282
1283                 /* Reset FDI_RX_MISC pwrdn lanes */
1284                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1285                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1286                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1287                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1288                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1289         }
1290
1291         /* Enable normal pixel sending for FDI */
1292         intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1293                        DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE);
1294 }
1295
1296 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1297 {
1298         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1299         struct intel_digital_port *intel_dig_port =
1300                 enc_to_dig_port(encoder);
1301
1302         intel_dp->DP = intel_dig_port->saved_port_bits |
1303                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1304         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1305 }
1306
1307 static struct intel_encoder *
1308 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1309 {
1310         struct drm_device *dev = crtc->base.dev;
1311         struct intel_encoder *encoder, *ret = NULL;
1312         int num_encoders = 0;
1313
1314         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1315                 ret = encoder;
1316                 num_encoders++;
1317         }
1318
1319         if (num_encoders != 1)
1320                 drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n",
1321                          num_encoders,
1322                          pipe_name(crtc->pipe));
1323
1324         BUG_ON(ret == NULL);
1325         return ret;
1326 }
1327
1328 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1329                                  enum port port)
1330 {
1331         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1332
1333         switch (val) {
1334         case DDI_CLK_SEL_NONE:
1335                 return 0;
1336         case DDI_CLK_SEL_TBT_162:
1337                 return 162000;
1338         case DDI_CLK_SEL_TBT_270:
1339                 return 270000;
1340         case DDI_CLK_SEL_TBT_540:
1341                 return 540000;
1342         case DDI_CLK_SEL_TBT_810:
1343                 return 810000;
1344         default:
1345                 MISSING_CASE(val);
1346                 return 0;
1347         }
1348 }
1349
1350 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1351 {
1352         int dotclock;
1353
1354         if (pipe_config->has_pch_encoder)
1355                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1356                                                     &pipe_config->fdi_m_n);
1357         else if (intel_crtc_has_dp_encoder(pipe_config))
1358                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1359                                                     &pipe_config->dp_m_n);
1360         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1361                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1362         else
1363                 dotclock = pipe_config->port_clock;
1364
1365         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1366             !intel_crtc_has_dp_encoder(pipe_config))
1367                 dotclock *= 2;
1368
1369         if (pipe_config->pixel_multiplier)
1370                 dotclock /= pipe_config->pixel_multiplier;
1371
1372         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1373 }
1374
1375 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1376                                 struct intel_crtc_state *pipe_config)
1377 {
1378         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1379         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1380
1381         if (intel_phy_is_tc(dev_priv, phy) &&
1382             intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1383             DPLL_ID_ICL_TBTPLL)
1384                 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1385                                                                 encoder->port);
1386         else
1387                 pipe_config->port_clock =
1388                         intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
1389
1390         ddi_dotclock_get(pipe_config);
1391 }
1392
1393 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1394                           const struct drm_connector_state *conn_state)
1395 {
1396         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1397         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1398         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1399         u32 temp;
1400
1401         if (!intel_crtc_has_dp_encoder(crtc_state))
1402                 return;
1403
1404         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1405
1406         temp = DP_MSA_MISC_SYNC_CLOCK;
1407
1408         switch (crtc_state->pipe_bpp) {
1409         case 18:
1410                 temp |= DP_MSA_MISC_6_BPC;
1411                 break;
1412         case 24:
1413                 temp |= DP_MSA_MISC_8_BPC;
1414                 break;
1415         case 30:
1416                 temp |= DP_MSA_MISC_10_BPC;
1417                 break;
1418         case 36:
1419                 temp |= DP_MSA_MISC_12_BPC;
1420                 break;
1421         default:
1422                 MISSING_CASE(crtc_state->pipe_bpp);
1423                 break;
1424         }
1425
1426         /* nonsense combination */
1427         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1428                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1429
1430         if (crtc_state->limited_color_range)
1431                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1432
1433         /*
1434          * As per DP 1.2 spec section 2.3.4.3 while sending
1435          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1436          * colorspace information.
1437          */
1438         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1439                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1440
1441         /*
1442          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1443          * of Color Encoding Format and Content Color Gamut] while sending
1444          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1445          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1446          */
1447         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1448                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1449
1450         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1451 }
1452
1453 /*
1454  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1455  *
1456  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1457  * intel_ddi_config_transcoder_func().
1458  */
1459 static u32
1460 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1461 {
1462         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1463         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1465         enum pipe pipe = crtc->pipe;
1466         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1467         enum port port = encoder->port;
1468         u32 temp;
1469
1470         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1471         temp = TRANS_DDI_FUNC_ENABLE;
1472         if (INTEL_GEN(dev_priv) >= 12)
1473                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1474         else
1475                 temp |= TRANS_DDI_SELECT_PORT(port);
1476
1477         switch (crtc_state->pipe_bpp) {
1478         case 18:
1479                 temp |= TRANS_DDI_BPC_6;
1480                 break;
1481         case 24:
1482                 temp |= TRANS_DDI_BPC_8;
1483                 break;
1484         case 30:
1485                 temp |= TRANS_DDI_BPC_10;
1486                 break;
1487         case 36:
1488                 temp |= TRANS_DDI_BPC_12;
1489                 break;
1490         default:
1491                 BUG();
1492         }
1493
1494         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1495                 temp |= TRANS_DDI_PVSYNC;
1496         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1497                 temp |= TRANS_DDI_PHSYNC;
1498
1499         if (cpu_transcoder == TRANSCODER_EDP) {
1500                 switch (pipe) {
1501                 case PIPE_A:
1502                         /* On Haswell, can only use the always-on power well for
1503                          * eDP when not using the panel fitter, and when not
1504                          * using motion blur mitigation (which we don't
1505                          * support). */
1506                         if (crtc_state->pch_pfit.force_thru)
1507                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1508                         else
1509                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1510                         break;
1511                 case PIPE_B:
1512                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1513                         break;
1514                 case PIPE_C:
1515                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1516                         break;
1517                 default:
1518                         BUG();
1519                         break;
1520                 }
1521         }
1522
1523         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1524                 if (crtc_state->has_hdmi_sink)
1525                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1526                 else
1527                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1528
1529                 if (crtc_state->hdmi_scrambling)
1530                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1531                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1532                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1533         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1534                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1535                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1536         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1537                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1538                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1539
1540                 if (INTEL_GEN(dev_priv) >= 12) {
1541                         enum transcoder master;
1542
1543                         master = crtc_state->mst_master_transcoder;
1544                         drm_WARN_ON(&dev_priv->drm,
1545                                     master == INVALID_TRANSCODER);
1546                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1547                 }
1548         } else {
1549                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1550                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1551         }
1552
1553         return temp;
1554 }
1555
1556 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1557 {
1558         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1559         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1560         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1561         u32 temp;
1562
1563         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1564         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1565                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1566         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1567 }
1568
1569 /*
1570  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1571  * bit.
1572  */
1573 static void
1574 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1575 {
1576         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1577         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1578         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1579         u32 temp;
1580
1581         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1582         temp &= ~TRANS_DDI_FUNC_ENABLE;
1583         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1584 }
1585
1586 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1587 {
1588         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1589         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1590         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1591         u32 val;
1592
1593         val = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1594         val &= ~TRANS_DDI_FUNC_ENABLE;
1595
1596         if (INTEL_GEN(dev_priv) >= 12) {
1597                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
1598                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
1599                                  TRANS_DDI_MODE_SELECT_MASK);
1600                 }
1601         } else {
1602                 val &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
1603         }
1604         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), val);
1605
1606         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1607             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1608                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1609                 /* Quirk time at 100ms for reliable operation */
1610                 msleep(100);
1611         }
1612 }
1613
1614 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1615                                      bool enable)
1616 {
1617         struct drm_device *dev = intel_encoder->base.dev;
1618         struct drm_i915_private *dev_priv = to_i915(dev);
1619         intel_wakeref_t wakeref;
1620         enum pipe pipe = 0;
1621         int ret = 0;
1622         u32 tmp;
1623
1624         wakeref = intel_display_power_get_if_enabled(dev_priv,
1625                                                      intel_encoder->power_domain);
1626         if (drm_WARN_ON(dev, !wakeref))
1627                 return -ENXIO;
1628
1629         if (drm_WARN_ON(dev,
1630                         !intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1631                 ret = -EIO;
1632                 goto out;
1633         }
1634
1635         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe));
1636         if (enable)
1637                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1638         else
1639                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1640         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp);
1641 out:
1642         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1643         return ret;
1644 }
1645
1646 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1647 {
1648         struct drm_device *dev = intel_connector->base.dev;
1649         struct drm_i915_private *dev_priv = to_i915(dev);
1650         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1651         int type = intel_connector->base.connector_type;
1652         enum port port = encoder->port;
1653         enum transcoder cpu_transcoder;
1654         intel_wakeref_t wakeref;
1655         enum pipe pipe = 0;
1656         u32 tmp;
1657         bool ret;
1658
1659         wakeref = intel_display_power_get_if_enabled(dev_priv,
1660                                                      encoder->power_domain);
1661         if (!wakeref)
1662                 return false;
1663
1664         if (!encoder->get_hw_state(encoder, &pipe)) {
1665                 ret = false;
1666                 goto out;
1667         }
1668
1669         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1670                 cpu_transcoder = TRANSCODER_EDP;
1671         else
1672                 cpu_transcoder = (enum transcoder) pipe;
1673
1674         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1675
1676         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1677         case TRANS_DDI_MODE_SELECT_HDMI:
1678         case TRANS_DDI_MODE_SELECT_DVI:
1679                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1680                 break;
1681
1682         case TRANS_DDI_MODE_SELECT_DP_SST:
1683                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1684                       type == DRM_MODE_CONNECTOR_DisplayPort;
1685                 break;
1686
1687         case TRANS_DDI_MODE_SELECT_DP_MST:
1688                 /* if the transcoder is in MST state then
1689                  * connector isn't connected */
1690                 ret = false;
1691                 break;
1692
1693         case TRANS_DDI_MODE_SELECT_FDI:
1694                 ret = type == DRM_MODE_CONNECTOR_VGA;
1695                 break;
1696
1697         default:
1698                 ret = false;
1699                 break;
1700         }
1701
1702 out:
1703         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1704
1705         return ret;
1706 }
1707
1708 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1709                                         u8 *pipe_mask, bool *is_dp_mst)
1710 {
1711         struct drm_device *dev = encoder->base.dev;
1712         struct drm_i915_private *dev_priv = to_i915(dev);
1713         enum port port = encoder->port;
1714         intel_wakeref_t wakeref;
1715         enum pipe p;
1716         u32 tmp;
1717         u8 mst_pipe_mask;
1718
1719         *pipe_mask = 0;
1720         *is_dp_mst = false;
1721
1722         wakeref = intel_display_power_get_if_enabled(dev_priv,
1723                                                      encoder->power_domain);
1724         if (!wakeref)
1725                 return;
1726
1727         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1728         if (!(tmp & DDI_BUF_CTL_ENABLE))
1729                 goto out;
1730
1731         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1732                 tmp = intel_de_read(dev_priv,
1733                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1734
1735                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1736                 default:
1737                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1738                         /* fallthrough */
1739                 case TRANS_DDI_EDP_INPUT_A_ON:
1740                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1741                         *pipe_mask = BIT(PIPE_A);
1742                         break;
1743                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1744                         *pipe_mask = BIT(PIPE_B);
1745                         break;
1746                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1747                         *pipe_mask = BIT(PIPE_C);
1748                         break;
1749                 }
1750
1751                 goto out;
1752         }
1753
1754         mst_pipe_mask = 0;
1755         for_each_pipe(dev_priv, p) {
1756                 enum transcoder cpu_transcoder = (enum transcoder)p;
1757                 unsigned int port_mask, ddi_select;
1758                 intel_wakeref_t trans_wakeref;
1759
1760                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
1761                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1762                 if (!trans_wakeref)
1763                         continue;
1764
1765                 if (INTEL_GEN(dev_priv) >= 12) {
1766                         port_mask = TGL_TRANS_DDI_PORT_MASK;
1767                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
1768                 } else {
1769                         port_mask = TRANS_DDI_PORT_MASK;
1770                         ddi_select = TRANS_DDI_SELECT_PORT(port);
1771                 }
1772
1773                 tmp = intel_de_read(dev_priv,
1774                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
1775                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
1776                                         trans_wakeref);
1777
1778                 if ((tmp & port_mask) != ddi_select)
1779                         continue;
1780
1781                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1782                     TRANS_DDI_MODE_SELECT_DP_MST)
1783                         mst_pipe_mask |= BIT(p);
1784
1785                 *pipe_mask |= BIT(p);
1786         }
1787
1788         if (!*pipe_mask)
1789                 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
1790                               encoder->base.base.id, encoder->base.name);
1791
1792         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1793                 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
1794                               encoder->base.base.id, encoder->base.name,
1795                               *pipe_mask);
1796                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
1797         }
1798
1799         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
1800                 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
1801                               encoder->base.base.id, encoder->base.name,
1802                               *pipe_mask, mst_pipe_mask);
1803         else
1804                 *is_dp_mst = mst_pipe_mask;
1805
1806 out:
1807         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
1808                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
1809                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1810                             BXT_PHY_LANE_POWERDOWN_ACK |
1811                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1812                         DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
1813                                   "(PHY_CTL %08x)\n", encoder->base.base.id,
1814                                   encoder->base.name, tmp);
1815         }
1816
1817         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1818 }
1819
1820 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1821                             enum pipe *pipe)
1822 {
1823         u8 pipe_mask;
1824         bool is_mst;
1825
1826         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
1827
1828         if (is_mst || !pipe_mask)
1829                 return false;
1830
1831         *pipe = ffs(pipe_mask) - 1;
1832
1833         return true;
1834 }
1835
1836 static inline enum intel_display_power_domain
1837 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
1838 {
1839         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
1840          * DC states enabled at the same time, while for driver initiated AUX
1841          * transfers we need the same AUX IOs to be powered but with DC states
1842          * disabled. Accordingly use the AUX power domain here which leaves DC
1843          * states enabled.
1844          * However, for non-A AUX ports the corresponding non-EDP transcoders
1845          * would have already enabled power well 2 and DC_OFF. This means we can
1846          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
1847          * specific AUX_IO reference without powering up any extra wells.
1848          * Note that PSR is enabled only on Port A even though this function
1849          * returns the correct domain for other ports too.
1850          */
1851         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
1852                                               intel_aux_power_domain(dig_port);
1853 }
1854
1855 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
1856                                         struct intel_crtc_state *crtc_state)
1857 {
1858         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1859         struct intel_digital_port *dig_port;
1860         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1861
1862         /*
1863          * TODO: Add support for MST encoders. Atm, the following should never
1864          * happen since fake-MST encoders don't set their get_power_domains()
1865          * hook.
1866          */
1867         if (drm_WARN_ON(&dev_priv->drm,
1868                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
1869                 return;
1870
1871         dig_port = enc_to_dig_port(encoder);
1872         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
1873
1874         /*
1875          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
1876          * ports.
1877          */
1878         if (intel_crtc_has_dp_encoder(crtc_state) ||
1879             intel_phy_is_tc(dev_priv, phy))
1880                 intel_display_power_get(dev_priv,
1881                                         intel_ddi_main_link_aux_domain(dig_port));
1882
1883         /*
1884          * VDSC power is needed when DSC is enabled
1885          */
1886         if (crtc_state->dsc.compression_enable)
1887                 intel_display_power_get(dev_priv,
1888                                         intel_dsc_power_domain(crtc_state));
1889 }
1890
1891 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1892 {
1893         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1894         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1895         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1896         enum port port = encoder->port;
1897         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1898
1899         if (cpu_transcoder != TRANSCODER_EDP) {
1900                 if (INTEL_GEN(dev_priv) >= 12)
1901                         intel_de_write(dev_priv,
1902                                        TRANS_CLK_SEL(cpu_transcoder),
1903                                        TGL_TRANS_CLK_SEL_PORT(port));
1904                 else
1905                         intel_de_write(dev_priv,
1906                                        TRANS_CLK_SEL(cpu_transcoder),
1907                                        TRANS_CLK_SEL_PORT(port));
1908         }
1909 }
1910
1911 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1912 {
1913         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1914         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1915
1916         if (cpu_transcoder != TRANSCODER_EDP) {
1917                 if (INTEL_GEN(dev_priv) >= 12)
1918                         intel_de_write(dev_priv,
1919                                        TRANS_CLK_SEL(cpu_transcoder),
1920                                        TGL_TRANS_CLK_SEL_DISABLED);
1921                 else
1922                         intel_de_write(dev_priv,
1923                                        TRANS_CLK_SEL(cpu_transcoder),
1924                                        TRANS_CLK_SEL_DISABLED);
1925         }
1926 }
1927
1928 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1929                                 enum port port, u8 iboost)
1930 {
1931         u32 tmp;
1932
1933         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
1934         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1935         if (iboost)
1936                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1937         else
1938                 tmp |= BALANCE_LEG_DISABLE(port);
1939         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
1940 }
1941
1942 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1943                                int level, enum intel_output_type type)
1944 {
1945         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1946         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1947         enum port port = encoder->port;
1948         u8 iboost;
1949
1950         if (type == INTEL_OUTPUT_HDMI)
1951                 iboost = intel_bios_hdmi_boost_level(encoder);
1952         else
1953                 iboost = intel_bios_dp_boost_level(encoder);
1954
1955         if (iboost == 0) {
1956                 const struct ddi_buf_trans *ddi_translations;
1957                 int n_entries;
1958
1959                 if (type == INTEL_OUTPUT_HDMI)
1960                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1961                 else if (type == INTEL_OUTPUT_EDP)
1962                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1963                 else
1964                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1965
1966                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1967                         return;
1968                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1969                         level = n_entries - 1;
1970
1971                 iboost = ddi_translations[level].i_boost;
1972         }
1973
1974         /* Make sure that the requested I_boost is valid */
1975         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1976                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1977                 return;
1978         }
1979
1980         _skl_ddi_set_iboost(dev_priv, port, iboost);
1981
1982         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1983                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1984 }
1985
1986 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1987                                     int level, enum intel_output_type type)
1988 {
1989         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1990         const struct bxt_ddi_buf_trans *ddi_translations;
1991         enum port port = encoder->port;
1992         int n_entries;
1993
1994         if (type == INTEL_OUTPUT_HDMI)
1995                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1996         else if (type == INTEL_OUTPUT_EDP)
1997                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1998         else
1999                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2000
2001         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2002                 return;
2003         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2004                 level = n_entries - 1;
2005
2006         bxt_ddi_phy_set_signal_level(dev_priv, port,
2007                                      ddi_translations[level].margin,
2008                                      ddi_translations[level].scale,
2009                                      ddi_translations[level].enable,
2010                                      ddi_translations[level].deemphasis);
2011 }
2012
2013 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2014 {
2015         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2016         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2017         enum port port = encoder->port;
2018         enum phy phy = intel_port_to_phy(dev_priv, port);
2019         int n_entries;
2020
2021         if (INTEL_GEN(dev_priv) >= 12) {
2022                 if (intel_phy_is_combo(dev_priv, phy))
2023                         tgl_get_combo_buf_trans(dev_priv, encoder->type,
2024                                                 intel_dp->link_rate, &n_entries);
2025                 else
2026                         n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2027         } else if (INTEL_GEN(dev_priv) == 11) {
2028                 if (IS_ELKHARTLAKE(dev_priv))
2029                         ehl_get_combo_buf_trans(dev_priv, encoder->type,
2030                                                 intel_dp->link_rate, &n_entries);
2031                 else if (intel_phy_is_combo(dev_priv, phy))
2032                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2033                                                 intel_dp->link_rate, &n_entries);
2034                 else
2035                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2036         } else if (IS_CANNONLAKE(dev_priv)) {
2037                 if (encoder->type == INTEL_OUTPUT_EDP)
2038                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2039                 else
2040                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2041         } else if (IS_GEN9_LP(dev_priv)) {
2042                 if (encoder->type == INTEL_OUTPUT_EDP)
2043                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2044                 else
2045                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2046         } else {
2047                 if (encoder->type == INTEL_OUTPUT_EDP)
2048                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2049                 else
2050                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2051         }
2052
2053         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2054                 n_entries = 1;
2055         if (drm_WARN_ON(&dev_priv->drm,
2056                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2057                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2058
2059         return index_to_dp_signal_levels[n_entries - 1] &
2060                 DP_TRAIN_VOLTAGE_SWING_MASK;
2061 }
2062
2063 /*
2064  * We assume that the full set of pre-emphasis values can be
2065  * used on all DDI platforms. Should that change we need to
2066  * rethink this code.
2067  */
2068 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2069 {
2070         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2071         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2072                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2073         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2074                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2075         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2076                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2077         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2078         default:
2079                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2080         }
2081 }
2082
2083 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2084                                    int level, enum intel_output_type type)
2085 {
2086         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2087         const struct cnl_ddi_buf_trans *ddi_translations;
2088         enum port port = encoder->port;
2089         int n_entries, ln;
2090         u32 val;
2091
2092         if (type == INTEL_OUTPUT_HDMI)
2093                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2094         else if (type == INTEL_OUTPUT_EDP)
2095                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2096         else
2097                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2098
2099         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2100                 return;
2101         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2102                 level = n_entries - 1;
2103
2104         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2105         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2106         val &= ~SCALING_MODE_SEL_MASK;
2107         val |= SCALING_MODE_SEL(2);
2108         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2109
2110         /* Program PORT_TX_DW2 */
2111         val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2112         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2113                  RCOMP_SCALAR_MASK);
2114         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2115         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2116         /* Rcomp scalar is fixed as 0x98 for every table entry */
2117         val |= RCOMP_SCALAR(0x98);
2118         intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2119
2120         /* Program PORT_TX_DW4 */
2121         /* We cannot write to GRP. It would overrite individual loadgen */
2122         for (ln = 0; ln < 4; ln++) {
2123                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2124                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2125                          CURSOR_COEFF_MASK);
2126                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2127                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2128                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2129                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2130         }
2131
2132         /* Program PORT_TX_DW5 */
2133         /* All DW5 values are fixed for every table entry */
2134         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2135         val &= ~RTERM_SELECT_MASK;
2136         val |= RTERM_SELECT(6);
2137         val |= TAP3_DISABLE;
2138         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2139
2140         /* Program PORT_TX_DW7 */
2141         val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2142         val &= ~N_SCALAR_MASK;
2143         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2144         intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2145 }
2146
2147 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2148                                     int level, enum intel_output_type type)
2149 {
2150         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2151         enum port port = encoder->port;
2152         int width, rate, ln;
2153         u32 val;
2154
2155         if (type == INTEL_OUTPUT_HDMI) {
2156                 width = 4;
2157                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2158         } else {
2159                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2160
2161                 width = intel_dp->lane_count;
2162                 rate = intel_dp->link_rate;
2163         }
2164
2165         /*
2166          * 1. If port type is eDP or DP,
2167          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2168          * else clear to 0b.
2169          */
2170         val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2171         if (type != INTEL_OUTPUT_HDMI)
2172                 val |= COMMON_KEEPER_EN;
2173         else
2174                 val &= ~COMMON_KEEPER_EN;
2175         intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2176
2177         /* 2. Program loadgen select */
2178         /*
2179          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2180          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2181          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2182          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2183          */
2184         for (ln = 0; ln <= 3; ln++) {
2185                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2186                 val &= ~LOADGEN_SELECT;
2187
2188                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2189                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2190                         val |= LOADGEN_SELECT;
2191                 }
2192                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2193         }
2194
2195         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2196         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2197         val |= SUS_CLOCK_CONFIG;
2198         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2199
2200         /* 4. Clear training enable to change swing values */
2201         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2202         val &= ~TX_TRAINING_EN;
2203         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2204
2205         /* 5. Program swing and de-emphasis */
2206         cnl_ddi_vswing_program(encoder, level, type);
2207
2208         /* 6. Set training enable to trigger update */
2209         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2210         val |= TX_TRAINING_EN;
2211         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2212 }
2213
2214 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2215                                         u32 level, enum phy phy, int type,
2216                                         int rate)
2217 {
2218         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2219         u32 n_entries, val;
2220         int ln;
2221
2222         if (INTEL_GEN(dev_priv) >= 12)
2223                 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
2224                                                            &n_entries);
2225         else if (IS_ELKHARTLAKE(dev_priv))
2226                 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
2227                                                            &n_entries);
2228         else
2229                 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2230                                                            &n_entries);
2231         if (!ddi_translations)
2232                 return;
2233
2234         if (level >= n_entries) {
2235                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2236                 level = n_entries - 1;
2237         }
2238
2239         /* Set PORT_TX_DW5 */
2240         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2241         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2242                   TAP2_DISABLE | TAP3_DISABLE);
2243         val |= SCALING_MODE_SEL(0x2);
2244         val |= RTERM_SELECT(0x6);
2245         val |= TAP3_DISABLE;
2246         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2247
2248         /* Program PORT_TX_DW2 */
2249         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2250         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2251                  RCOMP_SCALAR_MASK);
2252         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2253         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2254         /* Program Rcomp scalar for every table entry */
2255         val |= RCOMP_SCALAR(0x98);
2256         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2257
2258         /* Program PORT_TX_DW4 */
2259         /* We cannot write to GRP. It would overwrite individual loadgen. */
2260         for (ln = 0; ln <= 3; ln++) {
2261                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2262                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2263                          CURSOR_COEFF_MASK);
2264                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2265                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2266                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2267                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2268         }
2269
2270         /* Program PORT_TX_DW7 */
2271         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2272         val &= ~N_SCALAR_MASK;
2273         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2274         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2275 }
2276
2277 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2278                                               u32 level,
2279                                               enum intel_output_type type)
2280 {
2281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2282         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2283         int width = 0;
2284         int rate = 0;
2285         u32 val;
2286         int ln = 0;
2287
2288         if (type == INTEL_OUTPUT_HDMI) {
2289                 width = 4;
2290                 /* Rate is always < than 6GHz for HDMI */
2291         } else {
2292                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2293
2294                 width = intel_dp->lane_count;
2295                 rate = intel_dp->link_rate;
2296         }
2297
2298         /*
2299          * 1. If port type is eDP or DP,
2300          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2301          * else clear to 0b.
2302          */
2303         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2304         if (type == INTEL_OUTPUT_HDMI)
2305                 val &= ~COMMON_KEEPER_EN;
2306         else
2307                 val |= COMMON_KEEPER_EN;
2308         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2309
2310         /* 2. Program loadgen select */
2311         /*
2312          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2313          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2314          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2315          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2316          */
2317         for (ln = 0; ln <= 3; ln++) {
2318                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2319                 val &= ~LOADGEN_SELECT;
2320
2321                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2322                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2323                         val |= LOADGEN_SELECT;
2324                 }
2325                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2326         }
2327
2328         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2329         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2330         val |= SUS_CLOCK_CONFIG;
2331         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2332
2333         /* 4. Clear training enable to change swing values */
2334         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2335         val &= ~TX_TRAINING_EN;
2336         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2337
2338         /* 5. Program swing and de-emphasis */
2339         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2340
2341         /* 6. Set training enable to trigger update */
2342         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2343         val |= TX_TRAINING_EN;
2344         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2345 }
2346
2347 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2348                                            int link_clock,
2349                                            u32 level)
2350 {
2351         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2352         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2353         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2354         u32 n_entries, val;
2355         int ln;
2356
2357         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2358         ddi_translations = icl_mg_phy_ddi_translations;
2359         /* The table does not have values for level 3 and level 9. */
2360         if (level >= n_entries || level == 3 || level == 9) {
2361                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2362                               level, n_entries - 2);
2363                 level = n_entries - 2;
2364         }
2365
2366         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2367         for (ln = 0; ln < 2; ln++) {
2368                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2369                 val &= ~CRI_USE_FS32;
2370                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2371
2372                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2373                 val &= ~CRI_USE_FS32;
2374                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2375         }
2376
2377         /* Program MG_TX_SWINGCTRL with values from vswing table */
2378         for (ln = 0; ln < 2; ln++) {
2379                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2380                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2381                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2382                         ddi_translations[level].cri_txdeemph_override_17_12);
2383                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2384
2385                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2386                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2387                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2388                         ddi_translations[level].cri_txdeemph_override_17_12);
2389                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2390         }
2391
2392         /* Program MG_TX_DRVCTRL with values from vswing table */
2393         for (ln = 0; ln < 2; ln++) {
2394                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2395                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2396                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2397                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2398                         ddi_translations[level].cri_txdeemph_override_5_0) |
2399                         CRI_TXDEEMPH_OVERRIDE_11_6(
2400                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2401                         CRI_TXDEEMPH_OVERRIDE_EN;
2402                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2403
2404                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2405                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2406                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2407                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2408                         ddi_translations[level].cri_txdeemph_override_5_0) |
2409                         CRI_TXDEEMPH_OVERRIDE_11_6(
2410                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2411                         CRI_TXDEEMPH_OVERRIDE_EN;
2412                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2413
2414                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2415         }
2416
2417         /*
2418          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2419          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2420          * values from table for which TX1 and TX2 enabled.
2421          */
2422         for (ln = 0; ln < 2; ln++) {
2423                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2424                 if (link_clock < 300000)
2425                         val |= CFG_LOW_RATE_LKREN_EN;
2426                 else
2427                         val &= ~CFG_LOW_RATE_LKREN_EN;
2428                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2429         }
2430
2431         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2432         for (ln = 0; ln < 2; ln++) {
2433                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2434                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2435                 if (link_clock <= 500000) {
2436                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2437                 } else {
2438                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2439                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2440                 }
2441                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2442
2443                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2444                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2445                 if (link_clock <= 500000) {
2446                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2447                 } else {
2448                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2449                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2450                 }
2451                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2452         }
2453
2454         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2455         for (ln = 0; ln < 2; ln++) {
2456                 val = intel_de_read(dev_priv,
2457                                     MG_TX1_PISO_READLOAD(ln, tc_port));
2458                 val |= CRI_CALCINIT;
2459                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2460                                val);
2461
2462                 val = intel_de_read(dev_priv,
2463                                     MG_TX2_PISO_READLOAD(ln, tc_port));
2464                 val |= CRI_CALCINIT;
2465                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2466                                val);
2467         }
2468 }
2469
2470 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2471                                     int link_clock,
2472                                     u32 level,
2473                                     enum intel_output_type type)
2474 {
2475         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2476         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2477
2478         if (intel_phy_is_combo(dev_priv, phy))
2479                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2480         else
2481                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2482 }
2483
2484 static void
2485 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2486                                 u32 level)
2487 {
2488         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2489         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2490         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2491         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2492
2493         if (encoder->type == INTEL_OUTPUT_HDMI) {
2494                 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
2495                 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
2496         } else {
2497                 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2498                 ddi_translations = tgl_dkl_phy_dp_ddi_trans;
2499         }
2500
2501         if (level >= n_entries)
2502                 level = n_entries - 1;
2503
2504         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2505                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2506                       DKL_TX_VSWING_CONTROL_MASK);
2507         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2508         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2509         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2510
2511         for (ln = 0; ln < 2; ln++) {
2512                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2513                                HIP_INDEX_VAL(tc_port, ln));
2514
2515                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2516
2517                 /* All the registers are RMW */
2518                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2519                 val &= ~dpcnt_mask;
2520                 val |= dpcnt_val;
2521                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2522
2523                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2524                 val &= ~dpcnt_mask;
2525                 val |= dpcnt_val;
2526                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2527
2528                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2529                 val &= ~DKL_TX_DP20BITMODE;
2530                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2531         }
2532 }
2533
2534 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2535                                     int link_clock,
2536                                     u32 level,
2537                                     enum intel_output_type type)
2538 {
2539         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2540         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2541
2542         if (intel_phy_is_combo(dev_priv, phy))
2543                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2544         else
2545                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2546 }
2547
2548 static u32 translate_signal_level(int signal_levels)
2549 {
2550         int i;
2551
2552         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2553                 if (index_to_dp_signal_levels[i] == signal_levels)
2554                         return i;
2555         }
2556
2557         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2558              signal_levels);
2559
2560         return 0;
2561 }
2562
2563 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2564 {
2565         u8 train_set = intel_dp->train_set[0];
2566         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2567                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2568
2569         return translate_signal_level(signal_levels);
2570 }
2571
2572 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2573 {
2574         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2575         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2576         struct intel_encoder *encoder = &dport->base;
2577         int level = intel_ddi_dp_level(intel_dp);
2578
2579         if (INTEL_GEN(dev_priv) >= 12)
2580                 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2581                                         level, encoder->type);
2582         else if (INTEL_GEN(dev_priv) >= 11)
2583                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2584                                         level, encoder->type);
2585         else if (IS_CANNONLAKE(dev_priv))
2586                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2587         else
2588                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2589
2590         return 0;
2591 }
2592
2593 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2594 {
2595         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2596         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2597         struct intel_encoder *encoder = &dport->base;
2598         int level = intel_ddi_dp_level(intel_dp);
2599
2600         if (IS_GEN9_BC(dev_priv))
2601                 skl_ddi_set_iboost(encoder, level, encoder->type);
2602
2603         return DDI_BUF_TRANS_SELECT(level);
2604 }
2605
2606 static inline
2607 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2608                               enum phy phy)
2609 {
2610         if (intel_phy_is_combo(dev_priv, phy)) {
2611                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2612         } else if (intel_phy_is_tc(dev_priv, phy)) {
2613                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2614                                                         (enum port)phy);
2615
2616                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2617         }
2618
2619         return 0;
2620 }
2621
2622 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2623                                   const struct intel_crtc_state *crtc_state)
2624 {
2625         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2626         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2627         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2628         u32 val;
2629
2630         mutex_lock(&dev_priv->dpll.lock);
2631
2632         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2633         drm_WARN_ON(&dev_priv->drm,
2634                     (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2635
2636         if (intel_phy_is_combo(dev_priv, phy)) {
2637                 /*
2638                  * Even though this register references DDIs, note that we
2639                  * want to pass the PHY rather than the port (DDI).  For
2640                  * ICL, port=phy in all cases so it doesn't matter, but for
2641                  * EHL the bspec notes the following:
2642                  *
2643                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2644                  *   Clock Select chooses the PLL for both DDIA and DDID and
2645                  *   drives port A in all cases."
2646                  */
2647                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2648                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2649                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2650                 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
2651         }
2652
2653         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2654         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2655
2656         mutex_unlock(&dev_priv->dpll.lock);
2657 }
2658
2659 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2660 {
2661         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2662         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2663         u32 val;
2664
2665         mutex_lock(&dev_priv->dpll.lock);
2666
2667         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2668         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2669         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2670
2671         mutex_unlock(&dev_priv->dpll.lock);
2672 }
2673
2674 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
2675                                       u32 port_mask, bool ddi_clk_needed)
2676 {
2677         enum port port;
2678         u32 val;
2679
2680         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2681         for_each_port_masked(port, port_mask) {
2682                 enum phy phy = intel_port_to_phy(dev_priv, port);
2683                 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
2684                                                                    phy);
2685
2686                 if (ddi_clk_needed == !ddi_clk_off)
2687                         continue;
2688
2689                 /*
2690                  * Punt on the case now where clock is gated, but it would
2691                  * be needed by the port. Something else is really broken then.
2692                  */
2693                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
2694                         continue;
2695
2696                 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2697                          phy_name(phy));
2698                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2699                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2700         }
2701 }
2702
2703 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2704 {
2705         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2706         u32 port_mask;
2707         bool ddi_clk_needed;
2708
2709         /*
2710          * In case of DP MST, we sanitize the primary encoder only, not the
2711          * virtual ones.
2712          */
2713         if (encoder->type == INTEL_OUTPUT_DP_MST)
2714                 return;
2715
2716         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2717                 u8 pipe_mask;
2718                 bool is_mst;
2719
2720                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2721                 /*
2722                  * In the unlikely case that BIOS enables DP in MST mode, just
2723                  * warn since our MST HW readout is incomplete.
2724                  */
2725                 if (drm_WARN_ON(&dev_priv->drm, is_mst))
2726                         return;
2727         }
2728
2729         port_mask = BIT(encoder->port);
2730         ddi_clk_needed = encoder->base.crtc;
2731
2732         if (encoder->type == INTEL_OUTPUT_DSI) {
2733                 struct intel_encoder *other_encoder;
2734
2735                 port_mask = intel_dsi_encoder_ports(encoder);
2736                 /*
2737                  * Sanity check that we haven't incorrectly registered another
2738                  * encoder using any of the ports of this DSI encoder.
2739                  */
2740                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2741                         if (other_encoder == encoder)
2742                                 continue;
2743
2744                         if (drm_WARN_ON(&dev_priv->drm,
2745                                         port_mask & BIT(other_encoder->port)))
2746                                 return;
2747                 }
2748                 /*
2749                  * For DSI we keep the ddi clocks gated
2750                  * except during enable/disable sequence.
2751                  */
2752                 ddi_clk_needed = false;
2753         }
2754
2755         icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
2756 }
2757
2758 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2759                                  const struct intel_crtc_state *crtc_state)
2760 {
2761         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2762         enum port port = encoder->port;
2763         enum phy phy = intel_port_to_phy(dev_priv, port);
2764         u32 val;
2765         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2766
2767         if (drm_WARN_ON(&dev_priv->drm, !pll))
2768                 return;
2769
2770         mutex_lock(&dev_priv->dpll.lock);
2771
2772         if (INTEL_GEN(dev_priv) >= 11) {
2773                 if (!intel_phy_is_combo(dev_priv, phy))
2774                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2775                                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2776                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2777                         /*
2778                          * MG does not exist but the programming is required
2779                          * to ungate DDIC and DDID
2780                          */
2781                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2782                                        DDI_CLK_SEL_MG);
2783         } else if (IS_CANNONLAKE(dev_priv)) {
2784                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2785                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
2786                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2787                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2788                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
2789
2790                 /*
2791                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2792                  * This step and the step before must be done with separate
2793                  * register writes.
2794                  */
2795                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
2796                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2797                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
2798         } else if (IS_GEN9_BC(dev_priv)) {
2799                 /* DDI -> PLL mapping  */
2800                 val = intel_de_read(dev_priv, DPLL_CTRL2);
2801
2802                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2803                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2804                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2805                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2806
2807                 intel_de_write(dev_priv, DPLL_CTRL2, val);
2808
2809         } else if (INTEL_GEN(dev_priv) < 9) {
2810                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
2811                                hsw_pll_to_ddi_pll_sel(pll));
2812         }
2813
2814         mutex_unlock(&dev_priv->dpll.lock);
2815 }
2816
2817 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2818 {
2819         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2820         enum port port = encoder->port;
2821         enum phy phy = intel_port_to_phy(dev_priv, port);
2822
2823         if (INTEL_GEN(dev_priv) >= 11) {
2824                 if (!intel_phy_is_combo(dev_priv, phy) ||
2825                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
2826                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
2827                                        DDI_CLK_SEL_NONE);
2828         } else if (IS_CANNONLAKE(dev_priv)) {
2829                 intel_de_write(dev_priv, DPCLKA_CFGCR0,
2830                                intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2831         } else if (IS_GEN9_BC(dev_priv)) {
2832                 intel_de_write(dev_priv, DPLL_CTRL2,
2833                                intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
2834         } else if (INTEL_GEN(dev_priv) < 9) {
2835                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
2836                                PORT_CLK_SEL_NONE);
2837         }
2838 }
2839
2840 static void
2841 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
2842                        const struct intel_crtc_state *crtc_state)
2843 {
2844         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2845         enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
2846         u32 ln0, ln1, pin_assignment;
2847         u8 width;
2848
2849         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
2850                 return;
2851
2852         if (INTEL_GEN(dev_priv) >= 12) {
2853                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2854                                HIP_INDEX_VAL(tc_port, 0x0));
2855                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2856                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2857                                HIP_INDEX_VAL(tc_port, 0x1));
2858                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2859         } else {
2860                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2861                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2862         }
2863
2864         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
2865         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2866
2867         /* DPPATC */
2868         pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
2869         width = crtc_state->lane_count;
2870
2871         switch (pin_assignment) {
2872         case 0x0:
2873                 drm_WARN_ON(&dev_priv->drm,
2874                             intel_dig_port->tc_mode != TC_PORT_LEGACY);
2875                 if (width == 1) {
2876                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2877                 } else {
2878                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2879                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2880                 }
2881                 break;
2882         case 0x1:
2883                 if (width == 4) {
2884                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2885                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2886                 }
2887                 break;
2888         case 0x2:
2889                 if (width == 2) {
2890                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2891                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2892                 }
2893                 break;
2894         case 0x3:
2895         case 0x5:
2896                 if (width == 1) {
2897                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2898                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2899                 } else {
2900                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2901                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2902                 }
2903                 break;
2904         case 0x4:
2905         case 0x6:
2906                 if (width == 1) {
2907                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2908                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2909                 } else {
2910                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2911                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2912                 }
2913                 break;
2914         default:
2915                 MISSING_CASE(pin_assignment);
2916         }
2917
2918         if (INTEL_GEN(dev_priv) >= 12) {
2919                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2920                                HIP_INDEX_VAL(tc_port, 0x0));
2921                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2922                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2923                                HIP_INDEX_VAL(tc_port, 0x1));
2924                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2925         } else {
2926                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2927                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2928         }
2929 }
2930
2931 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2932                                         const struct intel_crtc_state *crtc_state)
2933 {
2934         if (!crtc_state->fec_enable)
2935                 return;
2936
2937         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2938                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
2939 }
2940
2941 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2942                                  const struct intel_crtc_state *crtc_state)
2943 {
2944         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2945         struct intel_dp *intel_dp;
2946         u32 val;
2947
2948         if (!crtc_state->fec_enable)
2949                 return;
2950
2951         intel_dp = enc_to_intel_dp(encoder);
2952         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
2953         val |= DP_TP_CTL_FEC_ENABLE;
2954         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
2955
2956         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
2957                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
2958                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
2959 }
2960
2961 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2962                                         const struct intel_crtc_state *crtc_state)
2963 {
2964         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2965         struct intel_dp *intel_dp;
2966         u32 val;
2967
2968         if (!crtc_state->fec_enable)
2969                 return;
2970
2971         intel_dp = enc_to_intel_dp(encoder);
2972         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
2973         val &= ~DP_TP_CTL_FEC_ENABLE;
2974         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
2975         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
2976 }
2977
2978 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
2979                                   const struct intel_crtc_state *crtc_state,
2980                                   const struct drm_connector_state *conn_state)
2981 {
2982         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2983         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2984         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2985         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2986         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2987         int level = intel_ddi_dp_level(intel_dp);
2988         enum transcoder transcoder = crtc_state->cpu_transcoder;
2989
2990         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2991                                  crtc_state->lane_count, is_mst);
2992
2993         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
2994         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
2995
2996         /*
2997          * 1. Enable Power Wells
2998          *
2999          * This was handled at the beginning of intel_atomic_commit_tail(),
3000          * before we called down into this function.
3001          */
3002
3003         /* 2. Enable Panel Power if PPS is required */
3004         intel_edp_panel_on(intel_dp);
3005
3006         /*
3007          * 3. For non-TBT Type-C ports, set FIA lane count
3008          * (DFLEXDPSP.DPX4TXLATC)
3009          *
3010          * This was done before tgl_ddi_pre_enable_dp by
3011          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3012          */
3013
3014         /*
3015          * 4. Enable the port PLL.
3016          *
3017          * The PLL enabling itself was already done before this function by
3018          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
3019          * configure the PLL to port mapping here.
3020          */
3021         intel_ddi_clk_select(encoder, crtc_state);
3022
3023         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3024         if (!intel_phy_is_tc(dev_priv, phy) ||
3025             dig_port->tc_mode != TC_PORT_TBT_ALT)
3026                 intel_display_power_get(dev_priv,
3027                                         dig_port->ddi_io_power_domain);
3028
3029         /* 6. Program DP_MODE */
3030         icl_program_mg_dp_mode(dig_port, crtc_state);
3031
3032         /*
3033          * 7. The rest of the below are substeps under the bspec's "Enable and
3034          * Train Display Port" step.  Note that steps that are specific to
3035          * MST will be handled by intel_mst_pre_enable_dp() before/after it
3036          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
3037          * us when active_mst_links==0, so any steps designated for "single
3038          * stream or multi-stream master transcoder" can just be performed
3039          * unconditionally here.
3040          */
3041
3042         /*
3043          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3044          * Transcoder.
3045          */
3046         intel_ddi_enable_pipe_clock(crtc_state);
3047
3048         /*
3049          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3050          * Transport Select
3051          */
3052         intel_ddi_config_transcoder_func(crtc_state);
3053
3054         /*
3055          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3056          * selected
3057          *
3058          * This will be handled by the intel_dp_start_link_train() farther
3059          * down this function.
3060          */
3061
3062         /* 7.e Configure voltage swing and related IO settings */
3063         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3064                                 encoder->type);
3065
3066         /*
3067          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3068          * the used lanes of the DDI.
3069          */
3070         if (intel_phy_is_combo(dev_priv, phy)) {
3071                 bool lane_reversal =
3072                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3073
3074                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3075                                                crtc_state->lane_count,
3076                                                lane_reversal);
3077         }
3078
3079         /*
3080          * 7.g Configure and enable DDI_BUF_CTL
3081          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3082          *     after 500 us.
3083          *
3084          * We only configure what the register value will be here.  Actual
3085          * enabling happens during link training farther down.
3086          */
3087         intel_ddi_init_dp_buf_reg(encoder);
3088
3089         if (!is_mst)
3090                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3091
3092         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3093         /*
3094          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3095          * in the FEC_CONFIGURATION register to 1 before initiating link
3096          * training
3097          */
3098         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3099
3100         /*
3101          * 7.i Follow DisplayPort specification training sequence (see notes for
3102          *     failure handling)
3103          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3104          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3105          *     (timeout after 800 us)
3106          */
3107         intel_dp_start_link_train(intel_dp);
3108
3109         /* 7.k Set DP_TP_CTL link training to Normal */
3110         if (!is_trans_port_sync_mode(crtc_state))
3111                 intel_dp_stop_link_train(intel_dp);
3112
3113         /* 7.l Configure and enable FEC if needed */
3114         intel_ddi_enable_fec(encoder, crtc_state);
3115         intel_dsc_enable(encoder, crtc_state);
3116 }
3117
3118 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3119                                   const struct intel_crtc_state *crtc_state,
3120                                   const struct drm_connector_state *conn_state)
3121 {
3122         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3123         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3124         enum port port = encoder->port;
3125         enum phy phy = intel_port_to_phy(dev_priv, port);
3126         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3127         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3128         int level = intel_ddi_dp_level(intel_dp);
3129
3130         if (INTEL_GEN(dev_priv) < 11)
3131                 drm_WARN_ON(&dev_priv->drm,
3132                             is_mst && (port == PORT_A || port == PORT_E));
3133         else
3134                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3135
3136         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3137                                  crtc_state->lane_count, is_mst);
3138
3139         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3140         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3141
3142         intel_edp_panel_on(intel_dp);
3143
3144         intel_ddi_clk_select(encoder, crtc_state);
3145
3146         if (!intel_phy_is_tc(dev_priv, phy) ||
3147             dig_port->tc_mode != TC_PORT_TBT_ALT)
3148                 intel_display_power_get(dev_priv,
3149                                         dig_port->ddi_io_power_domain);
3150
3151         icl_program_mg_dp_mode(dig_port, crtc_state);
3152
3153         if (INTEL_GEN(dev_priv) >= 11)
3154                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3155                                         level, encoder->type);
3156         else if (IS_CANNONLAKE(dev_priv))
3157                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3158         else if (IS_GEN9_LP(dev_priv))
3159                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3160         else
3161                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3162
3163         if (intel_phy_is_combo(dev_priv, phy)) {
3164                 bool lane_reversal =
3165                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3166
3167                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3168                                                crtc_state->lane_count,
3169                                                lane_reversal);
3170         }
3171
3172         intel_ddi_init_dp_buf_reg(encoder);
3173         if (!is_mst)
3174                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3175         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3176                                               true);
3177         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3178         intel_dp_start_link_train(intel_dp);
3179         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3180             !is_trans_port_sync_mode(crtc_state))
3181                 intel_dp_stop_link_train(intel_dp);
3182
3183         intel_ddi_enable_fec(encoder, crtc_state);
3184
3185         if (!is_mst)
3186                 intel_ddi_enable_pipe_clock(crtc_state);
3187
3188         intel_dsc_enable(encoder, crtc_state);
3189 }
3190
3191 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3192                                     const struct intel_crtc_state *crtc_state,
3193                                     const struct drm_connector_state *conn_state)
3194 {
3195         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3196
3197         if (INTEL_GEN(dev_priv) >= 12)
3198                 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3199         else
3200                 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3201
3202         /* MST will call a setting of MSA after an allocating of Virtual Channel
3203          * from MST encoder pre_enable callback.
3204          */
3205         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3206                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3207
3208                 intel_dp_set_m_n(crtc_state, M1_N1);
3209         }
3210 }
3211
3212 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3213                                       const struct intel_crtc_state *crtc_state,
3214                                       const struct drm_connector_state *conn_state)
3215 {
3216         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3217         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3219         int level = intel_ddi_hdmi_level(encoder);
3220         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3221
3222         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3223         intel_ddi_clk_select(encoder, crtc_state);
3224
3225         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3226
3227         icl_program_mg_dp_mode(dig_port, crtc_state);
3228
3229         if (INTEL_GEN(dev_priv) >= 12)
3230                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3231                                         level, INTEL_OUTPUT_HDMI);
3232         else if (INTEL_GEN(dev_priv) == 11)
3233                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3234                                         level, INTEL_OUTPUT_HDMI);
3235         else if (IS_CANNONLAKE(dev_priv))
3236                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3237         else if (IS_GEN9_LP(dev_priv))
3238                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3239         else
3240                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3241
3242         if (IS_GEN9_BC(dev_priv))
3243                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3244
3245         intel_ddi_enable_pipe_clock(crtc_state);
3246
3247         intel_dig_port->set_infoframes(encoder,
3248                                        crtc_state->has_infoframe,
3249                                        crtc_state, conn_state);
3250 }
3251
3252 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3253                                  const struct intel_crtc_state *crtc_state,
3254                                  const struct drm_connector_state *conn_state)
3255 {
3256         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3257         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3258         enum pipe pipe = crtc->pipe;
3259
3260         /*
3261          * When called from DP MST code:
3262          * - conn_state will be NULL
3263          * - encoder will be the main encoder (ie. mst->primary)
3264          * - the main connector associated with this port
3265          *   won't be active or linked to a crtc
3266          * - crtc_state will be the state of the first stream to
3267          *   be activated on this port, and it may not be the same
3268          *   stream that will be deactivated last, but each stream
3269          *   should have a state that is identical when it comes to
3270          *   the DP link parameteres
3271          */
3272
3273         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3274
3275         if (INTEL_GEN(dev_priv) >= 11)
3276                 icl_map_plls_to_ports(encoder, crtc_state);
3277
3278         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3279
3280         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3281                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3282         } else {
3283                 struct intel_lspcon *lspcon =
3284                                 enc_to_intel_lspcon(encoder);
3285
3286                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3287                 if (lspcon->active) {
3288                         struct intel_digital_port *dig_port =
3289                                         enc_to_dig_port(encoder);
3290
3291                         dig_port->set_infoframes(encoder,
3292                                                  crtc_state->has_infoframe,
3293                                                  crtc_state, conn_state);
3294                 }
3295         }
3296 }
3297
3298 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3299                                   const struct intel_crtc_state *crtc_state)
3300 {
3301         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3302         enum port port = encoder->port;
3303         bool wait = false;
3304         u32 val;
3305
3306         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3307         if (val & DDI_BUF_CTL_ENABLE) {
3308                 val &= ~DDI_BUF_CTL_ENABLE;
3309                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3310                 wait = true;
3311         }
3312
3313         if (intel_crtc_has_dp_encoder(crtc_state)) {
3314                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3315
3316                 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3317                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3318                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3319                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3320         }
3321
3322         /* Disable FEC in DP Sink */
3323         intel_ddi_disable_fec_state(encoder, crtc_state);
3324
3325         if (wait)
3326                 intel_wait_ddi_buf_idle(dev_priv, port);
3327 }
3328
3329 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3330                                       const struct intel_crtc_state *old_crtc_state,
3331                                       const struct drm_connector_state *old_conn_state)
3332 {
3333         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3334         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3335         struct intel_dp *intel_dp = &dig_port->dp;
3336         bool is_mst = intel_crtc_has_type(old_crtc_state,
3337                                           INTEL_OUTPUT_DP_MST);
3338         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3339
3340         /*
3341          * Power down sink before disabling the port, otherwise we end
3342          * up getting interrupts from the sink on detecting link loss.
3343          */
3344         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3345
3346         if (INTEL_GEN(dev_priv) >= 12) {
3347                 if (is_mst) {
3348                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3349                         u32 val;
3350
3351                         val = intel_de_read(dev_priv,
3352                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
3353                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
3354                                  TRANS_DDI_MODE_SELECT_MASK);
3355                         intel_de_write(dev_priv,
3356                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
3357                                        val);
3358                 }
3359         } else {
3360                 if (!is_mst)
3361                         intel_ddi_disable_pipe_clock(old_crtc_state);
3362         }
3363
3364         intel_disable_ddi_buf(encoder, old_crtc_state);
3365
3366         /*
3367          * From TGL spec: "If single stream or multi-stream master transcoder:
3368          * Configure Transcoder Clock select to direct no clock to the
3369          * transcoder"
3370          */
3371         if (INTEL_GEN(dev_priv) >= 12)
3372                 intel_ddi_disable_pipe_clock(old_crtc_state);
3373
3374         intel_edp_panel_vdd_on(intel_dp);
3375         intel_edp_panel_off(intel_dp);
3376
3377         if (!intel_phy_is_tc(dev_priv, phy) ||
3378             dig_port->tc_mode != TC_PORT_TBT_ALT)
3379                 intel_display_power_put_unchecked(dev_priv,
3380                                                   dig_port->ddi_io_power_domain);
3381
3382         intel_ddi_clk_disable(encoder);
3383 }
3384
3385 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3386                                         const struct intel_crtc_state *old_crtc_state,
3387                                         const struct drm_connector_state *old_conn_state)
3388 {
3389         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3390         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3391         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3392
3393         dig_port->set_infoframes(encoder, false,
3394                                  old_crtc_state, old_conn_state);
3395
3396         intel_ddi_disable_pipe_clock(old_crtc_state);
3397
3398         intel_disable_ddi_buf(encoder, old_crtc_state);
3399
3400         intel_display_power_put_unchecked(dev_priv,
3401                                           dig_port->ddi_io_power_domain);
3402
3403         intel_ddi_clk_disable(encoder);
3404
3405         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3406 }
3407
3408 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
3409 {
3410         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3411         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3412
3413         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
3414                 return;
3415
3416         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
3417                       transcoder_name(old_crtc_state->cpu_transcoder));
3418
3419         intel_de_write(dev_priv,
3420                        TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0);
3421 }
3422
3423 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3424                                    const struct intel_crtc_state *old_crtc_state,
3425                                    const struct drm_connector_state *old_conn_state)
3426 {
3427         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3428         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3429         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3430         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3431
3432         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3433                 intel_crtc_vblank_off(old_crtc_state);
3434
3435                 intel_disable_pipe(old_crtc_state);
3436
3437                 if (INTEL_GEN(dev_priv) >= 11)
3438                         icl_disable_transcoder_port_sync(old_crtc_state);
3439
3440                 intel_ddi_disable_transcoder_func(old_crtc_state);
3441
3442                 intel_dsc_disable(old_crtc_state);
3443
3444                 if (INTEL_GEN(dev_priv) >= 9)
3445                         skl_scaler_disable(old_crtc_state);
3446                 else
3447                         ilk_pfit_disable(old_crtc_state);
3448         }
3449
3450         /*
3451          * When called from DP MST code:
3452          * - old_conn_state will be NULL
3453          * - encoder will be the main encoder (ie. mst->primary)
3454          * - the main connector associated with this port
3455          *   won't be active or linked to a crtc
3456          * - old_crtc_state will be the state of the last stream to
3457          *   be deactivated on this port, and it may not be the same
3458          *   stream that was activated last, but each stream
3459          *   should have a state that is identical when it comes to
3460          *   the DP link parameteres
3461          */
3462
3463         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3464                 intel_ddi_post_disable_hdmi(encoder,
3465                                             old_crtc_state, old_conn_state);
3466         else
3467                 intel_ddi_post_disable_dp(encoder,
3468                                           old_crtc_state, old_conn_state);
3469
3470         if (INTEL_GEN(dev_priv) >= 11)
3471                 icl_unmap_plls_to_ports(encoder);
3472
3473         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3474                 intel_display_power_put_unchecked(dev_priv,
3475                                                   intel_ddi_main_link_aux_domain(dig_port));
3476
3477         if (is_tc_port)
3478                 intel_tc_port_put_link(dig_port);
3479 }
3480
3481 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3482                                 const struct intel_crtc_state *old_crtc_state,
3483                                 const struct drm_connector_state *old_conn_state)
3484 {
3485         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3486         u32 val;
3487
3488         /*
3489          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3490          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3491          * step 13 is the correct place for it. Step 18 is where it was
3492          * originally before the BUN.
3493          */
3494         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3495         val &= ~FDI_RX_ENABLE;
3496         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3497
3498         intel_disable_ddi_buf(encoder, old_crtc_state);
3499         intel_ddi_clk_disable(encoder);
3500
3501         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3502         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3503         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3504         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3505
3506         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3507         val &= ~FDI_PCDCLK;
3508         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3509
3510         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3511         val &= ~FDI_RX_PLL_ENABLE;
3512         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3513 }
3514
3515 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3516                                 const struct intel_crtc_state *crtc_state,
3517                                 const struct drm_connector_state *conn_state)
3518 {
3519         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3520         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3521         enum port port = encoder->port;
3522
3523         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3524                 intel_dp_stop_link_train(intel_dp);
3525
3526         intel_edp_backlight_on(crtc_state, conn_state);
3527         intel_psr_enable(intel_dp, crtc_state);
3528         intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3529         intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3530         intel_edp_drrs_enable(intel_dp, crtc_state);
3531
3532         if (crtc_state->has_audio)
3533                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3534 }
3535
3536 static i915_reg_t
3537 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3538                                enum port port)
3539 {
3540         static const enum transcoder trans[] = {
3541                 [PORT_A] = TRANSCODER_EDP,
3542                 [PORT_B] = TRANSCODER_A,
3543                 [PORT_C] = TRANSCODER_B,
3544                 [PORT_D] = TRANSCODER_C,
3545                 [PORT_E] = TRANSCODER_A,
3546         };
3547
3548         drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
3549
3550         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3551                 port = PORT_A;
3552
3553         return CHICKEN_TRANS(trans[port]);
3554 }
3555
3556 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3557                                   const struct intel_crtc_state *crtc_state,
3558                                   const struct drm_connector_state *conn_state)
3559 {
3560         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3561         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3562         struct drm_connector *connector = conn_state->connector;
3563         enum port port = encoder->port;
3564
3565         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3566                                                crtc_state->hdmi_high_tmds_clock_ratio,
3567                                                crtc_state->hdmi_scrambling))
3568                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3569                           connector->base.id, connector->name);
3570
3571         /* Display WA #1143: skl,kbl,cfl */
3572         if (IS_GEN9_BC(dev_priv)) {
3573                 /*
3574                  * For some reason these chicken bits have been
3575                  * stuffed into a transcoder register, event though
3576                  * the bits affect a specific DDI port rather than
3577                  * a specific transcoder.
3578                  */
3579                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3580                 u32 val;
3581
3582                 val = intel_de_read(dev_priv, reg);
3583
3584                 if (port == PORT_E)
3585                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3586                                 DDIE_TRAINING_OVERRIDE_VALUE;
3587                 else
3588                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3589                                 DDI_TRAINING_OVERRIDE_VALUE;
3590
3591                 intel_de_write(dev_priv, reg, val);
3592                 intel_de_posting_read(dev_priv, reg);
3593
3594                 udelay(1);
3595
3596                 if (port == PORT_E)
3597                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3598                                  DDIE_TRAINING_OVERRIDE_VALUE);
3599                 else
3600                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3601                                  DDI_TRAINING_OVERRIDE_VALUE);
3602
3603                 intel_de_write(dev_priv, reg, val);
3604         }
3605
3606         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3607          * are ignored so nothing special needs to be done besides
3608          * enabling the port.
3609          */
3610         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3611                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3612
3613         if (crtc_state->has_audio)
3614                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3615 }
3616
3617 static void intel_enable_ddi(struct intel_encoder *encoder,
3618                              const struct intel_crtc_state *crtc_state,
3619                              const struct drm_connector_state *conn_state)
3620 {
3621         WARN_ON(crtc_state->has_pch_encoder);
3622
3623         intel_enable_pipe(crtc_state);
3624
3625         intel_crtc_vblank_on(crtc_state);
3626
3627         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3628                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3629         else
3630                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3631
3632         /* Enable hdcp if it's desired */
3633         if (conn_state->content_protection ==
3634             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3635                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3636                                   crtc_state->cpu_transcoder,
3637                                   (u8)conn_state->hdcp_content_type);
3638 }
3639
3640 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3641                                  const struct intel_crtc_state *old_crtc_state,
3642                                  const struct drm_connector_state *old_conn_state)
3643 {
3644         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3645
3646         intel_dp->link_trained = false;
3647
3648         if (old_crtc_state->has_audio)
3649                 intel_audio_codec_disable(encoder,
3650                                           old_crtc_state, old_conn_state);
3651
3652         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3653         intel_psr_disable(intel_dp, old_crtc_state);
3654         intel_edp_backlight_off(old_conn_state);
3655         /* Disable the decompression in DP Sink */
3656         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3657                                               false);
3658 }
3659
3660 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3661                                    const struct intel_crtc_state *old_crtc_state,
3662                                    const struct drm_connector_state *old_conn_state)
3663 {
3664         struct drm_connector *connector = old_conn_state->connector;
3665
3666         if (old_crtc_state->has_audio)
3667                 intel_audio_codec_disable(encoder,
3668                                           old_crtc_state, old_conn_state);
3669
3670         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3671                                                false, false))
3672                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3673                               connector->base.id, connector->name);
3674 }
3675
3676 static void intel_disable_ddi(struct intel_encoder *encoder,
3677                               const struct intel_crtc_state *old_crtc_state,
3678                               const struct drm_connector_state *old_conn_state)
3679 {
3680         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3681
3682         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3683                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3684         else
3685                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3686 }
3687
3688 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3689                                      const struct intel_crtc_state *crtc_state,
3690                                      const struct drm_connector_state *conn_state)
3691 {
3692         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3693
3694         intel_ddi_set_dp_msa(crtc_state, conn_state);
3695
3696         intel_psr_update(intel_dp, crtc_state);
3697         intel_edp_drrs_enable(intel_dp, crtc_state);
3698
3699         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3700 }
3701
3702 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3703                                   const struct intel_crtc_state *crtc_state,
3704                                   const struct drm_connector_state *conn_state)
3705 {
3706
3707         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3708                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3709
3710         intel_hdcp_update_pipe(encoder, crtc_state, conn_state);
3711 }
3712
3713 static void
3714 intel_ddi_update_prepare(struct intel_atomic_state *state,
3715                          struct intel_encoder *encoder,
3716                          struct intel_crtc *crtc)
3717 {
3718         struct intel_crtc_state *crtc_state =
3719                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3720         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3721
3722         WARN_ON(crtc && crtc->active);
3723
3724         intel_tc_port_get_link(enc_to_dig_port(encoder),
3725                                required_lanes);
3726         if (crtc_state && crtc_state->hw.active)
3727                 intel_update_active_dpll(state, crtc, encoder);
3728 }
3729
3730 static void
3731 intel_ddi_update_complete(struct intel_atomic_state *state,
3732                           struct intel_encoder *encoder,
3733                           struct intel_crtc *crtc)
3734 {
3735         intel_tc_port_put_link(enc_to_dig_port(encoder));
3736 }
3737
3738 static void
3739 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3740                          const struct intel_crtc_state *crtc_state,
3741                          const struct drm_connector_state *conn_state)
3742 {
3743         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3744         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3745         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3746         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3747
3748         if (is_tc_port)
3749                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3750
3751         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3752                 intel_display_power_get(dev_priv,
3753                                         intel_ddi_main_link_aux_domain(dig_port));
3754
3755         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3756                 /*
3757                  * Program the lane count for static/dynamic connections on
3758                  * Type-C ports.  Skip this step for TBT.
3759                  */
3760                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3761         else if (IS_GEN9_LP(dev_priv))
3762                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3763                                                 crtc_state->lane_lat_optim_mask);
3764 }
3765
3766 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3767 {
3768         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3769         struct drm_i915_private *dev_priv =
3770                 to_i915(intel_dig_port->base.base.dev);
3771         enum port port = intel_dig_port->base.port;
3772         u32 dp_tp_ctl, ddi_buf_ctl;
3773         bool wait = false;
3774
3775         dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3776
3777         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3778                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3779                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3780                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3781                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3782                         wait = true;
3783                 }
3784
3785                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3786                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3787                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
3788                 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3789
3790                 if (wait)
3791                         intel_wait_ddi_buf_idle(dev_priv, port);
3792         }
3793
3794         dp_tp_ctl = DP_TP_CTL_ENABLE |
3795                     DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3796         if (intel_dp->link_mst)
3797                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3798         else {
3799                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3800                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3801                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3802         }
3803         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
3804         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3805
3806         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3807         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3808         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3809
3810         udelay(600);
3811 }
3812
3813 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3814                                        enum transcoder cpu_transcoder)
3815 {
3816         if (cpu_transcoder == TRANSCODER_EDP)
3817                 return false;
3818
3819         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3820                 return false;
3821
3822         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3823                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3824 }
3825
3826 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3827                                          struct intel_crtc_state *crtc_state)
3828 {
3829         if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3830                 crtc_state->min_voltage_level = 2;
3831         else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
3832                 crtc_state->min_voltage_level = 3;
3833         else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3834                 crtc_state->min_voltage_level = 1;
3835         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3836                 crtc_state->min_voltage_level = 2;
3837 }
3838
3839 void intel_ddi_get_config(struct intel_encoder *encoder,
3840                           struct intel_crtc_state *pipe_config)
3841 {
3842         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3843         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
3844         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3845         u32 temp, flags = 0;
3846
3847         /* XXX: DSI transcoder paranoia */
3848         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3849                 return;
3850
3851         intel_dsc_get_config(encoder, pipe_config);
3852
3853         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3854         if (temp & TRANS_DDI_PHSYNC)
3855                 flags |= DRM_MODE_FLAG_PHSYNC;
3856         else
3857                 flags |= DRM_MODE_FLAG_NHSYNC;
3858         if (temp & TRANS_DDI_PVSYNC)
3859                 flags |= DRM_MODE_FLAG_PVSYNC;
3860         else
3861                 flags |= DRM_MODE_FLAG_NVSYNC;
3862
3863         pipe_config->hw.adjusted_mode.flags |= flags;
3864
3865         switch (temp & TRANS_DDI_BPC_MASK) {
3866         case TRANS_DDI_BPC_6:
3867                 pipe_config->pipe_bpp = 18;
3868                 break;
3869         case TRANS_DDI_BPC_8:
3870                 pipe_config->pipe_bpp = 24;
3871                 break;
3872         case TRANS_DDI_BPC_10:
3873                 pipe_config->pipe_bpp = 30;
3874                 break;
3875         case TRANS_DDI_BPC_12:
3876                 pipe_config->pipe_bpp = 36;
3877                 break;
3878         default:
3879                 break;
3880         }
3881
3882         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3883         case TRANS_DDI_MODE_SELECT_HDMI:
3884                 pipe_config->has_hdmi_sink = true;
3885
3886                 pipe_config->infoframes.enable |=
3887                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3888
3889                 if (pipe_config->infoframes.enable)
3890                         pipe_config->has_infoframe = true;
3891
3892                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3893                         pipe_config->hdmi_scrambling = true;
3894                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3895                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3896                 /* fall through */
3897         case TRANS_DDI_MODE_SELECT_DVI:
3898                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3899                 pipe_config->lane_count = 4;
3900                 break;
3901         case TRANS_DDI_MODE_SELECT_FDI:
3902                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3903                 break;
3904         case TRANS_DDI_MODE_SELECT_DP_SST:
3905                 if (encoder->type == INTEL_OUTPUT_EDP)
3906                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3907                 else
3908                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3909                 pipe_config->lane_count =
3910                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3911                 intel_dp_get_m_n(intel_crtc, pipe_config);
3912
3913                 if (INTEL_GEN(dev_priv) >= 11) {
3914                         i915_reg_t dp_tp_ctl;
3915
3916                         if (IS_GEN(dev_priv, 11))
3917                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
3918                         else
3919                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
3920
3921                         pipe_config->fec_enable =
3922                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3923
3924                         DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
3925                                       encoder->base.base.id, encoder->base.name,
3926                                       pipe_config->fec_enable);
3927                 }
3928
3929                 break;
3930         case TRANS_DDI_MODE_SELECT_DP_MST:
3931                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3932                 pipe_config->lane_count =
3933                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3934
3935                 if (INTEL_GEN(dev_priv) >= 12)
3936                         pipe_config->mst_master_transcoder =
3937                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3938
3939                 intel_dp_get_m_n(intel_crtc, pipe_config);
3940                 break;
3941         default:
3942                 break;
3943         }
3944
3945         pipe_config->has_audio =
3946                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3947
3948         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3949             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3950                 /*
3951                  * This is a big fat ugly hack.
3952                  *
3953                  * Some machines in UEFI boot mode provide us a VBT that has 18
3954                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3955                  * unknown we fail to light up. Yet the same BIOS boots up with
3956                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3957                  * max, not what it tells us to use.
3958                  *
3959                  * Note: This will still be broken if the eDP panel is not lit
3960                  * up by the BIOS, and thus we can't get the mode at module
3961                  * load.
3962                  */
3963                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3964                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3965                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3966         }
3967
3968         intel_ddi_clock_get(encoder, pipe_config);
3969
3970         if (IS_GEN9_LP(dev_priv))
3971                 pipe_config->lane_lat_optim_mask =
3972                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3973
3974         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3975
3976         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3977
3978         intel_read_infoframe(encoder, pipe_config,
3979                              HDMI_INFOFRAME_TYPE_AVI,
3980                              &pipe_config->infoframes.avi);
3981         intel_read_infoframe(encoder, pipe_config,
3982                              HDMI_INFOFRAME_TYPE_SPD,
3983                              &pipe_config->infoframes.spd);
3984         intel_read_infoframe(encoder, pipe_config,
3985                              HDMI_INFOFRAME_TYPE_VENDOR,
3986                              &pipe_config->infoframes.hdmi);
3987         intel_read_infoframe(encoder, pipe_config,
3988                              HDMI_INFOFRAME_TYPE_DRM,
3989                              &pipe_config->infoframes.drm);
3990 }
3991
3992 static enum intel_output_type
3993 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3994                               struct intel_crtc_state *crtc_state,
3995                               struct drm_connector_state *conn_state)
3996 {
3997         switch (conn_state->connector->connector_type) {
3998         case DRM_MODE_CONNECTOR_HDMIA:
3999                 return INTEL_OUTPUT_HDMI;
4000         case DRM_MODE_CONNECTOR_eDP:
4001                 return INTEL_OUTPUT_EDP;
4002         case DRM_MODE_CONNECTOR_DisplayPort:
4003                 return INTEL_OUTPUT_DP;
4004         default:
4005                 MISSING_CASE(conn_state->connector->connector_type);
4006                 return INTEL_OUTPUT_UNUSED;
4007         }
4008 }
4009
4010 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4011                                     struct intel_crtc_state *pipe_config,
4012                                     struct drm_connector_state *conn_state)
4013 {
4014         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4015         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4016         enum port port = encoder->port;
4017         int ret;
4018
4019         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
4020                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4021
4022         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4023                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4024         } else {
4025                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4026         }
4027
4028         if (ret)
4029                 return ret;
4030
4031         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4032             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4033                 pipe_config->pch_pfit.force_thru =
4034                         pipe_config->pch_pfit.enabled ||
4035                         pipe_config->crc_enabled;
4036
4037         if (IS_GEN9_LP(dev_priv))
4038                 pipe_config->lane_lat_optim_mask =
4039                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4040
4041         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4042
4043         return 0;
4044 }
4045
4046 static bool mode_equal(const struct drm_display_mode *mode1,
4047                        const struct drm_display_mode *mode2)
4048 {
4049         return drm_mode_match(mode1, mode2,
4050                               DRM_MODE_MATCH_TIMINGS |
4051                               DRM_MODE_MATCH_FLAGS |
4052                               DRM_MODE_MATCH_3D_FLAGS) &&
4053                 mode1->clock == mode2->clock; /* we want an exact match */
4054 }
4055
4056 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4057                       const struct intel_link_m_n *m_n_2)
4058 {
4059         return m_n_1->tu == m_n_2->tu &&
4060                 m_n_1->gmch_m == m_n_2->gmch_m &&
4061                 m_n_1->gmch_n == m_n_2->gmch_n &&
4062                 m_n_1->link_m == m_n_2->link_m &&
4063                 m_n_1->link_n == m_n_2->link_n;
4064 }
4065
4066 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4067                                        const struct intel_crtc_state *crtc_state2)
4068 {
4069         return crtc_state1->hw.active && crtc_state2->hw.active &&
4070                 crtc_state1->output_types == crtc_state2->output_types &&
4071                 crtc_state1->output_format == crtc_state2->output_format &&
4072                 crtc_state1->lane_count == crtc_state2->lane_count &&
4073                 crtc_state1->port_clock == crtc_state2->port_clock &&
4074                 mode_equal(&crtc_state1->hw.adjusted_mode,
4075                            &crtc_state2->hw.adjusted_mode) &&
4076                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4077 }
4078
4079 static u8
4080 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4081                                 int tile_group_id)
4082 {
4083         struct drm_connector *connector;
4084         const struct drm_connector_state *conn_state;
4085         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4086         struct intel_atomic_state *state =
4087                 to_intel_atomic_state(ref_crtc_state->uapi.state);
4088         u8 transcoders = 0;
4089         int i;
4090
4091         if (INTEL_GEN(dev_priv) < 11)
4092                 return 0;
4093
4094         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4095                 return 0;
4096
4097         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4098                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4099                 const struct intel_crtc_state *crtc_state;
4100
4101                 if (!crtc)
4102                         continue;
4103
4104                 if (!connector->has_tile ||
4105                     connector->tile_group->id !=
4106                     tile_group_id)
4107                         continue;
4108                 crtc_state = intel_atomic_get_new_crtc_state(state,
4109                                                              crtc);
4110                 if (!crtcs_port_sync_compatible(ref_crtc_state,
4111                                                 crtc_state))
4112                         continue;
4113                 transcoders |= BIT(crtc_state->cpu_transcoder);
4114         }
4115
4116         return transcoders;
4117 }
4118
4119 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4120                                          struct intel_crtc_state *crtc_state,
4121                                          struct drm_connector_state *conn_state)
4122 {
4123         struct drm_connector *connector = conn_state->connector;
4124         u8 port_sync_transcoders = 0;
4125
4126         DRM_DEBUG_KMS("[ENCODER:%d:%s] [CRTC:%d:%s]",
4127                       encoder->base.base.id, encoder->base.name,
4128                       crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4129
4130         if (connector->has_tile)
4131                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4132                                                                         connector->tile_group->id);
4133
4134         /*
4135          * EDP Transcoders cannot be ensalved
4136          * make them a master always when present
4137          */
4138         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4139                 crtc_state->master_transcoder = TRANSCODER_EDP;
4140         else
4141                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4142
4143         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4144                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4145                 crtc_state->sync_mode_slaves_mask =
4146                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4147         }
4148
4149         return 0;
4150 }
4151
4152 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4153 {
4154         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4155
4156         intel_dp_encoder_flush_work(encoder);
4157
4158         drm_encoder_cleanup(encoder);
4159         kfree(dig_port);
4160 }
4161
4162 static const struct drm_encoder_funcs intel_ddi_funcs = {
4163         .reset = intel_dp_encoder_reset,
4164         .destroy = intel_ddi_encoder_destroy,
4165 };
4166
4167 static struct intel_connector *
4168 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4169 {
4170         struct intel_connector *connector;
4171         enum port port = intel_dig_port->base.port;
4172
4173         connector = intel_connector_alloc();
4174         if (!connector)
4175                 return NULL;
4176
4177         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4178         intel_dig_port->dp.prepare_link_retrain =
4179                 intel_ddi_prepare_link_retrain;
4180
4181         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4182                 kfree(connector);
4183                 return NULL;
4184         }
4185
4186         return connector;
4187 }
4188
4189 static int modeset_pipe(struct drm_crtc *crtc,
4190                         struct drm_modeset_acquire_ctx *ctx)
4191 {
4192         struct drm_atomic_state *state;
4193         struct drm_crtc_state *crtc_state;
4194         int ret;
4195
4196         state = drm_atomic_state_alloc(crtc->dev);
4197         if (!state)
4198                 return -ENOMEM;
4199
4200         state->acquire_ctx = ctx;
4201
4202         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4203         if (IS_ERR(crtc_state)) {
4204                 ret = PTR_ERR(crtc_state);
4205                 goto out;
4206         }
4207
4208         crtc_state->connectors_changed = true;
4209
4210         ret = drm_atomic_commit(state);
4211 out:
4212         drm_atomic_state_put(state);
4213
4214         return ret;
4215 }
4216
4217 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4218                                  struct drm_modeset_acquire_ctx *ctx)
4219 {
4220         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4221         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4222         struct intel_connector *connector = hdmi->attached_connector;
4223         struct i2c_adapter *adapter =
4224                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4225         struct drm_connector_state *conn_state;
4226         struct intel_crtc_state *crtc_state;
4227         struct intel_crtc *crtc;
4228         u8 config;
4229         int ret;
4230
4231         if (!connector || connector->base.status != connector_status_connected)
4232                 return 0;
4233
4234         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4235                                ctx);
4236         if (ret)
4237                 return ret;
4238
4239         conn_state = connector->base.state;
4240
4241         crtc = to_intel_crtc(conn_state->crtc);
4242         if (!crtc)
4243                 return 0;
4244
4245         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4246         if (ret)
4247                 return ret;
4248
4249         crtc_state = to_intel_crtc_state(crtc->base.state);
4250
4251         drm_WARN_ON(&dev_priv->drm,
4252                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4253
4254         if (!crtc_state->hw.active)
4255                 return 0;
4256
4257         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4258             !crtc_state->hdmi_scrambling)
4259                 return 0;
4260
4261         if (conn_state->commit &&
4262             !try_wait_for_completion(&conn_state->commit->hw_done))
4263                 return 0;
4264
4265         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4266         if (ret < 0) {
4267                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4268                 return 0;
4269         }
4270
4271         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4272             crtc_state->hdmi_high_tmds_clock_ratio &&
4273             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4274             crtc_state->hdmi_scrambling)
4275                 return 0;
4276
4277         /*
4278          * HDMI 2.0 says that one should not send scrambled data
4279          * prior to configuring the sink scrambling, and that
4280          * TMDS clock/data transmission should be suspended when
4281          * changing the TMDS clock rate in the sink. So let's
4282          * just do a full modeset here, even though some sinks
4283          * would be perfectly happy if were to just reconfigure
4284          * the SCDC settings on the fly.
4285          */
4286         return modeset_pipe(&crtc->base, ctx);
4287 }
4288
4289 static enum intel_hotplug_state
4290 intel_ddi_hotplug(struct intel_encoder *encoder,
4291                   struct intel_connector *connector,
4292                   bool irq_received)
4293 {
4294         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4295         struct drm_modeset_acquire_ctx ctx;
4296         enum intel_hotplug_state state;
4297         int ret;
4298
4299         state = intel_encoder_hotplug(encoder, connector, irq_received);
4300
4301         drm_modeset_acquire_init(&ctx, 0);
4302
4303         for (;;) {
4304                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4305                         ret = intel_hdmi_reset_link(encoder, &ctx);
4306                 else
4307                         ret = intel_dp_retrain_link(encoder, &ctx);
4308
4309                 if (ret == -EDEADLK) {
4310                         drm_modeset_backoff(&ctx);
4311                         continue;
4312                 }
4313
4314                 break;
4315         }
4316
4317         drm_modeset_drop_locks(&ctx);
4318         drm_modeset_acquire_fini(&ctx);
4319         drm_WARN(encoder->base.dev, ret,
4320                  "Acquiring modeset locks failed with %i\n", ret);
4321
4322         /*
4323          * Unpowered type-c dongles can take some time to boot and be
4324          * responsible, so here giving some time to those dongles to power up
4325          * and then retrying the probe.
4326          *
4327          * On many platforms the HDMI live state signal is known to be
4328          * unreliable, so we can't use it to detect if a sink is connected or
4329          * not. Instead we detect if it's connected based on whether we can
4330          * read the EDID or not. That in turn has a problem during disconnect,
4331          * since the HPD interrupt may be raised before the DDC lines get
4332          * disconnected (due to how the required length of DDC vs. HPD
4333          * connector pins are specified) and so we'll still be able to get a
4334          * valid EDID. To solve this schedule another detection cycle if this
4335          * time around we didn't detect any change in the sink's connection
4336          * status.
4337          */
4338         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4339             !dig_port->dp.is_mst)
4340                 state = INTEL_HOTPLUG_RETRY;
4341
4342         return state;
4343 }
4344
4345 static struct intel_connector *
4346 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4347 {
4348         struct intel_connector *connector;
4349         enum port port = intel_dig_port->base.port;
4350
4351         connector = intel_connector_alloc();
4352         if (!connector)
4353                 return NULL;
4354
4355         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4356         intel_hdmi_init_connector(intel_dig_port, connector);
4357
4358         return connector;
4359 }
4360
4361 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4362 {
4363         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4364
4365         if (dport->base.port != PORT_A)
4366                 return false;
4367
4368         if (dport->saved_port_bits & DDI_A_4_LANES)
4369                 return false;
4370
4371         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4372          *                     supported configuration
4373          */
4374         if (IS_GEN9_LP(dev_priv))
4375                 return true;
4376
4377         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4378          *             one who does also have a full A/E split called
4379          *             DDI_F what makes DDI_E useless. However for this
4380          *             case let's trust VBT info.
4381          */
4382         if (IS_CANNONLAKE(dev_priv) &&
4383             !intel_bios_is_port_present(dev_priv, PORT_E))
4384                 return true;
4385
4386         return false;
4387 }
4388
4389 static int
4390 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4391 {
4392         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4393         enum port port = intel_dport->base.port;
4394         int max_lanes = 4;
4395
4396         if (INTEL_GEN(dev_priv) >= 11)
4397                 return max_lanes;
4398
4399         if (port == PORT_A || port == PORT_E) {
4400                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4401                         max_lanes = port == PORT_A ? 4 : 0;
4402                 else
4403                         /* Both A and E share 2 lanes */
4404                         max_lanes = 2;
4405         }
4406
4407         /*
4408          * Some BIOS might fail to set this bit on port A if eDP
4409          * wasn't lit up at boot.  Force this bit set when needed
4410          * so we use the proper lane count for our calculations.
4411          */
4412         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4413                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4414                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4415                 max_lanes = 4;
4416         }
4417
4418         return max_lanes;
4419 }
4420
4421 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4422 {
4423         struct intel_digital_port *intel_dig_port;
4424         struct intel_encoder *encoder;
4425         bool init_hdmi, init_dp, init_lspcon = false;
4426         enum phy phy = intel_port_to_phy(dev_priv, port);
4427
4428         init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
4429                 intel_bios_port_supports_hdmi(dev_priv, port);
4430         init_dp = intel_bios_port_supports_dp(dev_priv, port);
4431
4432         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4433                 /*
4434                  * Lspcon device needs to be driven with DP connector
4435                  * with special detection sequence. So make sure DP
4436                  * is initialized before lspcon.
4437                  */
4438                 init_dp = true;
4439                 init_lspcon = true;
4440                 init_hdmi = false;
4441                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4442         }
4443
4444         if (!init_dp && !init_hdmi) {
4445                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4446                               port_name(port));
4447                 return;
4448         }
4449
4450         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4451         if (!intel_dig_port)
4452                 return;
4453
4454         encoder = &intel_dig_port->base;
4455
4456         drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4457                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4458
4459         encoder->hotplug = intel_ddi_hotplug;
4460         encoder->compute_output_type = intel_ddi_compute_output_type;
4461         encoder->compute_config = intel_ddi_compute_config;
4462         encoder->compute_config_late = intel_ddi_compute_config_late;
4463         encoder->enable = intel_enable_ddi;
4464         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4465         encoder->pre_enable = intel_ddi_pre_enable;
4466         encoder->disable = intel_disable_ddi;
4467         encoder->post_disable = intel_ddi_post_disable;
4468         encoder->update_pipe = intel_ddi_update_pipe;
4469         encoder->get_hw_state = intel_ddi_get_hw_state;
4470         encoder->get_config = intel_ddi_get_config;
4471         encoder->suspend = intel_dp_encoder_suspend;
4472         encoder->get_power_domains = intel_ddi_get_power_domains;
4473
4474         encoder->type = INTEL_OUTPUT_DDI;
4475         encoder->power_domain = intel_port_to_power_domain(port);
4476         encoder->port = port;
4477         encoder->cloneable = 0;
4478         encoder->pipe_mask = ~0;
4479
4480         if (INTEL_GEN(dev_priv) >= 11)
4481                 intel_dig_port->saved_port_bits = intel_de_read(dev_priv,
4482                                                                 DDI_BUF_CTL(port)) &
4483                         DDI_BUF_PORT_REVERSAL;
4484         else
4485                 intel_dig_port->saved_port_bits = intel_de_read(dev_priv,
4486                                                                 DDI_BUF_CTL(port)) &
4487                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4488
4489         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4490         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4491         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4492
4493         if (intel_phy_is_tc(dev_priv, phy)) {
4494                 bool is_legacy =
4495                         !intel_bios_port_supports_typec_usb(dev_priv, port) &&
4496                         !intel_bios_port_supports_tbt(dev_priv, port);
4497
4498                 intel_tc_port_init(intel_dig_port, is_legacy);
4499
4500                 encoder->update_prepare = intel_ddi_update_prepare;
4501                 encoder->update_complete = intel_ddi_update_complete;
4502         }
4503
4504         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4505         intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4506                                               port - PORT_A;
4507
4508         if (init_dp) {
4509                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4510                         goto err;
4511
4512                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4513         }
4514
4515         /* In theory we don't need the encoder->type check, but leave it just in
4516          * case we have some really bad VBTs... */
4517         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4518                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4519                         goto err;
4520         }
4521
4522         if (init_lspcon) {
4523                 if (lspcon_init(intel_dig_port))
4524                         /* TODO: handle hdmi info frame part */
4525                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4526                                 port_name(port));
4527                 else
4528                         /*
4529                          * LSPCON init faied, but DP init was success, so
4530                          * lets try to drive as DP++ port.
4531                          */
4532                         DRM_ERROR("LSPCON init failed on port %c\n",
4533                                 port_name(port));
4534         }
4535
4536         intel_infoframe_init(intel_dig_port);
4537
4538         return;
4539
4540 err:
4541         drm_encoder_cleanup(&encoder->base);
4542         kfree(intel_dig_port);
4543 }