drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_audio.h"
  33 #include "intel_combo_phy.h"
  34 #include "intel_connector.h"
  35 #include "intel_ddi.h"
  36 #include "intel_ddi_buf_trans.h"
  37 #include "intel_display_types.h"
  38 #include "intel_dp.h"
  39 #include "intel_dp_link_training.h"
  40 #include "intel_dp_mst.h"
  41 #include "intel_dpio_phy.h"
  42 #include "intel_dsi.h"
  43 #include "intel_fdi.h"
  44 #include "intel_fifo_underrun.h"
  45 #include "intel_gmbus.h"
  46 #include "intel_hdcp.h"
  47 #include "intel_hdmi.h"
  48 #include "intel_hotplug.h"
  49 #include "intel_lspcon.h"
  50 #include "intel_panel.h"
  51 #include "intel_pps.h"
  52 #include "intel_psr.h"
  53 #include "intel_sprite.h"
  54 #include "intel_tc.h"
  55 #include "intel_vdsc.h"
  56 #include "intel_vrr.h"
  57 #include "skl_scaler.h"
  58 #include "skl_universal_plane.h"
  59
  60 static const u8 index_to_dp_signal_levels[] = {
  61         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  62         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  63         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  64         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  65         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  66         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  67         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  68         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  70         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  71 };
  72
  73 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  74                                 const struct intel_crtc_state *crtc_state)
  75 {
  76         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  77         int n_entries, level, default_entry;
  78
  79         n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry);
  80         if (n_entries == 0)
  81                 return 0;
  82         level = intel_bios_hdmi_level_shift(encoder);
  83         if (level < 0)
  84                 level = default_entry;
  85
  86         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
  87                 level = n_entries - 1;
  88
  89         return level;
  90 }
  91
  92 /*
  93  * Starting with Haswell, DDI port buffers must be programmed with correct
  94  * values in advance. This function programs the correct values for
  95  * DP/eDP/FDI use cases.
  96  */
  97 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
  98                                   const struct intel_crtc_state *crtc_state)
  99 {
 100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 101         u32 iboost_bit = 0;
 102         int i, n_entries;
 103         enum port port = encoder->port;
 104         const struct ddi_buf_trans *ddi_translations;
 105
 106         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 107                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 108                                                                &n_entries);
 109         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 110                 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
 111                                                                &n_entries);
 112         else
 113                 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
 114                                                               &n_entries);
 115
 116         /* If we're boosting the current, set bit 31 of trans1 */
 117         if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
 118                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 119
 120         for (i = 0; i < n_entries; i++) {
 121                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 122                                ddi_translations[i].trans1 | iboost_bit);
 123                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 124                                ddi_translations[i].trans2);
 125         }
 126 }
 127
 128 /*
 129  * Starting with Haswell, DDI port buffers must be programmed with correct
 130  * values in advance. This function programs the correct values for
 131  * HDMI/DVI use cases.
 132  */
 133 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 134                                            int level)
 135 {
 136         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 137         u32 iboost_bit = 0;
 138         int n_entries;
 139         enum port port = encoder->port;
 140         const struct ddi_buf_trans *ddi_translations;
 141
 142         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
 143
 144         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 145                 return;
 146         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 147                 level = n_entries - 1;
 148
 149         /* If we're boosting the current, set bit 31 of trans1 */
 150         if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
 151                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 152
 153         /* Entry 9 is for HDMI: */
 154         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 155                        ddi_translations[level].trans1 | iboost_bit);
 156         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 157                        ddi_translations[level].trans2);
 158 }
 159
 160 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 161                              enum port port)
 162 {
 163         if (IS_BROXTON(dev_priv)) {
 164                 udelay(16);
 165                 return;
 166         }
 167
 168         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 169                          DDI_BUF_IS_IDLE), 8))
 170                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 171                         port_name(port));
 172 }
 173
 174 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 175                                       enum port port)
 176 {
 177         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 178         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
 179                 usleep_range(518, 1000);
 180                 return;
 181         }
 182
 183         if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 184                           DDI_BUF_IS_IDLE), 500))
 185                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 186                         port_name(port));
 187 }
 188
 189 u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 190 {
 191         switch (pll->info->id) {
 192         case DPLL_ID_WRPLL1:
 193                 return PORT_CLK_SEL_WRPLL1;
 194         case DPLL_ID_WRPLL2:
 195                 return PORT_CLK_SEL_WRPLL2;
 196         case DPLL_ID_SPLL:
 197                 return PORT_CLK_SEL_SPLL;
 198         case DPLL_ID_LCPLL_810:
 199                 return PORT_CLK_SEL_LCPLL_810;
 200         case DPLL_ID_LCPLL_1350:
 201                 return PORT_CLK_SEL_LCPLL_1350;
 202         case DPLL_ID_LCPLL_2700:
 203                 return PORT_CLK_SEL_LCPLL_2700;
 204         default:
 205                 MISSING_CASE(pll->info->id);
 206                 return PORT_CLK_SEL_NONE;
 207         }
 208 }
 209
 210 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 211                                   const struct intel_crtc_state *crtc_state)
 212 {
 213         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 214         int clock = crtc_state->port_clock;
 215         const enum intel_dpll_id id = pll->info->id;
 216
 217         switch (id) {
 218         default:
 219                 /*
 220                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 221                  * here, so do warn if this get passed in
 222                  */
 223                 MISSING_CASE(id);
 224                 return DDI_CLK_SEL_NONE;
 225         case DPLL_ID_ICL_TBTPLL:
 226                 switch (clock) {
 227                 case 162000:
 228                         return DDI_CLK_SEL_TBT_162;
 229                 case 270000:
 230                         return DDI_CLK_SEL_TBT_270;
 231                 case 540000:
 232                         return DDI_CLK_SEL_TBT_540;
 233                 case 810000:
 234                         return DDI_CLK_SEL_TBT_810;
 235                 default:
 236                         MISSING_CASE(clock);
 237                         return DDI_CLK_SEL_NONE;
 238                 }
 239         case DPLL_ID_ICL_MGPLL1:
 240         case DPLL_ID_ICL_MGPLL2:
 241         case DPLL_ID_ICL_MGPLL3:
 242         case DPLL_ID_ICL_MGPLL4:
 243         case DPLL_ID_TGL_MGPLL5:
 244         case DPLL_ID_TGL_MGPLL6:
 245                 return DDI_CLK_SEL_MG;
 246         }
 247 }
 248
 249 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 250                                       const struct intel_crtc_state *crtc_state)
 251 {
 252         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 253         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 254
 255         intel_dp->DP = dig_port->saved_port_bits |
 256                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 257         intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 258 }
 259
 260 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 261                                  enum port port)
 262 {
 263         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 264
 265         switch (val) {
 266         case DDI_CLK_SEL_NONE:
 267                 return 0;
 268         case DDI_CLK_SEL_TBT_162:
 269                 return 162000;
 270         case DDI_CLK_SEL_TBT_270:
 271                 return 270000;
 272         case DDI_CLK_SEL_TBT_540:
 273                 return 540000;
 274         case DDI_CLK_SEL_TBT_810:
 275                 return 810000;
 276         default:
 277                 MISSING_CASE(val);
 278                 return 0;
 279         }
 280 }
 281
 282 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 283 {
 284         int dotclock;
 285
 286         if (pipe_config->has_pch_encoder)
 287                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 288                                                     &pipe_config->fdi_m_n);
 289         else if (intel_crtc_has_dp_encoder(pipe_config))
 290                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 291                                                     &pipe_config->dp_m_n);
 292         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
 293                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
 294         else
 295                 dotclock = pipe_config->port_clock;
 296
 297         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
 298             !intel_crtc_has_dp_encoder(pipe_config))
 299                 dotclock *= 2;
 300
 301         if (pipe_config->pixel_multiplier)
 302                 dotclock /= pipe_config->pixel_multiplier;
 303
 304         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 305 }
 306
 307 static void intel_ddi_clock_get(struct intel_encoder *encoder,
 308                                 struct intel_crtc_state *pipe_config)
 309 {
 310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 311         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 312
 313         if (intel_phy_is_tc(dev_priv, phy) &&
 314             intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
 315             DPLL_ID_ICL_TBTPLL)
 316                 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
 317                                                                 encoder->port);
 318         else
 319                 pipe_config->port_clock =
 320                         intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll,
 321                                             &pipe_config->dpll_hw_state);
 322
 323         ddi_dotclock_get(pipe_config);
 324 }
 325
 326 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 327                           const struct drm_connector_state *conn_state)
 328 {
 329         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 330         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 331         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 332         u32 temp;
 333
 334         if (!intel_crtc_has_dp_encoder(crtc_state))
 335                 return;
 336
 337         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 338
 339         temp = DP_MSA_MISC_SYNC_CLOCK;
 340
 341         switch (crtc_state->pipe_bpp) {
 342         case 18:
 343                 temp |= DP_MSA_MISC_6_BPC;
 344                 break;
 345         case 24:
 346                 temp |= DP_MSA_MISC_8_BPC;
 347                 break;
 348         case 30:
 349                 temp |= DP_MSA_MISC_10_BPC;
 350                 break;
 351         case 36:
 352                 temp |= DP_MSA_MISC_12_BPC;
 353                 break;
 354         default:
 355                 MISSING_CASE(crtc_state->pipe_bpp);
 356                 break;
 357         }
 358
 359         /* nonsense combination */
 360         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 361                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 362
 363         if (crtc_state->limited_color_range)
 364                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 365
 366         /*
 367          * As per DP 1.2 spec section 2.3.4.3 while sending
 368          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 369          * colorspace information.
 370          */
 371         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 372                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 373
 374         /*
 375          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 376          * of Color Encoding Format and Content Color Gamut] while sending
 377          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 378          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 379          */
 380         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 381                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 382
 383         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 384 }
 385
 386 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 387 {
 388         if (master_transcoder == TRANSCODER_EDP)
 389                 return 0;
 390         else
 391                 return master_transcoder + 1;
 392 }
 393
 394 /*
 395  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 396  *
 397  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 398  * intel_ddi_config_transcoder_func().
 399  */
 400 static u32
 401 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 402                                       const struct intel_crtc_state *crtc_state)
 403 {
 404         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 405         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 406         enum pipe pipe = crtc->pipe;
 407         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 408         enum port port = encoder->port;
 409         u32 temp;
 410
 411         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 412         temp = TRANS_DDI_FUNC_ENABLE;
 413         if (INTEL_GEN(dev_priv) >= 12)
 414                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 415         else
 416                 temp |= TRANS_DDI_SELECT_PORT(port);
 417
 418         switch (crtc_state->pipe_bpp) {
 419         case 18:
 420                 temp |= TRANS_DDI_BPC_6;
 421                 break;
 422         case 24:
 423                 temp |= TRANS_DDI_BPC_8;
 424                 break;
 425         case 30:
 426                 temp |= TRANS_DDI_BPC_10;
 427                 break;
 428         case 36:
 429                 temp |= TRANS_DDI_BPC_12;
 430                 break;
 431         default:
 432                 BUG();
 433         }
 434
 435         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 436                 temp |= TRANS_DDI_PVSYNC;
 437         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 438                 temp |= TRANS_DDI_PHSYNC;
 439
 440         if (cpu_transcoder == TRANSCODER_EDP) {
 441                 switch (pipe) {
 442                 case PIPE_A:
 443                         /* On Haswell, can only use the always-on power well for
 444                          * eDP when not using the panel fitter, and when not
 445                          * using motion blur mitigation (which we don't
 446                          * support). */
 447                         if (crtc_state->pch_pfit.force_thru)
 448                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 449                         else
 450                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 451                         break;
 452                 case PIPE_B:
 453                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 454                         break;
 455                 case PIPE_C:
 456                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 457                         break;
 458                 default:
 459                         BUG();
 460                         break;
 461                 }
 462         }
 463
 464         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 465                 if (crtc_state->has_hdmi_sink)
 466                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 467                 else
 468                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 469
 470                 if (crtc_state->hdmi_scrambling)
 471                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 472                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 473                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 474         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 475                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 476                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 477         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 478                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 479                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 480
 481                 if (INTEL_GEN(dev_priv) >= 12) {
 482                         enum transcoder master;
 483
 484                         master = crtc_state->mst_master_transcoder;
 485                         drm_WARN_ON(&dev_priv->drm,
 486                                     master == INVALID_TRANSCODER);
 487                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 488                 }
 489         } else {
 490                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 491                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 492         }
 493
 494         if (IS_GEN_RANGE(dev_priv, 8, 10) &&
 495             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 496                 u8 master_select =
 497                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 498
 499                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 500                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 501         }
 502
 503         return temp;
 504 }
 505
 506 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 507                                       const struct intel_crtc_state *crtc_state)
 508 {
 509         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 510         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 511         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 512
 513         if (INTEL_GEN(dev_priv) >= 11) {
 514                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 515                 u32 ctl2 = 0;
 516
 517                 if (master_transcoder != INVALID_TRANSCODER) {
 518                         u8 master_select =
 519                                 bdw_trans_port_sync_master_select(master_transcoder);
 520
 521                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 522                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 523                 }
 524
 525                 intel_de_write(dev_priv,
 526                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 527         }
 528
 529         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 530                        intel_ddi_transcoder_func_reg_val_get(encoder,
 531                                                              crtc_state));
 532 }
 533
 534 /*
 535  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 536  * bit.
 537  */
 538 static void
 539 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 540                                  const struct intel_crtc_state *crtc_state)
 541 {
 542         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 543         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 544         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 545         u32 ctl;
 546
 547         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 548         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 549         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 550 }
 551
 552 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 553 {
 554         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 555         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 556         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 557         u32 ctl;
 558
 559         if (INTEL_GEN(dev_priv) >= 11)
 560                 intel_de_write(dev_priv,
 561                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 562
 563         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 564
 565         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 566
 567         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 568
 569         if (IS_GEN_RANGE(dev_priv, 8, 10))
 570                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 571                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 572
 573         if (INTEL_GEN(dev_priv) >= 12) {
 574                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 575                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 576                                  TRANS_DDI_MODE_SELECT_MASK);
 577                 }
 578         } else {
 579                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 580         }
 581
 582         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 583
 584         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
 585             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 586                 drm_dbg_kms(&dev_priv->drm,
 587                             "Quirk Increase DDI disabled time\n");
 588                 /* Quirk time at 100ms for reliable operation */
 589                 msleep(100);
 590         }
 591 }
 592
 593 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 594                                enum transcoder cpu_transcoder,
 595                                bool enable, u32 hdcp_mask)
 596 {
 597         struct drm_device *dev = intel_encoder->base.dev;
 598         struct drm_i915_private *dev_priv = to_i915(dev);
 599         intel_wakeref_t wakeref;
 600         int ret = 0;
 601         u32 tmp;
 602
 603         wakeref = intel_display_power_get_if_enabled(dev_priv,
 604                                                      intel_encoder->power_domain);
 605         if (drm_WARN_ON(dev, !wakeref))
 606                 return -ENXIO;
 607
 608         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 609         if (enable)
 610                 tmp |= hdcp_mask;
 611         else
 612                 tmp &= ~hdcp_mask;
 613         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
 614         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 615         return ret;
 616 }
 617
 618 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 619 {
 620         struct drm_device *dev = intel_connector->base.dev;
 621         struct drm_i915_private *dev_priv = to_i915(dev);
 622         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 623         int type = intel_connector->base.connector_type;
 624         enum port port = encoder->port;
 625         enum transcoder cpu_transcoder;
 626         intel_wakeref_t wakeref;
 627         enum pipe pipe = 0;
 628         u32 tmp;
 629         bool ret;
 630
 631         wakeref = intel_display_power_get_if_enabled(dev_priv,
 632                                                      encoder->power_domain);
 633         if (!wakeref)
 634                 return false;
 635
 636         if (!encoder->get_hw_state(encoder, &pipe)) {
 637                 ret = false;
 638                 goto out;
 639         }
 640
 641         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 642                 cpu_transcoder = TRANSCODER_EDP;
 643         else
 644                 cpu_transcoder = (enum transcoder) pipe;
 645
 646         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 647
 648         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 649         case TRANS_DDI_MODE_SELECT_HDMI:
 650         case TRANS_DDI_MODE_SELECT_DVI:
 651                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 652                 break;
 653
 654         case TRANS_DDI_MODE_SELECT_DP_SST:
 655                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 656                       type == DRM_MODE_CONNECTOR_DisplayPort;
 657                 break;
 658
 659         case TRANS_DDI_MODE_SELECT_DP_MST:
 660                 /* if the transcoder is in MST state then
 661                  * connector isn't connected */
 662                 ret = false;
 663                 break;
 664
 665         case TRANS_DDI_MODE_SELECT_FDI:
 666                 ret = type == DRM_MODE_CONNECTOR_VGA;
 667                 break;
 668
 669         default:
 670                 ret = false;
 671                 break;
 672         }
 673
 674 out:
 675         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 676
 677         return ret;
 678 }
 679
 680 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 681                                         u8 *pipe_mask, bool *is_dp_mst)
 682 {
 683         struct drm_device *dev = encoder->base.dev;
 684         struct drm_i915_private *dev_priv = to_i915(dev);
 685         enum port port = encoder->port;
 686         intel_wakeref_t wakeref;
 687         enum pipe p;
 688         u32 tmp;
 689         u8 mst_pipe_mask;
 690
 691         *pipe_mask = 0;
 692         *is_dp_mst = false;
 693
 694         wakeref = intel_display_power_get_if_enabled(dev_priv,
 695                                                      encoder->power_domain);
 696         if (!wakeref)
 697                 return;
 698
 699         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 700         if (!(tmp & DDI_BUF_CTL_ENABLE))
 701                 goto out;
 702
 703         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 704                 tmp = intel_de_read(dev_priv,
 705                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 706
 707                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 708                 default:
 709                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 710                         fallthrough;
 711                 case TRANS_DDI_EDP_INPUT_A_ON:
 712                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 713                         *pipe_mask = BIT(PIPE_A);
 714                         break;
 715                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 716                         *pipe_mask = BIT(PIPE_B);
 717                         break;
 718                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 719                         *pipe_mask = BIT(PIPE_C);
 720                         break;
 721                 }
 722
 723                 goto out;
 724         }
 725
 726         mst_pipe_mask = 0;
 727         for_each_pipe(dev_priv, p) {
 728                 enum transcoder cpu_transcoder = (enum transcoder)p;
 729                 unsigned int port_mask, ddi_select;
 730                 intel_wakeref_t trans_wakeref;
 731
 732                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 733                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 734                 if (!trans_wakeref)
 735                         continue;
 736
 737                 if (INTEL_GEN(dev_priv) >= 12) {
 738                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 739                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 740                 } else {
 741                         port_mask = TRANS_DDI_PORT_MASK;
 742                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 743                 }
 744
 745                 tmp = intel_de_read(dev_priv,
 746                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 747                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 748                                         trans_wakeref);
 749
 750                 if ((tmp & port_mask) != ddi_select)
 751                         continue;
 752
 753                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
 754                     TRANS_DDI_MODE_SELECT_DP_MST)
 755                         mst_pipe_mask |= BIT(p);
 756
 757                 *pipe_mask |= BIT(p);
 758         }
 759
 760         if (!*pipe_mask)
 761                 drm_dbg_kms(&dev_priv->drm,
 762                             "No pipe for [ENCODER:%d:%s] found\n",
 763                             encoder->base.base.id, encoder->base.name);
 764
 765         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 766                 drm_dbg_kms(&dev_priv->drm,
 767                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 768                             encoder->base.base.id, encoder->base.name,
 769                             *pipe_mask);
 770                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 771         }
 772
 773         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 774                 drm_dbg_kms(&dev_priv->drm,
 775                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 776                             encoder->base.base.id, encoder->base.name,
 777                             *pipe_mask, mst_pipe_mask);
 778         else
 779                 *is_dp_mst = mst_pipe_mask;
 780
 781 out:
 782         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
 783                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 784                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 785                             BXT_PHY_LANE_POWERDOWN_ACK |
 786                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 787                         drm_err(&dev_priv->drm,
 788                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 789                                 encoder->base.base.id, encoder->base.name, tmp);
 790         }
 791
 792         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 793 }
 794
 795 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 796                             enum pipe *pipe)
 797 {
 798         u8 pipe_mask;
 799         bool is_mst;
 800
 801         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 802
 803         if (is_mst || !pipe_mask)
 804                 return false;
 805
 806         *pipe = ffs(pipe_mask) - 1;
 807
 808         return true;
 809 }
 810
 811 static enum intel_display_power_domain
 812 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 813 {
 814         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
 815          * DC states enabled at the same time, while for driver initiated AUX
 816          * transfers we need the same AUX IOs to be powered but with DC states
 817          * disabled. Accordingly use the AUX power domain here which leaves DC
 818          * states enabled.
 819          * However, for non-A AUX ports the corresponding non-EDP transcoders
 820          * would have already enabled power well 2 and DC_OFF. This means we can
 821          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
 822          * specific AUX_IO reference without powering up any extra wells.
 823          * Note that PSR is enabled only on Port A even though this function
 824          * returns the correct domain for other ports too.
 825          */
 826         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
 827                                               intel_aux_power_domain(dig_port);
 828 }
 829
 830 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 831                                         struct intel_crtc_state *crtc_state)
 832 {
 833         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 834         struct intel_digital_port *dig_port;
 835         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 836
 837         /*
 838          * TODO: Add support for MST encoders. Atm, the following should never
 839          * happen since fake-MST encoders don't set their get_power_domains()
 840          * hook.
 841          */
 842         if (drm_WARN_ON(&dev_priv->drm,
 843                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 844                 return;
 845
 846         dig_port = enc_to_dig_port(encoder);
 847
 848         if (!intel_phy_is_tc(dev_priv, phy) ||
 849             dig_port->tc_mode != TC_PORT_TBT_ALT) {
 850                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 851                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 852                                                                    dig_port->ddi_io_power_domain);
 853         }
 854
 855         /*
 856          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
 857          * ports.
 858          */
 859         if (intel_crtc_has_dp_encoder(crtc_state) ||
 860             intel_phy_is_tc(dev_priv, phy)) {
 861                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 862                 dig_port->aux_wakeref =
 863                         intel_display_power_get(dev_priv,
 864                                                 intel_ddi_main_link_aux_domain(dig_port));
 865         }
 866 }
 867
 868 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
 869                                  const struct intel_crtc_state *crtc_state)
 870 {
 871         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 872         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 873         enum port port = encoder->port;
 874         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 875
 876         if (cpu_transcoder != TRANSCODER_EDP) {
 877                 if (INTEL_GEN(dev_priv) >= 12)
 878                         intel_de_write(dev_priv,
 879                                        TRANS_CLK_SEL(cpu_transcoder),
 880                                        TGL_TRANS_CLK_SEL_PORT(port));
 881                 else
 882                         intel_de_write(dev_priv,
 883                                        TRANS_CLK_SEL(cpu_transcoder),
 884                                        TRANS_CLK_SEL_PORT(port));
 885         }
 886 }
 887
 888 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 889 {
 890         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 891         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 892
 893         if (cpu_transcoder != TRANSCODER_EDP) {
 894                 if (INTEL_GEN(dev_priv) >= 12)
 895                         intel_de_write(dev_priv,
 896                                        TRANS_CLK_SEL(cpu_transcoder),
 897                                        TGL_TRANS_CLK_SEL_DISABLED);
 898                 else
 899                         intel_de_write(dev_priv,
 900                                        TRANS_CLK_SEL(cpu_transcoder),
 901                                        TRANS_CLK_SEL_DISABLED);
 902         }
 903 }
 904
 905 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 906                                 enum port port, u8 iboost)
 907 {
 908         u32 tmp;
 909
 910         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 911         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 912         if (iboost)
 913                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
 914         else
 915                 tmp |= BALANCE_LEG_DISABLE(port);
 916         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 917 }
 918
 919 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 920                                const struct intel_crtc_state *crtc_state,
 921                                int level)
 922 {
 923         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 924         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 925         u8 iboost;
 926
 927         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 928                 iboost = intel_bios_hdmi_boost_level(encoder);
 929         else
 930                 iboost = intel_bios_dp_boost_level(encoder);
 931
 932         if (iboost == 0) {
 933                 const struct ddi_buf_trans *ddi_translations;
 934                 int n_entries;
 935
 936                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 937                         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
 938                 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 939                         ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 940                 else
 941                         ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
 942
 943                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 944                         return;
 945                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 946                         level = n_entries - 1;
 947
 948                 iboost = ddi_translations[level].i_boost;
 949         }
 950
 951         /* Make sure that the requested I_boost is valid */
 952         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
 953                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
 954                 return;
 955         }
 956
 957         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
 958
 959         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
 960                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
 961 }
 962
 963 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 964                                     const struct intel_crtc_state *crtc_state,
 965                                     int level)
 966 {
 967         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 968         const struct bxt_ddi_buf_trans *ddi_translations;
 969         enum port port = encoder->port;
 970         int n_entries;
 971
 972         ddi_translations = bxt_get_buf_trans(encoder, crtc_state, &n_entries);
 973         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 974                 return;
 975         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 976                 level = n_entries - 1;
 977
 978         bxt_ddi_phy_set_signal_level(dev_priv, port,
 979                                      ddi_translations[level].margin,
 980                                      ddi_translations[level].scale,
 981                                      ddi_translations[level].enable,
 982                                      ddi_translations[level].deemphasis);
 983 }
 984
 985 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
 986                                    const struct intel_crtc_state *crtc_state)
 987 {
 988         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 989         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 990         enum port port = encoder->port;
 991         enum phy phy = intel_port_to_phy(dev_priv, port);
 992         int n_entries;
 993
 994         if (INTEL_GEN(dev_priv) >= 12) {
 995                 if (intel_phy_is_combo(dev_priv, phy))
 996                         tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 997                 else
 998                         tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 999         } else if (INTEL_GEN(dev_priv) == 11) {
1000                 if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
1001                         jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1002                 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1003                         ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1004                 else if (intel_phy_is_combo(dev_priv, phy))
1005                         icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1006                 else
1007                         icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
1008         } else if (IS_CANNONLAKE(dev_priv)) {
1009                 cnl_get_buf_trans(encoder, crtc_state, &n_entries);
1010         } else if (IS_GEN9_LP(dev_priv)) {
1011                 bxt_get_buf_trans(encoder, crtc_state, &n_entries);
1012         } else {
1013                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1014                         intel_ddi_get_buf_trans_edp(encoder, &n_entries);
1015                 else
1016                         intel_ddi_get_buf_trans_dp(encoder, &n_entries);
1017         }
1018
1019         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1020                 n_entries = 1;
1021         if (drm_WARN_ON(&dev_priv->drm,
1022                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1023                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1024
1025         return index_to_dp_signal_levels[n_entries - 1] &
1026                 DP_TRAIN_VOLTAGE_SWING_MASK;
1027 }
1028
1029 /*
1030  * We assume that the full set of pre-emphasis values can be
1031  * used on all DDI platforms. Should that change we need to
1032  * rethink this code.
1033  */
1034 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1035 {
1036         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1037 }
1038
1039 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1040                                    const struct intel_crtc_state *crtc_state,
1041                                    int level)
1042 {
1043         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1044         const struct cnl_ddi_buf_trans *ddi_translations;
1045         enum port port = encoder->port;
1046         int n_entries, ln;
1047         u32 val;
1048
1049         ddi_translations = cnl_get_buf_trans(encoder, crtc_state, &n_entries);
1050
1051         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1052                 return;
1053         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1054                 level = n_entries - 1;
1055
1056         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1057         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1058         val &= ~SCALING_MODE_SEL_MASK;
1059         val |= SCALING_MODE_SEL(2);
1060         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1061
1062         /* Program PORT_TX_DW2 */
1063         val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
1064         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1065                  RCOMP_SCALAR_MASK);
1066         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1067         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1068         /* Rcomp scalar is fixed as 0x98 for every table entry */
1069         val |= RCOMP_SCALAR(0x98);
1070         intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
1071
1072         /* Program PORT_TX_DW4 */
1073         /* We cannot write to GRP. It would overrite individual loadgen */
1074         for (ln = 0; ln < 4; ln++) {
1075                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
1076                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1077                          CURSOR_COEFF_MASK);
1078                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1079                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1080                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1081                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
1082         }
1083
1084         /* Program PORT_TX_DW5 */
1085         /* All DW5 values are fixed for every table entry */
1086         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1087         val &= ~RTERM_SELECT_MASK;
1088         val |= RTERM_SELECT(6);
1089         val |= TAP3_DISABLE;
1090         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1091
1092         /* Program PORT_TX_DW7 */
1093         val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
1094         val &= ~N_SCALAR_MASK;
1095         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1096         intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
1097 }
1098
1099 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
1100                                     const struct intel_crtc_state *crtc_state,
1101                                     int level)
1102 {
1103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1104         enum port port = encoder->port;
1105         int width, rate, ln;
1106         u32 val;
1107
1108         width = crtc_state->lane_count;
1109         rate = crtc_state->port_clock;
1110
1111         /*
1112          * 1. If port type is eDP or DP,
1113          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1114          * else clear to 0b.
1115          */
1116         val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
1117         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1118                 val &= ~COMMON_KEEPER_EN;
1119         else
1120                 val |= COMMON_KEEPER_EN;
1121         intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
1122
1123         /* 2. Program loadgen select */
1124         /*
1125          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1126          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1127          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1128          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1129          */
1130         for (ln = 0; ln <= 3; ln++) {
1131                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
1132                 val &= ~LOADGEN_SELECT;
1133
1134                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
1135                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1136                         val |= LOADGEN_SELECT;
1137                 }
1138                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
1139         }
1140
1141         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1142         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
1143         val |= SUS_CLOCK_CONFIG;
1144         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
1145
1146         /* 4. Clear training enable to change swing values */
1147         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1148         val &= ~TX_TRAINING_EN;
1149         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1150
1151         /* 5. Program swing and de-emphasis */
1152         cnl_ddi_vswing_program(encoder, crtc_state, level);
1153
1154         /* 6. Set training enable to trigger update */
1155         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1156         val |= TX_TRAINING_EN;
1157         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1158 }
1159
1160 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1161                                          const struct intel_crtc_state *crtc_state,
1162                                          int level)
1163 {
1164         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1165         const struct cnl_ddi_buf_trans *ddi_translations;
1166         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1167         int n_entries, ln;
1168         u32 val;
1169
1170         if (INTEL_GEN(dev_priv) >= 12)
1171                 ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1172         else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
1173                 ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1174         else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1175                 ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1176         else
1177                 ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1178
1179         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1180                 return;
1181         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1182                 level = n_entries - 1;
1183
1184         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1185                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1186
1187                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1188                 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
1189                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1190                              intel_dp->hobl_active ? val : 0);
1191         }
1192
1193         /* Set PORT_TX_DW5 */
1194         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1195         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1196                   TAP2_DISABLE | TAP3_DISABLE);
1197         val |= SCALING_MODE_SEL(0x2);
1198         val |= RTERM_SELECT(0x6);
1199         val |= TAP3_DISABLE;
1200         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1201
1202         /* Program PORT_TX_DW2 */
1203         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
1204         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1205                  RCOMP_SCALAR_MASK);
1206         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1207         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1208         /* Program Rcomp scalar for every table entry */
1209         val |= RCOMP_SCALAR(0x98);
1210         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
1211
1212         /* Program PORT_TX_DW4 */
1213         /* We cannot write to GRP. It would overwrite individual loadgen. */
1214         for (ln = 0; ln <= 3; ln++) {
1215                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1216                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1217                          CURSOR_COEFF_MASK);
1218                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1219                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1220                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1221                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1222         }
1223
1224         /* Program PORT_TX_DW7 */
1225         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
1226         val &= ~N_SCALAR_MASK;
1227         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1228         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
1229 }
1230
1231 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1232                                               const struct intel_crtc_state *crtc_state,
1233                                               int level)
1234 {
1235         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1236         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1237         int width, rate, ln;
1238         u32 val;
1239
1240         width = crtc_state->lane_count;
1241         rate = crtc_state->port_clock;
1242
1243         /*
1244          * 1. If port type is eDP or DP,
1245          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1246          * else clear to 0b.
1247          */
1248         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
1249         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1250                 val &= ~COMMON_KEEPER_EN;
1251         else
1252                 val |= COMMON_KEEPER_EN;
1253         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1254
1255         /* 2. Program loadgen select */
1256         /*
1257          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1258          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1259          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1260          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1261          */
1262         for (ln = 0; ln <= 3; ln++) {
1263                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1264                 val &= ~LOADGEN_SELECT;
1265
1266                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
1267                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1268                         val |= LOADGEN_SELECT;
1269                 }
1270                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1271         }
1272
1273         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1274         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
1275         val |= SUS_CLOCK_CONFIG;
1276         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
1277
1278         /* 4. Clear training enable to change swing values */
1279         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1280         val &= ~TX_TRAINING_EN;
1281         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1282
1283         /* 5. Program swing and de-emphasis */
1284         icl_ddi_combo_vswing_program(encoder, crtc_state, level);
1285
1286         /* 6. Set training enable to trigger update */
1287         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1288         val |= TX_TRAINING_EN;
1289         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1290 }
1291
1292 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1293                                            const struct intel_crtc_state *crtc_state,
1294                                            int level)
1295 {
1296         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1297         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1298         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
1299         int n_entries, ln;
1300         u32 val;
1301
1302         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1303                 return;
1304
1305         ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
1306
1307         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1308                 return;
1309         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1310                 level = n_entries - 1;
1311
1312         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
1313         for (ln = 0; ln < 2; ln++) {
1314                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
1315                 val &= ~CRI_USE_FS32;
1316                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
1317
1318                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
1319                 val &= ~CRI_USE_FS32;
1320                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
1321         }
1322
1323         /* Program MG_TX_SWINGCTRL with values from vswing table */
1324         for (ln = 0; ln < 2; ln++) {
1325                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
1326                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1327                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1328                         ddi_translations[level].cri_txdeemph_override_17_12);
1329                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
1330
1331                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
1332                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1333                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1334                         ddi_translations[level].cri_txdeemph_override_17_12);
1335                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
1336         }
1337
1338         /* Program MG_TX_DRVCTRL with values from vswing table */
1339         for (ln = 0; ln < 2; ln++) {
1340                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
1341                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1342                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1343                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1344                         ddi_translations[level].cri_txdeemph_override_5_0) |
1345                         CRI_TXDEEMPH_OVERRIDE_11_6(
1346                                 ddi_translations[level].cri_txdeemph_override_11_6) |
1347                         CRI_TXDEEMPH_OVERRIDE_EN;
1348                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
1349
1350                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
1351                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1352                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1353                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1354                         ddi_translations[level].cri_txdeemph_override_5_0) |
1355                         CRI_TXDEEMPH_OVERRIDE_11_6(
1356                                 ddi_translations[level].cri_txdeemph_override_11_6) |
1357                         CRI_TXDEEMPH_OVERRIDE_EN;
1358                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
1359
1360                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1361         }
1362
1363         /*
1364          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1365          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1366          * values from table for which TX1 and TX2 enabled.
1367          */
1368         for (ln = 0; ln < 2; ln++) {
1369                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
1370                 if (crtc_state->port_clock < 300000)
1371                         val |= CFG_LOW_RATE_LKREN_EN;
1372                 else
1373                         val &= ~CFG_LOW_RATE_LKREN_EN;
1374                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
1375         }
1376
1377         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1378         for (ln = 0; ln < 2; ln++) {
1379                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
1380                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1381                 if (crtc_state->port_clock <= 500000) {
1382                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1383                 } else {
1384                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1385                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1386                 }
1387                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
1388
1389                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
1390                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1391                 if (crtc_state->port_clock <= 500000) {
1392                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1393                 } else {
1394                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1395                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1396                 }
1397                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
1398         }
1399
1400         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1401         for (ln = 0; ln < 2; ln++) {
1402                 val = intel_de_read(dev_priv,
1403                                     MG_TX1_PISO_READLOAD(ln, tc_port));
1404                 val |= CRI_CALCINIT;
1405                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1406                                val);
1407
1408                 val = intel_de_read(dev_priv,
1409                                     MG_TX2_PISO_READLOAD(ln, tc_port));
1410                 val |= CRI_CALCINIT;
1411                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1412                                val);
1413         }
1414 }
1415
1416 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
1417                                     const struct intel_crtc_state *crtc_state,
1418                                     int level)
1419 {
1420         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1421         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1422
1423         if (intel_phy_is_combo(dev_priv, phy))
1424                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1425         else
1426                 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1427 }
1428
1429 static void
1430 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1431                                 const struct intel_crtc_state *crtc_state,
1432                                 int level)
1433 {
1434         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1435         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1436         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
1437         u32 val, dpcnt_mask, dpcnt_val;
1438         int n_entries, ln;
1439
1440         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1441                 return;
1442
1443         ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
1444
1445         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1446                 return;
1447         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1448                 level = n_entries - 1;
1449
1450         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
1451                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1452                       DKL_TX_VSWING_CONTROL_MASK);
1453         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
1454         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
1455         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
1456
1457         for (ln = 0; ln < 2; ln++) {
1458                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1459                                HIP_INDEX_VAL(tc_port, ln));
1460
1461                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
1462
1463                 /* All the registers are RMW */
1464                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
1465                 val &= ~dpcnt_mask;
1466                 val |= dpcnt_val;
1467                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
1468
1469                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
1470                 val &= ~dpcnt_mask;
1471                 val |= dpcnt_val;
1472                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
1473
1474                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
1475                 val &= ~DKL_TX_DP20BITMODE;
1476                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
1477         }
1478 }
1479
1480 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
1481                                     const struct intel_crtc_state *crtc_state,
1482                                     int level)
1483 {
1484         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1485         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1486
1487         if (intel_phy_is_combo(dev_priv, phy))
1488                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1489         else
1490                 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1491 }
1492
1493 static int translate_signal_level(struct intel_dp *intel_dp,
1494                                   u8 signal_levels)
1495 {
1496         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1497         int i;
1498
1499         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1500                 if (index_to_dp_signal_levels[i] == signal_levels)
1501                         return i;
1502         }
1503
1504         drm_WARN(&i915->drm, 1,
1505                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1506                  signal_levels);
1507
1508         return 0;
1509 }
1510
1511 static int intel_ddi_dp_level(struct intel_dp *intel_dp)
1512 {
1513         u8 train_set = intel_dp->train_set[0];
1514         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1515                                         DP_TRAIN_PRE_EMPHASIS_MASK);
1516
1517         return translate_signal_level(intel_dp, signal_levels);
1518 }
1519
1520 static void
1521 tgl_set_signal_levels(struct intel_dp *intel_dp,
1522                       const struct intel_crtc_state *crtc_state)
1523 {
1524         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1525         int level = intel_ddi_dp_level(intel_dp);
1526
1527         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
1528 }
1529
1530 static void
1531 icl_set_signal_levels(struct intel_dp *intel_dp,
1532                       const struct intel_crtc_state *crtc_state)
1533 {
1534         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1535         int level = intel_ddi_dp_level(intel_dp);
1536
1537         icl_ddi_vswing_sequence(encoder, crtc_state, level);
1538 }
1539
1540 static void
1541 cnl_set_signal_levels(struct intel_dp *intel_dp,
1542                       const struct intel_crtc_state *crtc_state)
1543 {
1544         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1545         int level = intel_ddi_dp_level(intel_dp);
1546
1547         cnl_ddi_vswing_sequence(encoder, crtc_state, level);
1548 }
1549
1550 static void
1551 bxt_set_signal_levels(struct intel_dp *intel_dp,
1552                       const struct intel_crtc_state *crtc_state)
1553 {
1554         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1555         int level = intel_ddi_dp_level(intel_dp);
1556
1557         bxt_ddi_vswing_sequence(encoder, crtc_state, level);
1558 }
1559
1560 static void
1561 hsw_set_signal_levels(struct intel_dp *intel_dp,
1562                       const struct intel_crtc_state *crtc_state)
1563 {
1564         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1566         int level = intel_ddi_dp_level(intel_dp);
1567         enum port port = encoder->port;
1568         u32 signal_levels;
1569
1570         signal_levels = DDI_BUF_TRANS_SELECT(level);
1571
1572         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1573                     signal_levels);
1574
1575         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1576         intel_dp->DP |= signal_levels;
1577
1578         if (IS_GEN9_BC(dev_priv))
1579                 skl_ddi_set_iboost(encoder, crtc_state, level);
1580
1581         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1582         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1583 }
1584
1585 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
1586                                      enum phy phy)
1587 {
1588         if (IS_ROCKETLAKE(dev_priv)) {
1589                 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
1590         } else if (intel_phy_is_combo(dev_priv, phy)) {
1591                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
1592         } else if (intel_phy_is_tc(dev_priv, phy)) {
1593                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
1594                                                         (enum port)phy);
1595
1596                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
1597         }
1598
1599         return 0;
1600 }
1601
1602 static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
1603                                   const struct intel_crtc_state *crtc_state)
1604 {
1605         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1606         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1607         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1608         u32 val;
1609
1610         /*
1611          * If we fail this, something went very wrong: first 2 PLLs should be
1612          * used by first 2 phys and last 2 PLLs by last phys
1613          */
1614         if (drm_WARN_ON(&dev_priv->drm,
1615                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1616                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1617                 return;
1618
1619         mutex_lock(&dev_priv->dpll.lock);
1620
1621         val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
1622         drm_WARN_ON(&dev_priv->drm,
1623                     (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
1624
1625         val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1626         val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
1627         intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
1628         intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
1629
1630         val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
1631         intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
1632
1633         mutex_unlock(&dev_priv->dpll.lock);
1634 }
1635
1636 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
1637                                   const struct intel_crtc_state *crtc_state)
1638 {
1639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1640         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1641         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1642         u32 val, mask, sel;
1643         i915_reg_t reg;
1644
1645         if (IS_ALDERLAKE_S(dev_priv)) {
1646                 reg = ADLS_DPCLKA_CFGCR(phy);
1647                 mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
1648                 sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1649         } else if (IS_ROCKETLAKE(dev_priv)) {
1650                 reg = ICL_DPCLKA_CFGCR0;
1651                 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1652                 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
1653         } else {
1654                 reg = ICL_DPCLKA_CFGCR0;
1655                 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1656                 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
1657         }
1658
1659         mutex_lock(&dev_priv->dpll.lock);
1660
1661         val = intel_de_read(dev_priv, reg);
1662         drm_WARN_ON(&dev_priv->drm,
1663                     (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
1664
1665         if (intel_phy_is_combo(dev_priv, phy)) {
1666                 /*
1667                  * Even though this register references DDIs, note that we
1668                  * want to pass the PHY rather than the port (DDI).  For
1669                  * ICL, port=phy in all cases so it doesn't matter, but for
1670                  * EHL the bspec notes the following:
1671                  *
1672                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
1673                  *   Clock Select chooses the PLL for both DDIA and DDID and
1674                  *   drives port A in all cases."
1675                  */
1676                 val &= ~mask;
1677                 val |= sel;
1678                 intel_de_write(dev_priv, reg, val);
1679                 intel_de_posting_read(dev_priv, reg);
1680         }
1681
1682         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
1683         intel_de_write(dev_priv, reg, val);
1684
1685         mutex_unlock(&dev_priv->dpll.lock);
1686 }
1687
1688 static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
1689 {
1690         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1691         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1692
1693         mutex_lock(&dev_priv->dpll.lock);
1694
1695         intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
1696                      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1697
1698         mutex_unlock(&dev_priv->dpll.lock);
1699 }
1700
1701 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
1702 {
1703         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1704         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1705         u32 val;
1706         i915_reg_t reg;
1707
1708         mutex_lock(&dev_priv->dpll.lock);
1709
1710         if (IS_ALDERLAKE_S(dev_priv))
1711                 reg = ADLS_DPCLKA_CFGCR(phy);
1712         else
1713                 reg = ICL_DPCLKA_CFGCR0;
1714
1715         val = intel_de_read(dev_priv, reg);
1716         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
1717
1718         intel_de_write(dev_priv, reg, val);
1719
1720         mutex_unlock(&dev_priv->dpll.lock);
1721 }
1722
1723 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
1724                                       u32 port_mask, bool ddi_clk_needed)
1725 {
1726         enum port port;
1727         u32 val;
1728
1729         for_each_port_masked(port, port_mask) {
1730                 enum phy phy = intel_port_to_phy(dev_priv, port);
1731                 bool ddi_clk_off;
1732
1733                 val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
1734                 ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
1735
1736                 if (ddi_clk_needed == !ddi_clk_off)
1737                         continue;
1738
1739                 /*
1740                  * Punt on the case now where clock is gated, but it would
1741                  * be needed by the port. Something else is really broken then.
1742                  */
1743                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
1744                         continue;
1745
1746                 drm_notice(&dev_priv->drm,
1747                            "PHY %c is disabled with an ungated DDI clock, gate it\n",
1748                            phy_name(phy));
1749                 val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
1750                 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
1751         }
1752 }
1753
1754 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
1755                                       u32 port_mask, bool ddi_clk_needed)
1756 {
1757         enum port port;
1758         bool ddi_clk_off;
1759         u32 val;
1760         i915_reg_t reg;
1761
1762         for_each_port_masked(port, port_mask) {
1763                 enum phy phy = intel_port_to_phy(dev_priv, port);
1764
1765                 if (IS_ALDERLAKE_S(dev_priv))
1766                         reg = ADLS_DPCLKA_CFGCR(phy);
1767                 else
1768                         reg = ICL_DPCLKA_CFGCR0;
1769
1770                 val = intel_de_read(dev_priv, reg);
1771                 ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
1772                                                               phy);
1773
1774                 if (ddi_clk_needed == !ddi_clk_off)
1775                         continue;
1776
1777                 /*
1778                  * Punt on the case now where clock is gated, but it would
1779                  * be needed by the port. Something else is really broken then.
1780                  */
1781                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
1782                         continue;
1783
1784                 drm_notice(&dev_priv->drm,
1785                            "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
1786                            phy_name(phy));
1787                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
1788                 intel_de_write(dev_priv, reg, val);
1789         }
1790 }
1791
1792 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
1793 {
1794         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1795         u32 port_mask;
1796         bool ddi_clk_needed;
1797
1798         /*
1799          * In case of DP MST, we sanitize the primary encoder only, not the
1800          * virtual ones.
1801          */
1802         if (encoder->type == INTEL_OUTPUT_DP_MST)
1803                 return;
1804
1805         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
1806                 u8 pipe_mask;
1807                 bool is_mst;
1808
1809                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
1810                 /*
1811                  * In the unlikely case that BIOS enables DP in MST mode, just
1812                  * warn since our MST HW readout is incomplete.
1813                  */
1814                 if (drm_WARN_ON(&dev_priv->drm, is_mst))
1815                         return;
1816         }
1817
1818         port_mask = BIT(encoder->port);
1819         ddi_clk_needed = encoder->base.crtc;
1820
1821         if (encoder->type == INTEL_OUTPUT_DSI) {
1822                 struct intel_encoder *other_encoder;
1823
1824                 port_mask = intel_dsi_encoder_ports(encoder);
1825                 /*
1826                  * Sanity check that we haven't incorrectly registered another
1827                  * encoder using any of the ports of this DSI encoder.
1828                  */
1829                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
1830                         if (other_encoder == encoder)
1831                                 continue;
1832
1833                         if (drm_WARN_ON(&dev_priv->drm,
1834                                         port_mask & BIT(other_encoder->port)))
1835                                 return;
1836                 }
1837                 /*
1838                  * For DSI we keep the ddi clocks gated
1839                  * except during enable/disable sequence.
1840                  */
1841                 ddi_clk_needed = false;
1842         }
1843
1844         if (IS_DG1(dev_priv))
1845                 dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
1846         else
1847                 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
1848 }
1849
1850 static void intel_ddi_clk_select(struct intel_encoder *encoder,
1851                                  const struct intel_crtc_state *crtc_state)
1852 {
1853         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1854         enum port port = encoder->port;
1855         enum phy phy = intel_port_to_phy(dev_priv, port);
1856         u32 val;
1857         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1858
1859         if (drm_WARN_ON(&dev_priv->drm, !pll))
1860                 return;
1861
1862         mutex_lock(&dev_priv->dpll.lock);
1863
1864         if (INTEL_GEN(dev_priv) >= 11) {
1865                 if (!intel_phy_is_combo(dev_priv, phy))
1866                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
1867                                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1868                 else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)
1869                         /*
1870                          * MG does not exist but the programming is required
1871                          * to ungate DDIC and DDID
1872                          */
1873                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
1874                                        DDI_CLK_SEL_MG);
1875         } else if (IS_CANNONLAKE(dev_priv)) {
1876                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
1877                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
1878                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
1879                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
1880                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
1881
1882                 /*
1883                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
1884                  * This step and the step before must be done with separate
1885                  * register writes.
1886                  */
1887                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
1888                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
1889                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
1890         } else if (IS_GEN9_BC(dev_priv)) {
1891                 /* DDI -> PLL mapping  */
1892                 val = intel_de_read(dev_priv, DPLL_CTRL2);
1893
1894                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1895                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1896                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1897                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1898
1899                 intel_de_write(dev_priv, DPLL_CTRL2, val);
1900
1901         } else if (INTEL_GEN(dev_priv) < 9) {
1902                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
1903                                hsw_pll_to_ddi_pll_sel(pll));
1904         }
1905
1906         mutex_unlock(&dev_priv->dpll.lock);
1907 }
1908
1909 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
1910 {
1911         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1912         enum port port = encoder->port;
1913         enum phy phy = intel_port_to_phy(dev_priv, port);
1914
1915         if (INTEL_GEN(dev_priv) >= 11) {
1916                 if (!intel_phy_is_combo(dev_priv, phy) ||
1917                     (IS_JSL_EHL(dev_priv) && port >= PORT_C))
1918                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
1919                                        DDI_CLK_SEL_NONE);
1920         } else if (IS_CANNONLAKE(dev_priv)) {
1921                 intel_de_write(dev_priv, DPCLKA_CFGCR0,
1922                                intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
1923         } else if (IS_GEN9_BC(dev_priv)) {
1924                 intel_de_write(dev_priv, DPLL_CTRL2,
1925                                intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
1926         } else if (INTEL_GEN(dev_priv) < 9) {
1927                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
1928                                PORT_CLK_SEL_NONE);
1929         }
1930 }
1931
1932 static void
1933 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
1934                        const struct intel_crtc_state *crtc_state)
1935 {
1936         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1937         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
1938         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
1939         u32 ln0, ln1, pin_assignment;
1940         u8 width;
1941
1942         if (!intel_phy_is_tc(dev_priv, phy) ||
1943             dig_port->tc_mode == TC_PORT_TBT_ALT)
1944                 return;
1945
1946         if (INTEL_GEN(dev_priv) >= 12) {
1947                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1948                                HIP_INDEX_VAL(tc_port, 0x0));
1949                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
1950                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1951                                HIP_INDEX_VAL(tc_port, 0x1));
1952                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
1953         } else {
1954                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
1955                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
1956         }
1957
1958         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
1959         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
1960
1961         /* DPPATC */
1962         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
1963         width = crtc_state->lane_count;
1964
1965         switch (pin_assignment) {
1966         case 0x0:
1967                 drm_WARN_ON(&dev_priv->drm,
1968                             dig_port->tc_mode != TC_PORT_LEGACY);
1969                 if (width == 1) {
1970                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
1971                 } else {
1972                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
1973                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
1974                 }
1975                 break;
1976         case 0x1:
1977                 if (width == 4) {
1978                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
1979                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
1980                 }
1981                 break;
1982         case 0x2:
1983                 if (width == 2) {
1984                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
1985                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
1986                 }
1987                 break;
1988         case 0x3:
1989         case 0x5:
1990                 if (width == 1) {
1991                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
1992                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
1993                 } else {
1994                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
1995                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
1996                 }
1997                 break;
1998         case 0x4:
1999         case 0x6:
2000                 if (width == 1) {
2001                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2002                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2003                 } else {
2004                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2005                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2006                 }
2007                 break;
2008         default:
2009                 MISSING_CASE(pin_assignment);
2010         }
2011
2012         if (INTEL_GEN(dev_priv) >= 12) {
2013                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2014                                HIP_INDEX_VAL(tc_port, 0x0));
2015                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2016                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2017                                HIP_INDEX_VAL(tc_port, 0x1));
2018                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2019         } else {
2020                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2021                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2022         }
2023 }
2024
2025 static enum transcoder
2026 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2027 {
2028         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2029                 return crtc_state->mst_master_transcoder;
2030         else
2031                 return crtc_state->cpu_transcoder;
2032 }
2033
2034 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2035                          const struct intel_crtc_state *crtc_state)
2036 {
2037         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2038
2039         if (INTEL_GEN(dev_priv) >= 12)
2040                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2041         else
2042                 return DP_TP_CTL(encoder->port);
2043 }
2044
2045 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2046                             const struct intel_crtc_state *crtc_state)
2047 {
2048         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2049
2050         if (INTEL_GEN(dev_priv) >= 12)
2051                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2052         else
2053                 return DP_TP_STATUS(encoder->port);
2054 }
2055
2056 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2057                                                           const struct intel_crtc_state *crtc_state,
2058                                                           bool enable)
2059 {
2060         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2061
2062         if (!crtc_state->vrr.enable)
2063                 return;
2064
2065         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2066                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2067                 drm_dbg_kms(&i915->drm,
2068                             "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
2069                             enable ? "enable" : "disable");
2070 }
2071
2072 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2073                                         const struct intel_crtc_state *crtc_state)
2074 {
2075         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2076
2077         if (!crtc_state->fec_enable)
2078                 return;
2079
2080         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2081                 drm_dbg_kms(&i915->drm,
2082                             "Failed to set FEC_READY in the sink\n");
2083 }
2084
2085 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2086                                  const struct intel_crtc_state *crtc_state)
2087 {
2088         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2089         struct intel_dp *intel_dp;
2090         u32 val;
2091
2092         if (!crtc_state->fec_enable)
2093                 return;
2094
2095         intel_dp = enc_to_intel_dp(encoder);
2096         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2097         val |= DP_TP_CTL_FEC_ENABLE;
2098         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2099 }
2100
2101 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2102                                         const struct intel_crtc_state *crtc_state)
2103 {
2104         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2105         struct intel_dp *intel_dp;
2106         u32 val;
2107
2108         if (!crtc_state->fec_enable)
2109                 return;
2110
2111         intel_dp = enc_to_intel_dp(encoder);
2112         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2113         val &= ~DP_TP_CTL_FEC_ENABLE;
2114         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2115         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2116 }
2117
2118 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2119                                      const struct intel_crtc_state *crtc_state)
2120 {
2121         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2122         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2123         enum phy phy = intel_port_to_phy(i915, encoder->port);
2124
2125         if (intel_phy_is_combo(i915, phy)) {
2126                 bool lane_reversal =
2127                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2128
2129                 intel_combo_phy_power_up_lanes(i915, phy, false,
2130                                                crtc_state->lane_count,
2131                                                lane_reversal);
2132         }
2133 }
2134
2135 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2136                                   struct intel_encoder *encoder,
2137                                   const struct intel_crtc_state *crtc_state,
2138                                   const struct drm_connector_state *conn_state)
2139 {
2140         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2141         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2142         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2143         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2144         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2145         int level = intel_ddi_dp_level(intel_dp);
2146
2147         intel_dp_set_link_params(intel_dp,
2148                                  crtc_state->port_clock,
2149                                  crtc_state->lane_count);
2150
2151         /*
2152          * 1. Enable Power Wells
2153          *
2154          * This was handled at the beginning of intel_atomic_commit_tail(),
2155          * before we called down into this function.
2156          */
2157
2158         /* 2. Enable Panel Power if PPS is required */
2159         intel_pps_on(intel_dp);
2160
2161         /*
2162          * 3. For non-TBT Type-C ports, set FIA lane count
2163          * (DFLEXDPSP.DPX4TXLATC)
2164          *
2165          * This was done before tgl_ddi_pre_enable_dp by
2166          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2167          */
2168
2169         /*
2170          * 4. Enable the port PLL.
2171          *
2172          * The PLL enabling itself was already done before this function by
2173          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2174          * configure the PLL to port mapping here.
2175          */
2176         intel_ddi_clk_select(encoder, crtc_state);
2177
2178         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2179         if (!intel_phy_is_tc(dev_priv, phy) ||
2180             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2181                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2182                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2183                                                                    dig_port->ddi_io_power_domain);
2184         }
2185
2186         /* 6. Program DP_MODE */
2187         icl_program_mg_dp_mode(dig_port, crtc_state);
2188
2189         /*
2190          * 7. The rest of the below are substeps under the bspec's "Enable and
2191          * Train Display Port" step.  Note that steps that are specific to
2192          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2193          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2194          * us when active_mst_links==0, so any steps designated for "single
2195          * stream or multi-stream master transcoder" can just be performed
2196          * unconditionally here.
2197          */
2198
2199         /*
2200          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2201          * Transcoder.
2202          */
2203         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2204
2205         /*
2206          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2207          * Transport Select
2208          */
2209         intel_ddi_config_transcoder_func(encoder, crtc_state);
2210
2211         /*
2212          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2213          * selected
2214          *
2215          * This will be handled by the intel_dp_start_link_train() farther
2216          * down this function.
2217          */
2218
2219         /* 7.e Configure voltage swing and related IO settings */
2220         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
2221
2222         /*
2223          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2224          * the used lanes of the DDI.
2225          */
2226         intel_ddi_power_up_lanes(encoder, crtc_state);
2227
2228         /*
2229          * 7.g Configure and enable DDI_BUF_CTL
2230          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2231          *     after 500 us.
2232          *
2233          * We only configure what the register value will be here.  Actual
2234          * enabling happens during link training farther down.
2235          */
2236         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2237
2238         if (!is_mst)
2239                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2240
2241         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2242         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2243         /*
2244          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2245          * in the FEC_CONFIGURATION register to 1 before initiating link
2246          * training
2247          */
2248         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2249
2250         intel_dp_check_frl_training(intel_dp);
2251         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2252
2253         /*
2254          * 7.i Follow DisplayPort specification training sequence (see notes for
2255          *     failure handling)
2256          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2257          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2258          *     (timeout after 800 us)
2259          */
2260         intel_dp_start_link_train(intel_dp, crtc_state);
2261
2262         /* 7.k Set DP_TP_CTL link training to Normal */
2263         if (!is_trans_port_sync_mode(crtc_state))
2264                 intel_dp_stop_link_train(intel_dp, crtc_state);
2265
2266         /* 7.l Configure and enable FEC if needed */
2267         intel_ddi_enable_fec(encoder, crtc_state);
2268         if (!crtc_state->bigjoiner)
2269                 intel_dsc_enable(encoder, crtc_state);
2270 }
2271
2272 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2273                                   struct intel_encoder *encoder,
2274                                   const struct intel_crtc_state *crtc_state,
2275                                   const struct drm_connector_state *conn_state)
2276 {
2277         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2278         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2279         enum port port = encoder->port;
2280         enum phy phy = intel_port_to_phy(dev_priv, port);
2281         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2282         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2283         int level = intel_ddi_dp_level(intel_dp);
2284
2285         if (INTEL_GEN(dev_priv) < 11)
2286                 drm_WARN_ON(&dev_priv->drm,
2287                             is_mst && (port == PORT_A || port == PORT_E));
2288         else
2289                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2290
2291         intel_dp_set_link_params(intel_dp,
2292                                  crtc_state->port_clock,
2293                                  crtc_state->lane_count);
2294
2295         intel_pps_on(intel_dp);
2296
2297         intel_ddi_clk_select(encoder, crtc_state);
2298
2299         if (!intel_phy_is_tc(dev_priv, phy) ||
2300             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2301                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2302                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2303                                                                    dig_port->ddi_io_power_domain);
2304         }
2305
2306         icl_program_mg_dp_mode(dig_port, crtc_state);
2307
2308         if (INTEL_GEN(dev_priv) >= 11)
2309                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
2310         else if (IS_CANNONLAKE(dev_priv))
2311                 cnl_ddi_vswing_sequence(encoder, crtc_state, level);
2312         else if (IS_GEN9_LP(dev_priv))
2313                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
2314         else
2315                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2316
2317         intel_ddi_power_up_lanes(encoder, crtc_state);
2318
2319         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2320         if (!is_mst)
2321                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2322         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2323         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2324                                               true);
2325         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2326         intel_dp_start_link_train(intel_dp, crtc_state);
2327         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
2328             !is_trans_port_sync_mode(crtc_state))
2329                 intel_dp_stop_link_train(intel_dp, crtc_state);
2330
2331         intel_ddi_enable_fec(encoder, crtc_state);
2332
2333         if (!is_mst)
2334                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2335
2336         if (!crtc_state->bigjoiner)
2337                 intel_dsc_enable(encoder, crtc_state);
2338 }
2339
2340 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2341                                     struct intel_encoder *encoder,
2342                                     const struct intel_crtc_state *crtc_state,
2343                                     const struct drm_connector_state *conn_state)
2344 {
2345         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2346
2347         if (INTEL_GEN(dev_priv) >= 12)
2348                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2349         else
2350                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2351
2352         /* MST will call a setting of MSA after an allocating of Virtual Channel
2353          * from MST encoder pre_enable callback.
2354          */
2355         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2356                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2357
2358                 intel_dp_set_m_n(crtc_state, M1_N1);
2359         }
2360 }
2361
2362 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2363                                       struct intel_encoder *encoder,
2364                                       const struct intel_crtc_state *crtc_state,
2365                                       const struct drm_connector_state *conn_state)
2366 {
2367         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2368         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2369         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2370
2371         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2372         intel_ddi_clk_select(encoder, crtc_state);
2373
2374         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2375         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2376                                                            dig_port->ddi_io_power_domain);
2377
2378         icl_program_mg_dp_mode(dig_port, crtc_state);
2379
2380         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2381
2382         dig_port->set_infoframes(encoder,
2383                                  crtc_state->has_infoframe,
2384                                  crtc_state, conn_state);
2385 }
2386
2387 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2388                                  struct intel_encoder *encoder,
2389                                  const struct intel_crtc_state *crtc_state,
2390                                  const struct drm_connector_state *conn_state)
2391 {
2392         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2393         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2394         enum pipe pipe = crtc->pipe;
2395
2396         /*
2397          * When called from DP MST code:
2398          * - conn_state will be NULL
2399          * - encoder will be the main encoder (ie. mst->primary)
2400          * - the main connector associated with this port
2401          *   won't be active or linked to a crtc
2402          * - crtc_state will be the state of the first stream to
2403          *   be activated on this port, and it may not be the same
2404          *   stream that will be deactivated last, but each stream
2405          *   should have a state that is identical when it comes to
2406          *   the DP link parameteres
2407          */
2408
2409         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2410
2411         if (IS_DG1(dev_priv))
2412                 dg1_map_plls_to_ports(encoder, crtc_state);
2413         else if (INTEL_GEN(dev_priv) >= 11)
2414                 icl_map_plls_to_ports(encoder, crtc_state);
2415
2416         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2417
2418         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2419                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2420                                           conn_state);
2421         } else {
2422                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2423
2424                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2425                                         conn_state);
2426
2427                 /* FIXME precompute everything properly */
2428                 /* FIXME how do we turn infoframes off again? */
2429                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2430                         dig_port->set_infoframes(encoder,
2431                                                  crtc_state->has_infoframe,
2432                                                  crtc_state, conn_state);
2433         }
2434 }
2435
2436 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2437                                   const struct intel_crtc_state *crtc_state)
2438 {
2439         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2440         enum port port = encoder->port;
2441         bool wait = false;
2442         u32 val;
2443
2444         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2445         if (val & DDI_BUF_CTL_ENABLE) {
2446                 val &= ~DDI_BUF_CTL_ENABLE;
2447                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2448                 wait = true;
2449         }
2450
2451         if (intel_crtc_has_dp_encoder(crtc_state)) {
2452                 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2453                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2454                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2455                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2456         }
2457
2458         /* Disable FEC in DP Sink */
2459         intel_ddi_disable_fec_state(encoder, crtc_state);
2460
2461         if (wait)
2462                 intel_wait_ddi_buf_idle(dev_priv, port);
2463 }
2464
2465 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2466                                       struct intel_encoder *encoder,
2467                                       const struct intel_crtc_state *old_crtc_state,
2468                                       const struct drm_connector_state *old_conn_state)
2469 {
2470         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2471         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2472         struct intel_dp *intel_dp = &dig_port->dp;
2473         bool is_mst = intel_crtc_has_type(old_crtc_state,
2474                                           INTEL_OUTPUT_DP_MST);
2475         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2476
2477         if (!is_mst)
2478                 intel_dp_set_infoframes(encoder, false,
2479                                         old_crtc_state, old_conn_state);
2480
2481         /*
2482          * Power down sink before disabling the port, otherwise we end
2483          * up getting interrupts from the sink on detecting link loss.
2484          */
2485         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2486
2487         if (INTEL_GEN(dev_priv) >= 12) {
2488                 if (is_mst) {
2489                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2490                         u32 val;
2491
2492                         val = intel_de_read(dev_priv,
2493                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
2494                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
2495                                  TRANS_DDI_MODE_SELECT_MASK);
2496                         intel_de_write(dev_priv,
2497                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
2498                                        val);
2499                 }
2500         } else {
2501                 if (!is_mst)
2502                         intel_ddi_disable_pipe_clock(old_crtc_state);
2503         }
2504
2505         intel_disable_ddi_buf(encoder, old_crtc_state);
2506
2507         /*
2508          * From TGL spec: "If single stream or multi-stream master transcoder:
2509          * Configure Transcoder Clock select to direct no clock to the
2510          * transcoder"
2511          */
2512         if (INTEL_GEN(dev_priv) >= 12)
2513                 intel_ddi_disable_pipe_clock(old_crtc_state);
2514
2515         intel_pps_vdd_on(intel_dp);
2516         intel_pps_off(intel_dp);
2517
2518         if (!intel_phy_is_tc(dev_priv, phy) ||
2519             dig_port->tc_mode != TC_PORT_TBT_ALT)
2520                 intel_display_power_put(dev_priv,
2521                                         dig_port->ddi_io_power_domain,
2522                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
2523
2524         intel_ddi_clk_disable(encoder);
2525 }
2526
2527 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2528                                         struct intel_encoder *encoder,
2529                                         const struct intel_crtc_state *old_crtc_state,
2530                                         const struct drm_connector_state *old_conn_state)
2531 {
2532         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2533         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2534         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2535
2536         dig_port->set_infoframes(encoder, false,
2537                                  old_crtc_state, old_conn_state);
2538
2539         intel_ddi_disable_pipe_clock(old_crtc_state);
2540
2541         intel_disable_ddi_buf(encoder, old_crtc_state);
2542
2543         intel_display_power_put(dev_priv,
2544                                 dig_port->ddi_io_power_domain,
2545                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
2546
2547         intel_ddi_clk_disable(encoder);
2548
2549         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2550 }
2551
2552 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2553                                    struct intel_encoder *encoder,
2554                                    const struct intel_crtc_state *old_crtc_state,
2555                                    const struct drm_connector_state *old_conn_state)
2556 {
2557         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2558         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2559         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2560         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2561
2562         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2563                 intel_crtc_vblank_off(old_crtc_state);
2564
2565                 intel_disable_pipe(old_crtc_state);
2566
2567                 intel_vrr_disable(old_crtc_state);
2568
2569                 intel_ddi_disable_transcoder_func(old_crtc_state);
2570
2571                 intel_dsc_disable(old_crtc_state);
2572
2573                 if (INTEL_GEN(dev_priv) >= 9)
2574                         skl_scaler_disable(old_crtc_state);
2575                 else
2576                         ilk_pfit_disable(old_crtc_state);
2577         }
2578
2579         if (old_crtc_state->bigjoiner_linked_crtc) {
2580                 struct intel_atomic_state *state =
2581                         to_intel_atomic_state(old_crtc_state->uapi.state);
2582                 struct intel_crtc *slave =
2583                         old_crtc_state->bigjoiner_linked_crtc;
2584                 const struct intel_crtc_state *old_slave_crtc_state =
2585                         intel_atomic_get_old_crtc_state(state, slave);
2586
2587                 intel_crtc_vblank_off(old_slave_crtc_state);
2588                 trace_intel_pipe_disable(slave);
2589
2590                 intel_dsc_disable(old_slave_crtc_state);
2591                 skl_scaler_disable(old_slave_crtc_state);
2592         }
2593
2594         /*
2595          * When called from DP MST code:
2596          * - old_conn_state will be NULL
2597          * - encoder will be the main encoder (ie. mst->primary)
2598          * - the main connector associated with this port
2599          *   won't be active or linked to a crtc
2600          * - old_crtc_state will be the state of the last stream to
2601          *   be deactivated on this port, and it may not be the same
2602          *   stream that was activated last, but each stream
2603          *   should have a state that is identical when it comes to
2604          *   the DP link parameteres
2605          */
2606
2607         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2608                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2609                                             old_conn_state);
2610         else
2611                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2612                                           old_conn_state);
2613
2614         if (IS_DG1(dev_priv))
2615                 dg1_unmap_plls_to_ports(encoder);
2616         else if (INTEL_GEN(dev_priv) >= 11)
2617                 icl_unmap_plls_to_ports(encoder);
2618
2619         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
2620                 intel_display_power_put(dev_priv,
2621                                         intel_ddi_main_link_aux_domain(dig_port),
2622                                         fetch_and_zero(&dig_port->aux_wakeref));
2623
2624         if (is_tc_port)
2625                 intel_tc_port_put_link(dig_port);
2626 }
2627
2628 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
2629                                 struct intel_encoder *encoder,
2630                                 const struct intel_crtc_state *old_crtc_state,
2631                                 const struct drm_connector_state *old_conn_state)
2632 {
2633         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2634         u32 val;
2635
2636         /*
2637          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2638          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2639          * step 13 is the correct place for it. Step 18 is where it was
2640          * originally before the BUN.
2641          */
2642         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2643         val &= ~FDI_RX_ENABLE;
2644         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2645
2646         intel_disable_ddi_buf(encoder, old_crtc_state);
2647         intel_ddi_clk_disable(encoder);
2648
2649         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
2650         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2651         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2652         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
2653
2654         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2655         val &= ~FDI_PCDCLK;
2656         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2657
2658         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2659         val &= ~FDI_RX_PLL_ENABLE;
2660         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2661 }
2662
2663 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2664                                             struct intel_encoder *encoder,
2665                                             const struct intel_crtc_state *crtc_state)
2666 {
2667         const struct drm_connector_state *conn_state;
2668         struct drm_connector *conn;
2669         int i;
2670
2671         if (!crtc_state->sync_mode_slaves_mask)
2672                 return;
2673
2674         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2675                 struct intel_encoder *slave_encoder =
2676                         to_intel_encoder(conn_state->best_encoder);
2677                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2678                 const struct intel_crtc_state *slave_crtc_state;
2679
2680                 if (!slave_crtc)
2681                         continue;
2682
2683                 slave_crtc_state =
2684                         intel_atomic_get_new_crtc_state(state, slave_crtc);
2685
2686                 if (slave_crtc_state->master_transcoder !=
2687                     crtc_state->cpu_transcoder)
2688                         continue;
2689
2690                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
2691                                          slave_crtc_state);
2692         }
2693
2694         usleep_range(200, 400);
2695
2696         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
2697                                  crtc_state);
2698 }
2699
2700 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
2701                                 struct intel_encoder *encoder,
2702                                 const struct intel_crtc_state *crtc_state,
2703                                 const struct drm_connector_state *conn_state)
2704 {
2705         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2706         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2707         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2708         enum port port = encoder->port;
2709
2710         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2711                 intel_dp_stop_link_train(intel_dp, crtc_state);
2712
2713         intel_edp_backlight_on(crtc_state, conn_state);
2714         intel_psr_enable(intel_dp, crtc_state, conn_state);
2715
2716         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
2717                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
2718
2719         intel_edp_drrs_enable(intel_dp, crtc_state);
2720
2721         if (crtc_state->has_audio)
2722                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2723
2724         trans_port_sync_stop_link_train(state, encoder, crtc_state);
2725 }
2726
2727 static i915_reg_t
2728 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
2729                                enum port port)
2730 {
2731         static const enum transcoder trans[] = {
2732                 [PORT_A] = TRANSCODER_EDP,
2733                 [PORT_B] = TRANSCODER_A,
2734                 [PORT_C] = TRANSCODER_B,
2735                 [PORT_D] = TRANSCODER_C,
2736                 [PORT_E] = TRANSCODER_A,
2737         };
2738
2739         drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
2740
2741         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
2742                 port = PORT_A;
2743
2744         return CHICKEN_TRANS(trans[port]);
2745 }
2746
2747 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
2748                                   struct intel_encoder *encoder,
2749                                   const struct intel_crtc_state *crtc_state,
2750                                   const struct drm_connector_state *conn_state)
2751 {
2752         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2753         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2754         struct drm_connector *connector = conn_state->connector;
2755         int level = intel_ddi_hdmi_level(encoder, crtc_state);
2756         enum port port = encoder->port;
2757
2758         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2759                                                crtc_state->hdmi_high_tmds_clock_ratio,
2760                                                crtc_state->hdmi_scrambling))
2761                 drm_dbg_kms(&dev_priv->drm,
2762                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2763                             connector->base.id, connector->name);
2764
2765         if (INTEL_GEN(dev_priv) >= 12)
2766                 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
2767         else if (INTEL_GEN(dev_priv) == 11)
2768                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
2769         else if (IS_CANNONLAKE(dev_priv))
2770                 cnl_ddi_vswing_sequence(encoder, crtc_state, level);
2771         else if (IS_GEN9_LP(dev_priv))
2772                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
2773         else
2774                 intel_prepare_hdmi_ddi_buffers(encoder, level);
2775
2776         if (IS_GEN9_BC(dev_priv))
2777                 skl_ddi_set_iboost(encoder, crtc_state, level);
2778
2779         /* Display WA #1143: skl,kbl,cfl */
2780         if (IS_GEN9_BC(dev_priv)) {
2781                 /*
2782                  * For some reason these chicken bits have been
2783                  * stuffed into a transcoder register, event though
2784                  * the bits affect a specific DDI port rather than
2785                  * a specific transcoder.
2786                  */
2787                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
2788                 u32 val;
2789
2790                 val = intel_de_read(dev_priv, reg);
2791
2792                 if (port == PORT_E)
2793                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2794                                 DDIE_TRAINING_OVERRIDE_VALUE;
2795                 else
2796                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
2797                                 DDI_TRAINING_OVERRIDE_VALUE;
2798
2799                 intel_de_write(dev_priv, reg, val);
2800                 intel_de_posting_read(dev_priv, reg);
2801
2802                 udelay(1);
2803
2804                 if (port == PORT_E)
2805                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2806                                  DDIE_TRAINING_OVERRIDE_VALUE);
2807                 else
2808                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2809                                  DDI_TRAINING_OVERRIDE_VALUE);
2810
2811                 intel_de_write(dev_priv, reg, val);
2812         }
2813
2814         intel_ddi_power_up_lanes(encoder, crtc_state);
2815
2816         /* In HDMI/DVI mode, the port width, and swing/emphasis values
2817          * are ignored so nothing special needs to be done besides
2818          * enabling the port.
2819          */
2820         intel_de_write(dev_priv, DDI_BUF_CTL(port),
2821                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2822
2823         if (crtc_state->has_audio)
2824                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2825 }
2826
2827 static void intel_enable_ddi(struct intel_atomic_state *state,
2828                              struct intel_encoder *encoder,
2829                              const struct intel_crtc_state *crtc_state,
2830                              const struct drm_connector_state *conn_state)
2831 {
2832         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
2833
2834         if (!crtc_state->bigjoiner_slave)
2835                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
2836
2837         intel_vrr_enable(encoder, crtc_state);
2838
2839         intel_enable_pipe(crtc_state);
2840
2841         intel_crtc_vblank_on(crtc_state);
2842
2843         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2844                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
2845         else
2846                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
2847
2848         /* Enable hdcp if it's desired */
2849         if (conn_state->content_protection ==
2850             DRM_MODE_CONTENT_PROTECTION_DESIRED)
2851                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
2852                                   crtc_state,
2853                                   (u8)conn_state->hdcp_content_type);
2854 }
2855
2856 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
2857                                  struct intel_encoder *encoder,
2858                                  const struct intel_crtc_state *old_crtc_state,
2859                                  const struct drm_connector_state *old_conn_state)
2860 {
2861         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2862
2863         intel_dp->link_trained = false;
2864
2865         if (old_crtc_state->has_audio)
2866                 intel_audio_codec_disable(encoder,
2867                                           old_crtc_state, old_conn_state);
2868
2869         intel_edp_drrs_disable(intel_dp, old_crtc_state);
2870         intel_psr_disable(intel_dp, old_crtc_state);
2871         intel_edp_backlight_off(old_conn_state);
2872         /* Disable the decompression in DP Sink */
2873         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
2874                                               false);
2875         /* Disable Ignore_MSA bit in DP Sink */
2876         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
2877                                                       false);
2878 }
2879
2880 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
2881                                    struct intel_encoder *encoder,
2882                                    const struct intel_crtc_state *old_crtc_state,
2883                                    const struct drm_connector_state *old_conn_state)
2884 {
2885         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2886         struct drm_connector *connector = old_conn_state->connector;
2887
2888         if (old_crtc_state->has_audio)
2889                 intel_audio_codec_disable(encoder,
2890                                           old_crtc_state, old_conn_state);
2891
2892         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2893                                                false, false))
2894                 drm_dbg_kms(&i915->drm,
2895                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
2896                             connector->base.id, connector->name);
2897 }
2898
2899 static void intel_disable_ddi(struct intel_atomic_state *state,
2900                               struct intel_encoder *encoder,
2901                               const struct intel_crtc_state *old_crtc_state,
2902                               const struct drm_connector_state *old_conn_state)
2903 {
2904         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
2905
2906         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2907                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
2908                                        old_conn_state);
2909         else
2910                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
2911                                      old_conn_state);
2912 }
2913
2914 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
2915                                      struct intel_encoder *encoder,
2916                                      const struct intel_crtc_state *crtc_state,
2917                                      const struct drm_connector_state *conn_state)
2918 {
2919         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2920
2921         intel_ddi_set_dp_msa(crtc_state, conn_state);
2922
2923         intel_psr_update(intel_dp, crtc_state, conn_state);
2924         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
2925         intel_edp_drrs_update(intel_dp, crtc_state);
2926
2927         intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
2928 }
2929
2930 void intel_ddi_update_pipe(struct intel_atomic_state *state,
2931                            struct intel_encoder *encoder,
2932                            const struct intel_crtc_state *crtc_state,
2933                            const struct drm_connector_state *conn_state)
2934 {
2935
2936         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
2937             !intel_encoder_is_mst(encoder))
2938                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
2939                                          conn_state);
2940
2941         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
2942 }
2943
2944 static void
2945 intel_ddi_update_prepare(struct intel_atomic_state *state,
2946                          struct intel_encoder *encoder,
2947                          struct intel_crtc *crtc)
2948 {
2949         struct intel_crtc_state *crtc_state =
2950                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
2951         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
2952
2953         drm_WARN_ON(state->base.dev, crtc && crtc->active);
2954
2955         intel_tc_port_get_link(enc_to_dig_port(encoder),
2956                                required_lanes);
2957         if (crtc_state && crtc_state->hw.active)
2958                 intel_update_active_dpll(state, crtc, encoder);
2959 }
2960
2961 static void
2962 intel_ddi_update_complete(struct intel_atomic_state *state,
2963                           struct intel_encoder *encoder,
2964                           struct intel_crtc *crtc)
2965 {
2966         intel_tc_port_put_link(enc_to_dig_port(encoder));
2967 }
2968
2969 static void
2970 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
2971                          struct intel_encoder *encoder,
2972                          const struct intel_crtc_state *crtc_state,
2973                          const struct drm_connector_state *conn_state)
2974 {
2975         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2976         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2977         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2978         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2979
2980         if (is_tc_port)
2981                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
2982
2983         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
2984                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
2985                 dig_port->aux_wakeref =
2986                         intel_display_power_get(dev_priv,
2987                                                 intel_ddi_main_link_aux_domain(dig_port));
2988         }
2989
2990         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
2991                 /*
2992                  * Program the lane count for static/dynamic connections on
2993                  * Type-C ports.  Skip this step for TBT.
2994                  */
2995                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
2996         else if (IS_GEN9_LP(dev_priv))
2997                 bxt_ddi_phy_set_lane_optim_mask(encoder,
2998                                                 crtc_state->lane_lat_optim_mask);
2999 }
3000
3001 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3002                                            const struct intel_crtc_state *crtc_state)
3003 {
3004         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3005         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3006         enum port port = encoder->port;
3007         u32 dp_tp_ctl, ddi_buf_ctl;
3008         bool wait = false;
3009
3010         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3011
3012         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3013                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3014                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3015                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3016                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3017                         wait = true;
3018                 }
3019
3020                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3021                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3022                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3023                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3024
3025                 if (wait)
3026                         intel_wait_ddi_buf_idle(dev_priv, port);
3027         }
3028
3029         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3030         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3031                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3032         } else {
3033                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3034                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3035                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3036         }
3037         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3038         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3039
3040         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3041         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3042         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3043
3044         intel_wait_ddi_buf_active(dev_priv, port);
3045 }
3046
3047 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3048                                      const struct intel_crtc_state *crtc_state,
3049                                      u8 dp_train_pat)
3050 {
3051         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3052         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3053         u32 temp;
3054
3055         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3056
3057         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3058         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3059         case DP_TRAINING_PATTERN_DISABLE:
3060                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3061                 break;
3062         case DP_TRAINING_PATTERN_1:
3063                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3064                 break;
3065         case DP_TRAINING_PATTERN_2:
3066                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3067                 break;
3068         case DP_TRAINING_PATTERN_3:
3069                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3070                 break;
3071         case DP_TRAINING_PATTERN_4:
3072                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3073                 break;
3074         }
3075
3076         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3077 }
3078
3079 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3080                                           const struct intel_crtc_state *crtc_state)
3081 {
3082         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3083         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3084         enum port port = encoder->port;
3085         u32 val;
3086
3087         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3088         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3089         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3090         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3091
3092         /*
3093          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3094          * reason we need to set idle transmission mode is to work around a HW
3095          * issue where we enable the pipe while not in idle link-training mode.
3096          * In this case there is requirement to wait for a minimum number of
3097          * idle patterns to be sent.
3098          */
3099         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
3100                 return;
3101
3102         if (intel_de_wait_for_set(dev_priv,
3103                                   dp_tp_status_reg(encoder, crtc_state),
3104                                   DP_TP_STATUS_IDLE_DONE, 1))
3105                 drm_err(&dev_priv->drm,
3106                         "Timed out waiting for DP idle patterns\n");
3107 }
3108
3109 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3110                                        enum transcoder cpu_transcoder)
3111 {
3112         if (cpu_transcoder == TRANSCODER_EDP)
3113                 return false;
3114
3115         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3116                 return false;
3117
3118         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3119                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3120 }
3121
3122 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3123                                          struct intel_crtc_state *crtc_state)
3124 {
3125         if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3126                 crtc_state->min_voltage_level = 2;
3127         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3128                 crtc_state->min_voltage_level = 3;
3129         else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3130                 crtc_state->min_voltage_level = 1;
3131         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3132                 crtc_state->min_voltage_level = 2;
3133 }
3134
3135 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3136                                                      enum transcoder cpu_transcoder)
3137 {
3138         u32 master_select;
3139
3140         if (INTEL_GEN(dev_priv) >= 11) {
3141                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3142
3143                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3144                         return INVALID_TRANSCODER;
3145
3146                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3147         } else {
3148                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3149
3150                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3151                         return INVALID_TRANSCODER;
3152
3153                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3154         }
3155
3156         if (master_select == 0)
3157                 return TRANSCODER_EDP;
3158         else
3159                 return master_select - 1;
3160 }
3161
3162 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3163 {
3164         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3165         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3166                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3167         enum transcoder cpu_transcoder;
3168
3169         crtc_state->master_transcoder =
3170                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3171
3172         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3173                 enum intel_display_power_domain power_domain;
3174                 intel_wakeref_t trans_wakeref;
3175
3176                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3177                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3178                                                                    power_domain);
3179
3180                 if (!trans_wakeref)
3181                         continue;
3182
3183                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3184                     crtc_state->cpu_transcoder)
3185                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3186
3187                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3188         }
3189
3190         drm_WARN_ON(&dev_priv->drm,
3191                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3192                     crtc_state->sync_mode_slaves_mask);
3193 }
3194
3195 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3196                                     struct intel_crtc_state *pipe_config)
3197 {
3198         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3199         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
3200         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3201         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3202         u32 temp, flags = 0;
3203
3204         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3205         if (temp & TRANS_DDI_PHSYNC)
3206                 flags |= DRM_MODE_FLAG_PHSYNC;
3207         else
3208                 flags |= DRM_MODE_FLAG_NHSYNC;
3209         if (temp & TRANS_DDI_PVSYNC)
3210                 flags |= DRM_MODE_FLAG_PVSYNC;
3211         else
3212                 flags |= DRM_MODE_FLAG_NVSYNC;
3213
3214         pipe_config->hw.adjusted_mode.flags |= flags;
3215
3216         switch (temp & TRANS_DDI_BPC_MASK) {
3217         case TRANS_DDI_BPC_6:
3218                 pipe_config->pipe_bpp = 18;
3219                 break;
3220         case TRANS_DDI_BPC_8:
3221                 pipe_config->pipe_bpp = 24;
3222                 break;
3223         case TRANS_DDI_BPC_10:
3224                 pipe_config->pipe_bpp = 30;
3225                 break;
3226         case TRANS_DDI_BPC_12:
3227                 pipe_config->pipe_bpp = 36;
3228                 break;
3229         default:
3230                 break;
3231         }
3232
3233         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3234         case TRANS_DDI_MODE_SELECT_HDMI:
3235                 pipe_config->has_hdmi_sink = true;
3236
3237                 pipe_config->infoframes.enable |=
3238                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3239
3240                 if (pipe_config->infoframes.enable)
3241                         pipe_config->has_infoframe = true;
3242
3243                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3244                         pipe_config->hdmi_scrambling = true;
3245                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3246                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3247                 fallthrough;
3248         case TRANS_DDI_MODE_SELECT_DVI:
3249                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3250                 pipe_config->lane_count = 4;
3251                 break;
3252         case TRANS_DDI_MODE_SELECT_FDI:
3253                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3254                 break;
3255         case TRANS_DDI_MODE_SELECT_DP_SST:
3256                 if (encoder->type == INTEL_OUTPUT_EDP)
3257                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3258                 else
3259                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3260                 pipe_config->lane_count =
3261                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3262                 intel_dp_get_m_n(intel_crtc, pipe_config);
3263
3264                 if (INTEL_GEN(dev_priv) >= 11) {
3265                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3266
3267                         pipe_config->fec_enable =
3268                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3269
3270                         drm_dbg_kms(&dev_priv->drm,
3271                                     "[ENCODER:%d:%s] Fec status: %u\n",
3272                                     encoder->base.base.id, encoder->base.name,
3273                                     pipe_config->fec_enable);
3274                 }
3275
3276                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3277                         pipe_config->infoframes.enable |=
3278                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3279                 else
3280                         pipe_config->infoframes.enable |=
3281                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3282                 break;
3283         case TRANS_DDI_MODE_SELECT_DP_MST:
3284                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3285                 pipe_config->lane_count =
3286                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3287
3288                 if (INTEL_GEN(dev_priv) >= 12)
3289                         pipe_config->mst_master_transcoder =
3290                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3291
3292                 intel_dp_get_m_n(intel_crtc, pipe_config);
3293
3294                 pipe_config->infoframes.enable |=
3295                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3296                 break;
3297         default:
3298                 break;
3299         }
3300 }
3301
3302 void intel_ddi_get_config(struct intel_encoder *encoder,
3303                           struct intel_crtc_state *pipe_config)
3304 {
3305         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3306         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3307
3308         /* XXX: DSI transcoder paranoia */
3309         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3310                 return;
3311
3312         if (pipe_config->bigjoiner_slave) {
3313                 /* read out pipe settings from master */
3314                 enum transcoder save = pipe_config->cpu_transcoder;
3315
3316                 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
3317                 WARN_ON(pipe_config->output_types);
3318                 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
3319                 intel_ddi_read_func_ctl(encoder, pipe_config);
3320                 pipe_config->cpu_transcoder = save;
3321         } else {
3322                 intel_ddi_read_func_ctl(encoder, pipe_config);
3323         }
3324
3325         pipe_config->has_audio =
3326                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3327
3328         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3329             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3330                 /*
3331                  * This is a big fat ugly hack.
3332                  *
3333                  * Some machines in UEFI boot mode provide us a VBT that has 18
3334                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3335                  * unknown we fail to light up. Yet the same BIOS boots up with
3336                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3337                  * max, not what it tells us to use.
3338                  *
3339                  * Note: This will still be broken if the eDP panel is not lit
3340                  * up by the BIOS, and thus we can't get the mode at module
3341                  * load.
3342                  */
3343                 drm_dbg_kms(&dev_priv->drm,
3344                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3345                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3346                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3347         }
3348
3349         if (!pipe_config->bigjoiner_slave)
3350                 intel_ddi_clock_get(encoder, pipe_config);
3351
3352         if (IS_GEN9_LP(dev_priv))
3353                 pipe_config->lane_lat_optim_mask =
3354                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3355
3356         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3357
3358         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3359
3360         intel_read_infoframe(encoder, pipe_config,
3361                              HDMI_INFOFRAME_TYPE_AVI,
3362                              &pipe_config->infoframes.avi);
3363         intel_read_infoframe(encoder, pipe_config,
3364                              HDMI_INFOFRAME_TYPE_SPD,
3365                              &pipe_config->infoframes.spd);
3366         intel_read_infoframe(encoder, pipe_config,
3367                              HDMI_INFOFRAME_TYPE_VENDOR,
3368                              &pipe_config->infoframes.hdmi);
3369         intel_read_infoframe(encoder, pipe_config,
3370                              HDMI_INFOFRAME_TYPE_DRM,
3371                              &pipe_config->infoframes.drm);
3372
3373         if (INTEL_GEN(dev_priv) >= 8)
3374                 bdw_get_trans_port_sync_config(pipe_config);
3375
3376         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3377         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3378 }
3379
3380 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3381                                  const struct intel_crtc_state *crtc_state)
3382 {
3383         if (intel_crtc_has_dp_encoder(crtc_state))
3384                 intel_dp_sync_state(encoder, crtc_state);
3385 }
3386
3387 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3388                                             struct intel_crtc_state *crtc_state)
3389 {
3390         if (intel_crtc_has_dp_encoder(crtc_state))
3391                 return intel_dp_initial_fastset_check(encoder, crtc_state);
3392
3393         return true;
3394 }
3395
3396 static enum intel_output_type
3397 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3398                               struct intel_crtc_state *crtc_state,
3399                               struct drm_connector_state *conn_state)
3400 {
3401         switch (conn_state->connector->connector_type) {
3402         case DRM_MODE_CONNECTOR_HDMIA:
3403                 return INTEL_OUTPUT_HDMI;
3404         case DRM_MODE_CONNECTOR_eDP:
3405                 return INTEL_OUTPUT_EDP;
3406         case DRM_MODE_CONNECTOR_DisplayPort:
3407                 return INTEL_OUTPUT_DP;
3408         default:
3409                 MISSING_CASE(conn_state->connector->connector_type);
3410                 return INTEL_OUTPUT_UNUSED;
3411         }
3412 }
3413
3414 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3415                                     struct intel_crtc_state *pipe_config,
3416                                     struct drm_connector_state *conn_state)
3417 {
3418         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3419         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3420         enum port port = encoder->port;
3421         int ret;
3422
3423         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3424                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3425
3426         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3427                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3428         } else {
3429                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3430         }
3431
3432         if (ret)
3433                 return ret;
3434
3435         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3436             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3437                 pipe_config->pch_pfit.force_thru =
3438                         pipe_config->pch_pfit.enabled ||
3439                         pipe_config->crc_enabled;
3440
3441         if (IS_GEN9_LP(dev_priv))
3442                 pipe_config->lane_lat_optim_mask =
3443                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3444
3445         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3446
3447         return 0;
3448 }
3449
3450 static bool mode_equal(const struct drm_display_mode *mode1,
3451                        const struct drm_display_mode *mode2)
3452 {
3453         return drm_mode_match(mode1, mode2,
3454                               DRM_MODE_MATCH_TIMINGS |
3455                               DRM_MODE_MATCH_FLAGS |
3456                               DRM_MODE_MATCH_3D_FLAGS) &&
3457                 mode1->clock == mode2->clock; /* we want an exact match */
3458 }
3459
3460 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3461                       const struct intel_link_m_n *m_n_2)
3462 {
3463         return m_n_1->tu == m_n_2->tu &&
3464                 m_n_1->gmch_m == m_n_2->gmch_m &&
3465                 m_n_1->gmch_n == m_n_2->gmch_n &&
3466                 m_n_1->link_m == m_n_2->link_m &&
3467                 m_n_1->link_n == m_n_2->link_n;
3468 }
3469
3470 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3471                                        const struct intel_crtc_state *crtc_state2)
3472 {
3473         return crtc_state1->hw.active && crtc_state2->hw.active &&
3474                 crtc_state1->output_types == crtc_state2->output_types &&
3475                 crtc_state1->output_format == crtc_state2->output_format &&
3476                 crtc_state1->lane_count == crtc_state2->lane_count &&
3477                 crtc_state1->port_clock == crtc_state2->port_clock &&
3478                 mode_equal(&crtc_state1->hw.adjusted_mode,
3479                            &crtc_state2->hw.adjusted_mode) &&
3480                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3481 }
3482
3483 static u8
3484 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3485                                 int tile_group_id)
3486 {
3487         struct drm_connector *connector;
3488         const struct drm_connector_state *conn_state;
3489         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3490         struct intel_atomic_state *state =
3491                 to_intel_atomic_state(ref_crtc_state->uapi.state);
3492         u8 transcoders = 0;
3493         int i;
3494
3495         /*
3496          * We don't enable port sync on BDW due to missing w/as and
3497          * due to not having adjusted the modeset sequence appropriately.
3498          */
3499         if (INTEL_GEN(dev_priv) < 9)
3500                 return 0;
3501
3502         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3503                 return 0;
3504
3505         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3506                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3507                 const struct intel_crtc_state *crtc_state;
3508
3509                 if (!crtc)
3510                         continue;
3511
3512                 if (!connector->has_tile ||
3513                     connector->tile_group->id !=
3514                     tile_group_id)
3515                         continue;
3516                 crtc_state = intel_atomic_get_new_crtc_state(state,
3517                                                              crtc);
3518                 if (!crtcs_port_sync_compatible(ref_crtc_state,
3519                                                 crtc_state))
3520                         continue;
3521                 transcoders |= BIT(crtc_state->cpu_transcoder);
3522         }
3523
3524         return transcoders;
3525 }
3526
3527 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3528                                          struct intel_crtc_state *crtc_state,
3529                                          struct drm_connector_state *conn_state)
3530 {
3531         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3532         struct drm_connector *connector = conn_state->connector;
3533         u8 port_sync_transcoders = 0;
3534
3535         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3536                     encoder->base.base.id, encoder->base.name,
3537                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3538
3539         if (connector->has_tile)
3540                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3541                                                                         connector->tile_group->id);
3542
3543         /*
3544          * EDP Transcoders cannot be ensalved
3545          * make them a master always when present
3546          */
3547         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3548                 crtc_state->master_transcoder = TRANSCODER_EDP;
3549         else
3550                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3551
3552         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
3553                 crtc_state->master_transcoder = INVALID_TRANSCODER;
3554                 crtc_state->sync_mode_slaves_mask =
3555                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
3556         }
3557
3558         return 0;
3559 }
3560
3561 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3562 {
3563         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3564
3565         intel_dp_encoder_flush_work(encoder);
3566
3567         drm_encoder_cleanup(encoder);
3568         if (dig_port)
3569                 kfree(dig_port->hdcp_port_data.streams);
3570         kfree(dig_port);
3571 }
3572
3573 static const struct drm_encoder_funcs intel_ddi_funcs = {
3574         .reset = intel_dp_encoder_reset,
3575         .destroy = intel_ddi_encoder_destroy,
3576 };
3577
3578 static struct intel_connector *
3579 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
3580 {
3581         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3582         struct intel_connector *connector;
3583         enum port port = dig_port->base.port;
3584
3585         connector = intel_connector_alloc();
3586         if (!connector)
3587                 return NULL;
3588
3589         dig_port->dp.output_reg = DDI_BUF_CTL(port);
3590         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
3591         dig_port->dp.set_link_train = intel_ddi_set_link_train;
3592         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
3593
3594         if (INTEL_GEN(dev_priv) >= 12)
3595                 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
3596         else if (INTEL_GEN(dev_priv) >= 11)
3597                 dig_port->dp.set_signal_levels = icl_set_signal_levels;
3598         else if (IS_CANNONLAKE(dev_priv))
3599                 dig_port->dp.set_signal_levels = cnl_set_signal_levels;
3600         else if (IS_GEN9_LP(dev_priv))
3601                 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
3602         else
3603                 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
3604
3605         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
3606         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
3607
3608         if (!intel_dp_init_connector(dig_port, connector)) {
3609                 kfree(connector);
3610                 return NULL;
3611         }
3612
3613         return connector;
3614 }
3615
3616 static int modeset_pipe(struct drm_crtc *crtc,
3617                         struct drm_modeset_acquire_ctx *ctx)
3618 {
3619         struct drm_atomic_state *state;
3620         struct drm_crtc_state *crtc_state;
3621         int ret;
3622
3623         state = drm_atomic_state_alloc(crtc->dev);
3624         if (!state)
3625                 return -ENOMEM;
3626
3627         state->acquire_ctx = ctx;
3628
3629         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3630         if (IS_ERR(crtc_state)) {
3631                 ret = PTR_ERR(crtc_state);
3632                 goto out;
3633         }
3634
3635         crtc_state->connectors_changed = true;
3636
3637         ret = drm_atomic_commit(state);
3638 out:
3639         drm_atomic_state_put(state);
3640
3641         return ret;
3642 }
3643
3644 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3645                                  struct drm_modeset_acquire_ctx *ctx)
3646 {
3647         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3648         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
3649         struct intel_connector *connector = hdmi->attached_connector;
3650         struct i2c_adapter *adapter =
3651                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3652         struct drm_connector_state *conn_state;
3653         struct intel_crtc_state *crtc_state;
3654         struct intel_crtc *crtc;
3655         u8 config;
3656         int ret;
3657
3658         if (!connector || connector->base.status != connector_status_connected)
3659                 return 0;
3660
3661         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3662                                ctx);
3663         if (ret)
3664                 return ret;
3665
3666         conn_state = connector->base.state;
3667
3668         crtc = to_intel_crtc(conn_state->crtc);
3669         if (!crtc)
3670                 return 0;
3671
3672         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3673         if (ret)
3674                 return ret;
3675
3676         crtc_state = to_intel_crtc_state(crtc->base.state);
3677
3678         drm_WARN_ON(&dev_priv->drm,
3679                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3680
3681         if (!crtc_state->hw.active)
3682                 return 0;
3683
3684         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3685             !crtc_state->hdmi_scrambling)
3686                 return 0;
3687
3688         if (conn_state->commit &&
3689             !try_wait_for_completion(&conn_state->commit->hw_done))
3690                 return 0;
3691
3692         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3693         if (ret < 0) {
3694                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
3695                         ret);
3696                 return 0;
3697         }
3698
3699         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3700             crtc_state->hdmi_high_tmds_clock_ratio &&
3701             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3702             crtc_state->hdmi_scrambling)
3703                 return 0;
3704
3705         /*
3706          * HDMI 2.0 says that one should not send scrambled data
3707          * prior to configuring the sink scrambling, and that
3708          * TMDS clock/data transmission should be suspended when
3709          * changing the TMDS clock rate in the sink. So let's
3710          * just do a full modeset here, even though some sinks
3711          * would be perfectly happy if were to just reconfigure
3712          * the SCDC settings on the fly.
3713          */
3714         return modeset_pipe(&crtc->base, ctx);
3715 }
3716
3717 static enum intel_hotplug_state
3718 intel_ddi_hotplug(struct intel_encoder *encoder,
3719                   struct intel_connector *connector)
3720 {
3721         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3722         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3723         struct intel_dp *intel_dp = &dig_port->dp;
3724         enum phy phy = intel_port_to_phy(i915, encoder->port);
3725         bool is_tc = intel_phy_is_tc(i915, phy);
3726         struct drm_modeset_acquire_ctx ctx;
3727         enum intel_hotplug_state state;
3728         int ret;
3729
3730         if (intel_dp->compliance.test_active &&
3731             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
3732                 intel_dp_phy_test(encoder);
3733                 /* just do the PHY test and nothing else */
3734                 return INTEL_HOTPLUG_UNCHANGED;
3735         }
3736
3737         state = intel_encoder_hotplug(encoder, connector);
3738
3739         drm_modeset_acquire_init(&ctx, 0);
3740
3741         for (;;) {
3742                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3743                         ret = intel_hdmi_reset_link(encoder, &ctx);
3744                 else
3745                         ret = intel_dp_retrain_link(encoder, &ctx);
3746
3747                 if (ret == -EDEADLK) {
3748                         drm_modeset_backoff(&ctx);
3749                         continue;
3750                 }
3751
3752                 break;
3753         }
3754
3755         drm_modeset_drop_locks(&ctx);
3756         drm_modeset_acquire_fini(&ctx);
3757         drm_WARN(encoder->base.dev, ret,
3758                  "Acquiring modeset locks failed with %i\n", ret);
3759
3760         /*
3761          * Unpowered type-c dongles can take some time to boot and be
3762          * responsible, so here giving some time to those dongles to power up
3763          * and then retrying the probe.
3764          *
3765          * On many platforms the HDMI live state signal is known to be
3766          * unreliable, so we can't use it to detect if a sink is connected or
3767          * not. Instead we detect if it's connected based on whether we can
3768          * read the EDID or not. That in turn has a problem during disconnect,
3769          * since the HPD interrupt may be raised before the DDC lines get
3770          * disconnected (due to how the required length of DDC vs. HPD
3771          * connector pins are specified) and so we'll still be able to get a
3772          * valid EDID. To solve this schedule another detection cycle if this
3773          * time around we didn't detect any change in the sink's connection
3774          * status.
3775          *
3776          * Type-c connectors which get their HPD signal deasserted then
3777          * reasserted, without unplugging/replugging the sink from the
3778          * connector, introduce a delay until the AUX channel communication
3779          * becomes functional. Retry the detection for 5 seconds on type-c
3780          * connectors to account for this delay.
3781          */
3782         if (state == INTEL_HOTPLUG_UNCHANGED &&
3783             connector->hotplug_retries < (is_tc ? 5 : 1) &&
3784             !dig_port->dp.is_mst)
3785                 state = INTEL_HOTPLUG_RETRY;
3786
3787         return state;
3788 }
3789
3790 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
3791 {
3792         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3793         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
3794
3795         return intel_de_read(dev_priv, SDEISR) & bit;
3796 }
3797
3798 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
3799 {
3800         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3801         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
3802
3803         return intel_de_read(dev_priv, DEISR) & bit;
3804 }
3805
3806 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
3807 {
3808         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3809         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
3810
3811         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
3812 }
3813
3814 static struct intel_connector *
3815 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
3816 {
3817         struct intel_connector *connector;
3818         enum port port = dig_port->base.port;
3819
3820         connector = intel_connector_alloc();
3821         if (!connector)
3822                 return NULL;
3823
3824         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3825         intel_hdmi_init_connector(dig_port, connector);
3826
3827         return connector;
3828 }
3829
3830 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
3831 {
3832         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3833
3834         if (dig_port->base.port != PORT_A)
3835                 return false;
3836
3837         if (dig_port->saved_port_bits & DDI_A_4_LANES)
3838                 return false;
3839
3840         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3841          *                     supported configuration
3842          */
3843         if (IS_GEN9_LP(dev_priv))
3844                 return true;
3845
3846         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3847          *             one who does also have a full A/E split called
3848          *             DDI_F what makes DDI_E useless. However for this
3849          *             case let's trust VBT info.
3850          */
3851         if (IS_CANNONLAKE(dev_priv) &&
3852             !intel_bios_is_port_present(dev_priv, PORT_E))
3853                 return true;
3854
3855         return false;
3856 }
3857
3858 static int
3859 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
3860 {
3861         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3862         enum port port = dig_port->base.port;
3863         int max_lanes = 4;
3864
3865         if (INTEL_GEN(dev_priv) >= 11)
3866                 return max_lanes;
3867
3868         if (port == PORT_A || port == PORT_E) {
3869                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3870                         max_lanes = port == PORT_A ? 4 : 0;
3871                 else
3872                         /* Both A and E share 2 lanes */
3873                         max_lanes = 2;
3874         }
3875
3876         /*
3877          * Some BIOS might fail to set this bit on port A if eDP
3878          * wasn't lit up at boot.  Force this bit set when needed
3879          * so we use the proper lane count for our calculations.
3880          */
3881         if (intel_ddi_a_force_4_lanes(dig_port)) {
3882                 drm_dbg_kms(&dev_priv->drm,
3883                             "Forcing DDI_A_4_LANES for port A\n");
3884                 dig_port->saved_port_bits |= DDI_A_4_LANES;
3885                 max_lanes = 4;
3886         }
3887
3888         return max_lanes;
3889 }
3890
3891 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
3892 {
3893         return i915->hti_state & HDPORT_ENABLED &&
3894                i915->hti_state & HDPORT_DDI_USED(phy);
3895 }
3896
3897 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
3898                                 enum port port)
3899 {
3900         if (port >= PORT_TC1)
3901                 return HPD_PORT_C + port - PORT_TC1;
3902         else
3903                 return HPD_PORT_A + port - PORT_A;
3904 }
3905
3906 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
3907                                 enum port port)
3908 {
3909         if (port >= PORT_TC1)
3910                 return HPD_PORT_TC1 + port - PORT_TC1;
3911         else
3912                 return HPD_PORT_A + port - PORT_A;
3913 }
3914
3915 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
3916                                 enum port port)
3917 {
3918         if (HAS_PCH_TGP(dev_priv))
3919                 return tgl_hpd_pin(dev_priv, port);
3920
3921         if (port >= PORT_TC1)
3922                 return HPD_PORT_C + port - PORT_TC1;
3923         else
3924                 return HPD_PORT_A + port - PORT_A;
3925 }
3926
3927 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
3928                                 enum port port)
3929 {
3930         if (port >= PORT_C)
3931                 return HPD_PORT_TC1 + port - PORT_C;
3932         else
3933                 return HPD_PORT_A + port - PORT_A;
3934 }
3935
3936 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
3937                                 enum port port)
3938 {
3939         if (port == PORT_D)
3940                 return HPD_PORT_A;
3941
3942         if (HAS_PCH_MCC(dev_priv))
3943                 return icl_hpd_pin(dev_priv, port);
3944
3945         return HPD_PORT_A + port - PORT_A;
3946 }
3947
3948 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
3949                                 enum port port)
3950 {
3951         if (port == PORT_F)
3952                 return HPD_PORT_E;
3953
3954         return HPD_PORT_A + port - PORT_A;
3955 }
3956
3957 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
3958 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
3959
3960 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3961 {
3962         struct intel_digital_port *dig_port;
3963         struct intel_encoder *encoder;
3964         bool init_hdmi, init_dp;
3965         enum phy phy = intel_port_to_phy(dev_priv, port);
3966
3967         /*
3968          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
3969          * have taken over some of the PHYs and made them unavailable to the
3970          * driver.  In that case we should skip initializing the corresponding
3971          * outputs.
3972          */
3973         if (hti_uses_phy(dev_priv, phy)) {
3974                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
3975                             port_name(port), phy_name(phy));
3976                 return;
3977         }
3978
3979         init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
3980                 intel_bios_port_supports_hdmi(dev_priv, port);
3981         init_dp = intel_bios_port_supports_dp(dev_priv, port);
3982
3983         if (intel_bios_is_lspcon_present(dev_priv, port)) {
3984                 /*
3985                  * Lspcon device needs to be driven with DP connector
3986                  * with special detection sequence. So make sure DP
3987                  * is initialized before lspcon.
3988                  */
3989                 init_dp = true;
3990                 init_hdmi = false;
3991                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
3992                             port_name(port));
3993         }
3994
3995         if (!init_dp && !init_hdmi) {
3996                 drm_dbg_kms(&dev_priv->drm,
3997                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3998                             port_name(port));
3999                 return;
4000         }
4001
4002         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4003         if (!dig_port)
4004                 return;
4005
4006         encoder = &dig_port->base;
4007
4008         if (INTEL_GEN(dev_priv) >= 12) {
4009                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4010
4011                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4012                                  DRM_MODE_ENCODER_TMDS,
4013                                  "DDI %s%c/PHY %s%c",
4014                                  port >= PORT_TC1 ? "TC" : "",
4015                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4016                                  tc_port != TC_PORT_NONE ? "TC" : "",
4017                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4018         } else if (INTEL_GEN(dev_priv) >= 11) {
4019                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4020
4021                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4022                                  DRM_MODE_ENCODER_TMDS,
4023                                  "DDI %c%s/PHY %s%c",
4024                                  port_name(port),
4025                                  port >= PORT_C ? " (TC)" : "",
4026                                  tc_port != TC_PORT_NONE ? "TC" : "",
4027                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4028         } else {
4029                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4030                                  DRM_MODE_ENCODER_TMDS,
4031                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4032         }
4033
4034         mutex_init(&dig_port->hdcp_mutex);
4035         dig_port->num_hdcp_streams = 0;
4036
4037         encoder->hotplug = intel_ddi_hotplug;
4038         encoder->compute_output_type = intel_ddi_compute_output_type;
4039         encoder->compute_config = intel_ddi_compute_config;
4040         encoder->compute_config_late = intel_ddi_compute_config_late;
4041         encoder->enable = intel_enable_ddi;
4042         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4043         encoder->pre_enable = intel_ddi_pre_enable;
4044         encoder->disable = intel_disable_ddi;
4045         encoder->post_disable = intel_ddi_post_disable;
4046         encoder->update_pipe = intel_ddi_update_pipe;
4047         encoder->get_hw_state = intel_ddi_get_hw_state;
4048         encoder->get_config = intel_ddi_get_config;
4049         encoder->sync_state = intel_ddi_sync_state;
4050         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4051         encoder->suspend = intel_dp_encoder_suspend;
4052         encoder->shutdown = intel_dp_encoder_shutdown;
4053         encoder->get_power_domains = intel_ddi_get_power_domains;
4054
4055         encoder->type = INTEL_OUTPUT_DDI;
4056         encoder->power_domain = intel_port_to_power_domain(port);
4057         encoder->port = port;
4058         encoder->cloneable = 0;
4059         encoder->pipe_mask = ~0;
4060
4061         if (IS_DG1(dev_priv))
4062                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4063         else if (IS_ROCKETLAKE(dev_priv))
4064                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4065         else if (INTEL_GEN(dev_priv) >= 12)
4066                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4067         else if (IS_JSL_EHL(dev_priv))
4068                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4069         else if (IS_GEN(dev_priv, 11))
4070                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4071         else if (IS_GEN(dev_priv, 10))
4072                 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
4073         else
4074                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4075
4076         if (INTEL_GEN(dev_priv) >= 11)
4077                 dig_port->saved_port_bits =
4078                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4079                         & DDI_BUF_PORT_REVERSAL;
4080         else
4081                 dig_port->saved_port_bits =
4082                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4083                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4084
4085         dig_port->dp.output_reg = INVALID_MMIO_REG;
4086         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4087         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4088
4089         if (intel_phy_is_tc(dev_priv, phy)) {
4090                 bool is_legacy =
4091                         !intel_bios_port_supports_typec_usb(dev_priv, port) &&
4092                         !intel_bios_port_supports_tbt(dev_priv, port);
4093
4094                 intel_tc_port_init(dig_port, is_legacy);
4095
4096                 encoder->update_prepare = intel_ddi_update_prepare;
4097                 encoder->update_complete = intel_ddi_update_complete;
4098         }
4099
4100         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4101         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4102                                               port - PORT_A;
4103
4104         if (init_dp) {
4105                 if (!intel_ddi_init_dp_connector(dig_port))
4106                         goto err;
4107
4108                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4109         }
4110
4111         /* In theory we don't need the encoder->type check, but leave it just in
4112          * case we have some really bad VBTs... */
4113         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4114                 if (!intel_ddi_init_hdmi_connector(dig_port))
4115                         goto err;
4116         }
4117
4118         if (INTEL_GEN(dev_priv) >= 11) {
4119                 if (intel_phy_is_tc(dev_priv, phy))
4120                         dig_port->connected = intel_tc_port_connected;
4121                 else
4122                         dig_port->connected = lpt_digital_port_connected;
4123         } else if (INTEL_GEN(dev_priv) >= 8) {
4124                 if (port == PORT_A || IS_GEN9_LP(dev_priv))
4125                         dig_port->connected = bdw_digital_port_connected;
4126                 else
4127                         dig_port->connected = lpt_digital_port_connected;
4128         } else {
4129                 if (port == PORT_A)
4130                         dig_port->connected = hsw_digital_port_connected;
4131                 else
4132                         dig_port->connected = lpt_digital_port_connected;
4133         }
4134
4135         intel_infoframe_init(dig_port);
4136
4137         return;
4138
4139 err:
4140         drm_encoder_cleanup(&encoder->base);
4141         kfree(dig_port);
4142 }