drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_backlight.h"
  33 #include "intel_combo_phy.h"
  34 #include "intel_connector.h"
  35 #include "intel_crtc.h"
  36 #include "intel_ddi.h"
  37 #include "intel_ddi_buf_trans.h"
  38 #include "intel_de.h"
  39 #include "intel_display_types.h"
  40 #include "intel_dp.h"
  41 #include "intel_dp_link_training.h"
  42 #include "intel_dp_mst.h"
  43 #include "intel_dpio_phy.h"
  44 #include "intel_drrs.h"
  45 #include "intel_dsi.h"
  46 #include "intel_fdi.h"
  47 #include "intel_fifo_underrun.h"
  48 #include "intel_gmbus.h"
  49 #include "intel_hdcp.h"
  50 #include "intel_hdmi.h"
  51 #include "intel_hotplug.h"
  52 #include "intel_lspcon.h"
  53 #include "intel_pps.h"
  54 #include "intel_psr.h"
  55 #include "intel_snps_phy.h"
  56 #include "intel_sprite.h"
  57 #include "intel_tc.h"
  58 #include "intel_vdsc.h"
  59 #include "intel_vrr.h"
  60 #include "skl_scaler.h"
  61 #include "skl_universal_plane.h"
  62
  63 static const u8 index_to_dp_signal_levels[] = {
  64         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  68         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  70         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  71         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  72         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  73         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  74 };
  75
  76 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  77                                 const struct intel_ddi_buf_trans *trans)
  78 {
  79         int level;
  80
  81         level = intel_bios_hdmi_level_shift(encoder);
  82         if (level < 0)
  83                 level = trans->hdmi_default_entry;
  84
  85         return level;
  86 }
  87
  88 static bool has_buf_trans_select(struct drm_i915_private *i915)
  89 {
  90         return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
  91 }
  92
  93 static bool has_iboost(struct drm_i915_private *i915)
  94 {
  95         return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
  96 }
  97
  98 /*
  99  * Starting with Haswell, DDI port buffers must be programmed with correct
 100  * values in advance. This function programs the correct values for
 101  * DP/eDP/FDI use cases.
 102  */
 103 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 104                                 const struct intel_crtc_state *crtc_state)
 105 {
 106         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 107         u32 iboost_bit = 0;
 108         int i, n_entries;
 109         enum port port = encoder->port;
 110         const struct intel_ddi_buf_trans *trans;
 111
 112         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 113         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 114                 return;
 115
 116         /* If we're boosting the current, set bit 31 of trans1 */
 117         if (has_iboost(dev_priv) &&
 118             intel_bios_encoder_dp_boost_level(encoder->devdata))
 119                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 120
 121         for (i = 0; i < n_entries; i++) {
 122                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 123                                trans->entries[i].hsw.trans1 | iboost_bit);
 124                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 125                                trans->entries[i].hsw.trans2);
 126         }
 127 }
 128
 129 /*
 130  * Starting with Haswell, DDI port buffers must be programmed with correct
 131  * values in advance. This function programs the correct values for
 132  * HDMI/DVI use cases.
 133  */
 134 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 135                                          const struct intel_crtc_state *crtc_state)
 136 {
 137         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 138         int level = intel_ddi_level(encoder, crtc_state, 0);
 139         u32 iboost_bit = 0;
 140         int n_entries;
 141         enum port port = encoder->port;
 142         const struct intel_ddi_buf_trans *trans;
 143
 144         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 145         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 146                 return;
 147
 148         /* If we're boosting the current, set bit 31 of trans1 */
 149         if (has_iboost(dev_priv) &&
 150             intel_bios_encoder_hdmi_boost_level(encoder->devdata))
 151                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 152
 153         /* Entry 9 is for HDMI: */
 154         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 155                        trans->entries[level].hsw.trans1 | iboost_bit);
 156         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 157                        trans->entries[level].hsw.trans2);
 158 }
 159
 160 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 161                              enum port port)
 162 {
 163         if (IS_BROXTON(dev_priv)) {
 164                 udelay(16);
 165                 return;
 166         }
 167
 168         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 169                          DDI_BUF_IS_IDLE), 8))
 170                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 171                         port_name(port));
 172 }
 173
 174 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 175                                       enum port port)
 176 {
 177         int ret;
 178
 179         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 180         if (DISPLAY_VER(dev_priv) < 10) {
 181                 usleep_range(518, 1000);
 182                 return;
 183         }
 184
 185         ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 186                           DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
 187
 188         if (ret)
 189                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 190                         port_name(port));
 191 }
 192
 193 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 194 {
 195         switch (pll->info->id) {
 196         case DPLL_ID_WRPLL1:
 197                 return PORT_CLK_SEL_WRPLL1;
 198         case DPLL_ID_WRPLL2:
 199                 return PORT_CLK_SEL_WRPLL2;
 200         case DPLL_ID_SPLL:
 201                 return PORT_CLK_SEL_SPLL;
 202         case DPLL_ID_LCPLL_810:
 203                 return PORT_CLK_SEL_LCPLL_810;
 204         case DPLL_ID_LCPLL_1350:
 205                 return PORT_CLK_SEL_LCPLL_1350;
 206         case DPLL_ID_LCPLL_2700:
 207                 return PORT_CLK_SEL_LCPLL_2700;
 208         default:
 209                 MISSING_CASE(pll->info->id);
 210                 return PORT_CLK_SEL_NONE;
 211         }
 212 }
 213
 214 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 215                                   const struct intel_crtc_state *crtc_state)
 216 {
 217         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 218         int clock = crtc_state->port_clock;
 219         const enum intel_dpll_id id = pll->info->id;
 220
 221         switch (id) {
 222         default:
 223                 /*
 224                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 225                  * here, so do warn if this get passed in
 226                  */
 227                 MISSING_CASE(id);
 228                 return DDI_CLK_SEL_NONE;
 229         case DPLL_ID_ICL_TBTPLL:
 230                 switch (clock) {
 231                 case 162000:
 232                         return DDI_CLK_SEL_TBT_162;
 233                 case 270000:
 234                         return DDI_CLK_SEL_TBT_270;
 235                 case 540000:
 236                         return DDI_CLK_SEL_TBT_540;
 237                 case 810000:
 238                         return DDI_CLK_SEL_TBT_810;
 239                 default:
 240                         MISSING_CASE(clock);
 241                         return DDI_CLK_SEL_NONE;
 242                 }
 243         case DPLL_ID_ICL_MGPLL1:
 244         case DPLL_ID_ICL_MGPLL2:
 245         case DPLL_ID_ICL_MGPLL3:
 246         case DPLL_ID_ICL_MGPLL4:
 247         case DPLL_ID_TGL_MGPLL5:
 248         case DPLL_ID_TGL_MGPLL6:
 249                 return DDI_CLK_SEL_MG;
 250         }
 251 }
 252
 253 static u32 ddi_buf_phy_link_rate(int port_clock)
 254 {
 255         switch (port_clock) {
 256         case 162000:
 257                 return DDI_BUF_PHY_LINK_RATE(0);
 258         case 216000:
 259                 return DDI_BUF_PHY_LINK_RATE(4);
 260         case 243000:
 261                 return DDI_BUF_PHY_LINK_RATE(5);
 262         case 270000:
 263                 return DDI_BUF_PHY_LINK_RATE(1);
 264         case 324000:
 265                 return DDI_BUF_PHY_LINK_RATE(6);
 266         case 432000:
 267                 return DDI_BUF_PHY_LINK_RATE(7);
 268         case 540000:
 269                 return DDI_BUF_PHY_LINK_RATE(2);
 270         case 810000:
 271                 return DDI_BUF_PHY_LINK_RATE(3);
 272         default:
 273                 MISSING_CASE(port_clock);
 274                 return DDI_BUF_PHY_LINK_RATE(0);
 275         }
 276 }
 277
 278 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 279                                       const struct intel_crtc_state *crtc_state)
 280 {
 281         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 282         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 283         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 284         enum phy phy = intel_port_to_phy(i915, encoder->port);
 285
 286         /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
 287         intel_dp->DP = dig_port->saved_port_bits |
 288                 DDI_PORT_WIDTH(crtc_state->lane_count) |
 289                 DDI_BUF_TRANS_SELECT(0);
 290
 291         if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 292                 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 293                 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
 294                         intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 295         }
 296 }
 297
 298 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 299                                  enum port port)
 300 {
 301         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 302
 303         switch (val) {
 304         case DDI_CLK_SEL_NONE:
 305                 return 0;
 306         case DDI_CLK_SEL_TBT_162:
 307                 return 162000;
 308         case DDI_CLK_SEL_TBT_270:
 309                 return 270000;
 310         case DDI_CLK_SEL_TBT_540:
 311                 return 540000;
 312         case DDI_CLK_SEL_TBT_810:
 313                 return 810000;
 314         default:
 315                 MISSING_CASE(val);
 316                 return 0;
 317         }
 318 }
 319
 320 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 321 {
 322         int dotclock;
 323
 324         if (pipe_config->has_pch_encoder)
 325                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 326                                                     &pipe_config->fdi_m_n);
 327         else if (intel_crtc_has_dp_encoder(pipe_config))
 328                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 329                                                     &pipe_config->dp_m_n);
 330         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
 331                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
 332         else
 333                 dotclock = pipe_config->port_clock;
 334
 335         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
 336             !intel_crtc_has_dp_encoder(pipe_config))
 337                 dotclock *= 2;
 338
 339         if (pipe_config->pixel_multiplier)
 340                 dotclock /= pipe_config->pixel_multiplier;
 341
 342         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 343 }
 344
 345 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 346                           const struct drm_connector_state *conn_state)
 347 {
 348         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 349         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 350         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 351         u32 temp;
 352
 353         if (!intel_crtc_has_dp_encoder(crtc_state))
 354                 return;
 355
 356         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 357
 358         temp = DP_MSA_MISC_SYNC_CLOCK;
 359
 360         switch (crtc_state->pipe_bpp) {
 361         case 18:
 362                 temp |= DP_MSA_MISC_6_BPC;
 363                 break;
 364         case 24:
 365                 temp |= DP_MSA_MISC_8_BPC;
 366                 break;
 367         case 30:
 368                 temp |= DP_MSA_MISC_10_BPC;
 369                 break;
 370         case 36:
 371                 temp |= DP_MSA_MISC_12_BPC;
 372                 break;
 373         default:
 374                 MISSING_CASE(crtc_state->pipe_bpp);
 375                 break;
 376         }
 377
 378         /* nonsense combination */
 379         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 380                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 381
 382         if (crtc_state->limited_color_range)
 383                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 384
 385         /*
 386          * As per DP 1.2 spec section 2.3.4.3 while sending
 387          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 388          * colorspace information.
 389          */
 390         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 391                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 392
 393         /*
 394          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 395          * of Color Encoding Format and Content Color Gamut] while sending
 396          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 397          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 398          */
 399         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 400                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 401
 402         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 403 }
 404
 405 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 406 {
 407         if (master_transcoder == TRANSCODER_EDP)
 408                 return 0;
 409         else
 410                 return master_transcoder + 1;
 411 }
 412
 413 static void
 414 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
 415                                 const struct intel_crtc_state *crtc_state)
 416 {
 417         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 418         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 419         u32 val = 0;
 420
 421         if (intel_dp_is_uhbr(crtc_state))
 422                 val = TRANS_DP2_128B132B_CHANNEL_CODING;
 423
 424         intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
 425 }
 426
 427 /*
 428  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 429  *
 430  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 431  * intel_ddi_config_transcoder_func().
 432  */
 433 static u32
 434 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 435                                       const struct intel_crtc_state *crtc_state)
 436 {
 437         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 439         enum pipe pipe = crtc->pipe;
 440         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 441         enum port port = encoder->port;
 442         u32 temp;
 443
 444         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 445         temp = TRANS_DDI_FUNC_ENABLE;
 446         if (DISPLAY_VER(dev_priv) >= 12)
 447                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 448         else
 449                 temp |= TRANS_DDI_SELECT_PORT(port);
 450
 451         switch (crtc_state->pipe_bpp) {
 452         case 18:
 453                 temp |= TRANS_DDI_BPC_6;
 454                 break;
 455         case 24:
 456                 temp |= TRANS_DDI_BPC_8;
 457                 break;
 458         case 30:
 459                 temp |= TRANS_DDI_BPC_10;
 460                 break;
 461         case 36:
 462                 temp |= TRANS_DDI_BPC_12;
 463                 break;
 464         default:
 465                 BUG();
 466         }
 467
 468         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 469                 temp |= TRANS_DDI_PVSYNC;
 470         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 471                 temp |= TRANS_DDI_PHSYNC;
 472
 473         if (cpu_transcoder == TRANSCODER_EDP) {
 474                 switch (pipe) {
 475                 case PIPE_A:
 476                         /* On Haswell, can only use the always-on power well for
 477                          * eDP when not using the panel fitter, and when not
 478                          * using motion blur mitigation (which we don't
 479                          * support). */
 480                         if (crtc_state->pch_pfit.force_thru)
 481                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 482                         else
 483                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 484                         break;
 485                 case PIPE_B:
 486                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 487                         break;
 488                 case PIPE_C:
 489                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 490                         break;
 491                 default:
 492                         BUG();
 493                         break;
 494                 }
 495         }
 496
 497         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 498                 if (crtc_state->has_hdmi_sink)
 499                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 500                 else
 501                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 502
 503                 if (crtc_state->hdmi_scrambling)
 504                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 505                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 506                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 507         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 508                 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 509                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 510         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 511                 if (intel_dp_is_uhbr(crtc_state))
 512                         temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 513                 else
 514                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 515                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 516
 517                 if (DISPLAY_VER(dev_priv) >= 12) {
 518                         enum transcoder master;
 519
 520                         master = crtc_state->mst_master_transcoder;
 521                         drm_WARN_ON(&dev_priv->drm,
 522                                     master == INVALID_TRANSCODER);
 523                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 524                 }
 525         } else {
 526                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 527                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 528         }
 529
 530         if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 531             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 532                 u8 master_select =
 533                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 534
 535                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 536                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 537         }
 538
 539         return temp;
 540 }
 541
 542 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 543                                       const struct intel_crtc_state *crtc_state)
 544 {
 545         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 546         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 547         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 548
 549         if (DISPLAY_VER(dev_priv) >= 11) {
 550                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 551                 u32 ctl2 = 0;
 552
 553                 if (master_transcoder != INVALID_TRANSCODER) {
 554                         u8 master_select =
 555                                 bdw_trans_port_sync_master_select(master_transcoder);
 556
 557                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 558                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 559                 }
 560
 561                 intel_de_write(dev_priv,
 562                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 563         }
 564
 565         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 566                        intel_ddi_transcoder_func_reg_val_get(encoder,
 567                                                              crtc_state));
 568 }
 569
 570 /*
 571  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 572  * bit.
 573  */
 574 static void
 575 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 576                                  const struct intel_crtc_state *crtc_state)
 577 {
 578         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 579         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 580         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 581         u32 ctl;
 582
 583         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 584         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 585         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 586 }
 587
 588 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 589 {
 590         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 591         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 592         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 593         u32 ctl;
 594
 595         if (DISPLAY_VER(dev_priv) >= 11)
 596                 intel_de_write(dev_priv,
 597                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 598
 599         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 600
 601         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 602
 603         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 604
 605         if (IS_DISPLAY_VER(dev_priv, 8, 10))
 606                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 607                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 608
 609         if (DISPLAY_VER(dev_priv) >= 12) {
 610                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 611                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 612                                  TRANS_DDI_MODE_SELECT_MASK);
 613                 }
 614         } else {
 615                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 616         }
 617
 618         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 619
 620         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
 621             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 622                 drm_dbg_kms(&dev_priv->drm,
 623                             "Quirk Increase DDI disabled time\n");
 624                 /* Quirk time at 100ms for reliable operation */
 625                 msleep(100);
 626         }
 627 }
 628
 629 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 630                                enum transcoder cpu_transcoder,
 631                                bool enable, u32 hdcp_mask)
 632 {
 633         struct drm_device *dev = intel_encoder->base.dev;
 634         struct drm_i915_private *dev_priv = to_i915(dev);
 635         intel_wakeref_t wakeref;
 636         int ret = 0;
 637         u32 tmp;
 638
 639         wakeref = intel_display_power_get_if_enabled(dev_priv,
 640                                                      intel_encoder->power_domain);
 641         if (drm_WARN_ON(dev, !wakeref))
 642                 return -ENXIO;
 643
 644         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 645         if (enable)
 646                 tmp |= hdcp_mask;
 647         else
 648                 tmp &= ~hdcp_mask;
 649         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
 650         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 651         return ret;
 652 }
 653
 654 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 655 {
 656         struct drm_device *dev = intel_connector->base.dev;
 657         struct drm_i915_private *dev_priv = to_i915(dev);
 658         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 659         int type = intel_connector->base.connector_type;
 660         enum port port = encoder->port;
 661         enum transcoder cpu_transcoder;
 662         intel_wakeref_t wakeref;
 663         enum pipe pipe = 0;
 664         u32 tmp;
 665         bool ret;
 666
 667         wakeref = intel_display_power_get_if_enabled(dev_priv,
 668                                                      encoder->power_domain);
 669         if (!wakeref)
 670                 return false;
 671
 672         if (!encoder->get_hw_state(encoder, &pipe)) {
 673                 ret = false;
 674                 goto out;
 675         }
 676
 677         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 678                 cpu_transcoder = TRANSCODER_EDP;
 679         else
 680                 cpu_transcoder = (enum transcoder) pipe;
 681
 682         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 683
 684         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 685         case TRANS_DDI_MODE_SELECT_HDMI:
 686         case TRANS_DDI_MODE_SELECT_DVI:
 687                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 688                 break;
 689
 690         case TRANS_DDI_MODE_SELECT_DP_SST:
 691                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 692                       type == DRM_MODE_CONNECTOR_DisplayPort;
 693                 break;
 694
 695         case TRANS_DDI_MODE_SELECT_DP_MST:
 696                 /* if the transcoder is in MST state then
 697                  * connector isn't connected */
 698                 ret = false;
 699                 break;
 700
 701         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
 702                 if (HAS_DP20(dev_priv))
 703                         /* 128b/132b */
 704                         ret = false;
 705                 else
 706                         /* FDI */
 707                         ret = type == DRM_MODE_CONNECTOR_VGA;
 708                 break;
 709
 710         default:
 711                 ret = false;
 712                 break;
 713         }
 714
 715 out:
 716         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 717
 718         return ret;
 719 }
 720
 721 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 722                                         u8 *pipe_mask, bool *is_dp_mst)
 723 {
 724         struct drm_device *dev = encoder->base.dev;
 725         struct drm_i915_private *dev_priv = to_i915(dev);
 726         enum port port = encoder->port;
 727         intel_wakeref_t wakeref;
 728         enum pipe p;
 729         u32 tmp;
 730         u8 mst_pipe_mask;
 731
 732         *pipe_mask = 0;
 733         *is_dp_mst = false;
 734
 735         wakeref = intel_display_power_get_if_enabled(dev_priv,
 736                                                      encoder->power_domain);
 737         if (!wakeref)
 738                 return;
 739
 740         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 741         if (!(tmp & DDI_BUF_CTL_ENABLE))
 742                 goto out;
 743
 744         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 745                 tmp = intel_de_read(dev_priv,
 746                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 747
 748                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 749                 default:
 750                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 751                         fallthrough;
 752                 case TRANS_DDI_EDP_INPUT_A_ON:
 753                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 754                         *pipe_mask = BIT(PIPE_A);
 755                         break;
 756                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 757                         *pipe_mask = BIT(PIPE_B);
 758                         break;
 759                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 760                         *pipe_mask = BIT(PIPE_C);
 761                         break;
 762                 }
 763
 764                 goto out;
 765         }
 766
 767         mst_pipe_mask = 0;
 768         for_each_pipe(dev_priv, p) {
 769                 enum transcoder cpu_transcoder = (enum transcoder)p;
 770                 unsigned int port_mask, ddi_select;
 771                 intel_wakeref_t trans_wakeref;
 772
 773                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 774                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 775                 if (!trans_wakeref)
 776                         continue;
 777
 778                 if (DISPLAY_VER(dev_priv) >= 12) {
 779                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 780                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 781                 } else {
 782                         port_mask = TRANS_DDI_PORT_MASK;
 783                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 784                 }
 785
 786                 tmp = intel_de_read(dev_priv,
 787                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 788                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 789                                         trans_wakeref);
 790
 791                 if ((tmp & port_mask) != ddi_select)
 792                         continue;
 793
 794                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
 795                     (HAS_DP20(dev_priv) &&
 796                      (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
 797                         mst_pipe_mask |= BIT(p);
 798
 799                 *pipe_mask |= BIT(p);
 800         }
 801
 802         if (!*pipe_mask)
 803                 drm_dbg_kms(&dev_priv->drm,
 804                             "No pipe for [ENCODER:%d:%s] found\n",
 805                             encoder->base.base.id, encoder->base.name);
 806
 807         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 808                 drm_dbg_kms(&dev_priv->drm,
 809                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 810                             encoder->base.base.id, encoder->base.name,
 811                             *pipe_mask);
 812                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 813         }
 814
 815         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 816                 drm_dbg_kms(&dev_priv->drm,
 817                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 818                             encoder->base.base.id, encoder->base.name,
 819                             *pipe_mask, mst_pipe_mask);
 820         else
 821                 *is_dp_mst = mst_pipe_mask;
 822
 823 out:
 824         if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 825                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 826                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 827                             BXT_PHY_LANE_POWERDOWN_ACK |
 828                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 829                         drm_err(&dev_priv->drm,
 830                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 831                                 encoder->base.base.id, encoder->base.name, tmp);
 832         }
 833
 834         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 835 }
 836
 837 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 838                             enum pipe *pipe)
 839 {
 840         u8 pipe_mask;
 841         bool is_mst;
 842
 843         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 844
 845         if (is_mst || !pipe_mask)
 846                 return false;
 847
 848         *pipe = ffs(pipe_mask) - 1;
 849
 850         return true;
 851 }
 852
 853 static enum intel_display_power_domain
 854 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 855 {
 856         /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 857          * DC states enabled at the same time, while for driver initiated AUX
 858          * transfers we need the same AUX IOs to be powered but with DC states
 859          * disabled. Accordingly use the AUX power domain here which leaves DC
 860          * states enabled.
 861          * However, for non-A AUX ports the corresponding non-EDP transcoders
 862          * would have already enabled power well 2 and DC_OFF. This means we can
 863          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
 864          * specific AUX_IO reference without powering up any extra wells.
 865          * Note that PSR is enabled only on Port A even though this function
 866          * returns the correct domain for other ports too.
 867          */
 868         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
 869                                               intel_aux_power_domain(dig_port);
 870 }
 871
 872 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 873                                         struct intel_crtc_state *crtc_state)
 874 {
 875         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 876         struct intel_digital_port *dig_port;
 877         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 878
 879         /*
 880          * TODO: Add support for MST encoders. Atm, the following should never
 881          * happen since fake-MST encoders don't set their get_power_domains()
 882          * hook.
 883          */
 884         if (drm_WARN_ON(&dev_priv->drm,
 885                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 886                 return;
 887
 888         dig_port = enc_to_dig_port(encoder);
 889
 890         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
 891                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 892                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 893                                                                    dig_port->ddi_io_power_domain);
 894         }
 895
 896         /*
 897          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
 898          * ports.
 899          */
 900         if (intel_crtc_has_dp_encoder(crtc_state) ||
 901             intel_phy_is_tc(dev_priv, phy)) {
 902                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 903                 dig_port->aux_wakeref =
 904                         intel_display_power_get(dev_priv,
 905                                                 intel_ddi_main_link_aux_domain(dig_port));
 906         }
 907 }
 908
 909 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
 910                                  const struct intel_crtc_state *crtc_state)
 911 {
 912         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 913         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 914         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 915         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 916         u32 val;
 917
 918         if (cpu_transcoder != TRANSCODER_EDP) {
 919                 if (DISPLAY_VER(dev_priv) >= 13)
 920                         val = TGL_TRANS_CLK_SEL_PORT(phy);
 921                 else if (DISPLAY_VER(dev_priv) >= 12)
 922                         val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 923                 else
 924                         val = TRANS_CLK_SEL_PORT(encoder->port);
 925
 926                 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 927         }
 928 }
 929
 930 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 931 {
 932         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 933         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 934
 935         if (cpu_transcoder != TRANSCODER_EDP) {
 936                 if (DISPLAY_VER(dev_priv) >= 12)
 937                         intel_de_write(dev_priv,
 938                                        TRANS_CLK_SEL(cpu_transcoder),
 939                                        TGL_TRANS_CLK_SEL_DISABLED);
 940                 else
 941                         intel_de_write(dev_priv,
 942                                        TRANS_CLK_SEL(cpu_transcoder),
 943                                        TRANS_CLK_SEL_DISABLED);
 944         }
 945 }
 946
 947 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 948                                 enum port port, u8 iboost)
 949 {
 950         u32 tmp;
 951
 952         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 953         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 954         if (iboost)
 955                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
 956         else
 957                 tmp |= BALANCE_LEG_DISABLE(port);
 958         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 959 }
 960
 961 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 962                                const struct intel_crtc_state *crtc_state,
 963                                int level)
 964 {
 965         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 966         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 967         u8 iboost;
 968
 969         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 970                 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata);
 971         else
 972                 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);
 973
 974         if (iboost == 0) {
 975                 const struct intel_ddi_buf_trans *trans;
 976                 int n_entries;
 977
 978                 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 979                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 980                         return;
 981
 982                 iboost = trans->entries[level].hsw.i_boost;
 983         }
 984
 985         /* Make sure that the requested I_boost is valid */
 986         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
 987                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
 988                 return;
 989         }
 990
 991         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
 992
 993         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
 994                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
 995 }
 996
 997 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
 998                                    const struct intel_crtc_state *crtc_state)
 999 {
1000         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1001         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1002         int n_entries;
1003
1004         encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1005
1006         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1007                 n_entries = 1;
1008         if (drm_WARN_ON(&dev_priv->drm,
1009                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1010                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1011
1012         return index_to_dp_signal_levels[n_entries - 1] &
1013                 DP_TRAIN_VOLTAGE_SWING_MASK;
1014 }
1015
1016 /*
1017  * We assume that the full set of pre-emphasis values can be
1018  * used on all DDI platforms. Should that change we need to
1019  * rethink this code.
1020  */
1021 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1022 {
1023         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1024 }
1025
1026 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1027                                         int lane)
1028 {
1029         if (crtc_state->port_clock > 600000)
1030                 return 0;
1031
1032         if (crtc_state->lane_count == 4)
1033                 return lane >= 1 ? LOADGEN_SELECT : 0;
1034         else
1035                 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1036 }
1037
1038 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1039                                          const struct intel_crtc_state *crtc_state)
1040 {
1041         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1042         int level = intel_ddi_level(encoder, crtc_state, 0);
1043         const struct intel_ddi_buf_trans *trans;
1044         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1045         int n_entries, ln;
1046         u32 val;
1047
1048         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1049         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1050                 return;
1051
1052         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1053                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1054
1055                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1056                 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1057                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1058                              intel_dp->hobl_active ? val : 0);
1059         }
1060
1061         /* Set PORT_TX_DW5 */
1062         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1063         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1064                   TAP2_DISABLE | TAP3_DISABLE);
1065         val |= SCALING_MODE_SEL(0x2);
1066         val |= RTERM_SELECT(0x6);
1067         val |= TAP3_DISABLE;
1068         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1069
1070         /* Program PORT_TX_DW2 */
1071         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
1072         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1073                  RCOMP_SCALAR_MASK);
1074         val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
1075         val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
1076         /* Program Rcomp scalar for every table entry */
1077         val |= RCOMP_SCALAR(0x98);
1078         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
1079
1080         /* Program PORT_TX_DW4 */
1081         /* We cannot write to GRP. It would overwrite individual loadgen. */
1082         for (ln = 0; ln < 4; ln++) {
1083                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1084                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1085                          CURSOR_COEFF_MASK);
1086                 val |= POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1);
1087                 val |= POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2);
1088                 val |= CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff);
1089                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1090         }
1091
1092         /* Program PORT_TX_DW7 */
1093         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
1094         val &= ~N_SCALAR_MASK;
1095         val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
1096         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
1097 }
1098
1099 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1100                                             const struct intel_crtc_state *crtc_state)
1101 {
1102         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1103         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1104         u32 val;
1105         int ln;
1106
1107         /*
1108          * 1. If port type is eDP or DP,
1109          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1110          * else clear to 0b.
1111          */
1112         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
1113         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1114                 val &= ~COMMON_KEEPER_EN;
1115         else
1116                 val |= COMMON_KEEPER_EN;
1117         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1118
1119         /* 2. Program loadgen select */
1120         /*
1121          * Program PORT_TX_DW4 depending on Bit rate and used lanes
1122          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1123          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1124          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1125          */
1126         for (ln = 0; ln < 4; ln++) {
1127                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1128                 val &= ~LOADGEN_SELECT;
1129                 val |= icl_combo_phy_loadgen_select(crtc_state, ln);
1130                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1131         }
1132
1133         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1134         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
1135         val |= SUS_CLOCK_CONFIG;
1136         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
1137
1138         /* 4. Clear training enable to change swing values */
1139         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1140         val &= ~TX_TRAINING_EN;
1141         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1142
1143         /* 5. Program swing and de-emphasis */
1144         icl_ddi_combo_vswing_program(encoder, crtc_state);
1145
1146         /* 6. Set training enable to trigger update */
1147         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1148         val |= TX_TRAINING_EN;
1149         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1150 }
1151
1152 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1153                                          const struct intel_crtc_state *crtc_state)
1154 {
1155         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1156         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1157         int level = intel_ddi_level(encoder, crtc_state, 0);
1158         const struct intel_ddi_buf_trans *trans;
1159         int n_entries, ln;
1160         u32 val;
1161
1162         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1163                 return;
1164
1165         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1166         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1167                 return;
1168
1169         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
1170         for (ln = 0; ln < 2; ln++) {
1171                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
1172                 val &= ~CRI_USE_FS32;
1173                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
1174
1175                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
1176                 val &= ~CRI_USE_FS32;
1177                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
1178         }
1179
1180         /* Program MG_TX_SWINGCTRL with values from vswing table */
1181         for (ln = 0; ln < 2; ln++) {
1182                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
1183                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1184                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1185                         trans->entries[level].mg.cri_txdeemph_override_17_12);
1186                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
1187
1188                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
1189                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1190                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1191                         trans->entries[level].mg.cri_txdeemph_override_17_12);
1192                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
1193         }
1194
1195         /* Program MG_TX_DRVCTRL with values from vswing table */
1196         for (ln = 0; ln < 2; ln++) {
1197                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
1198                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1199                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1200                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1201                         trans->entries[level].mg.cri_txdeemph_override_5_0) |
1202                         CRI_TXDEEMPH_OVERRIDE_11_6(
1203                                 trans->entries[level].mg.cri_txdeemph_override_11_6) |
1204                         CRI_TXDEEMPH_OVERRIDE_EN;
1205                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
1206
1207                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
1208                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1209                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1210                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1211                         trans->entries[level].mg.cri_txdeemph_override_5_0) |
1212                         CRI_TXDEEMPH_OVERRIDE_11_6(
1213                                 trans->entries[level].mg.cri_txdeemph_override_11_6) |
1214                         CRI_TXDEEMPH_OVERRIDE_EN;
1215                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
1216
1217                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1218         }
1219
1220         /*
1221          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1222          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1223          * values from table for which TX1 and TX2 enabled.
1224          */
1225         for (ln = 0; ln < 2; ln++) {
1226                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
1227                 if (crtc_state->port_clock < 300000)
1228                         val |= CFG_LOW_RATE_LKREN_EN;
1229                 else
1230                         val &= ~CFG_LOW_RATE_LKREN_EN;
1231                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
1232         }
1233
1234         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1235         for (ln = 0; ln < 2; ln++) {
1236                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
1237                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1238                 if (crtc_state->port_clock <= 500000) {
1239                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1240                 } else {
1241                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1242                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1243                 }
1244                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
1245
1246                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
1247                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1248                 if (crtc_state->port_clock <= 500000) {
1249                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1250                 } else {
1251                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1252                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1253                 }
1254                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
1255         }
1256
1257         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1258         for (ln = 0; ln < 2; ln++) {
1259                 val = intel_de_read(dev_priv,
1260                                     MG_TX1_PISO_READLOAD(ln, tc_port));
1261                 val |= CRI_CALCINIT;
1262                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1263                                val);
1264
1265                 val = intel_de_read(dev_priv,
1266                                     MG_TX2_PISO_READLOAD(ln, tc_port));
1267                 val |= CRI_CALCINIT;
1268                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1269                                val);
1270         }
1271 }
1272
1273 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1274                                           const struct intel_crtc_state *crtc_state)
1275 {
1276         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1277         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1278         int level = intel_ddi_level(encoder, crtc_state, 0);
1279         const struct intel_ddi_buf_trans *trans;
1280         u32 val, dpcnt_mask, dpcnt_val;
1281         int n_entries, ln;
1282
1283         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1284                 return;
1285
1286         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1287         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1288                 return;
1289
1290         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
1291                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1292                       DKL_TX_VSWING_CONTROL_MASK);
1293         dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing);
1294         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis);
1295         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
1296
1297         for (ln = 0; ln < 2; ln++) {
1298                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1299                                HIP_INDEX_VAL(tc_port, ln));
1300
1301                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
1302
1303                 /* All the registers are RMW */
1304                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
1305                 val &= ~dpcnt_mask;
1306                 val |= dpcnt_val;
1307                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
1308
1309                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
1310                 val &= ~dpcnt_mask;
1311                 val |= dpcnt_val;
1312                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
1313
1314                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
1315                 val &= ~DKL_TX_DP20BITMODE;
1316                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
1317         }
1318 }
1319
1320 static int translate_signal_level(struct intel_dp *intel_dp,
1321                                   u8 signal_levels)
1322 {
1323         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1324         int i;
1325
1326         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1327                 if (index_to_dp_signal_levels[i] == signal_levels)
1328                         return i;
1329         }
1330
1331         drm_WARN(&i915->drm, 1,
1332                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1333                  signal_levels);
1334
1335         return 0;
1336 }
1337
1338 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1339                               const struct intel_crtc_state *crtc_state,
1340                               int lane)
1341 {
1342         u8 train_set = intel_dp->train_set[lane];
1343
1344         if (intel_dp_is_uhbr(crtc_state)) {
1345                 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1346         } else {
1347                 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1348                                                 DP_TRAIN_PRE_EMPHASIS_MASK);
1349
1350                 return translate_signal_level(intel_dp, signal_levels);
1351         }
1352 }
1353
1354 int intel_ddi_level(struct intel_encoder *encoder,
1355                     const struct intel_crtc_state *crtc_state,
1356                     int lane)
1357 {
1358         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1359         const struct intel_ddi_buf_trans *trans;
1360         int level, n_entries;
1361
1362         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1363         if (drm_WARN_ON_ONCE(&i915->drm, !trans))
1364                 return 0;
1365
1366         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1367                 level = intel_ddi_hdmi_level(encoder, trans);
1368         else
1369                 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1370                                            lane);
1371
1372         if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
1373                 level = n_entries - 1;
1374
1375         return level;
1376 }
1377
1378 static void
1379 hsw_set_signal_levels(struct intel_encoder *encoder,
1380                       const struct intel_crtc_state *crtc_state)
1381 {
1382         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1383         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1384         int level = intel_ddi_level(encoder, crtc_state, 0);
1385         enum port port = encoder->port;
1386         u32 signal_levels;
1387
1388         if (has_iboost(dev_priv))
1389                 skl_ddi_set_iboost(encoder, crtc_state, level);
1390
1391         /* HDMI ignores the rest */
1392         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1393                 return;
1394
1395         signal_levels = DDI_BUF_TRANS_SELECT(level);
1396
1397         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1398                     signal_levels);
1399
1400         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1401         intel_dp->DP |= signal_levels;
1402
1403         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1404         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1405 }
1406
1407 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1408                                   u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1409 {
1410         mutex_lock(&i915->dpll.lock);
1411
1412         intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1413
1414         /*
1415          * "This step and the step before must be
1416          *  done with separate register writes."
1417          */
1418         intel_de_rmw(i915, reg, clk_off, 0);
1419
1420         mutex_unlock(&i915->dpll.lock);
1421 }
1422
1423 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1424                                    u32 clk_off)
1425 {
1426         mutex_lock(&i915->dpll.lock);
1427
1428         intel_de_rmw(i915, reg, 0, clk_off);
1429
1430         mutex_unlock(&i915->dpll.lock);
1431 }
1432
1433 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1434                                       u32 clk_off)
1435 {
1436         return !(intel_de_read(i915, reg) & clk_off);
1437 }
1438
1439 static struct intel_shared_dpll *
1440 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1441                  u32 clk_sel_mask, u32 clk_sel_shift)
1442 {
1443         enum intel_dpll_id id;
1444
1445         id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1446
1447         return intel_get_shared_dpll_by_id(i915, id);
1448 }
1449
1450 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1451                                   const struct intel_crtc_state *crtc_state)
1452 {
1453         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1454         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1455         enum phy phy = intel_port_to_phy(i915, encoder->port);
1456
1457         if (drm_WARN_ON(&i915->drm, !pll))
1458                 return;
1459
1460         _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1461                               ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1462                               pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1463                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1464 }
1465
1466 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1467 {
1468         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1469         enum phy phy = intel_port_to_phy(i915, encoder->port);
1470
1471         _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1472                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1473 }
1474
1475 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1476 {
1477         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1478         enum phy phy = intel_port_to_phy(i915, encoder->port);
1479
1480         return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1481                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1482 }
1483
1484 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1485 {
1486         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1487         enum phy phy = intel_port_to_phy(i915, encoder->port);
1488
1489         return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1490                                 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1491                                 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1492 }
1493
1494 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1495                                  const struct intel_crtc_state *crtc_state)
1496 {
1497         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1498         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1499         enum phy phy = intel_port_to_phy(i915, encoder->port);
1500
1501         if (drm_WARN_ON(&i915->drm, !pll))
1502                 return;
1503
1504         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1505                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1506                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1507                               RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1508 }
1509
1510 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1511 {
1512         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1513         enum phy phy = intel_port_to_phy(i915, encoder->port);
1514
1515         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1516                                RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1517 }
1518
1519 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1520 {
1521         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1522         enum phy phy = intel_port_to_phy(i915, encoder->port);
1523
1524         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1525                                          RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1526 }
1527
1528 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1529 {
1530         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1531         enum phy phy = intel_port_to_phy(i915, encoder->port);
1532
1533         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1534                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1535                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1536 }
1537
1538 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1539                                  const struct intel_crtc_state *crtc_state)
1540 {
1541         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1542         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1543         enum phy phy = intel_port_to_phy(i915, encoder->port);
1544
1545         if (drm_WARN_ON(&i915->drm, !pll))
1546                 return;
1547
1548         /*
1549          * If we fail this, something went very wrong: first 2 PLLs should be
1550          * used by first 2 phys and last 2 PLLs by last phys
1551          */
1552         if (drm_WARN_ON(&i915->drm,
1553                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1554                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1555                 return;
1556
1557         _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1558                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1559                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1560                               DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1561 }
1562
1563 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1564 {
1565         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1566         enum phy phy = intel_port_to_phy(i915, encoder->port);
1567
1568         _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1569                                DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1570 }
1571
1572 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1573 {
1574         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1575         enum phy phy = intel_port_to_phy(i915, encoder->port);
1576
1577         return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1578                                          DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1579 }
1580
1581 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1582 {
1583         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1584         enum phy phy = intel_port_to_phy(i915, encoder->port);
1585         enum intel_dpll_id id;
1586         u32 val;
1587
1588         val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1589         val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1590         val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1591         id = val;
1592
1593         /*
1594          * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1595          * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1596          * bit for phy C and D.
1597          */
1598         if (phy >= PHY_C)
1599                 id += DPLL_ID_DG1_DPLL2;
1600
1601         return intel_get_shared_dpll_by_id(i915, id);
1602 }
1603
1604 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1605                                        const struct intel_crtc_state *crtc_state)
1606 {
1607         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1608         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1609         enum phy phy = intel_port_to_phy(i915, encoder->port);
1610
1611         if (drm_WARN_ON(&i915->drm, !pll))
1612                 return;
1613
1614         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1615                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1616                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1617                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1618 }
1619
1620 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1621 {
1622         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1623         enum phy phy = intel_port_to_phy(i915, encoder->port);
1624
1625         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1626                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1627 }
1628
1629 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1630 {
1631         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1632         enum phy phy = intel_port_to_phy(i915, encoder->port);
1633
1634         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1635                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1636 }
1637
1638 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1639 {
1640         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1641         enum phy phy = intel_port_to_phy(i915, encoder->port);
1642
1643         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1644                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1645                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1646 }
1647
1648 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1649                                     const struct intel_crtc_state *crtc_state)
1650 {
1651         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1652         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1653         enum port port = encoder->port;
1654
1655         if (drm_WARN_ON(&i915->drm, !pll))
1656                 return;
1657
1658         /*
1659          * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1660          *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1661          */
1662         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1663
1664         icl_ddi_combo_enable_clock(encoder, crtc_state);
1665 }
1666
1667 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1668 {
1669         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1670         enum port port = encoder->port;
1671
1672         icl_ddi_combo_disable_clock(encoder);
1673
1674         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1675 }
1676
1677 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1678 {
1679         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1680         enum port port = encoder->port;
1681         u32 tmp;
1682
1683         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1684
1685         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1686                 return false;
1687
1688         return icl_ddi_combo_is_clock_enabled(encoder);
1689 }
1690
1691 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1692                                     const struct intel_crtc_state *crtc_state)
1693 {
1694         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1695         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1696         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1697         enum port port = encoder->port;
1698
1699         if (drm_WARN_ON(&i915->drm, !pll))
1700                 return;
1701
1702         intel_de_write(i915, DDI_CLK_SEL(port),
1703                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1704
1705         mutex_lock(&i915->dpll.lock);
1706
1707         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1708                      ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1709
1710         mutex_unlock(&i915->dpll.lock);
1711 }
1712
1713 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1714 {
1715         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1716         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1717         enum port port = encoder->port;
1718
1719         mutex_lock(&i915->dpll.lock);
1720
1721         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1722                      0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1723
1724         mutex_unlock(&i915->dpll.lock);
1725
1726         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1727 }
1728
1729 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1730 {
1731         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1732         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1733         enum port port = encoder->port;
1734         u32 tmp;
1735
1736         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1737
1738         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1739                 return false;
1740
1741         tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1742
1743         return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1744 }
1745
1746 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1747 {
1748         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1749         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1750         enum port port = encoder->port;
1751         enum intel_dpll_id id;
1752         u32 tmp;
1753
1754         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1755
1756         switch (tmp & DDI_CLK_SEL_MASK) {
1757         case DDI_CLK_SEL_TBT_162:
1758         case DDI_CLK_SEL_TBT_270:
1759         case DDI_CLK_SEL_TBT_540:
1760         case DDI_CLK_SEL_TBT_810:
1761                 id = DPLL_ID_ICL_TBTPLL;
1762                 break;
1763         case DDI_CLK_SEL_MG:
1764                 id = icl_tc_port_to_pll_id(tc_port);
1765                 break;
1766         default:
1767                 MISSING_CASE(tmp);
1768                 fallthrough;
1769         case DDI_CLK_SEL_NONE:
1770                 return NULL;
1771         }
1772
1773         return intel_get_shared_dpll_by_id(i915, id);
1774 }
1775
1776 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1777 {
1778         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1779         enum intel_dpll_id id;
1780
1781         switch (encoder->port) {
1782         case PORT_A:
1783                 id = DPLL_ID_SKL_DPLL0;
1784                 break;
1785         case PORT_B:
1786                 id = DPLL_ID_SKL_DPLL1;
1787                 break;
1788         case PORT_C:
1789                 id = DPLL_ID_SKL_DPLL2;
1790                 break;
1791         default:
1792                 MISSING_CASE(encoder->port);
1793                 return NULL;
1794         }
1795
1796         return intel_get_shared_dpll_by_id(i915, id);
1797 }
1798
1799 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1800                                  const struct intel_crtc_state *crtc_state)
1801 {
1802         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1803         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1804         enum port port = encoder->port;
1805
1806         if (drm_WARN_ON(&i915->drm, !pll))
1807                 return;
1808
1809         mutex_lock(&i915->dpll.lock);
1810
1811         intel_de_rmw(i915, DPLL_CTRL2,
1812                      DPLL_CTRL2_DDI_CLK_OFF(port) |
1813                      DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1814                      DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1815                      DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1816
1817         mutex_unlock(&i915->dpll.lock);
1818 }
1819
1820 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1821 {
1822         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1823         enum port port = encoder->port;
1824
1825         mutex_lock(&i915->dpll.lock);
1826
1827         intel_de_rmw(i915, DPLL_CTRL2,
1828                      0, DPLL_CTRL2_DDI_CLK_OFF(port));
1829
1830         mutex_unlock(&i915->dpll.lock);
1831 }
1832
1833 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1834 {
1835         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1836         enum port port = encoder->port;
1837
1838         /*
1839          * FIXME Not sure if the override affects both
1840          * the PLL selection and the CLK_OFF bit.
1841          */
1842         return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1843 }
1844
1845 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1846 {
1847         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1848         enum port port = encoder->port;
1849         enum intel_dpll_id id;
1850         u32 tmp;
1851
1852         tmp = intel_de_read(i915, DPLL_CTRL2);
1853
1854         /*
1855          * FIXME Not sure if the override affects both
1856          * the PLL selection and the CLK_OFF bit.
1857          */
1858         if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1859                 return NULL;
1860
1861         id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1862                 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1863
1864         return intel_get_shared_dpll_by_id(i915, id);
1865 }
1866
1867 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1868                           const struct intel_crtc_state *crtc_state)
1869 {
1870         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1871         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1872         enum port port = encoder->port;
1873
1874         if (drm_WARN_ON(&i915->drm, !pll))
1875                 return;
1876
1877         intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1878 }
1879
1880 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1881 {
1882         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1883         enum port port = encoder->port;
1884
1885         intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1886 }
1887
1888 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1889 {
1890         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1891         enum port port = encoder->port;
1892
1893         return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1894 }
1895
1896 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1897 {
1898         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1899         enum port port = encoder->port;
1900         enum intel_dpll_id id;
1901         u32 tmp;
1902
1903         tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1904
1905         switch (tmp & PORT_CLK_SEL_MASK) {
1906         case PORT_CLK_SEL_WRPLL1:
1907                 id = DPLL_ID_WRPLL1;
1908                 break;
1909         case PORT_CLK_SEL_WRPLL2:
1910                 id = DPLL_ID_WRPLL2;
1911                 break;
1912         case PORT_CLK_SEL_SPLL:
1913                 id = DPLL_ID_SPLL;
1914                 break;
1915         case PORT_CLK_SEL_LCPLL_810:
1916                 id = DPLL_ID_LCPLL_810;
1917                 break;
1918         case PORT_CLK_SEL_LCPLL_1350:
1919                 id = DPLL_ID_LCPLL_1350;
1920                 break;
1921         case PORT_CLK_SEL_LCPLL_2700:
1922                 id = DPLL_ID_LCPLL_2700;
1923                 break;
1924         default:
1925                 MISSING_CASE(tmp);
1926                 fallthrough;
1927         case PORT_CLK_SEL_NONE:
1928                 return NULL;
1929         }
1930
1931         return intel_get_shared_dpll_by_id(i915, id);
1932 }
1933
1934 void intel_ddi_enable_clock(struct intel_encoder *encoder,
1935                             const struct intel_crtc_state *crtc_state)
1936 {
1937         if (encoder->enable_clock)
1938                 encoder->enable_clock(encoder, crtc_state);
1939 }
1940
1941 static void intel_ddi_disable_clock(struct intel_encoder *encoder)
1942 {
1943         if (encoder->disable_clock)
1944                 encoder->disable_clock(encoder);
1945 }
1946
1947 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
1948 {
1949         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1950         u32 port_mask;
1951         bool ddi_clk_needed;
1952
1953         /*
1954          * In case of DP MST, we sanitize the primary encoder only, not the
1955          * virtual ones.
1956          */
1957         if (encoder->type == INTEL_OUTPUT_DP_MST)
1958                 return;
1959
1960         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
1961                 u8 pipe_mask;
1962                 bool is_mst;
1963
1964                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
1965                 /*
1966                  * In the unlikely case that BIOS enables DP in MST mode, just
1967                  * warn since our MST HW readout is incomplete.
1968                  */
1969                 if (drm_WARN_ON(&i915->drm, is_mst))
1970                         return;
1971         }
1972
1973         port_mask = BIT(encoder->port);
1974         ddi_clk_needed = encoder->base.crtc;
1975
1976         if (encoder->type == INTEL_OUTPUT_DSI) {
1977                 struct intel_encoder *other_encoder;
1978
1979                 port_mask = intel_dsi_encoder_ports(encoder);
1980                 /*
1981                  * Sanity check that we haven't incorrectly registered another
1982                  * encoder using any of the ports of this DSI encoder.
1983                  */
1984                 for_each_intel_encoder(&i915->drm, other_encoder) {
1985                         if (other_encoder == encoder)
1986                                 continue;
1987
1988                         if (drm_WARN_ON(&i915->drm,
1989                                         port_mask & BIT(other_encoder->port)))
1990                                 return;
1991                 }
1992                 /*
1993                  * For DSI we keep the ddi clocks gated
1994                  * except during enable/disable sequence.
1995                  */
1996                 ddi_clk_needed = false;
1997         }
1998
1999         if (ddi_clk_needed || !encoder->is_clock_enabled ||
2000             !encoder->is_clock_enabled(encoder))
2001                 return;
2002
2003         drm_notice(&i915->drm,
2004                    "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2005                    encoder->base.base.id, encoder->base.name);
2006
2007         encoder->disable_clock(encoder);
2008 }
2009
2010 static void
2011 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2012                        const struct intel_crtc_state *crtc_state)
2013 {
2014         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2015         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2016         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2017         u32 ln0, ln1, pin_assignment;
2018         u8 width;
2019
2020         if (!intel_phy_is_tc(dev_priv, phy) ||
2021             intel_tc_port_in_tbt_alt_mode(dig_port))
2022                 return;
2023
2024         if (DISPLAY_VER(dev_priv) >= 12) {
2025                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2026                                HIP_INDEX_VAL(tc_port, 0x0));
2027                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2028                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2029                                HIP_INDEX_VAL(tc_port, 0x1));
2030                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2031         } else {
2032                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2033                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2034         }
2035
2036         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2037         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2038
2039         /* DPPATC */
2040         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2041         width = crtc_state->lane_count;
2042
2043         switch (pin_assignment) {
2044         case 0x0:
2045                 drm_WARN_ON(&dev_priv->drm,
2046                             !intel_tc_port_in_legacy_mode(dig_port));
2047                 if (width == 1) {
2048                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2049                 } else {
2050                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2051                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2052                 }
2053                 break;
2054         case 0x1:
2055                 if (width == 4) {
2056                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2057                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2058                 }
2059                 break;
2060         case 0x2:
2061                 if (width == 2) {
2062                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2063                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2064                 }
2065                 break;
2066         case 0x3:
2067         case 0x5:
2068                 if (width == 1) {
2069                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2070                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2071                 } else {
2072                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2073                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2074                 }
2075                 break;
2076         case 0x4:
2077         case 0x6:
2078                 if (width == 1) {
2079                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2080                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2081                 } else {
2082                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2083                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(pin_assignment);
2088         }
2089
2090         if (DISPLAY_VER(dev_priv) >= 12) {
2091                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2092                                HIP_INDEX_VAL(tc_port, 0x0));
2093                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2094                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2095                                HIP_INDEX_VAL(tc_port, 0x1));
2096                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2097         } else {
2098                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2099                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2100         }
2101 }
2102
2103 static enum transcoder
2104 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2105 {
2106         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2107                 return crtc_state->mst_master_transcoder;
2108         else
2109                 return crtc_state->cpu_transcoder;
2110 }
2111
2112 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2113                          const struct intel_crtc_state *crtc_state)
2114 {
2115         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2116
2117         if (DISPLAY_VER(dev_priv) >= 12)
2118                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2119         else
2120                 return DP_TP_CTL(encoder->port);
2121 }
2122
2123 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2124                             const struct intel_crtc_state *crtc_state)
2125 {
2126         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2127
2128         if (DISPLAY_VER(dev_priv) >= 12)
2129                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2130         else
2131                 return DP_TP_STATUS(encoder->port);
2132 }
2133
2134 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2135                                                           const struct intel_crtc_state *crtc_state,
2136                                                           bool enable)
2137 {
2138         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2139
2140         if (!crtc_state->vrr.enable)
2141                 return;
2142
2143         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2144                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2145                 drm_dbg_kms(&i915->drm,
2146                             "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2147                             enabledisable(enable));
2148 }
2149
2150 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2151                                         const struct intel_crtc_state *crtc_state)
2152 {
2153         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2154
2155         if (!crtc_state->fec_enable)
2156                 return;
2157
2158         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2159                 drm_dbg_kms(&i915->drm,
2160                             "Failed to set FEC_READY in the sink\n");
2161 }
2162
2163 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2164                                  const struct intel_crtc_state *crtc_state)
2165 {
2166         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2167         struct intel_dp *intel_dp;
2168         u32 val;
2169
2170         if (!crtc_state->fec_enable)
2171                 return;
2172
2173         intel_dp = enc_to_intel_dp(encoder);
2174         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2175         val |= DP_TP_CTL_FEC_ENABLE;
2176         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2177 }
2178
2179 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2180                                         const struct intel_crtc_state *crtc_state)
2181 {
2182         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2183         struct intel_dp *intel_dp;
2184         u32 val;
2185
2186         if (!crtc_state->fec_enable)
2187                 return;
2188
2189         intel_dp = enc_to_intel_dp(encoder);
2190         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2191         val &= ~DP_TP_CTL_FEC_ENABLE;
2192         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2193         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2194 }
2195
2196 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2197                                      const struct intel_crtc_state *crtc_state)
2198 {
2199         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2200         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2201         enum phy phy = intel_port_to_phy(i915, encoder->port);
2202
2203         if (intel_phy_is_combo(i915, phy)) {
2204                 bool lane_reversal =
2205                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2206
2207                 intel_combo_phy_power_up_lanes(i915, phy, false,
2208                                                crtc_state->lane_count,
2209                                                lane_reversal);
2210         }
2211 }
2212
2213 /* Splitter enable for eDP MSO is limited to certain pipes. */
2214 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2215 {
2216         if (IS_ALDERLAKE_P(i915))
2217                 return BIT(PIPE_A) | BIT(PIPE_B);
2218         else
2219                 return BIT(PIPE_A);
2220 }
2221
2222 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2223                                      struct intel_crtc_state *pipe_config)
2224 {
2225         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2226         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2227         enum pipe pipe = crtc->pipe;
2228         u32 dss1;
2229
2230         if (!HAS_MSO(i915))
2231                 return;
2232
2233         dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2234
2235         pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2236         if (!pipe_config->splitter.enable)
2237                 return;
2238
2239         if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2240                 pipe_config->splitter.enable = false;
2241                 return;
2242         }
2243
2244         switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2245         default:
2246                 drm_WARN(&i915->drm, true,
2247                          "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2248                 fallthrough;
2249         case SPLITTER_CONFIGURATION_2_SEGMENT:
2250                 pipe_config->splitter.link_count = 2;
2251                 break;
2252         case SPLITTER_CONFIGURATION_4_SEGMENT:
2253                 pipe_config->splitter.link_count = 4;
2254                 break;
2255         }
2256
2257         pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2258 }
2259
2260 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2261 {
2262         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2263         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2264         enum pipe pipe = crtc->pipe;
2265         u32 dss1 = 0;
2266
2267         if (!HAS_MSO(i915))
2268                 return;
2269
2270         if (crtc_state->splitter.enable) {
2271                 dss1 |= SPLITTER_ENABLE;
2272                 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2273                 if (crtc_state->splitter.link_count == 2)
2274                         dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2275                 else
2276                         dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2277         }
2278
2279         intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2280                      SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2281                      OVERLAP_PIXELS_MASK, dss1);
2282 }
2283
2284 static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
2285                                   struct intel_encoder *encoder,
2286                                   const struct intel_crtc_state *crtc_state,
2287                                   const struct drm_connector_state *conn_state)
2288 {
2289         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2290         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2291         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2292         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2293
2294         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2295                                  crtc_state->lane_count);
2296
2297         /*
2298          * We only configure what the register value will be here.  Actual
2299          * enabling happens during link training farther down.
2300          */
2301         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2302
2303         /*
2304          * 1. Enable Power Wells
2305          *
2306          * This was handled at the beginning of intel_atomic_commit_tail(),
2307          * before we called down into this function.
2308          */
2309
2310         /* 2. Enable Panel Power if PPS is required */
2311         intel_pps_on(intel_dp);
2312
2313         /*
2314          * 3. Enable the port PLL.
2315          */
2316         intel_ddi_enable_clock(encoder, crtc_state);
2317
2318         /* 4. Enable IO power */
2319         if (!intel_tc_port_in_tbt_alt_mode(dig_port))
2320                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2321                                                                    dig_port->ddi_io_power_domain);
2322
2323         /*
2324          * 5. The rest of the below are substeps under the bspec's "Enable and
2325          * Train Display Port" step.  Note that steps that are specific to
2326          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2327          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2328          * us when active_mst_links==0, so any steps designated for "single
2329          * stream or multi-stream master transcoder" can just be performed
2330          * unconditionally here.
2331          */
2332
2333         /*
2334          * 5.a Configure Transcoder Clock Select to direct the Port clock to the
2335          * Transcoder.
2336          */
2337         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2338
2339         /* 5.b Configure transcoder for DP 2.0 128b/132b */
2340         intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2341
2342         /*
2343          * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2344          * Transport Select
2345          */
2346         intel_ddi_config_transcoder_func(encoder, crtc_state);
2347
2348         /*
2349          * 5.d Configure & enable DP_TP_CTL with link training pattern 1
2350          * selected
2351          *
2352          * This will be handled by the intel_dp_start_link_train() farther
2353          * down this function.
2354          */
2355
2356         /* 5.e Configure voltage swing and related IO settings */
2357         encoder->set_signal_levels(encoder, crtc_state);
2358
2359         if (!is_mst)
2360                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2361
2362         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2363         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2364         /*
2365          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2366          * in the FEC_CONFIGURATION register to 1 before initiating link
2367          * training
2368          */
2369         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2370         intel_dp_check_frl_training(intel_dp);
2371         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2372
2373         /*
2374          * 5.h Follow DisplayPort specification training sequence (see notes for
2375          *     failure handling)
2376          * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2377          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2378          *     (timeout after 800 us)
2379          */
2380         intel_dp_start_link_train(intel_dp, crtc_state);
2381
2382         /* 5.j Set DP_TP_CTL link training to Normal */
2383         if (!is_trans_port_sync_mode(crtc_state))
2384                 intel_dp_stop_link_train(intel_dp, crtc_state);
2385
2386         /* 5.k Configure and enable FEC if needed */
2387         intel_ddi_enable_fec(encoder, crtc_state);
2388         intel_dsc_enable(encoder, crtc_state);
2389 }
2390
2391 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2392                                   struct intel_encoder *encoder,
2393                                   const struct intel_crtc_state *crtc_state,
2394                                   const struct drm_connector_state *conn_state)
2395 {
2396         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2398         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2399         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2400
2401         intel_dp_set_link_params(intel_dp,
2402                                  crtc_state->port_clock,
2403                                  crtc_state->lane_count);
2404
2405         /*
2406          * We only configure what the register value will be here.  Actual
2407          * enabling happens during link training farther down.
2408          */
2409         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2410
2411         /*
2412          * 1. Enable Power Wells
2413          *
2414          * This was handled at the beginning of intel_atomic_commit_tail(),
2415          * before we called down into this function.
2416          */
2417
2418         /* 2. Enable Panel Power if PPS is required */
2419         intel_pps_on(intel_dp);
2420
2421         /*
2422          * 3. For non-TBT Type-C ports, set FIA lane count
2423          * (DFLEXDPSP.DPX4TXLATC)
2424          *
2425          * This was done before tgl_ddi_pre_enable_dp by
2426          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2427          */
2428
2429         /*
2430          * 4. Enable the port PLL.
2431          *
2432          * The PLL enabling itself was already done before this function by
2433          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2434          * configure the PLL to port mapping here.
2435          */
2436         intel_ddi_enable_clock(encoder, crtc_state);
2437
2438         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2439         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2440                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2441                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2442                                                                    dig_port->ddi_io_power_domain);
2443         }
2444
2445         /* 6. Program DP_MODE */
2446         icl_program_mg_dp_mode(dig_port, crtc_state);
2447
2448         /*
2449          * 7. The rest of the below are substeps under the bspec's "Enable and
2450          * Train Display Port" step.  Note that steps that are specific to
2451          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2452          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2453          * us when active_mst_links==0, so any steps designated for "single
2454          * stream or multi-stream master transcoder" can just be performed
2455          * unconditionally here.
2456          */
2457
2458         /*
2459          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2460          * Transcoder.
2461          */
2462         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2463
2464         /*
2465          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2466          * Transport Select
2467          */
2468         intel_ddi_config_transcoder_func(encoder, crtc_state);
2469
2470         /*
2471          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2472          * selected
2473          *
2474          * This will be handled by the intel_dp_start_link_train() farther
2475          * down this function.
2476          */
2477
2478         /* 7.e Configure voltage swing and related IO settings */
2479         encoder->set_signal_levels(encoder, crtc_state);
2480
2481         /*
2482          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2483          * the used lanes of the DDI.
2484          */
2485         intel_ddi_power_up_lanes(encoder, crtc_state);
2486
2487         /*
2488          * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2489          */
2490         intel_ddi_mso_configure(crtc_state);
2491
2492         if (!is_mst)
2493                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2494
2495         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2496         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2497         /*
2498          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2499          * in the FEC_CONFIGURATION register to 1 before initiating link
2500          * training
2501          */
2502         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2503
2504         intel_dp_check_frl_training(intel_dp);
2505         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2506
2507         /*
2508          * 7.i Follow DisplayPort specification training sequence (see notes for
2509          *     failure handling)
2510          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2511          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2512          *     (timeout after 800 us)
2513          */
2514         intel_dp_start_link_train(intel_dp, crtc_state);
2515
2516         /* 7.k Set DP_TP_CTL link training to Normal */
2517         if (!is_trans_port_sync_mode(crtc_state))
2518                 intel_dp_stop_link_train(intel_dp, crtc_state);
2519
2520         /* 7.l Configure and enable FEC if needed */
2521         intel_ddi_enable_fec(encoder, crtc_state);
2522         if (!crtc_state->bigjoiner)
2523                 intel_dsc_enable(encoder, crtc_state);
2524 }
2525
2526 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2527                                   struct intel_encoder *encoder,
2528                                   const struct intel_crtc_state *crtc_state,
2529                                   const struct drm_connector_state *conn_state)
2530 {
2531         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2532         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2533         enum port port = encoder->port;
2534         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2535         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2536
2537         if (DISPLAY_VER(dev_priv) < 11)
2538                 drm_WARN_ON(&dev_priv->drm,
2539                             is_mst && (port == PORT_A || port == PORT_E));
2540         else
2541                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2542
2543         intel_dp_set_link_params(intel_dp,
2544                                  crtc_state->port_clock,
2545                                  crtc_state->lane_count);
2546
2547         /*
2548          * We only configure what the register value will be here.  Actual
2549          * enabling happens during link training farther down.
2550          */
2551         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2552
2553         intel_pps_on(intel_dp);
2554
2555         intel_ddi_enable_clock(encoder, crtc_state);
2556
2557         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2558                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2559                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2560                                                                    dig_port->ddi_io_power_domain);
2561         }
2562
2563         icl_program_mg_dp_mode(dig_port, crtc_state);
2564
2565         if (has_buf_trans_select(dev_priv))
2566                 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2567
2568         encoder->set_signal_levels(encoder, crtc_state);
2569
2570         intel_ddi_power_up_lanes(encoder, crtc_state);
2571
2572         if (!is_mst)
2573                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2574         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2575         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2576                                               true);
2577         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2578         intel_dp_start_link_train(intel_dp, crtc_state);
2579         if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2580             !is_trans_port_sync_mode(crtc_state))
2581                 intel_dp_stop_link_train(intel_dp, crtc_state);
2582
2583         intel_ddi_enable_fec(encoder, crtc_state);
2584
2585         if (!is_mst)
2586                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2587
2588         if (!crtc_state->bigjoiner)
2589                 intel_dsc_enable(encoder, crtc_state);
2590 }
2591
2592 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2593                                     struct intel_encoder *encoder,
2594                                     const struct intel_crtc_state *crtc_state,
2595                                     const struct drm_connector_state *conn_state)
2596 {
2597         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2598
2599         if (IS_DG2(dev_priv))
2600                 dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2601         else if (DISPLAY_VER(dev_priv) >= 12)
2602                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2603         else
2604                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2605
2606         /* MST will call a setting of MSA after an allocating of Virtual Channel
2607          * from MST encoder pre_enable callback.
2608          */
2609         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2610                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2611
2612                 intel_dp_set_m_n(crtc_state, M1_N1);
2613         }
2614 }
2615
2616 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2617                                       struct intel_encoder *encoder,
2618                                       const struct intel_crtc_state *crtc_state,
2619                                       const struct drm_connector_state *conn_state)
2620 {
2621         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2622         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2623         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2624
2625         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2626         intel_ddi_enable_clock(encoder, crtc_state);
2627
2628         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2629         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2630                                                            dig_port->ddi_io_power_domain);
2631
2632         icl_program_mg_dp_mode(dig_port, crtc_state);
2633
2634         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2635
2636         dig_port->set_infoframes(encoder,
2637                                  crtc_state->has_infoframe,
2638                                  crtc_state, conn_state);
2639 }
2640
2641 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2642                                  struct intel_encoder *encoder,
2643                                  const struct intel_crtc_state *crtc_state,
2644                                  const struct drm_connector_state *conn_state)
2645 {
2646         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2647         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2648         enum pipe pipe = crtc->pipe;
2649
2650         /*
2651          * When called from DP MST code:
2652          * - conn_state will be NULL
2653          * - encoder will be the main encoder (ie. mst->primary)
2654          * - the main connector associated with this port
2655          *   won't be active or linked to a crtc
2656          * - crtc_state will be the state of the first stream to
2657          *   be activated on this port, and it may not be the same
2658          *   stream that will be deactivated last, but each stream
2659          *   should have a state that is identical when it comes to
2660          *   the DP link parameteres
2661          */
2662
2663         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2664
2665         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2666
2667         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2668                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2669                                           conn_state);
2670         } else {
2671                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2672
2673                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2674                                         conn_state);
2675
2676                 /* FIXME precompute everything properly */
2677                 /* FIXME how do we turn infoframes off again? */
2678                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2679                         dig_port->set_infoframes(encoder,
2680                                                  crtc_state->has_infoframe,
2681                                                  crtc_state, conn_state);
2682         }
2683 }
2684
2685 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2686                                   const struct intel_crtc_state *crtc_state)
2687 {
2688         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2689         enum port port = encoder->port;
2690         bool wait = false;
2691         u32 val;
2692
2693         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2694         if (val & DDI_BUF_CTL_ENABLE) {
2695                 val &= ~DDI_BUF_CTL_ENABLE;
2696                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2697                 wait = true;
2698         }
2699
2700         if (intel_crtc_has_dp_encoder(crtc_state)) {
2701                 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2702                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2703                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2704                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2705         }
2706
2707         /* Disable FEC in DP Sink */
2708         intel_ddi_disable_fec_state(encoder, crtc_state);
2709
2710         if (wait)
2711                 intel_wait_ddi_buf_idle(dev_priv, port);
2712 }
2713
2714 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2715                                       struct intel_encoder *encoder,
2716                                       const struct intel_crtc_state *old_crtc_state,
2717                                       const struct drm_connector_state *old_conn_state)
2718 {
2719         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2720         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2721         struct intel_dp *intel_dp = &dig_port->dp;
2722         bool is_mst = intel_crtc_has_type(old_crtc_state,
2723                                           INTEL_OUTPUT_DP_MST);
2724
2725         if (!is_mst)
2726                 intel_dp_set_infoframes(encoder, false,
2727                                         old_crtc_state, old_conn_state);
2728
2729         /*
2730          * Power down sink before disabling the port, otherwise we end
2731          * up getting interrupts from the sink on detecting link loss.
2732          */
2733         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2734
2735         if (DISPLAY_VER(dev_priv) >= 12) {
2736                 if (is_mst) {
2737                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2738                         u32 val;
2739
2740                         val = intel_de_read(dev_priv,
2741                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
2742                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
2743                                  TRANS_DDI_MODE_SELECT_MASK);
2744                         intel_de_write(dev_priv,
2745                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
2746                                        val);
2747                 }
2748         } else {
2749                 if (!is_mst)
2750                         intel_ddi_disable_pipe_clock(old_crtc_state);
2751         }
2752
2753         intel_disable_ddi_buf(encoder, old_crtc_state);
2754
2755         /*
2756          * From TGL spec: "If single stream or multi-stream master transcoder:
2757          * Configure Transcoder Clock select to direct no clock to the
2758          * transcoder"
2759          */
2760         if (DISPLAY_VER(dev_priv) >= 12)
2761                 intel_ddi_disable_pipe_clock(old_crtc_state);
2762
2763         intel_pps_vdd_on(intel_dp);
2764         intel_pps_off(intel_dp);
2765
2766         if (!intel_tc_port_in_tbt_alt_mode(dig_port))
2767                 intel_display_power_put(dev_priv,
2768                                         dig_port->ddi_io_power_domain,
2769                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
2770
2771         intel_ddi_disable_clock(encoder);
2772 }
2773
2774 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2775                                         struct intel_encoder *encoder,
2776                                         const struct intel_crtc_state *old_crtc_state,
2777                                         const struct drm_connector_state *old_conn_state)
2778 {
2779         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2780         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2781         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2782
2783         dig_port->set_infoframes(encoder, false,
2784                                  old_crtc_state, old_conn_state);
2785
2786         intel_ddi_disable_pipe_clock(old_crtc_state);
2787
2788         intel_disable_ddi_buf(encoder, old_crtc_state);
2789
2790         intel_display_power_put(dev_priv,
2791                                 dig_port->ddi_io_power_domain,
2792                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
2793
2794         intel_ddi_disable_clock(encoder);
2795
2796         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2797 }
2798
2799 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2800                                    struct intel_encoder *encoder,
2801                                    const struct intel_crtc_state *old_crtc_state,
2802                                    const struct drm_connector_state *old_conn_state)
2803 {
2804         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2805         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2806         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2807         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2808
2809         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2810                 intel_crtc_vblank_off(old_crtc_state);
2811
2812                 intel_disable_transcoder(old_crtc_state);
2813
2814                 intel_vrr_disable(old_crtc_state);
2815
2816                 intel_ddi_disable_transcoder_func(old_crtc_state);
2817
2818                 intel_dsc_disable(old_crtc_state);
2819
2820                 if (DISPLAY_VER(dev_priv) >= 9)
2821                         skl_scaler_disable(old_crtc_state);
2822                 else
2823                         ilk_pfit_disable(old_crtc_state);
2824         }
2825
2826         if (old_crtc_state->bigjoiner_linked_crtc) {
2827                 struct intel_atomic_state *state =
2828                         to_intel_atomic_state(old_crtc_state->uapi.state);
2829                 struct intel_crtc *slave =
2830                         old_crtc_state->bigjoiner_linked_crtc;
2831                 const struct intel_crtc_state *old_slave_crtc_state =
2832                         intel_atomic_get_old_crtc_state(state, slave);
2833
2834                 intel_crtc_vblank_off(old_slave_crtc_state);
2835
2836                 intel_dsc_disable(old_slave_crtc_state);
2837                 skl_scaler_disable(old_slave_crtc_state);
2838         }
2839
2840         /*
2841          * When called from DP MST code:
2842          * - old_conn_state will be NULL
2843          * - encoder will be the main encoder (ie. mst->primary)
2844          * - the main connector associated with this port
2845          *   won't be active or linked to a crtc
2846          * - old_crtc_state will be the state of the last stream to
2847          *   be deactivated on this port, and it may not be the same
2848          *   stream that was activated last, but each stream
2849          *   should have a state that is identical when it comes to
2850          *   the DP link parameteres
2851          */
2852
2853         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2854                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2855                                             old_conn_state);
2856         else
2857                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2858                                           old_conn_state);
2859
2860         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
2861                 intel_display_power_put(dev_priv,
2862                                         intel_ddi_main_link_aux_domain(dig_port),
2863                                         fetch_and_zero(&dig_port->aux_wakeref));
2864
2865         if (is_tc_port)
2866                 intel_tc_port_put_link(dig_port);
2867 }
2868
2869 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
2870                                 struct intel_encoder *encoder,
2871                                 const struct intel_crtc_state *old_crtc_state,
2872                                 const struct drm_connector_state *old_conn_state)
2873 {
2874         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2875         u32 val;
2876
2877         /*
2878          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2879          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2880          * step 13 is the correct place for it. Step 18 is where it was
2881          * originally before the BUN.
2882          */
2883         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2884         val &= ~FDI_RX_ENABLE;
2885         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2886
2887         intel_disable_ddi_buf(encoder, old_crtc_state);
2888         intel_ddi_disable_clock(encoder);
2889
2890         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
2891         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2892         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2893         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
2894
2895         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2896         val &= ~FDI_PCDCLK;
2897         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2898
2899         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2900         val &= ~FDI_RX_PLL_ENABLE;
2901         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2902 }
2903
2904 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2905                                             struct intel_encoder *encoder,
2906                                             const struct intel_crtc_state *crtc_state)
2907 {
2908         const struct drm_connector_state *conn_state;
2909         struct drm_connector *conn;
2910         int i;
2911
2912         if (!crtc_state->sync_mode_slaves_mask)
2913                 return;
2914
2915         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2916                 struct intel_encoder *slave_encoder =
2917                         to_intel_encoder(conn_state->best_encoder);
2918                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2919                 const struct intel_crtc_state *slave_crtc_state;
2920
2921                 if (!slave_crtc)
2922                         continue;
2923
2924                 slave_crtc_state =
2925                         intel_atomic_get_new_crtc_state(state, slave_crtc);
2926
2927                 if (slave_crtc_state->master_transcoder !=
2928                     crtc_state->cpu_transcoder)
2929                         continue;
2930
2931                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
2932                                          slave_crtc_state);
2933         }
2934
2935         usleep_range(200, 400);
2936
2937         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
2938                                  crtc_state);
2939 }
2940
2941 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
2942                                 struct intel_encoder *encoder,
2943                                 const struct intel_crtc_state *crtc_state,
2944                                 const struct drm_connector_state *conn_state)
2945 {
2946         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2947         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2948         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2949         enum port port = encoder->port;
2950
2951         if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
2952                 intel_dp_stop_link_train(intel_dp, crtc_state);
2953
2954         intel_edp_backlight_on(crtc_state, conn_state);
2955
2956         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
2957                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
2958
2959         intel_drrs_enable(intel_dp, crtc_state);
2960
2961         if (crtc_state->has_audio)
2962                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2963
2964         trans_port_sync_stop_link_train(state, encoder, crtc_state);
2965 }
2966
2967 static i915_reg_t
2968 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
2969                                enum port port)
2970 {
2971         static const enum transcoder trans[] = {
2972                 [PORT_A] = TRANSCODER_EDP,
2973                 [PORT_B] = TRANSCODER_A,
2974                 [PORT_C] = TRANSCODER_B,
2975                 [PORT_D] = TRANSCODER_C,
2976                 [PORT_E] = TRANSCODER_A,
2977         };
2978
2979         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
2980
2981         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
2982                 port = PORT_A;
2983
2984         return CHICKEN_TRANS(trans[port]);
2985 }
2986
2987 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
2988                                   struct intel_encoder *encoder,
2989                                   const struct intel_crtc_state *crtc_state,
2990                                   const struct drm_connector_state *conn_state)
2991 {
2992         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2993         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2994         struct drm_connector *connector = conn_state->connector;
2995         enum port port = encoder->port;
2996
2997         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2998                                                crtc_state->hdmi_high_tmds_clock_ratio,
2999                                                crtc_state->hdmi_scrambling))
3000                 drm_dbg_kms(&dev_priv->drm,
3001                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3002                             connector->base.id, connector->name);
3003
3004         if (has_buf_trans_select(dev_priv))
3005                 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
3006
3007         encoder->set_signal_levels(encoder, crtc_state);
3008
3009         /* Display WA #1143: skl,kbl,cfl */
3010         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3011                 /*
3012                  * For some reason these chicken bits have been
3013                  * stuffed into a transcoder register, event though
3014                  * the bits affect a specific DDI port rather than
3015                  * a specific transcoder.
3016                  */
3017                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3018                 u32 val;
3019
3020                 val = intel_de_read(dev_priv, reg);
3021
3022                 if (port == PORT_E)
3023                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3024                                 DDIE_TRAINING_OVERRIDE_VALUE;
3025                 else
3026                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3027                                 DDI_TRAINING_OVERRIDE_VALUE;
3028
3029                 intel_de_write(dev_priv, reg, val);
3030                 intel_de_posting_read(dev_priv, reg);
3031
3032                 udelay(1);
3033
3034                 if (port == PORT_E)
3035                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3036                                  DDIE_TRAINING_OVERRIDE_VALUE);
3037                 else
3038                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3039                                  DDI_TRAINING_OVERRIDE_VALUE);
3040
3041                 intel_de_write(dev_priv, reg, val);
3042         }
3043
3044         intel_ddi_power_up_lanes(encoder, crtc_state);
3045
3046         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3047          * are ignored so nothing special needs to be done besides
3048          * enabling the port.
3049          *
3050          * On ADL_P the PHY link rate and lane count must be programmed but
3051          * these are both 0 for HDMI.
3052          */
3053         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3054                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3055
3056         if (crtc_state->has_audio)
3057                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3058 }
3059
3060 static void intel_enable_ddi(struct intel_atomic_state *state,
3061                              struct intel_encoder *encoder,
3062                              const struct intel_crtc_state *crtc_state,
3063                              const struct drm_connector_state *conn_state)
3064 {
3065         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3066
3067         if (!crtc_state->bigjoiner_slave)
3068                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3069
3070         intel_vrr_enable(encoder, crtc_state);
3071
3072         intel_enable_transcoder(crtc_state);
3073
3074         intel_crtc_vblank_on(crtc_state);
3075
3076         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3077                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3078         else
3079                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3080
3081         /* Enable hdcp if it's desired */
3082         if (conn_state->content_protection ==
3083             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3084                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3085                                   crtc_state,
3086                                   (u8)conn_state->hdcp_content_type);
3087 }
3088
3089 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3090                                  struct intel_encoder *encoder,
3091                                  const struct intel_crtc_state *old_crtc_state,
3092                                  const struct drm_connector_state *old_conn_state)
3093 {
3094         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3095
3096         intel_dp->link_trained = false;
3097
3098         intel_edp_backlight_off(old_conn_state);
3099         /* Disable the decompression in DP Sink */
3100         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3101                                               false);
3102         /* Disable Ignore_MSA bit in DP Sink */
3103         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3104                                                       false);
3105 }
3106
3107 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3108                                    struct intel_encoder *encoder,
3109                                    const struct intel_crtc_state *old_crtc_state,
3110                                    const struct drm_connector_state *old_conn_state)
3111 {
3112         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3113         struct drm_connector *connector = old_conn_state->connector;
3114
3115         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3116                                                false, false))
3117                 drm_dbg_kms(&i915->drm,
3118                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3119                             connector->base.id, connector->name);
3120 }
3121
3122 static void intel_pre_disable_ddi(struct intel_atomic_state *state,
3123                                   struct intel_encoder *encoder,
3124                                   const struct intel_crtc_state *old_crtc_state,
3125                                   const struct drm_connector_state *old_conn_state)
3126 {
3127         struct intel_dp *intel_dp;
3128
3129         if (old_crtc_state->has_audio)
3130                 intel_audio_codec_disable(encoder, old_crtc_state,
3131                                           old_conn_state);
3132
3133         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3134                 return;
3135
3136         intel_dp = enc_to_intel_dp(encoder);
3137         intel_drrs_disable(intel_dp, old_crtc_state);
3138         intel_psr_disable(intel_dp, old_crtc_state);
3139 }
3140
3141 static void intel_disable_ddi(struct intel_atomic_state *state,
3142                               struct intel_encoder *encoder,
3143                               const struct intel_crtc_state *old_crtc_state,
3144                               const struct drm_connector_state *old_conn_state)
3145 {
3146         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3147
3148         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3149                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3150                                        old_conn_state);
3151         else
3152                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3153                                      old_conn_state);
3154 }
3155
3156 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3157                                      struct intel_encoder *encoder,
3158                                      const struct intel_crtc_state *crtc_state,
3159                                      const struct drm_connector_state *conn_state)
3160 {
3161         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3162
3163         intel_ddi_set_dp_msa(crtc_state, conn_state);
3164
3165         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3166         intel_drrs_update(intel_dp, crtc_state);
3167
3168         intel_backlight_update(state, encoder, crtc_state, conn_state);
3169 }
3170
3171 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3172                            struct intel_encoder *encoder,
3173                            const struct intel_crtc_state *crtc_state,
3174                            const struct drm_connector_state *conn_state)
3175 {
3176
3177         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3178             !intel_encoder_is_mst(encoder))
3179                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3180                                          conn_state);
3181
3182         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3183 }
3184
3185 static void
3186 intel_ddi_update_prepare(struct intel_atomic_state *state,
3187                          struct intel_encoder *encoder,
3188                          struct intel_crtc *crtc)
3189 {
3190         struct intel_crtc_state *crtc_state =
3191                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3192         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3193
3194         drm_WARN_ON(state->base.dev, crtc && crtc->active);
3195
3196         intel_tc_port_get_link(enc_to_dig_port(encoder),
3197                                required_lanes);
3198         if (crtc_state && crtc_state->hw.active)
3199                 intel_update_active_dpll(state, crtc, encoder);
3200 }
3201
3202 static void
3203 intel_ddi_update_complete(struct intel_atomic_state *state,
3204                           struct intel_encoder *encoder,
3205                           struct intel_crtc *crtc)
3206 {
3207         intel_tc_port_put_link(enc_to_dig_port(encoder));
3208 }
3209
3210 static void
3211 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3212                          struct intel_encoder *encoder,
3213                          const struct intel_crtc_state *crtc_state,
3214                          const struct drm_connector_state *conn_state)
3215 {
3216         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3217         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3218         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3219         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3220
3221         if (is_tc_port)
3222                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3223
3224         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
3225                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
3226                 dig_port->aux_wakeref =
3227                         intel_display_power_get(dev_priv,
3228                                                 intel_ddi_main_link_aux_domain(dig_port));
3229         }
3230
3231         if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3232                 /*
3233                  * Program the lane count for static/dynamic connections on
3234                  * Type-C ports.  Skip this step for TBT.
3235                  */
3236                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3237         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3238                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3239                                                 crtc_state->lane_lat_optim_mask);
3240 }
3241
3242 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3243                                            const struct intel_crtc_state *crtc_state)
3244 {
3245         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3246         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3247         enum port port = encoder->port;
3248         u32 dp_tp_ctl, ddi_buf_ctl;
3249         bool wait = false;
3250
3251         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3252
3253         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3254                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3255                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3256                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3257                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3258                         wait = true;
3259                 }
3260
3261                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3262                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3263                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3264                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3265
3266                 if (wait)
3267                         intel_wait_ddi_buf_idle(dev_priv, port);
3268         }
3269
3270         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3271         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3272                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3273         } else {
3274                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3275                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3276                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3277         }
3278         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3279         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3280
3281         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3282         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3283         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3284
3285         intel_wait_ddi_buf_active(dev_priv, port);
3286 }
3287
3288 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3289                                      const struct intel_crtc_state *crtc_state,
3290                                      u8 dp_train_pat)
3291 {
3292         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3293         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3294         u32 temp;
3295
3296         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3297
3298         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3299         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3300         case DP_TRAINING_PATTERN_DISABLE:
3301                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3302                 break;
3303         case DP_TRAINING_PATTERN_1:
3304                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3305                 break;
3306         case DP_TRAINING_PATTERN_2:
3307                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3308                 break;
3309         case DP_TRAINING_PATTERN_3:
3310                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3311                 break;
3312         case DP_TRAINING_PATTERN_4:
3313                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3314                 break;
3315         }
3316
3317         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3318 }
3319
3320 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3321                                           const struct intel_crtc_state *crtc_state)
3322 {
3323         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3324         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3325         enum port port = encoder->port;
3326         u32 val;
3327
3328         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3329         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3330         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3331         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3332
3333         /*
3334          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3335          * reason we need to set idle transmission mode is to work around a HW
3336          * issue where we enable the pipe while not in idle link-training mode.
3337          * In this case there is requirement to wait for a minimum number of
3338          * idle patterns to be sent.
3339          */
3340         if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3341                 return;
3342
3343         if (intel_de_wait_for_set(dev_priv,
3344                                   dp_tp_status_reg(encoder, crtc_state),
3345                                   DP_TP_STATUS_IDLE_DONE, 1))
3346                 drm_err(&dev_priv->drm,
3347                         "Timed out waiting for DP idle patterns\n");
3348 }
3349
3350 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3351                                        enum transcoder cpu_transcoder)
3352 {
3353         if (cpu_transcoder == TRANSCODER_EDP)
3354                 return false;
3355
3356         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3357                 return false;
3358
3359         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3360                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3361 }
3362
3363 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3364                                          struct intel_crtc_state *crtc_state)
3365 {
3366         if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3367                 crtc_state->min_voltage_level = 2;
3368         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3369                 crtc_state->min_voltage_level = 3;
3370         else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3371                 crtc_state->min_voltage_level = 1;
3372 }
3373
3374 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3375                                                      enum transcoder cpu_transcoder)
3376 {
3377         u32 master_select;
3378
3379         if (DISPLAY_VER(dev_priv) >= 11) {
3380                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3381
3382                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3383                         return INVALID_TRANSCODER;
3384
3385                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3386         } else {
3387                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3388
3389                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3390                         return INVALID_TRANSCODER;
3391
3392                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3393         }
3394
3395         if (master_select == 0)
3396                 return TRANSCODER_EDP;
3397         else
3398                 return master_select - 1;
3399 }
3400
3401 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3402 {
3403         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3404         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3405                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3406         enum transcoder cpu_transcoder;
3407
3408         crtc_state->master_transcoder =
3409                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3410
3411         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3412                 enum intel_display_power_domain power_domain;
3413                 intel_wakeref_t trans_wakeref;
3414
3415                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3416                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3417                                                                    power_domain);
3418
3419                 if (!trans_wakeref)
3420                         continue;
3421
3422                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3423                     crtc_state->cpu_transcoder)
3424                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3425
3426                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3427         }
3428
3429         drm_WARN_ON(&dev_priv->drm,
3430                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3431                     crtc_state->sync_mode_slaves_mask);
3432 }
3433
3434 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3435                                     struct intel_crtc_state *pipe_config)
3436 {
3437         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3438         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3439         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3440         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3441         u32 temp, flags = 0;
3442
3443         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3444         if (temp & TRANS_DDI_PHSYNC)
3445                 flags |= DRM_MODE_FLAG_PHSYNC;
3446         else
3447                 flags |= DRM_MODE_FLAG_NHSYNC;
3448         if (temp & TRANS_DDI_PVSYNC)
3449                 flags |= DRM_MODE_FLAG_PVSYNC;
3450         else
3451                 flags |= DRM_MODE_FLAG_NVSYNC;
3452
3453         pipe_config->hw.adjusted_mode.flags |= flags;
3454
3455         switch (temp & TRANS_DDI_BPC_MASK) {
3456         case TRANS_DDI_BPC_6:
3457                 pipe_config->pipe_bpp = 18;
3458                 break;
3459         case TRANS_DDI_BPC_8:
3460                 pipe_config->pipe_bpp = 24;
3461                 break;
3462         case TRANS_DDI_BPC_10:
3463                 pipe_config->pipe_bpp = 30;
3464                 break;
3465         case TRANS_DDI_BPC_12:
3466                 pipe_config->pipe_bpp = 36;
3467                 break;
3468         default:
3469                 break;
3470         }
3471
3472         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3473         case TRANS_DDI_MODE_SELECT_HDMI:
3474                 pipe_config->has_hdmi_sink = true;
3475
3476                 pipe_config->infoframes.enable |=
3477                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3478
3479                 if (pipe_config->infoframes.enable)
3480                         pipe_config->has_infoframe = true;
3481
3482                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3483                         pipe_config->hdmi_scrambling = true;
3484                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3485                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3486                 fallthrough;
3487         case TRANS_DDI_MODE_SELECT_DVI:
3488                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3489                 pipe_config->lane_count = 4;
3490                 break;
3491         case TRANS_DDI_MODE_SELECT_DP_SST:
3492                 if (encoder->type == INTEL_OUTPUT_EDP)
3493                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3494                 else
3495                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3496                 pipe_config->lane_count =
3497                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3498                 intel_dp_get_m_n(crtc, pipe_config);
3499
3500                 if (DISPLAY_VER(dev_priv) >= 11) {
3501                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3502
3503                         pipe_config->fec_enable =
3504                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3505
3506                         drm_dbg_kms(&dev_priv->drm,
3507                                     "[ENCODER:%d:%s] Fec status: %u\n",
3508                                     encoder->base.base.id, encoder->base.name,
3509                                     pipe_config->fec_enable);
3510                 }
3511
3512                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3513                         pipe_config->infoframes.enable |=
3514                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3515                 else
3516                         pipe_config->infoframes.enable |=
3517                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3518                 break;
3519         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3520                 if (!HAS_DP20(dev_priv)) {
3521                         /* FDI */
3522                         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3523                         break;
3524                 }
3525                 fallthrough; /* 128b/132b */
3526         case TRANS_DDI_MODE_SELECT_DP_MST:
3527                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3528                 pipe_config->lane_count =
3529                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3530
3531                 if (DISPLAY_VER(dev_priv) >= 12)
3532                         pipe_config->mst_master_transcoder =
3533                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3534
3535                 intel_dp_get_m_n(crtc, pipe_config);
3536
3537                 pipe_config->infoframes.enable |=
3538                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3539                 break;
3540         default:
3541                 break;
3542         }
3543 }
3544
3545 static void intel_ddi_get_config(struct intel_encoder *encoder,
3546                                  struct intel_crtc_state *pipe_config)
3547 {
3548         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3549         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3550
3551         /* XXX: DSI transcoder paranoia */
3552         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3553                 return;
3554
3555         if (pipe_config->bigjoiner_slave) {
3556                 /* read out pipe settings from master */
3557                 enum transcoder save = pipe_config->cpu_transcoder;
3558
3559                 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
3560                 WARN_ON(pipe_config->output_types);
3561                 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
3562                 intel_ddi_read_func_ctl(encoder, pipe_config);
3563                 pipe_config->cpu_transcoder = save;
3564         } else {
3565                 intel_ddi_read_func_ctl(encoder, pipe_config);
3566         }
3567
3568         intel_ddi_mso_get_config(encoder, pipe_config);
3569
3570         pipe_config->has_audio =
3571                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3572
3573         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3574             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3575                 /*
3576                  * This is a big fat ugly hack.
3577                  *
3578                  * Some machines in UEFI boot mode provide us a VBT that has 18
3579                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3580                  * unknown we fail to light up. Yet the same BIOS boots up with
3581                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3582                  * max, not what it tells us to use.
3583                  *
3584                  * Note: This will still be broken if the eDP panel is not lit
3585                  * up by the BIOS, and thus we can't get the mode at module
3586                  * load.
3587                  */
3588                 drm_dbg_kms(&dev_priv->drm,
3589                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3590                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3591                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3592         }
3593
3594         if (!pipe_config->bigjoiner_slave)
3595                 ddi_dotclock_get(pipe_config);
3596
3597         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3598                 pipe_config->lane_lat_optim_mask =
3599                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3600
3601         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3602
3603         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3604
3605         intel_read_infoframe(encoder, pipe_config,
3606                              HDMI_INFOFRAME_TYPE_AVI,
3607                              &pipe_config->infoframes.avi);
3608         intel_read_infoframe(encoder, pipe_config,
3609                              HDMI_INFOFRAME_TYPE_SPD,
3610                              &pipe_config->infoframes.spd);
3611         intel_read_infoframe(encoder, pipe_config,
3612                              HDMI_INFOFRAME_TYPE_VENDOR,
3613                              &pipe_config->infoframes.hdmi);
3614         intel_read_infoframe(encoder, pipe_config,
3615                              HDMI_INFOFRAME_TYPE_DRM,
3616                              &pipe_config->infoframes.drm);
3617
3618         if (DISPLAY_VER(dev_priv) >= 8)
3619                 bdw_get_trans_port_sync_config(pipe_config);
3620
3621         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3622         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3623
3624         intel_psr_get_config(encoder, pipe_config);
3625 }
3626
3627 void intel_ddi_get_clock(struct intel_encoder *encoder,
3628                          struct intel_crtc_state *crtc_state,
3629                          struct intel_shared_dpll *pll)
3630 {
3631         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3632         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3633         struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3634         bool pll_active;
3635
3636         if (drm_WARN_ON(&i915->drm, !pll))
3637                 return;
3638
3639         port_dpll->pll = pll;
3640         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3641         drm_WARN_ON(&i915->drm, !pll_active);
3642
3643         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3644
3645         crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3646                                                      &crtc_state->dpll_hw_state);
3647 }
3648
3649 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3650                                 struct intel_crtc_state *crtc_state)
3651 {
3652         intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3653         crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3654
3655         intel_ddi_get_config(encoder, crtc_state);
3656 }
3657
3658 static void adls_ddi_get_config(struct intel_encoder *encoder,
3659                                 struct intel_crtc_state *crtc_state)
3660 {
3661         intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3662         intel_ddi_get_config(encoder, crtc_state);
3663 }
3664
3665 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3666                                struct intel_crtc_state *crtc_state)
3667 {
3668         intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3669         intel_ddi_get_config(encoder, crtc_state);
3670 }
3671
3672 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3673                                struct intel_crtc_state *crtc_state)
3674 {
3675         intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3676         intel_ddi_get_config(encoder, crtc_state);
3677 }
3678
3679 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3680                                      struct intel_crtc_state *crtc_state)
3681 {
3682         intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3683         intel_ddi_get_config(encoder, crtc_state);
3684 }
3685
3686 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3687                                  struct intel_crtc_state *crtc_state,
3688                                  struct intel_shared_dpll *pll)
3689 {
3690         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3691         enum icl_port_dpll_id port_dpll_id;
3692         struct icl_port_dpll *port_dpll;
3693         bool pll_active;
3694
3695         if (drm_WARN_ON(&i915->drm, !pll))
3696                 return;
3697
3698         if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
3699                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3700         else
3701                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3702
3703         port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3704
3705         port_dpll->pll = pll;
3706         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3707         drm_WARN_ON(&i915->drm, !pll_active);
3708
3709         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3710
3711         if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
3712                 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3713         else
3714                 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3715                                                              &crtc_state->dpll_hw_state);
3716 }
3717
3718 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3719                                   struct intel_crtc_state *crtc_state)
3720 {
3721         icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3722         intel_ddi_get_config(encoder, crtc_state);
3723 }
3724
3725 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3726                                struct intel_crtc_state *crtc_state)
3727 {
3728         intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3729         intel_ddi_get_config(encoder, crtc_state);
3730 }
3731
3732 static void skl_ddi_get_config(struct intel_encoder *encoder,
3733                                struct intel_crtc_state *crtc_state)
3734 {
3735         intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3736         intel_ddi_get_config(encoder, crtc_state);
3737 }
3738
3739 void hsw_ddi_get_config(struct intel_encoder *encoder,
3740                         struct intel_crtc_state *crtc_state)
3741 {
3742         intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3743         intel_ddi_get_config(encoder, crtc_state);
3744 }
3745
3746 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3747                                  const struct intel_crtc_state *crtc_state)
3748 {
3749         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3750         enum phy phy = intel_port_to_phy(i915, encoder->port);
3751
3752         if (intel_phy_is_tc(i915, phy))
3753                 intel_tc_port_sanitize(enc_to_dig_port(encoder));
3754
3755         if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
3756                 intel_dp_sync_state(encoder, crtc_state);
3757 }
3758
3759 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3760                                             struct intel_crtc_state *crtc_state)
3761 {
3762         if (intel_crtc_has_dp_encoder(crtc_state))
3763                 return intel_dp_initial_fastset_check(encoder, crtc_state);
3764
3765         return true;
3766 }
3767
3768 static enum intel_output_type
3769 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3770                               struct intel_crtc_state *crtc_state,
3771                               struct drm_connector_state *conn_state)
3772 {
3773         switch (conn_state->connector->connector_type) {
3774         case DRM_MODE_CONNECTOR_HDMIA:
3775                 return INTEL_OUTPUT_HDMI;
3776         case DRM_MODE_CONNECTOR_eDP:
3777                 return INTEL_OUTPUT_EDP;
3778         case DRM_MODE_CONNECTOR_DisplayPort:
3779                 return INTEL_OUTPUT_DP;
3780         default:
3781                 MISSING_CASE(conn_state->connector->connector_type);
3782                 return INTEL_OUTPUT_UNUSED;
3783         }
3784 }
3785
3786 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3787                                     struct intel_crtc_state *pipe_config,
3788                                     struct drm_connector_state *conn_state)
3789 {
3790         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3791         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3792         enum port port = encoder->port;
3793         int ret;
3794
3795         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3796                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3797
3798         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3799                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3800         } else {
3801                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3802         }
3803
3804         if (ret)
3805                 return ret;
3806
3807         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3808             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3809                 pipe_config->pch_pfit.force_thru =
3810                         pipe_config->pch_pfit.enabled ||
3811                         pipe_config->crc_enabled;
3812
3813         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3814                 pipe_config->lane_lat_optim_mask =
3815                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3816
3817         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3818
3819         return 0;
3820 }
3821
3822 static bool mode_equal(const struct drm_display_mode *mode1,
3823                        const struct drm_display_mode *mode2)
3824 {
3825         return drm_mode_match(mode1, mode2,
3826                               DRM_MODE_MATCH_TIMINGS |
3827                               DRM_MODE_MATCH_FLAGS |
3828                               DRM_MODE_MATCH_3D_FLAGS) &&
3829                 mode1->clock == mode2->clock; /* we want an exact match */
3830 }
3831
3832 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3833                       const struct intel_link_m_n *m_n_2)
3834 {
3835         return m_n_1->tu == m_n_2->tu &&
3836                 m_n_1->gmch_m == m_n_2->gmch_m &&
3837                 m_n_1->gmch_n == m_n_2->gmch_n &&
3838                 m_n_1->link_m == m_n_2->link_m &&
3839                 m_n_1->link_n == m_n_2->link_n;
3840 }
3841
3842 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3843                                        const struct intel_crtc_state *crtc_state2)
3844 {
3845         return crtc_state1->hw.active && crtc_state2->hw.active &&
3846                 crtc_state1->output_types == crtc_state2->output_types &&
3847                 crtc_state1->output_format == crtc_state2->output_format &&
3848                 crtc_state1->lane_count == crtc_state2->lane_count &&
3849                 crtc_state1->port_clock == crtc_state2->port_clock &&
3850                 mode_equal(&crtc_state1->hw.adjusted_mode,
3851                            &crtc_state2->hw.adjusted_mode) &&
3852                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3853 }
3854
3855 static u8
3856 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3857                                 int tile_group_id)
3858 {
3859         struct drm_connector *connector;
3860         const struct drm_connector_state *conn_state;
3861         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3862         struct intel_atomic_state *state =
3863                 to_intel_atomic_state(ref_crtc_state->uapi.state);
3864         u8 transcoders = 0;
3865         int i;
3866
3867         /*
3868          * We don't enable port sync on BDW due to missing w/as and
3869          * due to not having adjusted the modeset sequence appropriately.
3870          */
3871         if (DISPLAY_VER(dev_priv) < 9)
3872                 return 0;
3873
3874         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3875                 return 0;
3876
3877         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3878                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3879                 const struct intel_crtc_state *crtc_state;
3880
3881                 if (!crtc)
3882                         continue;
3883
3884                 if (!connector->has_tile ||
3885                     connector->tile_group->id !=
3886                     tile_group_id)
3887                         continue;
3888                 crtc_state = intel_atomic_get_new_crtc_state(state,
3889                                                              crtc);
3890                 if (!crtcs_port_sync_compatible(ref_crtc_state,
3891                                                 crtc_state))
3892                         continue;
3893                 transcoders |= BIT(crtc_state->cpu_transcoder);
3894         }
3895
3896         return transcoders;
3897 }
3898
3899 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3900                                          struct intel_crtc_state *crtc_state,
3901                                          struct drm_connector_state *conn_state)
3902 {
3903         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3904         struct drm_connector *connector = conn_state->connector;
3905         u8 port_sync_transcoders = 0;
3906
3907         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3908                     encoder->base.base.id, encoder->base.name,
3909                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3910
3911         if (connector->has_tile)
3912                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3913                                                                         connector->tile_group->id);
3914
3915         /*
3916          * EDP Transcoders cannot be ensalved
3917          * make them a master always when present
3918          */
3919         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3920                 crtc_state->master_transcoder = TRANSCODER_EDP;
3921         else
3922                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3923
3924         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
3925                 crtc_state->master_transcoder = INVALID_TRANSCODER;
3926                 crtc_state->sync_mode_slaves_mask =
3927                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
3928         }
3929
3930         return 0;
3931 }
3932
3933 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3934 {
3935         struct drm_i915_private *i915 = to_i915(encoder->dev);
3936         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3937         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
3938
3939         intel_dp_encoder_flush_work(encoder);
3940         if (intel_phy_is_tc(i915, phy))
3941                 intel_tc_port_flush_work(dig_port);
3942         intel_display_power_flush_work(i915);
3943
3944         drm_encoder_cleanup(encoder);
3945         kfree(dig_port->hdcp_port_data.streams);
3946         kfree(dig_port);
3947 }
3948
3949 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
3950 {
3951         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
3952
3953         intel_dp->reset_link_params = true;
3954
3955         intel_pps_encoder_reset(intel_dp);
3956 }
3957
3958 static const struct drm_encoder_funcs intel_ddi_funcs = {
3959         .reset = intel_ddi_encoder_reset,
3960         .destroy = intel_ddi_encoder_destroy,
3961 };
3962
3963 static struct intel_connector *
3964 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
3965 {
3966         struct intel_connector *connector;
3967         enum port port = dig_port->base.port;
3968
3969         connector = intel_connector_alloc();
3970         if (!connector)
3971                 return NULL;
3972
3973         dig_port->dp.output_reg = DDI_BUF_CTL(port);
3974         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
3975         dig_port->dp.set_link_train = intel_ddi_set_link_train;
3976         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
3977
3978         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
3979         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
3980
3981         if (!intel_dp_init_connector(dig_port, connector)) {
3982                 kfree(connector);
3983                 return NULL;
3984         }
3985
3986         return connector;
3987 }
3988
3989 static int modeset_pipe(struct drm_crtc *crtc,
3990                         struct drm_modeset_acquire_ctx *ctx)
3991 {
3992         struct drm_atomic_state *state;
3993         struct drm_crtc_state *crtc_state;
3994         int ret;
3995
3996         state = drm_atomic_state_alloc(crtc->dev);
3997         if (!state)
3998                 return -ENOMEM;
3999
4000         state->acquire_ctx = ctx;
4001
4002         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4003         if (IS_ERR(crtc_state)) {
4004                 ret = PTR_ERR(crtc_state);
4005                 goto out;
4006         }
4007
4008         crtc_state->connectors_changed = true;
4009
4010         ret = drm_atomic_commit(state);
4011 out:
4012         drm_atomic_state_put(state);
4013
4014         return ret;
4015 }
4016
4017 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4018                                  struct drm_modeset_acquire_ctx *ctx)
4019 {
4020         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4021         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4022         struct intel_connector *connector = hdmi->attached_connector;
4023         struct i2c_adapter *adapter =
4024                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4025         struct drm_connector_state *conn_state;
4026         struct intel_crtc_state *crtc_state;
4027         struct intel_crtc *crtc;
4028         u8 config;
4029         int ret;
4030
4031         if (!connector || connector->base.status != connector_status_connected)
4032                 return 0;
4033
4034         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4035                                ctx);
4036         if (ret)
4037                 return ret;
4038
4039         conn_state = connector->base.state;
4040
4041         crtc = to_intel_crtc(conn_state->crtc);
4042         if (!crtc)
4043                 return 0;
4044
4045         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4046         if (ret)
4047                 return ret;
4048
4049         crtc_state = to_intel_crtc_state(crtc->base.state);
4050
4051         drm_WARN_ON(&dev_priv->drm,
4052                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4053
4054         if (!crtc_state->hw.active)
4055                 return 0;
4056
4057         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4058             !crtc_state->hdmi_scrambling)
4059                 return 0;
4060
4061         if (conn_state->commit &&
4062             !try_wait_for_completion(&conn_state->commit->hw_done))
4063                 return 0;
4064
4065         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4066         if (ret < 0) {
4067                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4068                         ret);
4069                 return 0;
4070         }
4071
4072         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4073             crtc_state->hdmi_high_tmds_clock_ratio &&
4074             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4075             crtc_state->hdmi_scrambling)
4076                 return 0;
4077
4078         /*
4079          * HDMI 2.0 says that one should not send scrambled data
4080          * prior to configuring the sink scrambling, and that
4081          * TMDS clock/data transmission should be suspended when
4082          * changing the TMDS clock rate in the sink. So let's
4083          * just do a full modeset here, even though some sinks
4084          * would be perfectly happy if were to just reconfigure
4085          * the SCDC settings on the fly.
4086          */
4087         return modeset_pipe(&crtc->base, ctx);
4088 }
4089
4090 static enum intel_hotplug_state
4091 intel_ddi_hotplug(struct intel_encoder *encoder,
4092                   struct intel_connector *connector)
4093 {
4094         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4095         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4096         struct intel_dp *intel_dp = &dig_port->dp;
4097         enum phy phy = intel_port_to_phy(i915, encoder->port);
4098         bool is_tc = intel_phy_is_tc(i915, phy);
4099         struct drm_modeset_acquire_ctx ctx;
4100         enum intel_hotplug_state state;
4101         int ret;
4102
4103         if (intel_dp->compliance.test_active &&
4104             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4105                 intel_dp_phy_test(encoder);
4106                 /* just do the PHY test and nothing else */
4107                 return INTEL_HOTPLUG_UNCHANGED;
4108         }
4109
4110         state = intel_encoder_hotplug(encoder, connector);
4111
4112         drm_modeset_acquire_init(&ctx, 0);
4113
4114         for (;;) {
4115                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4116                         ret = intel_hdmi_reset_link(encoder, &ctx);
4117                 else
4118                         ret = intel_dp_retrain_link(encoder, &ctx);
4119
4120                 if (ret == -EDEADLK) {
4121                         drm_modeset_backoff(&ctx);
4122                         continue;
4123                 }
4124
4125                 break;
4126         }
4127
4128         drm_modeset_drop_locks(&ctx);
4129         drm_modeset_acquire_fini(&ctx);
4130         drm_WARN(encoder->base.dev, ret,
4131                  "Acquiring modeset locks failed with %i\n", ret);
4132
4133         /*
4134          * Unpowered type-c dongles can take some time to boot and be
4135          * responsible, so here giving some time to those dongles to power up
4136          * and then retrying the probe.
4137          *
4138          * On many platforms the HDMI live state signal is known to be
4139          * unreliable, so we can't use it to detect if a sink is connected or
4140          * not. Instead we detect if it's connected based on whether we can
4141          * read the EDID or not. That in turn has a problem during disconnect,
4142          * since the HPD interrupt may be raised before the DDC lines get
4143          * disconnected (due to how the required length of DDC vs. HPD
4144          * connector pins are specified) and so we'll still be able to get a
4145          * valid EDID. To solve this schedule another detection cycle if this
4146          * time around we didn't detect any change in the sink's connection
4147          * status.
4148          *
4149          * Type-c connectors which get their HPD signal deasserted then
4150          * reasserted, without unplugging/replugging the sink from the
4151          * connector, introduce a delay until the AUX channel communication
4152          * becomes functional. Retry the detection for 5 seconds on type-c
4153          * connectors to account for this delay.
4154          */
4155         if (state == INTEL_HOTPLUG_UNCHANGED &&
4156             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4157             !dig_port->dp.is_mst)
4158                 state = INTEL_HOTPLUG_RETRY;
4159
4160         return state;
4161 }
4162
4163 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4164 {
4165         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4166         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4167
4168         return intel_de_read(dev_priv, SDEISR) & bit;
4169 }
4170
4171 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4172 {
4173         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4174         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4175
4176         return intel_de_read(dev_priv, DEISR) & bit;
4177 }
4178
4179 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4180 {
4181         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4182         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4183
4184         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4185 }
4186
4187 static struct intel_connector *
4188 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4189 {
4190         struct intel_connector *connector;
4191         enum port port = dig_port->base.port;
4192
4193         connector = intel_connector_alloc();
4194         if (!connector)
4195                 return NULL;
4196
4197         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4198         intel_hdmi_init_connector(dig_port, connector);
4199
4200         return connector;
4201 }
4202
4203 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4204 {
4205         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4206
4207         if (dig_port->base.port != PORT_A)
4208                 return false;
4209
4210         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4211                 return false;
4212
4213         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4214          *                     supported configuration
4215          */
4216         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4217                 return true;
4218
4219         return false;
4220 }
4221
4222 static int
4223 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4224 {
4225         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4226         enum port port = dig_port->base.port;
4227         int max_lanes = 4;
4228
4229         if (DISPLAY_VER(dev_priv) >= 11)
4230                 return max_lanes;
4231
4232         if (port == PORT_A || port == PORT_E) {
4233                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4234                         max_lanes = port == PORT_A ? 4 : 0;
4235                 else
4236                         /* Both A and E share 2 lanes */
4237                         max_lanes = 2;
4238         }
4239
4240         /*
4241          * Some BIOS might fail to set this bit on port A if eDP
4242          * wasn't lit up at boot.  Force this bit set when needed
4243          * so we use the proper lane count for our calculations.
4244          */
4245         if (intel_ddi_a_force_4_lanes(dig_port)) {
4246                 drm_dbg_kms(&dev_priv->drm,
4247                             "Forcing DDI_A_4_LANES for port A\n");
4248                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4249                 max_lanes = 4;
4250         }
4251
4252         return max_lanes;
4253 }
4254
4255 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4256 {
4257         return i915->hti_state & HDPORT_ENABLED &&
4258                i915->hti_state & HDPORT_DDI_USED(phy);
4259 }
4260
4261 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4262                                   enum port port)
4263 {
4264         if (port >= PORT_D_XELPD)
4265                 return HPD_PORT_D + port - PORT_D_XELPD;
4266         else if (port >= PORT_TC1)
4267                 return HPD_PORT_TC1 + port - PORT_TC1;
4268         else
4269                 return HPD_PORT_A + port - PORT_A;
4270 }
4271
4272 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4273                                 enum port port)
4274 {
4275         if (port >= PORT_TC1)
4276                 return HPD_PORT_C + port - PORT_TC1;
4277         else
4278                 return HPD_PORT_A + port - PORT_A;
4279 }
4280
4281 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4282                                 enum port port)
4283 {
4284         if (port >= PORT_TC1)
4285                 return HPD_PORT_TC1 + port - PORT_TC1;
4286         else
4287                 return HPD_PORT_A + port - PORT_A;
4288 }
4289
4290 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4291                                 enum port port)
4292 {
4293         if (HAS_PCH_TGP(dev_priv))
4294                 return tgl_hpd_pin(dev_priv, port);
4295
4296         if (port >= PORT_TC1)
4297                 return HPD_PORT_C + port - PORT_TC1;
4298         else
4299                 return HPD_PORT_A + port - PORT_A;
4300 }
4301
4302 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4303                                 enum port port)
4304 {
4305         if (port >= PORT_C)
4306                 return HPD_PORT_TC1 + port - PORT_C;
4307         else
4308                 return HPD_PORT_A + port - PORT_A;
4309 }
4310
4311 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4312                                 enum port port)
4313 {
4314         if (port == PORT_D)
4315                 return HPD_PORT_A;
4316
4317         if (HAS_PCH_MCC(dev_priv))
4318                 return icl_hpd_pin(dev_priv, port);
4319
4320         return HPD_PORT_A + port - PORT_A;
4321 }
4322
4323 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4324 {
4325         if (HAS_PCH_TGP(dev_priv))
4326                 return icl_hpd_pin(dev_priv, port);
4327
4328         return HPD_PORT_A + port - PORT_A;
4329 }
4330
4331 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4332 {
4333         if (DISPLAY_VER(i915) >= 12)
4334                 return port >= PORT_TC1;
4335         else if (DISPLAY_VER(i915) >= 11)
4336                 return port >= PORT_C;
4337         else
4338                 return false;
4339 }
4340
4341 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4342 {
4343         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4344         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4345         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4346         enum phy phy = intel_port_to_phy(i915, encoder->port);
4347
4348         intel_dp_encoder_suspend(encoder);
4349
4350         if (!intel_phy_is_tc(i915, phy))
4351                 return;
4352
4353         intel_tc_port_flush_work(dig_port);
4354 }
4355
4356 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4357 {
4358         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4359         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4360         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4361         enum phy phy = intel_port_to_phy(i915, encoder->port);
4362
4363         intel_dp_encoder_shutdown(encoder);
4364
4365         if (!intel_phy_is_tc(i915, phy))
4366                 return;
4367
4368         intel_tc_port_flush_work(dig_port);
4369 }
4370
4371 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4372 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4373
4374 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4375 {
4376         struct intel_digital_port *dig_port;
4377         struct intel_encoder *encoder;
4378         const struct intel_bios_encoder_data *devdata;
4379         bool init_hdmi, init_dp;
4380         enum phy phy = intel_port_to_phy(dev_priv, port);
4381
4382         /*
4383          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4384          * have taken over some of the PHYs and made them unavailable to the
4385          * driver.  In that case we should skip initializing the corresponding
4386          * outputs.
4387          */
4388         if (hti_uses_phy(dev_priv, phy)) {
4389                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4390                             port_name(port), phy_name(phy));
4391                 return;
4392         }
4393
4394         devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4395         if (!devdata) {
4396                 drm_dbg_kms(&dev_priv->drm,
4397                             "VBT says port %c is not present\n",
4398                             port_name(port));
4399                 return;
4400         }
4401
4402         init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4403                 intel_bios_encoder_supports_hdmi(devdata);
4404         init_dp = intel_bios_encoder_supports_dp(devdata);
4405
4406         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4407                 /*
4408                  * Lspcon device needs to be driven with DP connector
4409                  * with special detection sequence. So make sure DP
4410                  * is initialized before lspcon.
4411                  */
4412                 init_dp = true;
4413                 init_hdmi = false;
4414                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4415                             port_name(port));
4416         }
4417
4418         if (!init_dp && !init_hdmi) {
4419                 drm_dbg_kms(&dev_priv->drm,
4420                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4421                             port_name(port));
4422                 return;
4423         }
4424
4425         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4426         if (!dig_port)
4427                 return;
4428
4429         encoder = &dig_port->base;
4430         encoder->devdata = devdata;
4431
4432         if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4433                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4434                                  DRM_MODE_ENCODER_TMDS,
4435                                  "DDI %c/PHY %c",
4436                                  port_name(port - PORT_D_XELPD + PORT_D),
4437                                  phy_name(phy));
4438         } else if (DISPLAY_VER(dev_priv) >= 12) {
4439                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4440
4441                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4442                                  DRM_MODE_ENCODER_TMDS,
4443                                  "DDI %s%c/PHY %s%c",
4444                                  port >= PORT_TC1 ? "TC" : "",
4445                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4446                                  tc_port != TC_PORT_NONE ? "TC" : "",
4447                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4448         } else if (DISPLAY_VER(dev_priv) >= 11) {
4449                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4450
4451                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4452                                  DRM_MODE_ENCODER_TMDS,
4453                                  "DDI %c%s/PHY %s%c",
4454                                  port_name(port),
4455                                  port >= PORT_C ? " (TC)" : "",
4456                                  tc_port != TC_PORT_NONE ? "TC" : "",
4457                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4458         } else {
4459                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4460                                  DRM_MODE_ENCODER_TMDS,
4461                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4462         }
4463
4464         mutex_init(&dig_port->hdcp_mutex);
4465         dig_port->num_hdcp_streams = 0;
4466
4467         encoder->hotplug = intel_ddi_hotplug;
4468         encoder->compute_output_type = intel_ddi_compute_output_type;
4469         encoder->compute_config = intel_ddi_compute_config;
4470         encoder->compute_config_late = intel_ddi_compute_config_late;
4471         encoder->enable = intel_enable_ddi;
4472         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4473         encoder->pre_enable = intel_ddi_pre_enable;
4474         encoder->pre_disable = intel_pre_disable_ddi;
4475         encoder->disable = intel_disable_ddi;
4476         encoder->post_disable = intel_ddi_post_disable;
4477         encoder->update_pipe = intel_ddi_update_pipe;
4478         encoder->get_hw_state = intel_ddi_get_hw_state;
4479         encoder->sync_state = intel_ddi_sync_state;
4480         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4481         encoder->suspend = intel_ddi_encoder_suspend;
4482         encoder->shutdown = intel_ddi_encoder_shutdown;
4483         encoder->get_power_domains = intel_ddi_get_power_domains;
4484
4485         encoder->type = INTEL_OUTPUT_DDI;
4486         encoder->power_domain = intel_port_to_power_domain(port);
4487         encoder->port = port;
4488         encoder->cloneable = 0;
4489         encoder->pipe_mask = ~0;
4490
4491         if (IS_DG2(dev_priv)) {
4492                 encoder->enable_clock = intel_mpllb_enable;
4493                 encoder->disable_clock = intel_mpllb_disable;
4494                 encoder->get_config = dg2_ddi_get_config;
4495         } else if (IS_ALDERLAKE_S(dev_priv)) {
4496                 encoder->enable_clock = adls_ddi_enable_clock;
4497                 encoder->disable_clock = adls_ddi_disable_clock;
4498                 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4499                 encoder->get_config = adls_ddi_get_config;
4500         } else if (IS_ROCKETLAKE(dev_priv)) {
4501                 encoder->enable_clock = rkl_ddi_enable_clock;
4502                 encoder->disable_clock = rkl_ddi_disable_clock;
4503                 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4504                 encoder->get_config = rkl_ddi_get_config;
4505         } else if (IS_DG1(dev_priv)) {
4506                 encoder->enable_clock = dg1_ddi_enable_clock;
4507                 encoder->disable_clock = dg1_ddi_disable_clock;
4508                 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4509                 encoder->get_config = dg1_ddi_get_config;
4510         } else if (IS_JSL_EHL(dev_priv)) {
4511                 if (intel_ddi_is_tc(dev_priv, port)) {
4512                         encoder->enable_clock = jsl_ddi_tc_enable_clock;
4513                         encoder->disable_clock = jsl_ddi_tc_disable_clock;
4514                         encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4515                         encoder->get_config = icl_ddi_combo_get_config;
4516                 } else {
4517                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4518                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4519                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4520                         encoder->get_config = icl_ddi_combo_get_config;
4521                 }
4522         } else if (DISPLAY_VER(dev_priv) >= 11) {
4523                 if (intel_ddi_is_tc(dev_priv, port)) {
4524                         encoder->enable_clock = icl_ddi_tc_enable_clock;
4525                         encoder->disable_clock = icl_ddi_tc_disable_clock;
4526                         encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4527                         encoder->get_config = icl_ddi_tc_get_config;
4528                 } else {
4529                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4530                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4531                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4532                         encoder->get_config = icl_ddi_combo_get_config;
4533                 }
4534         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4535                 /* BXT/GLK have fixed PLL->port mapping */
4536                 encoder->get_config = bxt_ddi_get_config;
4537         } else if (DISPLAY_VER(dev_priv) == 9) {
4538                 encoder->enable_clock = skl_ddi_enable_clock;
4539                 encoder->disable_clock = skl_ddi_disable_clock;
4540                 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4541                 encoder->get_config = skl_ddi_get_config;
4542         } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4543                 encoder->enable_clock = hsw_ddi_enable_clock;
4544                 encoder->disable_clock = hsw_ddi_disable_clock;
4545                 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4546                 encoder->get_config = hsw_ddi_get_config;
4547         }
4548
4549         if (IS_DG2(dev_priv)) {
4550                 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
4551         } else if (DISPLAY_VER(dev_priv) >= 12) {
4552                 if (intel_phy_is_combo(dev_priv, phy))
4553                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4554                 else
4555                         encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
4556         } else if (DISPLAY_VER(dev_priv) >= 11) {
4557                 if (intel_phy_is_combo(dev_priv, phy))
4558                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4559                 else
4560                         encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
4561         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4562                 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
4563         } else {
4564                 encoder->set_signal_levels = hsw_set_signal_levels;
4565         }
4566
4567         intel_ddi_buf_trans_init(encoder);
4568
4569         if (DISPLAY_VER(dev_priv) >= 13)
4570                 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4571         else if (IS_DG1(dev_priv))
4572                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4573         else if (IS_ROCKETLAKE(dev_priv))
4574                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4575         else if (DISPLAY_VER(dev_priv) >= 12)
4576                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4577         else if (IS_JSL_EHL(dev_priv))
4578                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4579         else if (DISPLAY_VER(dev_priv) == 11)
4580                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4581         else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4582                 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4583         else
4584                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4585
4586         if (DISPLAY_VER(dev_priv) >= 11)
4587                 dig_port->saved_port_bits =
4588                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4589                         & DDI_BUF_PORT_REVERSAL;
4590         else
4591                 dig_port->saved_port_bits =
4592                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4593                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4594
4595         if (intel_bios_is_lane_reversal_needed(dev_priv, port))
4596                 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4597
4598         dig_port->dp.output_reg = INVALID_MMIO_REG;
4599         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4600         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4601
4602         if (intel_phy_is_tc(dev_priv, phy)) {
4603                 bool is_legacy =
4604                         !intel_bios_encoder_supports_typec_usb(devdata) &&
4605                         !intel_bios_encoder_supports_tbt(devdata);
4606
4607                 intel_tc_port_init(dig_port, is_legacy);
4608
4609                 encoder->update_prepare = intel_ddi_update_prepare;
4610                 encoder->update_complete = intel_ddi_update_complete;
4611         }
4612
4613         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4614         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4615                                               port - PORT_A;
4616
4617         if (init_dp) {
4618                 if (!intel_ddi_init_dp_connector(dig_port))
4619                         goto err;
4620
4621                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4622
4623                 if (dig_port->dp.mso_link_count)
4624                         encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4625         }
4626
4627         /* In theory we don't need the encoder->type check, but leave it just in
4628          * case we have some really bad VBTs... */
4629         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4630                 if (!intel_ddi_init_hdmi_connector(dig_port))
4631                         goto err;
4632         }
4633
4634         if (DISPLAY_VER(dev_priv) >= 11) {
4635                 if (intel_phy_is_tc(dev_priv, phy))
4636                         dig_port->connected = intel_tc_port_connected;
4637                 else
4638                         dig_port->connected = lpt_digital_port_connected;
4639         } else if (DISPLAY_VER(dev_priv) >= 8) {
4640                 if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||
4641                     IS_BROXTON(dev_priv))
4642                         dig_port->connected = bdw_digital_port_connected;
4643                 else
4644                         dig_port->connected = lpt_digital_port_connected;
4645         } else {
4646                 if (port == PORT_A)
4647                         dig_port->connected = hsw_digital_port_connected;
4648                 else
4649                         dig_port->connected = lpt_digital_port_connected;
4650         }
4651
4652         intel_infoframe_init(dig_port);
4653
4654         return;
4655
4656 err:
4657         drm_encoder_cleanup(&encoder->base);
4658         kfree(dig_port);
4659 }