2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <drm/drm_scdc_helper.h>
31 #include "intel_audio.h"
32 #include "intel_combo_phy.h"
33 #include "intel_connector.h"
34 #include "intel_ddi.h"
35 #include "intel_display_types.h"
37 #include "intel_dp_mst.h"
38 #include "intel_dp_link_training.h"
39 #include "intel_dpio_phy.h"
40 #include "intel_dsi.h"
41 #include "intel_fifo_underrun.h"
42 #include "intel_gmbus.h"
43 #include "intel_hdcp.h"
44 #include "intel_hdmi.h"
45 #include "intel_hotplug.h"
46 #include "intel_lspcon.h"
47 #include "intel_panel.h"
48 #include "intel_psr.h"
49 #include "intel_sprite.h"
51 #include "intel_vdsc.h"
53 struct ddi_buf_trans {
54 u32 trans1; /* balance leg enable, de-emph level */
55 u32 trans2; /* vref sel, vswing */
56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
59 static const u8 index_to_dp_signal_levels[] = {
60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
73 * them for both DP and FDI transports, allowing those ports to
74 * automatically adapt to HDMI connections as well
76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
77 { 0x00FFFFFF, 0x0006000E, 0x0 },
78 { 0x00D75FFF, 0x0005000A, 0x0 },
79 { 0x00C30FFF, 0x00040006, 0x0 },
80 { 0x80AAAFFF, 0x000B0000, 0x0 },
81 { 0x00FFFFFF, 0x0005000A, 0x0 },
82 { 0x00D75FFF, 0x000C0004, 0x0 },
83 { 0x80C30FFF, 0x000B0000, 0x0 },
84 { 0x00FFFFFF, 0x00040006, 0x0 },
85 { 0x80D75FFF, 0x000B0000, 0x0 },
88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
89 { 0x00FFFFFF, 0x0007000E, 0x0 },
90 { 0x00D75FFF, 0x000F000A, 0x0 },
91 { 0x00C30FFF, 0x00060006, 0x0 },
92 { 0x00AAAFFF, 0x001E0000, 0x0 },
93 { 0x00FFFFFF, 0x000F000A, 0x0 },
94 { 0x00D75FFF, 0x00160004, 0x0 },
95 { 0x00C30FFF, 0x001E0000, 0x0 },
96 { 0x00FFFFFF, 0x00060006, 0x0 },
97 { 0x00D75FFF, 0x001E0000, 0x0 },
100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
101 /* Idx NT mV d T mV d db */
102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
117 { 0x00FFFFFF, 0x00000012, 0x0 },
118 { 0x00EBAFFF, 0x00020011, 0x0 },
119 { 0x00C71FFF, 0x0006000F, 0x0 },
120 { 0x00AAAFFF, 0x000E000A, 0x0 },
121 { 0x00FFFFFF, 0x00020011, 0x0 },
122 { 0x00DB6FFF, 0x0005000F, 0x0 },
123 { 0x00BEEFFF, 0x000A000C, 0x0 },
124 { 0x00FFFFFF, 0x0005000F, 0x0 },
125 { 0x00DB6FFF, 0x000A000C, 0x0 },
128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
129 { 0x00FFFFFF, 0x0007000E, 0x0 },
130 { 0x00D75FFF, 0x000E000A, 0x0 },
131 { 0x00BEFFFF, 0x00140006, 0x0 },
132 { 0x80B2CFFF, 0x001B0002, 0x0 },
133 { 0x00FFFFFF, 0x000E000A, 0x0 },
134 { 0x00DB6FFF, 0x00160005, 0x0 },
135 { 0x80C71FFF, 0x001A0002, 0x0 },
136 { 0x00F7DFFF, 0x00180004, 0x0 },
137 { 0x80D75FFF, 0x001B0002, 0x0 },
140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
141 { 0x00FFFFFF, 0x0001000E, 0x0 },
142 { 0x00D75FFF, 0x0004000A, 0x0 },
143 { 0x00C30FFF, 0x00070006, 0x0 },
144 { 0x00AAAFFF, 0x000C0000, 0x0 },
145 { 0x00FFFFFF, 0x0004000A, 0x0 },
146 { 0x00D75FFF, 0x00090004, 0x0 },
147 { 0x00C30FFF, 0x000C0000, 0x0 },
148 { 0x00FFFFFF, 0x00070006, 0x0 },
149 { 0x00D75FFF, 0x000C0000, 0x0 },
152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
153 /* Idx NT mV d T mV df db */
154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
166 /* Skylake H and S */
167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
168 { 0x00002016, 0x000000A0, 0x0 },
169 { 0x00005012, 0x0000009B, 0x0 },
170 { 0x00007011, 0x00000088, 0x0 },
171 { 0x80009010, 0x000000C0, 0x1 },
172 { 0x00002016, 0x0000009B, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000C0, 0x1 },
175 { 0x00002016, 0x000000DF, 0x0 },
176 { 0x80005012, 0x000000C0, 0x1 },
180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
181 { 0x0000201B, 0x000000A2, 0x0 },
182 { 0x00005012, 0x00000088, 0x0 },
183 { 0x80007011, 0x000000CD, 0x1 },
184 { 0x80009010, 0x000000C0, 0x1 },
185 { 0x0000201B, 0x0000009D, 0x0 },
186 { 0x80005012, 0x000000C0, 0x1 },
187 { 0x80007011, 0x000000C0, 0x1 },
188 { 0x00002016, 0x00000088, 0x0 },
189 { 0x80005012, 0x000000C0, 0x1 },
193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
194 { 0x00000018, 0x000000A2, 0x0 },
195 { 0x00005012, 0x00000088, 0x0 },
196 { 0x80007011, 0x000000CD, 0x3 },
197 { 0x80009010, 0x000000C0, 0x3 },
198 { 0x00000018, 0x0000009D, 0x0 },
199 { 0x80005012, 0x000000C0, 0x3 },
200 { 0x80007011, 0x000000C0, 0x3 },
201 { 0x00000018, 0x00000088, 0x0 },
202 { 0x80005012, 0x000000C0, 0x3 },
205 /* Kabylake H and S */
206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
207 { 0x00002016, 0x000000A0, 0x0 },
208 { 0x00005012, 0x0000009B, 0x0 },
209 { 0x00007011, 0x00000088, 0x0 },
210 { 0x80009010, 0x000000C0, 0x1 },
211 { 0x00002016, 0x0000009B, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000C0, 0x1 },
214 { 0x00002016, 0x00000097, 0x0 },
215 { 0x80005012, 0x000000C0, 0x1 },
219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
220 { 0x0000201B, 0x000000A1, 0x0 },
221 { 0x00005012, 0x00000088, 0x0 },
222 { 0x80007011, 0x000000CD, 0x3 },
223 { 0x80009010, 0x000000C0, 0x3 },
224 { 0x0000201B, 0x0000009D, 0x0 },
225 { 0x80005012, 0x000000C0, 0x3 },
226 { 0x80007011, 0x000000C0, 0x3 },
227 { 0x00002016, 0x0000004F, 0x0 },
228 { 0x80005012, 0x000000C0, 0x3 },
232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
233 { 0x00001017, 0x000000A1, 0x0 },
234 { 0x00005012, 0x00000088, 0x0 },
235 { 0x80007011, 0x000000CD, 0x3 },
236 { 0x8000800F, 0x000000C0, 0x3 },
237 { 0x00001017, 0x0000009D, 0x0 },
238 { 0x80005012, 0x000000C0, 0x3 },
239 { 0x80007011, 0x000000C0, 0x3 },
240 { 0x00001017, 0x0000004C, 0x0 },
241 { 0x80005012, 0x000000C0, 0x3 },
245 * Skylake/Kabylake H and S
246 * eDP 1.4 low vswing translation parameters
248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
249 { 0x00000018, 0x000000A8, 0x0 },
250 { 0x00004013, 0x000000A9, 0x0 },
251 { 0x00007011, 0x000000A2, 0x0 },
252 { 0x00009010, 0x0000009C, 0x0 },
253 { 0x00000018, 0x000000A9, 0x0 },
254 { 0x00006013, 0x000000A2, 0x0 },
255 { 0x00007011, 0x000000A6, 0x0 },
256 { 0x00000018, 0x000000AB, 0x0 },
257 { 0x00007013, 0x0000009F, 0x0 },
258 { 0x00000018, 0x000000DF, 0x0 },
263 * eDP 1.4 low vswing translation parameters
265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
266 { 0x00000018, 0x000000A8, 0x0 },
267 { 0x00004013, 0x000000A9, 0x0 },
268 { 0x00007011, 0x000000A2, 0x0 },
269 { 0x00009010, 0x0000009C, 0x0 },
270 { 0x00000018, 0x000000A9, 0x0 },
271 { 0x00006013, 0x000000A2, 0x0 },
272 { 0x00007011, 0x000000A6, 0x0 },
273 { 0x00002016, 0x000000AB, 0x0 },
274 { 0x00005013, 0x0000009F, 0x0 },
275 { 0x00000018, 0x000000DF, 0x0 },
280 * eDP 1.4 low vswing translation parameters
282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
283 { 0x00000018, 0x000000A8, 0x0 },
284 { 0x00004013, 0x000000AB, 0x0 },
285 { 0x00007011, 0x000000A4, 0x0 },
286 { 0x00009010, 0x000000DF, 0x0 },
287 { 0x00000018, 0x000000AA, 0x0 },
288 { 0x00006013, 0x000000A4, 0x0 },
289 { 0x00007011, 0x0000009D, 0x0 },
290 { 0x00000018, 0x000000A0, 0x0 },
291 { 0x00006012, 0x000000DF, 0x0 },
292 { 0x00000018, 0x0000008A, 0x0 },
295 /* Skylake/Kabylake U, H and S */
296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
297 { 0x00000018, 0x000000AC, 0x0 },
298 { 0x00005012, 0x0000009D, 0x0 },
299 { 0x00007011, 0x00000088, 0x0 },
300 { 0x00000018, 0x000000A1, 0x0 },
301 { 0x00000018, 0x00000098, 0x0 },
302 { 0x00004013, 0x00000088, 0x0 },
303 { 0x80006012, 0x000000CD, 0x1 },
304 { 0x00000018, 0x000000DF, 0x0 },
305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
306 { 0x80003015, 0x000000C0, 0x1 },
307 { 0x80000018, 0x000000C0, 0x1 },
310 /* Skylake/Kabylake Y */
311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
312 { 0x00000018, 0x000000A1, 0x0 },
313 { 0x00005012, 0x000000DF, 0x0 },
314 { 0x80007011, 0x000000CB, 0x3 },
315 { 0x00000018, 0x000000A4, 0x0 },
316 { 0x00000018, 0x0000009D, 0x0 },
317 { 0x00004013, 0x00000080, 0x0 },
318 { 0x80006013, 0x000000C0, 0x3 },
319 { 0x00000018, 0x0000008A, 0x0 },
320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
321 { 0x80003015, 0x000000C0, 0x3 },
322 { 0x80000018, 0x000000C0, 0x3 },
325 struct bxt_ddi_buf_trans {
326 u8 margin; /* swing value */
327 u8 scale; /* scale value */
328 u8 enable; /* scale enable */
332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
333 /* Idx NT mV diff db */
334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
347 /* Idx NT mV diff db */
348 { 26, 0, 0, 128, }, /* 0: 200 0 */
349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
350 { 48, 0, 0, 96, }, /* 2: 200 4 */
351 { 54, 0, 0, 69, }, /* 3: 200 6 */
352 { 32, 0, 0, 128, }, /* 4: 250 0 */
353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
354 { 54, 0, 0, 85, }, /* 6: 250 4 */
355 { 43, 0, 0, 128, }, /* 7: 300 0 */
356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
357 { 48, 0, 0, 128, }, /* 9: 300 0 */
360 /* BSpec has 2 recommended values - entries 0 and 8.
361 * Using the entry with higher vswing.
363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
364 /* Idx NT mV diff db */
365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
377 struct cnl_ddi_buf_trans {
381 u8 dw4_post_cursor_2;
382 u8 dw4_post_cursor_1;
385 /* Voltage Swing Programming for VccIO 0.85V for DP */
386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
387 /* NT mV Trans mV db */
388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
402 /* NT mV Trans mV db */
403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
414 /* NT mV Trans mV db */
415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
426 /* Voltage Swing Programming for VccIO 0.95V for DP */
427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
428 /* NT mV Trans mV db */
429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
443 /* NT mV Trans mV db */
444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
459 /* NT mV Trans mV db */
460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
472 /* Voltage Swing Programming for VccIO 1.05V for DP */
473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
474 /* NT mV Trans mV db */
475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
489 /* NT mV Trans mV db */
490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
505 /* NT mV Trans mV db */
506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
517 /* icl_combo_phy_ddi_translations */
518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
519 /* NT mV Trans mV db */
520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
533 /* NT mV Trans mV db */
534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
547 /* NT mV Trans mV db */
548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
561 /* NT mV Trans mV db */
562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
572 /* NT mV Trans mV db */
573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
575 { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */
576 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
578 { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
579 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
581 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
585 struct icl_mg_phy_ddi_buf_trans {
586 u32 cri_txdeemph_override_11_6;
587 u32 cri_txdeemph_override_5_0;
588 u32 cri_txdeemph_override_17_12;
591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
592 /* Voltage swing pre-emphasis */
593 { 0x18, 0x00, 0x00 }, /* 0 0 */
594 { 0x1D, 0x00, 0x05 }, /* 0 1 */
595 { 0x24, 0x00, 0x0C }, /* 0 2 */
596 { 0x2B, 0x00, 0x14 }, /* 0 3 */
597 { 0x21, 0x00, 0x00 }, /* 1 0 */
598 { 0x2B, 0x00, 0x08 }, /* 1 1 */
599 { 0x30, 0x00, 0x0F }, /* 1 2 */
600 { 0x31, 0x00, 0x03 }, /* 2 0 */
601 { 0x34, 0x00, 0x0B }, /* 2 1 */
602 { 0x3F, 0x00, 0x00 }, /* 3 0 */
605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
606 /* Voltage swing pre-emphasis */
607 { 0x18, 0x00, 0x00 }, /* 0 0 */
608 { 0x1D, 0x00, 0x05 }, /* 0 1 */
609 { 0x24, 0x00, 0x0C }, /* 0 2 */
610 { 0x2B, 0x00, 0x14 }, /* 0 3 */
611 { 0x26, 0x00, 0x00 }, /* 1 0 */
612 { 0x2C, 0x00, 0x07 }, /* 1 1 */
613 { 0x33, 0x00, 0x0C }, /* 1 2 */
614 { 0x2E, 0x00, 0x00 }, /* 2 0 */
615 { 0x36, 0x00, 0x09 }, /* 2 1 */
616 { 0x3F, 0x00, 0x00 }, /* 3 0 */
619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
620 /* HDMI Preset VS Pre-emph */
621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */
622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */
623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */
624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */
625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */
626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */
627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */
628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */
629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */
630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */
633 struct tgl_dkl_phy_ddi_buf_trans {
634 u32 dkl_vswing_control;
635 u32 dkl_preshoot_control;
636 u32 dkl_de_emphasis_control;
639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
640 /* VS pre-emp Non-trans mV Pre-emph dB */
641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
642 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
643 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
644 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */
645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
646 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = {
654 /* VS pre-emp Non-trans mV Pre-emph dB */
655 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
656 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
657 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
658 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
659 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
660 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
661 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
662 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
663 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
664 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
668 /* HDMI Preset VS Pre-emph */
669 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */
670 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */
671 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */
672 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */
673 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */
674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */
675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */
676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */
677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */
678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
682 /* NT mV Trans mV db */
683 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
685 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
686 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
687 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
688 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
690 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
691 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
696 /* NT mV Trans mV db */
697 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
698 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
699 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
700 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
701 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
702 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
703 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
704 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
705 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
709 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
710 /* NT mV Trans mV db */
711 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
712 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
713 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
714 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
715 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
716 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
717 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
718 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
719 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
720 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
724 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
725 * that DisplayPort specification requires
727 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
729 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */
730 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */
731 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */
732 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */
733 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */
734 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */
735 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */
736 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */
737 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */
740 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
742 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
745 static const struct ddi_buf_trans *
746 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
750 if (dev_priv->vbt.edp.low_vswing) {
751 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
752 return bdw_ddi_translations_edp;
754 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
755 return bdw_ddi_translations_dp;
759 static const struct ddi_buf_trans *
760 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
762 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
764 if (IS_SKL_ULX(dev_priv)) {
765 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
766 return skl_y_ddi_translations_dp;
767 } else if (IS_SKL_ULT(dev_priv)) {
768 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
769 return skl_u_ddi_translations_dp;
771 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
772 return skl_ddi_translations_dp;
776 static const struct ddi_buf_trans *
777 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
781 if (IS_KBL_ULX(dev_priv) ||
782 IS_CFL_ULX(dev_priv) ||
783 IS_CML_ULX(dev_priv)) {
784 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
785 return kbl_y_ddi_translations_dp;
786 } else if (IS_KBL_ULT(dev_priv) ||
787 IS_CFL_ULT(dev_priv) ||
788 IS_CML_ULT(dev_priv)) {
789 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
790 return kbl_u_ddi_translations_dp;
792 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
793 return kbl_ddi_translations_dp;
797 static const struct ddi_buf_trans *
798 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
802 if (dev_priv->vbt.edp.low_vswing) {
803 if (IS_SKL_ULX(dev_priv) ||
804 IS_KBL_ULX(dev_priv) ||
805 IS_CFL_ULX(dev_priv) ||
806 IS_CML_ULX(dev_priv)) {
807 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
808 return skl_y_ddi_translations_edp;
809 } else if (IS_SKL_ULT(dev_priv) ||
810 IS_KBL_ULT(dev_priv) ||
811 IS_CFL_ULT(dev_priv) ||
812 IS_CML_ULT(dev_priv)) {
813 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
814 return skl_u_ddi_translations_edp;
816 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
817 return skl_ddi_translations_edp;
821 if (IS_KABYLAKE(dev_priv) ||
822 IS_COFFEELAKE(dev_priv) ||
823 IS_COMETLAKE(dev_priv))
824 return kbl_get_buf_trans_dp(encoder, n_entries);
826 return skl_get_buf_trans_dp(encoder, n_entries);
829 static const struct ddi_buf_trans *
830 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
832 if (IS_SKL_ULX(dev_priv) ||
833 IS_KBL_ULX(dev_priv) ||
834 IS_CFL_ULX(dev_priv) ||
835 IS_CML_ULX(dev_priv)) {
836 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
837 return skl_y_ddi_translations_hdmi;
839 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
840 return skl_ddi_translations_hdmi;
844 static int skl_buf_trans_num_entries(enum port port, int n_entries)
846 /* Only DDIA and DDIE can select the 10th register with DP */
847 if (port == PORT_A || port == PORT_E)
848 return min(n_entries, 10);
850 return min(n_entries, 9);
853 static const struct ddi_buf_trans *
854 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
858 if (IS_KABYLAKE(dev_priv) ||
859 IS_COFFEELAKE(dev_priv) ||
860 IS_COMETLAKE(dev_priv)) {
861 const struct ddi_buf_trans *ddi_translations =
862 kbl_get_buf_trans_dp(encoder, n_entries);
863 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
864 return ddi_translations;
865 } else if (IS_SKYLAKE(dev_priv)) {
866 const struct ddi_buf_trans *ddi_translations =
867 skl_get_buf_trans_dp(encoder, n_entries);
868 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
869 return ddi_translations;
870 } else if (IS_BROADWELL(dev_priv)) {
871 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
872 return bdw_ddi_translations_dp;
873 } else if (IS_HASWELL(dev_priv)) {
874 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
875 return hsw_ddi_translations_dp;
882 static const struct ddi_buf_trans *
883 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
887 if (IS_GEN9_BC(dev_priv)) {
888 const struct ddi_buf_trans *ddi_translations =
889 skl_get_buf_trans_edp(encoder, n_entries);
890 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
891 return ddi_translations;
892 } else if (IS_BROADWELL(dev_priv)) {
893 return bdw_get_buf_trans_edp(encoder, n_entries);
894 } else if (IS_HASWELL(dev_priv)) {
895 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
896 return hsw_ddi_translations_dp;
903 static const struct ddi_buf_trans *
904 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
907 if (IS_BROADWELL(dev_priv)) {
908 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
909 return bdw_ddi_translations_fdi;
910 } else if (IS_HASWELL(dev_priv)) {
911 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
912 return hsw_ddi_translations_fdi;
919 static const struct ddi_buf_trans *
920 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
925 if (IS_GEN9_BC(dev_priv)) {
926 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
927 } else if (IS_BROADWELL(dev_priv)) {
928 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
929 return bdw_ddi_translations_hdmi;
930 } else if (IS_HASWELL(dev_priv)) {
931 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
932 return hsw_ddi_translations_hdmi;
939 static const struct bxt_ddi_buf_trans *
940 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
942 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
943 return bxt_ddi_translations_dp;
946 static const struct bxt_ddi_buf_trans *
947 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
951 if (dev_priv->vbt.edp.low_vswing) {
952 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
953 return bxt_ddi_translations_edp;
956 return bxt_get_buf_trans_dp(encoder, n_entries);
959 static const struct bxt_ddi_buf_trans *
960 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
962 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
963 return bxt_ddi_translations_hdmi;
966 static const struct cnl_ddi_buf_trans *
967 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
969 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
970 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
972 if (voltage == VOLTAGE_INFO_0_85V) {
973 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
974 return cnl_ddi_translations_hdmi_0_85V;
975 } else if (voltage == VOLTAGE_INFO_0_95V) {
976 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
977 return cnl_ddi_translations_hdmi_0_95V;
978 } else if (voltage == VOLTAGE_INFO_1_05V) {
979 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
980 return cnl_ddi_translations_hdmi_1_05V;
982 *n_entries = 1; /* shut up gcc */
983 MISSING_CASE(voltage);
988 static const struct cnl_ddi_buf_trans *
989 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
992 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
994 if (voltage == VOLTAGE_INFO_0_85V) {
995 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
996 return cnl_ddi_translations_dp_0_85V;
997 } else if (voltage == VOLTAGE_INFO_0_95V) {
998 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
999 return cnl_ddi_translations_dp_0_95V;
1000 } else if (voltage == VOLTAGE_INFO_1_05V) {
1001 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1002 return cnl_ddi_translations_dp_1_05V;
1004 *n_entries = 1; /* shut up gcc */
1005 MISSING_CASE(voltage);
1010 static const struct cnl_ddi_buf_trans *
1011 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1014 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1016 if (dev_priv->vbt.edp.low_vswing) {
1017 if (voltage == VOLTAGE_INFO_0_85V) {
1018 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1019 return cnl_ddi_translations_edp_0_85V;
1020 } else if (voltage == VOLTAGE_INFO_0_95V) {
1021 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1022 return cnl_ddi_translations_edp_0_95V;
1023 } else if (voltage == VOLTAGE_INFO_1_05V) {
1024 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1025 return cnl_ddi_translations_edp_1_05V;
1027 *n_entries = 1; /* shut up gcc */
1028 MISSING_CASE(voltage);
1032 return cnl_get_buf_trans_dp(encoder, n_entries);
1036 static const struct cnl_ddi_buf_trans *
1037 icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1042 if (type == INTEL_OUTPUT_HDMI) {
1043 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1044 return icl_combo_phy_ddi_translations_hdmi;
1045 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
1046 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1047 return icl_combo_phy_ddi_translations_edp_hbr3;
1048 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1049 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1050 return icl_combo_phy_ddi_translations_edp_hbr2;
1053 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1054 return icl_combo_phy_ddi_translations_dp_hbr2;
1057 static const struct icl_mg_phy_ddi_buf_trans *
1058 icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
1061 if (type == INTEL_OUTPUT_HDMI) {
1062 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
1063 return icl_mg_phy_ddi_translations_hdmi;
1064 } else if (rate > 270000) {
1065 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
1066 return icl_mg_phy_ddi_translations_hbr2_hbr3;
1069 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
1070 return icl_mg_phy_ddi_translations_rbr_hbr;
1073 static const struct cnl_ddi_buf_trans *
1074 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1077 if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
1078 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
1079 return ehl_combo_phy_ddi_translations_dp;
1082 return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
1085 static const struct cnl_ddi_buf_trans *
1086 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1089 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1091 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
1092 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1094 if (!intel_dp->hobl_failed && rate <= 540000) {
1095 /* Same table applies to TGL, RKL and DG1 */
1096 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
1097 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
1101 if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
1102 return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
1103 } else if (rate > 270000) {
1104 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1105 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
1106 return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
1109 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1110 return tgl_combo_phy_ddi_translations_dp_hbr2;
1113 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1114 return tgl_combo_phy_ddi_translations_dp_hbr;
1117 static const struct tgl_dkl_phy_ddi_buf_trans *
1118 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
1121 if (type == INTEL_OUTPUT_HDMI) {
1122 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1123 return tgl_dkl_phy_hdmi_ddi_trans;
1124 } else if (rate > 270000) {
1125 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
1126 return tgl_dkl_phy_dp_ddi_trans_hbr2;
1129 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
1130 return tgl_dkl_phy_dp_ddi_trans;
1133 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
1135 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1136 int n_entries, level, default_entry;
1137 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1139 if (INTEL_GEN(dev_priv) >= 12) {
1140 if (intel_phy_is_combo(dev_priv, phy))
1141 tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1144 tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1146 default_entry = n_entries - 1;
1147 } else if (INTEL_GEN(dev_priv) == 11) {
1148 if (intel_phy_is_combo(dev_priv, phy))
1149 icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1152 icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1154 default_entry = n_entries - 1;
1155 } else if (IS_CANNONLAKE(dev_priv)) {
1156 cnl_get_buf_trans_hdmi(encoder, &n_entries);
1157 default_entry = n_entries - 1;
1158 } else if (IS_GEN9_LP(dev_priv)) {
1159 bxt_get_buf_trans_hdmi(encoder, &n_entries);
1160 default_entry = n_entries - 1;
1161 } else if (IS_GEN9_BC(dev_priv)) {
1162 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1164 } else if (IS_BROADWELL(dev_priv)) {
1165 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1167 } else if (IS_HASWELL(dev_priv)) {
1168 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1171 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1175 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1178 level = intel_bios_hdmi_level_shift(encoder);
1180 level = default_entry;
1182 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1183 level = n_entries - 1;
1189 * Starting with Haswell, DDI port buffers must be programmed with correct
1190 * values in advance. This function programs the correct values for
1191 * DP/eDP/FDI use cases.
1193 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1194 const struct intel_crtc_state *crtc_state)
1196 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1199 enum port port = encoder->port;
1200 const struct ddi_buf_trans *ddi_translations;
1202 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1203 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1205 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1206 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
1209 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
1212 /* If we're boosting the current, set bit 31 of trans1 */
1213 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1214 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1216 for (i = 0; i < n_entries; i++) {
1217 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1218 ddi_translations[i].trans1 | iboost_bit);
1219 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1220 ddi_translations[i].trans2);
1225 * Starting with Haswell, DDI port buffers must be programmed with correct
1226 * values in advance. This function programs the correct values for
1227 * HDMI/DVI use cases.
1229 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1235 enum port port = encoder->port;
1236 const struct ddi_buf_trans *ddi_translations;
1238 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1240 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1242 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1243 level = n_entries - 1;
1245 /* If we're boosting the current, set bit 31 of trans1 */
1246 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1247 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1249 /* Entry 9 is for HDMI: */
1250 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1251 ddi_translations[level].trans1 | iboost_bit);
1252 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1253 ddi_translations[level].trans2);
1256 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1259 if (IS_BROXTON(dev_priv)) {
1264 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1265 DDI_BUF_IS_IDLE), 8))
1266 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
1270 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
1273 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
1274 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
1275 usleep_range(518, 1000);
1279 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1280 DDI_BUF_IS_IDLE), 500))
1281 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
1285 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1287 switch (pll->info->id) {
1288 case DPLL_ID_WRPLL1:
1289 return PORT_CLK_SEL_WRPLL1;
1290 case DPLL_ID_WRPLL2:
1291 return PORT_CLK_SEL_WRPLL2;
1293 return PORT_CLK_SEL_SPLL;
1294 case DPLL_ID_LCPLL_810:
1295 return PORT_CLK_SEL_LCPLL_810;
1296 case DPLL_ID_LCPLL_1350:
1297 return PORT_CLK_SEL_LCPLL_1350;
1298 case DPLL_ID_LCPLL_2700:
1299 return PORT_CLK_SEL_LCPLL_2700;
1301 MISSING_CASE(pll->info->id);
1302 return PORT_CLK_SEL_NONE;
1306 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1307 const struct intel_crtc_state *crtc_state)
1309 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1310 int clock = crtc_state->port_clock;
1311 const enum intel_dpll_id id = pll->info->id;
1316 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1317 * here, so do warn if this get passed in
1320 return DDI_CLK_SEL_NONE;
1321 case DPLL_ID_ICL_TBTPLL:
1324 return DDI_CLK_SEL_TBT_162;
1326 return DDI_CLK_SEL_TBT_270;
1328 return DDI_CLK_SEL_TBT_540;
1330 return DDI_CLK_SEL_TBT_810;
1332 MISSING_CASE(clock);
1333 return DDI_CLK_SEL_NONE;
1335 case DPLL_ID_ICL_MGPLL1:
1336 case DPLL_ID_ICL_MGPLL2:
1337 case DPLL_ID_ICL_MGPLL3:
1338 case DPLL_ID_ICL_MGPLL4:
1339 case DPLL_ID_TGL_MGPLL5:
1340 case DPLL_ID_TGL_MGPLL6:
1341 return DDI_CLK_SEL_MG;
1345 /* Starting with Haswell, different DDI ports can work in FDI mode for
1346 * connection to the PCH-located connectors. For this, it is necessary to train
1347 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1349 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1350 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1351 * DDI A (which is used for eDP)
1354 void hsw_fdi_link_train(struct intel_encoder *encoder,
1355 const struct intel_crtc_state *crtc_state)
1357 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1359 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1361 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1363 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1364 * mode set "sequence for CRT port" document:
1365 * - TP1 to TP2 time with the default value
1366 * - FDI delay to 90h
1368 * WaFDIAutoLinkSetTimingOverrride:hsw
1370 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1371 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1373 /* Enable the PCH Receiver FDI PLL */
1374 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1376 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1377 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1378 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1381 /* Switch from Rawclk to PCDclk */
1382 rx_ctl_val |= FDI_PCDCLK;
1383 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1385 /* Configure Port Clock Select */
1386 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1387 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1388 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1390 /* Start the training iterating through available voltages and emphasis,
1391 * testing each value twice. */
1392 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1393 /* Configure DP_TP_CTL with auto-training */
1394 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1395 DP_TP_CTL_FDI_AUTOTRAIN |
1396 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1397 DP_TP_CTL_LINK_TRAIN_PAT1 |
1400 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1401 * DDI E does not support port reversal, the functionality is
1402 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1403 * port reversal bit */
1404 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1405 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1406 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1410 /* Program PCH FDI Receiver TU */
1411 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1413 /* Enable PCH FDI Receiver with auto-training */
1414 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1415 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1416 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1418 /* Wait for FDI receiver lane calibration */
1421 /* Unset FDI_RX_MISC pwrdn lanes */
1422 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1423 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1424 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1425 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1427 /* Wait for FDI auto training time */
1430 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1431 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1432 drm_dbg_kms(&dev_priv->drm,
1433 "FDI link training done on step %d\n", i);
1438 * Leave things enabled even if we failed to train FDI.
1439 * Results in less fireworks from the state checker.
1441 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1442 drm_err(&dev_priv->drm, "FDI link training failed!\n");
1446 rx_ctl_val &= ~FDI_RX_ENABLE;
1447 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1448 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1450 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1451 temp &= ~DDI_BUF_CTL_ENABLE;
1452 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1453 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1455 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1456 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1457 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1458 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1459 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1460 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1462 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1464 /* Reset FDI_RX_MISC pwrdn lanes */
1465 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1466 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1467 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1468 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1469 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1472 /* Enable normal pixel sending for FDI */
1473 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1474 DP_TP_CTL_FDI_AUTOTRAIN |
1475 DP_TP_CTL_LINK_TRAIN_NORMAL |
1476 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1480 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1482 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1483 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1485 intel_dp->DP = dig_port->saved_port_bits |
1486 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1487 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1490 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1493 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1496 case DDI_CLK_SEL_NONE:
1498 case DDI_CLK_SEL_TBT_162:
1500 case DDI_CLK_SEL_TBT_270:
1502 case DDI_CLK_SEL_TBT_540:
1504 case DDI_CLK_SEL_TBT_810:
1512 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1516 if (pipe_config->has_pch_encoder)
1517 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1518 &pipe_config->fdi_m_n);
1519 else if (intel_crtc_has_dp_encoder(pipe_config))
1520 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1521 &pipe_config->dp_m_n);
1522 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1523 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1525 dotclock = pipe_config->port_clock;
1527 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1528 !intel_crtc_has_dp_encoder(pipe_config))
1531 if (pipe_config->pixel_multiplier)
1532 dotclock /= pipe_config->pixel_multiplier;
1534 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1537 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1538 struct intel_crtc_state *pipe_config)
1540 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1541 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1543 if (intel_phy_is_tc(dev_priv, phy) &&
1544 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1546 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1549 pipe_config->port_clock =
1550 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
1552 ddi_dotclock_get(pipe_config);
1555 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1556 const struct drm_connector_state *conn_state)
1558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1560 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1563 if (!intel_crtc_has_dp_encoder(crtc_state))
1566 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1568 temp = DP_MSA_MISC_SYNC_CLOCK;
1570 switch (crtc_state->pipe_bpp) {
1572 temp |= DP_MSA_MISC_6_BPC;
1575 temp |= DP_MSA_MISC_8_BPC;
1578 temp |= DP_MSA_MISC_10_BPC;
1581 temp |= DP_MSA_MISC_12_BPC;
1584 MISSING_CASE(crtc_state->pipe_bpp);
1588 /* nonsense combination */
1589 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1590 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1592 if (crtc_state->limited_color_range)
1593 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1596 * As per DP 1.2 spec section 2.3.4.3 while sending
1597 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1598 * colorspace information.
1600 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1601 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1604 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1605 * of Color Encoding Format and Content Color Gamut] while sending
1606 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1607 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1609 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1610 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1612 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1615 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1617 if (master_transcoder == TRANSCODER_EDP)
1620 return master_transcoder + 1;
1624 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1626 * Only intended to be used by intel_ddi_enable_transcoder_func() and
1627 * intel_ddi_config_transcoder_func().
1630 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
1631 const struct intel_crtc_state *crtc_state)
1633 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1634 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1635 enum pipe pipe = crtc->pipe;
1636 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1637 enum port port = encoder->port;
1640 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1641 temp = TRANS_DDI_FUNC_ENABLE;
1642 if (INTEL_GEN(dev_priv) >= 12)
1643 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1645 temp |= TRANS_DDI_SELECT_PORT(port);
1647 switch (crtc_state->pipe_bpp) {
1649 temp |= TRANS_DDI_BPC_6;
1652 temp |= TRANS_DDI_BPC_8;
1655 temp |= TRANS_DDI_BPC_10;
1658 temp |= TRANS_DDI_BPC_12;
1664 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1665 temp |= TRANS_DDI_PVSYNC;
1666 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1667 temp |= TRANS_DDI_PHSYNC;
1669 if (cpu_transcoder == TRANSCODER_EDP) {
1672 /* On Haswell, can only use the always-on power well for
1673 * eDP when not using the panel fitter, and when not
1674 * using motion blur mitigation (which we don't
1676 if (crtc_state->pch_pfit.force_thru)
1677 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1679 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1682 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1685 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1693 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1694 if (crtc_state->has_hdmi_sink)
1695 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1697 temp |= TRANS_DDI_MODE_SELECT_DVI;
1699 if (crtc_state->hdmi_scrambling)
1700 temp |= TRANS_DDI_HDMI_SCRAMBLING;
1701 if (crtc_state->hdmi_high_tmds_clock_ratio)
1702 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1703 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1704 temp |= TRANS_DDI_MODE_SELECT_FDI;
1705 temp |= (crtc_state->fdi_lanes - 1) << 1;
1706 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1707 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1708 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1710 if (INTEL_GEN(dev_priv) >= 12) {
1711 enum transcoder master;
1713 master = crtc_state->mst_master_transcoder;
1714 drm_WARN_ON(&dev_priv->drm,
1715 master == INVALID_TRANSCODER);
1716 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1719 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1720 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1723 if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1724 crtc_state->master_transcoder != INVALID_TRANSCODER) {
1726 bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1728 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1729 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1735 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
1736 const struct intel_crtc_state *crtc_state)
1738 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1739 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1740 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1742 if (INTEL_GEN(dev_priv) >= 11) {
1743 enum transcoder master_transcoder = crtc_state->master_transcoder;
1746 if (master_transcoder != INVALID_TRANSCODER) {
1748 bdw_trans_port_sync_master_select(master_transcoder);
1750 ctl2 |= PORT_SYNC_MODE_ENABLE |
1751 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1754 intel_de_write(dev_priv,
1755 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
1758 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
1759 intel_ddi_transcoder_func_reg_val_get(encoder,
1764 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1768 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
1769 const struct intel_crtc_state *crtc_state)
1771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1772 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1773 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1776 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
1777 ctl &= ~TRANS_DDI_FUNC_ENABLE;
1778 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1781 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1783 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1784 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1785 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1788 if (INTEL_GEN(dev_priv) >= 11)
1789 intel_de_write(dev_priv,
1790 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
1792 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1794 ctl &= ~TRANS_DDI_FUNC_ENABLE;
1796 if (IS_GEN_RANGE(dev_priv, 8, 10))
1797 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
1798 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
1800 if (INTEL_GEN(dev_priv) >= 12) {
1801 if (!intel_dp_mst_is_master_trans(crtc_state)) {
1802 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
1803 TRANS_DDI_MODE_SELECT_MASK);
1806 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
1809 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1811 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1812 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1813 drm_dbg_kms(&dev_priv->drm,
1814 "Quirk Increase DDI disabled time\n");
1815 /* Quirk time at 100ms for reliable operation */
1820 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1823 struct drm_device *dev = intel_encoder->base.dev;
1824 struct drm_i915_private *dev_priv = to_i915(dev);
1825 intel_wakeref_t wakeref;
1830 wakeref = intel_display_power_get_if_enabled(dev_priv,
1831 intel_encoder->power_domain);
1832 if (drm_WARN_ON(dev, !wakeref))
1835 if (drm_WARN_ON(dev,
1836 !intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1841 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe));
1843 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1845 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1846 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp);
1848 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1852 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1854 struct drm_device *dev = intel_connector->base.dev;
1855 struct drm_i915_private *dev_priv = to_i915(dev);
1856 struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1857 int type = intel_connector->base.connector_type;
1858 enum port port = encoder->port;
1859 enum transcoder cpu_transcoder;
1860 intel_wakeref_t wakeref;
1865 wakeref = intel_display_power_get_if_enabled(dev_priv,
1866 encoder->power_domain);
1870 if (!encoder->get_hw_state(encoder, &pipe)) {
1875 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
1876 cpu_transcoder = TRANSCODER_EDP;
1878 cpu_transcoder = (enum transcoder) pipe;
1880 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1882 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1883 case TRANS_DDI_MODE_SELECT_HDMI:
1884 case TRANS_DDI_MODE_SELECT_DVI:
1885 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1888 case TRANS_DDI_MODE_SELECT_DP_SST:
1889 ret = type == DRM_MODE_CONNECTOR_eDP ||
1890 type == DRM_MODE_CONNECTOR_DisplayPort;
1893 case TRANS_DDI_MODE_SELECT_DP_MST:
1894 /* if the transcoder is in MST state then
1895 * connector isn't connected */
1899 case TRANS_DDI_MODE_SELECT_FDI:
1900 ret = type == DRM_MODE_CONNECTOR_VGA;
1909 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1914 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1915 u8 *pipe_mask, bool *is_dp_mst)
1917 struct drm_device *dev = encoder->base.dev;
1918 struct drm_i915_private *dev_priv = to_i915(dev);
1919 enum port port = encoder->port;
1920 intel_wakeref_t wakeref;
1928 wakeref = intel_display_power_get_if_enabled(dev_priv,
1929 encoder->power_domain);
1933 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1934 if (!(tmp & DDI_BUF_CTL_ENABLE))
1937 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
1938 tmp = intel_de_read(dev_priv,
1939 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1941 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1943 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1945 case TRANS_DDI_EDP_INPUT_A_ON:
1946 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1947 *pipe_mask = BIT(PIPE_A);
1949 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1950 *pipe_mask = BIT(PIPE_B);
1952 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1953 *pipe_mask = BIT(PIPE_C);
1961 for_each_pipe(dev_priv, p) {
1962 enum transcoder cpu_transcoder = (enum transcoder)p;
1963 unsigned int port_mask, ddi_select;
1964 intel_wakeref_t trans_wakeref;
1966 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
1967 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1971 if (INTEL_GEN(dev_priv) >= 12) {
1972 port_mask = TGL_TRANS_DDI_PORT_MASK;
1973 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
1975 port_mask = TRANS_DDI_PORT_MASK;
1976 ddi_select = TRANS_DDI_SELECT_PORT(port);
1979 tmp = intel_de_read(dev_priv,
1980 TRANS_DDI_FUNC_CTL(cpu_transcoder));
1981 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
1984 if ((tmp & port_mask) != ddi_select)
1987 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1988 TRANS_DDI_MODE_SELECT_DP_MST)
1989 mst_pipe_mask |= BIT(p);
1991 *pipe_mask |= BIT(p);
1995 drm_dbg_kms(&dev_priv->drm,
1996 "No pipe for [ENCODER:%d:%s] found\n",
1997 encoder->base.base.id, encoder->base.name);
1999 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2000 drm_dbg_kms(&dev_priv->drm,
2001 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2002 encoder->base.base.id, encoder->base.name,
2004 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2007 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2008 drm_dbg_kms(&dev_priv->drm,
2009 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2010 encoder->base.base.id, encoder->base.name,
2011 *pipe_mask, mst_pipe_mask);
2013 *is_dp_mst = mst_pipe_mask;
2016 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2017 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
2018 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2019 BXT_PHY_LANE_POWERDOWN_ACK |
2020 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2021 drm_err(&dev_priv->drm,
2022 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
2023 encoder->base.base.id, encoder->base.name, tmp);
2026 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2029 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2035 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2037 if (is_mst || !pipe_mask)
2040 *pipe = ffs(pipe_mask) - 1;
2045 static enum intel_display_power_domain
2046 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2048 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2049 * DC states enabled at the same time, while for driver initiated AUX
2050 * transfers we need the same AUX IOs to be powered but with DC states
2051 * disabled. Accordingly use the AUX power domain here which leaves DC
2053 * However, for non-A AUX ports the corresponding non-EDP transcoders
2054 * would have already enabled power well 2 and DC_OFF. This means we can
2055 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2056 * specific AUX_IO reference without powering up any extra wells.
2057 * Note that PSR is enabled only on Port A even though this function
2058 * returns the correct domain for other ports too.
2060 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2061 intel_aux_power_domain(dig_port);
2064 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2065 struct intel_crtc_state *crtc_state)
2067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2068 struct intel_digital_port *dig_port;
2069 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2072 * TODO: Add support for MST encoders. Atm, the following should never
2073 * happen since fake-MST encoders don't set their get_power_domains()
2076 if (drm_WARN_ON(&dev_priv->drm,
2077 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2080 dig_port = enc_to_dig_port(encoder);
2082 if (!intel_phy_is_tc(dev_priv, phy) ||
2083 dig_port->tc_mode != TC_PORT_TBT_ALT)
2084 intel_display_power_get(dev_priv,
2085 dig_port->ddi_io_power_domain);
2088 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2091 if (intel_crtc_has_dp_encoder(crtc_state) ||
2092 intel_phy_is_tc(dev_priv, phy))
2093 intel_display_power_get(dev_priv,
2094 intel_ddi_main_link_aux_domain(dig_port));
2097 * VDSC power is needed when DSC is enabled
2099 if (crtc_state->dsc.compression_enable)
2100 intel_display_power_get(dev_priv,
2101 intel_dsc_power_domain(crtc_state));
2104 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
2105 const struct intel_crtc_state *crtc_state)
2107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2109 enum port port = encoder->port;
2110 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2112 if (cpu_transcoder != TRANSCODER_EDP) {
2113 if (INTEL_GEN(dev_priv) >= 12)
2114 intel_de_write(dev_priv,
2115 TRANS_CLK_SEL(cpu_transcoder),
2116 TGL_TRANS_CLK_SEL_PORT(port));
2118 intel_de_write(dev_priv,
2119 TRANS_CLK_SEL(cpu_transcoder),
2120 TRANS_CLK_SEL_PORT(port));
2124 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2126 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2127 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2129 if (cpu_transcoder != TRANSCODER_EDP) {
2130 if (INTEL_GEN(dev_priv) >= 12)
2131 intel_de_write(dev_priv,
2132 TRANS_CLK_SEL(cpu_transcoder),
2133 TGL_TRANS_CLK_SEL_DISABLED);
2135 intel_de_write(dev_priv,
2136 TRANS_CLK_SEL(cpu_transcoder),
2137 TRANS_CLK_SEL_DISABLED);
2141 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2142 enum port port, u8 iboost)
2146 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2147 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2149 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2151 tmp |= BALANCE_LEG_DISABLE(port);
2152 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2155 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2156 int level, enum intel_output_type type)
2158 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2159 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2162 if (type == INTEL_OUTPUT_HDMI)
2163 iboost = intel_bios_hdmi_boost_level(encoder);
2165 iboost = intel_bios_dp_boost_level(encoder);
2168 const struct ddi_buf_trans *ddi_translations;
2171 if (type == INTEL_OUTPUT_HDMI)
2172 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
2173 else if (type == INTEL_OUTPUT_EDP)
2174 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
2177 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
2180 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2182 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2183 level = n_entries - 1;
2185 iboost = ddi_translations[level].i_boost;
2188 /* Make sure that the requested I_boost is valid */
2189 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2190 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2194 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
2196 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
2197 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2200 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2201 int level, enum intel_output_type type)
2203 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2204 const struct bxt_ddi_buf_trans *ddi_translations;
2205 enum port port = encoder->port;
2208 if (type == INTEL_OUTPUT_HDMI)
2209 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
2210 else if (type == INTEL_OUTPUT_EDP)
2211 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
2213 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
2215 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2217 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2218 level = n_entries - 1;
2220 bxt_ddi_phy_set_signal_level(dev_priv, port,
2221 ddi_translations[level].margin,
2222 ddi_translations[level].scale,
2223 ddi_translations[level].enable,
2224 ddi_translations[level].deemphasis);
2227 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
2229 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2230 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2231 enum port port = encoder->port;
2232 enum phy phy = intel_port_to_phy(dev_priv, port);
2235 if (INTEL_GEN(dev_priv) >= 12) {
2236 if (intel_phy_is_combo(dev_priv, phy))
2237 tgl_get_combo_buf_trans(encoder, encoder->type,
2238 intel_dp->link_rate, &n_entries);
2240 tgl_get_dkl_buf_trans(encoder, encoder->type,
2241 intel_dp->link_rate, &n_entries);
2242 } else if (INTEL_GEN(dev_priv) == 11) {
2243 if (IS_ELKHARTLAKE(dev_priv))
2244 ehl_get_combo_buf_trans(encoder, encoder->type,
2245 intel_dp->link_rate, &n_entries);
2246 else if (intel_phy_is_combo(dev_priv, phy))
2247 icl_get_combo_buf_trans(encoder, encoder->type,
2248 intel_dp->link_rate, &n_entries);
2250 icl_get_mg_buf_trans(encoder, encoder->type,
2251 intel_dp->link_rate, &n_entries);
2252 } else if (IS_CANNONLAKE(dev_priv)) {
2253 if (encoder->type == INTEL_OUTPUT_EDP)
2254 cnl_get_buf_trans_edp(encoder, &n_entries);
2256 cnl_get_buf_trans_dp(encoder, &n_entries);
2257 } else if (IS_GEN9_LP(dev_priv)) {
2258 if (encoder->type == INTEL_OUTPUT_EDP)
2259 bxt_get_buf_trans_edp(encoder, &n_entries);
2261 bxt_get_buf_trans_dp(encoder, &n_entries);
2263 if (encoder->type == INTEL_OUTPUT_EDP)
2264 intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2266 intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2269 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2271 if (drm_WARN_ON(&dev_priv->drm,
2272 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2273 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2275 return index_to_dp_signal_levels[n_entries - 1] &
2276 DP_TRAIN_VOLTAGE_SWING_MASK;
2280 * We assume that the full set of pre-emphasis values can be
2281 * used on all DDI platforms. Should that change we need to
2282 * rethink this code.
2284 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
2286 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2289 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2290 int level, enum intel_output_type type)
2292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2293 const struct cnl_ddi_buf_trans *ddi_translations;
2294 enum port port = encoder->port;
2298 if (type == INTEL_OUTPUT_HDMI)
2299 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
2300 else if (type == INTEL_OUTPUT_EDP)
2301 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
2303 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
2305 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2307 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2308 level = n_entries - 1;
2310 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2311 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2312 val &= ~SCALING_MODE_SEL_MASK;
2313 val |= SCALING_MODE_SEL(2);
2314 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2316 /* Program PORT_TX_DW2 */
2317 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2318 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2320 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2321 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2322 /* Rcomp scalar is fixed as 0x98 for every table entry */
2323 val |= RCOMP_SCALAR(0x98);
2324 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2326 /* Program PORT_TX_DW4 */
2327 /* We cannot write to GRP. It would overrite individual loadgen */
2328 for (ln = 0; ln < 4; ln++) {
2329 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2330 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2332 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2333 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2334 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2335 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2338 /* Program PORT_TX_DW5 */
2339 /* All DW5 values are fixed for every table entry */
2340 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2341 val &= ~RTERM_SELECT_MASK;
2342 val |= RTERM_SELECT(6);
2343 val |= TAP3_DISABLE;
2344 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2346 /* Program PORT_TX_DW7 */
2347 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2348 val &= ~N_SCALAR_MASK;
2349 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2350 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2353 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2354 int level, enum intel_output_type type)
2356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2357 enum port port = encoder->port;
2358 int width, rate, ln;
2361 if (type == INTEL_OUTPUT_HDMI) {
2363 rate = 0; /* Rate is always < than 6GHz for HDMI */
2365 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2367 width = intel_dp->lane_count;
2368 rate = intel_dp->link_rate;
2372 * 1. If port type is eDP or DP,
2373 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2376 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2377 if (type != INTEL_OUTPUT_HDMI)
2378 val |= COMMON_KEEPER_EN;
2380 val &= ~COMMON_KEEPER_EN;
2381 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2383 /* 2. Program loadgen select */
2385 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2386 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2387 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2388 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2390 for (ln = 0; ln <= 3; ln++) {
2391 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2392 val &= ~LOADGEN_SELECT;
2394 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2395 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2396 val |= LOADGEN_SELECT;
2398 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2401 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2402 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2403 val |= SUS_CLOCK_CONFIG;
2404 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2406 /* 4. Clear training enable to change swing values */
2407 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2408 val &= ~TX_TRAINING_EN;
2409 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2411 /* 5. Program swing and de-emphasis */
2412 cnl_ddi_vswing_program(encoder, level, type);
2414 /* 6. Set training enable to trigger update */
2415 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2416 val |= TX_TRAINING_EN;
2417 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2420 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
2421 u32 level, int type, int rate)
2423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2424 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2425 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2429 if (INTEL_GEN(dev_priv) >= 12)
2430 ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
2432 else if (IS_ELKHARTLAKE(dev_priv))
2433 ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
2436 ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
2438 if (!ddi_translations)
2441 if (level >= n_entries) {
2442 drm_dbg_kms(&dev_priv->drm,
2443 "DDI translation not found for level %d. Using %d instead.",
2444 level, n_entries - 1);
2445 level = n_entries - 1;
2448 if (type == INTEL_OUTPUT_EDP) {
2449 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2451 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
2452 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
2453 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
2454 intel_dp->hobl_active ? val : 0);
2457 /* Set PORT_TX_DW5 */
2458 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2459 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2460 TAP2_DISABLE | TAP3_DISABLE);
2461 val |= SCALING_MODE_SEL(0x2);
2462 val |= RTERM_SELECT(0x6);
2463 val |= TAP3_DISABLE;
2464 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2466 /* Program PORT_TX_DW2 */
2467 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2468 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2470 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2471 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2472 /* Program Rcomp scalar for every table entry */
2473 val |= RCOMP_SCALAR(0x98);
2474 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2476 /* Program PORT_TX_DW4 */
2477 /* We cannot write to GRP. It would overwrite individual loadgen. */
2478 for (ln = 0; ln <= 3; ln++) {
2479 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2480 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2482 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2483 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2484 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2485 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2488 /* Program PORT_TX_DW7 */
2489 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2490 val &= ~N_SCALAR_MASK;
2491 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2492 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2495 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2497 enum intel_output_type type)
2499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2500 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2506 if (type == INTEL_OUTPUT_HDMI) {
2508 /* Rate is always < than 6GHz for HDMI */
2510 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2512 width = intel_dp->lane_count;
2513 rate = intel_dp->link_rate;
2517 * 1. If port type is eDP or DP,
2518 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2521 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2522 if (type == INTEL_OUTPUT_HDMI)
2523 val &= ~COMMON_KEEPER_EN;
2525 val |= COMMON_KEEPER_EN;
2526 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2528 /* 2. Program loadgen select */
2530 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2531 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2532 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2533 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2535 for (ln = 0; ln <= 3; ln++) {
2536 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2537 val &= ~LOADGEN_SELECT;
2539 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2540 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2541 val |= LOADGEN_SELECT;
2543 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2546 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2547 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2548 val |= SUS_CLOCK_CONFIG;
2549 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2551 /* 4. Clear training enable to change swing values */
2552 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2553 val &= ~TX_TRAINING_EN;
2554 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2556 /* 5. Program swing and de-emphasis */
2557 icl_ddi_combo_vswing_program(encoder, level, type, rate);
2559 /* 6. Set training enable to trigger update */
2560 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2561 val |= TX_TRAINING_EN;
2562 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2565 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2566 int link_clock, u32 level,
2567 enum intel_output_type type)
2569 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2570 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2571 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2575 if (type != INTEL_OUTPUT_HDMI) {
2576 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2578 rate = intel_dp->link_rate;
2581 ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
2583 /* The table does not have values for level 3 and level 9. */
2584 if (level >= n_entries || level == 3 || level == 9) {
2585 drm_dbg_kms(&dev_priv->drm,
2586 "DDI translation not found for level %d. Using %d instead.",
2587 level, n_entries - 2);
2588 level = n_entries - 2;
2591 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2592 for (ln = 0; ln < 2; ln++) {
2593 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2594 val &= ~CRI_USE_FS32;
2595 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2597 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2598 val &= ~CRI_USE_FS32;
2599 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2602 /* Program MG_TX_SWINGCTRL with values from vswing table */
2603 for (ln = 0; ln < 2; ln++) {
2604 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2605 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2606 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2607 ddi_translations[level].cri_txdeemph_override_17_12);
2608 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2610 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2611 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2612 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2613 ddi_translations[level].cri_txdeemph_override_17_12);
2614 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2617 /* Program MG_TX_DRVCTRL with values from vswing table */
2618 for (ln = 0; ln < 2; ln++) {
2619 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2620 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2621 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2622 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2623 ddi_translations[level].cri_txdeemph_override_5_0) |
2624 CRI_TXDEEMPH_OVERRIDE_11_6(
2625 ddi_translations[level].cri_txdeemph_override_11_6) |
2626 CRI_TXDEEMPH_OVERRIDE_EN;
2627 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2629 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2630 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2631 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2632 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2633 ddi_translations[level].cri_txdeemph_override_5_0) |
2634 CRI_TXDEEMPH_OVERRIDE_11_6(
2635 ddi_translations[level].cri_txdeemph_override_11_6) |
2636 CRI_TXDEEMPH_OVERRIDE_EN;
2637 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2639 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2643 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2644 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2645 * values from table for which TX1 and TX2 enabled.
2647 for (ln = 0; ln < 2; ln++) {
2648 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2649 if (link_clock < 300000)
2650 val |= CFG_LOW_RATE_LKREN_EN;
2652 val &= ~CFG_LOW_RATE_LKREN_EN;
2653 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2656 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2657 for (ln = 0; ln < 2; ln++) {
2658 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2659 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2660 if (link_clock <= 500000) {
2661 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2663 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2664 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2666 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2668 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2669 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2670 if (link_clock <= 500000) {
2671 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2673 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2674 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2676 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2679 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2680 for (ln = 0; ln < 2; ln++) {
2681 val = intel_de_read(dev_priv,
2682 MG_TX1_PISO_READLOAD(ln, tc_port));
2683 val |= CRI_CALCINIT;
2684 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2687 val = intel_de_read(dev_priv,
2688 MG_TX2_PISO_READLOAD(ln, tc_port));
2689 val |= CRI_CALCINIT;
2690 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2695 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2698 enum intel_output_type type)
2700 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2701 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2703 if (intel_phy_is_combo(dev_priv, phy))
2704 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2706 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
2711 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2712 u32 level, enum intel_output_type type)
2714 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2715 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2716 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2717 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2720 if (type == INTEL_OUTPUT_HDMI) {
2721 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2723 rate = intel_dp->link_rate;
2726 ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
2729 if (level >= n_entries)
2730 level = n_entries - 1;
2732 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2733 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2734 DKL_TX_VSWING_CONTROL_MASK);
2735 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2736 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2737 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2739 for (ln = 0; ln < 2; ln++) {
2740 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2741 HIP_INDEX_VAL(tc_port, ln));
2743 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2745 /* All the registers are RMW */
2746 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2749 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2751 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2754 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2756 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2757 val &= ~DKL_TX_DP20BITMODE;
2758 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2762 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2765 enum intel_output_type type)
2767 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2768 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2770 if (intel_phy_is_combo(dev_priv, phy))
2771 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2773 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
2776 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
2778 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2781 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2782 if (index_to_dp_signal_levels[i] == signal_levels)
2786 drm_WARN(&i915->drm, 1,
2787 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2793 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2795 u8 train_set = intel_dp->train_set[0];
2796 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2797 DP_TRAIN_PRE_EMPHASIS_MASK);
2799 return translate_signal_level(intel_dp, signal_levels);
2803 tgl_set_signal_levels(struct intel_dp *intel_dp)
2805 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2806 int level = intel_ddi_dp_level(intel_dp);
2808 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2809 level, encoder->type);
2813 icl_set_signal_levels(struct intel_dp *intel_dp)
2815 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2816 int level = intel_ddi_dp_level(intel_dp);
2818 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2819 level, encoder->type);
2823 cnl_set_signal_levels(struct intel_dp *intel_dp)
2825 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2826 int level = intel_ddi_dp_level(intel_dp);
2828 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2832 bxt_set_signal_levels(struct intel_dp *intel_dp)
2834 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2835 int level = intel_ddi_dp_level(intel_dp);
2837 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2841 hsw_set_signal_levels(struct intel_dp *intel_dp)
2843 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2844 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2845 int level = intel_ddi_dp_level(intel_dp);
2846 enum port port = encoder->port;
2849 signal_levels = DDI_BUF_TRANS_SELECT(level);
2851 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
2854 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
2855 intel_dp->DP |= signal_levels;
2857 if (IS_GEN9_BC(dev_priv))
2858 skl_ddi_set_iboost(encoder, level, encoder->type);
2860 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
2861 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
2864 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2867 if (IS_ROCKETLAKE(dev_priv)) {
2868 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2869 } else if (intel_phy_is_combo(dev_priv, phy)) {
2870 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2871 } else if (intel_phy_is_tc(dev_priv, phy)) {
2872 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2875 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2881 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2882 const struct intel_crtc_state *crtc_state)
2884 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2885 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2886 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2889 mutex_lock(&dev_priv->dpll.lock);
2891 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2892 drm_WARN_ON(&dev_priv->drm,
2893 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2895 if (intel_phy_is_combo(dev_priv, phy)) {
2898 if (IS_ROCKETLAKE(dev_priv)) {
2899 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2900 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2902 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2903 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2907 * Even though this register references DDIs, note that we
2908 * want to pass the PHY rather than the port (DDI). For
2909 * ICL, port=phy in all cases so it doesn't matter, but for
2910 * EHL the bspec notes the following:
2912 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2913 * Clock Select chooses the PLL for both DDIA and DDID and
2914 * drives port A in all cases."
2918 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2919 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
2922 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2923 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2925 mutex_unlock(&dev_priv->dpll.lock);
2928 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2930 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2931 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2934 mutex_lock(&dev_priv->dpll.lock);
2936 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2937 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2938 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2940 mutex_unlock(&dev_priv->dpll.lock);
2943 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
2944 u32 port_mask, bool ddi_clk_needed)
2949 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2950 for_each_port_masked(port, port_mask) {
2951 enum phy phy = intel_port_to_phy(dev_priv, port);
2952 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
2955 if (ddi_clk_needed == !ddi_clk_off)
2959 * Punt on the case now where clock is gated, but it would
2960 * be needed by the port. Something else is really broken then.
2962 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
2965 drm_notice(&dev_priv->drm,
2966 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2968 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2969 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2973 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2977 bool ddi_clk_needed;
2980 * In case of DP MST, we sanitize the primary encoder only, not the
2983 if (encoder->type == INTEL_OUTPUT_DP_MST)
2986 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2990 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2992 * In the unlikely case that BIOS enables DP in MST mode, just
2993 * warn since our MST HW readout is incomplete.
2995 if (drm_WARN_ON(&dev_priv->drm, is_mst))
2999 port_mask = BIT(encoder->port);
3000 ddi_clk_needed = encoder->base.crtc;
3002 if (encoder->type == INTEL_OUTPUT_DSI) {
3003 struct intel_encoder *other_encoder;
3005 port_mask = intel_dsi_encoder_ports(encoder);
3007 * Sanity check that we haven't incorrectly registered another
3008 * encoder using any of the ports of this DSI encoder.
3010 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3011 if (other_encoder == encoder)
3014 if (drm_WARN_ON(&dev_priv->drm,
3015 port_mask & BIT(other_encoder->port)))
3019 * For DSI we keep the ddi clocks gated
3020 * except during enable/disable sequence.
3022 ddi_clk_needed = false;
3025 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3028 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3029 const struct intel_crtc_state *crtc_state)
3031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3032 enum port port = encoder->port;
3033 enum phy phy = intel_port_to_phy(dev_priv, port);
3035 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3037 if (drm_WARN_ON(&dev_priv->drm, !pll))
3040 mutex_lock(&dev_priv->dpll.lock);
3042 if (INTEL_GEN(dev_priv) >= 11) {
3043 if (!intel_phy_is_combo(dev_priv, phy))
3044 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3045 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3046 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3048 * MG does not exist but the programming is required
3049 * to ungate DDIC and DDID
3051 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3053 } else if (IS_CANNONLAKE(dev_priv)) {
3054 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3055 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3056 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3057 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3058 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3061 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3062 * This step and the step before must be done with separate
3065 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3066 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3067 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3068 } else if (IS_GEN9_BC(dev_priv)) {
3069 /* DDI -> PLL mapping */
3070 val = intel_de_read(dev_priv, DPLL_CTRL2);
3072 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3073 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3074 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3075 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3077 intel_de_write(dev_priv, DPLL_CTRL2, val);
3079 } else if (INTEL_GEN(dev_priv) < 9) {
3080 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3081 hsw_pll_to_ddi_pll_sel(pll));
3084 mutex_unlock(&dev_priv->dpll.lock);
3087 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3089 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3090 enum port port = encoder->port;
3091 enum phy phy = intel_port_to_phy(dev_priv, port);
3093 if (INTEL_GEN(dev_priv) >= 11) {
3094 if (!intel_phy_is_combo(dev_priv, phy) ||
3095 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3096 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3098 } else if (IS_CANNONLAKE(dev_priv)) {
3099 intel_de_write(dev_priv, DPCLKA_CFGCR0,
3100 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3101 } else if (IS_GEN9_BC(dev_priv)) {
3102 intel_de_write(dev_priv, DPLL_CTRL2,
3103 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
3104 } else if (INTEL_GEN(dev_priv) < 9) {
3105 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3111 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
3112 const struct intel_crtc_state *crtc_state)
3114 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3115 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3116 u32 ln0, ln1, pin_assignment;
3119 if (dig_port->tc_mode == TC_PORT_TBT_ALT)
3122 if (INTEL_GEN(dev_priv) >= 12) {
3123 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3124 HIP_INDEX_VAL(tc_port, 0x0));
3125 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3126 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3127 HIP_INDEX_VAL(tc_port, 0x1));
3128 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3130 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
3131 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
3134 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3135 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3138 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
3139 width = crtc_state->lane_count;
3141 switch (pin_assignment) {
3143 drm_WARN_ON(&dev_priv->drm,
3144 dig_port->tc_mode != TC_PORT_LEGACY);
3146 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3148 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3149 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3154 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3155 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3160 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3161 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3167 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3168 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3170 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3171 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3177 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3178 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3180 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3181 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3185 MISSING_CASE(pin_assignment);
3188 if (INTEL_GEN(dev_priv) >= 12) {
3189 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3190 HIP_INDEX_VAL(tc_port, 0x0));
3191 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3192 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3193 HIP_INDEX_VAL(tc_port, 0x1));
3194 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3196 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3197 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3201 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3202 const struct intel_crtc_state *crtc_state)
3204 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3206 if (!crtc_state->fec_enable)
3209 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3210 drm_dbg_kms(&i915->drm,
3211 "Failed to set FEC_READY in the sink\n");
3214 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3215 const struct intel_crtc_state *crtc_state)
3217 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3218 struct intel_dp *intel_dp;
3221 if (!crtc_state->fec_enable)
3224 intel_dp = enc_to_intel_dp(encoder);
3225 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3226 val |= DP_TP_CTL_FEC_ENABLE;
3227 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3229 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3230 DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3231 drm_err(&dev_priv->drm,
3232 "Timed out waiting for FEC Enable Status\n");
3235 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3236 const struct intel_crtc_state *crtc_state)
3238 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3239 struct intel_dp *intel_dp;
3242 if (!crtc_state->fec_enable)
3245 intel_dp = enc_to_intel_dp(encoder);
3246 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3247 val &= ~DP_TP_CTL_FEC_ENABLE;
3248 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3249 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3252 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3253 struct intel_encoder *encoder,
3254 const struct intel_crtc_state *crtc_state,
3255 const struct drm_connector_state *conn_state)
3257 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3259 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3260 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3261 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3262 int level = intel_ddi_dp_level(intel_dp);
3263 enum transcoder transcoder = crtc_state->cpu_transcoder;
3265 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3266 crtc_state->lane_count, is_mst);
3268 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3269 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3272 * 1. Enable Power Wells
3274 * This was handled at the beginning of intel_atomic_commit_tail(),
3275 * before we called down into this function.
3278 /* 2. Enable Panel Power if PPS is required */
3279 intel_edp_panel_on(intel_dp);
3282 * 3. For non-TBT Type-C ports, set FIA lane count
3283 * (DFLEXDPSP.DPX4TXLATC)
3285 * This was done before tgl_ddi_pre_enable_dp by
3286 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3290 * 4. Enable the port PLL.
3292 * The PLL enabling itself was already done before this function by
3293 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
3294 * configure the PLL to port mapping here.
3296 intel_ddi_clk_select(encoder, crtc_state);
3298 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3299 if (!intel_phy_is_tc(dev_priv, phy) ||
3300 dig_port->tc_mode != TC_PORT_TBT_ALT)
3301 intel_display_power_get(dev_priv,
3302 dig_port->ddi_io_power_domain);
3304 /* 6. Program DP_MODE */
3305 icl_program_mg_dp_mode(dig_port, crtc_state);
3308 * 7. The rest of the below are substeps under the bspec's "Enable and
3309 * Train Display Port" step. Note that steps that are specific to
3310 * MST will be handled by intel_mst_pre_enable_dp() before/after it
3311 * calls into this function. Also intel_mst_pre_enable_dp() only calls
3312 * us when active_mst_links==0, so any steps designated for "single
3313 * stream or multi-stream master transcoder" can just be performed
3314 * unconditionally here.
3318 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3321 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3324 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3327 intel_ddi_config_transcoder_func(encoder, crtc_state);
3330 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3333 * This will be handled by the intel_dp_start_link_train() farther
3334 * down this function.
3337 /* 7.e Configure voltage swing and related IO settings */
3338 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3342 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3343 * the used lanes of the DDI.
3345 if (intel_phy_is_combo(dev_priv, phy)) {
3346 bool lane_reversal =
3347 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3349 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3350 crtc_state->lane_count,
3355 * 7.g Configure and enable DDI_BUF_CTL
3356 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3359 * We only configure what the register value will be here. Actual
3360 * enabling happens during link training farther down.
3362 intel_ddi_init_dp_buf_reg(encoder);
3365 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3367 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3369 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3370 * in the FEC_CONFIGURATION register to 1 before initiating link
3373 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3376 * 7.i Follow DisplayPort specification training sequence (see notes for
3378 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3379 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3380 * (timeout after 800 us)
3382 intel_dp_start_link_train(intel_dp);
3384 /* 7.k Set DP_TP_CTL link training to Normal */
3385 if (!is_trans_port_sync_mode(crtc_state))
3386 intel_dp_stop_link_train(intel_dp);
3388 /* 7.l Configure and enable FEC if needed */
3389 intel_ddi_enable_fec(encoder, crtc_state);
3390 intel_dsc_enable(encoder, crtc_state);
3393 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3394 struct intel_encoder *encoder,
3395 const struct intel_crtc_state *crtc_state,
3396 const struct drm_connector_state *conn_state)
3398 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3400 enum port port = encoder->port;
3401 enum phy phy = intel_port_to_phy(dev_priv, port);
3402 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3403 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3404 int level = intel_ddi_dp_level(intel_dp);
3406 if (INTEL_GEN(dev_priv) < 11)
3407 drm_WARN_ON(&dev_priv->drm,
3408 is_mst && (port == PORT_A || port == PORT_E));
3410 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3412 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3413 crtc_state->lane_count, is_mst);
3415 intel_edp_panel_on(intel_dp);
3417 intel_ddi_clk_select(encoder, crtc_state);
3419 if (!intel_phy_is_tc(dev_priv, phy) ||
3420 dig_port->tc_mode != TC_PORT_TBT_ALT)
3421 intel_display_power_get(dev_priv,
3422 dig_port->ddi_io_power_domain);
3424 icl_program_mg_dp_mode(dig_port, crtc_state);
3426 if (INTEL_GEN(dev_priv) >= 11)
3427 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3428 level, encoder->type);
3429 else if (IS_CANNONLAKE(dev_priv))
3430 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3431 else if (IS_GEN9_LP(dev_priv))
3432 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3434 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3436 if (intel_phy_is_combo(dev_priv, phy)) {
3437 bool lane_reversal =
3438 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3440 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3441 crtc_state->lane_count,
3445 intel_ddi_init_dp_buf_reg(encoder);
3447 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3448 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3450 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3451 intel_dp_start_link_train(intel_dp);
3452 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3453 !is_trans_port_sync_mode(crtc_state))
3454 intel_dp_stop_link_train(intel_dp);
3456 intel_ddi_enable_fec(encoder, crtc_state);
3459 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3461 intel_dsc_enable(encoder, crtc_state);
3464 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3465 struct intel_encoder *encoder,
3466 const struct intel_crtc_state *crtc_state,
3467 const struct drm_connector_state *conn_state)
3469 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3471 if (INTEL_GEN(dev_priv) >= 12)
3472 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3474 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3476 /* MST will call a setting of MSA after an allocating of Virtual Channel
3477 * from MST encoder pre_enable callback.
3479 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3480 intel_ddi_set_dp_msa(crtc_state, conn_state);
3482 intel_dp_set_m_n(crtc_state, M1_N1);
3486 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3487 struct intel_encoder *encoder,
3488 const struct intel_crtc_state *crtc_state,
3489 const struct drm_connector_state *conn_state)
3491 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3492 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3494 int level = intel_ddi_hdmi_level(encoder);
3496 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3497 intel_ddi_clk_select(encoder, crtc_state);
3499 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3501 icl_program_mg_dp_mode(dig_port, crtc_state);
3503 if (INTEL_GEN(dev_priv) >= 12)
3504 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3505 level, INTEL_OUTPUT_HDMI);
3506 else if (INTEL_GEN(dev_priv) == 11)
3507 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3508 level, INTEL_OUTPUT_HDMI);
3509 else if (IS_CANNONLAKE(dev_priv))
3510 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3511 else if (IS_GEN9_LP(dev_priv))
3512 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3514 intel_prepare_hdmi_ddi_buffers(encoder, level);
3516 if (IS_GEN9_BC(dev_priv))
3517 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3519 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3521 dig_port->set_infoframes(encoder,
3522 crtc_state->has_infoframe,
3523 crtc_state, conn_state);
3526 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3527 struct intel_encoder *encoder,
3528 const struct intel_crtc_state *crtc_state,
3529 const struct drm_connector_state *conn_state)
3531 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3533 enum pipe pipe = crtc->pipe;
3536 * When called from DP MST code:
3537 * - conn_state will be NULL
3538 * - encoder will be the main encoder (ie. mst->primary)
3539 * - the main connector associated with this port
3540 * won't be active or linked to a crtc
3541 * - crtc_state will be the state of the first stream to
3542 * be activated on this port, and it may not be the same
3543 * stream that will be deactivated last, but each stream
3544 * should have a state that is identical when it comes to
3545 * the DP link parameteres
3548 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3550 if (INTEL_GEN(dev_priv) >= 11)
3551 icl_map_plls_to_ports(encoder, crtc_state);
3553 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3555 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3556 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3559 struct intel_lspcon *lspcon =
3560 enc_to_intel_lspcon(encoder);
3562 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3564 if (lspcon->active) {
3565 struct intel_digital_port *dig_port =
3566 enc_to_dig_port(encoder);
3568 dig_port->set_infoframes(encoder,
3569 crtc_state->has_infoframe,
3570 crtc_state, conn_state);
3575 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3576 const struct intel_crtc_state *crtc_state)
3578 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3579 enum port port = encoder->port;
3583 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3584 if (val & DDI_BUF_CTL_ENABLE) {
3585 val &= ~DDI_BUF_CTL_ENABLE;
3586 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3590 if (intel_crtc_has_dp_encoder(crtc_state)) {
3591 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3593 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3594 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3595 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3596 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3599 /* Disable FEC in DP Sink */
3600 intel_ddi_disable_fec_state(encoder, crtc_state);
3603 intel_wait_ddi_buf_idle(dev_priv, port);
3606 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3607 struct intel_encoder *encoder,
3608 const struct intel_crtc_state *old_crtc_state,
3609 const struct drm_connector_state *old_conn_state)
3611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3612 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3613 struct intel_dp *intel_dp = &dig_port->dp;
3614 bool is_mst = intel_crtc_has_type(old_crtc_state,
3615 INTEL_OUTPUT_DP_MST);
3616 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3619 intel_dp_set_infoframes(encoder, false,
3620 old_crtc_state, old_conn_state);
3623 * Power down sink before disabling the port, otherwise we end
3624 * up getting interrupts from the sink on detecting link loss.
3626 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3628 if (INTEL_GEN(dev_priv) >= 12) {
3630 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3633 val = intel_de_read(dev_priv,
3634 TRANS_DDI_FUNC_CTL(cpu_transcoder));
3635 val &= ~(TGL_TRANS_DDI_PORT_MASK |
3636 TRANS_DDI_MODE_SELECT_MASK);
3637 intel_de_write(dev_priv,
3638 TRANS_DDI_FUNC_CTL(cpu_transcoder),
3643 intel_ddi_disable_pipe_clock(old_crtc_state);
3646 intel_disable_ddi_buf(encoder, old_crtc_state);
3649 * From TGL spec: "If single stream or multi-stream master transcoder:
3650 * Configure Transcoder Clock select to direct no clock to the
3653 if (INTEL_GEN(dev_priv) >= 12)
3654 intel_ddi_disable_pipe_clock(old_crtc_state);
3656 intel_edp_panel_vdd_on(intel_dp);
3657 intel_edp_panel_off(intel_dp);
3659 if (!intel_phy_is_tc(dev_priv, phy) ||
3660 dig_port->tc_mode != TC_PORT_TBT_ALT)
3661 intel_display_power_put_unchecked(dev_priv,
3662 dig_port->ddi_io_power_domain);
3664 intel_ddi_clk_disable(encoder);
3667 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3668 struct intel_encoder *encoder,
3669 const struct intel_crtc_state *old_crtc_state,
3670 const struct drm_connector_state *old_conn_state)
3672 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3673 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3674 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3676 dig_port->set_infoframes(encoder, false,
3677 old_crtc_state, old_conn_state);
3679 intel_ddi_disable_pipe_clock(old_crtc_state);
3681 intel_disable_ddi_buf(encoder, old_crtc_state);
3683 intel_display_power_put_unchecked(dev_priv,
3684 dig_port->ddi_io_power_domain);
3686 intel_ddi_clk_disable(encoder);
3688 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3691 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3692 struct intel_encoder *encoder,
3693 const struct intel_crtc_state *old_crtc_state,
3694 const struct drm_connector_state *old_conn_state)
3696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3697 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3698 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3699 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3701 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3702 intel_crtc_vblank_off(old_crtc_state);
3704 intel_disable_pipe(old_crtc_state);
3706 intel_ddi_disable_transcoder_func(old_crtc_state);
3708 intel_dsc_disable(old_crtc_state);
3710 if (INTEL_GEN(dev_priv) >= 9)
3711 skl_scaler_disable(old_crtc_state);
3713 ilk_pfit_disable(old_crtc_state);
3717 * When called from DP MST code:
3718 * - old_conn_state will be NULL
3719 * - encoder will be the main encoder (ie. mst->primary)
3720 * - the main connector associated with this port
3721 * won't be active or linked to a crtc
3722 * - old_crtc_state will be the state of the last stream to
3723 * be deactivated on this port, and it may not be the same
3724 * stream that was activated last, but each stream
3725 * should have a state that is identical when it comes to
3726 * the DP link parameteres
3729 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3730 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3733 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3736 if (INTEL_GEN(dev_priv) >= 11)
3737 icl_unmap_plls_to_ports(encoder);
3739 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3740 intel_display_power_put_unchecked(dev_priv,
3741 intel_ddi_main_link_aux_domain(dig_port));
3744 intel_tc_port_put_link(dig_port);
3747 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
3748 struct intel_encoder *encoder,
3749 const struct intel_crtc_state *old_crtc_state,
3750 const struct drm_connector_state *old_conn_state)
3752 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3756 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3757 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3758 * step 13 is the correct place for it. Step 18 is where it was
3759 * originally before the BUN.
3761 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3762 val &= ~FDI_RX_ENABLE;
3763 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3765 intel_disable_ddi_buf(encoder, old_crtc_state);
3766 intel_ddi_clk_disable(encoder);
3768 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3769 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3770 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3771 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3773 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3775 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3777 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3778 val &= ~FDI_RX_PLL_ENABLE;
3779 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3782 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3783 struct intel_encoder *encoder,
3784 const struct intel_crtc_state *crtc_state)
3786 const struct drm_connector_state *conn_state;
3787 struct drm_connector *conn;
3790 if (!crtc_state->sync_mode_slaves_mask)
3793 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3794 struct intel_encoder *slave_encoder =
3795 to_intel_encoder(conn_state->best_encoder);
3796 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3797 const struct intel_crtc_state *slave_crtc_state;
3803 intel_atomic_get_new_crtc_state(state, slave_crtc);
3805 if (slave_crtc_state->master_transcoder !=
3806 crtc_state->cpu_transcoder)
3809 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
3812 usleep_range(200, 400);
3814 intel_dp_stop_link_train(enc_to_intel_dp(encoder));
3817 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3818 struct intel_encoder *encoder,
3819 const struct intel_crtc_state *crtc_state,
3820 const struct drm_connector_state *conn_state)
3822 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3823 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3824 enum port port = encoder->port;
3826 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3827 intel_dp_stop_link_train(intel_dp);
3829 intel_edp_backlight_on(crtc_state, conn_state);
3830 intel_psr_enable(intel_dp, crtc_state, conn_state);
3831 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3832 intel_edp_drrs_enable(intel_dp, crtc_state);
3834 if (crtc_state->has_audio)
3835 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3837 trans_port_sync_stop_link_train(state, encoder, crtc_state);
3841 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3844 static const enum transcoder trans[] = {
3845 [PORT_A] = TRANSCODER_EDP,
3846 [PORT_B] = TRANSCODER_A,
3847 [PORT_C] = TRANSCODER_B,
3848 [PORT_D] = TRANSCODER_C,
3849 [PORT_E] = TRANSCODER_A,
3852 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
3854 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3857 return CHICKEN_TRANS(trans[port]);
3860 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3861 struct intel_encoder *encoder,
3862 const struct intel_crtc_state *crtc_state,
3863 const struct drm_connector_state *conn_state)
3865 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3866 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3867 struct drm_connector *connector = conn_state->connector;
3868 enum port port = encoder->port;
3870 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3871 crtc_state->hdmi_high_tmds_clock_ratio,
3872 crtc_state->hdmi_scrambling))
3873 drm_dbg_kms(&dev_priv->drm,
3874 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3875 connector->base.id, connector->name);
3877 /* Display WA #1143: skl,kbl,cfl */
3878 if (IS_GEN9_BC(dev_priv)) {
3880 * For some reason these chicken bits have been
3881 * stuffed into a transcoder register, event though
3882 * the bits affect a specific DDI port rather than
3883 * a specific transcoder.
3885 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3888 val = intel_de_read(dev_priv, reg);
3891 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3892 DDIE_TRAINING_OVERRIDE_VALUE;
3894 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3895 DDI_TRAINING_OVERRIDE_VALUE;
3897 intel_de_write(dev_priv, reg, val);
3898 intel_de_posting_read(dev_priv, reg);
3903 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3904 DDIE_TRAINING_OVERRIDE_VALUE);
3906 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3907 DDI_TRAINING_OVERRIDE_VALUE);
3909 intel_de_write(dev_priv, reg, val);
3912 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3913 * are ignored so nothing special needs to be done besides
3914 * enabling the port.
3916 intel_de_write(dev_priv, DDI_BUF_CTL(port),
3917 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3919 if (crtc_state->has_audio)
3920 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3923 static void intel_enable_ddi(struct intel_atomic_state *state,
3924 struct intel_encoder *encoder,
3925 const struct intel_crtc_state *crtc_state,
3926 const struct drm_connector_state *conn_state)
3928 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3930 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3932 intel_enable_pipe(crtc_state);
3934 intel_crtc_vblank_on(crtc_state);
3936 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3937 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3939 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3941 /* Enable hdcp if it's desired */
3942 if (conn_state->content_protection ==
3943 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3944 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3945 crtc_state->cpu_transcoder,
3946 (u8)conn_state->hdcp_content_type);
3949 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3950 struct intel_encoder *encoder,
3951 const struct intel_crtc_state *old_crtc_state,
3952 const struct drm_connector_state *old_conn_state)
3954 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3956 intel_dp->link_trained = false;
3958 if (old_crtc_state->has_audio)
3959 intel_audio_codec_disable(encoder,
3960 old_crtc_state, old_conn_state);
3962 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3963 intel_psr_disable(intel_dp, old_crtc_state);
3964 intel_edp_backlight_off(old_conn_state);
3965 /* Disable the decompression in DP Sink */
3966 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3970 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3971 struct intel_encoder *encoder,
3972 const struct intel_crtc_state *old_crtc_state,
3973 const struct drm_connector_state *old_conn_state)
3975 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3976 struct drm_connector *connector = old_conn_state->connector;
3978 if (old_crtc_state->has_audio)
3979 intel_audio_codec_disable(encoder,
3980 old_crtc_state, old_conn_state);
3982 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3984 drm_dbg_kms(&i915->drm,
3985 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3986 connector->base.id, connector->name);
3989 static void intel_disable_ddi(struct intel_atomic_state *state,
3990 struct intel_encoder *encoder,
3991 const struct intel_crtc_state *old_crtc_state,
3992 const struct drm_connector_state *old_conn_state)
3994 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3996 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3997 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
4000 intel_disable_ddi_dp(state, encoder, old_crtc_state,
4004 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
4005 struct intel_encoder *encoder,
4006 const struct intel_crtc_state *crtc_state,
4007 const struct drm_connector_state *conn_state)
4009 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4011 intel_ddi_set_dp_msa(crtc_state, conn_state);
4013 intel_psr_update(intel_dp, crtc_state, conn_state);
4014 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
4015 intel_edp_drrs_enable(intel_dp, crtc_state);
4017 intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
4020 static void intel_ddi_update_pipe(struct intel_atomic_state *state,
4021 struct intel_encoder *encoder,
4022 const struct intel_crtc_state *crtc_state,
4023 const struct drm_connector_state *conn_state)
4026 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4027 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
4030 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
4034 intel_ddi_update_prepare(struct intel_atomic_state *state,
4035 struct intel_encoder *encoder,
4036 struct intel_crtc *crtc)
4038 struct intel_crtc_state *crtc_state =
4039 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4040 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4042 drm_WARN_ON(state->base.dev, crtc && crtc->active);
4044 intel_tc_port_get_link(enc_to_dig_port(encoder),
4046 if (crtc_state && crtc_state->hw.active)
4047 intel_update_active_dpll(state, crtc, encoder);
4051 intel_ddi_update_complete(struct intel_atomic_state *state,
4052 struct intel_encoder *encoder,
4053 struct intel_crtc *crtc)
4055 intel_tc_port_put_link(enc_to_dig_port(encoder));
4059 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
4060 struct intel_encoder *encoder,
4061 const struct intel_crtc_state *crtc_state,
4062 const struct drm_connector_state *conn_state)
4064 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4065 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4066 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4067 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4070 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4072 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4073 intel_display_power_get(dev_priv,
4074 intel_ddi_main_link_aux_domain(dig_port));
4076 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4078 * Program the lane count for static/dynamic connections on
4079 * Type-C ports. Skip this step for TBT.
4081 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4082 else if (IS_GEN9_LP(dev_priv))
4083 bxt_ddi_phy_set_lane_optim_mask(encoder,
4084 crtc_state->lane_lat_optim_mask);
4087 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4089 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4090 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4091 enum port port = dig_port->base.port;
4092 u32 dp_tp_ctl, ddi_buf_ctl;
4095 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4097 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4098 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
4099 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4100 intel_de_write(dev_priv, DDI_BUF_CTL(port),
4101 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4105 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4106 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4107 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4108 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4111 intel_wait_ddi_buf_idle(dev_priv, port);
4114 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
4115 if (intel_dp->link_mst)
4116 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4118 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4119 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4120 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4122 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4123 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4125 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4126 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
4127 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
4129 intel_wait_ddi_buf_active(dev_priv, port);
4132 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
4135 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4136 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
4139 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4141 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4142 switch (dp_train_pat & train_pat_mask) {
4143 case DP_TRAINING_PATTERN_DISABLE:
4144 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
4146 case DP_TRAINING_PATTERN_1:
4147 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
4149 case DP_TRAINING_PATTERN_2:
4150 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
4152 case DP_TRAINING_PATTERN_3:
4153 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
4155 case DP_TRAINING_PATTERN_4:
4156 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
4160 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
4163 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
4165 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4166 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4167 enum port port = encoder->port;
4170 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4171 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4172 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4173 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4176 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4177 * reason we need to set idle transmission mode is to work around a HW
4178 * issue where we enable the pipe while not in idle link-training mode.
4179 * In this case there is requirement to wait for a minimum number of
4180 * idle patterns to be sent.
4182 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4185 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4186 DP_TP_STATUS_IDLE_DONE, 1))
4187 drm_err(&dev_priv->drm,
4188 "Timed out waiting for DP idle patterns\n");
4191 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4192 enum transcoder cpu_transcoder)
4194 if (cpu_transcoder == TRANSCODER_EDP)
4197 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4200 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
4201 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4204 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4205 struct intel_crtc_state *crtc_state)
4207 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
4208 crtc_state->min_voltage_level = 2;
4209 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
4210 crtc_state->min_voltage_level = 3;
4211 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4212 crtc_state->min_voltage_level = 1;
4213 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4214 crtc_state->min_voltage_level = 2;
4217 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
4218 enum transcoder cpu_transcoder)
4222 if (INTEL_GEN(dev_priv) >= 11) {
4223 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4225 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4226 return INVALID_TRANSCODER;
4228 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4230 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4232 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4233 return INVALID_TRANSCODER;
4235 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4238 if (master_select == 0)
4239 return TRANSCODER_EDP;
4241 return master_select - 1;
4244 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4246 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4247 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4248 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4249 enum transcoder cpu_transcoder;
4251 crtc_state->master_transcoder =
4252 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4254 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4255 enum intel_display_power_domain power_domain;
4256 intel_wakeref_t trans_wakeref;
4258 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4259 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4265 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4266 crtc_state->cpu_transcoder)
4267 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4269 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4272 drm_WARN_ON(&dev_priv->drm,
4273 crtc_state->master_transcoder != INVALID_TRANSCODER &&
4274 crtc_state->sync_mode_slaves_mask);
4277 void intel_ddi_get_config(struct intel_encoder *encoder,
4278 struct intel_crtc_state *pipe_config)
4280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4281 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4282 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4283 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4284 u32 temp, flags = 0;
4286 /* XXX: DSI transcoder paranoia */
4287 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4290 intel_dsc_get_config(encoder, pipe_config);
4292 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4293 if (temp & TRANS_DDI_PHSYNC)
4294 flags |= DRM_MODE_FLAG_PHSYNC;
4296 flags |= DRM_MODE_FLAG_NHSYNC;
4297 if (temp & TRANS_DDI_PVSYNC)
4298 flags |= DRM_MODE_FLAG_PVSYNC;
4300 flags |= DRM_MODE_FLAG_NVSYNC;
4302 pipe_config->hw.adjusted_mode.flags |= flags;
4304 switch (temp & TRANS_DDI_BPC_MASK) {
4305 case TRANS_DDI_BPC_6:
4306 pipe_config->pipe_bpp = 18;
4308 case TRANS_DDI_BPC_8:
4309 pipe_config->pipe_bpp = 24;
4311 case TRANS_DDI_BPC_10:
4312 pipe_config->pipe_bpp = 30;
4314 case TRANS_DDI_BPC_12:
4315 pipe_config->pipe_bpp = 36;
4321 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4322 case TRANS_DDI_MODE_SELECT_HDMI:
4323 pipe_config->has_hdmi_sink = true;
4325 pipe_config->infoframes.enable |=
4326 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4328 if (pipe_config->infoframes.enable)
4329 pipe_config->has_infoframe = true;
4331 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4332 pipe_config->hdmi_scrambling = true;
4333 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4334 pipe_config->hdmi_high_tmds_clock_ratio = true;
4336 case TRANS_DDI_MODE_SELECT_DVI:
4337 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4338 pipe_config->lane_count = 4;
4340 case TRANS_DDI_MODE_SELECT_FDI:
4341 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4343 case TRANS_DDI_MODE_SELECT_DP_SST:
4344 if (encoder->type == INTEL_OUTPUT_EDP)
4345 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4347 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4348 pipe_config->lane_count =
4349 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4350 intel_dp_get_m_n(intel_crtc, pipe_config);
4352 if (INTEL_GEN(dev_priv) >= 11) {
4353 i915_reg_t dp_tp_ctl;
4355 if (IS_GEN(dev_priv, 11))
4356 dp_tp_ctl = DP_TP_CTL(encoder->port);
4358 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4360 pipe_config->fec_enable =
4361 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4363 drm_dbg_kms(&dev_priv->drm,
4364 "[ENCODER:%d:%s] Fec status: %u\n",
4365 encoder->base.base.id, encoder->base.name,
4366 pipe_config->fec_enable);
4369 pipe_config->infoframes.enable |=
4370 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4373 case TRANS_DDI_MODE_SELECT_DP_MST:
4374 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4375 pipe_config->lane_count =
4376 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4378 if (INTEL_GEN(dev_priv) >= 12)
4379 pipe_config->mst_master_transcoder =
4380 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4382 intel_dp_get_m_n(intel_crtc, pipe_config);
4384 pipe_config->infoframes.enable |=
4385 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4391 if (INTEL_GEN(dev_priv) >= 12) {
4392 enum transcoder transcoder =
4393 intel_dp_mst_is_slave_trans(pipe_config) ?
4394 pipe_config->mst_master_transcoder :
4395 pipe_config->cpu_transcoder;
4397 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
4398 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
4401 pipe_config->has_audio =
4402 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4404 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4405 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4407 * This is a big fat ugly hack.
4409 * Some machines in UEFI boot mode provide us a VBT that has 18
4410 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4411 * unknown we fail to light up. Yet the same BIOS boots up with
4412 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4413 * max, not what it tells us to use.
4415 * Note: This will still be broken if the eDP panel is not lit
4416 * up by the BIOS, and thus we can't get the mode at module
4419 drm_dbg_kms(&dev_priv->drm,
4420 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4421 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4422 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4425 intel_ddi_clock_get(encoder, pipe_config);
4427 if (IS_GEN9_LP(dev_priv))
4428 pipe_config->lane_lat_optim_mask =
4429 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4431 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4433 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4435 intel_read_infoframe(encoder, pipe_config,
4436 HDMI_INFOFRAME_TYPE_AVI,
4437 &pipe_config->infoframes.avi);
4438 intel_read_infoframe(encoder, pipe_config,
4439 HDMI_INFOFRAME_TYPE_SPD,
4440 &pipe_config->infoframes.spd);
4441 intel_read_infoframe(encoder, pipe_config,
4442 HDMI_INFOFRAME_TYPE_VENDOR,
4443 &pipe_config->infoframes.hdmi);
4444 intel_read_infoframe(encoder, pipe_config,
4445 HDMI_INFOFRAME_TYPE_DRM,
4446 &pipe_config->infoframes.drm);
4448 if (INTEL_GEN(dev_priv) >= 8)
4449 bdw_get_trans_port_sync_config(pipe_config);
4451 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4452 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4455 static enum intel_output_type
4456 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4457 struct intel_crtc_state *crtc_state,
4458 struct drm_connector_state *conn_state)
4460 switch (conn_state->connector->connector_type) {
4461 case DRM_MODE_CONNECTOR_HDMIA:
4462 return INTEL_OUTPUT_HDMI;
4463 case DRM_MODE_CONNECTOR_eDP:
4464 return INTEL_OUTPUT_EDP;
4465 case DRM_MODE_CONNECTOR_DisplayPort:
4466 return INTEL_OUTPUT_DP;
4468 MISSING_CASE(conn_state->connector->connector_type);
4469 return INTEL_OUTPUT_UNUSED;
4473 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4474 struct intel_crtc_state *pipe_config,
4475 struct drm_connector_state *conn_state)
4477 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4479 enum port port = encoder->port;
4482 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4483 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4485 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4486 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4488 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4494 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4495 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4496 pipe_config->pch_pfit.force_thru =
4497 pipe_config->pch_pfit.enabled ||
4498 pipe_config->crc_enabled;
4500 if (IS_GEN9_LP(dev_priv))
4501 pipe_config->lane_lat_optim_mask =
4502 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4504 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4509 static bool mode_equal(const struct drm_display_mode *mode1,
4510 const struct drm_display_mode *mode2)
4512 return drm_mode_match(mode1, mode2,
4513 DRM_MODE_MATCH_TIMINGS |
4514 DRM_MODE_MATCH_FLAGS |
4515 DRM_MODE_MATCH_3D_FLAGS) &&
4516 mode1->clock == mode2->clock; /* we want an exact match */
4519 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4520 const struct intel_link_m_n *m_n_2)
4522 return m_n_1->tu == m_n_2->tu &&
4523 m_n_1->gmch_m == m_n_2->gmch_m &&
4524 m_n_1->gmch_n == m_n_2->gmch_n &&
4525 m_n_1->link_m == m_n_2->link_m &&
4526 m_n_1->link_n == m_n_2->link_n;
4529 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4530 const struct intel_crtc_state *crtc_state2)
4532 return crtc_state1->hw.active && crtc_state2->hw.active &&
4533 crtc_state1->output_types == crtc_state2->output_types &&
4534 crtc_state1->output_format == crtc_state2->output_format &&
4535 crtc_state1->lane_count == crtc_state2->lane_count &&
4536 crtc_state1->port_clock == crtc_state2->port_clock &&
4537 mode_equal(&crtc_state1->hw.adjusted_mode,
4538 &crtc_state2->hw.adjusted_mode) &&
4539 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4543 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4546 struct drm_connector *connector;
4547 const struct drm_connector_state *conn_state;
4548 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4549 struct intel_atomic_state *state =
4550 to_intel_atomic_state(ref_crtc_state->uapi.state);
4555 * We don't enable port sync on BDW due to missing w/as and
4556 * due to not having adjusted the modeset sequence appropriately.
4558 if (INTEL_GEN(dev_priv) < 9)
4561 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4564 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4565 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4566 const struct intel_crtc_state *crtc_state;
4571 if (!connector->has_tile ||
4572 connector->tile_group->id !=
4575 crtc_state = intel_atomic_get_new_crtc_state(state,
4577 if (!crtcs_port_sync_compatible(ref_crtc_state,
4580 transcoders |= BIT(crtc_state->cpu_transcoder);
4586 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4587 struct intel_crtc_state *crtc_state,
4588 struct drm_connector_state *conn_state)
4590 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4591 struct drm_connector *connector = conn_state->connector;
4592 u8 port_sync_transcoders = 0;
4594 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4595 encoder->base.base.id, encoder->base.name,
4596 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4598 if (connector->has_tile)
4599 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4600 connector->tile_group->id);
4603 * EDP Transcoders cannot be ensalved
4604 * make them a master always when present
4606 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4607 crtc_state->master_transcoder = TRANSCODER_EDP;
4609 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4611 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4612 crtc_state->master_transcoder = INVALID_TRANSCODER;
4613 crtc_state->sync_mode_slaves_mask =
4614 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4620 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4622 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4624 intel_dp_encoder_flush_work(encoder);
4626 drm_encoder_cleanup(encoder);
4630 static const struct drm_encoder_funcs intel_ddi_funcs = {
4631 .reset = intel_dp_encoder_reset,
4632 .destroy = intel_ddi_encoder_destroy,
4635 static struct intel_connector *
4636 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4638 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4639 struct intel_connector *connector;
4640 enum port port = dig_port->base.port;
4642 connector = intel_connector_alloc();
4646 dig_port->dp.output_reg = DDI_BUF_CTL(port);
4647 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4648 dig_port->dp.set_link_train = intel_ddi_set_link_train;
4649 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4651 if (INTEL_GEN(dev_priv) >= 12)
4652 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4653 else if (INTEL_GEN(dev_priv) >= 11)
4654 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4655 else if (IS_CANNONLAKE(dev_priv))
4656 dig_port->dp.set_signal_levels = cnl_set_signal_levels;
4657 else if (IS_GEN9_LP(dev_priv))
4658 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4660 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4662 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4663 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4665 if (INTEL_GEN(dev_priv) < 12) {
4666 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
4667 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
4670 if (!intel_dp_init_connector(dig_port, connector)) {
4678 static int modeset_pipe(struct drm_crtc *crtc,
4679 struct drm_modeset_acquire_ctx *ctx)
4681 struct drm_atomic_state *state;
4682 struct drm_crtc_state *crtc_state;
4685 state = drm_atomic_state_alloc(crtc->dev);
4689 state->acquire_ctx = ctx;
4691 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4692 if (IS_ERR(crtc_state)) {
4693 ret = PTR_ERR(crtc_state);
4697 crtc_state->connectors_changed = true;
4699 ret = drm_atomic_commit(state);
4701 drm_atomic_state_put(state);
4706 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4707 struct drm_modeset_acquire_ctx *ctx)
4709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4710 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4711 struct intel_connector *connector = hdmi->attached_connector;
4712 struct i2c_adapter *adapter =
4713 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4714 struct drm_connector_state *conn_state;
4715 struct intel_crtc_state *crtc_state;
4716 struct intel_crtc *crtc;
4720 if (!connector || connector->base.status != connector_status_connected)
4723 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4728 conn_state = connector->base.state;
4730 crtc = to_intel_crtc(conn_state->crtc);
4734 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4738 crtc_state = to_intel_crtc_state(crtc->base.state);
4740 drm_WARN_ON(&dev_priv->drm,
4741 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4743 if (!crtc_state->hw.active)
4746 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4747 !crtc_state->hdmi_scrambling)
4750 if (conn_state->commit &&
4751 !try_wait_for_completion(&conn_state->commit->hw_done))
4754 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4756 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4761 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4762 crtc_state->hdmi_high_tmds_clock_ratio &&
4763 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4764 crtc_state->hdmi_scrambling)
4768 * HDMI 2.0 says that one should not send scrambled data
4769 * prior to configuring the sink scrambling, and that
4770 * TMDS clock/data transmission should be suspended when
4771 * changing the TMDS clock rate in the sink. So let's
4772 * just do a full modeset here, even though some sinks
4773 * would be perfectly happy if were to just reconfigure
4774 * the SCDC settings on the fly.
4776 return modeset_pipe(&crtc->base, ctx);
4779 static enum intel_hotplug_state
4780 intel_ddi_hotplug(struct intel_encoder *encoder,
4781 struct intel_connector *connector)
4783 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4784 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4785 enum phy phy = intel_port_to_phy(i915, encoder->port);
4786 bool is_tc = intel_phy_is_tc(i915, phy);
4787 struct drm_modeset_acquire_ctx ctx;
4788 enum intel_hotplug_state state;
4791 state = intel_encoder_hotplug(encoder, connector);
4793 drm_modeset_acquire_init(&ctx, 0);
4796 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4797 ret = intel_hdmi_reset_link(encoder, &ctx);
4799 ret = intel_dp_retrain_link(encoder, &ctx);
4801 if (ret == -EDEADLK) {
4802 drm_modeset_backoff(&ctx);
4809 drm_modeset_drop_locks(&ctx);
4810 drm_modeset_acquire_fini(&ctx);
4811 drm_WARN(encoder->base.dev, ret,
4812 "Acquiring modeset locks failed with %i\n", ret);
4815 * Unpowered type-c dongles can take some time to boot and be
4816 * responsible, so here giving some time to those dongles to power up
4817 * and then retrying the probe.
4819 * On many platforms the HDMI live state signal is known to be
4820 * unreliable, so we can't use it to detect if a sink is connected or
4821 * not. Instead we detect if it's connected based on whether we can
4822 * read the EDID or not. That in turn has a problem during disconnect,
4823 * since the HPD interrupt may be raised before the DDC lines get
4824 * disconnected (due to how the required length of DDC vs. HPD
4825 * connector pins are specified) and so we'll still be able to get a
4826 * valid EDID. To solve this schedule another detection cycle if this
4827 * time around we didn't detect any change in the sink's connection
4830 * Type-c connectors which get their HPD signal deasserted then
4831 * reasserted, without unplugging/replugging the sink from the
4832 * connector, introduce a delay until the AUX channel communication
4833 * becomes functional. Retry the detection for 5 seconds on type-c
4834 * connectors to account for this delay.
4836 if (state == INTEL_HOTPLUG_UNCHANGED &&
4837 connector->hotplug_retries < (is_tc ? 5 : 1) &&
4838 !dig_port->dp.is_mst)
4839 state = INTEL_HOTPLUG_RETRY;
4844 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4846 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4847 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4849 return intel_de_read(dev_priv, SDEISR) & bit;
4852 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4854 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4855 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4857 return intel_de_read(dev_priv, DEISR) & bit;
4860 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4862 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4863 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4865 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4868 static struct intel_connector *
4869 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4871 struct intel_connector *connector;
4872 enum port port = dig_port->base.port;
4874 connector = intel_connector_alloc();
4878 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4879 intel_hdmi_init_connector(dig_port, connector);
4884 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4886 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4888 if (dig_port->base.port != PORT_A)
4891 if (dig_port->saved_port_bits & DDI_A_4_LANES)
4894 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4895 * supported configuration
4897 if (IS_GEN9_LP(dev_priv))
4900 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4901 * one who does also have a full A/E split called
4902 * DDI_F what makes DDI_E useless. However for this
4903 * case let's trust VBT info.
4905 if (IS_CANNONLAKE(dev_priv) &&
4906 !intel_bios_is_port_present(dev_priv, PORT_E))
4913 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4915 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4916 enum port port = dig_port->base.port;
4919 if (INTEL_GEN(dev_priv) >= 11)
4922 if (port == PORT_A || port == PORT_E) {
4923 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4924 max_lanes = port == PORT_A ? 4 : 0;
4926 /* Both A and E share 2 lanes */
4931 * Some BIOS might fail to set this bit on port A if eDP
4932 * wasn't lit up at boot. Force this bit set when needed
4933 * so we use the proper lane count for our calculations.
4935 if (intel_ddi_a_force_4_lanes(dig_port)) {
4936 drm_dbg_kms(&dev_priv->drm,
4937 "Forcing DDI_A_4_LANES for port A\n");
4938 dig_port->saved_port_bits |= DDI_A_4_LANES;
4945 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4947 return i915->hti_state & HDPORT_ENABLED &&
4948 (i915->hti_state & HDPORT_PHY_USED_DP(phy) ||
4949 i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
4952 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4954 struct intel_digital_port *dig_port;
4955 struct intel_encoder *encoder;
4956 bool init_hdmi, init_dp, init_lspcon = false;
4957 enum phy phy = intel_port_to_phy(dev_priv, port);
4960 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4961 * have taken over some of the PHYs and made them unavailable to the
4962 * driver. In that case we should skip initializing the corresponding
4965 if (hti_uses_phy(dev_priv, phy)) {
4966 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4967 port_name(port), phy_name(phy));
4971 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
4972 intel_bios_port_supports_hdmi(dev_priv, port);
4973 init_dp = intel_bios_port_supports_dp(dev_priv, port);
4975 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4977 * Lspcon device needs to be driven with DP connector
4978 * with special detection sequence. So make sure DP
4979 * is initialized before lspcon.
4984 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4988 if (!init_dp && !init_hdmi) {
4989 drm_dbg_kms(&dev_priv->drm,
4990 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4995 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4999 encoder = &dig_port->base;
5001 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5002 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
5004 encoder->hotplug = intel_ddi_hotplug;
5005 encoder->compute_output_type = intel_ddi_compute_output_type;
5006 encoder->compute_config = intel_ddi_compute_config;
5007 encoder->compute_config_late = intel_ddi_compute_config_late;
5008 encoder->enable = intel_enable_ddi;
5009 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5010 encoder->pre_enable = intel_ddi_pre_enable;
5011 encoder->disable = intel_disable_ddi;
5012 encoder->post_disable = intel_ddi_post_disable;
5013 encoder->update_pipe = intel_ddi_update_pipe;
5014 encoder->get_hw_state = intel_ddi_get_hw_state;
5015 encoder->get_config = intel_ddi_get_config;
5016 encoder->suspend = intel_dp_encoder_suspend;
5017 encoder->get_power_domains = intel_ddi_get_power_domains;
5019 encoder->type = INTEL_OUTPUT_DDI;
5020 encoder->power_domain = intel_port_to_power_domain(port);
5021 encoder->port = port;
5022 encoder->cloneable = 0;
5023 encoder->pipe_mask = ~0;
5025 if (INTEL_GEN(dev_priv) >= 11)
5026 dig_port->saved_port_bits =
5027 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5028 & DDI_BUF_PORT_REVERSAL;
5030 dig_port->saved_port_bits =
5031 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5032 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
5034 dig_port->dp.output_reg = INVALID_MMIO_REG;
5035 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5036 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
5038 if (intel_phy_is_tc(dev_priv, phy)) {
5040 !intel_bios_port_supports_typec_usb(dev_priv, port) &&
5041 !intel_bios_port_supports_tbt(dev_priv, port);
5043 intel_tc_port_init(dig_port, is_legacy);
5045 encoder->update_prepare = intel_ddi_update_prepare;
5046 encoder->update_complete = intel_ddi_update_complete;
5049 drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5050 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
5054 if (!intel_ddi_init_dp_connector(dig_port))
5057 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5060 /* In theory we don't need the encoder->type check, but leave it just in
5061 * case we have some really bad VBTs... */
5062 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5063 if (!intel_ddi_init_hdmi_connector(dig_port))
5068 if (lspcon_init(dig_port))
5069 /* TODO: handle hdmi info frame part */
5070 drm_dbg_kms(&dev_priv->drm,
5071 "LSPCON init success on port %c\n",
5075 * LSPCON init faied, but DP init was success, so
5076 * lets try to drive as DP++ port.
5078 drm_err(&dev_priv->drm,
5079 "LSPCON init failed on port %c\n",
5083 if (INTEL_GEN(dev_priv) >= 11) {
5084 if (intel_phy_is_tc(dev_priv, phy))
5085 dig_port->connected = intel_tc_port_connected;
5087 dig_port->connected = lpt_digital_port_connected;
5088 } else if (INTEL_GEN(dev_priv) >= 8) {
5089 if (port == PORT_A || IS_GEN9_LP(dev_priv))
5090 dig_port->connected = bdw_digital_port_connected;
5092 dig_port->connected = lpt_digital_port_connected;
5095 dig_port->connected = hsw_digital_port_connected;
5097 dig_port->connected = lpt_digital_port_connected;
5100 intel_infoframe_init(dig_port);
5105 drm_encoder_cleanup(&encoder->base);