drivers/gpu/drm/i915/display/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/firmware.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_reg.h"
  29 #include "intel_csr.h"
  30 #include "intel_de.h"
  31
  32 /**
  33  * DOC: csr support for dmc
  34  *
  35  * Display Context Save and Restore (CSR) firmware support added from gen9
  36  * onwards to drive newly added DMC (Display microcontroller) in display
  37  * engine to save and restore the state of display engine when it enter into
  38  * low-power state and comes back to normal.
  39  */
  40
  41 #define GEN12_CSR_MAX_FW_SIZE           ICL_CSR_MAX_FW_SIZE
  42
  43 #define ADLS_CSR_PATH                   "i915/adls_dmc_ver2_01.bin"
  44 #define ADLS_CSR_VERSION_REQUIRED       CSR_VERSION(2, 1)
  45 MODULE_FIRMWARE(ADLS_CSR_PATH);
  46
  47 #define DG1_CSR_PATH                    "i915/dg1_dmc_ver2_02.bin"
  48 #define DG1_CSR_VERSION_REQUIRED        CSR_VERSION(2, 2)
  49 MODULE_FIRMWARE(DG1_CSR_PATH);
  50
  51 #define RKL_CSR_PATH                    "i915/rkl_dmc_ver2_02.bin"
  52 #define RKL_CSR_VERSION_REQUIRED        CSR_VERSION(2, 2)
  53 MODULE_FIRMWARE(RKL_CSR_PATH);
  54
  55 #define TGL_CSR_PATH                    "i915/tgl_dmc_ver2_08.bin"
  56 #define TGL_CSR_VERSION_REQUIRED        CSR_VERSION(2, 8)
  57 MODULE_FIRMWARE(TGL_CSR_PATH);
  58
  59 #define ICL_CSR_PATH                    "i915/icl_dmc_ver1_09.bin"
  60 #define ICL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 9)
  61 #define ICL_CSR_MAX_FW_SIZE             0x6000
  62 MODULE_FIRMWARE(ICL_CSR_PATH);
  63
  64 #define CNL_CSR_PATH                    "i915/cnl_dmc_ver1_07.bin"
  65 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  66 #define CNL_CSR_MAX_FW_SIZE             GLK_CSR_MAX_FW_SIZE
  67 MODULE_FIRMWARE(CNL_CSR_PATH);
  68
  69 #define GLK_CSR_PATH                    "i915/glk_dmc_ver1_04.bin"
  70 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  71 #define GLK_CSR_MAX_FW_SIZE             0x4000
  72 MODULE_FIRMWARE(GLK_CSR_PATH);
  73
  74 #define KBL_CSR_PATH                    "i915/kbl_dmc_ver1_04.bin"
  75 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  76 #define KBL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  77 MODULE_FIRMWARE(KBL_CSR_PATH);
  78
  79 #define SKL_CSR_PATH                    "i915/skl_dmc_ver1_27.bin"
  80 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  81 #define SKL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  82 MODULE_FIRMWARE(SKL_CSR_PATH);
  83
  84 #define BXT_CSR_PATH                    "i915/bxt_dmc_ver1_07.bin"
  85 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  86 #define BXT_CSR_MAX_FW_SIZE             0x3000
  87 MODULE_FIRMWARE(BXT_CSR_PATH);
  88
  89 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  90 #define PACKAGE_MAX_FW_INFO_ENTRIES     20
  91 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES  32
  92 #define DMC_V1_MAX_MMIO_COUNT           8
  93 #define DMC_V3_MAX_MMIO_COUNT           20
  94
  95 struct intel_css_header {
  96         /* 0x09 for DMC */
  97         u32 module_type;
  98
  99         /* Includes the DMC specific header in dwords */
 100         u32 header_len;
 101
 102         /* always value would be 0x10000 */
 103         u32 header_ver;
 104
 105         /* Not used */
 106         u32 module_id;
 107
 108         /* Not used */
 109         u32 module_vendor;
 110
 111         /* in YYYYMMDD format */
 112         u32 date;
 113
 114         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
 115         u32 size;
 116
 117         /* Not used */
 118         u32 key_size;
 119
 120         /* Not used */
 121         u32 modulus_size;
 122
 123         /* Not used */
 124         u32 exponent_size;
 125
 126         /* Not used */
 127         u32 reserved1[12];
 128
 129         /* Major Minor */
 130         u32 version;
 131
 132         /* Not used */
 133         u32 reserved2[8];
 134
 135         /* Not used */
 136         u32 kernel_header_info;
 137 } __packed;
 138
 139 struct intel_fw_info {
 140         u8 reserved1;
 141
 142         /* reserved on package_header version 1, must be 0 on version 2 */
 143         u8 dmc_id;
 144
 145         /* Stepping (A, B, C, ..., *). * is a wildcard */
 146         char stepping;
 147
 148         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 149         char substepping;
 150
 151         u32 offset;
 152         u32 reserved2;
 153 } __packed;
 154
 155 struct intel_package_header {
 156         /* DMC container header length in dwords */
 157         u8 header_len;
 158
 159         /* 0x01, 0x02 */
 160         u8 header_ver;
 161
 162         u8 reserved[10];
 163
 164         /* Number of valid entries in the FWInfo array below */
 165         u32 num_entries;
 166 } __packed;
 167
 168 struct intel_dmc_header_base {
 169         /* always value would be 0x40403E3E */
 170         u32 signature;
 171
 172         /* DMC binary header length */
 173         u8 header_len;
 174
 175         /* 0x01 */
 176         u8 header_ver;
 177
 178         /* Reserved */
 179         u16 dmcc_ver;
 180
 181         /* Major, Minor */
 182         u32 project;
 183
 184         /* Firmware program size (excluding header) in dwords */
 185         u32 fw_size;
 186
 187         /* Major Minor version */
 188         u32 fw_version;
 189 } __packed;
 190
 191 struct intel_dmc_header_v1 {
 192         struct intel_dmc_header_base base;
 193
 194         /* Number of valid MMIO cycles present. */
 195         u32 mmio_count;
 196
 197         /* MMIO address */
 198         u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
 199
 200         /* MMIO data */
 201         u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
 202
 203         /* FW filename  */
 204         char dfile[32];
 205
 206         u32 reserved1[2];
 207 } __packed;
 208
 209 struct intel_dmc_header_v3 {
 210         struct intel_dmc_header_base base;
 211
 212         /* DMC RAM start MMIO address */
 213         u32 start_mmioaddr;
 214
 215         u32 reserved[9];
 216
 217         /* FW filename */
 218         char dfile[32];
 219
 220         /* Number of valid MMIO cycles present. */
 221         u32 mmio_count;
 222
 223         /* MMIO address */
 224         u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
 225
 226         /* MMIO data */
 227         u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
 228 } __packed;
 229
 230 struct stepping_info {
 231         char stepping;
 232         char substepping;
 233 };
 234
 235 static const struct stepping_info skl_stepping_info[] = {
 236         {'A', '0'}, {'B', '0'}, {'C', '0'},
 237         {'D', '0'}, {'E', '0'}, {'F', '0'},
 238         {'G', '0'}, {'H', '0'}, {'I', '0'},
 239         {'J', '0'}, {'K', '0'}
 240 };
 241
 242 static const struct stepping_info bxt_stepping_info[] = {
 243         {'A', '0'}, {'A', '1'}, {'A', '2'},
 244         {'B', '0'}, {'B', '1'}, {'B', '2'}
 245 };
 246
 247 static const struct stepping_info icl_stepping_info[] = {
 248         {'A', '0'}, {'A', '1'}, {'A', '2'},
 249         {'B', '0'}, {'B', '2'},
 250         {'C', '0'}
 251 };
 252
 253 static const struct stepping_info no_stepping_info = { '*', '*' };
 254
 255 static const struct stepping_info *
 256 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 257 {
 258         const struct stepping_info *si;
 259         unsigned int size;
 260
 261         if (IS_ICELAKE(dev_priv)) {
 262                 size = ARRAY_SIZE(icl_stepping_info);
 263                 si = icl_stepping_info;
 264         } else if (IS_SKYLAKE(dev_priv)) {
 265                 size = ARRAY_SIZE(skl_stepping_info);
 266                 si = skl_stepping_info;
 267         } else if (IS_BROXTON(dev_priv)) {
 268                 size = ARRAY_SIZE(bxt_stepping_info);
 269                 si = bxt_stepping_info;
 270         } else {
 271                 size = 0;
 272                 si = NULL;
 273         }
 274
 275         if (INTEL_REVID(dev_priv) < size)
 276                 return si + INTEL_REVID(dev_priv);
 277
 278         return &no_stepping_info;
 279 }
 280
 281 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 282 {
 283         u32 val, mask;
 284
 285         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 286
 287         if (IS_GEN9_LP(dev_priv))
 288                 mask |= DC_STATE_DEBUG_MASK_CORES;
 289
 290         /* The below bit doesn't need to be cleared ever afterwards */
 291         val = intel_de_read(dev_priv, DC_STATE_DEBUG);
 292         if ((val & mask) != mask) {
 293                 val |= mask;
 294                 intel_de_write(dev_priv, DC_STATE_DEBUG, val);
 295                 intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
 296         }
 297 }
 298
 299 /**
 300  * intel_csr_load_program() - write the firmware from memory to register.
 301  * @dev_priv: i915 drm device.
 302  *
 303  * CSR firmware is read from a .bin file and kept in internal memory one time.
 304  * Everytime display comes back from low power state this function is called to
 305  * copy the firmware from internal memory to registers.
 306  */
 307 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 308 {
 309         u32 *payload = dev_priv->csr.dmc_payload;
 310         u32 i, fw_size;
 311
 312         if (!HAS_CSR(dev_priv)) {
 313                 drm_err(&dev_priv->drm,
 314                         "No CSR support available for this platform\n");
 315                 return;
 316         }
 317
 318         if (!dev_priv->csr.dmc_payload) {
 319                 drm_err(&dev_priv->drm,
 320                         "Tried to program CSR with empty payload\n");
 321                 return;
 322         }
 323
 324         fw_size = dev_priv->csr.dmc_fw_size;
 325         assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 326
 327         preempt_disable();
 328
 329         for (i = 0; i < fw_size; i++)
 330                 intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
 331                                       payload[i]);
 332
 333         preempt_enable();
 334
 335         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 336                 intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
 337                                dev_priv->csr.mmiodata[i]);
 338         }
 339
 340         dev_priv->csr.dc_state = 0;
 341
 342         gen9_set_dc_state_debugmask(dev_priv);
 343 }
 344
 345 /*
 346  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
 347  * already sanitized.
 348  */
 349 static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
 350                               unsigned int num_entries,
 351                               const struct stepping_info *si,
 352                               u8 package_ver)
 353 {
 354         u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
 355         unsigned int i;
 356
 357         for (i = 0; i < num_entries; i++) {
 358                 if (package_ver > 1 && fw_info[i].dmc_id != 0)
 359                         continue;
 360
 361                 if (fw_info[i].substepping == '*' &&
 362                     si->stepping == fw_info[i].stepping) {
 363                         dmc_offset = fw_info[i].offset;
 364                         break;
 365                 }
 366
 367                 if (si->stepping == fw_info[i].stepping &&
 368                     si->substepping == fw_info[i].substepping) {
 369                         dmc_offset = fw_info[i].offset;
 370                         break;
 371                 }
 372
 373                 if (fw_info[i].stepping == '*' &&
 374                     fw_info[i].substepping == '*') {
 375                         /*
 376                          * In theory we should stop the search as generic
 377                          * entries should always come after the more specific
 378                          * ones, but let's continue to make sure to work even
 379                          * with "broken" firmwares. If we don't find a more
 380                          * specific one, then we use this entry
 381                          */
 382                         dmc_offset = fw_info[i].offset;
 383                 }
 384         }
 385
 386         return dmc_offset;
 387 }
 388
 389 static u32 parse_csr_fw_dmc(struct intel_csr *csr,
 390                             const struct intel_dmc_header_base *dmc_header,
 391                             size_t rem_size)
 392 {
 393         unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 394         const u32 *mmioaddr, *mmiodata;
 395         u32 mmio_count, mmio_count_max;
 396         u8 *payload;
 397
 398         BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
 399                      ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
 400
 401         /*
 402          * Check if we can access common fields, we will checkc again below
 403          * after we have read the version
 404          */
 405         if (rem_size < sizeof(struct intel_dmc_header_base))
 406                 goto error_truncated;
 407
 408         /* Cope with small differences between v1 and v3 */
 409         if (dmc_header->header_ver == 3) {
 410                 const struct intel_dmc_header_v3 *v3 =
 411                         (const struct intel_dmc_header_v3 *)dmc_header;
 412
 413                 if (rem_size < sizeof(struct intel_dmc_header_v3))
 414                         goto error_truncated;
 415
 416                 mmioaddr = v3->mmioaddr;
 417                 mmiodata = v3->mmiodata;
 418                 mmio_count = v3->mmio_count;
 419                 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
 420                 /* header_len is in dwords */
 421                 header_len_bytes = dmc_header->header_len * 4;
 422                 dmc_header_size = sizeof(*v3);
 423         } else if (dmc_header->header_ver == 1) {
 424                 const struct intel_dmc_header_v1 *v1 =
 425                         (const struct intel_dmc_header_v1 *)dmc_header;
 426
 427                 if (rem_size < sizeof(struct intel_dmc_header_v1))
 428                         goto error_truncated;
 429
 430                 mmioaddr = v1->mmioaddr;
 431                 mmiodata = v1->mmiodata;
 432                 mmio_count = v1->mmio_count;
 433                 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
 434                 header_len_bytes = dmc_header->header_len;
 435                 dmc_header_size = sizeof(*v1);
 436         } else {
 437                 DRM_ERROR("Unknown DMC fw header version: %u\n",
 438                           dmc_header->header_ver);
 439                 return 0;
 440         }
 441
 442         if (header_len_bytes != dmc_header_size) {
 443                 DRM_ERROR("DMC firmware has wrong dmc header length "
 444                           "(%u bytes)\n", header_len_bytes);
 445                 return 0;
 446         }
 447
 448         /* Cache the dmc header info. */
 449         if (mmio_count > mmio_count_max) {
 450                 DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
 451                 return 0;
 452         }
 453
 454         for (i = 0; i < mmio_count; i++) {
 455                 if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
 456                     mmioaddr[i] > CSR_MMIO_END_RANGE) {
 457                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 458                                   mmioaddr[i]);
 459                         return 0;
 460                 }
 461                 csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
 462                 csr->mmiodata[i] = mmiodata[i];
 463         }
 464         csr->mmio_count = mmio_count;
 465
 466         rem_size -= header_len_bytes;
 467
 468         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 469         payload_size = dmc_header->fw_size * 4;
 470         if (rem_size < payload_size)
 471                 goto error_truncated;
 472
 473         if (payload_size > csr->max_fw_size) {
 474                 DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
 475                 return 0;
 476         }
 477         csr->dmc_fw_size = dmc_header->fw_size;
 478
 479         csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
 480         if (!csr->dmc_payload) {
 481                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 482                 return 0;
 483         }
 484
 485         payload = (u8 *)(dmc_header) + header_len_bytes;
 486         memcpy(csr->dmc_payload, payload, payload_size);
 487
 488         return header_len_bytes + payload_size;
 489
 490 error_truncated:
 491         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 492         return 0;
 493 }
 494
 495 static u32
 496 parse_csr_fw_package(struct intel_csr *csr,
 497                      const struct intel_package_header *package_header,
 498                      const struct stepping_info *si,
 499                      size_t rem_size)
 500 {
 501         u32 package_size = sizeof(struct intel_package_header);
 502         u32 num_entries, max_entries, dmc_offset;
 503         const struct intel_fw_info *fw_info;
 504
 505         if (rem_size < package_size)
 506                 goto error_truncated;
 507
 508         if (package_header->header_ver == 1) {
 509                 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
 510         } else if (package_header->header_ver == 2) {
 511                 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
 512         } else {
 513                 DRM_ERROR("DMC firmware has unknown header version %u\n",
 514                           package_header->header_ver);
 515                 return 0;
 516         }
 517
 518         /*
 519          * We should always have space for max_entries,
 520          * even if not all are used
 521          */
 522         package_size += max_entries * sizeof(struct intel_fw_info);
 523         if (rem_size < package_size)
 524                 goto error_truncated;
 525
 526         if (package_header->header_len * 4 != package_size) {
 527                 DRM_ERROR("DMC firmware has wrong package header length "
 528                           "(%u bytes)\n", package_size);
 529                 return 0;
 530         }
 531
 532         num_entries = package_header->num_entries;
 533         if (WARN_ON(package_header->num_entries > max_entries))
 534                 num_entries = max_entries;
 535
 536         fw_info = (const struct intel_fw_info *)
 537                 ((u8 *)package_header + sizeof(*package_header));
 538         dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
 539                                         package_header->header_ver);
 540         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 541                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 542                           si->stepping);
 543                 return 0;
 544         }
 545
 546         /* dmc_offset is in dwords */
 547         return package_size + dmc_offset * 4;
 548
 549 error_truncated:
 550         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 551         return 0;
 552 }
 553
 554 /* Return number of bytes parsed or 0 on error */
 555 static u32 parse_csr_fw_css(struct intel_csr *csr,
 556                             struct intel_css_header *css_header,
 557                             size_t rem_size)
 558 {
 559         if (rem_size < sizeof(struct intel_css_header)) {
 560                 DRM_ERROR("Truncated DMC firmware, refusing.\n");
 561                 return 0;
 562         }
 563
 564         if (sizeof(struct intel_css_header) !=
 565             (css_header->header_len * 4)) {
 566                 DRM_ERROR("DMC firmware has wrong CSS header length "
 567                           "(%u bytes)\n",
 568                           (css_header->header_len * 4));
 569                 return 0;
 570         }
 571
 572         if (csr->required_version &&
 573             css_header->version != csr->required_version) {
 574                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 575                          " please use v%u.%u\n",
 576                          CSR_VERSION_MAJOR(css_header->version),
 577                          CSR_VERSION_MINOR(css_header->version),
 578                          CSR_VERSION_MAJOR(csr->required_version),
 579                          CSR_VERSION_MINOR(csr->required_version));
 580                 return 0;
 581         }
 582
 583         csr->version = css_header->version;
 584
 585         return sizeof(struct intel_css_header);
 586 }
 587
 588 static void parse_csr_fw(struct drm_i915_private *dev_priv,
 589                          const struct firmware *fw)
 590 {
 591         struct intel_css_header *css_header;
 592         struct intel_package_header *package_header;
 593         struct intel_dmc_header_base *dmc_header;
 594         struct intel_csr *csr = &dev_priv->csr;
 595         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 596         u32 readcount = 0;
 597         u32 r;
 598
 599         if (!fw)
 600                 return;
 601
 602         /* Extract CSS Header information */
 603         css_header = (struct intel_css_header *)fw->data;
 604         r = parse_csr_fw_css(csr, css_header, fw->size);
 605         if (!r)
 606                 return;
 607
 608         readcount += r;
 609
 610         /* Extract Package Header information */
 611         package_header = (struct intel_package_header *)&fw->data[readcount];
 612         r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
 613         if (!r)
 614                 return;
 615
 616         readcount += r;
 617
 618         /* Extract dmc_header information */
 619         dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
 620         parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
 621 }
 622
 623 static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
 624 {
 625         drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
 626         dev_priv->csr.wakeref =
 627                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 628 }
 629
 630 static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
 631 {
 632         intel_wakeref_t wakeref __maybe_unused =
 633                 fetch_and_zero(&dev_priv->csr.wakeref);
 634
 635         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
 636 }
 637
 638 static void csr_load_work_fn(struct work_struct *work)
 639 {
 640         struct drm_i915_private *dev_priv;
 641         struct intel_csr *csr;
 642         const struct firmware *fw = NULL;
 643
 644         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 645         csr = &dev_priv->csr;
 646
 647         request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev);
 648         parse_csr_fw(dev_priv, fw);
 649
 650         if (dev_priv->csr.dmc_payload) {
 651                 intel_csr_load_program(dev_priv);
 652                 intel_csr_runtime_pm_put(dev_priv);
 653
 654                 drm_info(&dev_priv->drm,
 655                          "Finished loading DMC firmware %s (v%u.%u)\n",
 656                          dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version),
 657                          CSR_VERSION_MINOR(csr->version));
 658         } else {
 659                 drm_notice(&dev_priv->drm,
 660                            "Failed to load DMC firmware %s."
 661                            " Disabling runtime power management.\n",
 662                            csr->fw_path);
 663                 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
 664                            INTEL_UC_FIRMWARE_URL);
 665         }
 666
 667         release_firmware(fw);
 668 }
 669
 670 /**
 671  * intel_csr_ucode_init() - initialize the firmware loading.
 672  * @dev_priv: i915 drm device.
 673  *
 674  * This function is called at the time of loading the display driver to read
 675  * firmware from a .bin file and copied into a internal memory.
 676  */
 677 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 678 {
 679         struct intel_csr *csr = &dev_priv->csr;
 680
 681         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 682
 683         if (!HAS_CSR(dev_priv))
 684                 return;
 685
 686         /*
 687          * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
 688          * runtime-suspend.
 689          *
 690          * On error, we return with the rpm wakeref held to prevent runtime
 691          * suspend as runtime suspend *requires* a working CSR for whatever
 692          * reason.
 693          */
 694         intel_csr_runtime_pm_get(dev_priv);
 695
 696         if (IS_ALDERLAKE_S(dev_priv)) {
 697                 csr->fw_path = ADLS_CSR_PATH;
 698                 csr->required_version = ADLS_CSR_VERSION_REQUIRED;
 699                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 700         } else if (IS_DG1(dev_priv)) {
 701                 csr->fw_path = DG1_CSR_PATH;
 702                 csr->required_version = DG1_CSR_VERSION_REQUIRED;
 703                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 704         } else if (IS_ROCKETLAKE(dev_priv)) {
 705                 csr->fw_path = RKL_CSR_PATH;
 706                 csr->required_version = RKL_CSR_VERSION_REQUIRED;
 707                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 708         } else if (DISPLAY_VER(dev_priv) >= 12) {
 709                 csr->fw_path = TGL_CSR_PATH;
 710                 csr->required_version = TGL_CSR_VERSION_REQUIRED;
 711                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 712         } else if (IS_DISPLAY_VER(dev_priv, 11)) {
 713                 csr->fw_path = ICL_CSR_PATH;
 714                 csr->required_version = ICL_CSR_VERSION_REQUIRED;
 715                 csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
 716         } else if (IS_CANNONLAKE(dev_priv)) {
 717                 csr->fw_path = CNL_CSR_PATH;
 718                 csr->required_version = CNL_CSR_VERSION_REQUIRED;
 719                 csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
 720         } else if (IS_GEMINILAKE(dev_priv)) {
 721                 csr->fw_path = GLK_CSR_PATH;
 722                 csr->required_version = GLK_CSR_VERSION_REQUIRED;
 723                 csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
 724         } else if (IS_KABYLAKE(dev_priv) ||
 725                    IS_COFFEELAKE(dev_priv) ||
 726                    IS_COMETLAKE(dev_priv)) {
 727                 csr->fw_path = KBL_CSR_PATH;
 728                 csr->required_version = KBL_CSR_VERSION_REQUIRED;
 729                 csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
 730         } else if (IS_SKYLAKE(dev_priv)) {
 731                 csr->fw_path = SKL_CSR_PATH;
 732                 csr->required_version = SKL_CSR_VERSION_REQUIRED;
 733                 csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
 734         } else if (IS_BROXTON(dev_priv)) {
 735                 csr->fw_path = BXT_CSR_PATH;
 736                 csr->required_version = BXT_CSR_VERSION_REQUIRED;
 737                 csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
 738         }
 739
 740         if (dev_priv->params.dmc_firmware_path) {
 741                 if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
 742                         csr->fw_path = NULL;
 743                         drm_info(&dev_priv->drm,
 744                                  "Disabling CSR firmware and runtime PM\n");
 745                         return;
 746                 }
 747
 748                 csr->fw_path = dev_priv->params.dmc_firmware_path;
 749                 /* Bypass version check for firmware override. */
 750                 csr->required_version = 0;
 751         }
 752
 753         if (csr->fw_path == NULL) {
 754                 drm_dbg_kms(&dev_priv->drm,
 755                             "No known CSR firmware for platform, disabling runtime PM\n");
 756                 return;
 757         }
 758
 759         drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path);
 760         schedule_work(&dev_priv->csr.work);
 761 }
 762
 763 /**
 764  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 765  * @dev_priv: i915 drm device
 766  *
 767  * Prepare the DMC firmware before entering system suspend. This includes
 768  * flushing pending work items and releasing any resources acquired during
 769  * init.
 770  */
 771 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 772 {
 773         if (!HAS_CSR(dev_priv))
 774                 return;
 775
 776         flush_work(&dev_priv->csr.work);
 777
 778         /* Drop the reference held in case DMC isn't loaded. */
 779         if (!dev_priv->csr.dmc_payload)
 780                 intel_csr_runtime_pm_put(dev_priv);
 781 }
 782
 783 /**
 784  * intel_csr_ucode_resume() - init CSR firmware during system resume
 785  * @dev_priv: i915 drm device
 786  *
 787  * Reinitialize the DMC firmware during system resume, reacquiring any
 788  * resources released in intel_csr_ucode_suspend().
 789  */
 790 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 791 {
 792         if (!HAS_CSR(dev_priv))
 793                 return;
 794
 795         /*
 796          * Reacquire the reference to keep RPM disabled in case DMC isn't
 797          * loaded.
 798          */
 799         if (!dev_priv->csr.dmc_payload)
 800                 intel_csr_runtime_pm_get(dev_priv);
 801 }
 802
 803 /**
 804  * intel_csr_ucode_fini() - unload the CSR firmware.
 805  * @dev_priv: i915 drm device.
 806  *
 807  * Firmmware unloading includes freeing the internal memory and reset the
 808  * firmware loading status.
 809  */
 810 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 811 {
 812         if (!HAS_CSR(dev_priv))
 813                 return;
 814
 815         intel_csr_ucode_suspend(dev_priv);
 816         drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
 817
 818         kfree(dev_priv->csr.dmc_payload);
 819 }