drivers/gpu/drm/i915/display/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/firmware.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_reg.h"
  29 #include "intel_csr.h"
  30 #include "intel_de.h"
  31
  32 /**
  33  * DOC: csr support for dmc
  34  *
  35  * Display Context Save and Restore (CSR) firmware support added from gen9
  36  * onwards to drive newly added DMC (Display microcontroller) in display
  37  * engine to save and restore the state of display engine when it enter into
  38  * low-power state and comes back to normal.
  39  */
  40
  41 #define GEN12_CSR_MAX_FW_SIZE           ICL_CSR_MAX_FW_SIZE
  42
  43 #define DG1_CSR_PATH                    "i915/dg1_dmc_ver2_02.bin"
  44 #define DG1_CSR_VERSION_REQUIRED        CSR_VERSION(2, 2)
  45 MODULE_FIRMWARE(DG1_CSR_PATH);
  46
  47 #define RKL_CSR_PATH                    "i915/rkl_dmc_ver2_02.bin"
  48 #define RKL_CSR_VERSION_REQUIRED        CSR_VERSION(2, 2)
  49 MODULE_FIRMWARE(RKL_CSR_PATH);
  50
  51 #define TGL_CSR_PATH                    "i915/tgl_dmc_ver2_08.bin"
  52 #define TGL_CSR_VERSION_REQUIRED        CSR_VERSION(2, 8)
  53 MODULE_FIRMWARE(TGL_CSR_PATH);
  54
  55 #define ICL_CSR_PATH                    "i915/icl_dmc_ver1_09.bin"
  56 #define ICL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 9)
  57 #define ICL_CSR_MAX_FW_SIZE             0x6000
  58 MODULE_FIRMWARE(ICL_CSR_PATH);
  59
  60 #define CNL_CSR_PATH                    "i915/cnl_dmc_ver1_07.bin"
  61 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  62 #define CNL_CSR_MAX_FW_SIZE             GLK_CSR_MAX_FW_SIZE
  63 MODULE_FIRMWARE(CNL_CSR_PATH);
  64
  65 #define GLK_CSR_PATH                    "i915/glk_dmc_ver1_04.bin"
  66 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  67 #define GLK_CSR_MAX_FW_SIZE             0x4000
  68 MODULE_FIRMWARE(GLK_CSR_PATH);
  69
  70 #define KBL_CSR_PATH                    "i915/kbl_dmc_ver1_04.bin"
  71 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  72 #define KBL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  73 MODULE_FIRMWARE(KBL_CSR_PATH);
  74
  75 #define SKL_CSR_PATH                    "i915/skl_dmc_ver1_27.bin"
  76 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  77 #define SKL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  78 MODULE_FIRMWARE(SKL_CSR_PATH);
  79
  80 #define BXT_CSR_PATH                    "i915/bxt_dmc_ver1_07.bin"
  81 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  82 #define BXT_CSR_MAX_FW_SIZE             0x3000
  83 MODULE_FIRMWARE(BXT_CSR_PATH);
  84
  85 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  86 #define PACKAGE_MAX_FW_INFO_ENTRIES     20
  87 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES  32
  88 #define DMC_V1_MAX_MMIO_COUNT           8
  89 #define DMC_V3_MAX_MMIO_COUNT           20
  90
  91 struct intel_css_header {
  92         /* 0x09 for DMC */
  93         u32 module_type;
  94
  95         /* Includes the DMC specific header in dwords */
  96         u32 header_len;
  97
  98         /* always value would be 0x10000 */
  99         u32 header_ver;
 100
 101         /* Not used */
 102         u32 module_id;
 103
 104         /* Not used */
 105         u32 module_vendor;
 106
 107         /* in YYYYMMDD format */
 108         u32 date;
 109
 110         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
 111         u32 size;
 112
 113         /* Not used */
 114         u32 key_size;
 115
 116         /* Not used */
 117         u32 modulus_size;
 118
 119         /* Not used */
 120         u32 exponent_size;
 121
 122         /* Not used */
 123         u32 reserved1[12];
 124
 125         /* Major Minor */
 126         u32 version;
 127
 128         /* Not used */
 129         u32 reserved2[8];
 130
 131         /* Not used */
 132         u32 kernel_header_info;
 133 } __packed;
 134
 135 struct intel_fw_info {
 136         u8 reserved1;
 137
 138         /* reserved on package_header version 1, must be 0 on version 2 */
 139         u8 dmc_id;
 140
 141         /* Stepping (A, B, C, ..., *). * is a wildcard */
 142         char stepping;
 143
 144         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 145         char substepping;
 146
 147         u32 offset;
 148         u32 reserved2;
 149 } __packed;
 150
 151 struct intel_package_header {
 152         /* DMC container header length in dwords */
 153         u8 header_len;
 154
 155         /* 0x01, 0x02 */
 156         u8 header_ver;
 157
 158         u8 reserved[10];
 159
 160         /* Number of valid entries in the FWInfo array below */
 161         u32 num_entries;
 162 } __packed;
 163
 164 struct intel_dmc_header_base {
 165         /* always value would be 0x40403E3E */
 166         u32 signature;
 167
 168         /* DMC binary header length */
 169         u8 header_len;
 170
 171         /* 0x01 */
 172         u8 header_ver;
 173
 174         /* Reserved */
 175         u16 dmcc_ver;
 176
 177         /* Major, Minor */
 178         u32 project;
 179
 180         /* Firmware program size (excluding header) in dwords */
 181         u32 fw_size;
 182
 183         /* Major Minor version */
 184         u32 fw_version;
 185 } __packed;
 186
 187 struct intel_dmc_header_v1 {
 188         struct intel_dmc_header_base base;
 189
 190         /* Number of valid MMIO cycles present. */
 191         u32 mmio_count;
 192
 193         /* MMIO address */
 194         u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
 195
 196         /* MMIO data */
 197         u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
 198
 199         /* FW filename  */
 200         char dfile[32];
 201
 202         u32 reserved1[2];
 203 } __packed;
 204
 205 struct intel_dmc_header_v3 {
 206         struct intel_dmc_header_base base;
 207
 208         /* DMC RAM start MMIO address */
 209         u32 start_mmioaddr;
 210
 211         u32 reserved[9];
 212
 213         /* FW filename */
 214         char dfile[32];
 215
 216         /* Number of valid MMIO cycles present. */
 217         u32 mmio_count;
 218
 219         /* MMIO address */
 220         u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
 221
 222         /* MMIO data */
 223         u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
 224 } __packed;
 225
 226 struct stepping_info {
 227         char stepping;
 228         char substepping;
 229 };
 230
 231 static const struct stepping_info skl_stepping_info[] = {
 232         {'A', '0'}, {'B', '0'}, {'C', '0'},
 233         {'D', '0'}, {'E', '0'}, {'F', '0'},
 234         {'G', '0'}, {'H', '0'}, {'I', '0'},
 235         {'J', '0'}, {'K', '0'}
 236 };
 237
 238 static const struct stepping_info bxt_stepping_info[] = {
 239         {'A', '0'}, {'A', '1'}, {'A', '2'},
 240         {'B', '0'}, {'B', '1'}, {'B', '2'}
 241 };
 242
 243 static const struct stepping_info icl_stepping_info[] = {
 244         {'A', '0'}, {'A', '1'}, {'A', '2'},
 245         {'B', '0'}, {'B', '2'},
 246         {'C', '0'}
 247 };
 248
 249 static const struct stepping_info no_stepping_info = { '*', '*' };
 250
 251 static const struct stepping_info *
 252 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 253 {
 254         const struct stepping_info *si;
 255         unsigned int size;
 256
 257         if (IS_ICELAKE(dev_priv)) {
 258                 size = ARRAY_SIZE(icl_stepping_info);
 259                 si = icl_stepping_info;
 260         } else if (IS_SKYLAKE(dev_priv)) {
 261                 size = ARRAY_SIZE(skl_stepping_info);
 262                 si = skl_stepping_info;
 263         } else if (IS_BROXTON(dev_priv)) {
 264                 size = ARRAY_SIZE(bxt_stepping_info);
 265                 si = bxt_stepping_info;
 266         } else {
 267                 size = 0;
 268                 si = NULL;
 269         }
 270
 271         if (INTEL_REVID(dev_priv) < size)
 272                 return si + INTEL_REVID(dev_priv);
 273
 274         return &no_stepping_info;
 275 }
 276
 277 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 278 {
 279         u32 val, mask;
 280
 281         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 282
 283         if (IS_GEN9_LP(dev_priv))
 284                 mask |= DC_STATE_DEBUG_MASK_CORES;
 285
 286         /* The below bit doesn't need to be cleared ever afterwards */
 287         val = intel_de_read(dev_priv, DC_STATE_DEBUG);
 288         if ((val & mask) != mask) {
 289                 val |= mask;
 290                 intel_de_write(dev_priv, DC_STATE_DEBUG, val);
 291                 intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
 292         }
 293 }
 294
 295 /**
 296  * intel_csr_load_program() - write the firmware from memory to register.
 297  * @dev_priv: i915 drm device.
 298  *
 299  * CSR firmware is read from a .bin file and kept in internal memory one time.
 300  * Everytime display comes back from low power state this function is called to
 301  * copy the firmware from internal memory to registers.
 302  */
 303 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 304 {
 305         u32 *payload = dev_priv->csr.dmc_payload;
 306         u32 i, fw_size;
 307
 308         if (!HAS_CSR(dev_priv)) {
 309                 drm_err(&dev_priv->drm,
 310                         "No CSR support available for this platform\n");
 311                 return;
 312         }
 313
 314         if (!dev_priv->csr.dmc_payload) {
 315                 drm_err(&dev_priv->drm,
 316                         "Tried to program CSR with empty payload\n");
 317                 return;
 318         }
 319
 320         fw_size = dev_priv->csr.dmc_fw_size;
 321         assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 322
 323         preempt_disable();
 324
 325         for (i = 0; i < fw_size; i++)
 326                 intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
 327                                       payload[i]);
 328
 329         preempt_enable();
 330
 331         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 332                 intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
 333                                dev_priv->csr.mmiodata[i]);
 334         }
 335
 336         dev_priv->csr.dc_state = 0;
 337
 338         gen9_set_dc_state_debugmask(dev_priv);
 339 }
 340
 341 /*
 342  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
 343  * already sanitized.
 344  */
 345 static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
 346                               unsigned int num_entries,
 347                               const struct stepping_info *si,
 348                               u8 package_ver)
 349 {
 350         u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
 351         unsigned int i;
 352
 353         for (i = 0; i < num_entries; i++) {
 354                 if (package_ver > 1 && fw_info[i].dmc_id != 0)
 355                         continue;
 356
 357                 if (fw_info[i].substepping == '*' &&
 358                     si->stepping == fw_info[i].stepping) {
 359                         dmc_offset = fw_info[i].offset;
 360                         break;
 361                 }
 362
 363                 if (si->stepping == fw_info[i].stepping &&
 364                     si->substepping == fw_info[i].substepping) {
 365                         dmc_offset = fw_info[i].offset;
 366                         break;
 367                 }
 368
 369                 if (fw_info[i].stepping == '*' &&
 370                     fw_info[i].substepping == '*') {
 371                         /*
 372                          * In theory we should stop the search as generic
 373                          * entries should always come after the more specific
 374                          * ones, but let's continue to make sure to work even
 375                          * with "broken" firmwares. If we don't find a more
 376                          * specific one, then we use this entry
 377                          */
 378                         dmc_offset = fw_info[i].offset;
 379                 }
 380         }
 381
 382         return dmc_offset;
 383 }
 384
 385 static u32 parse_csr_fw_dmc(struct intel_csr *csr,
 386                             const struct intel_dmc_header_base *dmc_header,
 387                             size_t rem_size)
 388 {
 389         unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 390         const u32 *mmioaddr, *mmiodata;
 391         u32 mmio_count, mmio_count_max;
 392         u8 *payload;
 393
 394         BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
 395                      ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
 396
 397         /*
 398          * Check if we can access common fields, we will checkc again below
 399          * after we have read the version
 400          */
 401         if (rem_size < sizeof(struct intel_dmc_header_base))
 402                 goto error_truncated;
 403
 404         /* Cope with small differences between v1 and v3 */
 405         if (dmc_header->header_ver == 3) {
 406                 const struct intel_dmc_header_v3 *v3 =
 407                         (const struct intel_dmc_header_v3 *)dmc_header;
 408
 409                 if (rem_size < sizeof(struct intel_dmc_header_v3))
 410                         goto error_truncated;
 411
 412                 mmioaddr = v3->mmioaddr;
 413                 mmiodata = v3->mmiodata;
 414                 mmio_count = v3->mmio_count;
 415                 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
 416                 /* header_len is in dwords */
 417                 header_len_bytes = dmc_header->header_len * 4;
 418                 dmc_header_size = sizeof(*v3);
 419         } else if (dmc_header->header_ver == 1) {
 420                 const struct intel_dmc_header_v1 *v1 =
 421                         (const struct intel_dmc_header_v1 *)dmc_header;
 422
 423                 if (rem_size < sizeof(struct intel_dmc_header_v1))
 424                         goto error_truncated;
 425
 426                 mmioaddr = v1->mmioaddr;
 427                 mmiodata = v1->mmiodata;
 428                 mmio_count = v1->mmio_count;
 429                 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
 430                 header_len_bytes = dmc_header->header_len;
 431                 dmc_header_size = sizeof(*v1);
 432         } else {
 433                 DRM_ERROR("Unknown DMC fw header version: %u\n",
 434                           dmc_header->header_ver);
 435                 return 0;
 436         }
 437
 438         if (header_len_bytes != dmc_header_size) {
 439                 DRM_ERROR("DMC firmware has wrong dmc header length "
 440                           "(%u bytes)\n", header_len_bytes);
 441                 return 0;
 442         }
 443
 444         /* Cache the dmc header info. */
 445         if (mmio_count > mmio_count_max) {
 446                 DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
 447                 return 0;
 448         }
 449
 450         for (i = 0; i < mmio_count; i++) {
 451                 if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
 452                     mmioaddr[i] > CSR_MMIO_END_RANGE) {
 453                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 454                                   mmioaddr[i]);
 455                         return 0;
 456                 }
 457                 csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
 458                 csr->mmiodata[i] = mmiodata[i];
 459         }
 460         csr->mmio_count = mmio_count;
 461
 462         rem_size -= header_len_bytes;
 463
 464         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 465         payload_size = dmc_header->fw_size * 4;
 466         if (rem_size < payload_size)
 467                 goto error_truncated;
 468
 469         if (payload_size > csr->max_fw_size) {
 470                 DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
 471                 return 0;
 472         }
 473         csr->dmc_fw_size = dmc_header->fw_size;
 474
 475         csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
 476         if (!csr->dmc_payload) {
 477                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 478                 return 0;
 479         }
 480
 481         payload = (u8 *)(dmc_header) + header_len_bytes;
 482         memcpy(csr->dmc_payload, payload, payload_size);
 483
 484         return header_len_bytes + payload_size;
 485
 486 error_truncated:
 487         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 488         return 0;
 489 }
 490
 491 static u32
 492 parse_csr_fw_package(struct intel_csr *csr,
 493                      const struct intel_package_header *package_header,
 494                      const struct stepping_info *si,
 495                      size_t rem_size)
 496 {
 497         u32 package_size = sizeof(struct intel_package_header);
 498         u32 num_entries, max_entries, dmc_offset;
 499         const struct intel_fw_info *fw_info;
 500
 501         if (rem_size < package_size)
 502                 goto error_truncated;
 503
 504         if (package_header->header_ver == 1) {
 505                 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
 506         } else if (package_header->header_ver == 2) {
 507                 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
 508         } else {
 509                 DRM_ERROR("DMC firmware has unknown header version %u\n",
 510                           package_header->header_ver);
 511                 return 0;
 512         }
 513
 514         /*
 515          * We should always have space for max_entries,
 516          * even if not all are used
 517          */
 518         package_size += max_entries * sizeof(struct intel_fw_info);
 519         if (rem_size < package_size)
 520                 goto error_truncated;
 521
 522         if (package_header->header_len * 4 != package_size) {
 523                 DRM_ERROR("DMC firmware has wrong package header length "
 524                           "(%u bytes)\n", package_size);
 525                 return 0;
 526         }
 527
 528         num_entries = package_header->num_entries;
 529         if (WARN_ON(package_header->num_entries > max_entries))
 530                 num_entries = max_entries;
 531
 532         fw_info = (const struct intel_fw_info *)
 533                 ((u8 *)package_header + sizeof(*package_header));
 534         dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
 535                                         package_header->header_ver);
 536         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 537                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 538                           si->stepping);
 539                 return 0;
 540         }
 541
 542         /* dmc_offset is in dwords */
 543         return package_size + dmc_offset * 4;
 544
 545 error_truncated:
 546         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 547         return 0;
 548 }
 549
 550 /* Return number of bytes parsed or 0 on error */
 551 static u32 parse_csr_fw_css(struct intel_csr *csr,
 552                             struct intel_css_header *css_header,
 553                             size_t rem_size)
 554 {
 555         if (rem_size < sizeof(struct intel_css_header)) {
 556                 DRM_ERROR("Truncated DMC firmware, refusing.\n");
 557                 return 0;
 558         }
 559
 560         if (sizeof(struct intel_css_header) !=
 561             (css_header->header_len * 4)) {
 562                 DRM_ERROR("DMC firmware has wrong CSS header length "
 563                           "(%u bytes)\n",
 564                           (css_header->header_len * 4));
 565                 return 0;
 566         }
 567
 568         if (csr->required_version &&
 569             css_header->version != csr->required_version) {
 570                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 571                          " please use v%u.%u\n",
 572                          CSR_VERSION_MAJOR(css_header->version),
 573                          CSR_VERSION_MINOR(css_header->version),
 574                          CSR_VERSION_MAJOR(csr->required_version),
 575                          CSR_VERSION_MINOR(csr->required_version));
 576                 return 0;
 577         }
 578
 579         csr->version = css_header->version;
 580
 581         return sizeof(struct intel_css_header);
 582 }
 583
 584 static void parse_csr_fw(struct drm_i915_private *dev_priv,
 585                          const struct firmware *fw)
 586 {
 587         struct intel_css_header *css_header;
 588         struct intel_package_header *package_header;
 589         struct intel_dmc_header_base *dmc_header;
 590         struct intel_csr *csr = &dev_priv->csr;
 591         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 592         u32 readcount = 0;
 593         u32 r;
 594
 595         if (!fw)
 596                 return;
 597
 598         /* Extract CSS Header information */
 599         css_header = (struct intel_css_header *)fw->data;
 600         r = parse_csr_fw_css(csr, css_header, fw->size);
 601         if (!r)
 602                 return;
 603
 604         readcount += r;
 605
 606         /* Extract Package Header information */
 607         package_header = (struct intel_package_header *)&fw->data[readcount];
 608         r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
 609         if (!r)
 610                 return;
 611
 612         readcount += r;
 613
 614         /* Extract dmc_header information */
 615         dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
 616         parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
 617 }
 618
 619 static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
 620 {
 621         drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
 622         dev_priv->csr.wakeref =
 623                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 624 }
 625
 626 static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
 627 {
 628         intel_wakeref_t wakeref __maybe_unused =
 629                 fetch_and_zero(&dev_priv->csr.wakeref);
 630
 631         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
 632 }
 633
 634 static void csr_load_work_fn(struct work_struct *work)
 635 {
 636         struct drm_i915_private *dev_priv;
 637         struct intel_csr *csr;
 638         const struct firmware *fw = NULL;
 639
 640         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 641         csr = &dev_priv->csr;
 642
 643         request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 644         parse_csr_fw(dev_priv, fw);
 645
 646         if (dev_priv->csr.dmc_payload) {
 647                 intel_csr_load_program(dev_priv);
 648                 intel_csr_runtime_pm_put(dev_priv);
 649
 650                 drm_info(&dev_priv->drm,
 651                          "Finished loading DMC firmware %s (v%u.%u)\n",
 652                          dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version),
 653                          CSR_VERSION_MINOR(csr->version));
 654         } else {
 655                 drm_notice(&dev_priv->drm,
 656                            "Failed to load DMC firmware %s."
 657                            " Disabling runtime power management.\n",
 658                            csr->fw_path);
 659                 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
 660                            INTEL_UC_FIRMWARE_URL);
 661         }
 662
 663         release_firmware(fw);
 664 }
 665
 666 /**
 667  * intel_csr_ucode_init() - initialize the firmware loading.
 668  * @dev_priv: i915 drm device.
 669  *
 670  * This function is called at the time of loading the display driver to read
 671  * firmware from a .bin file and copied into a internal memory.
 672  */
 673 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 674 {
 675         struct intel_csr *csr = &dev_priv->csr;
 676
 677         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 678
 679         if (!HAS_CSR(dev_priv))
 680                 return;
 681
 682         /*
 683          * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
 684          * runtime-suspend.
 685          *
 686          * On error, we return with the rpm wakeref held to prevent runtime
 687          * suspend as runtime suspend *requires* a working CSR for whatever
 688          * reason.
 689          */
 690         intel_csr_runtime_pm_get(dev_priv);
 691
 692         if (IS_DG1(dev_priv)) {
 693                 csr->fw_path = DG1_CSR_PATH;
 694                 csr->required_version = DG1_CSR_VERSION_REQUIRED;
 695                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 696         } else if (IS_ROCKETLAKE(dev_priv)) {
 697                 csr->fw_path = RKL_CSR_PATH;
 698                 csr->required_version = RKL_CSR_VERSION_REQUIRED;
 699                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 700         } else if (INTEL_GEN(dev_priv) >= 12) {
 701                 csr->fw_path = TGL_CSR_PATH;
 702                 csr->required_version = TGL_CSR_VERSION_REQUIRED;
 703                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 704         } else if (IS_GEN(dev_priv, 11)) {
 705                 csr->fw_path = ICL_CSR_PATH;
 706                 csr->required_version = ICL_CSR_VERSION_REQUIRED;
 707                 csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
 708         } else if (IS_CANNONLAKE(dev_priv)) {
 709                 csr->fw_path = CNL_CSR_PATH;
 710                 csr->required_version = CNL_CSR_VERSION_REQUIRED;
 711                 csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
 712         } else if (IS_GEMINILAKE(dev_priv)) {
 713                 csr->fw_path = GLK_CSR_PATH;
 714                 csr->required_version = GLK_CSR_VERSION_REQUIRED;
 715                 csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
 716         } else if (IS_KABYLAKE(dev_priv) ||
 717                    IS_COFFEELAKE(dev_priv) ||
 718                    IS_COMETLAKE(dev_priv)) {
 719                 csr->fw_path = KBL_CSR_PATH;
 720                 csr->required_version = KBL_CSR_VERSION_REQUIRED;
 721                 csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
 722         } else if (IS_SKYLAKE(dev_priv)) {
 723                 csr->fw_path = SKL_CSR_PATH;
 724                 csr->required_version = SKL_CSR_VERSION_REQUIRED;
 725                 csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
 726         } else if (IS_BROXTON(dev_priv)) {
 727                 csr->fw_path = BXT_CSR_PATH;
 728                 csr->required_version = BXT_CSR_VERSION_REQUIRED;
 729                 csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
 730         }
 731
 732         if (dev_priv->params.dmc_firmware_path) {
 733                 if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
 734                         csr->fw_path = NULL;
 735                         drm_info(&dev_priv->drm,
 736                                  "Disabling CSR firmware and runtime PM\n");
 737                         return;
 738                 }
 739
 740                 csr->fw_path = dev_priv->params.dmc_firmware_path;
 741                 /* Bypass version check for firmware override. */
 742                 csr->required_version = 0;
 743         }
 744
 745         if (csr->fw_path == NULL) {
 746                 drm_dbg_kms(&dev_priv->drm,
 747                             "No known CSR firmware for platform, disabling runtime PM\n");
 748                 return;
 749         }
 750
 751         drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path);
 752         schedule_work(&dev_priv->csr.work);
 753 }
 754
 755 /**
 756  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 757  * @dev_priv: i915 drm device
 758  *
 759  * Prepare the DMC firmware before entering system suspend. This includes
 760  * flushing pending work items and releasing any resources acquired during
 761  * init.
 762  */
 763 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 764 {
 765         if (!HAS_CSR(dev_priv))
 766                 return;
 767
 768         flush_work(&dev_priv->csr.work);
 769
 770         /* Drop the reference held in case DMC isn't loaded. */
 771         if (!dev_priv->csr.dmc_payload)
 772                 intel_csr_runtime_pm_put(dev_priv);
 773 }
 774
 775 /**
 776  * intel_csr_ucode_resume() - init CSR firmware during system resume
 777  * @dev_priv: i915 drm device
 778  *
 779  * Reinitialize the DMC firmware during system resume, reacquiring any
 780  * resources released in intel_csr_ucode_suspend().
 781  */
 782 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 783 {
 784         if (!HAS_CSR(dev_priv))
 785                 return;
 786
 787         /*
 788          * Reacquire the reference to keep RPM disabled in case DMC isn't
 789          * loaded.
 790          */
 791         if (!dev_priv->csr.dmc_payload)
 792                 intel_csr_runtime_pm_get(dev_priv);
 793 }
 794
 795 /**
 796  * intel_csr_ucode_fini() - unload the CSR firmware.
 797  * @dev_priv: i915 drm device.
 798  *
 799  * Firmmware unloading includes freeing the internal memory and reset the
 800  * firmware loading status.
 801  */
 802 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 803 {
 804         if (!HAS_CSR(dev_priv))
 805                 return;
 806
 807         intel_csr_ucode_suspend(dev_priv);
 808         drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
 809
 810         kfree(dev_priv->csr.dmc_payload);
 811 }