drivers/gpu/drm/i915/display/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_edid.h>
  34 #include <drm/drm_probe_helper.h>
  35
  36 #include "i915_drv.h"
  37 #include "intel_connector.h"
  38 #include "intel_crt.h"
  39 #include "intel_ddi.h"
  40 #include "intel_display_types.h"
  41 #include "intel_fifo_underrun.h"
  42 #include "intel_gmbus.h"
  43 #include "intel_hotplug.h"
  44
  45 /* Here's the desired hotplug mode */
  46 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  47                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  48                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  49                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  50                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  51                            ADPA_CRT_HOTPLUG_ENABLE)
  52
  53 struct intel_crt {
  54         struct intel_encoder base;
  55         /* DPMS state is stored in the connector, which we need in the
  56          * encoder's enable/disable callbacks */
  57         struct intel_connector *connector;
  58         bool force_hotplug_required;
  59         i915_reg_t adpa_reg;
  60 };
  61
  62 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  63 {
  64         return container_of(encoder, struct intel_crt, base);
  65 }
  66
  67 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
  68 {
  69         return intel_encoder_to_crt(intel_attached_encoder(connector));
  70 }
  71
  72 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  73                             i915_reg_t adpa_reg, enum pipe *pipe)
  74 {
  75         u32 val;
  76
  77         val = intel_de_read(dev_priv, adpa_reg);
  78
  79         /* asserts want to know the pipe even if the port is disabled */
  80         if (HAS_PCH_CPT(dev_priv))
  81                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  82         else
  83                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  84
  85         return val & ADPA_DAC_ENABLE;
  86 }
  87
  88 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  89                                    enum pipe *pipe)
  90 {
  91         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  92         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  93         intel_wakeref_t wakeref;
  94         bool ret;
  95
  96         wakeref = intel_display_power_get_if_enabled(dev_priv,
  97                                                      encoder->power_domain);
  98         if (!wakeref)
  99                 return false;
 100
 101         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
 102
 103         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 104
 105         return ret;
 106 }
 107
 108 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 109 {
 110         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 111         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 112         u32 tmp, flags = 0;
 113
 114         tmp = intel_de_read(dev_priv, crt->adpa_reg);
 115
 116         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 117                 flags |= DRM_MODE_FLAG_PHSYNC;
 118         else
 119                 flags |= DRM_MODE_FLAG_NHSYNC;
 120
 121         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 122                 flags |= DRM_MODE_FLAG_PVSYNC;
 123         else
 124                 flags |= DRM_MODE_FLAG_NVSYNC;
 125
 126         return flags;
 127 }
 128
 129 static void intel_crt_get_config(struct intel_encoder *encoder,
 130                                  struct intel_crtc_state *pipe_config)
 131 {
 132         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 133
 134         pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 135
 136         pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 137 }
 138
 139 static void hsw_crt_get_config(struct intel_encoder *encoder,
 140                                struct intel_crtc_state *pipe_config)
 141 {
 142         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 143
 144         intel_ddi_get_config(encoder, pipe_config);
 145
 146         pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 147                                               DRM_MODE_FLAG_NHSYNC |
 148                                               DRM_MODE_FLAG_PVSYNC |
 149                                               DRM_MODE_FLAG_NVSYNC);
 150         pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 151
 152         pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 153 }
 154
 155 /* Note: The caller is required to filter out dpms modes not supported by the
 156  * platform. */
 157 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 158                                const struct intel_crtc_state *crtc_state,
 159                                int mode)
 160 {
 161         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 162         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 163         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 164         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 165         u32 adpa;
 166
 167         if (INTEL_GEN(dev_priv) >= 5)
 168                 adpa = ADPA_HOTPLUG_BITS;
 169         else
 170                 adpa = 0;
 171
 172         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 173                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 174         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 175                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 176
 177         /* For CPT allow 3 pipe config, for others just use A or B */
 178         if (HAS_PCH_LPT(dev_priv))
 179                 ; /* Those bits don't exist here */
 180         else if (HAS_PCH_CPT(dev_priv))
 181                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 182         else
 183                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 184
 185         if (!HAS_PCH_SPLIT(dev_priv))
 186                 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
 187
 188         switch (mode) {
 189         case DRM_MODE_DPMS_ON:
 190                 adpa |= ADPA_DAC_ENABLE;
 191                 break;
 192         case DRM_MODE_DPMS_STANDBY:
 193                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 194                 break;
 195         case DRM_MODE_DPMS_SUSPEND:
 196                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 197                 break;
 198         case DRM_MODE_DPMS_OFF:
 199                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 200                 break;
 201         }
 202
 203         intel_de_write(dev_priv, crt->adpa_reg, adpa);
 204 }
 205
 206 static void intel_disable_crt(struct intel_encoder *encoder,
 207                               const struct intel_crtc_state *old_crtc_state,
 208                               const struct drm_connector_state *old_conn_state)
 209 {
 210         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 211 }
 212
 213 static void pch_disable_crt(struct intel_encoder *encoder,
 214                             const struct intel_crtc_state *old_crtc_state,
 215                             const struct drm_connector_state *old_conn_state)
 216 {
 217 }
 218
 219 static void pch_post_disable_crt(struct intel_encoder *encoder,
 220                                  const struct intel_crtc_state *old_crtc_state,
 221                                  const struct drm_connector_state *old_conn_state)
 222 {
 223         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 224 }
 225
 226 static void hsw_disable_crt(struct intel_encoder *encoder,
 227                             const struct intel_crtc_state *old_crtc_state,
 228                             const struct drm_connector_state *old_conn_state)
 229 {
 230         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 231
 232         drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
 233
 234         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 235 }
 236
 237 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 238                                  const struct intel_crtc_state *old_crtc_state,
 239                                  const struct drm_connector_state *old_conn_state)
 240 {
 241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 242
 243         intel_crtc_vblank_off(old_crtc_state);
 244
 245         intel_disable_pipe(old_crtc_state);
 246
 247         intel_ddi_disable_transcoder_func(old_crtc_state);
 248
 249         ilk_pfit_disable(old_crtc_state);
 250
 251         intel_ddi_disable_pipe_clock(old_crtc_state);
 252
 253         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 254
 255         lpt_disable_pch_transcoder(dev_priv);
 256         lpt_disable_iclkip(dev_priv);
 257
 258         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 259
 260         drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
 261
 262         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 263 }
 264
 265 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 266                                    const struct intel_crtc_state *crtc_state,
 267                                    const struct drm_connector_state *conn_state)
 268 {
 269         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 270
 271         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 272
 273         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 274 }
 275
 276 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 277                                const struct intel_crtc_state *crtc_state,
 278                                const struct drm_connector_state *conn_state)
 279 {
 280         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 281         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 282         enum pipe pipe = crtc->pipe;
 283
 284         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 285
 286         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 287
 288         hsw_fdi_link_train(encoder, crtc_state);
 289
 290         intel_ddi_enable_pipe_clock(crtc_state);
 291 }
 292
 293 static void hsw_enable_crt(struct intel_encoder *encoder,
 294                            const struct intel_crtc_state *crtc_state,
 295                            const struct drm_connector_state *conn_state)
 296 {
 297         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 298         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 299         enum pipe pipe = crtc->pipe;
 300
 301         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 302
 303         intel_enable_pipe(crtc_state);
 304
 305         lpt_pch_enable(crtc_state);
 306
 307         intel_crtc_vblank_on(crtc_state);
 308
 309         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 310
 311         intel_wait_for_vblank(dev_priv, pipe);
 312         intel_wait_for_vblank(dev_priv, pipe);
 313         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 314         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 315 }
 316
 317 static void intel_enable_crt(struct intel_encoder *encoder,
 318                              const struct intel_crtc_state *crtc_state,
 319                              const struct drm_connector_state *conn_state)
 320 {
 321         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 322 }
 323
 324 static enum drm_mode_status
 325 intel_crt_mode_valid(struct drm_connector *connector,
 326                      struct drm_display_mode *mode)
 327 {
 328         struct drm_device *dev = connector->dev;
 329         struct drm_i915_private *dev_priv = to_i915(dev);
 330         int max_dotclk = dev_priv->max_dotclk_freq;
 331         int max_clock;
 332
 333         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 334                 return MODE_NO_DBLESCAN;
 335
 336         if (mode->clock < 25000)
 337                 return MODE_CLOCK_LOW;
 338
 339         if (HAS_PCH_LPT(dev_priv))
 340                 max_clock = 180000;
 341         else if (IS_VALLEYVIEW(dev_priv))
 342                 /*
 343                  * 270 MHz due to current DPLL limits,
 344                  * DAC limit supposedly 355 MHz.
 345                  */
 346                 max_clock = 270000;
 347         else if (IS_GEN_RANGE(dev_priv, 3, 4))
 348                 max_clock = 400000;
 349         else
 350                 max_clock = 350000;
 351         if (mode->clock > max_clock)
 352                 return MODE_CLOCK_HIGH;
 353
 354         if (mode->clock > max_dotclk)
 355                 return MODE_CLOCK_HIGH;
 356
 357         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 358         if (HAS_PCH_LPT(dev_priv) &&
 359             ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
 360                 return MODE_CLOCK_HIGH;
 361
 362         /* HSW/BDW FDI limited to 4k */
 363         if (mode->hdisplay > 4096)
 364                 return MODE_H_ILLEGAL;
 365
 366         return MODE_OK;
 367 }
 368
 369 static int intel_crt_compute_config(struct intel_encoder *encoder,
 370                                     struct intel_crtc_state *pipe_config,
 371                                     struct drm_connector_state *conn_state)
 372 {
 373         struct drm_display_mode *adjusted_mode =
 374                 &pipe_config->hw.adjusted_mode;
 375
 376         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 377                 return -EINVAL;
 378
 379         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 380
 381         return 0;
 382 }
 383
 384 static int pch_crt_compute_config(struct intel_encoder *encoder,
 385                                   struct intel_crtc_state *pipe_config,
 386                                   struct drm_connector_state *conn_state)
 387 {
 388         struct drm_display_mode *adjusted_mode =
 389                 &pipe_config->hw.adjusted_mode;
 390
 391         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 392                 return -EINVAL;
 393
 394         pipe_config->has_pch_encoder = true;
 395         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 396
 397         return 0;
 398 }
 399
 400 static int hsw_crt_compute_config(struct intel_encoder *encoder,
 401                                   struct intel_crtc_state *pipe_config,
 402                                   struct drm_connector_state *conn_state)
 403 {
 404         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 405         struct drm_display_mode *adjusted_mode =
 406                 &pipe_config->hw.adjusted_mode;
 407
 408         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 409                 return -EINVAL;
 410
 411         /* HSW/BDW FDI limited to 4k */
 412         if (adjusted_mode->crtc_hdisplay > 4096 ||
 413             adjusted_mode->crtc_hblank_start > 4096)
 414                 return -EINVAL;
 415
 416         pipe_config->has_pch_encoder = true;
 417         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 418
 419         /* LPT FDI RX only supports 8bpc. */
 420         if (HAS_PCH_LPT(dev_priv)) {
 421                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 422                         drm_dbg_kms(&dev_priv->drm,
 423                                     "LPT only supports 24bpp\n");
 424                         return -EINVAL;
 425                 }
 426
 427                 pipe_config->pipe_bpp = 24;
 428         }
 429
 430         /* FDI must always be 2.7 GHz */
 431         pipe_config->port_clock = 135000 * 2;
 432
 433         return 0;
 434 }
 435
 436 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
 437 {
 438         struct drm_device *dev = connector->dev;
 439         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 440         struct drm_i915_private *dev_priv = to_i915(dev);
 441         u32 adpa;
 442         bool ret;
 443
 444         /* The first time through, trigger an explicit detection cycle */
 445         if (crt->force_hotplug_required) {
 446                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 447                 u32 save_adpa;
 448
 449                 crt->force_hotplug_required = false;
 450
 451                 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
 452                 drm_dbg_kms(&dev_priv->drm,
 453                             "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 454
 455                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 456                 if (turn_off_dac)
 457                         adpa &= ~ADPA_DAC_ENABLE;
 458
 459                 intel_de_write(dev_priv, crt->adpa_reg, adpa);
 460
 461                 if (intel_de_wait_for_clear(dev_priv,
 462                                             crt->adpa_reg,
 463                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
 464                                             1000))
 465                         drm_dbg_kms(&dev_priv->drm,
 466                                     "timed out waiting for FORCE_TRIGGER");
 467
 468                 if (turn_off_dac) {
 469                         intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
 470                         intel_de_posting_read(dev_priv, crt->adpa_reg);
 471                 }
 472         }
 473
 474         /* Check the status to see if both blue and green are on now */
 475         adpa = intel_de_read(dev_priv, crt->adpa_reg);
 476         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 477                 ret = true;
 478         else
 479                 ret = false;
 480         drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
 481                     adpa, ret);
 482
 483         return ret;
 484 }
 485
 486 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 487 {
 488         struct drm_device *dev = connector->dev;
 489         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 490         struct drm_i915_private *dev_priv = to_i915(dev);
 491         bool reenable_hpd;
 492         u32 adpa;
 493         bool ret;
 494         u32 save_adpa;
 495
 496         /*
 497          * Doing a force trigger causes a hpd interrupt to get sent, which can
 498          * get us stuck in a loop if we're polling:
 499          *  - We enable power wells and reset the ADPA
 500          *  - output_poll_exec does force probe on VGA, triggering a hpd
 501          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 502          *  - output_poll_exec shuts off the ADPA, unlocks
 503          *    dev->mode_config.mutex
 504          *  - HPD handler runs, resets ADPA and brings us back to the start
 505          *
 506          * Just disable HPD interrupts here to prevent this
 507          */
 508         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 509
 510         save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
 511         drm_dbg_kms(&dev_priv->drm,
 512                     "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 513
 514         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 515
 516         intel_de_write(dev_priv, crt->adpa_reg, adpa);
 517
 518         if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
 519                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
 520                 drm_dbg_kms(&dev_priv->drm,
 521                             "timed out waiting for FORCE_TRIGGER");
 522                 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
 523         }
 524
 525         /* Check the status to see if both blue and green are on now */
 526         adpa = intel_de_read(dev_priv, crt->adpa_reg);
 527         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 528                 ret = true;
 529         else
 530                 ret = false;
 531
 532         drm_dbg_kms(&dev_priv->drm,
 533                     "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 534
 535         if (reenable_hpd)
 536                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 537
 538         return ret;
 539 }
 540
 541 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 542 {
 543         struct drm_device *dev = connector->dev;
 544         struct drm_i915_private *dev_priv = to_i915(dev);
 545         u32 stat;
 546         bool ret = false;
 547         int i, tries = 0;
 548
 549         if (HAS_PCH_SPLIT(dev_priv))
 550                 return ilk_crt_detect_hotplug(connector);
 551
 552         if (IS_VALLEYVIEW(dev_priv))
 553                 return valleyview_crt_detect_hotplug(connector);
 554
 555         /*
 556          * On 4 series desktop, CRT detect sequence need to be done twice
 557          * to get a reliable result.
 558          */
 559
 560         if (IS_G45(dev_priv))
 561                 tries = 2;
 562         else
 563                 tries = 1;
 564
 565         for (i = 0; i < tries ; i++) {
 566                 /* turn on the FORCE_DETECT */
 567                 i915_hotplug_interrupt_update(dev_priv,
 568                                               CRT_HOTPLUG_FORCE_DETECT,
 569                                               CRT_HOTPLUG_FORCE_DETECT);
 570                 /* wait for FORCE_DETECT to go off */
 571                 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
 572                                             CRT_HOTPLUG_FORCE_DETECT, 1000))
 573                         drm_dbg_kms(&dev_priv->drm,
 574                                     "timed out waiting for FORCE_DETECT to go off");
 575         }
 576
 577         stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
 578         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 579                 ret = true;
 580
 581         /* clear the interrupt we just generated, if any */
 582         intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 583
 584         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 585
 586         return ret;
 587 }
 588
 589 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 590                                 struct i2c_adapter *i2c)
 591 {
 592         struct edid *edid;
 593
 594         edid = drm_get_edid(connector, i2c);
 595
 596         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 597                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 598                 intel_gmbus_force_bit(i2c, true);
 599                 edid = drm_get_edid(connector, i2c);
 600                 intel_gmbus_force_bit(i2c, false);
 601         }
 602
 603         return edid;
 604 }
 605
 606 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 607 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 608                                 struct i2c_adapter *adapter)
 609 {
 610         struct edid *edid;
 611         int ret;
 612
 613         edid = intel_crt_get_edid(connector, adapter);
 614         if (!edid)
 615                 return 0;
 616
 617         ret = intel_connector_update_modes(connector, edid);
 618         kfree(edid);
 619
 620         return ret;
 621 }
 622
 623 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 624 {
 625         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 626         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 627         struct edid *edid;
 628         struct i2c_adapter *i2c;
 629         bool ret = false;
 630
 631         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 632
 633         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 634         edid = intel_crt_get_edid(connector, i2c);
 635
 636         if (edid) {
 637                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 638
 639                 /*
 640                  * This may be a DVI-I connector with a shared DDC
 641                  * link between analog and digital outputs, so we
 642                  * have to check the EDID input spec of the attached device.
 643                  */
 644                 if (!is_digital) {
 645                         drm_dbg_kms(&dev_priv->drm,
 646                                     "CRT detected via DDC:0x50 [EDID]\n");
 647                         ret = true;
 648                 } else {
 649                         drm_dbg_kms(&dev_priv->drm,
 650                                     "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 651                 }
 652         } else {
 653                 drm_dbg_kms(&dev_priv->drm,
 654                             "CRT not detected via DDC:0x50 [no valid EDID found]\n");
 655         }
 656
 657         kfree(edid);
 658
 659         return ret;
 660 }
 661
 662 static enum drm_connector_status
 663 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
 664 {
 665         struct drm_device *dev = crt->base.base.dev;
 666         struct drm_i915_private *dev_priv = to_i915(dev);
 667         struct intel_uncore *uncore = &dev_priv->uncore;
 668         u32 save_bclrpat;
 669         u32 save_vtotal;
 670         u32 vtotal, vactive;
 671         u32 vsample;
 672         u32 vblank, vblank_start, vblank_end;
 673         u32 dsl;
 674         i915_reg_t bclrpat_reg, vtotal_reg,
 675                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 676         u8 st00;
 677         enum drm_connector_status status;
 678
 679         drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
 680
 681         bclrpat_reg = BCLRPAT(pipe);
 682         vtotal_reg = VTOTAL(pipe);
 683         vblank_reg = VBLANK(pipe);
 684         vsync_reg = VSYNC(pipe);
 685         pipeconf_reg = PIPECONF(pipe);
 686         pipe_dsl_reg = PIPEDSL(pipe);
 687
 688         save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
 689         save_vtotal = intel_uncore_read(uncore, vtotal_reg);
 690         vblank = intel_uncore_read(uncore, vblank_reg);
 691
 692         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 693         vactive = (save_vtotal & 0x7ff) + 1;
 694
 695         vblank_start = (vblank & 0xfff) + 1;
 696         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 697
 698         /* Set the border color to purple. */
 699         intel_uncore_write(uncore, bclrpat_reg, 0x500050);
 700
 701         if (!IS_GEN(dev_priv, 2)) {
 702                 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
 703                 intel_uncore_write(uncore,
 704                                    pipeconf_reg,
 705                                    pipeconf | PIPECONF_FORCE_BORDER);
 706                 intel_uncore_posting_read(uncore, pipeconf_reg);
 707                 /* Wait for next Vblank to substitue
 708                  * border color for Color info */
 709                 intel_wait_for_vblank(dev_priv, pipe);
 710                 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
 711                 status = ((st00 & (1 << 4)) != 0) ?
 712                         connector_status_connected :
 713                         connector_status_disconnected;
 714
 715                 intel_uncore_write(uncore, pipeconf_reg, pipeconf);
 716         } else {
 717                 bool restore_vblank = false;
 718                 int count, detect;
 719
 720                 /*
 721                 * If there isn't any border, add some.
 722                 * Yes, this will flicker
 723                 */
 724                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 725                         u32 vsync = intel_de_read(dev_priv, vsync_reg);
 726                         u32 vsync_start = (vsync & 0xffff) + 1;
 727
 728                         vblank_start = vsync_start;
 729                         intel_uncore_write(uncore,
 730                                            vblank_reg,
 731                                            (vblank_start - 1) |
 732                                            ((vblank_end - 1) << 16));
 733                         restore_vblank = true;
 734                 }
 735                 /* sample in the vertical border, selecting the larger one */
 736                 if (vblank_start - vactive >= vtotal - vblank_end)
 737                         vsample = (vblank_start + vactive) >> 1;
 738                 else
 739                         vsample = (vtotal + vblank_end) >> 1;
 740
 741                 /*
 742                  * Wait for the border to be displayed
 743                  */
 744                 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
 745                         ;
 746                 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
 747                        vsample)
 748                         ;
 749                 /*
 750                  * Watch ST00 for an entire scanline
 751                  */
 752                 detect = 0;
 753                 count = 0;
 754                 do {
 755                         count++;
 756                         /* Read the ST00 VGA status register */
 757                         st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
 758                         if (st00 & (1 << 4))
 759                                 detect++;
 760                 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
 761
 762                 /* restore vblank if necessary */
 763                 if (restore_vblank)
 764                         intel_uncore_write(uncore, vblank_reg, vblank);
 765                 /*
 766                  * If more than 3/4 of the scanline detected a monitor,
 767                  * then it is assumed to be present. This works even on i830,
 768                  * where there isn't any way to force the border color across
 769                  * the screen
 770                  */
 771                 status = detect * 4 > count * 3 ?
 772                          connector_status_connected :
 773                          connector_status_disconnected;
 774         }
 775
 776         /* Restore previous settings */
 777         intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
 778
 779         return status;
 780 }
 781
 782 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 783 {
 784         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 785         return 1;
 786 }
 787
 788 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 789         {
 790                 .callback = intel_spurious_crt_detect_dmi_callback,
 791                 .ident = "ACER ZGB",
 792                 .matches = {
 793                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 794                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 795                 },
 796         },
 797         {
 798                 .callback = intel_spurious_crt_detect_dmi_callback,
 799                 .ident = "Intel DZ77BH-55K",
 800                 .matches = {
 801                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 802                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 803                 },
 804         },
 805         { }
 806 };
 807
 808 static int
 809 intel_crt_detect(struct drm_connector *connector,
 810                  struct drm_modeset_acquire_ctx *ctx,
 811                  bool force)
 812 {
 813         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 814         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 815         struct intel_encoder *intel_encoder = &crt->base;
 816         intel_wakeref_t wakeref;
 817         int status, ret;
 818         struct intel_load_detect_pipe tmp;
 819
 820         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
 821                     connector->base.id, connector->name,
 822                     force);
 823
 824         if (i915_modparams.load_detect_test) {
 825                 wakeref = intel_display_power_get(dev_priv,
 826                                                   intel_encoder->power_domain);
 827                 goto load_detect;
 828         }
 829
 830         /* Skip machines without VGA that falsely report hotplug events */
 831         if (dmi_check_system(intel_spurious_crt_detect))
 832                 return connector_status_disconnected;
 833
 834         wakeref = intel_display_power_get(dev_priv,
 835                                           intel_encoder->power_domain);
 836
 837         if (I915_HAS_HOTPLUG(dev_priv)) {
 838                 /* We can not rely on the HPD pin always being correctly wired
 839                  * up, for example many KVM do not pass it through, and so
 840                  * only trust an assertion that the monitor is connected.
 841                  */
 842                 if (intel_crt_detect_hotplug(connector)) {
 843                         drm_dbg_kms(&dev_priv->drm,
 844                                     "CRT detected via hotplug\n");
 845                         status = connector_status_connected;
 846                         goto out;
 847                 } else
 848                         drm_dbg_kms(&dev_priv->drm,
 849                                     "CRT not detected via hotplug\n");
 850         }
 851
 852         if (intel_crt_detect_ddc(connector)) {
 853                 status = connector_status_connected;
 854                 goto out;
 855         }
 856
 857         /* Load detection is broken on HPD capable machines. Whoever wants a
 858          * broken monitor (without edid) to work behind a broken kvm (that fails
 859          * to have the right resistors for HP detection) needs to fix this up.
 860          * For now just bail out. */
 861         if (I915_HAS_HOTPLUG(dev_priv)) {
 862                 status = connector_status_disconnected;
 863                 goto out;
 864         }
 865
 866 load_detect:
 867         if (!force) {
 868                 status = connector->status;
 869                 goto out;
 870         }
 871
 872         /* for pre-945g platforms use load detect */
 873         ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
 874         if (ret > 0) {
 875                 if (intel_crt_detect_ddc(connector))
 876                         status = connector_status_connected;
 877                 else if (INTEL_GEN(dev_priv) < 4)
 878                         status = intel_crt_load_detect(crt,
 879                                 to_intel_crtc(connector->state->crtc)->pipe);
 880                 else if (i915_modparams.load_detect_test)
 881                         status = connector_status_disconnected;
 882                 else
 883                         status = connector_status_unknown;
 884                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 885         } else if (ret == 0) {
 886                 status = connector_status_unknown;
 887         } else {
 888                 status = ret;
 889         }
 890
 891 out:
 892         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 893
 894         /*
 895          * Make sure the refs for power wells enabled during detect are
 896          * dropped to avoid a new detect cycle triggered by HPD polling.
 897          */
 898         intel_display_power_flush_work(dev_priv);
 899
 900         return status;
 901 }
 902
 903 static int intel_crt_get_modes(struct drm_connector *connector)
 904 {
 905         struct drm_device *dev = connector->dev;
 906         struct drm_i915_private *dev_priv = to_i915(dev);
 907         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 908         struct intel_encoder *intel_encoder = &crt->base;
 909         intel_wakeref_t wakeref;
 910         struct i2c_adapter *i2c;
 911         int ret;
 912
 913         wakeref = intel_display_power_get(dev_priv,
 914                                           intel_encoder->power_domain);
 915
 916         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 917         ret = intel_crt_ddc_get_modes(connector, i2c);
 918         if (ret || !IS_G4X(dev_priv))
 919                 goto out;
 920
 921         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 922         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 923         ret = intel_crt_ddc_get_modes(connector, i2c);
 924
 925 out:
 926         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 927
 928         return ret;
 929 }
 930
 931 void intel_crt_reset(struct drm_encoder *encoder)
 932 {
 933         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 934         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 935
 936         if (INTEL_GEN(dev_priv) >= 5) {
 937                 u32 adpa;
 938
 939                 adpa = intel_de_read(dev_priv, crt->adpa_reg);
 940                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 941                 adpa |= ADPA_HOTPLUG_BITS;
 942                 intel_de_write(dev_priv, crt->adpa_reg, adpa);
 943                 intel_de_posting_read(dev_priv, crt->adpa_reg);
 944
 945                 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
 946                 crt->force_hotplug_required = true;
 947         }
 948
 949 }
 950
 951 /*
 952  * Routines for controlling stuff on the analog port
 953  */
 954
 955 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 956         .fill_modes = drm_helper_probe_single_connector_modes,
 957         .late_register = intel_connector_register,
 958         .early_unregister = intel_connector_unregister,
 959         .destroy = intel_connector_destroy,
 960         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 961         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 962 };
 963
 964 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 965         .detect_ctx = intel_crt_detect,
 966         .mode_valid = intel_crt_mode_valid,
 967         .get_modes = intel_crt_get_modes,
 968 };
 969
 970 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 971         .reset = intel_crt_reset,
 972         .destroy = intel_encoder_destroy,
 973 };
 974
 975 void intel_crt_init(struct drm_i915_private *dev_priv)
 976 {
 977         struct drm_connector *connector;
 978         struct intel_crt *crt;
 979         struct intel_connector *intel_connector;
 980         i915_reg_t adpa_reg;
 981         u32 adpa;
 982
 983         if (HAS_PCH_SPLIT(dev_priv))
 984                 adpa_reg = PCH_ADPA;
 985         else if (IS_VALLEYVIEW(dev_priv))
 986                 adpa_reg = VLV_ADPA;
 987         else
 988                 adpa_reg = ADPA;
 989
 990         adpa = intel_de_read(dev_priv, adpa_reg);
 991         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 992                 /*
 993                  * On some machines (some IVB at least) CRT can be
 994                  * fused off, but there's no known fuse bit to
 995                  * indicate that. On these machine the ADPA register
 996                  * works normally, except the DAC enable bit won't
 997                  * take. So the only way to tell is attempt to enable
 998                  * it and see what happens.
 999                  */
1000                 intel_de_write(dev_priv, adpa_reg,
1001                                adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1002                 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1003                         return;
1004                 intel_de_write(dev_priv, adpa_reg, adpa);
1005         }
1006
1007         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1008         if (!crt)
1009                 return;
1010
1011         intel_connector = intel_connector_alloc();
1012         if (!intel_connector) {
1013                 kfree(crt);
1014                 return;
1015         }
1016
1017         connector = &intel_connector->base;
1018         crt->connector = intel_connector;
1019         drm_connector_init(&dev_priv->drm, &intel_connector->base,
1020                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1021
1022         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1023                          DRM_MODE_ENCODER_DAC, "CRT");
1024
1025         intel_connector_attach_encoder(intel_connector, &crt->base);
1026
1027         crt->base.type = INTEL_OUTPUT_ANALOG;
1028         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
1029         if (IS_I830(dev_priv))
1030                 crt->base.pipe_mask = BIT(PIPE_A);
1031         else
1032                 crt->base.pipe_mask = ~0;
1033
1034         if (IS_GEN(dev_priv, 2))
1035                 connector->interlace_allowed = 0;
1036         else
1037                 connector->interlace_allowed = 1;
1038         connector->doublescan_allowed = 0;
1039
1040         crt->adpa_reg = adpa_reg;
1041
1042         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1043
1044         if (I915_HAS_HOTPLUG(dev_priv) &&
1045             !dmi_check_system(intel_spurious_crt_detect)) {
1046                 crt->base.hpd_pin = HPD_CRT;
1047                 crt->base.hotplug = intel_encoder_hotplug;
1048                 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1049         } else {
1050                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1051         }
1052
1053         if (HAS_DDI(dev_priv)) {
1054                 crt->base.port = PORT_E;
1055                 crt->base.get_config = hsw_crt_get_config;
1056                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1057                 crt->base.compute_config = hsw_crt_compute_config;
1058                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1059                 crt->base.pre_enable = hsw_pre_enable_crt;
1060                 crt->base.enable = hsw_enable_crt;
1061                 crt->base.disable = hsw_disable_crt;
1062                 crt->base.post_disable = hsw_post_disable_crt;
1063         } else {
1064                 if (HAS_PCH_SPLIT(dev_priv)) {
1065                         crt->base.compute_config = pch_crt_compute_config;
1066                         crt->base.disable = pch_disable_crt;
1067                         crt->base.post_disable = pch_post_disable_crt;
1068                 } else {
1069                         crt->base.compute_config = intel_crt_compute_config;
1070                         crt->base.disable = intel_disable_crt;
1071                 }
1072                 crt->base.port = PORT_NONE;
1073                 crt->base.get_config = intel_crt_get_config;
1074                 crt->base.get_hw_state = intel_crt_get_hw_state;
1075                 crt->base.enable = intel_enable_crt;
1076         }
1077         intel_connector->get_hw_state = intel_connector_get_hw_state;
1078
1079         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1080
1081         /*
1082          * TODO: find a proper way to discover whether we need to set the the
1083          * polarity and link reversal bits or not, instead of relying on the
1084          * BIOS.
1085          */
1086         if (HAS_PCH_LPT(dev_priv)) {
1087                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1088                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1089
1090                 dev_priv->fdi_rx_config = intel_de_read(dev_priv,
1091                                                         FDI_RX_CTL(PIPE_A)) & fdi_config;
1092         }
1093
1094         intel_crt_reset(&crt->base.base);
1095 }