drivers/gpu/drm/i915/display/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_edid.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/i915_drm.h>
  36
  37 #include "i915_drv.h"
  38 #include "intel_connector.h"
  39 #include "intel_crt.h"
  40 #include "intel_ddi.h"
  41 #include "intel_display_types.h"
  42 #include "intel_fifo_underrun.h"
  43 #include "intel_gmbus.h"
  44 #include "intel_hotplug.h"
  45
  46 /* Here's the desired hotplug mode */
  47 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  48                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  49                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  50                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  51                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  52                            ADPA_CRT_HOTPLUG_ENABLE)
  53
  54 struct intel_crt {
  55         struct intel_encoder base;
  56         /* DPMS state is stored in the connector, which we need in the
  57          * encoder's enable/disable callbacks */
  58         struct intel_connector *connector;
  59         bool force_hotplug_required;
  60         i915_reg_t adpa_reg;
  61 };
  62
  63 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  64 {
  65         return container_of(encoder, struct intel_crt, base);
  66 }
  67
  68 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
  69 {
  70         return intel_encoder_to_crt(intel_attached_encoder(connector));
  71 }
  72
  73 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  74                             i915_reg_t adpa_reg, enum pipe *pipe)
  75 {
  76         u32 val;
  77
  78         val = intel_de_read(dev_priv, adpa_reg);
  79
  80         /* asserts want to know the pipe even if the port is disabled */
  81         if (HAS_PCH_CPT(dev_priv))
  82                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  83         else
  84                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  85
  86         return val & ADPA_DAC_ENABLE;
  87 }
  88
  89 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  90                                    enum pipe *pipe)
  91 {
  92         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  93         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  94         intel_wakeref_t wakeref;
  95         bool ret;
  96
  97         wakeref = intel_display_power_get_if_enabled(dev_priv,
  98                                                      encoder->power_domain);
  99         if (!wakeref)
 100                 return false;
 101
 102         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
 103
 104         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 105
 106         return ret;
 107 }
 108
 109 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 110 {
 111         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 112         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 113         u32 tmp, flags = 0;
 114
 115         tmp = intel_de_read(dev_priv, crt->adpa_reg);
 116
 117         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 118                 flags |= DRM_MODE_FLAG_PHSYNC;
 119         else
 120                 flags |= DRM_MODE_FLAG_NHSYNC;
 121
 122         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 123                 flags |= DRM_MODE_FLAG_PVSYNC;
 124         else
 125                 flags |= DRM_MODE_FLAG_NVSYNC;
 126
 127         return flags;
 128 }
 129
 130 static void intel_crt_get_config(struct intel_encoder *encoder,
 131                                  struct intel_crtc_state *pipe_config)
 132 {
 133         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 134
 135         pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 136
 137         pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 138 }
 139
 140 static void hsw_crt_get_config(struct intel_encoder *encoder,
 141                                struct intel_crtc_state *pipe_config)
 142 {
 143         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 144
 145         intel_ddi_get_config(encoder, pipe_config);
 146
 147         pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 148                                               DRM_MODE_FLAG_NHSYNC |
 149                                               DRM_MODE_FLAG_PVSYNC |
 150                                               DRM_MODE_FLAG_NVSYNC);
 151         pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 152
 153         pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 154 }
 155
 156 /* Note: The caller is required to filter out dpms modes not supported by the
 157  * platform. */
 158 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 159                                const struct intel_crtc_state *crtc_state,
 160                                int mode)
 161 {
 162         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 163         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 164         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 165         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 166         u32 adpa;
 167
 168         if (INTEL_GEN(dev_priv) >= 5)
 169                 adpa = ADPA_HOTPLUG_BITS;
 170         else
 171                 adpa = 0;
 172
 173         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 174                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 175         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 176                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 177
 178         /* For CPT allow 3 pipe config, for others just use A or B */
 179         if (HAS_PCH_LPT(dev_priv))
 180                 ; /* Those bits don't exist here */
 181         else if (HAS_PCH_CPT(dev_priv))
 182                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 183         else
 184                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 185
 186         if (!HAS_PCH_SPLIT(dev_priv))
 187                 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
 188
 189         switch (mode) {
 190         case DRM_MODE_DPMS_ON:
 191                 adpa |= ADPA_DAC_ENABLE;
 192                 break;
 193         case DRM_MODE_DPMS_STANDBY:
 194                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 195                 break;
 196         case DRM_MODE_DPMS_SUSPEND:
 197                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 198                 break;
 199         case DRM_MODE_DPMS_OFF:
 200                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 201                 break;
 202         }
 203
 204         intel_de_write(dev_priv, crt->adpa_reg, adpa);
 205 }
 206
 207 static void intel_disable_crt(struct intel_encoder *encoder,
 208                               const struct intel_crtc_state *old_crtc_state,
 209                               const struct drm_connector_state *old_conn_state)
 210 {
 211         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 212 }
 213
 214 static void pch_disable_crt(struct intel_encoder *encoder,
 215                             const struct intel_crtc_state *old_crtc_state,
 216                             const struct drm_connector_state *old_conn_state)
 217 {
 218 }
 219
 220 static void pch_post_disable_crt(struct intel_encoder *encoder,
 221                                  const struct intel_crtc_state *old_crtc_state,
 222                                  const struct drm_connector_state *old_conn_state)
 223 {
 224         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 225 }
 226
 227 static void hsw_disable_crt(struct intel_encoder *encoder,
 228                             const struct intel_crtc_state *old_crtc_state,
 229                             const struct drm_connector_state *old_conn_state)
 230 {
 231         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 232
 233         drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
 234
 235         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 236 }
 237
 238 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 239                                  const struct intel_crtc_state *old_crtc_state,
 240                                  const struct drm_connector_state *old_conn_state)
 241 {
 242         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 243
 244         intel_crtc_vblank_off(old_crtc_state);
 245
 246         intel_disable_pipe(old_crtc_state);
 247
 248         intel_ddi_disable_transcoder_func(old_crtc_state);
 249
 250         ilk_pfit_disable(old_crtc_state);
 251
 252         intel_ddi_disable_pipe_clock(old_crtc_state);
 253
 254         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 255
 256         lpt_disable_pch_transcoder(dev_priv);
 257         lpt_disable_iclkip(dev_priv);
 258
 259         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 260
 261         drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
 262
 263         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 264 }
 265
 266 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 267                                    const struct intel_crtc_state *crtc_state,
 268                                    const struct drm_connector_state *conn_state)
 269 {
 270         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 271
 272         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 273
 274         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 275 }
 276
 277 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 278                                const struct intel_crtc_state *crtc_state,
 279                                const struct drm_connector_state *conn_state)
 280 {
 281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 282         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 283         enum pipe pipe = crtc->pipe;
 284
 285         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 286
 287         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 288
 289         hsw_fdi_link_train(encoder, crtc_state);
 290
 291         intel_ddi_enable_pipe_clock(crtc_state);
 292 }
 293
 294 static void hsw_enable_crt(struct intel_encoder *encoder,
 295                            const struct intel_crtc_state *crtc_state,
 296                            const struct drm_connector_state *conn_state)
 297 {
 298         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 299         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 300         enum pipe pipe = crtc->pipe;
 301
 302         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 303
 304         intel_enable_pipe(crtc_state);
 305
 306         lpt_pch_enable(crtc_state);
 307
 308         intel_crtc_vblank_on(crtc_state);
 309
 310         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 311
 312         intel_wait_for_vblank(dev_priv, pipe);
 313         intel_wait_for_vblank(dev_priv, pipe);
 314         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 315         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 316 }
 317
 318 static void intel_enable_crt(struct intel_encoder *encoder,
 319                              const struct intel_crtc_state *crtc_state,
 320                              const struct drm_connector_state *conn_state)
 321 {
 322         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 323 }
 324
 325 static enum drm_mode_status
 326 intel_crt_mode_valid(struct drm_connector *connector,
 327                      struct drm_display_mode *mode)
 328 {
 329         struct drm_device *dev = connector->dev;
 330         struct drm_i915_private *dev_priv = to_i915(dev);
 331         int max_dotclk = dev_priv->max_dotclk_freq;
 332         int max_clock;
 333
 334         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 335                 return MODE_NO_DBLESCAN;
 336
 337         if (mode->clock < 25000)
 338                 return MODE_CLOCK_LOW;
 339
 340         if (HAS_PCH_LPT(dev_priv))
 341                 max_clock = 180000;
 342         else if (IS_VALLEYVIEW(dev_priv))
 343                 /*
 344                  * 270 MHz due to current DPLL limits,
 345                  * DAC limit supposedly 355 MHz.
 346                  */
 347                 max_clock = 270000;
 348         else if (IS_GEN_RANGE(dev_priv, 3, 4))
 349                 max_clock = 400000;
 350         else
 351                 max_clock = 350000;
 352         if (mode->clock > max_clock)
 353                 return MODE_CLOCK_HIGH;
 354
 355         if (mode->clock > max_dotclk)
 356                 return MODE_CLOCK_HIGH;
 357
 358         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 359         if (HAS_PCH_LPT(dev_priv) &&
 360             ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
 361                 return MODE_CLOCK_HIGH;
 362
 363         /* HSW/BDW FDI limited to 4k */
 364         if (mode->hdisplay > 4096)
 365                 return MODE_H_ILLEGAL;
 366
 367         return MODE_OK;
 368 }
 369
 370 static int intel_crt_compute_config(struct intel_encoder *encoder,
 371                                     struct intel_crtc_state *pipe_config,
 372                                     struct drm_connector_state *conn_state)
 373 {
 374         struct drm_display_mode *adjusted_mode =
 375                 &pipe_config->hw.adjusted_mode;
 376
 377         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 378                 return -EINVAL;
 379
 380         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 381
 382         return 0;
 383 }
 384
 385 static int pch_crt_compute_config(struct intel_encoder *encoder,
 386                                   struct intel_crtc_state *pipe_config,
 387                                   struct drm_connector_state *conn_state)
 388 {
 389         struct drm_display_mode *adjusted_mode =
 390                 &pipe_config->hw.adjusted_mode;
 391
 392         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 393                 return -EINVAL;
 394
 395         pipe_config->has_pch_encoder = true;
 396         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 397
 398         return 0;
 399 }
 400
 401 static int hsw_crt_compute_config(struct intel_encoder *encoder,
 402                                   struct intel_crtc_state *pipe_config,
 403                                   struct drm_connector_state *conn_state)
 404 {
 405         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 406         struct drm_display_mode *adjusted_mode =
 407                 &pipe_config->hw.adjusted_mode;
 408
 409         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 410                 return -EINVAL;
 411
 412         /* HSW/BDW FDI limited to 4k */
 413         if (adjusted_mode->crtc_hdisplay > 4096 ||
 414             adjusted_mode->crtc_hblank_start > 4096)
 415                 return -EINVAL;
 416
 417         pipe_config->has_pch_encoder = true;
 418         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 419
 420         /* LPT FDI RX only supports 8bpc. */
 421         if (HAS_PCH_LPT(dev_priv)) {
 422                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 423                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 424                         return -EINVAL;
 425                 }
 426
 427                 pipe_config->pipe_bpp = 24;
 428         }
 429
 430         /* FDI must always be 2.7 GHz */
 431         pipe_config->port_clock = 135000 * 2;
 432
 433         return 0;
 434 }
 435
 436 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
 437 {
 438         struct drm_device *dev = connector->dev;
 439         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 440         struct drm_i915_private *dev_priv = to_i915(dev);
 441         u32 adpa;
 442         bool ret;
 443
 444         /* The first time through, trigger an explicit detection cycle */
 445         if (crt->force_hotplug_required) {
 446                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 447                 u32 save_adpa;
 448
 449                 crt->force_hotplug_required = false;
 450
 451                 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
 452                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 453
 454                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 455                 if (turn_off_dac)
 456                         adpa &= ~ADPA_DAC_ENABLE;
 457
 458                 intel_de_write(dev_priv, crt->adpa_reg, adpa);
 459
 460                 if (intel_de_wait_for_clear(dev_priv,
 461                                             crt->adpa_reg,
 462                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
 463                                             1000))
 464                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 465
 466                 if (turn_off_dac) {
 467                         intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
 468                         intel_de_posting_read(dev_priv, crt->adpa_reg);
 469                 }
 470         }
 471
 472         /* Check the status to see if both blue and green are on now */
 473         adpa = intel_de_read(dev_priv, crt->adpa_reg);
 474         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 475                 ret = true;
 476         else
 477                 ret = false;
 478         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 479
 480         return ret;
 481 }
 482
 483 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 484 {
 485         struct drm_device *dev = connector->dev;
 486         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 487         struct drm_i915_private *dev_priv = to_i915(dev);
 488         bool reenable_hpd;
 489         u32 adpa;
 490         bool ret;
 491         u32 save_adpa;
 492
 493         /*
 494          * Doing a force trigger causes a hpd interrupt to get sent, which can
 495          * get us stuck in a loop if we're polling:
 496          *  - We enable power wells and reset the ADPA
 497          *  - output_poll_exec does force probe on VGA, triggering a hpd
 498          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 499          *  - output_poll_exec shuts off the ADPA, unlocks
 500          *    dev->mode_config.mutex
 501          *  - HPD handler runs, resets ADPA and brings us back to the start
 502          *
 503          * Just disable HPD interrupts here to prevent this
 504          */
 505         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 506
 507         save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
 508         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 509
 510         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 511
 512         intel_de_write(dev_priv, crt->adpa_reg, adpa);
 513
 514         if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
 515                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
 516                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 517                 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
 518         }
 519
 520         /* Check the status to see if both blue and green are on now */
 521         adpa = intel_de_read(dev_priv, crt->adpa_reg);
 522         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 523                 ret = true;
 524         else
 525                 ret = false;
 526
 527         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 528
 529         if (reenable_hpd)
 530                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 531
 532         return ret;
 533 }
 534
 535 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 536 {
 537         struct drm_device *dev = connector->dev;
 538         struct drm_i915_private *dev_priv = to_i915(dev);
 539         u32 stat;
 540         bool ret = false;
 541         int i, tries = 0;
 542
 543         if (HAS_PCH_SPLIT(dev_priv))
 544                 return ilk_crt_detect_hotplug(connector);
 545
 546         if (IS_VALLEYVIEW(dev_priv))
 547                 return valleyview_crt_detect_hotplug(connector);
 548
 549         /*
 550          * On 4 series desktop, CRT detect sequence need to be done twice
 551          * to get a reliable result.
 552          */
 553
 554         if (IS_G45(dev_priv))
 555                 tries = 2;
 556         else
 557                 tries = 1;
 558
 559         for (i = 0; i < tries ; i++) {
 560                 /* turn on the FORCE_DETECT */
 561                 i915_hotplug_interrupt_update(dev_priv,
 562                                               CRT_HOTPLUG_FORCE_DETECT,
 563                                               CRT_HOTPLUG_FORCE_DETECT);
 564                 /* wait for FORCE_DETECT to go off */
 565                 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
 566                                             CRT_HOTPLUG_FORCE_DETECT, 1000))
 567                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 568         }
 569
 570         stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
 571         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 572                 ret = true;
 573
 574         /* clear the interrupt we just generated, if any */
 575         intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 576
 577         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 578
 579         return ret;
 580 }
 581
 582 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 583                                 struct i2c_adapter *i2c)
 584 {
 585         struct edid *edid;
 586
 587         edid = drm_get_edid(connector, i2c);
 588
 589         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 590                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 591                 intel_gmbus_force_bit(i2c, true);
 592                 edid = drm_get_edid(connector, i2c);
 593                 intel_gmbus_force_bit(i2c, false);
 594         }
 595
 596         return edid;
 597 }
 598
 599 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 600 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 601                                 struct i2c_adapter *adapter)
 602 {
 603         struct edid *edid;
 604         int ret;
 605
 606         edid = intel_crt_get_edid(connector, adapter);
 607         if (!edid)
 608                 return 0;
 609
 610         ret = intel_connector_update_modes(connector, edid);
 611         kfree(edid);
 612
 613         return ret;
 614 }
 615
 616 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 617 {
 618         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 619         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 620         struct edid *edid;
 621         struct i2c_adapter *i2c;
 622         bool ret = false;
 623
 624         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 625
 626         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 627         edid = intel_crt_get_edid(connector, i2c);
 628
 629         if (edid) {
 630                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 631
 632                 /*
 633                  * This may be a DVI-I connector with a shared DDC
 634                  * link between analog and digital outputs, so we
 635                  * have to check the EDID input spec of the attached device.
 636                  */
 637                 if (!is_digital) {
 638                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 639                         ret = true;
 640                 } else {
 641                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 642                 }
 643         } else {
 644                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 645         }
 646
 647         kfree(edid);
 648
 649         return ret;
 650 }
 651
 652 static enum drm_connector_status
 653 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
 654 {
 655         struct drm_device *dev = crt->base.base.dev;
 656         struct drm_i915_private *dev_priv = to_i915(dev);
 657         struct intel_uncore *uncore = &dev_priv->uncore;
 658         u32 save_bclrpat;
 659         u32 save_vtotal;
 660         u32 vtotal, vactive;
 661         u32 vsample;
 662         u32 vblank, vblank_start, vblank_end;
 663         u32 dsl;
 664         i915_reg_t bclrpat_reg, vtotal_reg,
 665                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 666         u8 st00;
 667         enum drm_connector_status status;
 668
 669         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 670
 671         bclrpat_reg = BCLRPAT(pipe);
 672         vtotal_reg = VTOTAL(pipe);
 673         vblank_reg = VBLANK(pipe);
 674         vsync_reg = VSYNC(pipe);
 675         pipeconf_reg = PIPECONF(pipe);
 676         pipe_dsl_reg = PIPEDSL(pipe);
 677
 678         save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
 679         save_vtotal = intel_uncore_read(uncore, vtotal_reg);
 680         vblank = intel_uncore_read(uncore, vblank_reg);
 681
 682         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 683         vactive = (save_vtotal & 0x7ff) + 1;
 684
 685         vblank_start = (vblank & 0xfff) + 1;
 686         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 687
 688         /* Set the border color to purple. */
 689         intel_uncore_write(uncore, bclrpat_reg, 0x500050);
 690
 691         if (!IS_GEN(dev_priv, 2)) {
 692                 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
 693                 intel_uncore_write(uncore,
 694                                    pipeconf_reg,
 695                                    pipeconf | PIPECONF_FORCE_BORDER);
 696                 intel_uncore_posting_read(uncore, pipeconf_reg);
 697                 /* Wait for next Vblank to substitue
 698                  * border color for Color info */
 699                 intel_wait_for_vblank(dev_priv, pipe);
 700                 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
 701                 status = ((st00 & (1 << 4)) != 0) ?
 702                         connector_status_connected :
 703                         connector_status_disconnected;
 704
 705                 intel_uncore_write(uncore, pipeconf_reg, pipeconf);
 706         } else {
 707                 bool restore_vblank = false;
 708                 int count, detect;
 709
 710                 /*
 711                 * If there isn't any border, add some.
 712                 * Yes, this will flicker
 713                 */
 714                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 715                         u32 vsync = intel_de_read(dev_priv, vsync_reg);
 716                         u32 vsync_start = (vsync & 0xffff) + 1;
 717
 718                         vblank_start = vsync_start;
 719                         intel_uncore_write(uncore,
 720                                            vblank_reg,
 721                                            (vblank_start - 1) |
 722                                            ((vblank_end - 1) << 16));
 723                         restore_vblank = true;
 724                 }
 725                 /* sample in the vertical border, selecting the larger one */
 726                 if (vblank_start - vactive >= vtotal - vblank_end)
 727                         vsample = (vblank_start + vactive) >> 1;
 728                 else
 729                         vsample = (vtotal + vblank_end) >> 1;
 730
 731                 /*
 732                  * Wait for the border to be displayed
 733                  */
 734                 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
 735                         ;
 736                 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
 737                        vsample)
 738                         ;
 739                 /*
 740                  * Watch ST00 for an entire scanline
 741                  */
 742                 detect = 0;
 743                 count = 0;
 744                 do {
 745                         count++;
 746                         /* Read the ST00 VGA status register */
 747                         st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
 748                         if (st00 & (1 << 4))
 749                                 detect++;
 750                 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
 751
 752                 /* restore vblank if necessary */
 753                 if (restore_vblank)
 754                         intel_uncore_write(uncore, vblank_reg, vblank);
 755                 /*
 756                  * If more than 3/4 of the scanline detected a monitor,
 757                  * then it is assumed to be present. This works even on i830,
 758                  * where there isn't any way to force the border color across
 759                  * the screen
 760                  */
 761                 status = detect * 4 > count * 3 ?
 762                          connector_status_connected :
 763                          connector_status_disconnected;
 764         }
 765
 766         /* Restore previous settings */
 767         intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
 768
 769         return status;
 770 }
 771
 772 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 773 {
 774         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 775         return 1;
 776 }
 777
 778 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 779         {
 780                 .callback = intel_spurious_crt_detect_dmi_callback,
 781                 .ident = "ACER ZGB",
 782                 .matches = {
 783                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 784                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 785                 },
 786         },
 787         {
 788                 .callback = intel_spurious_crt_detect_dmi_callback,
 789                 .ident = "Intel DZ77BH-55K",
 790                 .matches = {
 791                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 792                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 793                 },
 794         },
 795         { }
 796 };
 797
 798 static int
 799 intel_crt_detect(struct drm_connector *connector,
 800                  struct drm_modeset_acquire_ctx *ctx,
 801                  bool force)
 802 {
 803         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 804         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 805         struct intel_encoder *intel_encoder = &crt->base;
 806         intel_wakeref_t wakeref;
 807         int status, ret;
 808         struct intel_load_detect_pipe tmp;
 809
 810         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 811                       connector->base.id, connector->name,
 812                       force);
 813
 814         if (i915_modparams.load_detect_test) {
 815                 wakeref = intel_display_power_get(dev_priv,
 816                                                   intel_encoder->power_domain);
 817                 goto load_detect;
 818         }
 819
 820         /* Skip machines without VGA that falsely report hotplug events */
 821         if (dmi_check_system(intel_spurious_crt_detect))
 822                 return connector_status_disconnected;
 823
 824         wakeref = intel_display_power_get(dev_priv,
 825                                           intel_encoder->power_domain);
 826
 827         if (I915_HAS_HOTPLUG(dev_priv)) {
 828                 /* We can not rely on the HPD pin always being correctly wired
 829                  * up, for example many KVM do not pass it through, and so
 830                  * only trust an assertion that the monitor is connected.
 831                  */
 832                 if (intel_crt_detect_hotplug(connector)) {
 833                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 834                         status = connector_status_connected;
 835                         goto out;
 836                 } else
 837                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 838         }
 839
 840         if (intel_crt_detect_ddc(connector)) {
 841                 status = connector_status_connected;
 842                 goto out;
 843         }
 844
 845         /* Load detection is broken on HPD capable machines. Whoever wants a
 846          * broken monitor (without edid) to work behind a broken kvm (that fails
 847          * to have the right resistors for HP detection) needs to fix this up.
 848          * For now just bail out. */
 849         if (I915_HAS_HOTPLUG(dev_priv)) {
 850                 status = connector_status_disconnected;
 851                 goto out;
 852         }
 853
 854 load_detect:
 855         if (!force) {
 856                 status = connector->status;
 857                 goto out;
 858         }
 859
 860         /* for pre-945g platforms use load detect */
 861         ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
 862         if (ret > 0) {
 863                 if (intel_crt_detect_ddc(connector))
 864                         status = connector_status_connected;
 865                 else if (INTEL_GEN(dev_priv) < 4)
 866                         status = intel_crt_load_detect(crt,
 867                                 to_intel_crtc(connector->state->crtc)->pipe);
 868                 else if (i915_modparams.load_detect_test)
 869                         status = connector_status_disconnected;
 870                 else
 871                         status = connector_status_unknown;
 872                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 873         } else if (ret == 0) {
 874                 status = connector_status_unknown;
 875         } else {
 876                 status = ret;
 877         }
 878
 879 out:
 880         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 881
 882         /*
 883          * Make sure the refs for power wells enabled during detect are
 884          * dropped to avoid a new detect cycle triggered by HPD polling.
 885          */
 886         intel_display_power_flush_work(dev_priv);
 887
 888         return status;
 889 }
 890
 891 static int intel_crt_get_modes(struct drm_connector *connector)
 892 {
 893         struct drm_device *dev = connector->dev;
 894         struct drm_i915_private *dev_priv = to_i915(dev);
 895         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 896         struct intel_encoder *intel_encoder = &crt->base;
 897         intel_wakeref_t wakeref;
 898         struct i2c_adapter *i2c;
 899         int ret;
 900
 901         wakeref = intel_display_power_get(dev_priv,
 902                                           intel_encoder->power_domain);
 903
 904         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 905         ret = intel_crt_ddc_get_modes(connector, i2c);
 906         if (ret || !IS_G4X(dev_priv))
 907                 goto out;
 908
 909         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 910         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 911         ret = intel_crt_ddc_get_modes(connector, i2c);
 912
 913 out:
 914         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 915
 916         return ret;
 917 }
 918
 919 void intel_crt_reset(struct drm_encoder *encoder)
 920 {
 921         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 922         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 923
 924         if (INTEL_GEN(dev_priv) >= 5) {
 925                 u32 adpa;
 926
 927                 adpa = intel_de_read(dev_priv, crt->adpa_reg);
 928                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 929                 adpa |= ADPA_HOTPLUG_BITS;
 930                 intel_de_write(dev_priv, crt->adpa_reg, adpa);
 931                 intel_de_posting_read(dev_priv, crt->adpa_reg);
 932
 933                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 934                 crt->force_hotplug_required = true;
 935         }
 936
 937 }
 938
 939 /*
 940  * Routines for controlling stuff on the analog port
 941  */
 942
 943 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 944         .fill_modes = drm_helper_probe_single_connector_modes,
 945         .late_register = intel_connector_register,
 946         .early_unregister = intel_connector_unregister,
 947         .destroy = intel_connector_destroy,
 948         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 949         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 950 };
 951
 952 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 953         .detect_ctx = intel_crt_detect,
 954         .mode_valid = intel_crt_mode_valid,
 955         .get_modes = intel_crt_get_modes,
 956 };
 957
 958 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 959         .reset = intel_crt_reset,
 960         .destroy = intel_encoder_destroy,
 961 };
 962
 963 void intel_crt_init(struct drm_i915_private *dev_priv)
 964 {
 965         struct drm_connector *connector;
 966         struct intel_crt *crt;
 967         struct intel_connector *intel_connector;
 968         i915_reg_t adpa_reg;
 969         u32 adpa;
 970
 971         if (HAS_PCH_SPLIT(dev_priv))
 972                 adpa_reg = PCH_ADPA;
 973         else if (IS_VALLEYVIEW(dev_priv))
 974                 adpa_reg = VLV_ADPA;
 975         else
 976                 adpa_reg = ADPA;
 977
 978         adpa = intel_de_read(dev_priv, adpa_reg);
 979         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 980                 /*
 981                  * On some machines (some IVB at least) CRT can be
 982                  * fused off, but there's no known fuse bit to
 983                  * indicate that. On these machine the ADPA register
 984                  * works normally, except the DAC enable bit won't
 985                  * take. So the only way to tell is attempt to enable
 986                  * it and see what happens.
 987                  */
 988                 intel_de_write(dev_priv, adpa_reg,
 989                                adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 990                 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
 991                         return;
 992                 intel_de_write(dev_priv, adpa_reg, adpa);
 993         }
 994
 995         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 996         if (!crt)
 997                 return;
 998
 999         intel_connector = intel_connector_alloc();
1000         if (!intel_connector) {
1001                 kfree(crt);
1002                 return;
1003         }
1004
1005         connector = &intel_connector->base;
1006         crt->connector = intel_connector;
1007         drm_connector_init(&dev_priv->drm, &intel_connector->base,
1008                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1009
1010         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1011                          DRM_MODE_ENCODER_DAC, "CRT");
1012
1013         intel_connector_attach_encoder(intel_connector, &crt->base);
1014
1015         crt->base.type = INTEL_OUTPUT_ANALOG;
1016         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
1017         if (IS_I830(dev_priv))
1018                 crt->base.pipe_mask = BIT(PIPE_A);
1019         else
1020                 crt->base.pipe_mask = ~0;
1021
1022         if (IS_GEN(dev_priv, 2))
1023                 connector->interlace_allowed = 0;
1024         else
1025                 connector->interlace_allowed = 1;
1026         connector->doublescan_allowed = 0;
1027
1028         crt->adpa_reg = adpa_reg;
1029
1030         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1031
1032         if (I915_HAS_HOTPLUG(dev_priv) &&
1033             !dmi_check_system(intel_spurious_crt_detect)) {
1034                 crt->base.hpd_pin = HPD_CRT;
1035                 crt->base.hotplug = intel_encoder_hotplug;
1036         }
1037
1038         if (HAS_DDI(dev_priv)) {
1039                 crt->base.port = PORT_E;
1040                 crt->base.get_config = hsw_crt_get_config;
1041                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1042                 crt->base.compute_config = hsw_crt_compute_config;
1043                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1044                 crt->base.pre_enable = hsw_pre_enable_crt;
1045                 crt->base.enable = hsw_enable_crt;
1046                 crt->base.disable = hsw_disable_crt;
1047                 crt->base.post_disable = hsw_post_disable_crt;
1048         } else {
1049                 if (HAS_PCH_SPLIT(dev_priv)) {
1050                         crt->base.compute_config = pch_crt_compute_config;
1051                         crt->base.disable = pch_disable_crt;
1052                         crt->base.post_disable = pch_post_disable_crt;
1053                 } else {
1054                         crt->base.compute_config = intel_crt_compute_config;
1055                         crt->base.disable = intel_disable_crt;
1056                 }
1057                 crt->base.port = PORT_NONE;
1058                 crt->base.get_config = intel_crt_get_config;
1059                 crt->base.get_hw_state = intel_crt_get_hw_state;
1060                 crt->base.enable = intel_enable_crt;
1061         }
1062         intel_connector->get_hw_state = intel_connector_get_hw_state;
1063
1064         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1065
1066         if (!I915_HAS_HOTPLUG(dev_priv))
1067                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1068
1069         /*
1070          * Configure the automatic hotplug detection stuff
1071          */
1072         crt->force_hotplug_required = false;
1073
1074         /*
1075          * TODO: find a proper way to discover whether we need to set the the
1076          * polarity and link reversal bits or not, instead of relying on the
1077          * BIOS.
1078          */
1079         if (HAS_PCH_LPT(dev_priv)) {
1080                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1081                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1082
1083                 dev_priv->fdi_rx_config = intel_de_read(dev_priv,
1084                                                         FDI_RX_CTL(PIPE_A)) & fdi_config;
1085         }
1086
1087         intel_crt_reset(&crt->base.base);
1088 }