drivers/gpu/drm/i915/display/intel_combo_phy.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  */
   5
   6 #include "intel_combo_phy.h"
   7 #include "intel_display_types.h"
   8
   9 #define for_each_combo_phy(__dev_priv, __phy) \
  10         for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
  11                 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
  12
  13 #define for_each_combo_phy_reverse(__dev_priv, __phy) \
  14         for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
  15                 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
  16
  17 enum {
  18         PROCMON_0_85V_DOT_0,
  19         PROCMON_0_95V_DOT_0,
  20         PROCMON_0_95V_DOT_1,
  21         PROCMON_1_05V_DOT_0,
  22         PROCMON_1_05V_DOT_1,
  23 };
  24
  25 static const struct cnl_procmon {
  26         u32 dw1, dw9, dw10;
  27 } cnl_procmon_values[] = {
  28         [PROCMON_0_85V_DOT_0] =
  29                 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
  30         [PROCMON_0_95V_DOT_0] =
  31                 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
  32         [PROCMON_0_95V_DOT_1] =
  33                 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
  34         [PROCMON_1_05V_DOT_0] =
  35                 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
  36         [PROCMON_1_05V_DOT_1] =
  37                 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
  38 };
  39
  40 /*
  41  * CNL has just one set of registers, while gen11 has a set for each combo PHY.
  42  * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
  43  * call the ICL macros even though the function has CNL on its name.
  44  */
  45 static const struct cnl_procmon *
  46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
  47 {
  48         const struct cnl_procmon *procmon;
  49         u32 val;
  50
  51         val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
  52         switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
  53         default:
  54                 MISSING_CASE(val);
  55                 fallthrough;
  56         case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
  57                 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
  58                 break;
  59         case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
  60                 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
  61                 break;
  62         case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
  63                 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
  64                 break;
  65         case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
  66                 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
  67                 break;
  68         case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
  69                 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
  70                 break;
  71         }
  72
  73         return procmon;
  74 }
  75
  76 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
  77                                        enum phy phy)
  78 {
  79         const struct cnl_procmon *procmon;
  80         u32 val;
  81
  82         procmon = cnl_get_procmon_ref_values(dev_priv, phy);
  83
  84         val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
  85         val &= ~((0xff << 16) | 0xff);
  86         val |= procmon->dw1;
  87         intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);
  88
  89         intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
  90         intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
  91 }
  92
  93 static bool check_phy_reg(struct drm_i915_private *dev_priv,
  94                           enum phy phy, i915_reg_t reg, u32 mask,
  95                           u32 expected_val)
  96 {
  97         u32 val = intel_de_read(dev_priv, reg);
  98
  99         if ((val & mask) != expected_val) {
 100                 drm_dbg(&dev_priv->drm,
 101                         "Combo PHY %c reg %08x state mismatch: "
 102                         "current %08x mask %08x expected %08x\n",
 103                         phy_name(phy),
 104                         reg.reg, val, mask, expected_val);
 105                 return false;
 106         }
 107
 108         return true;
 109 }
 110
 111 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
 112                                           enum phy phy)
 113 {
 114         const struct cnl_procmon *procmon;
 115         bool ret;
 116
 117         procmon = cnl_get_procmon_ref_values(dev_priv, phy);
 118
 119         ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
 120                             (0xff << 16) | 0xff, procmon->dw1);
 121         ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
 122                              -1U, procmon->dw9);
 123         ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
 124                              -1U, procmon->dw10);
 125
 126         return ret;
 127 }
 128
 129 static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
 130 {
 131         return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
 132                 (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
 133 }
 134
 135 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
 136 {
 137         enum phy phy = PHY_A;
 138         bool ret;
 139
 140         if (!cnl_combo_phy_enabled(dev_priv))
 141                 return false;
 142
 143         ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 144
 145         ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
 146                              CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 147
 148         return ret;
 149 }
 150
 151 static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
 152 {
 153         u32 val;
 154
 155         val = intel_de_read(dev_priv, CHICKEN_MISC_2);
 156         val &= ~CNL_COMP_PWR_DOWN;
 157         intel_de_write(dev_priv, CHICKEN_MISC_2, val);
 158
 159         /* Dummy PORT_A to get the correct CNL register from the ICL macro */
 160         cnl_set_procmon_ref_values(dev_priv, PHY_A);
 161
 162         val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
 163         val |= COMP_INIT;
 164         intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
 165
 166         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
 167         val |= CL_POWER_DOWN_ENABLE;
 168         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
 169 }
 170
 171 static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 172 {
 173         u32 val;
 174
 175         if (!cnl_combo_phy_verify_state(dev_priv))
 176                 drm_warn(&dev_priv->drm,
 177                          "Combo PHY HW state changed unexpectedly.\n");
 178
 179         val = intel_de_read(dev_priv, CHICKEN_MISC_2);
 180         val |= CNL_COMP_PWR_DOWN;
 181         intel_de_write(dev_priv, CHICKEN_MISC_2, val);
 182 }
 183
 184 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 185 {
 186         /*
 187          * Some platforms only expect PHY_MISC to be programmed for PHY-A and
 188          * PHY-B and may not even have instances of the register for the
 189          * other combo PHY's.
 190          */
 191         if (IS_JSL_EHL(i915) ||
 192             IS_ROCKETLAKE(i915) ||
 193             IS_DG1(i915))
 194                 return phy < PHY_C;
 195
 196         return true;
 197 }
 198
 199 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
 200                                   enum phy phy)
 201 {
 202         /* The PHY C added by EHL has no PHY_MISC register */
 203         if (!has_phy_misc(dev_priv, phy))
 204                 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
 205         else
 206                 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
 207                          ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
 208                         (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
 209 }
 210
 211 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
 212 {
 213         bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
 214         bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
 215         bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
 216
 217         /*
 218          * VBT's 'dvo port' field for child devices references the DDI, not
 219          * the PHY.  So if combo PHY A is wired up to drive an external
 220          * display, we should see a child device present on PORT_D and
 221          * nothing on PORT_A and no DSI.
 222          */
 223         if (ddi_d_present && !ddi_a_present && !dsi_present)
 224                 return true;
 225
 226         /*
 227          * If we encounter a VBT that claims to have an external display on
 228          * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
 229          * in the log and let the internal display win.
 230          */
 231         if (ddi_d_present)
 232                 drm_err(&i915->drm,
 233                         "VBT claims to have both internal and external displays on PHY A.  Configuring for internal.\n");
 234
 235         return false;
 236 }
 237
 238 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 239 {
 240         /*
 241          * Certain PHYs are connected to compensation resistors and act
 242          * as masters to other PHYs.
 243          *
 244          * ICL,TGL:
 245          *   A(master) -> B(slave), C(slave)
 246          * RKL,DG1:
 247          *   A(master) -> B(slave)
 248          *   C(master) -> D(slave)
 249          * ADL-S:
 250          *   A(master) -> B(slave), C(slave)
 251          *   D(master) -> E(slave)
 252          *
 253          * We must set the IREFGEN bit for any PHY acting as a master
 254          * to another PHY.
 255          */
 256         if (phy == PHY_A)
 257                 return true;
 258         else if (IS_ALDERLAKE_S(dev_priv))
 259                 return phy == PHY_D;
 260         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 261                 return phy == PHY_C;
 262
 263         return false;
 264 }
 265
 266 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 267                                        enum phy phy)
 268 {
 269         bool ret = true;
 270         u32 expected_val = 0;
 271
 272         if (!icl_combo_phy_enabled(dev_priv, phy))
 273                 return false;
 274
 275         if (INTEL_GEN(dev_priv) >= 12) {
 276                 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
 277                                      ICL_PORT_TX_DW8_ODCC_CLK_SEL |
 278                                      ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
 279                                      ICL_PORT_TX_DW8_ODCC_CLK_SEL |
 280                                      ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
 281
 282                 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
 283                                      DCC_MODE_SELECT_MASK,
 284                                      DCC_MODE_SELECT_CONTINUOSLY);
 285         }
 286
 287         ret &= cnl_verify_procmon_ref_values(dev_priv, phy);
 288
 289         if (phy_is_master(dev_priv, phy)) {
 290                 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 291                                      IREFGEN, IREFGEN);
 292
 293                 if (IS_JSL_EHL(dev_priv)) {
 294                         if (ehl_vbt_ddi_d_present(dev_priv))
 295                                 expected_val = ICL_PHY_MISC_MUX_DDID;
 296
 297                         ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
 298                                              ICL_PHY_MISC_MUX_DDID,
 299                                              expected_val);
 300                 }
 301         }
 302
 303         ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
 304                              CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 305
 306         return ret;
 307 }
 308
 309 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
 310                                     enum phy phy, bool is_dsi,
 311                                     int lane_count, bool lane_reversal)
 312 {
 313         u8 lane_mask;
 314         u32 val;
 315
 316         if (is_dsi) {
 317                 drm_WARN_ON(&dev_priv->drm, lane_reversal);
 318
 319                 switch (lane_count) {
 320                 case 1:
 321                         lane_mask = PWR_DOWN_LN_3_1_0;
 322                         break;
 323                 case 2:
 324                         lane_mask = PWR_DOWN_LN_3_1;
 325                         break;
 326                 case 3:
 327                         lane_mask = PWR_DOWN_LN_3;
 328                         break;
 329                 default:
 330                         MISSING_CASE(lane_count);
 331                         fallthrough;
 332                 case 4:
 333                         lane_mask = PWR_UP_ALL_LANES;
 334                         break;
 335                 }
 336         } else {
 337                 switch (lane_count) {
 338                 case 1:
 339                         lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
 340                                                     PWR_DOWN_LN_3_2_1;
 341                         break;
 342                 case 2:
 343                         lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
 344                                                     PWR_DOWN_LN_3_2;
 345                         break;
 346                 default:
 347                         MISSING_CASE(lane_count);
 348                         fallthrough;
 349                 case 4:
 350                         lane_mask = PWR_UP_ALL_LANES;
 351                         break;
 352                 }
 353         }
 354
 355         val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
 356         val &= ~PWR_DOWN_LN_MASK;
 357         val |= lane_mask << PWR_DOWN_LN_SHIFT;
 358         intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
 359 }
 360
 361 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 362 {
 363         enum phy phy;
 364
 365         for_each_combo_phy(dev_priv, phy) {
 366                 u32 val;
 367
 368                 if (icl_combo_phy_verify_state(dev_priv, phy)) {
 369                         drm_dbg(&dev_priv->drm,
 370                                 "Combo PHY %c already enabled, won't reprogram it.\n",
 371                                 phy_name(phy));
 372                         continue;
 373                 }
 374
 375                 if (!has_phy_misc(dev_priv, phy))
 376                         goto skip_phy_misc;
 377
 378                 /*
 379                  * EHL's combo PHY A can be hooked up to either an external
 380                  * display (via DDI-D) or an internal display (via DDI-A or
 381                  * the DSI DPHY).  This is a motherboard design decision that
 382                  * can't be changed on the fly, so initialize the PHY's mux
 383                  * based on whether our VBT indicates the presence of any
 384                  * "internal" child devices.
 385                  */
 386                 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
 387                 if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
 388                         val &= ~ICL_PHY_MISC_MUX_DDID;
 389
 390                         if (ehl_vbt_ddi_d_present(dev_priv))
 391                                 val |= ICL_PHY_MISC_MUX_DDID;
 392                 }
 393
 394                 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
 395                 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
 396
 397 skip_phy_misc:
 398                 if (INTEL_GEN(dev_priv) >= 12) {
 399                         val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
 400                         val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
 401                         val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
 402                         val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
 403                         intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
 404
 405                         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
 406                         val &= ~DCC_MODE_SELECT_MASK;
 407                         val |= DCC_MODE_SELECT_CONTINUOSLY;
 408                         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
 409                 }
 410
 411                 cnl_set_procmon_ref_values(dev_priv, phy);
 412
 413                 if (phy_is_master(dev_priv, phy)) {
 414                         val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
 415                         val |= IREFGEN;
 416                         intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
 417                 }
 418
 419                 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
 420                 val |= COMP_INIT;
 421                 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
 422
 423                 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
 424                 val |= CL_POWER_DOWN_ENABLE;
 425                 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
 426         }
 427 }
 428
 429 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 430 {
 431         enum phy phy;
 432
 433         for_each_combo_phy_reverse(dev_priv, phy) {
 434                 u32 val;
 435
 436                 if (phy == PHY_A &&
 437                     !icl_combo_phy_verify_state(dev_priv, phy)) {
 438                         if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
 439                                 /*
 440                                  * A known problem with old ifwi:
 441                                  * https://gitlab.freedesktop.org/drm/intel/-/issues/2411
 442                                  * Suppress the warning for CI. Remove ASAP!
 443                                  */
 444                                 drm_dbg_kms(&dev_priv->drm,
 445                                             "Combo PHY %c HW state changed unexpectedly\n",
 446                                             phy_name(phy));
 447                         } else {
 448                                 drm_warn(&dev_priv->drm,
 449                                          "Combo PHY %c HW state changed unexpectedly\n",
 450                                          phy_name(phy));
 451                         }
 452                 }
 453
 454                 if (!has_phy_misc(dev_priv, phy))
 455                         goto skip_phy_misc;
 456
 457                 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
 458                 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
 459                 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
 460
 461 skip_phy_misc:
 462                 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
 463                 val &= ~COMP_INIT;
 464                 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
 465         }
 466 }
 467
 468 void intel_combo_phy_init(struct drm_i915_private *i915)
 469 {
 470         if (INTEL_GEN(i915) >= 11)
 471                 icl_combo_phys_init(i915);
 472         else if (IS_CANNONLAKE(i915))
 473                 cnl_combo_phys_init(i915);
 474 }
 475
 476 void intel_combo_phy_uninit(struct drm_i915_private *i915)
 477 {
 478         if (INTEL_GEN(i915) >= 11)
 479                 icl_combo_phys_uninit(i915);
 480         else if (IS_CANNONLAKE(i915))
 481                 cnl_combo_phys_uninit(i915);
 482 }