drivers/gpu/drm/i915/display/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_color.h"
  26 #include "intel_display_types.h"
  27
  28 #define CTM_COEFF_SIGN  (1ULL << 63)
  29
  30 #define CTM_COEFF_1_0   (1ULL << 32)
  31 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  32 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  33 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  34 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  35 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  36 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  37
  38 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  39
  40 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  41 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  42
  43 #define LEGACY_LUT_LENGTH               256
  44
  45 /*
  46  * ILK+ csc matrix:
  47  *
  48  * |R/Cr|   | c0 c1 c2 |   ( |R/Cr|   |preoff0| )   |postoff0|
  49  * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
  50  * |B/Cb|   | c6 c7 c8 |   ( |B/Cb|   |preoff2| )   |postoff2|
  51  *
  52  * ILK/SNB don't have explicit post offsets, and instead
  53  * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
  54  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
  55  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
  56  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
  57  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
  58  */
  59
  60 /*
  61  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  62  * format). This macro takes the coefficient we want transformed and the
  63  * number of fractional bits.
  64  *
  65  * We only have a 9 bits precision window which slides depending on the value
  66  * of the CTM coefficient and we write the value from bit 3. We also round the
  67  * value.
  68  */
  69 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  70         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  71
  72 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
  73 #define ILK_CSC_COEFF_1_0 0x7800
  74
  75 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
  76
  77 /* Nop pre/post offsets */
  78 static const u16 ilk_csc_off_zero[3] = {};
  79
  80 /* Identity matrix */
  81 static const u16 ilk_csc_coeff_identity[9] = {
  82         ILK_CSC_COEFF_1_0, 0, 0,
  83         0, ILK_CSC_COEFF_1_0, 0,
  84         0, 0, ILK_CSC_COEFF_1_0,
  85 };
  86
  87 /* Limited range RGB post offsets */
  88 static const u16 ilk_csc_postoff_limited_range[3] = {
  89         ILK_CSC_POSTOFF_LIMITED_RANGE,
  90         ILK_CSC_POSTOFF_LIMITED_RANGE,
  91         ILK_CSC_POSTOFF_LIMITED_RANGE,
  92 };
  93
  94 /* Full range RGB -> limited range RGB matrix */
  95 static const u16 ilk_csc_coeff_limited_range[9] = {
  96         ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
  97         0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
  98         0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
  99 };
 100
 101 /* BT.709 full range RGB -> limited range YCbCr matrix */
 102 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
 103         0x1e08, 0x9cc0, 0xb528,
 104         0x2ba8, 0x09d8, 0x37e8,
 105         0xbce8, 0x9ad8, 0x1e08,
 106 };
 107
 108 /* Limited range YCbCr post offsets */
 109 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
 110         0x0800, 0x0100, 0x0800,
 111 };
 112
 113 static bool lut_is_legacy(const struct drm_property_blob *lut)
 114 {
 115         return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
 116 }
 117
 118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
 119 {
 120         return !crtc_state->base.degamma_lut &&
 121                 !crtc_state->base.ctm &&
 122                 crtc_state->base.gamma_lut &&
 123                 lut_is_legacy(crtc_state->base.gamma_lut);
 124 }
 125
 126 /*
 127  * When using limited range, multiply the matrix given by userspace by
 128  * the matrix that we would use for the limited range.
 129  */
 130 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 131 {
 132         int i;
 133
 134         for (i = 0; i < 9; i++) {
 135                 u64 user_coeff = input[i];
 136                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
 137                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
 138                                           CTM_COEFF_4_0 - 1) >> 2;
 139
 140                 /*
 141                  * By scaling every co-efficient with limited range (16-235)
 142                  * vs full range (0-255) the final o/p will be scaled down to
 143                  * fit in the limited range supported by the panel.
 144                  */
 145                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 146                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 147         }
 148
 149         return result;
 150 }
 151
 152 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
 153                                 const u16 preoff[3],
 154                                 const u16 coeff[9],
 155                                 const u16 postoff[3])
 156 {
 157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 158         enum pipe pipe = crtc->pipe;
 159
 160         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
 161         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
 162         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
 163
 164         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
 165         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
 166
 167         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
 168         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
 169
 170         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
 171         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
 172
 173         if (INTEL_GEN(dev_priv) >= 7) {
 174                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]);
 175                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]);
 176                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]);
 177         }
 178 }
 179
 180 static void icl_update_output_csc(struct intel_crtc *crtc,
 181                                   const u16 preoff[3],
 182                                   const u16 coeff[9],
 183                                   const u16 postoff[3])
 184 {
 185         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 186         enum pipe pipe = crtc->pipe;
 187
 188         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
 189         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
 190         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
 191
 192         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
 193         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16);
 194
 195         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
 196         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16);
 197
 198         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
 199         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16);
 200
 201         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
 202         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
 203         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
 204 }
 205
 206 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 207 {
 208         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 209
 210         /*
 211          * FIXME if there's a gamma LUT after the CSC, we should
 212          * do the range compression using the gamma LUT instead.
 213          */
 214         return crtc_state->limited_color_range &&
 215                 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
 216                  IS_GEN_RANGE(dev_priv, 9, 10));
 217 }
 218
 219 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 220                                 u16 coeffs[9])
 221 {
 222         const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 223         const u64 *input;
 224         u64 temp[9];
 225         int i;
 226
 227         if (ilk_csc_limited_range(crtc_state))
 228                 input = ctm_mult_by_limited(temp, ctm->matrix);
 229         else
 230                 input = ctm->matrix;
 231
 232         /*
 233          * Convert fixed point S31.32 input to format supported by the
 234          * hardware.
 235          */
 236         for (i = 0; i < 9; i++) {
 237                 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
 238
 239                 /*
 240                  * Clamp input value to min/max supported by
 241                  * hardware.
 242                  */
 243                 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 244
 245                 coeffs[i] = 0;
 246
 247                 /* sign bit */
 248                 if (CTM_COEFF_NEGATIVE(input[i]))
 249                         coeffs[i] |= 1 << 15;
 250
 251                 if (abs_coeff < CTM_COEFF_0_125)
 252                         coeffs[i] |= (3 << 12) |
 253                                 ILK_CSC_COEFF_FP(abs_coeff, 12);
 254                 else if (abs_coeff < CTM_COEFF_0_25)
 255                         coeffs[i] |= (2 << 12) |
 256                                 ILK_CSC_COEFF_FP(abs_coeff, 11);
 257                 else if (abs_coeff < CTM_COEFF_0_5)
 258                         coeffs[i] |= (1 << 12) |
 259                                 ILK_CSC_COEFF_FP(abs_coeff, 10);
 260                 else if (abs_coeff < CTM_COEFF_1_0)
 261                         coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 262                 else if (abs_coeff < CTM_COEFF_2_0)
 263                         coeffs[i] |= (7 << 12) |
 264                                 ILK_CSC_COEFF_FP(abs_coeff, 8);
 265                 else
 266                         coeffs[i] |= (6 << 12) |
 267                                 ILK_CSC_COEFF_FP(abs_coeff, 7);
 268         }
 269 }
 270
 271 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 272 {
 273         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 274         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 275         bool limited_color_range = ilk_csc_limited_range(crtc_state);
 276
 277         if (crtc_state->base.ctm) {
 278                 u16 coeff[9];
 279
 280                 ilk_csc_convert_ctm(crtc_state, coeff);
 281                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
 282                                     limited_color_range ?
 283                                     ilk_csc_postoff_limited_range :
 284                                     ilk_csc_off_zero);
 285         } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 286                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 287                                     ilk_csc_coeff_rgb_to_ycbcr,
 288                                     ilk_csc_postoff_rgb_to_ycbcr);
 289         } else if (limited_color_range) {
 290                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 291                                     ilk_csc_coeff_limited_range,
 292                                     ilk_csc_postoff_limited_range);
 293         } else if (crtc_state->csc_enable) {
 294                 /*
 295                  * On GLK+ both pipe CSC and degamma LUT are controlled
 296                  * by csc_enable. Hence for the cases where the degama
 297                  * LUT is needed but CSC is not we need to load an
 298                  * identity matrix.
 299                  */
 300                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_GEMINILAKE(dev_priv));
 301
 302                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 303                                     ilk_csc_coeff_identity,
 304                                     ilk_csc_off_zero);
 305         }
 306
 307         I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 308 }
 309
 310 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 311 {
 312         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 313         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 314
 315         if (crtc_state->base.ctm) {
 316                 u16 coeff[9];
 317
 318                 ilk_csc_convert_ctm(crtc_state, coeff);
 319                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 320                                     coeff, ilk_csc_off_zero);
 321         }
 322
 323         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 324                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 325                                       ilk_csc_coeff_rgb_to_ycbcr,
 326                                       ilk_csc_postoff_rgb_to_ycbcr);
 327         } else if (crtc_state->limited_color_range) {
 328                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 329                                       ilk_csc_coeff_limited_range,
 330                                       ilk_csc_postoff_limited_range);
 331         }
 332
 333         I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 334 }
 335
 336 /*
 337  * Set up the pipe CSC unit on CherryView.
 338  */
 339 static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 340 {
 341         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 342         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 343         enum pipe pipe = crtc->pipe;
 344
 345         if (crtc_state->base.ctm) {
 346                 const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 347                 u16 coeffs[9] = {};
 348                 int i;
 349
 350                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 351                         u64 abs_coeff =
 352                                 ((1ULL << 63) - 1) & ctm->matrix[i];
 353
 354                         /* Round coefficient. */
 355                         abs_coeff += 1 << (32 - 13);
 356                         /* Clamp to hardware limits. */
 357                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 358
 359                         /* Write coefficients in S3.12 format. */
 360                         if (ctm->matrix[i] & (1ULL << 63))
 361                                 coeffs[i] = 1 << 15;
 362                         coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 363                         coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 364                 }
 365
 366                 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
 367                            coeffs[1] << 16 | coeffs[0]);
 368                 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
 369                            coeffs[3] << 16 | coeffs[2]);
 370                 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
 371                            coeffs[5] << 16 | coeffs[4]);
 372                 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
 373                            coeffs[7] << 16 | coeffs[6]);
 374                 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 375         }
 376
 377         I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
 378 }
 379
 380 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 381 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 382 {
 383         return (color->red & 0xff) << 16 |
 384                 (color->green & 0xff) << 8 |
 385                 (color->blue & 0xff);
 386 }
 387
 388 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
 389 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
 390 {
 391         return (color->red >> 8) << 16 |
 392                 (color->green >> 8) << 8 |
 393                 (color->blue >> 8);
 394 }
 395
 396 static u32 ilk_lut_10(const struct drm_color_lut *color)
 397 {
 398         return drm_color_lut_extract(color->red, 10) << 20 |
 399                 drm_color_lut_extract(color->green, 10) << 10 |
 400                 drm_color_lut_extract(color->blue, 10);
 401 }
 402
 403 /* Loads the legacy palette/gamma unit for the CRTC. */
 404 static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 405                                     const struct drm_property_blob *blob)
 406 {
 407         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 408         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 409         enum pipe pipe = crtc->pipe;
 410         int i;
 411
 412         if (HAS_GMCH(dev_priv)) {
 413                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 414                         assert_dsi_pll_enabled(dev_priv);
 415                 else
 416                         assert_pll_enabled(dev_priv, pipe);
 417         }
 418
 419         if (blob) {
 420                 const struct drm_color_lut *lut = blob->data;
 421
 422                 for (i = 0; i < 256; i++) {
 423                         u32 word =
 424                                 (drm_color_lut_extract(lut[i].red, 8) << 16) |
 425                                 (drm_color_lut_extract(lut[i].green, 8) << 8) |
 426                                 drm_color_lut_extract(lut[i].blue, 8);
 427
 428                         if (HAS_GMCH(dev_priv))
 429                                 I915_WRITE(PALETTE(pipe, i), word);
 430                         else
 431                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 432                 }
 433         }
 434 }
 435
 436 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 437 {
 438         i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 439 }
 440
 441 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 442 {
 443         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 444         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 445         enum pipe pipe = crtc->pipe;
 446         u32 val;
 447
 448         val = I915_READ(PIPECONF(pipe));
 449         val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
 450         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 451         I915_WRITE(PIPECONF(pipe), val);
 452 }
 453
 454 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
 455 {
 456         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 458         enum pipe pipe = crtc->pipe;
 459         u32 val;
 460
 461         val = I915_READ(PIPECONF(pipe));
 462         val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
 463         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 464         I915_WRITE(PIPECONF(pipe), val);
 465
 466         ilk_load_csc_matrix(crtc_state);
 467 }
 468
 469 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 470 {
 471         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 472         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 473
 474         I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 475
 476         ilk_load_csc_matrix(crtc_state);
 477 }
 478
 479 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 480 {
 481         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 482         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 483         enum pipe pipe = crtc->pipe;
 484         u32 val = 0;
 485
 486         /*
 487          * We don't (yet) allow userspace to control the pipe background color,
 488          * so force it to black, but apply pipe gamma and CSC appropriately
 489          * so that its handling will match how we program our planes.
 490          */
 491         if (crtc_state->gamma_enable)
 492                 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
 493         if (crtc_state->csc_enable)
 494                 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
 495         I915_WRITE(SKL_BOTTOM_COLOR(pipe), val);
 496
 497         I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 498
 499         if (INTEL_GEN(dev_priv) >= 11)
 500                 icl_load_csc_matrix(crtc_state);
 501         else
 502                 ilk_load_csc_matrix(crtc_state);
 503 }
 504
 505 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 506                                const struct drm_property_blob *blob)
 507 {
 508         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 509         const struct drm_color_lut *lut = blob->data;
 510         int i, lut_size = drm_color_lut_size(blob);
 511         enum pipe pipe = crtc->pipe;
 512
 513         for (i = 0; i < lut_size - 1; i++) {
 514                 I915_WRITE(PALETTE(pipe, 2 * i + 0),
 515                            i965_lut_10p6_ldw(&lut[i]));
 516                 I915_WRITE(PALETTE(pipe, 2 * i + 1),
 517                            i965_lut_10p6_udw(&lut[i]));
 518         }
 519
 520         I915_WRITE(PIPEGCMAX(pipe, 0), lut[i].red);
 521         I915_WRITE(PIPEGCMAX(pipe, 1), lut[i].green);
 522         I915_WRITE(PIPEGCMAX(pipe, 2), lut[i].blue);
 523 }
 524
 525 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 526 {
 527         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 528         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 529
 530         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 531                 i9xx_load_luts(crtc_state);
 532         else
 533                 i965_load_lut_10p6(crtc, gamma_lut);
 534 }
 535
 536 static void ilk_load_lut_10(struct intel_crtc *crtc,
 537                             const struct drm_property_blob *blob)
 538 {
 539         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 540         const struct drm_color_lut *lut = blob->data;
 541         int i, lut_size = drm_color_lut_size(blob);
 542         enum pipe pipe = crtc->pipe;
 543
 544         for (i = 0; i < lut_size; i++)
 545                 I915_WRITE(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i]));
 546 }
 547
 548 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 549 {
 550         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 551         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 552
 553         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 554                 i9xx_load_luts(crtc_state);
 555         else
 556                 ilk_load_lut_10(crtc, gamma_lut);
 557 }
 558
 559 static int ivb_lut_10_size(u32 prec_index)
 560 {
 561         if (prec_index & PAL_PREC_SPLIT_MODE)
 562                 return 512;
 563         else
 564                 return 1024;
 565 }
 566
 567 /*
 568  * IVB/HSW Bspec / PAL_PREC_INDEX:
 569  * "Restriction : Index auto increment mode is not
 570  *  supported and must not be enabled."
 571  */
 572 static void ivb_load_lut_10(struct intel_crtc *crtc,
 573                             const struct drm_property_blob *blob,
 574                             u32 prec_index)
 575 {
 576         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 577         int hw_lut_size = ivb_lut_10_size(prec_index);
 578         const struct drm_color_lut *lut = blob->data;
 579         int i, lut_size = drm_color_lut_size(blob);
 580         enum pipe pipe = crtc->pipe;
 581
 582         for (i = 0; i < hw_lut_size; i++) {
 583                 /* We discard half the user entries in split gamma mode */
 584                 const struct drm_color_lut *entry =
 585                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 586
 587                 I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
 588                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry));
 589         }
 590
 591         /*
 592          * Reset the index, otherwise it prevents the legacy palette to be
 593          * written properly.
 594          */
 595         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 596 }
 597
 598 /* On BDW+ the index auto increment mode actually works */
 599 static void bdw_load_lut_10(struct intel_crtc *crtc,
 600                             const struct drm_property_blob *blob,
 601                             u32 prec_index)
 602 {
 603         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 604         int hw_lut_size = ivb_lut_10_size(prec_index);
 605         const struct drm_color_lut *lut = blob->data;
 606         int i, lut_size = drm_color_lut_size(blob);
 607         enum pipe pipe = crtc->pipe;
 608
 609         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
 610                    PAL_PREC_AUTO_INCREMENT);
 611
 612         for (i = 0; i < hw_lut_size; i++) {
 613                 /* We discard half the user entries in split gamma mode */
 614                 const struct drm_color_lut *entry =
 615                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 616
 617                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry));
 618         }
 619
 620         /*
 621          * Reset the index, otherwise it prevents the legacy palette to be
 622          * written properly.
 623          */
 624         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 625 }
 626
 627 static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
 628 {
 629         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 630         struct intel_dsb *dsb = intel_dsb_get(crtc);
 631         enum pipe pipe = crtc->pipe;
 632
 633         /* Program the max register to clamp values > 1.0. */
 634         intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
 635         intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
 636         intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
 637
 638         /*
 639          * Program the gc max 2 register to clamp values > 1.0.
 640          * ToDo: Extend the ABI to be able to program values
 641          * from 3.0 to 7.0
 642          */
 643         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 644                 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
 645                                     1 << 16);
 646                 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
 647                                     1 << 16);
 648                 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
 649                                     1 << 16);
 650         }
 651
 652         intel_dsb_put(dsb);
 653 }
 654
 655 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 656 {
 657         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 658         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 659         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 660
 661         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 662                 i9xx_load_luts(crtc_state);
 663         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 664                 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 665                                 PAL_PREC_INDEX_VALUE(0));
 666                 ivb_load_lut_ext_max(crtc);
 667                 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 668                                 PAL_PREC_INDEX_VALUE(512));
 669         } else {
 670                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 671
 672                 ivb_load_lut_10(crtc, blob,
 673                                 PAL_PREC_INDEX_VALUE(0));
 674                 ivb_load_lut_ext_max(crtc);
 675         }
 676 }
 677
 678 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 679 {
 680         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 681         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 682         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 683
 684         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 685                 i9xx_load_luts(crtc_state);
 686         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 687                 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 688                                 PAL_PREC_INDEX_VALUE(0));
 689                 ivb_load_lut_ext_max(crtc);
 690                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 691                                 PAL_PREC_INDEX_VALUE(512));
 692         } else {
 693                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 694
 695                 bdw_load_lut_10(crtc, blob,
 696                                 PAL_PREC_INDEX_VALUE(0));
 697                 ivb_load_lut_ext_max(crtc);
 698         }
 699 }
 700
 701 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 702 {
 703         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 704         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 705         enum pipe pipe = crtc->pipe;
 706         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 707         const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
 708         u32 i;
 709
 710         /*
 711          * When setting the auto-increment bit, the hardware seems to
 712          * ignore the index bits, so we need to reset it to index 0
 713          * separately.
 714          */
 715         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 716         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 717
 718         for (i = 0; i < lut_size; i++) {
 719                 /*
 720                  * First 33 entries represent range from 0 to 1.0
 721                  * 34th and 35th entry will represent extended range
 722                  * inputs 3.0 and 7.0 respectively, currently clamped
 723                  * at 1.0. Since the precision is 16bit, the user
 724                  * value can be directly filled to register.
 725                  * The pipe degamma table in GLK+ onwards doesn't
 726                  * support different values per channel, so this just
 727                  * programs green value which will be equal to Red and
 728                  * Blue into the lut registers.
 729                  * ToDo: Extend to max 7.0. Enable 32 bit input value
 730                  * as compared to just 16 to achieve this.
 731                  */
 732                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
 733         }
 734
 735         /* Clamp values > 1.0. */
 736         while (i++ < 35)
 737                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 738 }
 739
 740 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
 741 {
 742         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 743         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 744         enum pipe pipe = crtc->pipe;
 745         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 746         u32 i;
 747
 748         /*
 749          * When setting the auto-increment bit, the hardware seems to
 750          * ignore the index bits, so we need to reset it to index 0
 751          * separately.
 752          */
 753         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 754         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 755
 756         for (i = 0; i < lut_size; i++) {
 757                 u32 v = (i << 16) / (lut_size - 1);
 758
 759                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
 760         }
 761
 762         /* Clamp values > 1.0. */
 763         while (i++ < 35)
 764                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 765 }
 766
 767 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 768 {
 769         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 770         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 771
 772         /*
 773          * On GLK+ both pipe CSC and degamma LUT are controlled
 774          * by csc_enable. Hence for the cases where the CSC is
 775          * needed but degamma LUT is not we need to load a
 776          * linear degamma LUT. In fact we'll just always load
 777          * the degama LUT so that we don't have to reload
 778          * it every time the pipe CSC is being enabled.
 779          */
 780         if (crtc_state->base.degamma_lut)
 781                 glk_load_degamma_lut(crtc_state);
 782         else
 783                 glk_load_degamma_lut_linear(crtc_state);
 784
 785         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 786                 i9xx_load_luts(crtc_state);
 787         } else {
 788                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 789                 ivb_load_lut_ext_max(crtc);
 790         }
 791 }
 792
 793 /* ilk+ "12.4" interpolated format (high 10 bits) */
 794 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
 795 {
 796         return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
 797                 (color->blue >> 6);
 798 }
 799
 800 /* ilk+ "12.4" interpolated format (low 6 bits) */
 801 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 802 {
 803         return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
 804                 (color->blue & 0x3f) << 4;
 805 }
 806
 807 static void
 808 icl_load_gcmax(const struct intel_crtc_state *crtc_state,
 809                const struct drm_color_lut *color)
 810 {
 811         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 812         struct intel_dsb *dsb = intel_dsb_get(crtc);
 813         enum pipe pipe = crtc->pipe;
 814
 815         /* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */
 816         intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
 817         intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
 818         intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
 819         intel_dsb_put(dsb);
 820 }
 821
 822 static void
 823 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 824 {
 825         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 826         const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
 827         const struct drm_color_lut *lut = blob->data;
 828         struct intel_dsb *dsb = intel_dsb_get(crtc);
 829         enum pipe pipe = crtc->pipe;
 830         u32 i;
 831
 832         /*
 833          * Program Super Fine segment (let's call it seg1)...
 834          *
 835          * Super Fine segment's step is 1/(8 * 128 * 256) and it has
 836          * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
 837          * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
 838          */
 839         intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
 840                             PAL_PREC_AUTO_INCREMENT);
 841
 842         for (i = 0; i < 9; i++) {
 843                 const struct drm_color_lut *entry = &lut[i];
 844
 845                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
 846                                             ilk_lut_12p4_ldw(entry));
 847                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
 848                                             ilk_lut_12p4_udw(entry));
 849         }
 850
 851         intel_dsb_put(dsb);
 852 }
 853
 854 static void
 855 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 856 {
 857         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 858         const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
 859         const struct drm_color_lut *lut = blob->data;
 860         const struct drm_color_lut *entry;
 861         struct intel_dsb *dsb = intel_dsb_get(crtc);
 862         enum pipe pipe = crtc->pipe;
 863         u32 i;
 864
 865         /*
 866          * Program Fine segment (let's call it seg2)...
 867          *
 868          * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
 869          * ... 256/(128 * 256). So in order to program fine segment of LUT we
 870          * need to pick every 8th entry in the LUT, and program 256 indexes.
 871          *
 872          * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
 873          * seg2[0] being unused by the hardware.
 874          */
 875         intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
 876         for (i = 1; i < 257; i++) {
 877                 entry = &lut[i * 8];
 878                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 879                                             ilk_lut_12p4_ldw(entry));
 880                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 881                                             ilk_lut_12p4_udw(entry));
 882         }
 883
 884         /*
 885          * Program Coarse segment (let's call it seg3)...
 886          *
 887          * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
 888          * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
 889          * above, we need to pick every (8 * 128)th entry in LUT, and
 890          * program 256 of those.
 891          *
 892          * Spec is not very clear about if entries seg3[0] and seg3[1] are
 893          * being used or not, but we still need to program these to advance
 894          * the index.
 895          */
 896         for (i = 0; i < 256; i++) {
 897                 entry = &lut[i * 8 * 128];
 898                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 899                                             ilk_lut_12p4_ldw(entry));
 900                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 901                                             ilk_lut_12p4_udw(entry));
 902         }
 903
 904         /* The last entry in the LUT is to be programmed in GCMAX */
 905         entry = &lut[256 * 8 * 128];
 906         icl_load_gcmax(crtc_state, entry);
 907         ivb_load_lut_ext_max(crtc);
 908         intel_dsb_put(dsb);
 909 }
 910
 911 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 912 {
 913         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 914         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 915         struct intel_dsb *dsb = intel_dsb_get(crtc);
 916
 917         if (crtc_state->base.degamma_lut)
 918                 glk_load_degamma_lut(crtc_state);
 919
 920         switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
 921         case GAMMA_MODE_MODE_8BIT:
 922                 i9xx_load_luts(crtc_state);
 923                 break;
 924         case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 925                 icl_program_gamma_superfine_segment(crtc_state);
 926                 icl_program_gamma_multi_segment(crtc_state);
 927                 break;
 928         default:
 929                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 930                 ivb_load_lut_ext_max(crtc);
 931         }
 932
 933         intel_dsb_commit(dsb);
 934         intel_dsb_put(dsb);
 935 }
 936
 937 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
 938 {
 939         return drm_color_lut_extract(color->green, 14) << 16 |
 940                 drm_color_lut_extract(color->blue, 14);
 941 }
 942
 943 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 944 {
 945         return drm_color_lut_extract(color->red, 14);
 946 }
 947
 948 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 949                                  const struct drm_property_blob *blob)
 950 {
 951         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 952         const struct drm_color_lut *lut = blob->data;
 953         int i, lut_size = drm_color_lut_size(blob);
 954         enum pipe pipe = crtc->pipe;
 955
 956         for (i = 0; i < lut_size; i++) {
 957                 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0),
 958                            chv_cgm_degamma_ldw(&lut[i]));
 959                 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1),
 960                            chv_cgm_degamma_udw(&lut[i]));
 961         }
 962 }
 963
 964 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
 965 {
 966         return drm_color_lut_extract(color->green, 10) << 16 |
 967                 drm_color_lut_extract(color->blue, 10);
 968 }
 969
 970 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
 971 {
 972         return drm_color_lut_extract(color->red, 10);
 973 }
 974
 975 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 976                                const struct drm_property_blob *blob)
 977 {
 978         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 979         const struct drm_color_lut *lut = blob->data;
 980         int i, lut_size = drm_color_lut_size(blob);
 981         enum pipe pipe = crtc->pipe;
 982
 983         for (i = 0; i < lut_size; i++) {
 984                 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0),
 985                            chv_cgm_gamma_ldw(&lut[i]));
 986                 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1),
 987                            chv_cgm_gamma_udw(&lut[i]));
 988         }
 989 }
 990
 991 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 992 {
 993         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 994         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 995         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 996
 997         cherryview_load_csc_matrix(crtc_state);
 998
 999         if (crtc_state_is_legacy_gamma(crtc_state)) {
1000                 i9xx_load_luts(crtc_state);
1001                 return;
1002         }
1003
1004         if (degamma_lut)
1005                 chv_load_cgm_degamma(crtc, degamma_lut);
1006
1007         if (gamma_lut)
1008                 chv_load_cgm_gamma(crtc, gamma_lut);
1009 }
1010
1011 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1012 {
1013         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1014
1015         dev_priv->display.load_luts(crtc_state);
1016 }
1017
1018 void intel_color_commit(const struct intel_crtc_state *crtc_state)
1019 {
1020         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1021
1022         dev_priv->display.color_commit(crtc_state);
1023 }
1024
1025 int intel_color_check(struct intel_crtc_state *crtc_state)
1026 {
1027         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1028
1029         return dev_priv->display.color_check(crtc_state);
1030 }
1031
1032 void intel_color_get_config(struct intel_crtc_state *crtc_state)
1033 {
1034         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1035
1036         if (dev_priv->display.read_luts)
1037                 dev_priv->display.read_luts(crtc_state);
1038 }
1039
1040 static bool need_plane_update(struct intel_plane *plane,
1041                               const struct intel_crtc_state *crtc_state)
1042 {
1043         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1044
1045         /*
1046          * On pre-SKL the pipe gamma enable and pipe csc enable for
1047          * the pipe bottom color are configured via the primary plane.
1048          * We have to reconfigure that even if the plane is inactive.
1049          */
1050         return crtc_state->active_planes & BIT(plane->id) ||
1051                 (INTEL_GEN(dev_priv) < 9 &&
1052                  plane->id == PLANE_PRIMARY);
1053 }
1054
1055 static int
1056 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1057 {
1058         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1059         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1060         struct intel_atomic_state *state =
1061                 to_intel_atomic_state(new_crtc_state->base.state);
1062         const struct intel_crtc_state *old_crtc_state =
1063                 intel_atomic_get_old_crtc_state(state, crtc);
1064         struct intel_plane *plane;
1065
1066         if (!new_crtc_state->base.active ||
1067             drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
1068                 return 0;
1069
1070         if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1071             new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1072                 return 0;
1073
1074         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1075                 struct intel_plane_state *plane_state;
1076
1077                 if (!need_plane_update(plane, new_crtc_state))
1078                         continue;
1079
1080                 plane_state = intel_atomic_get_plane_state(state, plane);
1081                 if (IS_ERR(plane_state))
1082                         return PTR_ERR(plane_state);
1083
1084                 new_crtc_state->update_planes |= BIT(plane->id);
1085         }
1086
1087         return 0;
1088 }
1089
1090 static int check_lut_size(const struct drm_property_blob *lut, int expected)
1091 {
1092         int len;
1093
1094         if (!lut)
1095                 return 0;
1096
1097         len = drm_color_lut_size(lut);
1098         if (len != expected) {
1099                 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1100                               len, expected);
1101                 return -EINVAL;
1102         }
1103
1104         return 0;
1105 }
1106
1107 static int check_luts(const struct intel_crtc_state *crtc_state)
1108 {
1109         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1110         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
1111         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
1112         int gamma_length, degamma_length;
1113         u32 gamma_tests, degamma_tests;
1114
1115         /* Always allow legacy gamma LUT with no further checking. */
1116         if (crtc_state_is_legacy_gamma(crtc_state))
1117                 return 0;
1118
1119         /* C8 relies on its palette being stored in the legacy LUT */
1120         if (crtc_state->c8_planes) {
1121                 DRM_DEBUG_KMS("C8 pixelformat requires the legacy LUT\n");
1122                 return -EINVAL;
1123         }
1124
1125         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1126         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1127         degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1128         gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1129
1130         if (check_lut_size(degamma_lut, degamma_length) ||
1131             check_lut_size(gamma_lut, gamma_length))
1132                 return -EINVAL;
1133
1134         if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1135             drm_color_lut_check(gamma_lut, gamma_tests))
1136                 return -EINVAL;
1137
1138         return 0;
1139 }
1140
1141 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1142 {
1143         if (!crtc_state->gamma_enable ||
1144             crtc_state_is_legacy_gamma(crtc_state))
1145                 return GAMMA_MODE_MODE_8BIT;
1146         else
1147                 return GAMMA_MODE_MODE_10BIT; /* i965+ only */
1148 }
1149
1150 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1151 {
1152         int ret;
1153
1154         ret = check_luts(crtc_state);
1155         if (ret)
1156                 return ret;
1157
1158         crtc_state->gamma_enable =
1159                 crtc_state->base.gamma_lut &&
1160                 !crtc_state->c8_planes;
1161
1162         crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1163
1164         ret = intel_color_add_affected_planes(crtc_state);
1165         if (ret)
1166                 return ret;
1167
1168         return 0;
1169 }
1170
1171 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1172 {
1173         u32 cgm_mode = 0;
1174
1175         if (crtc_state_is_legacy_gamma(crtc_state))
1176                 return 0;
1177
1178         if (crtc_state->base.degamma_lut)
1179                 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1180         if (crtc_state->base.ctm)
1181                 cgm_mode |= CGM_PIPE_MODE_CSC;
1182         if (crtc_state->base.gamma_lut)
1183                 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1184
1185         return cgm_mode;
1186 }
1187
1188 /*
1189  * CHV color pipeline:
1190  * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
1191  * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
1192  *
1193  * We always bypass the WGC csc and use the CGM csc
1194  * instead since it has degamma and better precision.
1195  */
1196 static int chv_color_check(struct intel_crtc_state *crtc_state)
1197 {
1198         int ret;
1199
1200         ret = check_luts(crtc_state);
1201         if (ret)
1202                 return ret;
1203
1204         /*
1205          * Pipe gamma will be used only for the legacy LUT.
1206          * Otherwise we bypass it and use the CGM gamma instead.
1207          */
1208         crtc_state->gamma_enable =
1209                 crtc_state_is_legacy_gamma(crtc_state) &&
1210                 !crtc_state->c8_planes;
1211
1212         crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1213
1214         crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1215
1216         ret = intel_color_add_affected_planes(crtc_state);
1217         if (ret)
1218                 return ret;
1219
1220         return 0;
1221 }
1222
1223 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1224 {
1225         if (!crtc_state->gamma_enable ||
1226             crtc_state_is_legacy_gamma(crtc_state))
1227                 return GAMMA_MODE_MODE_8BIT;
1228         else
1229                 return GAMMA_MODE_MODE_10BIT;
1230 }
1231
1232 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1233 {
1234         /*
1235          * CSC comes after the LUT in RGB->YCbCr mode.
1236          * RGB->YCbCr needs the limited range offsets added to
1237          * the output. RGB limited range output is handled by
1238          * the hw automagically elsewhere.
1239          */
1240         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1241                 return CSC_BLACK_SCREEN_OFFSET;
1242
1243         return CSC_MODE_YUV_TO_RGB |
1244                 CSC_POSITION_BEFORE_GAMMA;
1245 }
1246
1247 static int ilk_color_check(struct intel_crtc_state *crtc_state)
1248 {
1249         int ret;
1250
1251         ret = check_luts(crtc_state);
1252         if (ret)
1253                 return ret;
1254
1255         crtc_state->gamma_enable =
1256                 crtc_state->base.gamma_lut &&
1257                 !crtc_state->c8_planes;
1258
1259         /*
1260          * We don't expose the ctm on ilk/snb currently, also RGB
1261          * limited range output is handled by the hw automagically.
1262          */
1263         crtc_state->csc_enable =
1264                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1265
1266         crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1267
1268         crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1269
1270         ret = intel_color_add_affected_planes(crtc_state);
1271         if (ret)
1272                 return ret;
1273
1274         return 0;
1275 }
1276
1277 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1278 {
1279         if (!crtc_state->gamma_enable ||
1280             crtc_state_is_legacy_gamma(crtc_state))
1281                 return GAMMA_MODE_MODE_8BIT;
1282         else if (crtc_state->base.gamma_lut &&
1283                  crtc_state->base.degamma_lut)
1284                 return GAMMA_MODE_MODE_SPLIT;
1285         else
1286                 return GAMMA_MODE_MODE_10BIT;
1287 }
1288
1289 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1290 {
1291         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1292
1293         /*
1294          * CSC comes after the LUT in degamma, RGB->YCbCr,
1295          * and RGB full->limited range mode.
1296          */
1297         if (crtc_state->base.degamma_lut ||
1298             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1299             limited_color_range)
1300                 return 0;
1301
1302         return CSC_POSITION_BEFORE_GAMMA;
1303 }
1304
1305 static int ivb_color_check(struct intel_crtc_state *crtc_state)
1306 {
1307         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1308         int ret;
1309
1310         ret = check_luts(crtc_state);
1311         if (ret)
1312                 return ret;
1313
1314         crtc_state->gamma_enable =
1315                 (crtc_state->base.gamma_lut ||
1316                  crtc_state->base.degamma_lut) &&
1317                 !crtc_state->c8_planes;
1318
1319         crtc_state->csc_enable =
1320                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1321                 crtc_state->base.ctm || limited_color_range;
1322
1323         crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1324
1325         crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1326
1327         ret = intel_color_add_affected_planes(crtc_state);
1328         if (ret)
1329                 return ret;
1330
1331         return 0;
1332 }
1333
1334 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1335 {
1336         if (!crtc_state->gamma_enable ||
1337             crtc_state_is_legacy_gamma(crtc_state))
1338                 return GAMMA_MODE_MODE_8BIT;
1339         else
1340                 return GAMMA_MODE_MODE_10BIT;
1341 }
1342
1343 static int glk_color_check(struct intel_crtc_state *crtc_state)
1344 {
1345         int ret;
1346
1347         ret = check_luts(crtc_state);
1348         if (ret)
1349                 return ret;
1350
1351         crtc_state->gamma_enable =
1352                 crtc_state->base.gamma_lut &&
1353                 !crtc_state->c8_planes;
1354
1355         /* On GLK+ degamma LUT is controlled by csc_enable */
1356         crtc_state->csc_enable =
1357                 crtc_state->base.degamma_lut ||
1358                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1359                 crtc_state->base.ctm || crtc_state->limited_color_range;
1360
1361         crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1362
1363         crtc_state->csc_mode = 0;
1364
1365         ret = intel_color_add_affected_planes(crtc_state);
1366         if (ret)
1367                 return ret;
1368
1369         return 0;
1370 }
1371
1372 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1373 {
1374         u32 gamma_mode = 0;
1375
1376         if (crtc_state->base.degamma_lut)
1377                 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1378
1379         if (crtc_state->base.gamma_lut &&
1380             !crtc_state->c8_planes)
1381                 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1382
1383         if (!crtc_state->base.gamma_lut ||
1384             crtc_state_is_legacy_gamma(crtc_state))
1385                 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1386         else
1387                 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1388
1389         return gamma_mode;
1390 }
1391
1392 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1393 {
1394         u32 csc_mode = 0;
1395
1396         if (crtc_state->base.ctm)
1397                 csc_mode |= ICL_CSC_ENABLE;
1398
1399         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1400             crtc_state->limited_color_range)
1401                 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1402
1403         return csc_mode;
1404 }
1405
1406 static int icl_color_check(struct intel_crtc_state *crtc_state)
1407 {
1408         int ret;
1409
1410         ret = check_luts(crtc_state);
1411         if (ret)
1412                 return ret;
1413
1414         crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1415
1416         crtc_state->csc_mode = icl_csc_mode(crtc_state);
1417
1418         return 0;
1419 }
1420
1421 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1422 {
1423         if (!crtc_state->gamma_enable)
1424                 return 0;
1425
1426         switch (crtc_state->gamma_mode) {
1427         case GAMMA_MODE_MODE_8BIT:
1428                 return 8;
1429         case GAMMA_MODE_MODE_10BIT:
1430                 return 16;
1431         default:
1432                 MISSING_CASE(crtc_state->gamma_mode);
1433                 return 0;
1434         }
1435 }
1436
1437 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1438 {
1439         if (!crtc_state->gamma_enable)
1440                 return 0;
1441
1442         if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1443                 return 0;
1444
1445         switch (crtc_state->gamma_mode) {
1446         case GAMMA_MODE_MODE_8BIT:
1447                 return 8;
1448         case GAMMA_MODE_MODE_10BIT:
1449                 return 10;
1450         default:
1451                 MISSING_CASE(crtc_state->gamma_mode);
1452                 return 0;
1453         }
1454 }
1455
1456 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1457 {
1458         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1459                 return 10;
1460         else
1461                 return i9xx_gamma_precision(crtc_state);
1462 }
1463
1464 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1465 {
1466         if (!crtc_state->gamma_enable)
1467                 return 0;
1468
1469         switch (crtc_state->gamma_mode) {
1470         case GAMMA_MODE_MODE_8BIT:
1471                 return 8;
1472         case GAMMA_MODE_MODE_10BIT:
1473                 return 10;
1474         default:
1475                 MISSING_CASE(crtc_state->gamma_mode);
1476                 return 0;
1477         }
1478 }
1479
1480 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1481 {
1482         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1483         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1484
1485         if (HAS_GMCH(dev_priv)) {
1486                 if (IS_CHERRYVIEW(dev_priv))
1487                         return chv_gamma_precision(crtc_state);
1488                 else
1489                         return i9xx_gamma_precision(crtc_state);
1490         } else {
1491                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1492                         return glk_gamma_precision(crtc_state);
1493                 else if (IS_IRONLAKE(dev_priv))
1494                         return ilk_gamma_precision(crtc_state);
1495         }
1496
1497         return 0;
1498 }
1499
1500 static bool err_check(struct drm_color_lut *lut1,
1501                       struct drm_color_lut *lut2, u32 err)
1502 {
1503         return ((abs((long)lut2->red - lut1->red)) <= err) &&
1504                 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1505                 ((abs((long)lut2->green - lut1->green)) <= err);
1506 }
1507
1508 static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
1509                                         struct drm_color_lut *lut2,
1510                                         int lut_size, u32 err)
1511 {
1512         int i;
1513
1514         for (i = 0; i < lut_size; i++) {
1515                 if (!err_check(&lut1[i], &lut2[i], err))
1516                         return false;
1517         }
1518
1519         return true;
1520 }
1521
1522 bool intel_color_lut_equal(struct drm_property_blob *blob1,
1523                            struct drm_property_blob *blob2,
1524                            u32 gamma_mode, u32 bit_precision)
1525 {
1526         struct drm_color_lut *lut1, *lut2;
1527         int lut_size1, lut_size2;
1528         u32 err;
1529
1530         if (!blob1 != !blob2)
1531                 return false;
1532
1533         if (!blob1)
1534                 return true;
1535
1536         lut_size1 = drm_color_lut_size(blob1);
1537         lut_size2 = drm_color_lut_size(blob2);
1538
1539         /* check sw and hw lut size */
1540         switch (gamma_mode) {
1541         case GAMMA_MODE_MODE_8BIT:
1542         case GAMMA_MODE_MODE_10BIT:
1543                 if (lut_size1 != lut_size2)
1544                         return false;
1545                 break;
1546         default:
1547                 MISSING_CASE(gamma_mode);
1548                         return false;
1549         }
1550
1551         lut1 = blob1->data;
1552         lut2 = blob2->data;
1553
1554         err = 0xffff >> bit_precision;
1555
1556         /* check sw and hw lut entry to be equal */
1557         switch (gamma_mode) {
1558         case GAMMA_MODE_MODE_8BIT:
1559         case GAMMA_MODE_MODE_10BIT:
1560                 if (!intel_color_lut_entry_equal(lut1, lut2,
1561                                                  lut_size2, err))
1562                         return false;
1563                 break;
1564         default:
1565                 MISSING_CASE(gamma_mode);
1566                         return false;
1567         }
1568
1569         return true;
1570 }
1571
1572 /* convert hw value with given bit_precision to lut property val */
1573 static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
1574 {
1575         u32 max = 0xffff >> (16 - bit_precision);
1576
1577         val = clamp_val(val, 0, max);
1578
1579         if (bit_precision < 16)
1580                 val <<= 16 - bit_precision;
1581
1582         return val;
1583 }
1584
1585 static struct drm_property_blob *
1586 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
1587 {
1588         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1589         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1590         enum pipe pipe = crtc->pipe;
1591         struct drm_property_blob *blob;
1592         struct drm_color_lut *blob_data;
1593         u32 i, val;
1594
1595         blob = drm_property_create_blob(&dev_priv->drm,
1596                                         sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1597                                         NULL);
1598         if (IS_ERR(blob))
1599                 return NULL;
1600
1601         blob_data = blob->data;
1602
1603         for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1604                 if (HAS_GMCH(dev_priv))
1605                         val = I915_READ(PALETTE(pipe, i));
1606                 else
1607                         val = I915_READ(LGC_PALETTE(pipe, i));
1608
1609                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1610                                                         LGC_PALETTE_RED_MASK, val), 8);
1611                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1612                                                           LGC_PALETTE_GREEN_MASK, val), 8);
1613                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1614                                                          LGC_PALETTE_BLUE_MASK, val), 8);
1615         }
1616
1617         return blob;
1618 }
1619
1620 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1621 {
1622         if (!crtc_state->gamma_enable)
1623                 return;
1624
1625         crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1626 }
1627
1628 static struct drm_property_blob *
1629 i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
1630 {
1631         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1632         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1633         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1634         enum pipe pipe = crtc->pipe;
1635         struct drm_property_blob *blob;
1636         struct drm_color_lut *blob_data;
1637         u32 i, val1, val2;
1638
1639         blob = drm_property_create_blob(&dev_priv->drm,
1640                                         sizeof(struct drm_color_lut) * lut_size,
1641                                         NULL);
1642         if (IS_ERR(blob))
1643                 return NULL;
1644
1645         blob_data = blob->data;
1646
1647         for (i = 0; i < lut_size - 1; i++) {
1648                 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
1649                 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
1650
1651                 blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
1652                                                  REG_FIELD_GET(PALETTE_RED_MASK, val1);
1653                 blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
1654                                                    REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
1655                 blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
1656                                                   REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
1657         }
1658
1659         blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1660                                          I915_READ(PIPEGCMAX(pipe, 0)));
1661         blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1662                                            I915_READ(PIPEGCMAX(pipe, 1)));
1663         blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1664                                           I915_READ(PIPEGCMAX(pipe, 2)));
1665
1666         return blob;
1667 }
1668
1669 static void i965_read_luts(struct intel_crtc_state *crtc_state)
1670 {
1671         if (!crtc_state->gamma_enable)
1672                 return;
1673
1674         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1675                 crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1676         else
1677                 crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
1678 }
1679
1680 static struct drm_property_blob *
1681 chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
1682 {
1683         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1684         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1685         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1686         enum pipe pipe = crtc->pipe;
1687         struct drm_property_blob *blob;
1688         struct drm_color_lut *blob_data;
1689         u32 i, val;
1690
1691         blob = drm_property_create_blob(&dev_priv->drm,
1692                                         sizeof(struct drm_color_lut) * lut_size,
1693                                         NULL);
1694         if (IS_ERR(blob))
1695                 return NULL;
1696
1697         blob_data = blob->data;
1698
1699         for (i = 0; i < lut_size; i++) {
1700                 val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
1701                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1702                                                           CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
1703                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1704                                                          CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
1705
1706                 val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
1707                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1708                                                         CGM_PIPE_GAMMA_RED_MASK, val), 10);
1709         }
1710
1711         return blob;
1712 }
1713
1714 static void chv_read_luts(struct intel_crtc_state *crtc_state)
1715 {
1716         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1717                 crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
1718         else
1719                 i965_read_luts(crtc_state);
1720 }
1721
1722 static struct drm_property_blob *
1723 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
1724 {
1725         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1726         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1727         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1728         enum pipe pipe = crtc->pipe;
1729         struct drm_property_blob *blob;
1730         struct drm_color_lut *blob_data;
1731         u32 i, val;
1732
1733         blob = drm_property_create_blob(&dev_priv->drm,
1734                                         sizeof(struct drm_color_lut) * lut_size,
1735                                         NULL);
1736         if (IS_ERR(blob))
1737                 return NULL;
1738
1739         blob_data = blob->data;
1740
1741         for (i = 0; i < lut_size; i++) {
1742                 val = I915_READ(PREC_PALETTE(pipe, i));
1743
1744                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1745                                                         PREC_PALETTE_RED_MASK, val), 10);
1746                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1747                                                           PREC_PALETTE_GREEN_MASK, val), 10);
1748                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1749                                                          PREC_PALETTE_BLUE_MASK, val), 10);
1750         }
1751
1752         return blob;
1753 }
1754
1755 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1756 {
1757         if (!crtc_state->gamma_enable)
1758                 return;
1759
1760         if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1761                 return;
1762
1763         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1764                 crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1765         else
1766                 crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
1767 }
1768
1769 static struct drm_property_blob *
1770 glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
1771 {
1772         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1773         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1774         int hw_lut_size = ivb_lut_10_size(prec_index);
1775         enum pipe pipe = crtc->pipe;
1776         struct drm_property_blob *blob;
1777         struct drm_color_lut *blob_data;
1778         u32 i, val;
1779
1780         blob = drm_property_create_blob(&dev_priv->drm,
1781                                         sizeof(struct drm_color_lut) * hw_lut_size,
1782                                         NULL);
1783         if (IS_ERR(blob))
1784                 return NULL;
1785
1786         blob_data = blob->data;
1787
1788         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
1789                    PAL_PREC_AUTO_INCREMENT);
1790
1791         for (i = 0; i < hw_lut_size; i++) {
1792                 val = I915_READ(PREC_PAL_DATA(pipe));
1793
1794                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1795                                                         PREC_PAL_DATA_RED_MASK, val), 10);
1796                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1797                                                         PREC_PAL_DATA_GREEN_MASK, val), 10);
1798                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1799                                                         PREC_PAL_DATA_BLUE_MASK, val), 10);
1800         }
1801
1802         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
1803
1804         return blob;
1805 }
1806
1807 static void glk_read_luts(struct intel_crtc_state *crtc_state)
1808 {
1809         if (!crtc_state->gamma_enable)
1810                 return;
1811
1812         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1813                 crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1814         else
1815                 crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
1816 }
1817
1818 void intel_color_init(struct intel_crtc *crtc)
1819 {
1820         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1821         bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
1822
1823         drm_mode_crtc_set_gamma_size(&crtc->base, 256);
1824
1825         if (HAS_GMCH(dev_priv)) {
1826                 if (IS_CHERRYVIEW(dev_priv)) {
1827                         dev_priv->display.color_check = chv_color_check;
1828                         dev_priv->display.color_commit = i9xx_color_commit;
1829                         dev_priv->display.load_luts = chv_load_luts;
1830                         dev_priv->display.read_luts = chv_read_luts;
1831                 } else if (INTEL_GEN(dev_priv) >= 4) {
1832                         dev_priv->display.color_check = i9xx_color_check;
1833                         dev_priv->display.color_commit = i9xx_color_commit;
1834                         dev_priv->display.load_luts = i965_load_luts;
1835                         dev_priv->display.read_luts = i965_read_luts;
1836                 } else {
1837                         dev_priv->display.color_check = i9xx_color_check;
1838                         dev_priv->display.color_commit = i9xx_color_commit;
1839                         dev_priv->display.load_luts = i9xx_load_luts;
1840                         dev_priv->display.read_luts = i9xx_read_luts;
1841                 }
1842         } else {
1843                 if (INTEL_GEN(dev_priv) >= 11)
1844                         dev_priv->display.color_check = icl_color_check;
1845                 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1846                         dev_priv->display.color_check = glk_color_check;
1847                 else if (INTEL_GEN(dev_priv) >= 7)
1848                         dev_priv->display.color_check = ivb_color_check;
1849                 else
1850                         dev_priv->display.color_check = ilk_color_check;
1851
1852                 if (INTEL_GEN(dev_priv) >= 9)
1853                         dev_priv->display.color_commit = skl_color_commit;
1854                 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1855                         dev_priv->display.color_commit = hsw_color_commit;
1856                 else
1857                         dev_priv->display.color_commit = ilk_color_commit;
1858
1859                 if (INTEL_GEN(dev_priv) >= 11) {
1860                         dev_priv->display.load_luts = icl_load_luts;
1861                 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1862                         dev_priv->display.load_luts = glk_load_luts;
1863                         dev_priv->display.read_luts = glk_read_luts;
1864                 } else if (INTEL_GEN(dev_priv) >= 8) {
1865                         dev_priv->display.load_luts = bdw_load_luts;
1866                 } else if (INTEL_GEN(dev_priv) >= 7) {
1867                         dev_priv->display.load_luts = ivb_load_luts;
1868                 } else {
1869                         dev_priv->display.load_luts = ilk_load_luts;
1870                         dev_priv->display.read_luts = ilk_read_luts;
1871                 }
1872         }
1873
1874         drm_crtc_enable_color_mgmt(&crtc->base,
1875                                    INTEL_INFO(dev_priv)->color.degamma_lut_size,
1876                                    has_ctm,
1877                                    INTEL_INFO(dev_priv)->color.gamma_lut_size);
1878 }