2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 #include "intel_color.h"
26 #include "intel_display_types.h"
28 #define CTM_COEFF_SIGN (1ULL << 63)
30 #define CTM_COEFF_1_0 (1ULL << 32)
31 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
32 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
33 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
34 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
35 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
36 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
38 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
40 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
41 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
43 #define LEGACY_LUT_LENGTH 256
48 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0|
49 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
50 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2|
52 * ILK/SNB don't have explicit post offsets, and instead
53 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
54 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
55 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
56 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
57 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
61 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
62 * format). This macro takes the coefficient we want transformed and the
63 * number of fractional bits.
65 * We only have a 9 bits precision window which slides depending on the value
66 * of the CTM coefficient and we write the value from bit 3. We also round the
69 #define ILK_CSC_COEFF_FP(coeff, fbits) \
70 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
72 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
73 #define ILK_CSC_COEFF_1_0 0x7800
75 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
77 /* Nop pre/post offsets */
78 static const u16 ilk_csc_off_zero[3] = {};
81 static const u16 ilk_csc_coeff_identity[9] = {
82 ILK_CSC_COEFF_1_0, 0, 0,
83 0, ILK_CSC_COEFF_1_0, 0,
84 0, 0, ILK_CSC_COEFF_1_0,
87 /* Limited range RGB post offsets */
88 static const u16 ilk_csc_postoff_limited_range[3] = {
89 ILK_CSC_POSTOFF_LIMITED_RANGE,
90 ILK_CSC_POSTOFF_LIMITED_RANGE,
91 ILK_CSC_POSTOFF_LIMITED_RANGE,
94 /* Full range RGB -> limited range RGB matrix */
95 static const u16 ilk_csc_coeff_limited_range[9] = {
96 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
97 0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
98 0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
101 /* BT.709 full range RGB -> limited range YCbCr matrix */
102 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
103 0x1e08, 0x9cc0, 0xb528,
104 0x2ba8, 0x09d8, 0x37e8,
105 0xbce8, 0x9ad8, 0x1e08,
108 /* Limited range YCbCr post offsets */
109 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
110 0x0800, 0x0100, 0x0800,
113 static bool lut_is_legacy(const struct drm_property_blob *lut)
115 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
120 return !crtc_state->hw.degamma_lut &&
121 !crtc_state->hw.ctm &&
122 crtc_state->hw.gamma_lut &&
123 lut_is_legacy(crtc_state->hw.gamma_lut);
127 * When using limited range, multiply the matrix given by userspace by
128 * the matrix that we would use for the limited range.
130 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
134 for (i = 0; i < 9; i++) {
135 u64 user_coeff = input[i];
136 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
137 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
138 CTM_COEFF_4_0 - 1) >> 2;
141 * By scaling every co-efficient with limited range (16-235)
142 * vs full range (0-255) the final o/p will be scaled down to
143 * fit in the limited range supported by the panel.
145 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
146 result[i] |= user_coeff & CTM_COEFF_SIGN;
152 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
155 const u16 postoff[3])
157 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
158 enum pipe pipe = crtc->pipe;
160 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
161 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
162 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
164 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
165 coeff[0] << 16 | coeff[1]);
166 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
168 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
169 coeff[3] << 16 | coeff[4]);
170 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
172 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
173 coeff[6] << 16 | coeff[7]);
174 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
176 if (INTEL_GEN(dev_priv) >= 7) {
177 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
179 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
181 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
186 static void icl_update_output_csc(struct intel_crtc *crtc,
189 const u16 postoff[3])
191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
192 enum pipe pipe = crtc->pipe;
194 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
195 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
196 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
198 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
199 coeff[0] << 16 | coeff[1]);
200 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
203 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
204 coeff[3] << 16 | coeff[4]);
205 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
208 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
209 coeff[6] << 16 | coeff[7]);
210 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
213 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
214 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
215 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
218 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
220 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
223 * FIXME if there's a gamma LUT after the CSC, we should
224 * do the range compression using the gamma LUT instead.
226 return crtc_state->limited_color_range &&
227 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
228 IS_GEN_RANGE(dev_priv, 9, 10));
231 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
234 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
239 if (ilk_csc_limited_range(crtc_state))
240 input = ctm_mult_by_limited(temp, ctm->matrix);
245 * Convert fixed point S31.32 input to format supported by the
248 for (i = 0; i < 9; i++) {
249 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
252 * Clamp input value to min/max supported by
255 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
260 if (CTM_COEFF_NEGATIVE(input[i]))
261 coeffs[i] |= 1 << 15;
263 if (abs_coeff < CTM_COEFF_0_125)
264 coeffs[i] |= (3 << 12) |
265 ILK_CSC_COEFF_FP(abs_coeff, 12);
266 else if (abs_coeff < CTM_COEFF_0_25)
267 coeffs[i] |= (2 << 12) |
268 ILK_CSC_COEFF_FP(abs_coeff, 11);
269 else if (abs_coeff < CTM_COEFF_0_5)
270 coeffs[i] |= (1 << 12) |
271 ILK_CSC_COEFF_FP(abs_coeff, 10);
272 else if (abs_coeff < CTM_COEFF_1_0)
273 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
274 else if (abs_coeff < CTM_COEFF_2_0)
275 coeffs[i] |= (7 << 12) |
276 ILK_CSC_COEFF_FP(abs_coeff, 8);
278 coeffs[i] |= (6 << 12) |
279 ILK_CSC_COEFF_FP(abs_coeff, 7);
283 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
287 bool limited_color_range = ilk_csc_limited_range(crtc_state);
289 if (crtc_state->hw.ctm) {
292 ilk_csc_convert_ctm(crtc_state, coeff);
293 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
294 limited_color_range ?
295 ilk_csc_postoff_limited_range :
297 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
298 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
299 ilk_csc_coeff_rgb_to_ycbcr,
300 ilk_csc_postoff_rgb_to_ycbcr);
301 } else if (limited_color_range) {
302 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
303 ilk_csc_coeff_limited_range,
304 ilk_csc_postoff_limited_range);
305 } else if (crtc_state->csc_enable) {
307 * On GLK+ both pipe CSC and degamma LUT are controlled
308 * by csc_enable. Hence for the cases where the degama
309 * LUT is needed but CSC is not we need to load an
312 drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
313 !IS_GEMINILAKE(dev_priv));
315 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
316 ilk_csc_coeff_identity,
320 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
321 crtc_state->csc_mode);
324 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
326 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
327 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
329 if (crtc_state->hw.ctm) {
332 ilk_csc_convert_ctm(crtc_state, coeff);
333 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
334 coeff, ilk_csc_off_zero);
337 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
338 icl_update_output_csc(crtc, ilk_csc_off_zero,
339 ilk_csc_coeff_rgb_to_ycbcr,
340 ilk_csc_postoff_rgb_to_ycbcr);
341 } else if (crtc_state->limited_color_range) {
342 icl_update_output_csc(crtc, ilk_csc_off_zero,
343 ilk_csc_coeff_limited_range,
344 ilk_csc_postoff_limited_range);
347 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
348 crtc_state->csc_mode);
351 static void chv_load_cgm_csc(struct intel_crtc *crtc,
352 const struct drm_property_blob *blob)
354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
355 const struct drm_color_ctm *ctm = blob->data;
356 enum pipe pipe = crtc->pipe;
360 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
361 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
363 /* Round coefficient. */
364 abs_coeff += 1 << (32 - 13);
365 /* Clamp to hardware limits. */
366 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
370 /* Write coefficients in S3.12 format. */
371 if (ctm->matrix[i] & (1ULL << 63))
372 coeffs[i] |= 1 << 15;
374 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
375 coeffs[i] |= (abs_coeff >> 20) & 0xfff;
378 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
379 coeffs[1] << 16 | coeffs[0]);
380 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
381 coeffs[3] << 16 | coeffs[2]);
382 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
383 coeffs[5] << 16 | coeffs[4]);
384 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
385 coeffs[7] << 16 | coeffs[6]);
386 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
390 static u32 i9xx_lut_8(const struct drm_color_lut *color)
392 return drm_color_lut_extract(color->red, 8) << 16 |
393 drm_color_lut_extract(color->green, 8) << 8 |
394 drm_color_lut_extract(color->blue, 8);
397 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
398 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
400 return (color->red & 0xff) << 16 |
401 (color->green & 0xff) << 8 |
402 (color->blue & 0xff);
405 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
406 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
408 return (color->red >> 8) << 16 |
409 (color->green >> 8) << 8 |
413 static u32 ilk_lut_10(const struct drm_color_lut *color)
415 return drm_color_lut_extract(color->red, 10) << 20 |
416 drm_color_lut_extract(color->green, 10) << 10 |
417 drm_color_lut_extract(color->blue, 10);
420 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
422 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
424 enum pipe pipe = crtc->pipe;
427 val = intel_de_read(dev_priv, PIPECONF(pipe));
428 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
429 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
430 intel_de_write(dev_priv, PIPECONF(pipe), val);
433 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
435 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
436 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
437 enum pipe pipe = crtc->pipe;
440 val = intel_de_read(dev_priv, PIPECONF(pipe));
441 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
442 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
443 intel_de_write(dev_priv, PIPECONF(pipe), val);
445 ilk_load_csc_matrix(crtc_state);
448 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
450 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
451 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
453 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
454 crtc_state->gamma_mode);
456 ilk_load_csc_matrix(crtc_state);
459 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
461 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
463 enum pipe pipe = crtc->pipe;
467 * We don't (yet) allow userspace to control the pipe background color,
468 * so force it to black, but apply pipe gamma and CSC appropriately
469 * so that its handling will match how we program our planes.
471 if (crtc_state->gamma_enable)
472 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
473 if (crtc_state->csc_enable)
474 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
475 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
477 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
478 crtc_state->gamma_mode);
480 if (INTEL_GEN(dev_priv) >= 11)
481 icl_load_csc_matrix(crtc_state);
483 ilk_load_csc_matrix(crtc_state);
486 static void i9xx_load_lut_8(struct intel_crtc *crtc,
487 const struct drm_property_blob *blob)
489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
490 const struct drm_color_lut *lut;
491 enum pipe pipe = crtc->pipe;
499 for (i = 0; i < 256; i++)
500 intel_de_write(dev_priv, PALETTE(pipe, i),
501 i9xx_lut_8(&lut[i]));
504 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
506 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
507 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
508 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
510 assert_pll_enabled(dev_priv, crtc->pipe);
512 i9xx_load_lut_8(crtc, gamma_lut);
515 static void i965_load_lut_10p6(struct intel_crtc *crtc,
516 const struct drm_property_blob *blob)
518 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
519 const struct drm_color_lut *lut = blob->data;
520 int i, lut_size = drm_color_lut_size(blob);
521 enum pipe pipe = crtc->pipe;
523 for (i = 0; i < lut_size - 1; i++) {
524 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0),
525 i965_lut_10p6_ldw(&lut[i]));
526 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1),
527 i965_lut_10p6_udw(&lut[i]));
530 intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red);
531 intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green);
532 intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue);
535 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
537 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
538 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
539 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
541 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
542 assert_dsi_pll_enabled(dev_priv);
544 assert_pll_enabled(dev_priv, crtc->pipe);
546 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
547 i9xx_load_lut_8(crtc, gamma_lut);
549 i965_load_lut_10p6(crtc, gamma_lut);
552 static void ilk_load_lut_8(struct intel_crtc *crtc,
553 const struct drm_property_blob *blob)
555 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
556 const struct drm_color_lut *lut;
557 enum pipe pipe = crtc->pipe;
565 for (i = 0; i < 256; i++)
566 intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
567 i9xx_lut_8(&lut[i]));
570 static void ilk_load_lut_10(struct intel_crtc *crtc,
571 const struct drm_property_blob *blob)
573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
574 const struct drm_color_lut *lut = blob->data;
575 int i, lut_size = drm_color_lut_size(blob);
576 enum pipe pipe = crtc->pipe;
578 for (i = 0; i < lut_size; i++)
579 intel_de_write(dev_priv, PREC_PALETTE(pipe, i),
580 ilk_lut_10(&lut[i]));
583 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
585 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
586 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
588 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
589 ilk_load_lut_8(crtc, gamma_lut);
591 ilk_load_lut_10(crtc, gamma_lut);
594 static int ivb_lut_10_size(u32 prec_index)
596 if (prec_index & PAL_PREC_SPLIT_MODE)
603 * IVB/HSW Bspec / PAL_PREC_INDEX:
604 * "Restriction : Index auto increment mode is not
605 * supported and must not be enabled."
607 static void ivb_load_lut_10(struct intel_crtc *crtc,
608 const struct drm_property_blob *blob,
611 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
612 int hw_lut_size = ivb_lut_10_size(prec_index);
613 const struct drm_color_lut *lut = blob->data;
614 int i, lut_size = drm_color_lut_size(blob);
615 enum pipe pipe = crtc->pipe;
617 for (i = 0; i < hw_lut_size; i++) {
618 /* We discard half the user entries in split gamma mode */
619 const struct drm_color_lut *entry =
620 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
622 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
623 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
628 * Reset the index, otherwise it prevents the legacy palette to be
631 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
634 /* On BDW+ the index auto increment mode actually works */
635 static void bdw_load_lut_10(struct intel_crtc *crtc,
636 const struct drm_property_blob *blob,
639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
640 int hw_lut_size = ivb_lut_10_size(prec_index);
641 const struct drm_color_lut *lut = blob->data;
642 int i, lut_size = drm_color_lut_size(blob);
643 enum pipe pipe = crtc->pipe;
645 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
646 prec_index | PAL_PREC_AUTO_INCREMENT);
648 for (i = 0; i < hw_lut_size; i++) {
649 /* We discard half the user entries in split gamma mode */
650 const struct drm_color_lut *entry =
651 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
653 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
658 * Reset the index, otherwise it prevents the legacy palette to be
661 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
664 static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
666 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
667 struct intel_dsb *dsb = intel_dsb_get(crtc);
668 enum pipe pipe = crtc->pipe;
670 /* Program the max register to clamp values > 1.0. */
671 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
672 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
673 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
676 * Program the gc max 2 register to clamp values > 1.0.
677 * ToDo: Extend the ABI to be able to program values
680 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
681 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
683 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
685 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
692 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
694 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
695 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
696 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
698 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
699 ilk_load_lut_8(crtc, gamma_lut);
700 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
701 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
702 PAL_PREC_INDEX_VALUE(0));
703 ivb_load_lut_ext_max(crtc);
704 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
705 PAL_PREC_INDEX_VALUE(512));
707 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
709 ivb_load_lut_10(crtc, blob,
710 PAL_PREC_INDEX_VALUE(0));
711 ivb_load_lut_ext_max(crtc);
715 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
717 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
718 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
719 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
721 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
722 ilk_load_lut_8(crtc, gamma_lut);
723 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
724 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
725 PAL_PREC_INDEX_VALUE(0));
726 ivb_load_lut_ext_max(crtc);
727 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
728 PAL_PREC_INDEX_VALUE(512));
730 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
732 bdw_load_lut_10(crtc, blob,
733 PAL_PREC_INDEX_VALUE(0));
734 ivb_load_lut_ext_max(crtc);
738 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
740 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
741 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
742 enum pipe pipe = crtc->pipe;
743 const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
744 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
748 * When setting the auto-increment bit, the hardware seems to
749 * ignore the index bits, so we need to reset it to index 0
752 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
753 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
754 PRE_CSC_GAMC_AUTO_INCREMENT);
756 for (i = 0; i < lut_size; i++) {
758 * First 33 entries represent range from 0 to 1.0
759 * 34th and 35th entry will represent extended range
760 * inputs 3.0 and 7.0 respectively, currently clamped
761 * at 1.0. Since the precision is 16bit, the user
762 * value can be directly filled to register.
763 * The pipe degamma table in GLK+ onwards doesn't
764 * support different values per channel, so this just
765 * programs green value which will be equal to Red and
766 * Blue into the lut registers.
767 * ToDo: Extend to max 7.0. Enable 32 bit input value
768 * as compared to just 16 to achieve this.
770 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe),
774 /* Clamp values > 1.0. */
776 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
779 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
781 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
782 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
783 enum pipe pipe = crtc->pipe;
784 const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
788 * When setting the auto-increment bit, the hardware seems to
789 * ignore the index bits, so we need to reset it to index 0
792 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
793 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
794 PRE_CSC_GAMC_AUTO_INCREMENT);
796 for (i = 0; i < lut_size; i++) {
797 u32 v = (i << 16) / (lut_size - 1);
799 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v);
802 /* Clamp values > 1.0. */
804 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
807 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
809 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
813 * On GLK+ both pipe CSC and degamma LUT are controlled
814 * by csc_enable. Hence for the cases where the CSC is
815 * needed but degamma LUT is not we need to load a
816 * linear degamma LUT. In fact we'll just always load
817 * the degama LUT so that we don't have to reload
818 * it every time the pipe CSC is being enabled.
820 if (crtc_state->hw.degamma_lut)
821 glk_load_degamma_lut(crtc_state);
823 glk_load_degamma_lut_linear(crtc_state);
825 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
826 ilk_load_lut_8(crtc, gamma_lut);
828 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
829 ivb_load_lut_ext_max(crtc);
833 /* ilk+ "12.4" interpolated format (high 10 bits) */
834 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
836 return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
840 /* ilk+ "12.4" interpolated format (low 6 bits) */
841 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
843 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
844 (color->blue & 0x3f) << 4;
848 icl_load_gcmax(const struct intel_crtc_state *crtc_state,
849 const struct drm_color_lut *color)
851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
852 struct intel_dsb *dsb = intel_dsb_get(crtc);
853 enum pipe pipe = crtc->pipe;
855 /* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */
856 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
857 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
858 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
863 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
865 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
866 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
867 const struct drm_color_lut *lut = blob->data;
868 struct intel_dsb *dsb = intel_dsb_get(crtc);
869 enum pipe pipe = crtc->pipe;
873 * Program Super Fine segment (let's call it seg1)...
875 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
876 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
877 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
879 intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
880 PAL_PREC_AUTO_INCREMENT);
882 for (i = 0; i < 9; i++) {
883 const struct drm_color_lut *entry = &lut[i];
885 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
886 ilk_lut_12p4_ldw(entry));
887 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
888 ilk_lut_12p4_udw(entry));
895 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
897 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
898 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
899 const struct drm_color_lut *lut = blob->data;
900 const struct drm_color_lut *entry;
901 struct intel_dsb *dsb = intel_dsb_get(crtc);
902 enum pipe pipe = crtc->pipe;
906 * Program Fine segment (let's call it seg2)...
908 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
909 * ... 256/(128 * 256). So in order to program fine segment of LUT we
910 * need to pick every 8th entry in the LUT, and program 256 indexes.
912 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
913 * seg2[0] being unused by the hardware.
915 intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
916 for (i = 1; i < 257; i++) {
918 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
919 ilk_lut_12p4_ldw(entry));
920 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
921 ilk_lut_12p4_udw(entry));
925 * Program Coarse segment (let's call it seg3)...
927 * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
928 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
929 * above, we need to pick every (8 * 128)th entry in LUT, and
930 * program 256 of those.
932 * Spec is not very clear about if entries seg3[0] and seg3[1] are
933 * being used or not, but we still need to program these to advance
936 for (i = 0; i < 256; i++) {
937 entry = &lut[i * 8 * 128];
938 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
939 ilk_lut_12p4_ldw(entry));
940 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
941 ilk_lut_12p4_udw(entry));
944 /* The last entry in the LUT is to be programmed in GCMAX */
945 entry = &lut[256 * 8 * 128];
946 icl_load_gcmax(crtc_state, entry);
947 ivb_load_lut_ext_max(crtc);
951 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
953 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
954 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
955 struct intel_dsb *dsb = intel_dsb_get(crtc);
957 if (crtc_state->hw.degamma_lut)
958 glk_load_degamma_lut(crtc_state);
960 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
961 case GAMMA_MODE_MODE_8BIT:
962 ilk_load_lut_8(crtc, gamma_lut);
964 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
965 icl_program_gamma_superfine_segment(crtc_state);
966 icl_program_gamma_multi_segment(crtc_state);
969 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
970 ivb_load_lut_ext_max(crtc);
973 intel_dsb_commit(dsb);
977 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
979 return drm_color_lut_extract(color->green, 14) << 16 |
980 drm_color_lut_extract(color->blue, 14);
983 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
985 return drm_color_lut_extract(color->red, 14);
988 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
989 const struct drm_property_blob *blob)
991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
992 const struct drm_color_lut *lut = blob->data;
993 int i, lut_size = drm_color_lut_size(blob);
994 enum pipe pipe = crtc->pipe;
996 for (i = 0; i < lut_size; i++) {
997 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
998 chv_cgm_degamma_ldw(&lut[i]));
999 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
1000 chv_cgm_degamma_udw(&lut[i]));
1004 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
1006 return drm_color_lut_extract(color->green, 10) << 16 |
1007 drm_color_lut_extract(color->blue, 10);
1010 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
1012 return drm_color_lut_extract(color->red, 10);
1015 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1016 const struct drm_property_blob *blob)
1018 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1019 const struct drm_color_lut *lut = blob->data;
1020 int i, lut_size = drm_color_lut_size(blob);
1021 enum pipe pipe = crtc->pipe;
1023 for (i = 0; i < lut_size; i++) {
1024 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
1025 chv_cgm_gamma_ldw(&lut[i]));
1026 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
1027 chv_cgm_gamma_udw(&lut[i]));
1031 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1033 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1034 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1035 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1036 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1037 const struct drm_property_blob *ctm = crtc_state->hw.ctm;
1039 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
1040 chv_load_cgm_csc(crtc, ctm);
1042 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
1043 chv_load_cgm_degamma(crtc, degamma_lut);
1045 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1046 chv_load_cgm_gamma(crtc, gamma_lut);
1048 i965_load_luts(crtc_state);
1050 intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
1051 crtc_state->cgm_mode);
1054 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1056 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1058 dev_priv->display.load_luts(crtc_state);
1061 void intel_color_commit(const struct intel_crtc_state *crtc_state)
1063 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1065 dev_priv->display.color_commit(crtc_state);
1068 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1070 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1071 struct intel_atomic_state *state =
1072 to_intel_atomic_state(new_crtc_state->uapi.state);
1073 const struct intel_crtc_state *old_crtc_state =
1074 intel_atomic_get_old_crtc_state(state, crtc);
1076 return !old_crtc_state->hw.gamma_lut &&
1077 !old_crtc_state->hw.degamma_lut;
1080 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1082 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1083 struct intel_atomic_state *state =
1084 to_intel_atomic_state(new_crtc_state->uapi.state);
1085 const struct intel_crtc_state *old_crtc_state =
1086 intel_atomic_get_old_crtc_state(state, crtc);
1089 * CGM_PIPE_MODE is itself single buffered. We'd have to
1090 * somehow split it out from chv_load_luts() if we wanted
1091 * the ability to preload the CGM LUTs/CSC without tearing.
1093 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1096 return !old_crtc_state->hw.gamma_lut;
1099 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1101 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1102 struct intel_atomic_state *state =
1103 to_intel_atomic_state(new_crtc_state->uapi.state);
1104 const struct intel_crtc_state *old_crtc_state =
1105 intel_atomic_get_old_crtc_state(state, crtc);
1108 * The hardware degamma is active whenever the pipe
1109 * CSC is active. Thus even if the old state has no
1110 * software degamma we need to avoid clobbering the
1111 * linear hardware degamma mid scanout.
1113 return !old_crtc_state->csc_enable &&
1114 !old_crtc_state->hw.gamma_lut;
1117 int intel_color_check(struct intel_crtc_state *crtc_state)
1119 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1121 return dev_priv->display.color_check(crtc_state);
1124 void intel_color_get_config(struct intel_crtc_state *crtc_state)
1126 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1128 if (dev_priv->display.read_luts)
1129 dev_priv->display.read_luts(crtc_state);
1132 static bool need_plane_update(struct intel_plane *plane,
1133 const struct intel_crtc_state *crtc_state)
1135 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1138 * On pre-SKL the pipe gamma enable and pipe csc enable for
1139 * the pipe bottom color are configured via the primary plane.
1140 * We have to reconfigure that even if the plane is inactive.
1142 return crtc_state->active_planes & BIT(plane->id) ||
1143 (INTEL_GEN(dev_priv) < 9 &&
1144 plane->id == PLANE_PRIMARY);
1148 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1150 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1151 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1152 struct intel_atomic_state *state =
1153 to_intel_atomic_state(new_crtc_state->uapi.state);
1154 const struct intel_crtc_state *old_crtc_state =
1155 intel_atomic_get_old_crtc_state(state, crtc);
1156 struct intel_plane *plane;
1158 if (!new_crtc_state->hw.active ||
1159 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
1162 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1163 new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1166 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1167 struct intel_plane_state *plane_state;
1169 if (!need_plane_update(plane, new_crtc_state))
1172 plane_state = intel_atomic_get_plane_state(state, plane);
1173 if (IS_ERR(plane_state))
1174 return PTR_ERR(plane_state);
1176 new_crtc_state->update_planes |= BIT(plane->id);
1182 static int check_lut_size(const struct drm_property_blob *lut, int expected)
1189 len = drm_color_lut_size(lut);
1190 if (len != expected) {
1191 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1199 static int check_luts(const struct intel_crtc_state *crtc_state)
1201 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1202 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1203 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1204 int gamma_length, degamma_length;
1205 u32 gamma_tests, degamma_tests;
1207 /* Always allow legacy gamma LUT with no further checking. */
1208 if (crtc_state_is_legacy_gamma(crtc_state))
1211 /* C8 relies on its palette being stored in the legacy LUT */
1212 if (crtc_state->c8_planes) {
1213 drm_dbg_kms(&dev_priv->drm,
1214 "C8 pixelformat requires the legacy LUT\n");
1218 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1219 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1220 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1221 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1223 if (check_lut_size(degamma_lut, degamma_length) ||
1224 check_lut_size(gamma_lut, gamma_length))
1227 if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1228 drm_color_lut_check(gamma_lut, gamma_tests))
1234 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1236 if (!crtc_state->gamma_enable ||
1237 crtc_state_is_legacy_gamma(crtc_state))
1238 return GAMMA_MODE_MODE_8BIT;
1240 return GAMMA_MODE_MODE_10BIT; /* i965+ only */
1243 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1247 ret = check_luts(crtc_state);
1251 crtc_state->gamma_enable =
1252 crtc_state->hw.gamma_lut &&
1253 !crtc_state->c8_planes;
1255 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1257 ret = intel_color_add_affected_planes(crtc_state);
1261 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1266 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1270 if (crtc_state_is_legacy_gamma(crtc_state))
1273 if (crtc_state->hw.degamma_lut)
1274 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1275 if (crtc_state->hw.ctm)
1276 cgm_mode |= CGM_PIPE_MODE_CSC;
1277 if (crtc_state->hw.gamma_lut)
1278 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1284 * CHV color pipeline:
1285 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
1286 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
1288 * We always bypass the WGC csc and use the CGM csc
1289 * instead since it has degamma and better precision.
1291 static int chv_color_check(struct intel_crtc_state *crtc_state)
1295 ret = check_luts(crtc_state);
1300 * Pipe gamma will be used only for the legacy LUT.
1301 * Otherwise we bypass it and use the CGM gamma instead.
1303 crtc_state->gamma_enable =
1304 crtc_state_is_legacy_gamma(crtc_state) &&
1305 !crtc_state->c8_planes;
1307 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1309 crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1311 ret = intel_color_add_affected_planes(crtc_state);
1315 crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
1320 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1322 if (!crtc_state->gamma_enable ||
1323 crtc_state_is_legacy_gamma(crtc_state))
1324 return GAMMA_MODE_MODE_8BIT;
1326 return GAMMA_MODE_MODE_10BIT;
1329 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1332 * CSC comes after the LUT in RGB->YCbCr mode.
1333 * RGB->YCbCr needs the limited range offsets added to
1334 * the output. RGB limited range output is handled by
1335 * the hw automagically elsewhere.
1337 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1338 return CSC_BLACK_SCREEN_OFFSET;
1340 return CSC_MODE_YUV_TO_RGB |
1341 CSC_POSITION_BEFORE_GAMMA;
1344 static int ilk_color_check(struct intel_crtc_state *crtc_state)
1348 ret = check_luts(crtc_state);
1352 crtc_state->gamma_enable =
1353 crtc_state->hw.gamma_lut &&
1354 !crtc_state->c8_planes;
1357 * We don't expose the ctm on ilk/snb currently, also RGB
1358 * limited range output is handled by the hw automagically.
1360 crtc_state->csc_enable =
1361 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1363 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1365 crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1367 ret = intel_color_add_affected_planes(crtc_state);
1371 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1376 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1378 if (!crtc_state->gamma_enable ||
1379 crtc_state_is_legacy_gamma(crtc_state))
1380 return GAMMA_MODE_MODE_8BIT;
1381 else if (crtc_state->hw.gamma_lut &&
1382 crtc_state->hw.degamma_lut)
1383 return GAMMA_MODE_MODE_SPLIT;
1385 return GAMMA_MODE_MODE_10BIT;
1388 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1390 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1393 * CSC comes after the LUT in degamma, RGB->YCbCr,
1394 * and RGB full->limited range mode.
1396 if (crtc_state->hw.degamma_lut ||
1397 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1398 limited_color_range)
1401 return CSC_POSITION_BEFORE_GAMMA;
1404 static int ivb_color_check(struct intel_crtc_state *crtc_state)
1406 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1409 ret = check_luts(crtc_state);
1413 crtc_state->gamma_enable =
1414 (crtc_state->hw.gamma_lut ||
1415 crtc_state->hw.degamma_lut) &&
1416 !crtc_state->c8_planes;
1418 crtc_state->csc_enable =
1419 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1420 crtc_state->hw.ctm || limited_color_range;
1422 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1424 crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1426 ret = intel_color_add_affected_planes(crtc_state);
1430 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1435 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1437 if (!crtc_state->gamma_enable ||
1438 crtc_state_is_legacy_gamma(crtc_state))
1439 return GAMMA_MODE_MODE_8BIT;
1441 return GAMMA_MODE_MODE_10BIT;
1444 static int glk_color_check(struct intel_crtc_state *crtc_state)
1448 ret = check_luts(crtc_state);
1452 crtc_state->gamma_enable =
1453 crtc_state->hw.gamma_lut &&
1454 !crtc_state->c8_planes;
1456 /* On GLK+ degamma LUT is controlled by csc_enable */
1457 crtc_state->csc_enable =
1458 crtc_state->hw.degamma_lut ||
1459 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1460 crtc_state->hw.ctm || crtc_state->limited_color_range;
1462 crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1464 crtc_state->csc_mode = 0;
1466 ret = intel_color_add_affected_planes(crtc_state);
1470 crtc_state->preload_luts = glk_can_preload_luts(crtc_state);
1475 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1479 if (crtc_state->hw.degamma_lut)
1480 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1482 if (crtc_state->hw.gamma_lut &&
1483 !crtc_state->c8_planes)
1484 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1486 if (!crtc_state->hw.gamma_lut ||
1487 crtc_state_is_legacy_gamma(crtc_state))
1488 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1490 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1495 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1499 if (crtc_state->hw.ctm)
1500 csc_mode |= ICL_CSC_ENABLE;
1502 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1503 crtc_state->limited_color_range)
1504 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1509 static int icl_color_check(struct intel_crtc_state *crtc_state)
1513 ret = check_luts(crtc_state);
1517 crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1519 crtc_state->csc_mode = icl_csc_mode(crtc_state);
1521 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1526 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1528 if (!crtc_state->gamma_enable)
1531 switch (crtc_state->gamma_mode) {
1532 case GAMMA_MODE_MODE_8BIT:
1534 case GAMMA_MODE_MODE_10BIT:
1537 MISSING_CASE(crtc_state->gamma_mode);
1542 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1544 if (!crtc_state->gamma_enable)
1547 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1550 switch (crtc_state->gamma_mode) {
1551 case GAMMA_MODE_MODE_8BIT:
1553 case GAMMA_MODE_MODE_10BIT:
1556 MISSING_CASE(crtc_state->gamma_mode);
1561 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1563 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1566 return i9xx_gamma_precision(crtc_state);
1569 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1571 if (!crtc_state->gamma_enable)
1574 switch (crtc_state->gamma_mode) {
1575 case GAMMA_MODE_MODE_8BIT:
1577 case GAMMA_MODE_MODE_10BIT:
1580 MISSING_CASE(crtc_state->gamma_mode);
1585 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1587 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1588 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1590 if (HAS_GMCH(dev_priv)) {
1591 if (IS_CHERRYVIEW(dev_priv))
1592 return chv_gamma_precision(crtc_state);
1594 return i9xx_gamma_precision(crtc_state);
1596 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1597 return glk_gamma_precision(crtc_state);
1598 else if (IS_IRONLAKE(dev_priv))
1599 return ilk_gamma_precision(crtc_state);
1605 static bool err_check(struct drm_color_lut *lut1,
1606 struct drm_color_lut *lut2, u32 err)
1608 return ((abs((long)lut2->red - lut1->red)) <= err) &&
1609 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1610 ((abs((long)lut2->green - lut1->green)) <= err);
1613 static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
1614 struct drm_color_lut *lut2,
1615 int lut_size, u32 err)
1619 for (i = 0; i < lut_size; i++) {
1620 if (!err_check(&lut1[i], &lut2[i], err))
1627 bool intel_color_lut_equal(struct drm_property_blob *blob1,
1628 struct drm_property_blob *blob2,
1629 u32 gamma_mode, u32 bit_precision)
1631 struct drm_color_lut *lut1, *lut2;
1632 int lut_size1, lut_size2;
1635 if (!blob1 != !blob2)
1641 lut_size1 = drm_color_lut_size(blob1);
1642 lut_size2 = drm_color_lut_size(blob2);
1644 /* check sw and hw lut size */
1645 switch (gamma_mode) {
1646 case GAMMA_MODE_MODE_8BIT:
1647 case GAMMA_MODE_MODE_10BIT:
1648 if (lut_size1 != lut_size2)
1652 MISSING_CASE(gamma_mode);
1659 err = 0xffff >> bit_precision;
1661 /* check sw and hw lut entry to be equal */
1662 switch (gamma_mode) {
1663 case GAMMA_MODE_MODE_8BIT:
1664 case GAMMA_MODE_MODE_10BIT:
1665 if (!intel_color_lut_entry_equal(lut1, lut2,
1670 MISSING_CASE(gamma_mode);
1677 /* convert hw value with given bit_precision to lut property val */
1678 static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
1680 u32 max = 0xffff >> (16 - bit_precision);
1682 val = clamp_val(val, 0, max);
1684 if (bit_precision < 16)
1685 val <<= 16 - bit_precision;
1690 static struct drm_property_blob *
1691 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
1693 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1694 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1695 enum pipe pipe = crtc->pipe;
1696 struct drm_property_blob *blob;
1697 struct drm_color_lut *blob_data;
1700 blob = drm_property_create_blob(&dev_priv->drm,
1701 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1706 blob_data = blob->data;
1708 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1709 if (HAS_GMCH(dev_priv))
1710 val = intel_de_read(dev_priv, PALETTE(pipe, i));
1712 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
1714 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1715 LGC_PALETTE_RED_MASK, val), 8);
1716 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1717 LGC_PALETTE_GREEN_MASK, val), 8);
1718 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1719 LGC_PALETTE_BLUE_MASK, val), 8);
1725 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1727 if (!crtc_state->gamma_enable)
1730 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
1733 static struct drm_property_blob *
1734 i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
1736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1737 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1738 u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1739 enum pipe pipe = crtc->pipe;
1740 struct drm_property_blob *blob;
1741 struct drm_color_lut *blob_data;
1744 blob = drm_property_create_blob(&dev_priv->drm,
1745 sizeof(struct drm_color_lut) * lut_size,
1750 blob_data = blob->data;
1752 for (i = 0; i < lut_size - 1; i++) {
1753 val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
1754 val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
1756 blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
1757 REG_FIELD_GET(PALETTE_RED_MASK, val1);
1758 blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
1759 REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
1760 blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
1761 REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
1764 blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1765 intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
1766 blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1767 intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
1768 blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1769 intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
1774 static void i965_read_luts(struct intel_crtc_state *crtc_state)
1776 if (!crtc_state->gamma_enable)
1779 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1780 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
1782 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
1785 static struct drm_property_blob *
1786 chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
1788 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1790 u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1791 enum pipe pipe = crtc->pipe;
1792 struct drm_property_blob *blob;
1793 struct drm_color_lut *blob_data;
1796 blob = drm_property_create_blob(&dev_priv->drm,
1797 sizeof(struct drm_color_lut) * lut_size,
1802 blob_data = blob->data;
1804 for (i = 0; i < lut_size; i++) {
1805 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
1806 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1807 CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
1808 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1809 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
1811 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
1812 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1813 CGM_PIPE_GAMMA_RED_MASK, val), 10);
1819 static void chv_read_luts(struct intel_crtc_state *crtc_state)
1821 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1822 crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
1824 i965_read_luts(crtc_state);
1827 static struct drm_property_blob *
1828 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
1830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1832 u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1833 enum pipe pipe = crtc->pipe;
1834 struct drm_property_blob *blob;
1835 struct drm_color_lut *blob_data;
1838 blob = drm_property_create_blob(&dev_priv->drm,
1839 sizeof(struct drm_color_lut) * lut_size,
1844 blob_data = blob->data;
1846 for (i = 0; i < lut_size; i++) {
1847 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
1849 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1850 PREC_PALETTE_RED_MASK, val), 10);
1851 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1852 PREC_PALETTE_GREEN_MASK, val), 10);
1853 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1854 PREC_PALETTE_BLUE_MASK, val), 10);
1860 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1862 if (!crtc_state->gamma_enable)
1865 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1868 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1869 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
1871 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
1874 static struct drm_property_blob *
1875 glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
1877 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1879 int hw_lut_size = ivb_lut_10_size(prec_index);
1880 enum pipe pipe = crtc->pipe;
1881 struct drm_property_blob *blob;
1882 struct drm_color_lut *blob_data;
1885 blob = drm_property_create_blob(&dev_priv->drm,
1886 sizeof(struct drm_color_lut) * hw_lut_size,
1891 blob_data = blob->data;
1893 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
1894 prec_index | PAL_PREC_AUTO_INCREMENT);
1896 for (i = 0; i < hw_lut_size; i++) {
1897 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
1899 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1900 PREC_PAL_DATA_RED_MASK, val), 10);
1901 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1902 PREC_PAL_DATA_GREEN_MASK, val), 10);
1903 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1904 PREC_PAL_DATA_BLUE_MASK, val), 10);
1907 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
1912 static void glk_read_luts(struct intel_crtc_state *crtc_state)
1914 if (!crtc_state->gamma_enable)
1917 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1918 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
1920 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
1923 void intel_color_init(struct intel_crtc *crtc)
1925 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1926 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
1928 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
1930 if (HAS_GMCH(dev_priv)) {
1931 if (IS_CHERRYVIEW(dev_priv)) {
1932 dev_priv->display.color_check = chv_color_check;
1933 dev_priv->display.color_commit = i9xx_color_commit;
1934 dev_priv->display.load_luts = chv_load_luts;
1935 dev_priv->display.read_luts = chv_read_luts;
1936 } else if (INTEL_GEN(dev_priv) >= 4) {
1937 dev_priv->display.color_check = i9xx_color_check;
1938 dev_priv->display.color_commit = i9xx_color_commit;
1939 dev_priv->display.load_luts = i965_load_luts;
1940 dev_priv->display.read_luts = i965_read_luts;
1942 dev_priv->display.color_check = i9xx_color_check;
1943 dev_priv->display.color_commit = i9xx_color_commit;
1944 dev_priv->display.load_luts = i9xx_load_luts;
1945 dev_priv->display.read_luts = i9xx_read_luts;
1948 if (INTEL_GEN(dev_priv) >= 11)
1949 dev_priv->display.color_check = icl_color_check;
1950 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1951 dev_priv->display.color_check = glk_color_check;
1952 else if (INTEL_GEN(dev_priv) >= 7)
1953 dev_priv->display.color_check = ivb_color_check;
1955 dev_priv->display.color_check = ilk_color_check;
1957 if (INTEL_GEN(dev_priv) >= 9)
1958 dev_priv->display.color_commit = skl_color_commit;
1959 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1960 dev_priv->display.color_commit = hsw_color_commit;
1962 dev_priv->display.color_commit = ilk_color_commit;
1964 if (INTEL_GEN(dev_priv) >= 11) {
1965 dev_priv->display.load_luts = icl_load_luts;
1966 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1967 dev_priv->display.load_luts = glk_load_luts;
1968 dev_priv->display.read_luts = glk_read_luts;
1969 } else if (INTEL_GEN(dev_priv) >= 8) {
1970 dev_priv->display.load_luts = bdw_load_luts;
1971 } else if (INTEL_GEN(dev_priv) >= 7) {
1972 dev_priv->display.load_luts = ivb_load_luts;
1974 dev_priv->display.load_luts = ilk_load_luts;
1975 dev_priv->display.read_luts = ilk_read_luts;
1979 drm_crtc_enable_color_mgmt(&crtc->base,
1980 INTEL_INFO(dev_priv)->color.degamma_lut_size,
1982 INTEL_INFO(dev_priv)->color.gamma_lut_size);