2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 #include "intel_color.h"
26 #include "intel_display_types.h"
28 #define CTM_COEFF_SIGN (1ULL << 63)
30 #define CTM_COEFF_1_0 (1ULL << 32)
31 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
32 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
33 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
34 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
35 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
36 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
38 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
40 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
41 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
43 #define LEGACY_LUT_LENGTH 256
48 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0|
49 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
50 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2|
52 * ILK/SNB don't have explicit post offsets, and instead
53 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
54 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
55 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
56 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
57 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
61 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
62 * format). This macro takes the coefficient we want transformed and the
63 * number of fractional bits.
65 * We only have a 9 bits precision window which slides depending on the value
66 * of the CTM coefficient and we write the value from bit 3. We also round the
69 #define ILK_CSC_COEFF_FP(coeff, fbits) \
70 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
72 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
73 #define ILK_CSC_COEFF_1_0 0x7800
75 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
77 /* Nop pre/post offsets */
78 static const u16 ilk_csc_off_zero[3] = {};
81 static const u16 ilk_csc_coeff_identity[9] = {
82 ILK_CSC_COEFF_1_0, 0, 0,
83 0, ILK_CSC_COEFF_1_0, 0,
84 0, 0, ILK_CSC_COEFF_1_0,
87 /* Limited range RGB post offsets */
88 static const u16 ilk_csc_postoff_limited_range[3] = {
89 ILK_CSC_POSTOFF_LIMITED_RANGE,
90 ILK_CSC_POSTOFF_LIMITED_RANGE,
91 ILK_CSC_POSTOFF_LIMITED_RANGE,
94 /* Full range RGB -> limited range RGB matrix */
95 static const u16 ilk_csc_coeff_limited_range[9] = {
96 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
97 0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
98 0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
101 /* BT.709 full range RGB -> limited range YCbCr matrix */
102 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
103 0x1e08, 0x9cc0, 0xb528,
104 0x2ba8, 0x09d8, 0x37e8,
105 0xbce8, 0x9ad8, 0x1e08,
108 /* Limited range YCbCr post offsets */
109 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
110 0x0800, 0x0100, 0x0800,
113 static bool lut_is_legacy(const struct drm_property_blob *lut)
115 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
120 return !crtc_state->hw.degamma_lut &&
121 !crtc_state->hw.ctm &&
122 crtc_state->hw.gamma_lut &&
123 lut_is_legacy(crtc_state->hw.gamma_lut);
127 * When using limited range, multiply the matrix given by userspace by
128 * the matrix that we would use for the limited range.
130 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
134 for (i = 0; i < 9; i++) {
135 u64 user_coeff = input[i];
136 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
137 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
138 CTM_COEFF_4_0 - 1) >> 2;
141 * By scaling every co-efficient with limited range (16-235)
142 * vs full range (0-255) the final o/p will be scaled down to
143 * fit in the limited range supported by the panel.
145 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
146 result[i] |= user_coeff & CTM_COEFF_SIGN;
152 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
155 const u16 postoff[3])
157 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
158 enum pipe pipe = crtc->pipe;
160 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
161 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
162 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
164 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
165 coeff[0] << 16 | coeff[1]);
166 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
168 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
169 coeff[3] << 16 | coeff[4]);
170 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
172 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
173 coeff[6] << 16 | coeff[7]);
174 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
176 if (INTEL_GEN(dev_priv) >= 7) {
177 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
179 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
181 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
186 static void icl_update_output_csc(struct intel_crtc *crtc,
189 const u16 postoff[3])
191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
192 enum pipe pipe = crtc->pipe;
194 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
195 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
196 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
198 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
199 coeff[0] << 16 | coeff[1]);
200 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
203 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
204 coeff[3] << 16 | coeff[4]);
205 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
208 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
209 coeff[6] << 16 | coeff[7]);
210 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
213 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
214 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
215 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
218 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
220 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
223 * FIXME if there's a gamma LUT after the CSC, we should
224 * do the range compression using the gamma LUT instead.
226 return crtc_state->limited_color_range &&
227 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
228 IS_GEN_RANGE(dev_priv, 9, 10));
231 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
234 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
239 if (ilk_csc_limited_range(crtc_state))
240 input = ctm_mult_by_limited(temp, ctm->matrix);
245 * Convert fixed point S31.32 input to format supported by the
248 for (i = 0; i < 9; i++) {
249 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
252 * Clamp input value to min/max supported by
255 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
260 if (CTM_COEFF_NEGATIVE(input[i]))
261 coeffs[i] |= 1 << 15;
263 if (abs_coeff < CTM_COEFF_0_125)
264 coeffs[i] |= (3 << 12) |
265 ILK_CSC_COEFF_FP(abs_coeff, 12);
266 else if (abs_coeff < CTM_COEFF_0_25)
267 coeffs[i] |= (2 << 12) |
268 ILK_CSC_COEFF_FP(abs_coeff, 11);
269 else if (abs_coeff < CTM_COEFF_0_5)
270 coeffs[i] |= (1 << 12) |
271 ILK_CSC_COEFF_FP(abs_coeff, 10);
272 else if (abs_coeff < CTM_COEFF_1_0)
273 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
274 else if (abs_coeff < CTM_COEFF_2_0)
275 coeffs[i] |= (7 << 12) |
276 ILK_CSC_COEFF_FP(abs_coeff, 8);
278 coeffs[i] |= (6 << 12) |
279 ILK_CSC_COEFF_FP(abs_coeff, 7);
283 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
287 bool limited_color_range = ilk_csc_limited_range(crtc_state);
289 if (crtc_state->hw.ctm) {
292 ilk_csc_convert_ctm(crtc_state, coeff);
293 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
294 limited_color_range ?
295 ilk_csc_postoff_limited_range :
297 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
298 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
299 ilk_csc_coeff_rgb_to_ycbcr,
300 ilk_csc_postoff_rgb_to_ycbcr);
301 } else if (limited_color_range) {
302 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
303 ilk_csc_coeff_limited_range,
304 ilk_csc_postoff_limited_range);
305 } else if (crtc_state->csc_enable) {
307 * On GLK+ both pipe CSC and degamma LUT are controlled
308 * by csc_enable. Hence for the cases where the degama
309 * LUT is needed but CSC is not we need to load an
312 drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
313 !IS_GEMINILAKE(dev_priv));
315 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
316 ilk_csc_coeff_identity,
320 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
321 crtc_state->csc_mode);
324 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
326 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
327 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
329 if (crtc_state->hw.ctm) {
332 ilk_csc_convert_ctm(crtc_state, coeff);
333 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
334 coeff, ilk_csc_off_zero);
337 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
338 icl_update_output_csc(crtc, ilk_csc_off_zero,
339 ilk_csc_coeff_rgb_to_ycbcr,
340 ilk_csc_postoff_rgb_to_ycbcr);
341 } else if (crtc_state->limited_color_range) {
342 icl_update_output_csc(crtc, ilk_csc_off_zero,
343 ilk_csc_coeff_limited_range,
344 ilk_csc_postoff_limited_range);
347 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
348 crtc_state->csc_mode);
351 static void chv_load_cgm_csc(struct intel_crtc *crtc,
352 const struct drm_property_blob *blob)
354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
355 const struct drm_color_ctm *ctm = blob->data;
356 enum pipe pipe = crtc->pipe;
360 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
361 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
363 /* Round coefficient. */
364 abs_coeff += 1 << (32 - 13);
365 /* Clamp to hardware limits. */
366 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
370 /* Write coefficients in S3.12 format. */
371 if (ctm->matrix[i] & (1ULL << 63))
372 coeffs[i] |= 1 << 15;
374 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
375 coeffs[i] |= (abs_coeff >> 20) & 0xfff;
378 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
379 coeffs[1] << 16 | coeffs[0]);
380 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
381 coeffs[3] << 16 | coeffs[2]);
382 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
383 coeffs[5] << 16 | coeffs[4]);
384 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
385 coeffs[7] << 16 | coeffs[6]);
386 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
390 /* convert hw value with given bit_precision to lut property val */
391 static u32 intel_color_lut_pack(u32 val, int bit_precision)
393 u32 max = 0xffff >> (16 - bit_precision);
395 val = clamp_val(val, 0, max);
397 if (bit_precision < 16)
398 val <<= 16 - bit_precision;
403 static u32 i9xx_lut_8(const struct drm_color_lut *color)
405 return drm_color_lut_extract(color->red, 8) << 16 |
406 drm_color_lut_extract(color->green, 8) << 8 |
407 drm_color_lut_extract(color->blue, 8);
410 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
412 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
413 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
414 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
417 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
418 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
420 return (color->red & 0xff) << 16 |
421 (color->green & 0xff) << 8 |
422 (color->blue & 0xff);
425 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
426 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
428 return (color->red >> 8) << 16 |
429 (color->green >> 8) << 8 |
433 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
435 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
436 REG_FIELD_GET(PALETTE_RED_MASK, ldw);
437 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
438 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
439 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
440 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
443 static u16 i965_lut_11p6_max_pack(u32 val)
445 /* PIPEGCMAX is 11.6, clamp to 10.6 */
446 return clamp_val(val, 0, 0xffff);
449 static u32 ilk_lut_10(const struct drm_color_lut *color)
451 return drm_color_lut_extract(color->red, 10) << 20 |
452 drm_color_lut_extract(color->green, 10) << 10 |
453 drm_color_lut_extract(color->blue, 10);
456 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
458 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
459 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
460 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
463 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
465 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
466 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
467 enum pipe pipe = crtc->pipe;
470 val = intel_de_read(dev_priv, PIPECONF(pipe));
471 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
472 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
473 intel_de_write(dev_priv, PIPECONF(pipe), val);
476 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
480 enum pipe pipe = crtc->pipe;
483 val = intel_de_read(dev_priv, PIPECONF(pipe));
484 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
485 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
486 intel_de_write(dev_priv, PIPECONF(pipe), val);
488 ilk_load_csc_matrix(crtc_state);
491 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
493 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
494 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
496 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
497 crtc_state->gamma_mode);
499 ilk_load_csc_matrix(crtc_state);
502 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
504 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
505 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
506 enum pipe pipe = crtc->pipe;
510 * We don't (yet) allow userspace to control the pipe background color,
511 * so force it to black, but apply pipe gamma and CSC appropriately
512 * so that its handling will match how we program our planes.
514 if (crtc_state->gamma_enable)
515 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
516 if (crtc_state->csc_enable)
517 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
518 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
520 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
521 crtc_state->gamma_mode);
523 if (INTEL_GEN(dev_priv) >= 11)
524 icl_load_csc_matrix(crtc_state);
526 ilk_load_csc_matrix(crtc_state);
529 static void i9xx_load_lut_8(struct intel_crtc *crtc,
530 const struct drm_property_blob *blob)
532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
533 const struct drm_color_lut *lut;
534 enum pipe pipe = crtc->pipe;
542 for (i = 0; i < 256; i++)
543 intel_de_write(dev_priv, PALETTE(pipe, i),
544 i9xx_lut_8(&lut[i]));
547 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
550 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
551 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
553 assert_pll_enabled(dev_priv, crtc->pipe);
555 i9xx_load_lut_8(crtc, gamma_lut);
558 static void i965_load_lut_10p6(struct intel_crtc *crtc,
559 const struct drm_property_blob *blob)
561 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
562 const struct drm_color_lut *lut = blob->data;
563 int i, lut_size = drm_color_lut_size(blob);
564 enum pipe pipe = crtc->pipe;
566 for (i = 0; i < lut_size - 1; i++) {
567 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0),
568 i965_lut_10p6_ldw(&lut[i]));
569 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1),
570 i965_lut_10p6_udw(&lut[i]));
573 intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red);
574 intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green);
575 intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue);
578 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
582 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
584 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
585 assert_dsi_pll_enabled(dev_priv);
587 assert_pll_enabled(dev_priv, crtc->pipe);
589 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
590 i9xx_load_lut_8(crtc, gamma_lut);
592 i965_load_lut_10p6(crtc, gamma_lut);
595 static void ilk_load_lut_8(struct intel_crtc *crtc,
596 const struct drm_property_blob *blob)
598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
599 const struct drm_color_lut *lut;
600 enum pipe pipe = crtc->pipe;
608 for (i = 0; i < 256; i++)
609 intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
610 i9xx_lut_8(&lut[i]));
613 static void ilk_load_lut_10(struct intel_crtc *crtc,
614 const struct drm_property_blob *blob)
616 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
617 const struct drm_color_lut *lut = blob->data;
618 int i, lut_size = drm_color_lut_size(blob);
619 enum pipe pipe = crtc->pipe;
621 for (i = 0; i < lut_size; i++)
622 intel_de_write(dev_priv, PREC_PALETTE(pipe, i),
623 ilk_lut_10(&lut[i]));
626 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
628 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
629 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
631 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
632 ilk_load_lut_8(crtc, gamma_lut);
634 ilk_load_lut_10(crtc, gamma_lut);
637 static int ivb_lut_10_size(u32 prec_index)
639 if (prec_index & PAL_PREC_SPLIT_MODE)
646 * IVB/HSW Bspec / PAL_PREC_INDEX:
647 * "Restriction : Index auto increment mode is not
648 * supported and must not be enabled."
650 static void ivb_load_lut_10(struct intel_crtc *crtc,
651 const struct drm_property_blob *blob,
654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
655 int hw_lut_size = ivb_lut_10_size(prec_index);
656 const struct drm_color_lut *lut = blob->data;
657 int i, lut_size = drm_color_lut_size(blob);
658 enum pipe pipe = crtc->pipe;
660 for (i = 0; i < hw_lut_size; i++) {
661 /* We discard half the user entries in split gamma mode */
662 const struct drm_color_lut *entry =
663 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
665 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
666 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
671 * Reset the index, otherwise it prevents the legacy palette to be
674 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
677 /* On BDW+ the index auto increment mode actually works */
678 static void bdw_load_lut_10(struct intel_crtc *crtc,
679 const struct drm_property_blob *blob,
682 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
683 int hw_lut_size = ivb_lut_10_size(prec_index);
684 const struct drm_color_lut *lut = blob->data;
685 int i, lut_size = drm_color_lut_size(blob);
686 enum pipe pipe = crtc->pipe;
688 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
689 prec_index | PAL_PREC_AUTO_INCREMENT);
691 for (i = 0; i < hw_lut_size; i++) {
692 /* We discard half the user entries in split gamma mode */
693 const struct drm_color_lut *entry =
694 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
696 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
701 * Reset the index, otherwise it prevents the legacy palette to be
704 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
707 static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
709 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
710 struct intel_dsb *dsb = intel_dsb_get(crtc);
711 enum pipe pipe = crtc->pipe;
713 /* Program the max register to clamp values > 1.0. */
714 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
715 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
716 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
719 * Program the gc max 2 register to clamp values > 1.0.
720 * ToDo: Extend the ABI to be able to program values
723 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
724 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
726 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
728 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
735 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
738 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
739 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
741 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
742 ilk_load_lut_8(crtc, gamma_lut);
743 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
744 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
745 PAL_PREC_INDEX_VALUE(0));
746 ivb_load_lut_ext_max(crtc);
747 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
748 PAL_PREC_INDEX_VALUE(512));
750 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
752 ivb_load_lut_10(crtc, blob,
753 PAL_PREC_INDEX_VALUE(0));
754 ivb_load_lut_ext_max(crtc);
758 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
760 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
761 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
762 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
764 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
765 ilk_load_lut_8(crtc, gamma_lut);
766 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
767 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
768 PAL_PREC_INDEX_VALUE(0));
769 ivb_load_lut_ext_max(crtc);
770 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
771 PAL_PREC_INDEX_VALUE(512));
773 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
775 bdw_load_lut_10(crtc, blob,
776 PAL_PREC_INDEX_VALUE(0));
777 ivb_load_lut_ext_max(crtc);
781 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
783 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
784 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
785 enum pipe pipe = crtc->pipe;
786 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
787 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
790 * When setting the auto-increment bit, the hardware seems to
791 * ignore the index bits, so we need to reset it to index 0
794 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
795 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
796 PRE_CSC_GAMC_AUTO_INCREMENT);
798 for (i = 0; i < lut_size; i++) {
800 * First 33 entries represent range from 0 to 1.0
801 * 34th and 35th entry will represent extended range
802 * inputs 3.0 and 7.0 respectively, currently clamped
803 * at 1.0. Since the precision is 16bit, the user
804 * value can be directly filled to register.
805 * The pipe degamma table in GLK+ onwards doesn't
806 * support different values per channel, so this just
807 * programs green value which will be equal to Red and
808 * Blue into the lut registers.
809 * ToDo: Extend to max 7.0. Enable 32 bit input value
810 * as compared to just 16 to achieve this.
812 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe),
816 /* Clamp values > 1.0. */
818 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
821 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
823 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
825 enum pipe pipe = crtc->pipe;
826 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
829 * When setting the auto-increment bit, the hardware seems to
830 * ignore the index bits, so we need to reset it to index 0
833 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
834 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
835 PRE_CSC_GAMC_AUTO_INCREMENT);
837 for (i = 0; i < lut_size; i++) {
838 u32 v = (i << 16) / (lut_size - 1);
840 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v);
843 /* Clamp values > 1.0. */
845 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
848 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
850 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
854 * On GLK+ both pipe CSC and degamma LUT are controlled
855 * by csc_enable. Hence for the cases where the CSC is
856 * needed but degamma LUT is not we need to load a
857 * linear degamma LUT. In fact we'll just always load
858 * the degama LUT so that we don't have to reload
859 * it every time the pipe CSC is being enabled.
861 if (crtc_state->hw.degamma_lut)
862 glk_load_degamma_lut(crtc_state);
864 glk_load_degamma_lut_linear(crtc_state);
866 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
867 ilk_load_lut_8(crtc, gamma_lut);
869 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
870 ivb_load_lut_ext_max(crtc);
874 /* ilk+ "12.4" interpolated format (high 10 bits) */
875 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
877 return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
881 /* ilk+ "12.4" interpolated format (low 6 bits) */
882 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
884 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
885 (color->blue & 0x3f) << 4;
889 icl_load_gcmax(const struct intel_crtc_state *crtc_state,
890 const struct drm_color_lut *color)
892 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
893 struct intel_dsb *dsb = intel_dsb_get(crtc);
894 enum pipe pipe = crtc->pipe;
896 /* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */
897 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
898 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
899 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
904 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
906 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
907 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
908 const struct drm_color_lut *lut = blob->data;
909 struct intel_dsb *dsb = intel_dsb_get(crtc);
910 enum pipe pipe = crtc->pipe;
914 * Program Super Fine segment (let's call it seg1)...
916 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
917 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
918 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
920 intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
921 PAL_PREC_AUTO_INCREMENT);
923 for (i = 0; i < 9; i++) {
924 const struct drm_color_lut *entry = &lut[i];
926 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
927 ilk_lut_12p4_ldw(entry));
928 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
929 ilk_lut_12p4_udw(entry));
936 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
938 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
939 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
940 const struct drm_color_lut *lut = blob->data;
941 const struct drm_color_lut *entry;
942 struct intel_dsb *dsb = intel_dsb_get(crtc);
943 enum pipe pipe = crtc->pipe;
947 * Program Fine segment (let's call it seg2)...
949 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
950 * ... 256/(128 * 256). So in order to program fine segment of LUT we
951 * need to pick every 8th entry in the LUT, and program 256 indexes.
953 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
954 * seg2[0] being unused by the hardware.
956 intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
957 for (i = 1; i < 257; i++) {
959 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
960 ilk_lut_12p4_ldw(entry));
961 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
962 ilk_lut_12p4_udw(entry));
966 * Program Coarse segment (let's call it seg3)...
968 * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
969 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
970 * above, we need to pick every (8 * 128)th entry in LUT, and
971 * program 256 of those.
973 * Spec is not very clear about if entries seg3[0] and seg3[1] are
974 * being used or not, but we still need to program these to advance
977 for (i = 0; i < 256; i++) {
978 entry = &lut[i * 8 * 128];
979 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
980 ilk_lut_12p4_ldw(entry));
981 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
982 ilk_lut_12p4_udw(entry));
985 /* The last entry in the LUT is to be programmed in GCMAX */
986 entry = &lut[256 * 8 * 128];
987 icl_load_gcmax(crtc_state, entry);
988 ivb_load_lut_ext_max(crtc);
992 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
994 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
996 struct intel_dsb *dsb = intel_dsb_get(crtc);
998 if (crtc_state->hw.degamma_lut)
999 glk_load_degamma_lut(crtc_state);
1001 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
1002 case GAMMA_MODE_MODE_8BIT:
1003 ilk_load_lut_8(crtc, gamma_lut);
1005 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1006 icl_program_gamma_superfine_segment(crtc_state);
1007 icl_program_gamma_multi_segment(crtc_state);
1010 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
1011 ivb_load_lut_ext_max(crtc);
1014 intel_dsb_commit(dsb);
1018 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
1020 return drm_color_lut_extract(color->green, 14) << 16 |
1021 drm_color_lut_extract(color->blue, 14);
1024 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
1026 return drm_color_lut_extract(color->red, 14);
1029 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
1031 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
1032 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
1033 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
1036 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
1037 const struct drm_property_blob *blob)
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040 const struct drm_color_lut *lut = blob->data;
1041 int i, lut_size = drm_color_lut_size(blob);
1042 enum pipe pipe = crtc->pipe;
1044 for (i = 0; i < lut_size; i++) {
1045 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
1046 chv_cgm_degamma_ldw(&lut[i]));
1047 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
1048 chv_cgm_degamma_udw(&lut[i]));
1052 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
1054 return drm_color_lut_extract(color->green, 10) << 16 |
1055 drm_color_lut_extract(color->blue, 10);
1058 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
1060 return drm_color_lut_extract(color->red, 10);
1063 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1064 const struct drm_property_blob *blob)
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 const struct drm_color_lut *lut = blob->data;
1068 int i, lut_size = drm_color_lut_size(blob);
1069 enum pipe pipe = crtc->pipe;
1071 for (i = 0; i < lut_size; i++) {
1072 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
1073 chv_cgm_gamma_ldw(&lut[i]));
1074 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
1075 chv_cgm_gamma_udw(&lut[i]));
1079 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1081 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1082 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1083 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1084 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1085 const struct drm_property_blob *ctm = crtc_state->hw.ctm;
1087 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
1088 chv_load_cgm_csc(crtc, ctm);
1090 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
1091 chv_load_cgm_degamma(crtc, degamma_lut);
1093 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1094 chv_load_cgm_gamma(crtc, gamma_lut);
1096 i965_load_luts(crtc_state);
1098 intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
1099 crtc_state->cgm_mode);
1102 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1104 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1106 dev_priv->display.load_luts(crtc_state);
1109 void intel_color_commit(const struct intel_crtc_state *crtc_state)
1111 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1113 dev_priv->display.color_commit(crtc_state);
1116 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1118 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1119 struct intel_atomic_state *state =
1120 to_intel_atomic_state(new_crtc_state->uapi.state);
1121 const struct intel_crtc_state *old_crtc_state =
1122 intel_atomic_get_old_crtc_state(state, crtc);
1124 return !old_crtc_state->hw.gamma_lut &&
1125 !old_crtc_state->hw.degamma_lut;
1128 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1130 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1131 struct intel_atomic_state *state =
1132 to_intel_atomic_state(new_crtc_state->uapi.state);
1133 const struct intel_crtc_state *old_crtc_state =
1134 intel_atomic_get_old_crtc_state(state, crtc);
1137 * CGM_PIPE_MODE is itself single buffered. We'd have to
1138 * somehow split it out from chv_load_luts() if we wanted
1139 * the ability to preload the CGM LUTs/CSC without tearing.
1141 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1144 return !old_crtc_state->hw.gamma_lut;
1147 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1149 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1150 struct intel_atomic_state *state =
1151 to_intel_atomic_state(new_crtc_state->uapi.state);
1152 const struct intel_crtc_state *old_crtc_state =
1153 intel_atomic_get_old_crtc_state(state, crtc);
1156 * The hardware degamma is active whenever the pipe
1157 * CSC is active. Thus even if the old state has no
1158 * software degamma we need to avoid clobbering the
1159 * linear hardware degamma mid scanout.
1161 return !old_crtc_state->csc_enable &&
1162 !old_crtc_state->hw.gamma_lut;
1165 int intel_color_check(struct intel_crtc_state *crtc_state)
1167 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1169 return dev_priv->display.color_check(crtc_state);
1172 void intel_color_get_config(struct intel_crtc_state *crtc_state)
1174 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1176 if (dev_priv->display.read_luts)
1177 dev_priv->display.read_luts(crtc_state);
1180 static bool need_plane_update(struct intel_plane *plane,
1181 const struct intel_crtc_state *crtc_state)
1183 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1186 * On pre-SKL the pipe gamma enable and pipe csc enable for
1187 * the pipe bottom color are configured via the primary plane.
1188 * We have to reconfigure that even if the plane is inactive.
1190 return crtc_state->active_planes & BIT(plane->id) ||
1191 (INTEL_GEN(dev_priv) < 9 &&
1192 plane->id == PLANE_PRIMARY);
1196 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1198 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1200 struct intel_atomic_state *state =
1201 to_intel_atomic_state(new_crtc_state->uapi.state);
1202 const struct intel_crtc_state *old_crtc_state =
1203 intel_atomic_get_old_crtc_state(state, crtc);
1204 struct intel_plane *plane;
1206 if (!new_crtc_state->hw.active ||
1207 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
1210 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1211 new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1214 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1215 struct intel_plane_state *plane_state;
1217 if (!need_plane_update(plane, new_crtc_state))
1220 plane_state = intel_atomic_get_plane_state(state, plane);
1221 if (IS_ERR(plane_state))
1222 return PTR_ERR(plane_state);
1224 new_crtc_state->update_planes |= BIT(plane->id);
1230 static int check_lut_size(const struct drm_property_blob *lut, int expected)
1237 len = drm_color_lut_size(lut);
1238 if (len != expected) {
1239 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1247 static int check_luts(const struct intel_crtc_state *crtc_state)
1249 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1250 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1251 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1252 int gamma_length, degamma_length;
1253 u32 gamma_tests, degamma_tests;
1255 /* Always allow legacy gamma LUT with no further checking. */
1256 if (crtc_state_is_legacy_gamma(crtc_state))
1259 /* C8 relies on its palette being stored in the legacy LUT */
1260 if (crtc_state->c8_planes) {
1261 drm_dbg_kms(&dev_priv->drm,
1262 "C8 pixelformat requires the legacy LUT\n");
1266 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1267 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1268 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1269 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1271 if (check_lut_size(degamma_lut, degamma_length) ||
1272 check_lut_size(gamma_lut, gamma_length))
1275 if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1276 drm_color_lut_check(gamma_lut, gamma_tests))
1282 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1284 if (!crtc_state->gamma_enable ||
1285 crtc_state_is_legacy_gamma(crtc_state))
1286 return GAMMA_MODE_MODE_8BIT;
1288 return GAMMA_MODE_MODE_10BIT; /* i965+ only */
1291 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1295 ret = check_luts(crtc_state);
1299 crtc_state->gamma_enable =
1300 crtc_state->hw.gamma_lut &&
1301 !crtc_state->c8_planes;
1303 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1305 ret = intel_color_add_affected_planes(crtc_state);
1309 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1314 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1318 if (crtc_state_is_legacy_gamma(crtc_state))
1321 if (crtc_state->hw.degamma_lut)
1322 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1323 if (crtc_state->hw.ctm)
1324 cgm_mode |= CGM_PIPE_MODE_CSC;
1325 if (crtc_state->hw.gamma_lut)
1326 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1332 * CHV color pipeline:
1333 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
1334 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
1336 * We always bypass the WGC csc and use the CGM csc
1337 * instead since it has degamma and better precision.
1339 static int chv_color_check(struct intel_crtc_state *crtc_state)
1343 ret = check_luts(crtc_state);
1348 * Pipe gamma will be used only for the legacy LUT.
1349 * Otherwise we bypass it and use the CGM gamma instead.
1351 crtc_state->gamma_enable =
1352 crtc_state_is_legacy_gamma(crtc_state) &&
1353 !crtc_state->c8_planes;
1355 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1357 crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1359 ret = intel_color_add_affected_planes(crtc_state);
1363 crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
1368 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1370 if (!crtc_state->gamma_enable ||
1371 crtc_state_is_legacy_gamma(crtc_state))
1372 return GAMMA_MODE_MODE_8BIT;
1374 return GAMMA_MODE_MODE_10BIT;
1377 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1380 * CSC comes after the LUT in RGB->YCbCr mode.
1381 * RGB->YCbCr needs the limited range offsets added to
1382 * the output. RGB limited range output is handled by
1383 * the hw automagically elsewhere.
1385 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1386 return CSC_BLACK_SCREEN_OFFSET;
1388 return CSC_MODE_YUV_TO_RGB |
1389 CSC_POSITION_BEFORE_GAMMA;
1392 static int ilk_color_check(struct intel_crtc_state *crtc_state)
1396 ret = check_luts(crtc_state);
1400 crtc_state->gamma_enable =
1401 crtc_state->hw.gamma_lut &&
1402 !crtc_state->c8_planes;
1405 * We don't expose the ctm on ilk/snb currently, also RGB
1406 * limited range output is handled by the hw automagically.
1408 crtc_state->csc_enable =
1409 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1411 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1413 crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1415 ret = intel_color_add_affected_planes(crtc_state);
1419 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1424 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1426 if (!crtc_state->gamma_enable ||
1427 crtc_state_is_legacy_gamma(crtc_state))
1428 return GAMMA_MODE_MODE_8BIT;
1429 else if (crtc_state->hw.gamma_lut &&
1430 crtc_state->hw.degamma_lut)
1431 return GAMMA_MODE_MODE_SPLIT;
1433 return GAMMA_MODE_MODE_10BIT;
1436 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1438 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1441 * CSC comes after the LUT in degamma, RGB->YCbCr,
1442 * and RGB full->limited range mode.
1444 if (crtc_state->hw.degamma_lut ||
1445 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1446 limited_color_range)
1449 return CSC_POSITION_BEFORE_GAMMA;
1452 static int ivb_color_check(struct intel_crtc_state *crtc_state)
1454 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1457 ret = check_luts(crtc_state);
1461 crtc_state->gamma_enable =
1462 (crtc_state->hw.gamma_lut ||
1463 crtc_state->hw.degamma_lut) &&
1464 !crtc_state->c8_planes;
1466 crtc_state->csc_enable =
1467 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1468 crtc_state->hw.ctm || limited_color_range;
1470 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1472 crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1474 ret = intel_color_add_affected_planes(crtc_state);
1478 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1483 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1485 if (!crtc_state->gamma_enable ||
1486 crtc_state_is_legacy_gamma(crtc_state))
1487 return GAMMA_MODE_MODE_8BIT;
1489 return GAMMA_MODE_MODE_10BIT;
1492 static int glk_color_check(struct intel_crtc_state *crtc_state)
1496 ret = check_luts(crtc_state);
1500 crtc_state->gamma_enable =
1501 crtc_state->hw.gamma_lut &&
1502 !crtc_state->c8_planes;
1504 /* On GLK+ degamma LUT is controlled by csc_enable */
1505 crtc_state->csc_enable =
1506 crtc_state->hw.degamma_lut ||
1507 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1508 crtc_state->hw.ctm || crtc_state->limited_color_range;
1510 crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1512 crtc_state->csc_mode = 0;
1514 ret = intel_color_add_affected_planes(crtc_state);
1518 crtc_state->preload_luts = glk_can_preload_luts(crtc_state);
1523 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1527 if (crtc_state->hw.degamma_lut)
1528 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1530 if (crtc_state->hw.gamma_lut &&
1531 !crtc_state->c8_planes)
1532 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1534 if (!crtc_state->hw.gamma_lut ||
1535 crtc_state_is_legacy_gamma(crtc_state))
1536 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1538 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1543 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1547 if (crtc_state->hw.ctm)
1548 csc_mode |= ICL_CSC_ENABLE;
1550 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1551 crtc_state->limited_color_range)
1552 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1557 static int icl_color_check(struct intel_crtc_state *crtc_state)
1561 ret = check_luts(crtc_state);
1565 crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1567 crtc_state->csc_mode = icl_csc_mode(crtc_state);
1569 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1574 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1576 if (!crtc_state->gamma_enable)
1579 switch (crtc_state->gamma_mode) {
1580 case GAMMA_MODE_MODE_8BIT:
1582 case GAMMA_MODE_MODE_10BIT:
1585 MISSING_CASE(crtc_state->gamma_mode);
1590 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1592 if (!crtc_state->gamma_enable)
1595 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1598 switch (crtc_state->gamma_mode) {
1599 case GAMMA_MODE_MODE_8BIT:
1601 case GAMMA_MODE_MODE_10BIT:
1604 MISSING_CASE(crtc_state->gamma_mode);
1609 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1611 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1614 return i9xx_gamma_precision(crtc_state);
1617 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1619 if (!crtc_state->gamma_enable)
1622 switch (crtc_state->gamma_mode) {
1623 case GAMMA_MODE_MODE_8BIT:
1625 case GAMMA_MODE_MODE_10BIT:
1628 MISSING_CASE(crtc_state->gamma_mode);
1633 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1638 if (HAS_GMCH(dev_priv)) {
1639 if (IS_CHERRYVIEW(dev_priv))
1640 return chv_gamma_precision(crtc_state);
1642 return i9xx_gamma_precision(crtc_state);
1644 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1645 return glk_gamma_precision(crtc_state);
1646 else if (IS_IRONLAKE(dev_priv))
1647 return ilk_gamma_precision(crtc_state);
1653 static bool err_check(struct drm_color_lut *lut1,
1654 struct drm_color_lut *lut2, u32 err)
1656 return ((abs((long)lut2->red - lut1->red)) <= err) &&
1657 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1658 ((abs((long)lut2->green - lut1->green)) <= err);
1661 static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
1662 struct drm_color_lut *lut2,
1663 int lut_size, u32 err)
1667 for (i = 0; i < lut_size; i++) {
1668 if (!err_check(&lut1[i], &lut2[i], err))
1675 bool intel_color_lut_equal(struct drm_property_blob *blob1,
1676 struct drm_property_blob *blob2,
1677 u32 gamma_mode, u32 bit_precision)
1679 struct drm_color_lut *lut1, *lut2;
1680 int lut_size1, lut_size2;
1683 if (!blob1 != !blob2)
1689 lut_size1 = drm_color_lut_size(blob1);
1690 lut_size2 = drm_color_lut_size(blob2);
1692 /* check sw and hw lut size */
1693 switch (gamma_mode) {
1694 case GAMMA_MODE_MODE_8BIT:
1695 case GAMMA_MODE_MODE_10BIT:
1696 if (lut_size1 != lut_size2)
1700 MISSING_CASE(gamma_mode);
1707 err = 0xffff >> bit_precision;
1709 /* check sw and hw lut entry to be equal */
1710 switch (gamma_mode) {
1711 case GAMMA_MODE_MODE_8BIT:
1712 case GAMMA_MODE_MODE_10BIT:
1713 if (!intel_color_lut_entry_equal(lut1, lut2,
1718 MISSING_CASE(gamma_mode);
1725 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
1727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1728 enum pipe pipe = crtc->pipe;
1729 struct drm_property_blob *blob;
1730 struct drm_color_lut *lut;
1733 blob = drm_property_create_blob(&dev_priv->drm,
1734 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1741 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1742 u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
1744 i9xx_lut_8_pack(&lut[i], val);
1750 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1752 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1754 if (!crtc_state->gamma_enable)
1757 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1760 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
1762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1763 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1764 enum pipe pipe = crtc->pipe;
1765 struct drm_property_blob *blob;
1766 struct drm_color_lut *lut;
1768 blob = drm_property_create_blob(&dev_priv->drm,
1769 sizeof(struct drm_color_lut) * lut_size,
1776 for (i = 0; i < lut_size - 1; i++) {
1777 u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
1778 u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
1780 i965_lut_10p6_pack(&lut[i], ldw, udw);
1783 lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
1784 lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
1785 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
1790 static void i965_read_luts(struct intel_crtc_state *crtc_state)
1792 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1794 if (!crtc_state->gamma_enable)
1797 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1798 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1800 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
1803 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
1805 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1806 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1807 enum pipe pipe = crtc->pipe;
1808 struct drm_property_blob *blob;
1809 struct drm_color_lut *lut;
1811 blob = drm_property_create_blob(&dev_priv->drm,
1812 sizeof(struct drm_color_lut) * lut_size,
1819 for (i = 0; i < lut_size; i++) {
1820 u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
1821 u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
1823 chv_cgm_gamma_pack(&lut[i], ldw, udw);
1829 static void chv_read_luts(struct intel_crtc_state *crtc_state)
1831 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1833 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1834 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
1836 i965_read_luts(crtc_state);
1839 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
1841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1842 enum pipe pipe = crtc->pipe;
1843 struct drm_property_blob *blob;
1844 struct drm_color_lut *lut;
1847 blob = drm_property_create_blob(&dev_priv->drm,
1848 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1855 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1856 u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
1858 i9xx_lut_8_pack(&lut[i], val);
1864 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
1866 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1867 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1868 enum pipe pipe = crtc->pipe;
1869 struct drm_property_blob *blob;
1870 struct drm_color_lut *lut;
1872 blob = drm_property_create_blob(&dev_priv->drm,
1873 sizeof(struct drm_color_lut) * lut_size,
1880 for (i = 0; i < lut_size; i++) {
1881 u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
1883 ilk_lut_10_pack(&lut[i], val);
1889 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1891 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1893 if (!crtc_state->gamma_enable)
1896 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1899 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1900 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
1902 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
1905 static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
1908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1909 int i, hw_lut_size = ivb_lut_10_size(prec_index);
1910 enum pipe pipe = crtc->pipe;
1911 struct drm_property_blob *blob;
1912 struct drm_color_lut *lut;
1914 blob = drm_property_create_blob(&dev_priv->drm,
1915 sizeof(struct drm_color_lut) * hw_lut_size,
1922 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
1923 prec_index | PAL_PREC_AUTO_INCREMENT);
1925 for (i = 0; i < hw_lut_size; i++) {
1926 u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
1928 ilk_lut_10_pack(&lut[i], val);
1931 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
1936 static void glk_read_luts(struct intel_crtc_state *crtc_state)
1938 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1940 if (!crtc_state->gamma_enable)
1943 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1944 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
1946 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
1949 void intel_color_init(struct intel_crtc *crtc)
1951 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1952 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
1954 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
1956 if (HAS_GMCH(dev_priv)) {
1957 if (IS_CHERRYVIEW(dev_priv)) {
1958 dev_priv->display.color_check = chv_color_check;
1959 dev_priv->display.color_commit = i9xx_color_commit;
1960 dev_priv->display.load_luts = chv_load_luts;
1961 dev_priv->display.read_luts = chv_read_luts;
1962 } else if (INTEL_GEN(dev_priv) >= 4) {
1963 dev_priv->display.color_check = i9xx_color_check;
1964 dev_priv->display.color_commit = i9xx_color_commit;
1965 dev_priv->display.load_luts = i965_load_luts;
1966 dev_priv->display.read_luts = i965_read_luts;
1968 dev_priv->display.color_check = i9xx_color_check;
1969 dev_priv->display.color_commit = i9xx_color_commit;
1970 dev_priv->display.load_luts = i9xx_load_luts;
1971 dev_priv->display.read_luts = i9xx_read_luts;
1974 if (INTEL_GEN(dev_priv) >= 11)
1975 dev_priv->display.color_check = icl_color_check;
1976 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1977 dev_priv->display.color_check = glk_color_check;
1978 else if (INTEL_GEN(dev_priv) >= 7)
1979 dev_priv->display.color_check = ivb_color_check;
1981 dev_priv->display.color_check = ilk_color_check;
1983 if (INTEL_GEN(dev_priv) >= 9)
1984 dev_priv->display.color_commit = skl_color_commit;
1985 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1986 dev_priv->display.color_commit = hsw_color_commit;
1988 dev_priv->display.color_commit = ilk_color_commit;
1990 if (INTEL_GEN(dev_priv) >= 11) {
1991 dev_priv->display.load_luts = icl_load_luts;
1992 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1993 dev_priv->display.load_luts = glk_load_luts;
1994 dev_priv->display.read_luts = glk_read_luts;
1995 } else if (INTEL_GEN(dev_priv) >= 8) {
1996 dev_priv->display.load_luts = bdw_load_luts;
1997 } else if (INTEL_GEN(dev_priv) >= 7) {
1998 dev_priv->display.load_luts = ivb_load_luts;
2000 dev_priv->display.load_luts = ilk_load_luts;
2001 dev_priv->display.read_luts = ilk_read_luts;
2005 drm_crtc_enable_color_mgmt(&crtc->base,
2006 INTEL_INFO(dev_priv)->color.degamma_lut_size,
2008 INTEL_INFO(dev_priv)->color.gamma_lut_size);