drivers/gpu/drm/i915/display/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_color.h"
  26 #include "intel_display_types.h"
  27
  28 #define CTM_COEFF_SIGN  (1ULL << 63)
  29
  30 #define CTM_COEFF_1_0   (1ULL << 32)
  31 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  32 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  33 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  34 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  35 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  36 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  37
  38 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  39
  40 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  41 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  42
  43 #define LEGACY_LUT_LENGTH               256
  44
  45 /*
  46  * ILK+ csc matrix:
  47  *
  48  * |R/Cr|   | c0 c1 c2 |   ( |R/Cr|   |preoff0| )   |postoff0|
  49  * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
  50  * |B/Cb|   | c6 c7 c8 |   ( |B/Cb|   |preoff2| )   |postoff2|
  51  *
  52  * ILK/SNB don't have explicit post offsets, and instead
  53  * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
  54  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
  55  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
  56  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
  57  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
  58  */
  59
  60 /*
  61  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  62  * format). This macro takes the coefficient we want transformed and the
  63  * number of fractional bits.
  64  *
  65  * We only have a 9 bits precision window which slides depending on the value
  66  * of the CTM coefficient and we write the value from bit 3. We also round the
  67  * value.
  68  */
  69 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  70         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  71
  72 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
  73 #define ILK_CSC_COEFF_1_0 0x7800
  74
  75 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
  76
  77 /* Nop pre/post offsets */
  78 static const u16 ilk_csc_off_zero[3] = {};
  79
  80 /* Identity matrix */
  81 static const u16 ilk_csc_coeff_identity[9] = {
  82         ILK_CSC_COEFF_1_0, 0, 0,
  83         0, ILK_CSC_COEFF_1_0, 0,
  84         0, 0, ILK_CSC_COEFF_1_0,
  85 };
  86
  87 /* Limited range RGB post offsets */
  88 static const u16 ilk_csc_postoff_limited_range[3] = {
  89         ILK_CSC_POSTOFF_LIMITED_RANGE,
  90         ILK_CSC_POSTOFF_LIMITED_RANGE,
  91         ILK_CSC_POSTOFF_LIMITED_RANGE,
  92 };
  93
  94 /* Full range RGB -> limited range RGB matrix */
  95 static const u16 ilk_csc_coeff_limited_range[9] = {
  96         ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
  97         0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
  98         0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
  99 };
 100
 101 /* BT.709 full range RGB -> limited range YCbCr matrix */
 102 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
 103         0x1e08, 0x9cc0, 0xb528,
 104         0x2ba8, 0x09d8, 0x37e8,
 105         0xbce8, 0x9ad8, 0x1e08,
 106 };
 107
 108 /* Limited range YCbCr post offsets */
 109 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
 110         0x0800, 0x0100, 0x0800,
 111 };
 112
 113 static bool lut_is_legacy(const struct drm_property_blob *lut)
 114 {
 115         return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
 116 }
 117
 118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
 119 {
 120         return !crtc_state->hw.degamma_lut &&
 121                 !crtc_state->hw.ctm &&
 122                 crtc_state->hw.gamma_lut &&
 123                 lut_is_legacy(crtc_state->hw.gamma_lut);
 124 }
 125
 126 /*
 127  * When using limited range, multiply the matrix given by userspace by
 128  * the matrix that we would use for the limited range.
 129  */
 130 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 131 {
 132         int i;
 133
 134         for (i = 0; i < 9; i++) {
 135                 u64 user_coeff = input[i];
 136                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
 137                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
 138                                           CTM_COEFF_4_0 - 1) >> 2;
 139
 140                 /*
 141                  * By scaling every co-efficient with limited range (16-235)
 142                  * vs full range (0-255) the final o/p will be scaled down to
 143                  * fit in the limited range supported by the panel.
 144                  */
 145                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 146                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 147         }
 148
 149         return result;
 150 }
 151
 152 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
 153                                 const u16 preoff[3],
 154                                 const u16 coeff[9],
 155                                 const u16 postoff[3])
 156 {
 157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 158         enum pipe pipe = crtc->pipe;
 159
 160         intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
 161         intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
 162         intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
 163
 164         intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
 165                        coeff[0] << 16 | coeff[1]);
 166         intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
 167
 168         intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
 169                        coeff[3] << 16 | coeff[4]);
 170         intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
 171
 172         intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
 173                        coeff[6] << 16 | coeff[7]);
 174         intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
 175
 176         if (INTEL_GEN(dev_priv) >= 7) {
 177                 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
 178                                postoff[0]);
 179                 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
 180                                postoff[1]);
 181                 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
 182                                postoff[2]);
 183         }
 184 }
 185
 186 static void icl_update_output_csc(struct intel_crtc *crtc,
 187                                   const u16 preoff[3],
 188                                   const u16 coeff[9],
 189                                   const u16 postoff[3])
 190 {
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192         enum pipe pipe = crtc->pipe;
 193
 194         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
 195         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
 196         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
 197
 198         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
 199                        coeff[0] << 16 | coeff[1]);
 200         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
 201                        coeff[2] << 16);
 202
 203         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
 204                        coeff[3] << 16 | coeff[4]);
 205         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
 206                        coeff[5] << 16);
 207
 208         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
 209                        coeff[6] << 16 | coeff[7]);
 210         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
 211                        coeff[8] << 16);
 212
 213         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
 214         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
 215         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
 216 }
 217
 218 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 219 {
 220         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 221
 222         /*
 223          * FIXME if there's a gamma LUT after the CSC, we should
 224          * do the range compression using the gamma LUT instead.
 225          */
 226         return crtc_state->limited_color_range &&
 227                 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
 228                  IS_GEN_RANGE(dev_priv, 9, 10));
 229 }
 230
 231 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 232                                 u16 coeffs[9])
 233 {
 234         const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
 235         const u64 *input;
 236         u64 temp[9];
 237         int i;
 238
 239         if (ilk_csc_limited_range(crtc_state))
 240                 input = ctm_mult_by_limited(temp, ctm->matrix);
 241         else
 242                 input = ctm->matrix;
 243
 244         /*
 245          * Convert fixed point S31.32 input to format supported by the
 246          * hardware.
 247          */
 248         for (i = 0; i < 9; i++) {
 249                 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
 250
 251                 /*
 252                  * Clamp input value to min/max supported by
 253                  * hardware.
 254                  */
 255                 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 256
 257                 coeffs[i] = 0;
 258
 259                 /* sign bit */
 260                 if (CTM_COEFF_NEGATIVE(input[i]))
 261                         coeffs[i] |= 1 << 15;
 262
 263                 if (abs_coeff < CTM_COEFF_0_125)
 264                         coeffs[i] |= (3 << 12) |
 265                                 ILK_CSC_COEFF_FP(abs_coeff, 12);
 266                 else if (abs_coeff < CTM_COEFF_0_25)
 267                         coeffs[i] |= (2 << 12) |
 268                                 ILK_CSC_COEFF_FP(abs_coeff, 11);
 269                 else if (abs_coeff < CTM_COEFF_0_5)
 270                         coeffs[i] |= (1 << 12) |
 271                                 ILK_CSC_COEFF_FP(abs_coeff, 10);
 272                 else if (abs_coeff < CTM_COEFF_1_0)
 273                         coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 274                 else if (abs_coeff < CTM_COEFF_2_0)
 275                         coeffs[i] |= (7 << 12) |
 276                                 ILK_CSC_COEFF_FP(abs_coeff, 8);
 277                 else
 278                         coeffs[i] |= (6 << 12) |
 279                                 ILK_CSC_COEFF_FP(abs_coeff, 7);
 280         }
 281 }
 282
 283 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 284 {
 285         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 286         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 287         bool limited_color_range = ilk_csc_limited_range(crtc_state);
 288
 289         if (crtc_state->hw.ctm) {
 290                 u16 coeff[9];
 291
 292                 ilk_csc_convert_ctm(crtc_state, coeff);
 293                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
 294                                     limited_color_range ?
 295                                     ilk_csc_postoff_limited_range :
 296                                     ilk_csc_off_zero);
 297         } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 298                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 299                                     ilk_csc_coeff_rgb_to_ycbcr,
 300                                     ilk_csc_postoff_rgb_to_ycbcr);
 301         } else if (limited_color_range) {
 302                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 303                                     ilk_csc_coeff_limited_range,
 304                                     ilk_csc_postoff_limited_range);
 305         } else if (crtc_state->csc_enable) {
 306                 /*
 307                  * On GLK+ both pipe CSC and degamma LUT are controlled
 308                  * by csc_enable. Hence for the cases where the degama
 309                  * LUT is needed but CSC is not we need to load an
 310                  * identity matrix.
 311                  */
 312                 drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
 313                             !IS_GEMINILAKE(dev_priv));
 314
 315                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 316                                     ilk_csc_coeff_identity,
 317                                     ilk_csc_off_zero);
 318         }
 319
 320         intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
 321                        crtc_state->csc_mode);
 322 }
 323
 324 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 325 {
 326         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 327         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 328
 329         if (crtc_state->hw.ctm) {
 330                 u16 coeff[9];
 331
 332                 ilk_csc_convert_ctm(crtc_state, coeff);
 333                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 334                                     coeff, ilk_csc_off_zero);
 335         }
 336
 337         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 338                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 339                                       ilk_csc_coeff_rgb_to_ycbcr,
 340                                       ilk_csc_postoff_rgb_to_ycbcr);
 341         } else if (crtc_state->limited_color_range) {
 342                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 343                                       ilk_csc_coeff_limited_range,
 344                                       ilk_csc_postoff_limited_range);
 345         }
 346
 347         intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
 348                        crtc_state->csc_mode);
 349 }
 350
 351 static void chv_load_cgm_csc(struct intel_crtc *crtc,
 352                              const struct drm_property_blob *blob)
 353 {
 354         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 355         const struct drm_color_ctm *ctm = blob->data;
 356         enum pipe pipe = crtc->pipe;
 357         u16 coeffs[9];
 358         int i;
 359
 360         for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 361                 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
 362
 363                 /* Round coefficient. */
 364                 abs_coeff += 1 << (32 - 13);
 365                 /* Clamp to hardware limits. */
 366                 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 367
 368                 coeffs[i] = 0;
 369
 370                 /* Write coefficients in S3.12 format. */
 371                 if (ctm->matrix[i] & (1ULL << 63))
 372                         coeffs[i] |= 1 << 15;
 373
 374                 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 375                 coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 376         }
 377
 378         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
 379                        coeffs[1] << 16 | coeffs[0]);
 380         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
 381                        coeffs[3] << 16 | coeffs[2]);
 382         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
 383                        coeffs[5] << 16 | coeffs[4]);
 384         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
 385                        coeffs[7] << 16 | coeffs[6]);
 386         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
 387                        coeffs[8]);
 388 }
 389
 390 static u32 i9xx_lut_8(const struct drm_color_lut *color)
 391 {
 392         return drm_color_lut_extract(color->red, 8) << 16 |
 393                 drm_color_lut_extract(color->green, 8) << 8 |
 394                 drm_color_lut_extract(color->blue, 8);
 395 }
 396
 397 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 398 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 399 {
 400         return (color->red & 0xff) << 16 |
 401                 (color->green & 0xff) << 8 |
 402                 (color->blue & 0xff);
 403 }
 404
 405 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
 406 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
 407 {
 408         return (color->red >> 8) << 16 |
 409                 (color->green >> 8) << 8 |
 410                 (color->blue >> 8);
 411 }
 412
 413 static u32 ilk_lut_10(const struct drm_color_lut *color)
 414 {
 415         return drm_color_lut_extract(color->red, 10) << 20 |
 416                 drm_color_lut_extract(color->green, 10) << 10 |
 417                 drm_color_lut_extract(color->blue, 10);
 418 }
 419
 420 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 421 {
 422         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 424         enum pipe pipe = crtc->pipe;
 425         u32 val;
 426
 427         val = intel_de_read(dev_priv, PIPECONF(pipe));
 428         val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
 429         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 430         intel_de_write(dev_priv, PIPECONF(pipe), val);
 431 }
 432
 433 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
 434 {
 435         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 436         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 437         enum pipe pipe = crtc->pipe;
 438         u32 val;
 439
 440         val = intel_de_read(dev_priv, PIPECONF(pipe));
 441         val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
 442         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 443         intel_de_write(dev_priv, PIPECONF(pipe), val);
 444
 445         ilk_load_csc_matrix(crtc_state);
 446 }
 447
 448 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 449 {
 450         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 451         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 452
 453         intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
 454                        crtc_state->gamma_mode);
 455
 456         ilk_load_csc_matrix(crtc_state);
 457 }
 458
 459 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 460 {
 461         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 462         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 463         enum pipe pipe = crtc->pipe;
 464         u32 val = 0;
 465
 466         /*
 467          * We don't (yet) allow userspace to control the pipe background color,
 468          * so force it to black, but apply pipe gamma and CSC appropriately
 469          * so that its handling will match how we program our planes.
 470          */
 471         if (crtc_state->gamma_enable)
 472                 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
 473         if (crtc_state->csc_enable)
 474                 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
 475         intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
 476
 477         intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
 478                        crtc_state->gamma_mode);
 479
 480         if (INTEL_GEN(dev_priv) >= 11)
 481                 icl_load_csc_matrix(crtc_state);
 482         else
 483                 ilk_load_csc_matrix(crtc_state);
 484 }
 485
 486 static void i9xx_load_lut_8(struct intel_crtc *crtc,
 487                             const struct drm_property_blob *blob)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 490         const struct drm_color_lut *lut;
 491         enum pipe pipe = crtc->pipe;
 492         int i;
 493
 494         if (!blob)
 495                 return;
 496
 497         lut = blob->data;
 498
 499         for (i = 0; i < 256; i++)
 500                 intel_de_write(dev_priv, PALETTE(pipe, i),
 501                                i9xx_lut_8(&lut[i]));
 502 }
 503
 504 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 505 {
 506         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 507         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 508         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 509
 510         assert_pll_enabled(dev_priv, crtc->pipe);
 511
 512         i9xx_load_lut_8(crtc, gamma_lut);
 513 }
 514
 515 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 516                                const struct drm_property_blob *blob)
 517 {
 518         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 519         const struct drm_color_lut *lut = blob->data;
 520         int i, lut_size = drm_color_lut_size(blob);
 521         enum pipe pipe = crtc->pipe;
 522
 523         for (i = 0; i < lut_size - 1; i++) {
 524                 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0),
 525                                i965_lut_10p6_ldw(&lut[i]));
 526                 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1),
 527                                i965_lut_10p6_udw(&lut[i]));
 528         }
 529
 530         intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red);
 531         intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green);
 532         intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue);
 533 }
 534
 535 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 536 {
 537         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 538         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 539         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 540
 541         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 542                 assert_dsi_pll_enabled(dev_priv);
 543         else
 544                 assert_pll_enabled(dev_priv, crtc->pipe);
 545
 546         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 547                 i9xx_load_lut_8(crtc, gamma_lut);
 548         else
 549                 i965_load_lut_10p6(crtc, gamma_lut);
 550 }
 551
 552 static void ilk_load_lut_8(struct intel_crtc *crtc,
 553                            const struct drm_property_blob *blob)
 554 {
 555         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 556         const struct drm_color_lut *lut;
 557         enum pipe pipe = crtc->pipe;
 558         int i;
 559
 560         if (!blob)
 561                 return;
 562
 563         lut = blob->data;
 564
 565         for (i = 0; i < 256; i++)
 566                 intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
 567                                i9xx_lut_8(&lut[i]));
 568 }
 569
 570 static void ilk_load_lut_10(struct intel_crtc *crtc,
 571                             const struct drm_property_blob *blob)
 572 {
 573         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 574         const struct drm_color_lut *lut = blob->data;
 575         int i, lut_size = drm_color_lut_size(blob);
 576         enum pipe pipe = crtc->pipe;
 577
 578         for (i = 0; i < lut_size; i++)
 579                 intel_de_write(dev_priv, PREC_PALETTE(pipe, i),
 580                                ilk_lut_10(&lut[i]));
 581 }
 582
 583 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 584 {
 585         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 586         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 587
 588         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 589                 ilk_load_lut_8(crtc, gamma_lut);
 590         else
 591                 ilk_load_lut_10(crtc, gamma_lut);
 592 }
 593
 594 static int ivb_lut_10_size(u32 prec_index)
 595 {
 596         if (prec_index & PAL_PREC_SPLIT_MODE)
 597                 return 512;
 598         else
 599                 return 1024;
 600 }
 601
 602 /*
 603  * IVB/HSW Bspec / PAL_PREC_INDEX:
 604  * "Restriction : Index auto increment mode is not
 605  *  supported and must not be enabled."
 606  */
 607 static void ivb_load_lut_10(struct intel_crtc *crtc,
 608                             const struct drm_property_blob *blob,
 609                             u32 prec_index)
 610 {
 611         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 612         int hw_lut_size = ivb_lut_10_size(prec_index);
 613         const struct drm_color_lut *lut = blob->data;
 614         int i, lut_size = drm_color_lut_size(blob);
 615         enum pipe pipe = crtc->pipe;
 616
 617         for (i = 0; i < hw_lut_size; i++) {
 618                 /* We discard half the user entries in split gamma mode */
 619                 const struct drm_color_lut *entry =
 620                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 621
 622                 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
 623                 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
 624                                ilk_lut_10(entry));
 625         }
 626
 627         /*
 628          * Reset the index, otherwise it prevents the legacy palette to be
 629          * written properly.
 630          */
 631         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
 632 }
 633
 634 /* On BDW+ the index auto increment mode actually works */
 635 static void bdw_load_lut_10(struct intel_crtc *crtc,
 636                             const struct drm_property_blob *blob,
 637                             u32 prec_index)
 638 {
 639         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 640         int hw_lut_size = ivb_lut_10_size(prec_index);
 641         const struct drm_color_lut *lut = blob->data;
 642         int i, lut_size = drm_color_lut_size(blob);
 643         enum pipe pipe = crtc->pipe;
 644
 645         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
 646                        prec_index | PAL_PREC_AUTO_INCREMENT);
 647
 648         for (i = 0; i < hw_lut_size; i++) {
 649                 /* We discard half the user entries in split gamma mode */
 650                 const struct drm_color_lut *entry =
 651                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 652
 653                 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
 654                                ilk_lut_10(entry));
 655         }
 656
 657         /*
 658          * Reset the index, otherwise it prevents the legacy palette to be
 659          * written properly.
 660          */
 661         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
 662 }
 663
 664 static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
 665 {
 666         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 667         struct intel_dsb *dsb = intel_dsb_get(crtc);
 668         enum pipe pipe = crtc->pipe;
 669
 670         /* Program the max register to clamp values > 1.0. */
 671         intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
 672         intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
 673         intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
 674
 675         /*
 676          * Program the gc max 2 register to clamp values > 1.0.
 677          * ToDo: Extend the ABI to be able to program values
 678          * from 3.0 to 7.0
 679          */
 680         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 681                 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
 682                                     1 << 16);
 683                 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
 684                                     1 << 16);
 685                 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
 686                                     1 << 16);
 687         }
 688
 689         intel_dsb_put(dsb);
 690 }
 691
 692 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 693 {
 694         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 695         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 696         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 697
 698         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 699                 ilk_load_lut_8(crtc, gamma_lut);
 700         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 701                 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 702                                 PAL_PREC_INDEX_VALUE(0));
 703                 ivb_load_lut_ext_max(crtc);
 704                 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 705                                 PAL_PREC_INDEX_VALUE(512));
 706         } else {
 707                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 708
 709                 ivb_load_lut_10(crtc, blob,
 710                                 PAL_PREC_INDEX_VALUE(0));
 711                 ivb_load_lut_ext_max(crtc);
 712         }
 713 }
 714
 715 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 716 {
 717         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 718         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 719         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 720
 721         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 722                 ilk_load_lut_8(crtc, gamma_lut);
 723         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 724                 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 725                                 PAL_PREC_INDEX_VALUE(0));
 726                 ivb_load_lut_ext_max(crtc);
 727                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 728                                 PAL_PREC_INDEX_VALUE(512));
 729         } else {
 730                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 731
 732                 bdw_load_lut_10(crtc, blob,
 733                                 PAL_PREC_INDEX_VALUE(0));
 734                 ivb_load_lut_ext_max(crtc);
 735         }
 736 }
 737
 738 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 739 {
 740         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 741         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 742         enum pipe pipe = crtc->pipe;
 743         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 744         const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
 745         u32 i;
 746
 747         /*
 748          * When setting the auto-increment bit, the hardware seems to
 749          * ignore the index bits, so we need to reset it to index 0
 750          * separately.
 751          */
 752         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
 753         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
 754                        PRE_CSC_GAMC_AUTO_INCREMENT);
 755
 756         for (i = 0; i < lut_size; i++) {
 757                 /*
 758                  * First 33 entries represent range from 0 to 1.0
 759                  * 34th and 35th entry will represent extended range
 760                  * inputs 3.0 and 7.0 respectively, currently clamped
 761                  * at 1.0. Since the precision is 16bit, the user
 762                  * value can be directly filled to register.
 763                  * The pipe degamma table in GLK+ onwards doesn't
 764                  * support different values per channel, so this just
 765                  * programs green value which will be equal to Red and
 766                  * Blue into the lut registers.
 767                  * ToDo: Extend to max 7.0. Enable 32 bit input value
 768                  * as compared to just 16 to achieve this.
 769                  */
 770                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe),
 771                                lut[i].green);
 772         }
 773
 774         /* Clamp values > 1.0. */
 775         while (i++ < 35)
 776                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 777 }
 778
 779 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
 780 {
 781         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 782         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 783         enum pipe pipe = crtc->pipe;
 784         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 785         u32 i;
 786
 787         /*
 788          * When setting the auto-increment bit, the hardware seems to
 789          * ignore the index bits, so we need to reset it to index 0
 790          * separately.
 791          */
 792         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
 793         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
 794                        PRE_CSC_GAMC_AUTO_INCREMENT);
 795
 796         for (i = 0; i < lut_size; i++) {
 797                 u32 v = (i << 16) / (lut_size - 1);
 798
 799                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v);
 800         }
 801
 802         /* Clamp values > 1.0. */
 803         while (i++ < 35)
 804                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 805 }
 806
 807 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 808 {
 809         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 810         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 811
 812         /*
 813          * On GLK+ both pipe CSC and degamma LUT are controlled
 814          * by csc_enable. Hence for the cases where the CSC is
 815          * needed but degamma LUT is not we need to load a
 816          * linear degamma LUT. In fact we'll just always load
 817          * the degama LUT so that we don't have to reload
 818          * it every time the pipe CSC is being enabled.
 819          */
 820         if (crtc_state->hw.degamma_lut)
 821                 glk_load_degamma_lut(crtc_state);
 822         else
 823                 glk_load_degamma_lut_linear(crtc_state);
 824
 825         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 826                 ilk_load_lut_8(crtc, gamma_lut);
 827         } else {
 828                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 829                 ivb_load_lut_ext_max(crtc);
 830         }
 831 }
 832
 833 /* ilk+ "12.4" interpolated format (high 10 bits) */
 834 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
 835 {
 836         return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
 837                 (color->blue >> 6);
 838 }
 839
 840 /* ilk+ "12.4" interpolated format (low 6 bits) */
 841 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 842 {
 843         return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
 844                 (color->blue & 0x3f) << 4;
 845 }
 846
 847 static void
 848 icl_load_gcmax(const struct intel_crtc_state *crtc_state,
 849                const struct drm_color_lut *color)
 850 {
 851         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 852         struct intel_dsb *dsb = intel_dsb_get(crtc);
 853         enum pipe pipe = crtc->pipe;
 854
 855         /* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */
 856         intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
 857         intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
 858         intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
 859         intel_dsb_put(dsb);
 860 }
 861
 862 static void
 863 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 864 {
 865         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 866         const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 867         const struct drm_color_lut *lut = blob->data;
 868         struct intel_dsb *dsb = intel_dsb_get(crtc);
 869         enum pipe pipe = crtc->pipe;
 870         u32 i;
 871
 872         /*
 873          * Program Super Fine segment (let's call it seg1)...
 874          *
 875          * Super Fine segment's step is 1/(8 * 128 * 256) and it has
 876          * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
 877          * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
 878          */
 879         intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
 880                             PAL_PREC_AUTO_INCREMENT);
 881
 882         for (i = 0; i < 9; i++) {
 883                 const struct drm_color_lut *entry = &lut[i];
 884
 885                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
 886                                             ilk_lut_12p4_ldw(entry));
 887                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
 888                                             ilk_lut_12p4_udw(entry));
 889         }
 890
 891         intel_dsb_put(dsb);
 892 }
 893
 894 static void
 895 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 896 {
 897         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 898         const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 899         const struct drm_color_lut *lut = blob->data;
 900         const struct drm_color_lut *entry;
 901         struct intel_dsb *dsb = intel_dsb_get(crtc);
 902         enum pipe pipe = crtc->pipe;
 903         u32 i;
 904
 905         /*
 906          * Program Fine segment (let's call it seg2)...
 907          *
 908          * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
 909          * ... 256/(128 * 256). So in order to program fine segment of LUT we
 910          * need to pick every 8th entry in the LUT, and program 256 indexes.
 911          *
 912          * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
 913          * seg2[0] being unused by the hardware.
 914          */
 915         intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
 916         for (i = 1; i < 257; i++) {
 917                 entry = &lut[i * 8];
 918                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 919                                             ilk_lut_12p4_ldw(entry));
 920                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 921                                             ilk_lut_12p4_udw(entry));
 922         }
 923
 924         /*
 925          * Program Coarse segment (let's call it seg3)...
 926          *
 927          * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
 928          * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
 929          * above, we need to pick every (8 * 128)th entry in LUT, and
 930          * program 256 of those.
 931          *
 932          * Spec is not very clear about if entries seg3[0] and seg3[1] are
 933          * being used or not, but we still need to program these to advance
 934          * the index.
 935          */
 936         for (i = 0; i < 256; i++) {
 937                 entry = &lut[i * 8 * 128];
 938                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 939                                             ilk_lut_12p4_ldw(entry));
 940                 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
 941                                             ilk_lut_12p4_udw(entry));
 942         }
 943
 944         /* The last entry in the LUT is to be programmed in GCMAX */
 945         entry = &lut[256 * 8 * 128];
 946         icl_load_gcmax(crtc_state, entry);
 947         ivb_load_lut_ext_max(crtc);
 948         intel_dsb_put(dsb);
 949 }
 950
 951 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 952 {
 953         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 954         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 955         struct intel_dsb *dsb = intel_dsb_get(crtc);
 956
 957         if (crtc_state->hw.degamma_lut)
 958                 glk_load_degamma_lut(crtc_state);
 959
 960         switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
 961         case GAMMA_MODE_MODE_8BIT:
 962                 ilk_load_lut_8(crtc, gamma_lut);
 963                 break;
 964         case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 965                 icl_program_gamma_superfine_segment(crtc_state);
 966                 icl_program_gamma_multi_segment(crtc_state);
 967                 break;
 968         default:
 969                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 970                 ivb_load_lut_ext_max(crtc);
 971         }
 972
 973         intel_dsb_commit(dsb);
 974         intel_dsb_put(dsb);
 975 }
 976
 977 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
 978 {
 979         return drm_color_lut_extract(color->green, 14) << 16 |
 980                 drm_color_lut_extract(color->blue, 14);
 981 }
 982
 983 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 984 {
 985         return drm_color_lut_extract(color->red, 14);
 986 }
 987
 988 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 989                                  const struct drm_property_blob *blob)
 990 {
 991         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 992         const struct drm_color_lut *lut = blob->data;
 993         int i, lut_size = drm_color_lut_size(blob);
 994         enum pipe pipe = crtc->pipe;
 995
 996         for (i = 0; i < lut_size; i++) {
 997                 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
 998                                chv_cgm_degamma_ldw(&lut[i]));
 999                 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
1000                                chv_cgm_degamma_udw(&lut[i]));
1001         }
1002 }
1003
1004 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
1005 {
1006         return drm_color_lut_extract(color->green, 10) << 16 |
1007                 drm_color_lut_extract(color->blue, 10);
1008 }
1009
1010 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
1011 {
1012         return drm_color_lut_extract(color->red, 10);
1013 }
1014
1015 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1016                                const struct drm_property_blob *blob)
1017 {
1018         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1019         const struct drm_color_lut *lut = blob->data;
1020         int i, lut_size = drm_color_lut_size(blob);
1021         enum pipe pipe = crtc->pipe;
1022
1023         for (i = 0; i < lut_size; i++) {
1024                 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
1025                                chv_cgm_gamma_ldw(&lut[i]));
1026                 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
1027                                chv_cgm_gamma_udw(&lut[i]));
1028         }
1029 }
1030
1031 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1032 {
1033         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1034         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1035         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1036         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1037         const struct drm_property_blob *ctm = crtc_state->hw.ctm;
1038
1039         if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
1040                 chv_load_cgm_csc(crtc, ctm);
1041
1042         if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
1043                 chv_load_cgm_degamma(crtc, degamma_lut);
1044
1045         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1046                 chv_load_cgm_gamma(crtc, gamma_lut);
1047         else
1048                 i965_load_luts(crtc_state);
1049
1050         intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
1051                        crtc_state->cgm_mode);
1052 }
1053
1054 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1055 {
1056         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1057
1058         dev_priv->display.load_luts(crtc_state);
1059 }
1060
1061 void intel_color_commit(const struct intel_crtc_state *crtc_state)
1062 {
1063         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1064
1065         dev_priv->display.color_commit(crtc_state);
1066 }
1067
1068 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1069 {
1070         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1071         struct intel_atomic_state *state =
1072                 to_intel_atomic_state(new_crtc_state->uapi.state);
1073         const struct intel_crtc_state *old_crtc_state =
1074                 intel_atomic_get_old_crtc_state(state, crtc);
1075
1076         return !old_crtc_state->hw.gamma_lut &&
1077                 !old_crtc_state->hw.degamma_lut;
1078 }
1079
1080 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1081 {
1082         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1083         struct intel_atomic_state *state =
1084                 to_intel_atomic_state(new_crtc_state->uapi.state);
1085         const struct intel_crtc_state *old_crtc_state =
1086                 intel_atomic_get_old_crtc_state(state, crtc);
1087
1088         /*
1089          * CGM_PIPE_MODE is itself single buffered. We'd have to
1090          * somehow split it out from chv_load_luts() if we wanted
1091          * the ability to preload the CGM LUTs/CSC without tearing.
1092          */
1093         if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1094                 return false;
1095
1096         return !old_crtc_state->hw.gamma_lut;
1097 }
1098
1099 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1100 {
1101         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1102         struct intel_atomic_state *state =
1103                 to_intel_atomic_state(new_crtc_state->uapi.state);
1104         const struct intel_crtc_state *old_crtc_state =
1105                 intel_atomic_get_old_crtc_state(state, crtc);
1106
1107         /*
1108          * The hardware degamma is active whenever the pipe
1109          * CSC is active. Thus even if the old state has no
1110          * software degamma we need to avoid clobbering the
1111          * linear hardware degamma mid scanout.
1112          */
1113         return !old_crtc_state->csc_enable &&
1114                 !old_crtc_state->hw.gamma_lut;
1115 }
1116
1117 int intel_color_check(struct intel_crtc_state *crtc_state)
1118 {
1119         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1120
1121         return dev_priv->display.color_check(crtc_state);
1122 }
1123
1124 void intel_color_get_config(struct intel_crtc_state *crtc_state)
1125 {
1126         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1127
1128         if (dev_priv->display.read_luts)
1129                 dev_priv->display.read_luts(crtc_state);
1130 }
1131
1132 static bool need_plane_update(struct intel_plane *plane,
1133                               const struct intel_crtc_state *crtc_state)
1134 {
1135         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1136
1137         /*
1138          * On pre-SKL the pipe gamma enable and pipe csc enable for
1139          * the pipe bottom color are configured via the primary plane.
1140          * We have to reconfigure that even if the plane is inactive.
1141          */
1142         return crtc_state->active_planes & BIT(plane->id) ||
1143                 (INTEL_GEN(dev_priv) < 9 &&
1144                  plane->id == PLANE_PRIMARY);
1145 }
1146
1147 static int
1148 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1149 {
1150         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1151         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1152         struct intel_atomic_state *state =
1153                 to_intel_atomic_state(new_crtc_state->uapi.state);
1154         const struct intel_crtc_state *old_crtc_state =
1155                 intel_atomic_get_old_crtc_state(state, crtc);
1156         struct intel_plane *plane;
1157
1158         if (!new_crtc_state->hw.active ||
1159             drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
1160                 return 0;
1161
1162         if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1163             new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1164                 return 0;
1165
1166         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1167                 struct intel_plane_state *plane_state;
1168
1169                 if (!need_plane_update(plane, new_crtc_state))
1170                         continue;
1171
1172                 plane_state = intel_atomic_get_plane_state(state, plane);
1173                 if (IS_ERR(plane_state))
1174                         return PTR_ERR(plane_state);
1175
1176                 new_crtc_state->update_planes |= BIT(plane->id);
1177         }
1178
1179         return 0;
1180 }
1181
1182 static int check_lut_size(const struct drm_property_blob *lut, int expected)
1183 {
1184         int len;
1185
1186         if (!lut)
1187                 return 0;
1188
1189         len = drm_color_lut_size(lut);
1190         if (len != expected) {
1191                 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1192                               len, expected);
1193                 return -EINVAL;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int check_luts(const struct intel_crtc_state *crtc_state)
1200 {
1201         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1202         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1203         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1204         int gamma_length, degamma_length;
1205         u32 gamma_tests, degamma_tests;
1206
1207         /* Always allow legacy gamma LUT with no further checking. */
1208         if (crtc_state_is_legacy_gamma(crtc_state))
1209                 return 0;
1210
1211         /* C8 relies on its palette being stored in the legacy LUT */
1212         if (crtc_state->c8_planes) {
1213                 drm_dbg_kms(&dev_priv->drm,
1214                             "C8 pixelformat requires the legacy LUT\n");
1215                 return -EINVAL;
1216         }
1217
1218         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1219         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1220         degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1221         gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1222
1223         if (check_lut_size(degamma_lut, degamma_length) ||
1224             check_lut_size(gamma_lut, gamma_length))
1225                 return -EINVAL;
1226
1227         if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1228             drm_color_lut_check(gamma_lut, gamma_tests))
1229                 return -EINVAL;
1230
1231         return 0;
1232 }
1233
1234 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1235 {
1236         if (!crtc_state->gamma_enable ||
1237             crtc_state_is_legacy_gamma(crtc_state))
1238                 return GAMMA_MODE_MODE_8BIT;
1239         else
1240                 return GAMMA_MODE_MODE_10BIT; /* i965+ only */
1241 }
1242
1243 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1244 {
1245         int ret;
1246
1247         ret = check_luts(crtc_state);
1248         if (ret)
1249                 return ret;
1250
1251         crtc_state->gamma_enable =
1252                 crtc_state->hw.gamma_lut &&
1253                 !crtc_state->c8_planes;
1254
1255         crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1256
1257         ret = intel_color_add_affected_planes(crtc_state);
1258         if (ret)
1259                 return ret;
1260
1261         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1262
1263         return 0;
1264 }
1265
1266 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1267 {
1268         u32 cgm_mode = 0;
1269
1270         if (crtc_state_is_legacy_gamma(crtc_state))
1271                 return 0;
1272
1273         if (crtc_state->hw.degamma_lut)
1274                 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1275         if (crtc_state->hw.ctm)
1276                 cgm_mode |= CGM_PIPE_MODE_CSC;
1277         if (crtc_state->hw.gamma_lut)
1278                 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1279
1280         return cgm_mode;
1281 }
1282
1283 /*
1284  * CHV color pipeline:
1285  * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
1286  * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
1287  *
1288  * We always bypass the WGC csc and use the CGM csc
1289  * instead since it has degamma and better precision.
1290  */
1291 static int chv_color_check(struct intel_crtc_state *crtc_state)
1292 {
1293         int ret;
1294
1295         ret = check_luts(crtc_state);
1296         if (ret)
1297                 return ret;
1298
1299         /*
1300          * Pipe gamma will be used only for the legacy LUT.
1301          * Otherwise we bypass it and use the CGM gamma instead.
1302          */
1303         crtc_state->gamma_enable =
1304                 crtc_state_is_legacy_gamma(crtc_state) &&
1305                 !crtc_state->c8_planes;
1306
1307         crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1308
1309         crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1310
1311         ret = intel_color_add_affected_planes(crtc_state);
1312         if (ret)
1313                 return ret;
1314
1315         crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
1316
1317         return 0;
1318 }
1319
1320 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1321 {
1322         if (!crtc_state->gamma_enable ||
1323             crtc_state_is_legacy_gamma(crtc_state))
1324                 return GAMMA_MODE_MODE_8BIT;
1325         else
1326                 return GAMMA_MODE_MODE_10BIT;
1327 }
1328
1329 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1330 {
1331         /*
1332          * CSC comes after the LUT in RGB->YCbCr mode.
1333          * RGB->YCbCr needs the limited range offsets added to
1334          * the output. RGB limited range output is handled by
1335          * the hw automagically elsewhere.
1336          */
1337         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1338                 return CSC_BLACK_SCREEN_OFFSET;
1339
1340         return CSC_MODE_YUV_TO_RGB |
1341                 CSC_POSITION_BEFORE_GAMMA;
1342 }
1343
1344 static int ilk_color_check(struct intel_crtc_state *crtc_state)
1345 {
1346         int ret;
1347
1348         ret = check_luts(crtc_state);
1349         if (ret)
1350                 return ret;
1351
1352         crtc_state->gamma_enable =
1353                 crtc_state->hw.gamma_lut &&
1354                 !crtc_state->c8_planes;
1355
1356         /*
1357          * We don't expose the ctm on ilk/snb currently, also RGB
1358          * limited range output is handled by the hw automagically.
1359          */
1360         crtc_state->csc_enable =
1361                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1362
1363         crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1364
1365         crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1366
1367         ret = intel_color_add_affected_planes(crtc_state);
1368         if (ret)
1369                 return ret;
1370
1371         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1372
1373         return 0;
1374 }
1375
1376 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1377 {
1378         if (!crtc_state->gamma_enable ||
1379             crtc_state_is_legacy_gamma(crtc_state))
1380                 return GAMMA_MODE_MODE_8BIT;
1381         else if (crtc_state->hw.gamma_lut &&
1382                  crtc_state->hw.degamma_lut)
1383                 return GAMMA_MODE_MODE_SPLIT;
1384         else
1385                 return GAMMA_MODE_MODE_10BIT;
1386 }
1387
1388 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1389 {
1390         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1391
1392         /*
1393          * CSC comes after the LUT in degamma, RGB->YCbCr,
1394          * and RGB full->limited range mode.
1395          */
1396         if (crtc_state->hw.degamma_lut ||
1397             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1398             limited_color_range)
1399                 return 0;
1400
1401         return CSC_POSITION_BEFORE_GAMMA;
1402 }
1403
1404 static int ivb_color_check(struct intel_crtc_state *crtc_state)
1405 {
1406         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1407         int ret;
1408
1409         ret = check_luts(crtc_state);
1410         if (ret)
1411                 return ret;
1412
1413         crtc_state->gamma_enable =
1414                 (crtc_state->hw.gamma_lut ||
1415                  crtc_state->hw.degamma_lut) &&
1416                 !crtc_state->c8_planes;
1417
1418         crtc_state->csc_enable =
1419                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1420                 crtc_state->hw.ctm || limited_color_range;
1421
1422         crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1423
1424         crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1425
1426         ret = intel_color_add_affected_planes(crtc_state);
1427         if (ret)
1428                 return ret;
1429
1430         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1431
1432         return 0;
1433 }
1434
1435 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1436 {
1437         if (!crtc_state->gamma_enable ||
1438             crtc_state_is_legacy_gamma(crtc_state))
1439                 return GAMMA_MODE_MODE_8BIT;
1440         else
1441                 return GAMMA_MODE_MODE_10BIT;
1442 }
1443
1444 static int glk_color_check(struct intel_crtc_state *crtc_state)
1445 {
1446         int ret;
1447
1448         ret = check_luts(crtc_state);
1449         if (ret)
1450                 return ret;
1451
1452         crtc_state->gamma_enable =
1453                 crtc_state->hw.gamma_lut &&
1454                 !crtc_state->c8_planes;
1455
1456         /* On GLK+ degamma LUT is controlled by csc_enable */
1457         crtc_state->csc_enable =
1458                 crtc_state->hw.degamma_lut ||
1459                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1460                 crtc_state->hw.ctm || crtc_state->limited_color_range;
1461
1462         crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1463
1464         crtc_state->csc_mode = 0;
1465
1466         ret = intel_color_add_affected_planes(crtc_state);
1467         if (ret)
1468                 return ret;
1469
1470         crtc_state->preload_luts = glk_can_preload_luts(crtc_state);
1471
1472         return 0;
1473 }
1474
1475 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1476 {
1477         u32 gamma_mode = 0;
1478
1479         if (crtc_state->hw.degamma_lut)
1480                 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1481
1482         if (crtc_state->hw.gamma_lut &&
1483             !crtc_state->c8_planes)
1484                 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1485
1486         if (!crtc_state->hw.gamma_lut ||
1487             crtc_state_is_legacy_gamma(crtc_state))
1488                 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1489         else
1490                 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1491
1492         return gamma_mode;
1493 }
1494
1495 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1496 {
1497         u32 csc_mode = 0;
1498
1499         if (crtc_state->hw.ctm)
1500                 csc_mode |= ICL_CSC_ENABLE;
1501
1502         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1503             crtc_state->limited_color_range)
1504                 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1505
1506         return csc_mode;
1507 }
1508
1509 static int icl_color_check(struct intel_crtc_state *crtc_state)
1510 {
1511         int ret;
1512
1513         ret = check_luts(crtc_state);
1514         if (ret)
1515                 return ret;
1516
1517         crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1518
1519         crtc_state->csc_mode = icl_csc_mode(crtc_state);
1520
1521         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1522
1523         return 0;
1524 }
1525
1526 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1527 {
1528         if (!crtc_state->gamma_enable)
1529                 return 0;
1530
1531         switch (crtc_state->gamma_mode) {
1532         case GAMMA_MODE_MODE_8BIT:
1533                 return 8;
1534         case GAMMA_MODE_MODE_10BIT:
1535                 return 16;
1536         default:
1537                 MISSING_CASE(crtc_state->gamma_mode);
1538                 return 0;
1539         }
1540 }
1541
1542 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1543 {
1544         if (!crtc_state->gamma_enable)
1545                 return 0;
1546
1547         if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1548                 return 0;
1549
1550         switch (crtc_state->gamma_mode) {
1551         case GAMMA_MODE_MODE_8BIT:
1552                 return 8;
1553         case GAMMA_MODE_MODE_10BIT:
1554                 return 10;
1555         default:
1556                 MISSING_CASE(crtc_state->gamma_mode);
1557                 return 0;
1558         }
1559 }
1560
1561 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1562 {
1563         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1564                 return 10;
1565         else
1566                 return i9xx_gamma_precision(crtc_state);
1567 }
1568
1569 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1570 {
1571         if (!crtc_state->gamma_enable)
1572                 return 0;
1573
1574         switch (crtc_state->gamma_mode) {
1575         case GAMMA_MODE_MODE_8BIT:
1576                 return 8;
1577         case GAMMA_MODE_MODE_10BIT:
1578                 return 10;
1579         default:
1580                 MISSING_CASE(crtc_state->gamma_mode);
1581                 return 0;
1582         }
1583 }
1584
1585 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1586 {
1587         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1588         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1589
1590         if (HAS_GMCH(dev_priv)) {
1591                 if (IS_CHERRYVIEW(dev_priv))
1592                         return chv_gamma_precision(crtc_state);
1593                 else
1594                         return i9xx_gamma_precision(crtc_state);
1595         } else {
1596                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1597                         return glk_gamma_precision(crtc_state);
1598                 else if (IS_IRONLAKE(dev_priv))
1599                         return ilk_gamma_precision(crtc_state);
1600         }
1601
1602         return 0;
1603 }
1604
1605 static bool err_check(struct drm_color_lut *lut1,
1606                       struct drm_color_lut *lut2, u32 err)
1607 {
1608         return ((abs((long)lut2->red - lut1->red)) <= err) &&
1609                 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1610                 ((abs((long)lut2->green - lut1->green)) <= err);
1611 }
1612
1613 static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
1614                                         struct drm_color_lut *lut2,
1615                                         int lut_size, u32 err)
1616 {
1617         int i;
1618
1619         for (i = 0; i < lut_size; i++) {
1620                 if (!err_check(&lut1[i], &lut2[i], err))
1621                         return false;
1622         }
1623
1624         return true;
1625 }
1626
1627 bool intel_color_lut_equal(struct drm_property_blob *blob1,
1628                            struct drm_property_blob *blob2,
1629                            u32 gamma_mode, u32 bit_precision)
1630 {
1631         struct drm_color_lut *lut1, *lut2;
1632         int lut_size1, lut_size2;
1633         u32 err;
1634
1635         if (!blob1 != !blob2)
1636                 return false;
1637
1638         if (!blob1)
1639                 return true;
1640
1641         lut_size1 = drm_color_lut_size(blob1);
1642         lut_size2 = drm_color_lut_size(blob2);
1643
1644         /* check sw and hw lut size */
1645         switch (gamma_mode) {
1646         case GAMMA_MODE_MODE_8BIT:
1647         case GAMMA_MODE_MODE_10BIT:
1648                 if (lut_size1 != lut_size2)
1649                         return false;
1650                 break;
1651         default:
1652                 MISSING_CASE(gamma_mode);
1653                         return false;
1654         }
1655
1656         lut1 = blob1->data;
1657         lut2 = blob2->data;
1658
1659         err = 0xffff >> bit_precision;
1660
1661         /* check sw and hw lut entry to be equal */
1662         switch (gamma_mode) {
1663         case GAMMA_MODE_MODE_8BIT:
1664         case GAMMA_MODE_MODE_10BIT:
1665                 if (!intel_color_lut_entry_equal(lut1, lut2,
1666                                                  lut_size2, err))
1667                         return false;
1668                 break;
1669         default:
1670                 MISSING_CASE(gamma_mode);
1671                         return false;
1672         }
1673
1674         return true;
1675 }
1676
1677 /* convert hw value with given bit_precision to lut property val */
1678 static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
1679 {
1680         u32 max = 0xffff >> (16 - bit_precision);
1681
1682         val = clamp_val(val, 0, max);
1683
1684         if (bit_precision < 16)
1685                 val <<= 16 - bit_precision;
1686
1687         return val;
1688 }
1689
1690 static struct drm_property_blob *
1691 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
1692 {
1693         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1694         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1695         enum pipe pipe = crtc->pipe;
1696         struct drm_property_blob *blob;
1697         struct drm_color_lut *lut;
1698         u32 i, val;
1699
1700         blob = drm_property_create_blob(&dev_priv->drm,
1701                                         sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1702                                         NULL);
1703         if (IS_ERR(blob))
1704                 return NULL;
1705
1706         lut = blob->data;
1707
1708         for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1709                 val = intel_de_read(dev_priv, PALETTE(pipe, i));
1710
1711                 lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
1712                                                         LGC_PALETTE_RED_MASK, val), 8);
1713                 lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
1714                                                           LGC_PALETTE_GREEN_MASK, val), 8);
1715                 lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1716                                                          LGC_PALETTE_BLUE_MASK, val), 8);
1717         }
1718
1719         return blob;
1720 }
1721
1722 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1723 {
1724         if (!crtc_state->gamma_enable)
1725                 return;
1726
1727         crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
1728 }
1729
1730 static struct drm_property_blob *
1731 i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
1732 {
1733         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1734         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1735         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1736         enum pipe pipe = crtc->pipe;
1737         struct drm_property_blob *blob;
1738         struct drm_color_lut *lut;
1739         u32 i, val1, val2;
1740
1741         blob = drm_property_create_blob(&dev_priv->drm,
1742                                         sizeof(struct drm_color_lut) * lut_size,
1743                                         NULL);
1744         if (IS_ERR(blob))
1745                 return NULL;
1746
1747         lut = blob->data;
1748
1749         for (i = 0; i < lut_size - 1; i++) {
1750                 val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
1751                 val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
1752
1753                 lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
1754                                                  REG_FIELD_GET(PALETTE_RED_MASK, val1);
1755                 lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
1756                                                    REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
1757                 lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
1758                                                   REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
1759         }
1760
1761         lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1762                                          intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
1763         lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1764                                            intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
1765         lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1766                                           intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
1767
1768         return blob;
1769 }
1770
1771 static void i965_read_luts(struct intel_crtc_state *crtc_state)
1772 {
1773         if (!crtc_state->gamma_enable)
1774                 return;
1775
1776         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1777                 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
1778         else
1779                 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
1780 }
1781
1782 static struct drm_property_blob *
1783 chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
1784 {
1785         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1786         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1787         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1788         enum pipe pipe = crtc->pipe;
1789         struct drm_property_blob *blob;
1790         struct drm_color_lut *lut;
1791         u32 i, val;
1792
1793         blob = drm_property_create_blob(&dev_priv->drm,
1794                                         sizeof(struct drm_color_lut) * lut_size,
1795                                         NULL);
1796         if (IS_ERR(blob))
1797                 return NULL;
1798
1799         lut = blob->data;
1800
1801         for (i = 0; i < lut_size; i++) {
1802                 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
1803                 lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
1804                                                           CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
1805                 lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1806                                                          CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
1807
1808                 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
1809                 lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
1810                                                         CGM_PIPE_GAMMA_RED_MASK, val), 10);
1811         }
1812
1813         return blob;
1814 }
1815
1816 static void chv_read_luts(struct intel_crtc_state *crtc_state)
1817 {
1818         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1819                 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
1820         else
1821                 i965_read_luts(crtc_state);
1822 }
1823
1824 static struct drm_property_blob *
1825 ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
1826 {
1827         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1828         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1829         enum pipe pipe = crtc->pipe;
1830         struct drm_property_blob *blob;
1831         struct drm_color_lut *lut;
1832         u32 i, val;
1833
1834         blob = drm_property_create_blob(&dev_priv->drm,
1835                                         sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1836                                         NULL);
1837         if (IS_ERR(blob))
1838                 return NULL;
1839
1840         lut = blob->data;
1841
1842         for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1843                 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
1844
1845                 lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
1846                                                         LGC_PALETTE_RED_MASK, val), 8);
1847                 lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
1848                                                           LGC_PALETTE_GREEN_MASK, val), 8);
1849                 lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1850                                                          LGC_PALETTE_BLUE_MASK, val), 8);
1851         }
1852
1853         return blob;
1854 }
1855
1856 static struct drm_property_blob *
1857 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
1858 {
1859         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1860         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1861         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1862         enum pipe pipe = crtc->pipe;
1863         struct drm_property_blob *blob;
1864         struct drm_color_lut *lut;
1865         u32 i, val;
1866
1867         blob = drm_property_create_blob(&dev_priv->drm,
1868                                         sizeof(struct drm_color_lut) * lut_size,
1869                                         NULL);
1870         if (IS_ERR(blob))
1871                 return NULL;
1872
1873         lut = blob->data;
1874
1875         for (i = 0; i < lut_size; i++) {
1876                 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
1877
1878                 lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
1879                                                         PREC_PALETTE_RED_MASK, val), 10);
1880                 lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
1881                                                           PREC_PALETTE_GREEN_MASK, val), 10);
1882                 lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1883                                                          PREC_PALETTE_BLUE_MASK, val), 10);
1884         }
1885
1886         return blob;
1887 }
1888
1889 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1890 {
1891         if (!crtc_state->gamma_enable)
1892                 return;
1893
1894         if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1895                 return;
1896
1897         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1898                 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
1899         else
1900                 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
1901 }
1902
1903 static struct drm_property_blob *
1904 glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
1905 {
1906         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1907         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1908         int hw_lut_size = ivb_lut_10_size(prec_index);
1909         enum pipe pipe = crtc->pipe;
1910         struct drm_property_blob *blob;
1911         struct drm_color_lut *lut;
1912         u32 i, val;
1913
1914         blob = drm_property_create_blob(&dev_priv->drm,
1915                                         sizeof(struct drm_color_lut) * hw_lut_size,
1916                                         NULL);
1917         if (IS_ERR(blob))
1918                 return NULL;
1919
1920         lut = blob->data;
1921
1922         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
1923                        prec_index | PAL_PREC_AUTO_INCREMENT);
1924
1925         for (i = 0; i < hw_lut_size; i++) {
1926                 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
1927
1928                 lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
1929                                                         PREC_PAL_DATA_RED_MASK, val), 10);
1930                 lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
1931                                                         PREC_PAL_DATA_GREEN_MASK, val), 10);
1932                 lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1933                                                         PREC_PAL_DATA_BLUE_MASK, val), 10);
1934         }
1935
1936         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
1937
1938         return blob;
1939 }
1940
1941 static void glk_read_luts(struct intel_crtc_state *crtc_state)
1942 {
1943         if (!crtc_state->gamma_enable)
1944                 return;
1945
1946         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1947                 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
1948         else
1949                 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
1950 }
1951
1952 void intel_color_init(struct intel_crtc *crtc)
1953 {
1954         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1955         bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
1956
1957         drm_mode_crtc_set_gamma_size(&crtc->base, 256);
1958
1959         if (HAS_GMCH(dev_priv)) {
1960                 if (IS_CHERRYVIEW(dev_priv)) {
1961                         dev_priv->display.color_check = chv_color_check;
1962                         dev_priv->display.color_commit = i9xx_color_commit;
1963                         dev_priv->display.load_luts = chv_load_luts;
1964                         dev_priv->display.read_luts = chv_read_luts;
1965                 } else if (INTEL_GEN(dev_priv) >= 4) {
1966                         dev_priv->display.color_check = i9xx_color_check;
1967                         dev_priv->display.color_commit = i9xx_color_commit;
1968                         dev_priv->display.load_luts = i965_load_luts;
1969                         dev_priv->display.read_luts = i965_read_luts;
1970                 } else {
1971                         dev_priv->display.color_check = i9xx_color_check;
1972                         dev_priv->display.color_commit = i9xx_color_commit;
1973                         dev_priv->display.load_luts = i9xx_load_luts;
1974                         dev_priv->display.read_luts = i9xx_read_luts;
1975                 }
1976         } else {
1977                 if (INTEL_GEN(dev_priv) >= 11)
1978                         dev_priv->display.color_check = icl_color_check;
1979                 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1980                         dev_priv->display.color_check = glk_color_check;
1981                 else if (INTEL_GEN(dev_priv) >= 7)
1982                         dev_priv->display.color_check = ivb_color_check;
1983                 else
1984                         dev_priv->display.color_check = ilk_color_check;
1985
1986                 if (INTEL_GEN(dev_priv) >= 9)
1987                         dev_priv->display.color_commit = skl_color_commit;
1988                 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1989                         dev_priv->display.color_commit = hsw_color_commit;
1990                 else
1991                         dev_priv->display.color_commit = ilk_color_commit;
1992
1993                 if (INTEL_GEN(dev_priv) >= 11) {
1994                         dev_priv->display.load_luts = icl_load_luts;
1995                 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1996                         dev_priv->display.load_luts = glk_load_luts;
1997                         dev_priv->display.read_luts = glk_read_luts;
1998                 } else if (INTEL_GEN(dev_priv) >= 8) {
1999                         dev_priv->display.load_luts = bdw_load_luts;
2000                 } else if (INTEL_GEN(dev_priv) >= 7) {
2001                         dev_priv->display.load_luts = ivb_load_luts;
2002                 } else {
2003                         dev_priv->display.load_luts = ilk_load_luts;
2004                         dev_priv->display.read_luts = ilk_read_luts;
2005                 }
2006         }
2007
2008         drm_crtc_enable_color_mgmt(&crtc->base,
2009                                    INTEL_INFO(dev_priv)->color.degamma_lut_size,
2010                                    has_ctm,
2011                                    INTEL_INFO(dev_priv)->color.gamma_lut_size);
2012 }