drivers/gpu/drm/i915/display/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_color.h"
  26 #include "intel_display_types.h"
  27
  28 #define CTM_COEFF_SIGN  (1ULL << 63)
  29
  30 #define CTM_COEFF_1_0   (1ULL << 32)
  31 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  32 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  33 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  34 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  35 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  36 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  37
  38 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  39
  40 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  41 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  42
  43 #define LEGACY_LUT_LENGTH               256
  44
  45 /*
  46  * ILK+ csc matrix:
  47  *
  48  * |R/Cr|   | c0 c1 c2 |   ( |R/Cr|   |preoff0| )   |postoff0|
  49  * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
  50  * |B/Cb|   | c6 c7 c8 |   ( |B/Cb|   |preoff2| )   |postoff2|
  51  *
  52  * ILK/SNB don't have explicit post offsets, and instead
  53  * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
  54  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
  55  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
  56  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
  57  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
  58  */
  59
  60 /*
  61  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  62  * format). This macro takes the coefficient we want transformed and the
  63  * number of fractional bits.
  64  *
  65  * We only have a 9 bits precision window which slides depending on the value
  66  * of the CTM coefficient and we write the value from bit 3. We also round the
  67  * value.
  68  */
  69 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  70         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  71
  72 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
  73 #define ILK_CSC_COEFF_1_0 0x7800
  74
  75 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
  76
  77 /* Nop pre/post offsets */
  78 static const u16 ilk_csc_off_zero[3] = {};
  79
  80 /* Identity matrix */
  81 static const u16 ilk_csc_coeff_identity[9] = {
  82         ILK_CSC_COEFF_1_0, 0, 0,
  83         0, ILK_CSC_COEFF_1_0, 0,
  84         0, 0, ILK_CSC_COEFF_1_0,
  85 };
  86
  87 /* Limited range RGB post offsets */
  88 static const u16 ilk_csc_postoff_limited_range[3] = {
  89         ILK_CSC_POSTOFF_LIMITED_RANGE,
  90         ILK_CSC_POSTOFF_LIMITED_RANGE,
  91         ILK_CSC_POSTOFF_LIMITED_RANGE,
  92 };
  93
  94 /* Full range RGB -> limited range RGB matrix */
  95 static const u16 ilk_csc_coeff_limited_range[9] = {
  96         ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
  97         0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
  98         0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
  99 };
 100
 101 /* BT.709 full range RGB -> limited range YCbCr matrix */
 102 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
 103         0x1e08, 0x9cc0, 0xb528,
 104         0x2ba8, 0x09d8, 0x37e8,
 105         0xbce8, 0x9ad8, 0x1e08,
 106 };
 107
 108 /* Limited range YCbCr post offsets */
 109 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
 110         0x0800, 0x0100, 0x0800,
 111 };
 112
 113 static bool lut_is_legacy(const struct drm_property_blob *lut)
 114 {
 115         return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
 116 }
 117
 118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
 119 {
 120         return !crtc_state->hw.degamma_lut &&
 121                 !crtc_state->hw.ctm &&
 122                 crtc_state->hw.gamma_lut &&
 123                 lut_is_legacy(crtc_state->hw.gamma_lut);
 124 }
 125
 126 /*
 127  * When using limited range, multiply the matrix given by userspace by
 128  * the matrix that we would use for the limited range.
 129  */
 130 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 131 {
 132         int i;
 133
 134         for (i = 0; i < 9; i++) {
 135                 u64 user_coeff = input[i];
 136                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
 137                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
 138                                           CTM_COEFF_4_0 - 1) >> 2;
 139
 140                 /*
 141                  * By scaling every co-efficient with limited range (16-235)
 142                  * vs full range (0-255) the final o/p will be scaled down to
 143                  * fit in the limited range supported by the panel.
 144                  */
 145                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 146                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 147         }
 148
 149         return result;
 150 }
 151
 152 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
 153                                 const u16 preoff[3],
 154                                 const u16 coeff[9],
 155                                 const u16 postoff[3])
 156 {
 157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 158         enum pipe pipe = crtc->pipe;
 159
 160         intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
 161         intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
 162         intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
 163
 164         intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
 165                        coeff[0] << 16 | coeff[1]);
 166         intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
 167
 168         intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
 169                        coeff[3] << 16 | coeff[4]);
 170         intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
 171
 172         intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
 173                        coeff[6] << 16 | coeff[7]);
 174         intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
 175
 176         if (INTEL_GEN(dev_priv) >= 7) {
 177                 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
 178                                postoff[0]);
 179                 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
 180                                postoff[1]);
 181                 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
 182                                postoff[2]);
 183         }
 184 }
 185
 186 static void icl_update_output_csc(struct intel_crtc *crtc,
 187                                   const u16 preoff[3],
 188                                   const u16 coeff[9],
 189                                   const u16 postoff[3])
 190 {
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192         enum pipe pipe = crtc->pipe;
 193
 194         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
 195         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
 196         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
 197
 198         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
 199                        coeff[0] << 16 | coeff[1]);
 200         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
 201                        coeff[2] << 16);
 202
 203         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
 204                        coeff[3] << 16 | coeff[4]);
 205         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
 206                        coeff[5] << 16);
 207
 208         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
 209                        coeff[6] << 16 | coeff[7]);
 210         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
 211                        coeff[8] << 16);
 212
 213         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
 214         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
 215         intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
 216 }
 217
 218 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 219 {
 220         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 221
 222         /*
 223          * FIXME if there's a gamma LUT after the CSC, we should
 224          * do the range compression using the gamma LUT instead.
 225          */
 226         return crtc_state->limited_color_range &&
 227                 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
 228                  IS_GEN_RANGE(dev_priv, 9, 10));
 229 }
 230
 231 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 232                                 u16 coeffs[9])
 233 {
 234         const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
 235         const u64 *input;
 236         u64 temp[9];
 237         int i;
 238
 239         if (ilk_csc_limited_range(crtc_state))
 240                 input = ctm_mult_by_limited(temp, ctm->matrix);
 241         else
 242                 input = ctm->matrix;
 243
 244         /*
 245          * Convert fixed point S31.32 input to format supported by the
 246          * hardware.
 247          */
 248         for (i = 0; i < 9; i++) {
 249                 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
 250
 251                 /*
 252                  * Clamp input value to min/max supported by
 253                  * hardware.
 254                  */
 255                 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 256
 257                 coeffs[i] = 0;
 258
 259                 /* sign bit */
 260                 if (CTM_COEFF_NEGATIVE(input[i]))
 261                         coeffs[i] |= 1 << 15;
 262
 263                 if (abs_coeff < CTM_COEFF_0_125)
 264                         coeffs[i] |= (3 << 12) |
 265                                 ILK_CSC_COEFF_FP(abs_coeff, 12);
 266                 else if (abs_coeff < CTM_COEFF_0_25)
 267                         coeffs[i] |= (2 << 12) |
 268                                 ILK_CSC_COEFF_FP(abs_coeff, 11);
 269                 else if (abs_coeff < CTM_COEFF_0_5)
 270                         coeffs[i] |= (1 << 12) |
 271                                 ILK_CSC_COEFF_FP(abs_coeff, 10);
 272                 else if (abs_coeff < CTM_COEFF_1_0)
 273                         coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 274                 else if (abs_coeff < CTM_COEFF_2_0)
 275                         coeffs[i] |= (7 << 12) |
 276                                 ILK_CSC_COEFF_FP(abs_coeff, 8);
 277                 else
 278                         coeffs[i] |= (6 << 12) |
 279                                 ILK_CSC_COEFF_FP(abs_coeff, 7);
 280         }
 281 }
 282
 283 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 284 {
 285         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 286         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 287         bool limited_color_range = ilk_csc_limited_range(crtc_state);
 288
 289         if (crtc_state->hw.ctm) {
 290                 u16 coeff[9];
 291
 292                 ilk_csc_convert_ctm(crtc_state, coeff);
 293                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
 294                                     limited_color_range ?
 295                                     ilk_csc_postoff_limited_range :
 296                                     ilk_csc_off_zero);
 297         } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 298                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 299                                     ilk_csc_coeff_rgb_to_ycbcr,
 300                                     ilk_csc_postoff_rgb_to_ycbcr);
 301         } else if (limited_color_range) {
 302                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 303                                     ilk_csc_coeff_limited_range,
 304                                     ilk_csc_postoff_limited_range);
 305         } else if (crtc_state->csc_enable) {
 306                 /*
 307                  * On GLK+ both pipe CSC and degamma LUT are controlled
 308                  * by csc_enable. Hence for the cases where the degama
 309                  * LUT is needed but CSC is not we need to load an
 310                  * identity matrix.
 311                  */
 312                 drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
 313                             !IS_GEMINILAKE(dev_priv));
 314
 315                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 316                                     ilk_csc_coeff_identity,
 317                                     ilk_csc_off_zero);
 318         }
 319
 320         intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
 321                        crtc_state->csc_mode);
 322 }
 323
 324 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 325 {
 326         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 327         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 328
 329         if (crtc_state->hw.ctm) {
 330                 u16 coeff[9];
 331
 332                 ilk_csc_convert_ctm(crtc_state, coeff);
 333                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 334                                     coeff, ilk_csc_off_zero);
 335         }
 336
 337         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 338                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 339                                       ilk_csc_coeff_rgb_to_ycbcr,
 340                                       ilk_csc_postoff_rgb_to_ycbcr);
 341         } else if (crtc_state->limited_color_range) {
 342                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 343                                       ilk_csc_coeff_limited_range,
 344                                       ilk_csc_postoff_limited_range);
 345         }
 346
 347         intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
 348                        crtc_state->csc_mode);
 349 }
 350
 351 static void chv_load_cgm_csc(struct intel_crtc *crtc,
 352                              const struct drm_property_blob *blob)
 353 {
 354         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 355         const struct drm_color_ctm *ctm = blob->data;
 356         enum pipe pipe = crtc->pipe;
 357         u16 coeffs[9];
 358         int i;
 359
 360         for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 361                 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
 362
 363                 /* Round coefficient. */
 364                 abs_coeff += 1 << (32 - 13);
 365                 /* Clamp to hardware limits. */
 366                 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 367
 368                 coeffs[i] = 0;
 369
 370                 /* Write coefficients in S3.12 format. */
 371                 if (ctm->matrix[i] & (1ULL << 63))
 372                         coeffs[i] |= 1 << 15;
 373
 374                 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 375                 coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 376         }
 377
 378         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
 379                        coeffs[1] << 16 | coeffs[0]);
 380         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
 381                        coeffs[3] << 16 | coeffs[2]);
 382         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
 383                        coeffs[5] << 16 | coeffs[4]);
 384         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
 385                        coeffs[7] << 16 | coeffs[6]);
 386         intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
 387                        coeffs[8]);
 388 }
 389
 390 /* convert hw value with given bit_precision to lut property val */
 391 static u32 intel_color_lut_pack(u32 val, int bit_precision)
 392 {
 393         u32 max = 0xffff >> (16 - bit_precision);
 394
 395         val = clamp_val(val, 0, max);
 396
 397         if (bit_precision < 16)
 398                 val <<= 16 - bit_precision;
 399
 400         return val;
 401 }
 402
 403 static u32 i9xx_lut_8(const struct drm_color_lut *color)
 404 {
 405         return drm_color_lut_extract(color->red, 8) << 16 |
 406                 drm_color_lut_extract(color->green, 8) << 8 |
 407                 drm_color_lut_extract(color->blue, 8);
 408 }
 409
 410 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
 411 {
 412         entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
 413         entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
 414         entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
 415 }
 416
 417 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 418 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 419 {
 420         return (color->red & 0xff) << 16 |
 421                 (color->green & 0xff) << 8 |
 422                 (color->blue & 0xff);
 423 }
 424
 425 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
 426 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
 427 {
 428         return (color->red >> 8) << 16 |
 429                 (color->green >> 8) << 8 |
 430                 (color->blue >> 8);
 431 }
 432
 433 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 434 {
 435         entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
 436                 REG_FIELD_GET(PALETTE_RED_MASK, ldw);
 437         entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
 438                 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
 439         entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
 440                 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
 441 }
 442
 443 static u16 i965_lut_11p6_max_pack(u32 val)
 444 {
 445         /* PIPEGCMAX is 11.6, clamp to 10.6 */
 446         return clamp_val(val, 0, 0xffff);
 447 }
 448
 449 static u32 ilk_lut_10(const struct drm_color_lut *color)
 450 {
 451         return drm_color_lut_extract(color->red, 10) << 20 |
 452                 drm_color_lut_extract(color->green, 10) << 10 |
 453                 drm_color_lut_extract(color->blue, 10);
 454 }
 455
 456 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
 457 {
 458         entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
 459         entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
 460         entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
 461 }
 462
 463 static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 464 {
 465         entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
 466                                    REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
 467         entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 |
 468                                      REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
 469         entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 |
 470                                     REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
 471 }
 472
 473 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 474 {
 475         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 476         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 477         enum pipe pipe = crtc->pipe;
 478         u32 val;
 479
 480         val = intel_de_read(dev_priv, PIPECONF(pipe));
 481         val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
 482         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 483         intel_de_write(dev_priv, PIPECONF(pipe), val);
 484 }
 485
 486 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
 487 {
 488         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 489         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 490         enum pipe pipe = crtc->pipe;
 491         u32 val;
 492
 493         val = intel_de_read(dev_priv, PIPECONF(pipe));
 494         val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
 495         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 496         intel_de_write(dev_priv, PIPECONF(pipe), val);
 497
 498         ilk_load_csc_matrix(crtc_state);
 499 }
 500
 501 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 502 {
 503         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 504         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 505
 506         intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
 507                        crtc_state->gamma_mode);
 508
 509         ilk_load_csc_matrix(crtc_state);
 510 }
 511
 512 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 513 {
 514         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 515         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 516         enum pipe pipe = crtc->pipe;
 517         u32 val = 0;
 518
 519         /*
 520          * We don't (yet) allow userspace to control the pipe background color,
 521          * so force it to black, but apply pipe gamma and CSC appropriately
 522          * so that its handling will match how we program our planes.
 523          */
 524         if (crtc_state->gamma_enable)
 525                 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
 526         if (crtc_state->csc_enable)
 527                 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
 528         intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
 529
 530         intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
 531                        crtc_state->gamma_mode);
 532
 533         if (INTEL_GEN(dev_priv) >= 11)
 534                 icl_load_csc_matrix(crtc_state);
 535         else
 536                 ilk_load_csc_matrix(crtc_state);
 537 }
 538
 539 static void i9xx_load_lut_8(struct intel_crtc *crtc,
 540                             const struct drm_property_blob *blob)
 541 {
 542         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 543         const struct drm_color_lut *lut;
 544         enum pipe pipe = crtc->pipe;
 545         int i;
 546
 547         if (!blob)
 548                 return;
 549
 550         lut = blob->data;
 551
 552         for (i = 0; i < 256; i++)
 553                 intel_de_write(dev_priv, PALETTE(pipe, i),
 554                                i9xx_lut_8(&lut[i]));
 555 }
 556
 557 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 558 {
 559         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 561         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 562
 563         assert_pll_enabled(dev_priv, crtc->pipe);
 564
 565         i9xx_load_lut_8(crtc, gamma_lut);
 566 }
 567
 568 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 569                                const struct drm_property_blob *blob)
 570 {
 571         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 572         const struct drm_color_lut *lut = blob->data;
 573         int i, lut_size = drm_color_lut_size(blob);
 574         enum pipe pipe = crtc->pipe;
 575
 576         for (i = 0; i < lut_size - 1; i++) {
 577                 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0),
 578                                i965_lut_10p6_ldw(&lut[i]));
 579                 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1),
 580                                i965_lut_10p6_udw(&lut[i]));
 581         }
 582
 583         intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red);
 584         intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green);
 585         intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue);
 586 }
 587
 588 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 589 {
 590         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 591         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 592         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 593
 594         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 595                 assert_dsi_pll_enabled(dev_priv);
 596         else
 597                 assert_pll_enabled(dev_priv, crtc->pipe);
 598
 599         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 600                 i9xx_load_lut_8(crtc, gamma_lut);
 601         else
 602                 i965_load_lut_10p6(crtc, gamma_lut);
 603 }
 604
 605 static void ilk_load_lut_8(struct intel_crtc *crtc,
 606                            const struct drm_property_blob *blob)
 607 {
 608         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 609         const struct drm_color_lut *lut;
 610         enum pipe pipe = crtc->pipe;
 611         int i;
 612
 613         if (!blob)
 614                 return;
 615
 616         lut = blob->data;
 617
 618         for (i = 0; i < 256; i++)
 619                 intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
 620                                i9xx_lut_8(&lut[i]));
 621 }
 622
 623 static void ilk_load_lut_10(struct intel_crtc *crtc,
 624                             const struct drm_property_blob *blob)
 625 {
 626         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 627         const struct drm_color_lut *lut = blob->data;
 628         int i, lut_size = drm_color_lut_size(blob);
 629         enum pipe pipe = crtc->pipe;
 630
 631         for (i = 0; i < lut_size; i++)
 632                 intel_de_write(dev_priv, PREC_PALETTE(pipe, i),
 633                                ilk_lut_10(&lut[i]));
 634 }
 635
 636 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 637 {
 638         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 639         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 640
 641         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 642                 ilk_load_lut_8(crtc, gamma_lut);
 643         else
 644                 ilk_load_lut_10(crtc, gamma_lut);
 645 }
 646
 647 static int ivb_lut_10_size(u32 prec_index)
 648 {
 649         if (prec_index & PAL_PREC_SPLIT_MODE)
 650                 return 512;
 651         else
 652                 return 1024;
 653 }
 654
 655 /*
 656  * IVB/HSW Bspec / PAL_PREC_INDEX:
 657  * "Restriction : Index auto increment mode is not
 658  *  supported and must not be enabled."
 659  */
 660 static void ivb_load_lut_10(struct intel_crtc *crtc,
 661                             const struct drm_property_blob *blob,
 662                             u32 prec_index)
 663 {
 664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 665         int hw_lut_size = ivb_lut_10_size(prec_index);
 666         const struct drm_color_lut *lut = blob->data;
 667         int i, lut_size = drm_color_lut_size(blob);
 668         enum pipe pipe = crtc->pipe;
 669
 670         for (i = 0; i < hw_lut_size; i++) {
 671                 /* We discard half the user entries in split gamma mode */
 672                 const struct drm_color_lut *entry =
 673                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 674
 675                 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
 676                 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
 677                                ilk_lut_10(entry));
 678         }
 679
 680         /*
 681          * Reset the index, otherwise it prevents the legacy palette to be
 682          * written properly.
 683          */
 684         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
 685 }
 686
 687 /* On BDW+ the index auto increment mode actually works */
 688 static void bdw_load_lut_10(struct intel_crtc *crtc,
 689                             const struct drm_property_blob *blob,
 690                             u32 prec_index)
 691 {
 692         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 693         int hw_lut_size = ivb_lut_10_size(prec_index);
 694         const struct drm_color_lut *lut = blob->data;
 695         int i, lut_size = drm_color_lut_size(blob);
 696         enum pipe pipe = crtc->pipe;
 697
 698         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
 699                        prec_index | PAL_PREC_AUTO_INCREMENT);
 700
 701         for (i = 0; i < hw_lut_size; i++) {
 702                 /* We discard half the user entries in split gamma mode */
 703                 const struct drm_color_lut *entry =
 704                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 705
 706                 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
 707                                ilk_lut_10(entry));
 708         }
 709
 710         /*
 711          * Reset the index, otherwise it prevents the legacy palette to be
 712          * written properly.
 713          */
 714         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
 715 }
 716
 717 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
 718 {
 719         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 720         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 721         enum pipe pipe = crtc->pipe;
 722
 723         /* Program the max register to clamp values > 1.0. */
 724         intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
 725         intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
 726         intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
 727
 728         /*
 729          * Program the gc max 2 register to clamp values > 1.0.
 730          * ToDo: Extend the ABI to be able to program values
 731          * from 3.0 to 7.0
 732          */
 733         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 734                 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
 735                                     1 << 16);
 736                 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
 737                                     1 << 16);
 738                 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2),
 739                                     1 << 16);
 740         }
 741 }
 742
 743 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 744 {
 745         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 746         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 747         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 748
 749         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 750                 ilk_load_lut_8(crtc, gamma_lut);
 751         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 752                 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 753                                 PAL_PREC_INDEX_VALUE(0));
 754                 ivb_load_lut_ext_max(crtc_state);
 755                 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 756                                 PAL_PREC_INDEX_VALUE(512));
 757         } else {
 758                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 759
 760                 ivb_load_lut_10(crtc, blob,
 761                                 PAL_PREC_INDEX_VALUE(0));
 762                 ivb_load_lut_ext_max(crtc_state);
 763         }
 764 }
 765
 766 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 767 {
 768         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 769         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 770         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 771
 772         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 773                 ilk_load_lut_8(crtc, gamma_lut);
 774         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 775                 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 776                                 PAL_PREC_INDEX_VALUE(0));
 777                 ivb_load_lut_ext_max(crtc_state);
 778                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 779                                 PAL_PREC_INDEX_VALUE(512));
 780         } else {
 781                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 782
 783                 bdw_load_lut_10(crtc, blob,
 784                                 PAL_PREC_INDEX_VALUE(0));
 785                 ivb_load_lut_ext_max(crtc_state);
 786         }
 787 }
 788
 789 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 790 {
 791         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 792         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 793         enum pipe pipe = crtc->pipe;
 794         int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 795         const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
 796
 797         /*
 798          * When setting the auto-increment bit, the hardware seems to
 799          * ignore the index bits, so we need to reset it to index 0
 800          * separately.
 801          */
 802         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
 803         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
 804                        PRE_CSC_GAMC_AUTO_INCREMENT);
 805
 806         for (i = 0; i < lut_size; i++) {
 807                 /*
 808                  * First 33 entries represent range from 0 to 1.0
 809                  * 34th and 35th entry will represent extended range
 810                  * inputs 3.0 and 7.0 respectively, currently clamped
 811                  * at 1.0. Since the precision is 16bit, the user
 812                  * value can be directly filled to register.
 813                  * The pipe degamma table in GLK+ onwards doesn't
 814                  * support different values per channel, so this just
 815                  * programs green value which will be equal to Red and
 816                  * Blue into the lut registers.
 817                  * ToDo: Extend to max 7.0. Enable 32 bit input value
 818                  * as compared to just 16 to achieve this.
 819                  */
 820                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe),
 821                                lut[i].green);
 822         }
 823
 824         /* Clamp values > 1.0. */
 825         while (i++ < 35)
 826                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 827 }
 828
 829 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
 830 {
 831         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 832         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 833         enum pipe pipe = crtc->pipe;
 834         int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 835
 836         /*
 837          * When setting the auto-increment bit, the hardware seems to
 838          * ignore the index bits, so we need to reset it to index 0
 839          * separately.
 840          */
 841         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
 842         intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
 843                        PRE_CSC_GAMC_AUTO_INCREMENT);
 844
 845         for (i = 0; i < lut_size; i++) {
 846                 u32 v = (i << 16) / (lut_size - 1);
 847
 848                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v);
 849         }
 850
 851         /* Clamp values > 1.0. */
 852         while (i++ < 35)
 853                 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 854 }
 855
 856 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 857 {
 858         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 859         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 860
 861         /*
 862          * On GLK+ both pipe CSC and degamma LUT are controlled
 863          * by csc_enable. Hence for the cases where the CSC is
 864          * needed but degamma LUT is not we need to load a
 865          * linear degamma LUT. In fact we'll just always load
 866          * the degama LUT so that we don't have to reload
 867          * it every time the pipe CSC is being enabled.
 868          */
 869         if (crtc_state->hw.degamma_lut)
 870                 glk_load_degamma_lut(crtc_state);
 871         else
 872                 glk_load_degamma_lut_linear(crtc_state);
 873
 874         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 875                 ilk_load_lut_8(crtc, gamma_lut);
 876         } else {
 877                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 878                 ivb_load_lut_ext_max(crtc_state);
 879         }
 880 }
 881
 882 /* ilk+ "12.4" interpolated format (high 10 bits) */
 883 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
 884 {
 885         return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
 886                 (color->blue >> 6);
 887 }
 888
 889 /* ilk+ "12.4" interpolated format (low 6 bits) */
 890 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 891 {
 892         return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
 893                 (color->blue & 0x3f) << 4;
 894 }
 895
 896 static void
 897 icl_load_gcmax(const struct intel_crtc_state *crtc_state,
 898                const struct drm_color_lut *color)
 899 {
 900         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 901         enum pipe pipe = crtc->pipe;
 902
 903         /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
 904         intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
 905         intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
 906         intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
 907 }
 908
 909 static void
 910 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 911 {
 912         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 913         const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 914         const struct drm_color_lut *lut = blob->data;
 915         enum pipe pipe = crtc->pipe;
 916         int i;
 917
 918         /*
 919          * Program Super Fine segment (let's call it seg1)...
 920          *
 921          * Super Fine segment's step is 1/(8 * 128 * 256) and it has
 922          * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
 923          * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
 924          */
 925         intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
 926                             PAL_PREC_AUTO_INCREMENT);
 927
 928         for (i = 0; i < 9; i++) {
 929                 const struct drm_color_lut *entry = &lut[i];
 930
 931                 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
 932                                             ilk_lut_12p4_ldw(entry));
 933                 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
 934                                             ilk_lut_12p4_udw(entry));
 935         }
 936 }
 937
 938 static void
 939 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 940 {
 941         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 942         const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 943         const struct drm_color_lut *lut = blob->data;
 944         const struct drm_color_lut *entry;
 945         enum pipe pipe = crtc->pipe;
 946         int i;
 947
 948         /*
 949          * Program Fine segment (let's call it seg2)...
 950          *
 951          * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
 952          * ... 256/(128 * 256). So in order to program fine segment of LUT we
 953          * need to pick every 8th entry in the LUT, and program 256 indexes.
 954          *
 955          * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
 956          * seg2[0] being unused by the hardware.
 957          */
 958         intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe),
 959                             PAL_PREC_AUTO_INCREMENT);
 960         for (i = 1; i < 257; i++) {
 961                 entry = &lut[i * 8];
 962                 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
 963                                             ilk_lut_12p4_ldw(entry));
 964                 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
 965                                             ilk_lut_12p4_udw(entry));
 966         }
 967
 968         /*
 969          * Program Coarse segment (let's call it seg3)...
 970          *
 971          * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
 972          * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
 973          * above, we need to pick every (8 * 128)th entry in LUT, and
 974          * program 256 of those.
 975          *
 976          * Spec is not very clear about if entries seg3[0] and seg3[1] are
 977          * being used or not, but we still need to program these to advance
 978          * the index.
 979          */
 980         for (i = 0; i < 256; i++) {
 981                 entry = &lut[i * 8 * 128];
 982                 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
 983                                             ilk_lut_12p4_ldw(entry));
 984                 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
 985                                             ilk_lut_12p4_udw(entry));
 986         }
 987
 988         /* The last entry in the LUT is to be programmed in GCMAX */
 989         entry = &lut[256 * 8 * 128];
 990         icl_load_gcmax(crtc_state, entry);
 991         ivb_load_lut_ext_max(crtc_state);
 992 }
 993
 994 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 995 {
 996         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 997         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 998
 999         if (crtc_state->hw.degamma_lut)
1000                 glk_load_degamma_lut(crtc_state);
1001
1002         switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
1003         case GAMMA_MODE_MODE_8BIT:
1004                 ilk_load_lut_8(crtc, gamma_lut);
1005                 break;
1006         case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1007                 icl_program_gamma_superfine_segment(crtc_state);
1008                 icl_program_gamma_multi_segment(crtc_state);
1009                 break;
1010         default:
1011                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
1012                 ivb_load_lut_ext_max(crtc_state);
1013         }
1014
1015         intel_dsb_commit(crtc_state);
1016 }
1017
1018 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
1019 {
1020         return drm_color_lut_extract(color->green, 14) << 16 |
1021                 drm_color_lut_extract(color->blue, 14);
1022 }
1023
1024 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
1025 {
1026         return drm_color_lut_extract(color->red, 14);
1027 }
1028
1029 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
1030 {
1031         entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
1032         entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
1033         entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
1034 }
1035
1036 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
1037                                  const struct drm_property_blob *blob)
1038 {
1039         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040         const struct drm_color_lut *lut = blob->data;
1041         int i, lut_size = drm_color_lut_size(blob);
1042         enum pipe pipe = crtc->pipe;
1043
1044         for (i = 0; i < lut_size; i++) {
1045                 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
1046                                chv_cgm_degamma_ldw(&lut[i]));
1047                 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
1048                                chv_cgm_degamma_udw(&lut[i]));
1049         }
1050 }
1051
1052 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
1053 {
1054         return drm_color_lut_extract(color->green, 10) << 16 |
1055                 drm_color_lut_extract(color->blue, 10);
1056 }
1057
1058 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
1059 {
1060         return drm_color_lut_extract(color->red, 10);
1061 }
1062
1063 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1064                                const struct drm_property_blob *blob)
1065 {
1066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067         const struct drm_color_lut *lut = blob->data;
1068         int i, lut_size = drm_color_lut_size(blob);
1069         enum pipe pipe = crtc->pipe;
1070
1071         for (i = 0; i < lut_size; i++) {
1072                 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
1073                                chv_cgm_gamma_ldw(&lut[i]));
1074                 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
1075                                chv_cgm_gamma_udw(&lut[i]));
1076         }
1077 }
1078
1079 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1080 {
1081         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1082         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1083         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1084         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1085         const struct drm_property_blob *ctm = crtc_state->hw.ctm;
1086
1087         if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
1088                 chv_load_cgm_csc(crtc, ctm);
1089
1090         if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
1091                 chv_load_cgm_degamma(crtc, degamma_lut);
1092
1093         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1094                 chv_load_cgm_gamma(crtc, gamma_lut);
1095         else
1096                 i965_load_luts(crtc_state);
1097
1098         intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
1099                        crtc_state->cgm_mode);
1100 }
1101
1102 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1103 {
1104         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1105
1106         dev_priv->display.load_luts(crtc_state);
1107 }
1108
1109 void intel_color_commit(const struct intel_crtc_state *crtc_state)
1110 {
1111         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1112
1113         dev_priv->display.color_commit(crtc_state);
1114 }
1115
1116 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1117 {
1118         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1119         struct intel_atomic_state *state =
1120                 to_intel_atomic_state(new_crtc_state->uapi.state);
1121         const struct intel_crtc_state *old_crtc_state =
1122                 intel_atomic_get_old_crtc_state(state, crtc);
1123
1124         return !old_crtc_state->hw.gamma_lut &&
1125                 !old_crtc_state->hw.degamma_lut;
1126 }
1127
1128 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1129 {
1130         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1131         struct intel_atomic_state *state =
1132                 to_intel_atomic_state(new_crtc_state->uapi.state);
1133         const struct intel_crtc_state *old_crtc_state =
1134                 intel_atomic_get_old_crtc_state(state, crtc);
1135
1136         /*
1137          * CGM_PIPE_MODE is itself single buffered. We'd have to
1138          * somehow split it out from chv_load_luts() if we wanted
1139          * the ability to preload the CGM LUTs/CSC without tearing.
1140          */
1141         if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1142                 return false;
1143
1144         return !old_crtc_state->hw.gamma_lut;
1145 }
1146
1147 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1148 {
1149         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1150         struct intel_atomic_state *state =
1151                 to_intel_atomic_state(new_crtc_state->uapi.state);
1152         const struct intel_crtc_state *old_crtc_state =
1153                 intel_atomic_get_old_crtc_state(state, crtc);
1154
1155         /*
1156          * The hardware degamma is active whenever the pipe
1157          * CSC is active. Thus even if the old state has no
1158          * software degamma we need to avoid clobbering the
1159          * linear hardware degamma mid scanout.
1160          */
1161         return !old_crtc_state->csc_enable &&
1162                 !old_crtc_state->hw.gamma_lut;
1163 }
1164
1165 int intel_color_check(struct intel_crtc_state *crtc_state)
1166 {
1167         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1168
1169         return dev_priv->display.color_check(crtc_state);
1170 }
1171
1172 void intel_color_get_config(struct intel_crtc_state *crtc_state)
1173 {
1174         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1175
1176         if (dev_priv->display.read_luts)
1177                 dev_priv->display.read_luts(crtc_state);
1178 }
1179
1180 static bool need_plane_update(struct intel_plane *plane,
1181                               const struct intel_crtc_state *crtc_state)
1182 {
1183         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1184
1185         /*
1186          * On pre-SKL the pipe gamma enable and pipe csc enable for
1187          * the pipe bottom color are configured via the primary plane.
1188          * We have to reconfigure that even if the plane is inactive.
1189          */
1190         return crtc_state->active_planes & BIT(plane->id) ||
1191                 (INTEL_GEN(dev_priv) < 9 &&
1192                  plane->id == PLANE_PRIMARY);
1193 }
1194
1195 static int
1196 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1197 {
1198         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1199         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1200         struct intel_atomic_state *state =
1201                 to_intel_atomic_state(new_crtc_state->uapi.state);
1202         const struct intel_crtc_state *old_crtc_state =
1203                 intel_atomic_get_old_crtc_state(state, crtc);
1204         struct intel_plane *plane;
1205
1206         if (!new_crtc_state->hw.active ||
1207             drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
1208                 return 0;
1209
1210         if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1211             new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1212                 return 0;
1213
1214         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1215                 struct intel_plane_state *plane_state;
1216
1217                 if (!need_plane_update(plane, new_crtc_state))
1218                         continue;
1219
1220                 plane_state = intel_atomic_get_plane_state(state, plane);
1221                 if (IS_ERR(plane_state))
1222                         return PTR_ERR(plane_state);
1223
1224                 new_crtc_state->update_planes |= BIT(plane->id);
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int check_lut_size(const struct drm_property_blob *lut, int expected)
1231 {
1232         int len;
1233
1234         if (!lut)
1235                 return 0;
1236
1237         len = drm_color_lut_size(lut);
1238         if (len != expected) {
1239                 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1240                               len, expected);
1241                 return -EINVAL;
1242         }
1243
1244         return 0;
1245 }
1246
1247 static int check_luts(const struct intel_crtc_state *crtc_state)
1248 {
1249         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1250         const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1251         const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1252         int gamma_length, degamma_length;
1253         u32 gamma_tests, degamma_tests;
1254
1255         /* Always allow legacy gamma LUT with no further checking. */
1256         if (crtc_state_is_legacy_gamma(crtc_state))
1257                 return 0;
1258
1259         /* C8 relies on its palette being stored in the legacy LUT */
1260         if (crtc_state->c8_planes) {
1261                 drm_dbg_kms(&dev_priv->drm,
1262                             "C8 pixelformat requires the legacy LUT\n");
1263                 return -EINVAL;
1264         }
1265
1266         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1267         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1268         degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1269         gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1270
1271         if (check_lut_size(degamma_lut, degamma_length) ||
1272             check_lut_size(gamma_lut, gamma_length))
1273                 return -EINVAL;
1274
1275         if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1276             drm_color_lut_check(gamma_lut, gamma_tests))
1277                 return -EINVAL;
1278
1279         return 0;
1280 }
1281
1282 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1283 {
1284         if (!crtc_state->gamma_enable ||
1285             crtc_state_is_legacy_gamma(crtc_state))
1286                 return GAMMA_MODE_MODE_8BIT;
1287         else
1288                 return GAMMA_MODE_MODE_10BIT; /* i965+ only */
1289 }
1290
1291 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1292 {
1293         int ret;
1294
1295         ret = check_luts(crtc_state);
1296         if (ret)
1297                 return ret;
1298
1299         crtc_state->gamma_enable =
1300                 crtc_state->hw.gamma_lut &&
1301                 !crtc_state->c8_planes;
1302
1303         crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1304
1305         ret = intel_color_add_affected_planes(crtc_state);
1306         if (ret)
1307                 return ret;
1308
1309         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1310
1311         return 0;
1312 }
1313
1314 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1315 {
1316         u32 cgm_mode = 0;
1317
1318         if (crtc_state_is_legacy_gamma(crtc_state))
1319                 return 0;
1320
1321         if (crtc_state->hw.degamma_lut)
1322                 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1323         if (crtc_state->hw.ctm)
1324                 cgm_mode |= CGM_PIPE_MODE_CSC;
1325         if (crtc_state->hw.gamma_lut)
1326                 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1327
1328         return cgm_mode;
1329 }
1330
1331 /*
1332  * CHV color pipeline:
1333  * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
1334  * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
1335  *
1336  * We always bypass the WGC csc and use the CGM csc
1337  * instead since it has degamma and better precision.
1338  */
1339 static int chv_color_check(struct intel_crtc_state *crtc_state)
1340 {
1341         int ret;
1342
1343         ret = check_luts(crtc_state);
1344         if (ret)
1345                 return ret;
1346
1347         /*
1348          * Pipe gamma will be used only for the legacy LUT.
1349          * Otherwise we bypass it and use the CGM gamma instead.
1350          */
1351         crtc_state->gamma_enable =
1352                 crtc_state_is_legacy_gamma(crtc_state) &&
1353                 !crtc_state->c8_planes;
1354
1355         crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1356
1357         crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1358
1359         ret = intel_color_add_affected_planes(crtc_state);
1360         if (ret)
1361                 return ret;
1362
1363         crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
1364
1365         return 0;
1366 }
1367
1368 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1369 {
1370         if (!crtc_state->gamma_enable ||
1371             crtc_state_is_legacy_gamma(crtc_state))
1372                 return GAMMA_MODE_MODE_8BIT;
1373         else
1374                 return GAMMA_MODE_MODE_10BIT;
1375 }
1376
1377 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1378 {
1379         /*
1380          * CSC comes after the LUT in RGB->YCbCr mode.
1381          * RGB->YCbCr needs the limited range offsets added to
1382          * the output. RGB limited range output is handled by
1383          * the hw automagically elsewhere.
1384          */
1385         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1386                 return CSC_BLACK_SCREEN_OFFSET;
1387
1388         return CSC_MODE_YUV_TO_RGB |
1389                 CSC_POSITION_BEFORE_GAMMA;
1390 }
1391
1392 static int ilk_color_check(struct intel_crtc_state *crtc_state)
1393 {
1394         int ret;
1395
1396         ret = check_luts(crtc_state);
1397         if (ret)
1398                 return ret;
1399
1400         crtc_state->gamma_enable =
1401                 crtc_state->hw.gamma_lut &&
1402                 !crtc_state->c8_planes;
1403
1404         /*
1405          * We don't expose the ctm on ilk/snb currently, also RGB
1406          * limited range output is handled by the hw automagically.
1407          */
1408         crtc_state->csc_enable =
1409                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1410
1411         crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1412
1413         crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1414
1415         ret = intel_color_add_affected_planes(crtc_state);
1416         if (ret)
1417                 return ret;
1418
1419         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1420
1421         return 0;
1422 }
1423
1424 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1425 {
1426         if (!crtc_state->gamma_enable ||
1427             crtc_state_is_legacy_gamma(crtc_state))
1428                 return GAMMA_MODE_MODE_8BIT;
1429         else if (crtc_state->hw.gamma_lut &&
1430                  crtc_state->hw.degamma_lut)
1431                 return GAMMA_MODE_MODE_SPLIT;
1432         else
1433                 return GAMMA_MODE_MODE_10BIT;
1434 }
1435
1436 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1437 {
1438         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1439
1440         /*
1441          * CSC comes after the LUT in degamma, RGB->YCbCr,
1442          * and RGB full->limited range mode.
1443          */
1444         if (crtc_state->hw.degamma_lut ||
1445             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1446             limited_color_range)
1447                 return 0;
1448
1449         return CSC_POSITION_BEFORE_GAMMA;
1450 }
1451
1452 static int ivb_color_check(struct intel_crtc_state *crtc_state)
1453 {
1454         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1455         int ret;
1456
1457         ret = check_luts(crtc_state);
1458         if (ret)
1459                 return ret;
1460
1461         crtc_state->gamma_enable =
1462                 (crtc_state->hw.gamma_lut ||
1463                  crtc_state->hw.degamma_lut) &&
1464                 !crtc_state->c8_planes;
1465
1466         crtc_state->csc_enable =
1467                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1468                 crtc_state->hw.ctm || limited_color_range;
1469
1470         crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1471
1472         crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1473
1474         ret = intel_color_add_affected_planes(crtc_state);
1475         if (ret)
1476                 return ret;
1477
1478         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1479
1480         return 0;
1481 }
1482
1483 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1484 {
1485         if (!crtc_state->gamma_enable ||
1486             crtc_state_is_legacy_gamma(crtc_state))
1487                 return GAMMA_MODE_MODE_8BIT;
1488         else
1489                 return GAMMA_MODE_MODE_10BIT;
1490 }
1491
1492 static int glk_color_check(struct intel_crtc_state *crtc_state)
1493 {
1494         int ret;
1495
1496         ret = check_luts(crtc_state);
1497         if (ret)
1498                 return ret;
1499
1500         crtc_state->gamma_enable =
1501                 crtc_state->hw.gamma_lut &&
1502                 !crtc_state->c8_planes;
1503
1504         /* On GLK+ degamma LUT is controlled by csc_enable */
1505         crtc_state->csc_enable =
1506                 crtc_state->hw.degamma_lut ||
1507                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1508                 crtc_state->hw.ctm || crtc_state->limited_color_range;
1509
1510         crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1511
1512         crtc_state->csc_mode = 0;
1513
1514         ret = intel_color_add_affected_planes(crtc_state);
1515         if (ret)
1516                 return ret;
1517
1518         crtc_state->preload_luts = glk_can_preload_luts(crtc_state);
1519
1520         return 0;
1521 }
1522
1523 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1524 {
1525         u32 gamma_mode = 0;
1526
1527         if (crtc_state->hw.degamma_lut)
1528                 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1529
1530         if (crtc_state->hw.gamma_lut &&
1531             !crtc_state->c8_planes)
1532                 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1533
1534         if (!crtc_state->hw.gamma_lut ||
1535             crtc_state_is_legacy_gamma(crtc_state))
1536                 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1537         else
1538                 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1539
1540         return gamma_mode;
1541 }
1542
1543 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1544 {
1545         u32 csc_mode = 0;
1546
1547         if (crtc_state->hw.ctm)
1548                 csc_mode |= ICL_CSC_ENABLE;
1549
1550         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1551             crtc_state->limited_color_range)
1552                 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1553
1554         return csc_mode;
1555 }
1556
1557 static int icl_color_check(struct intel_crtc_state *crtc_state)
1558 {
1559         int ret;
1560
1561         ret = check_luts(crtc_state);
1562         if (ret)
1563                 return ret;
1564
1565         crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1566
1567         crtc_state->csc_mode = icl_csc_mode(crtc_state);
1568
1569         crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1570
1571         return 0;
1572 }
1573
1574 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1575 {
1576         if (!crtc_state->gamma_enable)
1577                 return 0;
1578
1579         switch (crtc_state->gamma_mode) {
1580         case GAMMA_MODE_MODE_8BIT:
1581                 return 8;
1582         case GAMMA_MODE_MODE_10BIT:
1583                 return 16;
1584         default:
1585                 MISSING_CASE(crtc_state->gamma_mode);
1586                 return 0;
1587         }
1588 }
1589
1590 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1591 {
1592         if (!crtc_state->gamma_enable)
1593                 return 0;
1594
1595         if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1596                 return 0;
1597
1598         switch (crtc_state->gamma_mode) {
1599         case GAMMA_MODE_MODE_8BIT:
1600                 return 8;
1601         case GAMMA_MODE_MODE_10BIT:
1602                 return 10;
1603         default:
1604                 MISSING_CASE(crtc_state->gamma_mode);
1605                 return 0;
1606         }
1607 }
1608
1609 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1610 {
1611         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1612                 return 10;
1613         else
1614                 return i9xx_gamma_precision(crtc_state);
1615 }
1616
1617 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1618 {
1619         if (!crtc_state->gamma_enable)
1620                 return 0;
1621
1622         switch (crtc_state->gamma_mode) {
1623         case GAMMA_MODE_MODE_8BIT:
1624                 return 8;
1625         case GAMMA_MODE_MODE_10BIT:
1626                 return 10;
1627         default:
1628                 MISSING_CASE(crtc_state->gamma_mode);
1629                 return 0;
1630         }
1631 }
1632
1633 static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
1634 {
1635         if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
1636                 return 0;
1637
1638         switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
1639         case GAMMA_MODE_MODE_8BIT:
1640                 return 8;
1641         case GAMMA_MODE_MODE_10BIT:
1642                 return 10;
1643         case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1644                 return 16;
1645         default:
1646                 MISSING_CASE(crtc_state->gamma_mode);
1647                 return 0;
1648         }
1649 }
1650
1651 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1652 {
1653         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1654         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1655
1656         if (HAS_GMCH(dev_priv)) {
1657                 if (IS_CHERRYVIEW(dev_priv))
1658                         return chv_gamma_precision(crtc_state);
1659                 else
1660                         return i9xx_gamma_precision(crtc_state);
1661         } else {
1662                 if (INTEL_GEN(dev_priv) >= 11)
1663                         return icl_gamma_precision(crtc_state);
1664                 else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1665                         return glk_gamma_precision(crtc_state);
1666                 else if (IS_IRONLAKE(dev_priv))
1667                         return ilk_gamma_precision(crtc_state);
1668         }
1669
1670         return 0;
1671 }
1672
1673 static bool err_check(struct drm_color_lut *lut1,
1674                       struct drm_color_lut *lut2, u32 err)
1675 {
1676         return ((abs((long)lut2->red - lut1->red)) <= err) &&
1677                 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1678                 ((abs((long)lut2->green - lut1->green)) <= err);
1679 }
1680
1681 static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1,
1682                                           struct drm_color_lut *lut2,
1683                                           int lut_size, u32 err)
1684 {
1685         int i;
1686
1687         for (i = 0; i < lut_size; i++) {
1688                 if (!err_check(&lut1[i], &lut2[i], err))
1689                         return false;
1690         }
1691
1692         return true;
1693 }
1694
1695 bool intel_color_lut_equal(struct drm_property_blob *blob1,
1696                            struct drm_property_blob *blob2,
1697                            u32 gamma_mode, u32 bit_precision)
1698 {
1699         struct drm_color_lut *lut1, *lut2;
1700         int lut_size1, lut_size2;
1701         u32 err;
1702
1703         if (!blob1 != !blob2)
1704                 return false;
1705
1706         if (!blob1)
1707                 return true;
1708
1709         lut_size1 = drm_color_lut_size(blob1);
1710         lut_size2 = drm_color_lut_size(blob2);
1711
1712         /* check sw and hw lut size */
1713         if (lut_size1 != lut_size2)
1714                 return false;
1715
1716         lut1 = blob1->data;
1717         lut2 = blob2->data;
1718
1719         err = 0xffff >> bit_precision;
1720
1721         /* check sw and hw lut entry to be equal */
1722         switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
1723         case GAMMA_MODE_MODE_8BIT:
1724         case GAMMA_MODE_MODE_10BIT:
1725                 if (!intel_color_lut_entries_equal(lut1, lut2,
1726                                                    lut_size2, err))
1727                         return false;
1728                 break;
1729         case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1730                 if (!intel_color_lut_entries_equal(lut1, lut2,
1731                                                    9, err))
1732                         return false;
1733                 break;
1734         default:
1735                 MISSING_CASE(gamma_mode);
1736                         return false;
1737         }
1738
1739         return true;
1740 }
1741
1742 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
1743 {
1744         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1745         enum pipe pipe = crtc->pipe;
1746         struct drm_property_blob *blob;
1747         struct drm_color_lut *lut;
1748         int i;
1749
1750         blob = drm_property_create_blob(&dev_priv->drm,
1751                                         sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1752                                         NULL);
1753         if (IS_ERR(blob))
1754                 return NULL;
1755
1756         lut = blob->data;
1757
1758         for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1759                 u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
1760
1761                 i9xx_lut_8_pack(&lut[i], val);
1762         }
1763
1764         return blob;
1765 }
1766
1767 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1768 {
1769         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1770
1771         if (!crtc_state->gamma_enable)
1772                 return;
1773
1774         crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1775 }
1776
1777 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
1778 {
1779         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1780         int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1781         enum pipe pipe = crtc->pipe;
1782         struct drm_property_blob *blob;
1783         struct drm_color_lut *lut;
1784
1785         blob = drm_property_create_blob(&dev_priv->drm,
1786                                         sizeof(struct drm_color_lut) * lut_size,
1787                                         NULL);
1788         if (IS_ERR(blob))
1789                 return NULL;
1790
1791         lut = blob->data;
1792
1793         for (i = 0; i < lut_size - 1; i++) {
1794                 u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
1795                 u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
1796
1797                 i965_lut_10p6_pack(&lut[i], ldw, udw);
1798         }
1799
1800         lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
1801         lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
1802         lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
1803
1804         return blob;
1805 }
1806
1807 static void i965_read_luts(struct intel_crtc_state *crtc_state)
1808 {
1809         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1810
1811         if (!crtc_state->gamma_enable)
1812                 return;
1813
1814         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1815                 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1816         else
1817                 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
1818 }
1819
1820 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
1821 {
1822         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823         int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1824         enum pipe pipe = crtc->pipe;
1825         struct drm_property_blob *blob;
1826         struct drm_color_lut *lut;
1827
1828         blob = drm_property_create_blob(&dev_priv->drm,
1829                                         sizeof(struct drm_color_lut) * lut_size,
1830                                         NULL);
1831         if (IS_ERR(blob))
1832                 return NULL;
1833
1834         lut = blob->data;
1835
1836         for (i = 0; i < lut_size; i++) {
1837                 u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
1838                 u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
1839
1840                 chv_cgm_gamma_pack(&lut[i], ldw, udw);
1841         }
1842
1843         return blob;
1844 }
1845
1846 static void chv_read_luts(struct intel_crtc_state *crtc_state)
1847 {
1848         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1849
1850         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1851                 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
1852         else
1853                 i965_read_luts(crtc_state);
1854 }
1855
1856 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
1857 {
1858         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859         enum pipe pipe = crtc->pipe;
1860         struct drm_property_blob *blob;
1861         struct drm_color_lut *lut;
1862         int i;
1863
1864         blob = drm_property_create_blob(&dev_priv->drm,
1865                                         sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1866                                         NULL);
1867         if (IS_ERR(blob))
1868                 return NULL;
1869
1870         lut = blob->data;
1871
1872         for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1873                 u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
1874
1875                 i9xx_lut_8_pack(&lut[i], val);
1876         }
1877
1878         return blob;
1879 }
1880
1881 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
1882 {
1883         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1884         int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1885         enum pipe pipe = crtc->pipe;
1886         struct drm_property_blob *blob;
1887         struct drm_color_lut *lut;
1888
1889         blob = drm_property_create_blob(&dev_priv->drm,
1890                                         sizeof(struct drm_color_lut) * lut_size,
1891                                         NULL);
1892         if (IS_ERR(blob))
1893                 return NULL;
1894
1895         lut = blob->data;
1896
1897         for (i = 0; i < lut_size; i++) {
1898                 u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
1899
1900                 ilk_lut_10_pack(&lut[i], val);
1901         }
1902
1903         return blob;
1904 }
1905
1906 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1907 {
1908         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1909
1910         if (!crtc_state->gamma_enable)
1911                 return;
1912
1913         if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1914                 return;
1915
1916         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1917                 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
1918         else
1919                 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
1920 }
1921
1922 static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
1923                                                  u32 prec_index)
1924 {
1925         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1926         int i, hw_lut_size = ivb_lut_10_size(prec_index);
1927         enum pipe pipe = crtc->pipe;
1928         struct drm_property_blob *blob;
1929         struct drm_color_lut *lut;
1930
1931         blob = drm_property_create_blob(&dev_priv->drm,
1932                                         sizeof(struct drm_color_lut) * hw_lut_size,
1933                                         NULL);
1934         if (IS_ERR(blob))
1935                 return NULL;
1936
1937         lut = blob->data;
1938
1939         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
1940                        prec_index | PAL_PREC_AUTO_INCREMENT);
1941
1942         for (i = 0; i < hw_lut_size; i++) {
1943                 u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
1944
1945                 ilk_lut_10_pack(&lut[i], val);
1946         }
1947
1948         intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
1949
1950         return blob;
1951 }
1952
1953 static void glk_read_luts(struct intel_crtc_state *crtc_state)
1954 {
1955         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1956
1957         if (!crtc_state->gamma_enable)
1958                 return;
1959
1960         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1961                 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
1962         else
1963                 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
1964 }
1965
1966 static struct drm_property_blob *
1967 icl_read_lut_multi_segment(struct intel_crtc *crtc)
1968 {
1969         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1970         int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1971         enum pipe pipe = crtc->pipe;
1972         struct drm_property_blob *blob;
1973         struct drm_color_lut *lut;
1974
1975         blob = drm_property_create_blob(&dev_priv->drm,
1976                                         sizeof(struct drm_color_lut) * lut_size,
1977                                         NULL);
1978         if (IS_ERR(blob))
1979                 return NULL;
1980
1981         lut = blob->data;
1982
1983         intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe),
1984                        PAL_PREC_AUTO_INCREMENT);
1985
1986         for (i = 0; i < 9; i++) {
1987                 u32 ldw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
1988                 u32 udw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe));
1989
1990                 icl_lut_multi_seg_pack(&lut[i], ldw, udw);
1991         }
1992
1993         intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0);
1994
1995         /*
1996          * FIXME readouts from PAL_PREC_DATA register aren't giving
1997          * correct values in the case of fine and coarse segments.
1998          * Restricting readouts only for super fine segment as of now.
1999          */
2000
2001         return blob;
2002 }
2003
2004 static void icl_read_luts(struct intel_crtc_state *crtc_state)
2005 {
2006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2007
2008         if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
2009                 return;
2010
2011         switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
2012         case GAMMA_MODE_MODE_8BIT:
2013                 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
2014                 break;
2015         case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
2016                 crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc);
2017                 break;
2018         default:
2019                 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
2020         }
2021 }
2022
2023 void intel_color_init(struct intel_crtc *crtc)
2024 {
2025         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2026         bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
2027
2028         drm_mode_crtc_set_gamma_size(&crtc->base, 256);
2029
2030         if (HAS_GMCH(dev_priv)) {
2031                 if (IS_CHERRYVIEW(dev_priv)) {
2032                         dev_priv->display.color_check = chv_color_check;
2033                         dev_priv->display.color_commit = i9xx_color_commit;
2034                         dev_priv->display.load_luts = chv_load_luts;
2035                         dev_priv->display.read_luts = chv_read_luts;
2036                 } else if (INTEL_GEN(dev_priv) >= 4) {
2037                         dev_priv->display.color_check = i9xx_color_check;
2038                         dev_priv->display.color_commit = i9xx_color_commit;
2039                         dev_priv->display.load_luts = i965_load_luts;
2040                         dev_priv->display.read_luts = i965_read_luts;
2041                 } else {
2042                         dev_priv->display.color_check = i9xx_color_check;
2043                         dev_priv->display.color_commit = i9xx_color_commit;
2044                         dev_priv->display.load_luts = i9xx_load_luts;
2045                         dev_priv->display.read_luts = i9xx_read_luts;
2046                 }
2047         } else {
2048                 if (INTEL_GEN(dev_priv) >= 11)
2049                         dev_priv->display.color_check = icl_color_check;
2050                 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2051                         dev_priv->display.color_check = glk_color_check;
2052                 else if (INTEL_GEN(dev_priv) >= 7)
2053                         dev_priv->display.color_check = ivb_color_check;
2054                 else
2055                         dev_priv->display.color_check = ilk_color_check;
2056
2057                 if (INTEL_GEN(dev_priv) >= 9)
2058                         dev_priv->display.color_commit = skl_color_commit;
2059                 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2060                         dev_priv->display.color_commit = hsw_color_commit;
2061                 else
2062                         dev_priv->display.color_commit = ilk_color_commit;
2063
2064                 if (INTEL_GEN(dev_priv) >= 11) {
2065                         dev_priv->display.load_luts = icl_load_luts;
2066                         dev_priv->display.read_luts = icl_read_luts;
2067                 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2068                         dev_priv->display.load_luts = glk_load_luts;
2069                         dev_priv->display.read_luts = glk_read_luts;
2070                 } else if (INTEL_GEN(dev_priv) >= 8) {
2071                         dev_priv->display.load_luts = bdw_load_luts;
2072                 } else if (INTEL_GEN(dev_priv) >= 7) {
2073                         dev_priv->display.load_luts = ivb_load_luts;
2074                 } else {
2075                         dev_priv->display.load_luts = ilk_load_luts;
2076                         dev_priv->display.read_luts = ilk_read_luts;
2077                 }
2078         }
2079
2080         drm_crtc_enable_color_mgmt(&crtc->base,
2081                                    INTEL_INFO(dev_priv)->color.degamma_lut_size,
2082                                    has_ctm,
2083                                    INTEL_INFO(dev_priv)->color.gamma_lut_size);
2084 }