2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_cdclk.h"
25 #include "intel_drv.h"
26 #include "intel_sideband.h"
31 * The display engine uses several different clocks to do its work. There
32 * are two main clocks involved that aren't directly related to the actual
33 * pixel clock or any symbol/bit clock of the actual output port. These
34 * are the core display clock (CDCLK) and RAWCLK.
36 * CDCLK clocks most of the display pipe logic, and thus its frequency
37 * must be high enough to support the rate at which pixels are flowing
38 * through the pipes. Downscaling must also be accounted as that increases
39 * the effective pixel rate.
41 * On several platforms the CDCLK frequency can be changed dynamically
42 * to minimize power consumption for a given display configuration.
43 * Typically changes to the CDCLK frequency require all the display pipes
44 * to be shut down while the frequency is being changed.
46 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
47 * DMC will not change the active CDCLK frequency however, so that part
48 * will still be performed by the driver directly.
50 * RAWCLK is a fixed frequency clock, often used by various auxiliary
51 * blocks such as AUX CH or backlight PWM. Hence the only thing we
52 * really need to know about RAWCLK is its frequency so that various
53 * dividers can be programmed correctly.
56 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
57 struct intel_cdclk_state *cdclk_state)
59 cdclk_state->cdclk = 133333;
62 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
63 struct intel_cdclk_state *cdclk_state)
65 cdclk_state->cdclk = 200000;
68 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
69 struct intel_cdclk_state *cdclk_state)
71 cdclk_state->cdclk = 266667;
74 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
75 struct intel_cdclk_state *cdclk_state)
77 cdclk_state->cdclk = 333333;
80 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
81 struct intel_cdclk_state *cdclk_state)
83 cdclk_state->cdclk = 400000;
86 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
87 struct intel_cdclk_state *cdclk_state)
89 cdclk_state->cdclk = 450000;
92 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
93 struct intel_cdclk_state *cdclk_state)
95 struct pci_dev *pdev = dev_priv->drm.pdev;
99 * 852GM/852GMV only supports 133 MHz and the HPLLCC
100 * encoding is different :(
101 * FIXME is this the right way to detect 852GM/852GMV?
103 if (pdev->revision == 0x1) {
104 cdclk_state->cdclk = 133333;
108 pci_bus_read_config_word(pdev->bus,
109 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
111 /* Assume that the hardware is in the high speed state. This
112 * should be the default.
114 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
115 case GC_CLOCK_133_200:
116 case GC_CLOCK_133_200_2:
117 case GC_CLOCK_100_200:
118 cdclk_state->cdclk = 200000;
120 case GC_CLOCK_166_250:
121 cdclk_state->cdclk = 250000;
123 case GC_CLOCK_100_133:
124 cdclk_state->cdclk = 133333;
126 case GC_CLOCK_133_266:
127 case GC_CLOCK_133_266_2:
128 case GC_CLOCK_166_266:
129 cdclk_state->cdclk = 266667;
134 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
135 struct intel_cdclk_state *cdclk_state)
137 struct pci_dev *pdev = dev_priv->drm.pdev;
140 pci_read_config_word(pdev, GCFGC, &gcfgc);
142 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
143 cdclk_state->cdclk = 133333;
147 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
148 case GC_DISPLAY_CLOCK_333_320_MHZ:
149 cdclk_state->cdclk = 333333;
152 case GC_DISPLAY_CLOCK_190_200_MHZ:
153 cdclk_state->cdclk = 190000;
158 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
159 struct intel_cdclk_state *cdclk_state)
161 struct pci_dev *pdev = dev_priv->drm.pdev;
164 pci_read_config_word(pdev, GCFGC, &gcfgc);
166 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
167 cdclk_state->cdclk = 133333;
171 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
172 case GC_DISPLAY_CLOCK_333_320_MHZ:
173 cdclk_state->cdclk = 320000;
176 case GC_DISPLAY_CLOCK_190_200_MHZ:
177 cdclk_state->cdclk = 200000;
182 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
184 static const unsigned int blb_vco[8] = {
191 static const unsigned int pnv_vco[8] = {
198 static const unsigned int cl_vco[8] = {
207 static const unsigned int elk_vco[8] = {
213 static const unsigned int ctg_vco[8] = {
221 const unsigned int *vco_table;
225 /* FIXME other chipsets? */
226 if (IS_GM45(dev_priv))
228 else if (IS_G45(dev_priv))
230 else if (IS_I965GM(dev_priv))
232 else if (IS_PINEVIEW(dev_priv))
234 else if (IS_G33(dev_priv))
239 tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ?
240 HPLLVCO_MOBILE : HPLLVCO);
242 vco = vco_table[tmp & 0x7];
244 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
246 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
251 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
252 struct intel_cdclk_state *cdclk_state)
254 struct pci_dev *pdev = dev_priv->drm.pdev;
255 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
256 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
257 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
258 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
260 unsigned int cdclk_sel;
263 cdclk_state->vco = intel_hpll_vco(dev_priv);
265 pci_read_config_word(pdev, GCFGC, &tmp);
267 cdclk_sel = (tmp >> 4) & 0x7;
269 if (cdclk_sel >= ARRAY_SIZE(div_3200))
272 switch (cdclk_state->vco) {
274 div_table = div_3200;
277 div_table = div_4000;
280 div_table = div_4800;
283 div_table = div_5333;
289 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
290 div_table[cdclk_sel]);
294 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
295 cdclk_state->vco, tmp);
296 cdclk_state->cdclk = 190476;
299 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
300 struct intel_cdclk_state *cdclk_state)
302 struct pci_dev *pdev = dev_priv->drm.pdev;
305 pci_read_config_word(pdev, GCFGC, &gcfgc);
307 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
308 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
309 cdclk_state->cdclk = 266667;
311 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
312 cdclk_state->cdclk = 333333;
314 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
315 cdclk_state->cdclk = 444444;
317 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
318 cdclk_state->cdclk = 200000;
321 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
323 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
324 cdclk_state->cdclk = 133333;
326 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
327 cdclk_state->cdclk = 166667;
332 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
333 struct intel_cdclk_state *cdclk_state)
335 struct pci_dev *pdev = dev_priv->drm.pdev;
336 static const u8 div_3200[] = { 16, 10, 8 };
337 static const u8 div_4000[] = { 20, 12, 10 };
338 static const u8 div_5333[] = { 24, 16, 14 };
340 unsigned int cdclk_sel;
343 cdclk_state->vco = intel_hpll_vco(dev_priv);
345 pci_read_config_word(pdev, GCFGC, &tmp);
347 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
349 if (cdclk_sel >= ARRAY_SIZE(div_3200))
352 switch (cdclk_state->vco) {
354 div_table = div_3200;
357 div_table = div_4000;
360 div_table = div_5333;
366 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
367 div_table[cdclk_sel]);
371 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
372 cdclk_state->vco, tmp);
373 cdclk_state->cdclk = 200000;
376 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
377 struct intel_cdclk_state *cdclk_state)
379 struct pci_dev *pdev = dev_priv->drm.pdev;
380 unsigned int cdclk_sel;
383 cdclk_state->vco = intel_hpll_vco(dev_priv);
385 pci_read_config_word(pdev, GCFGC, &tmp);
387 cdclk_sel = (tmp >> 12) & 0x1;
389 switch (cdclk_state->vco) {
393 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
396 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
399 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
400 cdclk_state->vco, tmp);
401 cdclk_state->cdclk = 222222;
406 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
407 struct intel_cdclk_state *cdclk_state)
409 u32 lcpll = I915_READ(LCPLL_CTL);
410 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
412 if (lcpll & LCPLL_CD_SOURCE_FCLK)
413 cdclk_state->cdclk = 800000;
414 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
415 cdclk_state->cdclk = 450000;
416 else if (freq == LCPLL_CLK_FREQ_450)
417 cdclk_state->cdclk = 450000;
418 else if (IS_HSW_ULT(dev_priv))
419 cdclk_state->cdclk = 337500;
421 cdclk_state->cdclk = 540000;
424 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
426 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
430 * We seem to get an unstable or solid color picture at 200MHz.
431 * Not sure what's wrong. For now use 200MHz only when all pipes
434 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
436 else if (min_cdclk > 266667)
438 else if (min_cdclk > 0)
444 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
446 if (IS_VALLEYVIEW(dev_priv)) {
447 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
449 else if (cdclk >= 266667)
455 * Specs are full of misinformation, but testing on actual
456 * hardware has shown that we just need to write the desired
457 * CCK divider into the Punit register.
459 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
463 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
464 struct intel_cdclk_state *cdclk_state)
468 vlv_iosf_sb_get(dev_priv,
469 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
471 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
472 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
473 CCK_DISPLAY_CLOCK_CONTROL,
476 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
478 vlv_iosf_sb_put(dev_priv,
479 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
481 if (IS_VALLEYVIEW(dev_priv))
482 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
485 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
486 DSPFREQGUAR_SHIFT_CHV;
489 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
491 unsigned int credits, default_credits;
493 if (IS_CHERRYVIEW(dev_priv))
494 default_credits = PFI_CREDIT(12);
496 default_credits = PFI_CREDIT(8);
498 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
499 /* CHV suggested value is 31 or 63 */
500 if (IS_CHERRYVIEW(dev_priv))
501 credits = PFI_CREDIT_63;
503 credits = PFI_CREDIT(15);
505 credits = default_credits;
509 * WA - write default credits before re-programming
510 * FIXME: should we also set the resend bit here?
512 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
515 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
516 credits | PFI_CREDIT_RESEND);
519 * FIXME is this guaranteed to clear
520 * immediately or should we poll for it?
522 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
525 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
526 const struct intel_cdclk_state *cdclk_state,
529 int cdclk = cdclk_state->cdclk;
530 u32 val, cmd = cdclk_state->voltage_level;
531 intel_wakeref_t wakeref;
545 /* There are cases where we can end up here with power domains
546 * off and a CDCLK frequency other than the minimum, like when
547 * issuing a modeset without actually changing any display after
548 * a system suspend. So grab the PIPE-A domain, which covers
549 * the HW blocks needed for the following programming.
551 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
553 vlv_iosf_sb_get(dev_priv,
554 BIT(VLV_IOSF_SB_CCK) |
555 BIT(VLV_IOSF_SB_BUNIT) |
556 BIT(VLV_IOSF_SB_PUNIT));
558 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
559 val &= ~DSPFREQGUAR_MASK;
560 val |= (cmd << DSPFREQGUAR_SHIFT);
561 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
562 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
563 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
565 DRM_ERROR("timed out waiting for CDclk change\n");
568 if (cdclk == 400000) {
571 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
574 /* adjust cdclk divider */
575 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
576 val &= ~CCK_FREQUENCY_VALUES;
578 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
580 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
581 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
583 DRM_ERROR("timed out waiting for CDclk change\n");
586 /* adjust self-refresh exit latency value */
587 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
591 * For high bandwidth configs, we set a higher latency in the bunit
592 * so that the core display fetch happens in time to avoid underruns.
595 val |= 4500 / 250; /* 4.5 usec */
597 val |= 3000 / 250; /* 3.0 usec */
598 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
600 vlv_iosf_sb_put(dev_priv,
601 BIT(VLV_IOSF_SB_CCK) |
602 BIT(VLV_IOSF_SB_BUNIT) |
603 BIT(VLV_IOSF_SB_PUNIT));
605 intel_update_cdclk(dev_priv);
607 vlv_program_pfi_credits(dev_priv);
609 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
612 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
613 const struct intel_cdclk_state *cdclk_state,
616 int cdclk = cdclk_state->cdclk;
617 u32 val, cmd = cdclk_state->voltage_level;
618 intel_wakeref_t wakeref;
631 /* There are cases where we can end up here with power domains
632 * off and a CDCLK frequency other than the minimum, like when
633 * issuing a modeset without actually changing any display after
634 * a system suspend. So grab the PIPE-A domain, which covers
635 * the HW blocks needed for the following programming.
637 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
639 vlv_punit_get(dev_priv);
640 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
641 val &= ~DSPFREQGUAR_MASK_CHV;
642 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
643 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
644 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
645 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
647 DRM_ERROR("timed out waiting for CDclk change\n");
650 vlv_punit_put(dev_priv);
652 intel_update_cdclk(dev_priv);
654 vlv_program_pfi_credits(dev_priv);
656 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
659 static int bdw_calc_cdclk(int min_cdclk)
661 if (min_cdclk > 540000)
663 else if (min_cdclk > 450000)
665 else if (min_cdclk > 337500)
671 static u8 bdw_calc_voltage_level(int cdclk)
686 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
687 struct intel_cdclk_state *cdclk_state)
689 u32 lcpll = I915_READ(LCPLL_CTL);
690 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
692 if (lcpll & LCPLL_CD_SOURCE_FCLK)
693 cdclk_state->cdclk = 800000;
694 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
695 cdclk_state->cdclk = 450000;
696 else if (freq == LCPLL_CLK_FREQ_450)
697 cdclk_state->cdclk = 450000;
698 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
699 cdclk_state->cdclk = 540000;
700 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
701 cdclk_state->cdclk = 337500;
703 cdclk_state->cdclk = 675000;
706 * Can't read this out :( Let's assume it's
707 * at least what the CDCLK frequency requires.
709 cdclk_state->voltage_level =
710 bdw_calc_voltage_level(cdclk_state->cdclk);
713 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
714 const struct intel_cdclk_state *cdclk_state,
717 int cdclk = cdclk_state->cdclk;
721 if (WARN((I915_READ(LCPLL_CTL) &
722 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
723 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
724 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
725 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
726 "trying to change cdclk frequency with cdclk not enabled\n"))
729 ret = sandybridge_pcode_write(dev_priv,
730 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
732 DRM_ERROR("failed to inform pcode about cdclk change\n");
736 val = I915_READ(LCPLL_CTL);
737 val |= LCPLL_CD_SOURCE_FCLK;
738 I915_WRITE(LCPLL_CTL, val);
741 * According to the spec, it should be enough to poll for this 1 us.
742 * However, extensive testing shows that this can take longer.
744 if (wait_for_us(I915_READ(LCPLL_CTL) &
745 LCPLL_CD_SOURCE_FCLK_DONE, 100))
746 DRM_ERROR("Switching to FCLK failed\n");
748 val = I915_READ(LCPLL_CTL);
749 val &= ~LCPLL_CLK_FREQ_MASK;
756 val |= LCPLL_CLK_FREQ_337_5_BDW;
759 val |= LCPLL_CLK_FREQ_450;
762 val |= LCPLL_CLK_FREQ_54O_BDW;
765 val |= LCPLL_CLK_FREQ_675_BDW;
769 I915_WRITE(LCPLL_CTL, val);
771 val = I915_READ(LCPLL_CTL);
772 val &= ~LCPLL_CD_SOURCE_FCLK;
773 I915_WRITE(LCPLL_CTL, val);
775 if (wait_for_us((I915_READ(LCPLL_CTL) &
776 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
777 DRM_ERROR("Switching back to LCPLL failed\n");
779 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
780 cdclk_state->voltage_level);
782 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
784 intel_update_cdclk(dev_priv);
787 static int skl_calc_cdclk(int min_cdclk, int vco)
789 if (vco == 8640000) {
790 if (min_cdclk > 540000)
792 else if (min_cdclk > 432000)
794 else if (min_cdclk > 308571)
799 if (min_cdclk > 540000)
801 else if (min_cdclk > 450000)
803 else if (min_cdclk > 337500)
810 static u8 skl_calc_voltage_level(int cdclk)
814 else if (cdclk > 450000)
816 else if (cdclk > 337500)
822 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
823 struct intel_cdclk_state *cdclk_state)
827 cdclk_state->ref = 24000;
828 cdclk_state->vco = 0;
830 val = I915_READ(LCPLL1_CTL);
831 if ((val & LCPLL_PLL_ENABLE) == 0)
834 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
837 val = I915_READ(DPLL_CTRL1);
839 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
840 DPLL_CTRL1_SSC(SKL_DPLL0) |
841 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
842 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
845 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
846 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
847 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
848 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
849 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
850 cdclk_state->vco = 8100000;
852 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
853 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
854 cdclk_state->vco = 8640000;
857 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
862 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
863 struct intel_cdclk_state *cdclk_state)
867 skl_dpll0_update(dev_priv, cdclk_state);
869 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
871 if (cdclk_state->vco == 0)
874 cdctl = I915_READ(CDCLK_CTL);
876 if (cdclk_state->vco == 8640000) {
877 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
878 case CDCLK_FREQ_450_432:
879 cdclk_state->cdclk = 432000;
881 case CDCLK_FREQ_337_308:
882 cdclk_state->cdclk = 308571;
885 cdclk_state->cdclk = 540000;
887 case CDCLK_FREQ_675_617:
888 cdclk_state->cdclk = 617143;
891 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
895 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
896 case CDCLK_FREQ_450_432:
897 cdclk_state->cdclk = 450000;
899 case CDCLK_FREQ_337_308:
900 cdclk_state->cdclk = 337500;
903 cdclk_state->cdclk = 540000;
905 case CDCLK_FREQ_675_617:
906 cdclk_state->cdclk = 675000;
909 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
916 * Can't read this out :( Let's assume it's
917 * at least what the CDCLK frequency requires.
919 cdclk_state->voltage_level =
920 skl_calc_voltage_level(cdclk_state->cdclk);
923 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
924 static int skl_cdclk_decimal(int cdclk)
926 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
929 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
932 bool changed = dev_priv->skl_preferred_vco_freq != vco;
934 dev_priv->skl_preferred_vco_freq = vco;
937 intel_update_max_cdclk(dev_priv);
940 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
944 WARN_ON(vco != 8100000 && vco != 8640000);
947 * We always enable DPLL0 with the lowest link rate possible, but still
948 * taking into account the VCO required to operate the eDP panel at the
949 * desired frequency. The usual DP link rates operate with a VCO of
950 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
951 * The modeset code is responsible for the selection of the exact link
952 * rate later on, with the constraint of choosing a frequency that
955 val = I915_READ(DPLL_CTRL1);
957 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
958 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
959 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
961 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
964 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
967 I915_WRITE(DPLL_CTRL1, val);
968 POSTING_READ(DPLL_CTRL1);
970 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
972 if (intel_wait_for_register(&dev_priv->uncore,
973 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
975 DRM_ERROR("DPLL0 not locked\n");
977 dev_priv->cdclk.hw.vco = vco;
979 /* We'll want to keep using the current vco from now on. */
980 skl_set_preferred_cdclk_vco(dev_priv, vco);
983 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
985 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
986 if (intel_wait_for_register(&dev_priv->uncore,
987 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
989 DRM_ERROR("Couldn't disable DPLL0\n");
991 dev_priv->cdclk.hw.vco = 0;
994 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
995 const struct intel_cdclk_state *cdclk_state,
998 int cdclk = cdclk_state->cdclk;
999 int vco = cdclk_state->vco;
1000 u32 freq_select, cdclk_ctl;
1004 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1005 * unsupported on SKL. In theory this should never happen since only
1006 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1007 * supported on SKL either, see the above WA. WARN whenever trying to
1008 * use the corresponding VCO freq as that always leads to using the
1009 * minimum 308MHz CDCLK.
1011 WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1013 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1014 SKL_CDCLK_PREPARE_FOR_CHANGE,
1015 SKL_CDCLK_READY_FOR_CHANGE,
1016 SKL_CDCLK_READY_FOR_CHANGE, 3);
1018 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1023 /* Choose frequency for this cdclk */
1026 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1031 freq_select = CDCLK_FREQ_337_308;
1035 freq_select = CDCLK_FREQ_450_432;
1038 freq_select = CDCLK_FREQ_540;
1042 freq_select = CDCLK_FREQ_675_617;
1046 if (dev_priv->cdclk.hw.vco != 0 &&
1047 dev_priv->cdclk.hw.vco != vco)
1048 skl_dpll0_disable(dev_priv);
1050 cdclk_ctl = I915_READ(CDCLK_CTL);
1052 if (dev_priv->cdclk.hw.vco != vco) {
1053 /* Wa Display #1183: skl,kbl,cfl */
1054 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1055 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1056 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1059 /* Wa Display #1183: skl,kbl,cfl */
1060 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1061 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1062 POSTING_READ(CDCLK_CTL);
1064 if (dev_priv->cdclk.hw.vco != vco)
1065 skl_dpll0_enable(dev_priv, vco);
1067 /* Wa Display #1183: skl,kbl,cfl */
1068 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1069 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1071 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1072 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1074 /* Wa Display #1183: skl,kbl,cfl */
1075 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1076 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1077 POSTING_READ(CDCLK_CTL);
1079 /* inform PCU of the change */
1080 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1081 cdclk_state->voltage_level);
1083 intel_update_cdclk(dev_priv);
1086 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1088 u32 cdctl, expected;
1091 * check if the pre-os initialized the display
1092 * There is SWF18 scratchpad register defined which is set by the
1093 * pre-os which can be used by the OS drivers to check the status
1095 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1098 intel_update_cdclk(dev_priv);
1099 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1101 /* Is PLL enabled and locked ? */
1102 if (dev_priv->cdclk.hw.vco == 0 ||
1103 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1106 /* DPLL okay; verify the cdclock
1108 * Noticed in some instances that the freq selection is correct but
1109 * decimal part is programmed wrong from BIOS where pre-os does not
1110 * enable display. Verify the same as well.
1112 cdctl = I915_READ(CDCLK_CTL);
1113 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1114 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1115 if (cdctl == expected)
1116 /* All well; nothing to sanitize */
1120 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1122 /* force cdclk programming */
1123 dev_priv->cdclk.hw.cdclk = 0;
1124 /* force full PLL disable + enable */
1125 dev_priv->cdclk.hw.vco = -1;
1128 static void skl_init_cdclk(struct drm_i915_private *dev_priv)
1130 struct intel_cdclk_state cdclk_state;
1132 skl_sanitize_cdclk(dev_priv);
1134 if (dev_priv->cdclk.hw.cdclk != 0 &&
1135 dev_priv->cdclk.hw.vco != 0) {
1137 * Use the current vco as our initial
1138 * guess as to what the preferred vco is.
1140 if (dev_priv->skl_preferred_vco_freq == 0)
1141 skl_set_preferred_cdclk_vco(dev_priv,
1142 dev_priv->cdclk.hw.vco);
1146 cdclk_state = dev_priv->cdclk.hw;
1148 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1149 if (cdclk_state.vco == 0)
1150 cdclk_state.vco = 8100000;
1151 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1152 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1154 skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1157 static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1159 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1161 cdclk_state.cdclk = cdclk_state.bypass;
1162 cdclk_state.vco = 0;
1163 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1165 skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1168 static int bxt_calc_cdclk(int min_cdclk)
1170 if (min_cdclk > 576000)
1172 else if (min_cdclk > 384000)
1174 else if (min_cdclk > 288000)
1176 else if (min_cdclk > 144000)
1182 static int glk_calc_cdclk(int min_cdclk)
1184 if (min_cdclk > 158400)
1186 else if (min_cdclk > 79200)
1192 static u8 bxt_calc_voltage_level(int cdclk)
1194 return DIV_ROUND_UP(cdclk, 25000);
1197 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1201 if (cdclk == dev_priv->cdclk.hw.bypass)
1206 MISSING_CASE(cdclk);
1219 return dev_priv->cdclk.hw.ref * ratio;
1222 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1226 if (cdclk == dev_priv->cdclk.hw.bypass)
1231 MISSING_CASE(cdclk);
1240 return dev_priv->cdclk.hw.ref * ratio;
1243 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1244 struct intel_cdclk_state *cdclk_state)
1248 cdclk_state->ref = 19200;
1249 cdclk_state->vco = 0;
1251 val = I915_READ(BXT_DE_PLL_ENABLE);
1252 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1255 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1258 val = I915_READ(BXT_DE_PLL_CTL);
1259 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1262 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1263 struct intel_cdclk_state *cdclk_state)
1268 bxt_de_pll_update(dev_priv, cdclk_state);
1270 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1272 if (cdclk_state->vco == 0)
1275 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1278 case BXT_CDCLK_CD2X_DIV_SEL_1:
1281 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1282 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1285 case BXT_CDCLK_CD2X_DIV_SEL_2:
1288 case BXT_CDCLK_CD2X_DIV_SEL_4:
1292 MISSING_CASE(divider);
1296 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1300 * Can't read this out :( Let's assume it's
1301 * at least what the CDCLK frequency requires.
1303 cdclk_state->voltage_level =
1304 bxt_calc_voltage_level(cdclk_state->cdclk);
1307 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1309 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1312 if (intel_wait_for_register(&dev_priv->uncore,
1313 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1315 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1317 dev_priv->cdclk.hw.vco = 0;
1320 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1322 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1325 val = I915_READ(BXT_DE_PLL_CTL);
1326 val &= ~BXT_DE_PLL_RATIO_MASK;
1327 val |= BXT_DE_PLL_RATIO(ratio);
1328 I915_WRITE(BXT_DE_PLL_CTL, val);
1330 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1333 if (intel_wait_for_register(&dev_priv->uncore,
1338 DRM_ERROR("timeout waiting for DE PLL lock\n");
1340 dev_priv->cdclk.hw.vco = vco;
1343 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1344 const struct intel_cdclk_state *cdclk_state,
1347 int cdclk = cdclk_state->cdclk;
1348 int vco = cdclk_state->vco;
1352 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1353 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1355 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1359 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1362 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1363 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1366 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1369 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1374 * Inform power controller of upcoming frequency change. BSpec
1375 * requires us to wait up to 150usec, but that leads to timeouts;
1376 * the 2ms used here is based on experiment.
1378 ret = sandybridge_pcode_write_timeout(dev_priv,
1379 HSW_PCODE_DE_WRITE_FREQ_REQ,
1380 0x80000000, 150, 2);
1382 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1387 if (dev_priv->cdclk.hw.vco != 0 &&
1388 dev_priv->cdclk.hw.vco != vco)
1389 bxt_de_pll_disable(dev_priv);
1391 if (dev_priv->cdclk.hw.vco != vco)
1392 bxt_de_pll_enable(dev_priv, vco);
1394 val = divider | skl_cdclk_decimal(cdclk);
1395 if (pipe == INVALID_PIPE)
1396 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1398 val |= BXT_CDCLK_CD2X_PIPE(pipe);
1400 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1403 if (cdclk >= 500000)
1404 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1405 I915_WRITE(CDCLK_CTL, val);
1407 if (pipe != INVALID_PIPE)
1408 intel_wait_for_vblank(dev_priv, pipe);
1411 * The timeout isn't specified, the 2ms used here is based on
1413 * FIXME: Waiting for the request completion could be delayed until
1414 * the next PCODE request based on BSpec.
1416 ret = sandybridge_pcode_write_timeout(dev_priv,
1417 HSW_PCODE_DE_WRITE_FREQ_REQ,
1418 cdclk_state->voltage_level, 150, 2);
1420 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1425 intel_update_cdclk(dev_priv);
1428 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1430 u32 cdctl, expected;
1432 intel_update_cdclk(dev_priv);
1433 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1435 if (dev_priv->cdclk.hw.vco == 0 ||
1436 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1439 /* DPLL okay; verify the cdclock
1441 * Some BIOS versions leave an incorrect decimal frequency value and
1442 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1443 * so sanitize this register.
1445 cdctl = I915_READ(CDCLK_CTL);
1447 * Let's ignore the pipe field, since BIOS could have configured the
1448 * dividers both synching to an active pipe, or asynchronously
1451 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1453 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1454 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1456 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1459 if (dev_priv->cdclk.hw.cdclk >= 500000)
1460 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1462 if (cdctl == expected)
1463 /* All well; nothing to sanitize */
1467 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1469 /* force cdclk programming */
1470 dev_priv->cdclk.hw.cdclk = 0;
1472 /* force full PLL disable + enable */
1473 dev_priv->cdclk.hw.vco = -1;
1476 static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1478 struct intel_cdclk_state cdclk_state;
1480 bxt_sanitize_cdclk(dev_priv);
1482 if (dev_priv->cdclk.hw.cdclk != 0 &&
1483 dev_priv->cdclk.hw.vco != 0)
1486 cdclk_state = dev_priv->cdclk.hw;
1490 * - The initial CDCLK needs to be read from VBT.
1491 * Need to make this change after VBT has changes for BXT.
1493 if (IS_GEMINILAKE(dev_priv)) {
1494 cdclk_state.cdclk = glk_calc_cdclk(0);
1495 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1497 cdclk_state.cdclk = bxt_calc_cdclk(0);
1498 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1500 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1502 bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1505 static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1507 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1509 cdclk_state.cdclk = cdclk_state.bypass;
1510 cdclk_state.vco = 0;
1511 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1513 bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1516 static int cnl_calc_cdclk(int min_cdclk)
1518 if (min_cdclk > 336000)
1520 else if (min_cdclk > 168000)
1526 static u8 cnl_calc_voltage_level(int cdclk)
1530 else if (cdclk > 168000)
1536 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1537 struct intel_cdclk_state *cdclk_state)
1541 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1542 cdclk_state->ref = 24000;
1544 cdclk_state->ref = 19200;
1546 cdclk_state->vco = 0;
1548 val = I915_READ(BXT_DE_PLL_ENABLE);
1549 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1552 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1555 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1558 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1559 struct intel_cdclk_state *cdclk_state)
1564 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1566 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1568 if (cdclk_state->vco == 0)
1571 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1574 case BXT_CDCLK_CD2X_DIV_SEL_1:
1577 case BXT_CDCLK_CD2X_DIV_SEL_2:
1581 MISSING_CASE(divider);
1585 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1589 * Can't read this out :( Let's assume it's
1590 * at least what the CDCLK frequency requires.
1592 cdclk_state->voltage_level =
1593 cnl_calc_voltage_level(cdclk_state->cdclk);
1596 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1600 val = I915_READ(BXT_DE_PLL_ENABLE);
1601 val &= ~BXT_DE_PLL_PLL_ENABLE;
1602 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1605 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1606 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
1608 dev_priv->cdclk.hw.vco = 0;
1611 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1613 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1616 val = CNL_CDCLK_PLL_RATIO(ratio);
1617 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1619 val |= BXT_DE_PLL_PLL_ENABLE;
1620 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1623 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1624 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
1626 dev_priv->cdclk.hw.vco = vco;
1629 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1630 const struct intel_cdclk_state *cdclk_state,
1633 int cdclk = cdclk_state->cdclk;
1634 int vco = cdclk_state->vco;
1638 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1639 SKL_CDCLK_PREPARE_FOR_CHANGE,
1640 SKL_CDCLK_READY_FOR_CHANGE,
1641 SKL_CDCLK_READY_FOR_CHANGE, 3);
1643 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1648 /* cdclk = vco / 2 / div{1,2} */
1649 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1651 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1655 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1658 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1662 if (dev_priv->cdclk.hw.vco != 0 &&
1663 dev_priv->cdclk.hw.vco != vco)
1664 cnl_cdclk_pll_disable(dev_priv);
1666 if (dev_priv->cdclk.hw.vco != vco)
1667 cnl_cdclk_pll_enable(dev_priv, vco);
1669 val = divider | skl_cdclk_decimal(cdclk);
1670 if (pipe == INVALID_PIPE)
1671 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1673 val |= BXT_CDCLK_CD2X_PIPE(pipe);
1674 I915_WRITE(CDCLK_CTL, val);
1676 if (pipe != INVALID_PIPE)
1677 intel_wait_for_vblank(dev_priv, pipe);
1679 /* inform PCU of the change */
1680 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1681 cdclk_state->voltage_level);
1683 intel_update_cdclk(dev_priv);
1686 * Can't read out the voltage level :(
1687 * Let's just assume everything is as expected.
1689 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1692 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1696 if (cdclk == dev_priv->cdclk.hw.bypass)
1701 MISSING_CASE(cdclk);
1705 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1708 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1712 return dev_priv->cdclk.hw.ref * ratio;
1715 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1717 u32 cdctl, expected;
1719 intel_update_cdclk(dev_priv);
1720 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1722 if (dev_priv->cdclk.hw.vco == 0 ||
1723 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1726 /* DPLL okay; verify the cdclock
1728 * Some BIOS versions leave an incorrect decimal frequency value and
1729 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1730 * so sanitize this register.
1732 cdctl = I915_READ(CDCLK_CTL);
1734 * Let's ignore the pipe field, since BIOS could have configured the
1735 * dividers both synching to an active pipe, or asynchronously
1738 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1740 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1741 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1743 if (cdctl == expected)
1744 /* All well; nothing to sanitize */
1748 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1750 /* force cdclk programming */
1751 dev_priv->cdclk.hw.cdclk = 0;
1753 /* force full PLL disable + enable */
1754 dev_priv->cdclk.hw.vco = -1;
1757 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1759 int ranges_24[] = { 312000, 552000, 648000 };
1760 int ranges_19_38[] = { 307200, 556800, 652800 };
1772 ranges = ranges_19_38;
1776 if (min_cdclk > ranges[1])
1778 else if (min_cdclk > ranges[0])
1784 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1788 if (cdclk == dev_priv->cdclk.hw.bypass)
1793 MISSING_CASE(cdclk);
1798 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1799 dev_priv->cdclk.hw.ref != 38400);
1804 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1807 ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1809 return dev_priv->cdclk.hw.ref * ratio;
1812 static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1813 const struct intel_cdclk_state *cdclk_state,
1816 unsigned int cdclk = cdclk_state->cdclk;
1817 unsigned int vco = cdclk_state->vco;
1820 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1821 SKL_CDCLK_PREPARE_FOR_CHANGE,
1822 SKL_CDCLK_READY_FOR_CHANGE,
1823 SKL_CDCLK_READY_FOR_CHANGE, 3);
1825 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1830 if (dev_priv->cdclk.hw.vco != 0 &&
1831 dev_priv->cdclk.hw.vco != vco)
1832 cnl_cdclk_pll_disable(dev_priv);
1834 if (dev_priv->cdclk.hw.vco != vco)
1835 cnl_cdclk_pll_enable(dev_priv, vco);
1838 * On ICL CD2X_DIV can only be 1, so we'll never end up changing the
1839 * divider here synchronized to a pipe while CDCLK is on, nor will we
1840 * need the corresponding vblank wait.
1842 I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1843 skl_cdclk_decimal(cdclk));
1845 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1846 cdclk_state->voltage_level);
1848 intel_update_cdclk(dev_priv);
1851 * Can't read out the voltage level :(
1852 * Let's just assume everything is as expected.
1854 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1857 static u8 icl_calc_voltage_level(int cdclk)
1861 else if (cdclk > 312000)
1867 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1868 struct intel_cdclk_state *cdclk_state)
1872 cdclk_state->bypass = 50000;
1874 val = I915_READ(SKL_DSSM);
1875 switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1879 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1880 cdclk_state->ref = 24000;
1882 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1883 cdclk_state->ref = 19200;
1885 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1886 cdclk_state->ref = 38400;
1890 val = I915_READ(BXT_DE_PLL_ENABLE);
1891 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1892 (val & BXT_DE_PLL_LOCK) == 0) {
1894 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1895 * setting it to zero is a way to signal that.
1897 cdclk_state->vco = 0;
1898 cdclk_state->cdclk = cdclk_state->bypass;
1902 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1904 val = I915_READ(CDCLK_CTL);
1905 WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1907 cdclk_state->cdclk = cdclk_state->vco / 2;
1911 * Can't read this out :( Let's assume it's
1912 * at least what the CDCLK frequency requires.
1914 cdclk_state->voltage_level =
1915 icl_calc_voltage_level(cdclk_state->cdclk);
1918 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
1920 struct intel_cdclk_state sanitized_state;
1923 /* This sets dev_priv->cdclk.hw. */
1924 intel_update_cdclk(dev_priv);
1925 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1927 /* This means CDCLK disabled. */
1928 if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1931 val = I915_READ(CDCLK_CTL);
1933 if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1936 if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1937 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1943 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1945 sanitized_state.ref = dev_priv->cdclk.hw.ref;
1946 sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
1947 sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1948 sanitized_state.cdclk);
1949 sanitized_state.voltage_level =
1950 icl_calc_voltage_level(sanitized_state.cdclk);
1952 icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
1955 static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
1957 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1959 cdclk_state.cdclk = cdclk_state.bypass;
1960 cdclk_state.vco = 0;
1961 cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
1963 icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1966 static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1968 struct intel_cdclk_state cdclk_state;
1970 cnl_sanitize_cdclk(dev_priv);
1972 if (dev_priv->cdclk.hw.cdclk != 0 &&
1973 dev_priv->cdclk.hw.vco != 0)
1976 cdclk_state = dev_priv->cdclk.hw;
1978 cdclk_state.cdclk = cnl_calc_cdclk(0);
1979 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1980 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1982 cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1985 static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1987 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1989 cdclk_state.cdclk = cdclk_state.bypass;
1990 cdclk_state.vco = 0;
1991 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1993 cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1997 * intel_cdclk_init - Initialize CDCLK
1998 * @i915: i915 device
2000 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
2001 * sanitizing the state of the hardware if needed. This is generally done only
2002 * during the display core initialization sequence, after which the DMC will
2003 * take care of turning CDCLK off/on as needed.
2005 void intel_cdclk_init(struct drm_i915_private *i915)
2007 if (INTEL_GEN(i915) >= 11)
2008 icl_init_cdclk(i915);
2009 else if (IS_CANNONLAKE(i915))
2010 cnl_init_cdclk(i915);
2011 else if (IS_GEN9_BC(i915))
2012 skl_init_cdclk(i915);
2013 else if (IS_GEN9_LP(i915))
2014 bxt_init_cdclk(i915);
2018 * intel_cdclk_uninit - Uninitialize CDCLK
2019 * @i915: i915 device
2021 * Uninitialize CDCLK. This is done only during the display core
2022 * uninitialization sequence.
2024 void intel_cdclk_uninit(struct drm_i915_private *i915)
2026 if (INTEL_GEN(i915) >= 11)
2027 icl_uninit_cdclk(i915);
2028 else if (IS_CANNONLAKE(i915))
2029 cnl_uninit_cdclk(i915);
2030 else if (IS_GEN9_BC(i915))
2031 skl_uninit_cdclk(i915);
2032 else if (IS_GEN9_LP(i915))
2033 bxt_uninit_cdclk(i915);
2037 * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
2038 * @a: first CDCLK state
2039 * @b: second CDCLK state
2042 * True if the CDCLK states require pipes to be off during reprogramming, false if not.
2044 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
2045 const struct intel_cdclk_state *b)
2047 return a->cdclk != b->cdclk ||
2053 * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
2054 * @dev_priv: Not a CDCLK state, it's the drm_i915_private!
2055 * @a: first CDCLK state
2056 * @b: second CDCLK state
2059 * True if the CDCLK states require just a cd2x divider update, false if not.
2061 bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
2062 const struct intel_cdclk_state *a,
2063 const struct intel_cdclk_state *b)
2065 /* Older hw doesn't have the capability */
2066 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
2069 return a->cdclk != b->cdclk &&
2075 * intel_cdclk_changed - Determine if two CDCLK states are different
2076 * @a: first CDCLK state
2077 * @b: second CDCLK state
2080 * True if the CDCLK states don't match, false if they do.
2082 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2083 const struct intel_cdclk_state *b)
2085 return intel_cdclk_needs_modeset(a, b) ||
2086 a->voltage_level != b->voltage_level;
2090 * intel_cdclk_swap_state - make atomic CDCLK configuration effective
2091 * @state: atomic state
2093 * This is the CDCLK version of drm_atomic_helper_swap_state() since the
2094 * helper does not handle driver-specific global state.
2096 * Similarly to the atomic helpers this function does a complete swap,
2097 * i.e. it also puts the old state into @state. This is used by the commit
2098 * code to determine how CDCLK has changed (for instance did it increase or
2101 void intel_cdclk_swap_state(struct intel_atomic_state *state)
2103 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2105 swap(state->cdclk.logical, dev_priv->cdclk.logical);
2106 swap(state->cdclk.actual, dev_priv->cdclk.actual);
2109 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2110 const char *context)
2112 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2113 context, cdclk_state->cdclk, cdclk_state->vco,
2114 cdclk_state->ref, cdclk_state->bypass,
2115 cdclk_state->voltage_level);
2119 * intel_set_cdclk - Push the CDCLK state to the hardware
2120 * @dev_priv: i915 device
2121 * @cdclk_state: new CDCLK state
2122 * @pipe: pipe with which to synchronize the update
2124 * Program the hardware based on the passed in CDCLK state,
2127 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2128 const struct intel_cdclk_state *cdclk_state,
2131 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
2134 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2137 intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
2139 dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
2141 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2142 "cdclk state doesn't match!\n")) {
2143 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2144 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2149 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2150 * @dev_priv: i915 device
2151 * @old_state: old CDCLK state
2152 * @new_state: new CDCLK state
2153 * @pipe: pipe with which to synchronize the update
2155 * Program the hardware before updating the HW plane state based on the passed
2156 * in CDCLK state, if necessary.
2159 intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
2160 const struct intel_cdclk_state *old_state,
2161 const struct intel_cdclk_state *new_state,
2164 if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
2165 intel_set_cdclk(dev_priv, new_state, pipe);
2169 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2170 * @dev_priv: i915 device
2171 * @old_state: old CDCLK state
2172 * @new_state: new CDCLK state
2173 * @pipe: pipe with which to synchronize the update
2175 * Program the hardware after updating the HW plane state based on the passed
2176 * in CDCLK state, if necessary.
2179 intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
2180 const struct intel_cdclk_state *old_state,
2181 const struct intel_cdclk_state *new_state,
2184 if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
2185 intel_set_cdclk(dev_priv, new_state, pipe);
2188 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2191 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2192 return DIV_ROUND_UP(pixel_rate, 2);
2193 else if (IS_GEN(dev_priv, 9) ||
2194 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2196 else if (IS_CHERRYVIEW(dev_priv))
2197 return DIV_ROUND_UP(pixel_rate * 100, 95);
2199 return DIV_ROUND_UP(pixel_rate * 100, 90);
2202 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2204 struct drm_i915_private *dev_priv =
2205 to_i915(crtc_state->base.crtc->dev);
2208 if (!crtc_state->base.enable)
2211 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
2213 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2214 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2215 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2217 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2218 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2219 * there may be audio corruption or screen corruption." This cdclk
2220 * restriction for GLK is 316.8 MHz.
2222 if (intel_crtc_has_dp_encoder(crtc_state) &&
2223 crtc_state->has_audio &&
2224 crtc_state->port_clock >= 540000 &&
2225 crtc_state->lane_count == 4) {
2226 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2227 /* Display WA #1145: glk,cnl */
2228 min_cdclk = max(316800, min_cdclk);
2229 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2230 /* Display WA #1144: skl,bxt */
2231 min_cdclk = max(432000, min_cdclk);
2236 * According to BSpec, "The CD clock frequency must be at least twice
2237 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2239 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
2240 min_cdclk = max(2 * 96000, min_cdclk);
2243 * "For DP audio configuration, cdclk frequency shall be set to
2244 * meet the following requirements:
2245 * DP Link Frequency(MHz) | Cdclk frequency(MHz)
2246 * 270 | 320 or higher
2247 * 162 | 200 or higher"
2249 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2250 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2251 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2254 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2257 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2258 IS_VALLEYVIEW(dev_priv))
2259 min_cdclk = max(320000, min_cdclk);
2262 * On Geminilake once the CDCLK gets as low as 79200
2263 * picture gets unstable, despite that values are
2264 * correct for DSI PLL and DE PLL.
2266 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2267 IS_GEMINILAKE(dev_priv))
2268 min_cdclk = max(158400, min_cdclk);
2270 if (min_cdclk > dev_priv->max_cdclk_freq) {
2271 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2272 min_cdclk, dev_priv->max_cdclk_freq);
2279 static int intel_compute_min_cdclk(struct intel_atomic_state *state)
2281 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2282 struct intel_crtc *crtc;
2283 struct intel_crtc_state *crtc_state;
2287 memcpy(state->min_cdclk, dev_priv->min_cdclk,
2288 sizeof(state->min_cdclk));
2290 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2291 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2295 state->min_cdclk[i] = min_cdclk;
2298 min_cdclk = state->cdclk.force_min_cdclk;
2299 for_each_pipe(dev_priv, pipe)
2300 min_cdclk = max(state->min_cdclk[pipe], min_cdclk);
2306 * Note that this functions assumes that 0 is
2307 * the lowest voltage value, and higher values
2308 * correspond to increasingly higher voltages.
2310 * Should that relationship no longer hold on
2311 * future platforms this code will need to be
2314 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2316 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2317 struct intel_crtc *crtc;
2318 struct intel_crtc_state *crtc_state;
2319 u8 min_voltage_level;
2323 memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2324 sizeof(state->min_voltage_level));
2326 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2327 if (crtc_state->base.enable)
2328 state->min_voltage_level[i] =
2329 crtc_state->min_voltage_level;
2331 state->min_voltage_level[i] = 0;
2334 min_voltage_level = 0;
2335 for_each_pipe(dev_priv, pipe)
2336 min_voltage_level = max(state->min_voltage_level[pipe],
2339 return min_voltage_level;
2342 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
2344 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2345 int min_cdclk, cdclk;
2347 min_cdclk = intel_compute_min_cdclk(state);
2351 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2353 state->cdclk.logical.cdclk = cdclk;
2354 state->cdclk.logical.voltage_level =
2355 vlv_calc_voltage_level(dev_priv, cdclk);
2357 if (!state->active_crtcs) {
2358 cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
2360 state->cdclk.actual.cdclk = cdclk;
2361 state->cdclk.actual.voltage_level =
2362 vlv_calc_voltage_level(dev_priv, cdclk);
2364 state->cdclk.actual = state->cdclk.logical;
2370 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
2372 int min_cdclk, cdclk;
2374 min_cdclk = intel_compute_min_cdclk(state);
2379 * FIXME should also account for plane ratio
2380 * once 64bpp pixel formats are supported.
2382 cdclk = bdw_calc_cdclk(min_cdclk);
2384 state->cdclk.logical.cdclk = cdclk;
2385 state->cdclk.logical.voltage_level =
2386 bdw_calc_voltage_level(cdclk);
2388 if (!state->active_crtcs) {
2389 cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk);
2391 state->cdclk.actual.cdclk = cdclk;
2392 state->cdclk.actual.voltage_level =
2393 bdw_calc_voltage_level(cdclk);
2395 state->cdclk.actual = state->cdclk.logical;
2401 static int skl_dpll0_vco(struct intel_atomic_state *state)
2403 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2404 struct intel_crtc *crtc;
2405 struct intel_crtc_state *crtc_state;
2408 vco = state->cdclk.logical.vco;
2410 vco = dev_priv->skl_preferred_vco_freq;
2412 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2413 if (!crtc_state->base.enable)
2416 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2420 * DPLL0 VCO may need to be adjusted to get the correct
2421 * clock for eDP. This will affect cdclk as well.
2423 switch (crtc_state->port_clock / 2) {
2437 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
2439 int min_cdclk, cdclk, vco;
2441 min_cdclk = intel_compute_min_cdclk(state);
2445 vco = skl_dpll0_vco(state);
2448 * FIXME should also account for plane ratio
2449 * once 64bpp pixel formats are supported.
2451 cdclk = skl_calc_cdclk(min_cdclk, vco);
2453 state->cdclk.logical.vco = vco;
2454 state->cdclk.logical.cdclk = cdclk;
2455 state->cdclk.logical.voltage_level =
2456 skl_calc_voltage_level(cdclk);
2458 if (!state->active_crtcs) {
2459 cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco);
2461 state->cdclk.actual.vco = vco;
2462 state->cdclk.actual.cdclk = cdclk;
2463 state->cdclk.actual.voltage_level =
2464 skl_calc_voltage_level(cdclk);
2466 state->cdclk.actual = state->cdclk.logical;
2472 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
2474 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2475 int min_cdclk, cdclk, vco;
2477 min_cdclk = intel_compute_min_cdclk(state);
2481 if (IS_GEMINILAKE(dev_priv)) {
2482 cdclk = glk_calc_cdclk(min_cdclk);
2483 vco = glk_de_pll_vco(dev_priv, cdclk);
2485 cdclk = bxt_calc_cdclk(min_cdclk);
2486 vco = bxt_de_pll_vco(dev_priv, cdclk);
2489 state->cdclk.logical.vco = vco;
2490 state->cdclk.logical.cdclk = cdclk;
2491 state->cdclk.logical.voltage_level =
2492 bxt_calc_voltage_level(cdclk);
2494 if (!state->active_crtcs) {
2495 if (IS_GEMINILAKE(dev_priv)) {
2496 cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk);
2497 vco = glk_de_pll_vco(dev_priv, cdclk);
2499 cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk);
2500 vco = bxt_de_pll_vco(dev_priv, cdclk);
2503 state->cdclk.actual.vco = vco;
2504 state->cdclk.actual.cdclk = cdclk;
2505 state->cdclk.actual.voltage_level =
2506 bxt_calc_voltage_level(cdclk);
2508 state->cdclk.actual = state->cdclk.logical;
2514 static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
2516 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2517 int min_cdclk, cdclk, vco;
2519 min_cdclk = intel_compute_min_cdclk(state);
2523 cdclk = cnl_calc_cdclk(min_cdclk);
2524 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2526 state->cdclk.logical.vco = vco;
2527 state->cdclk.logical.cdclk = cdclk;
2528 state->cdclk.logical.voltage_level =
2529 max(cnl_calc_voltage_level(cdclk),
2530 cnl_compute_min_voltage_level(state));
2532 if (!state->active_crtcs) {
2533 cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk);
2534 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2536 state->cdclk.actual.vco = vco;
2537 state->cdclk.actual.cdclk = cdclk;
2538 state->cdclk.actual.voltage_level =
2539 cnl_calc_voltage_level(cdclk);
2541 state->cdclk.actual = state->cdclk.logical;
2547 static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
2549 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2550 unsigned int ref = state->cdclk.logical.ref;
2551 int min_cdclk, cdclk, vco;
2553 min_cdclk = intel_compute_min_cdclk(state);
2557 cdclk = icl_calc_cdclk(min_cdclk, ref);
2558 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2560 state->cdclk.logical.vco = vco;
2561 state->cdclk.logical.cdclk = cdclk;
2562 state->cdclk.logical.voltage_level =
2563 max(icl_calc_voltage_level(cdclk),
2564 cnl_compute_min_voltage_level(state));
2566 if (!state->active_crtcs) {
2567 cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
2568 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2570 state->cdclk.actual.vco = vco;
2571 state->cdclk.actual.cdclk = cdclk;
2572 state->cdclk.actual.voltage_level =
2573 icl_calc_voltage_level(cdclk);
2575 state->cdclk.actual = state->cdclk.logical;
2581 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2583 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2585 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2586 return 2 * max_cdclk_freq;
2587 else if (IS_GEN(dev_priv, 9) ||
2588 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2589 return max_cdclk_freq;
2590 else if (IS_CHERRYVIEW(dev_priv))
2591 return max_cdclk_freq*95/100;
2592 else if (INTEL_GEN(dev_priv) < 4)
2593 return 2*max_cdclk_freq*90/100;
2595 return max_cdclk_freq*90/100;
2599 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2600 * @dev_priv: i915 device
2602 * Determine the maximum CDCLK frequency the platform supports, and also
2603 * derive the maximum dot clock frequency the maximum CDCLK frequency
2606 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2608 if (INTEL_GEN(dev_priv) >= 11) {
2609 if (dev_priv->cdclk.hw.ref == 24000)
2610 dev_priv->max_cdclk_freq = 648000;
2612 dev_priv->max_cdclk_freq = 652800;
2613 } else if (IS_CANNONLAKE(dev_priv)) {
2614 dev_priv->max_cdclk_freq = 528000;
2615 } else if (IS_GEN9_BC(dev_priv)) {
2616 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2619 vco = dev_priv->skl_preferred_vco_freq;
2620 WARN_ON(vco != 8100000 && vco != 8640000);
2623 * Use the lower (vco 8640) cdclk values as a
2624 * first guess. skl_calc_cdclk() will correct it
2625 * if the preferred vco is 8100 instead.
2627 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2629 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2631 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2636 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2637 } else if (IS_GEMINILAKE(dev_priv)) {
2638 dev_priv->max_cdclk_freq = 316800;
2639 } else if (IS_BROXTON(dev_priv)) {
2640 dev_priv->max_cdclk_freq = 624000;
2641 } else if (IS_BROADWELL(dev_priv)) {
2643 * FIXME with extra cooling we can allow
2644 * 540 MHz for ULX and 675 Mhz for ULT.
2645 * How can we know if extra cooling is
2646 * available? PCI ID, VTB, something else?
2648 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2649 dev_priv->max_cdclk_freq = 450000;
2650 else if (IS_BDW_ULX(dev_priv))
2651 dev_priv->max_cdclk_freq = 450000;
2652 else if (IS_BDW_ULT(dev_priv))
2653 dev_priv->max_cdclk_freq = 540000;
2655 dev_priv->max_cdclk_freq = 675000;
2656 } else if (IS_CHERRYVIEW(dev_priv)) {
2657 dev_priv->max_cdclk_freq = 320000;
2658 } else if (IS_VALLEYVIEW(dev_priv)) {
2659 dev_priv->max_cdclk_freq = 400000;
2661 /* otherwise assume cdclk is fixed */
2662 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2665 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2667 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2668 dev_priv->max_cdclk_freq);
2670 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2671 dev_priv->max_dotclk_freq);
2675 * intel_update_cdclk - Determine the current CDCLK frequency
2676 * @dev_priv: i915 device
2678 * Determine the current CDCLK frequency.
2680 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2682 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2685 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2686 * Programmng [sic] note: bit[9:2] should be programmed to the number
2687 * of cdclk that generates 4MHz reference clock freq which is used to
2688 * generate GMBus clock. This will vary with the cdclk freq.
2690 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2691 I915_WRITE(GMBUSFREQ_VLV,
2692 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2695 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2698 int divider, fraction;
2700 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2710 rawclk = CNP_RAWCLK_DIV(divider / 1000);
2714 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2716 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2717 rawclk |= ICP_RAWCLK_NUM(numerator);
2720 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2721 return divider + fraction;
2724 static int pch_rawclk(struct drm_i915_private *dev_priv)
2726 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2729 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2731 /* RAWCLK_FREQ_VLV register updated from power well code */
2732 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2733 CCK_DISPLAY_REF_CLOCK_CONTROL);
2736 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2740 /* hrawclock is 1/4 the FSB frequency */
2741 clkcfg = I915_READ(CLKCFG);
2742 switch (clkcfg & CLKCFG_FSB_MASK) {
2743 case CLKCFG_FSB_400:
2745 case CLKCFG_FSB_533:
2747 case CLKCFG_FSB_667:
2749 case CLKCFG_FSB_800:
2751 case CLKCFG_FSB_1067:
2752 case CLKCFG_FSB_1067_ALT:
2754 case CLKCFG_FSB_1333:
2755 case CLKCFG_FSB_1333_ALT:
2763 * intel_update_rawclk - Determine the current RAWCLK frequency
2764 * @dev_priv: i915 device
2766 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2767 * frequency clock so this needs to done only once.
2769 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2771 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2772 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2773 else if (HAS_PCH_SPLIT(dev_priv))
2774 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2775 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2776 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2777 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2778 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2780 /* no rawclk on other platforms, or no need to know it */
2783 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2787 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2788 * @dev_priv: i915 device
2790 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2792 if (INTEL_GEN(dev_priv) >= 11) {
2793 dev_priv->display.set_cdclk = icl_set_cdclk;
2794 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2795 } else if (IS_CANNONLAKE(dev_priv)) {
2796 dev_priv->display.set_cdclk = cnl_set_cdclk;
2797 dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
2798 } else if (IS_GEN9_LP(dev_priv)) {
2799 dev_priv->display.set_cdclk = bxt_set_cdclk;
2800 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2801 } else if (IS_GEN9_BC(dev_priv)) {
2802 dev_priv->display.set_cdclk = skl_set_cdclk;
2803 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
2804 } else if (IS_BROADWELL(dev_priv)) {
2805 dev_priv->display.set_cdclk = bdw_set_cdclk;
2806 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
2807 } else if (IS_CHERRYVIEW(dev_priv)) {
2808 dev_priv->display.set_cdclk = chv_set_cdclk;
2809 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2810 } else if (IS_VALLEYVIEW(dev_priv)) {
2811 dev_priv->display.set_cdclk = vlv_set_cdclk;
2812 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2815 if (INTEL_GEN(dev_priv) >= 11)
2816 dev_priv->display.get_cdclk = icl_get_cdclk;
2817 else if (IS_CANNONLAKE(dev_priv))
2818 dev_priv->display.get_cdclk = cnl_get_cdclk;
2819 else if (IS_GEN9_LP(dev_priv))
2820 dev_priv->display.get_cdclk = bxt_get_cdclk;
2821 else if (IS_GEN9_BC(dev_priv))
2822 dev_priv->display.get_cdclk = skl_get_cdclk;
2823 else if (IS_BROADWELL(dev_priv))
2824 dev_priv->display.get_cdclk = bdw_get_cdclk;
2825 else if (IS_HASWELL(dev_priv))
2826 dev_priv->display.get_cdclk = hsw_get_cdclk;
2827 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2828 dev_priv->display.get_cdclk = vlv_get_cdclk;
2829 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2830 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2831 else if (IS_GEN(dev_priv, 5))
2832 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2833 else if (IS_GM45(dev_priv))
2834 dev_priv->display.get_cdclk = gm45_get_cdclk;
2835 else if (IS_G45(dev_priv))
2836 dev_priv->display.get_cdclk = g33_get_cdclk;
2837 else if (IS_I965GM(dev_priv))
2838 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2839 else if (IS_I965G(dev_priv))
2840 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2841 else if (IS_PINEVIEW(dev_priv))
2842 dev_priv->display.get_cdclk = pnv_get_cdclk;
2843 else if (IS_G33(dev_priv))
2844 dev_priv->display.get_cdclk = g33_get_cdclk;
2845 else if (IS_I945GM(dev_priv))
2846 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2847 else if (IS_I945G(dev_priv))
2848 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2849 else if (IS_I915GM(dev_priv))
2850 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2851 else if (IS_I915G(dev_priv))
2852 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2853 else if (IS_I865G(dev_priv))
2854 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2855 else if (IS_I85X(dev_priv))
2856 dev_priv->display.get_cdclk = i85x_get_cdclk;
2857 else if (IS_I845G(dev_priv))
2858 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2860 WARN(!IS_I830(dev_priv),
2861 "Unknown platform. Assuming 133 MHz CDCLK\n");
2862 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;