1 // SPDX-License-Identifier: MIT
3 * Copyright © 2019 Intel Corporation
6 #include <drm/drm_atomic_state_helper.h>
9 #include "intel_display_types.h"
10 #include "intel_sideband.h"
12 /* Parameters for Qclk Geyserville (QGV) */
13 struct intel_qgv_point {
14 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
17 struct intel_qgv_info {
18 struct intel_qgv_point points[3];
22 enum intel_dram_type dram_type;
25 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
26 struct intel_qgv_info *qi)
31 ret = sandybridge_pcode_read(dev_priv,
32 ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
33 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
40 qi->dram_type = INTEL_DRAM_DDR4;
43 qi->dram_type = INTEL_DRAM_DDR3;
46 qi->dram_type = INTEL_DRAM_LPDDR3;
49 qi->dram_type = INTEL_DRAM_LPDDR3;
52 MISSING_CASE(val & 0xf);
56 qi->num_channels = (val & 0xf0) >> 4;
57 qi->num_points = (val & 0xf00) >> 8;
59 qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
64 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
65 struct intel_qgv_point *sp,
68 u32 val = 0, val2 = 0;
71 ret = sandybridge_pcode_read(dev_priv,
72 ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
73 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
78 sp->dclk = val & 0xffff;
79 sp->t_rp = (val & 0xff0000) >> 16;
80 sp->t_rcd = (val & 0xff000000) >> 24;
82 sp->t_rdpre = val2 & 0xff;
83 sp->t_ras = (val2 & 0xff00) >> 8;
85 sp->t_rc = sp->t_rp + sp->t_ras;
90 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
91 struct intel_qgv_info *qi)
95 ret = icl_pcode_read_mem_global_info(dev_priv, qi);
99 if (WARN_ON(qi->num_points > ARRAY_SIZE(qi->points)))
100 qi->num_points = ARRAY_SIZE(qi->points);
102 for (i = 0; i < qi->num_points; i++) {
103 struct intel_qgv_point *sp = &qi->points[i];
105 ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
109 DRM_DEBUG_KMS("QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
110 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
111 sp->t_rcd, sp->t_rc);
117 static int icl_calc_bw(int dclk, int num, int den)
119 /* multiples of 16.666MHz (100/6) */
120 return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6);
123 static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
128 for (i = 0; i < qi->num_points; i++)
129 dclk = max(dclk, qi->points[i].dclk);
134 struct intel_sa_info {
135 u8 deburst, mpagesize, deprogbwlimit, displayrtids;
138 static const struct intel_sa_info icl_sa_info = {
141 .deprogbwlimit = 25, /* GB/s */
145 static int icl_get_bw_info(struct drm_i915_private *dev_priv)
147 struct intel_qgv_info qi = {};
148 const struct intel_sa_info *sa = &icl_sa_info;
149 bool is_y_tile = true; /* assume y tile may be used */
152 int ipqdepth, ipqdepthpch;
157 ret = icl_get_qgv_points(dev_priv, &qi);
159 DRM_DEBUG_KMS("Failed to get memory subsystem information, ignoring bandwidth limits");
162 num_channels = qi.num_channels;
164 deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
165 dclk_max = icl_sagv_max_dclk(&qi);
169 maxdebw = min(sa->deprogbwlimit * 1000,
170 icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */
171 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
173 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
174 struct intel_bw_info *bi = &dev_priv->max_bw[i];
178 clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
179 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
181 bi->num_qgv_points = qi.num_points;
183 for (j = 0; j < qi.num_points; j++) {
184 const struct intel_qgv_point *sp = &qi.points[j];
190 * FIXME what is the logic behind the
191 * assumed burst length?
193 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
194 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
195 bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
197 bi->deratedbw[j] = min(maxdebw,
198 bw * 9 / 10); /* 90% */
200 DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
201 i, j, bi->num_planes, bi->deratedbw[j]);
204 if (bi->num_planes == 1)
211 static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
212 int num_planes, int qgv_point)
216 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
217 const struct intel_bw_info *bi =
218 &dev_priv->max_bw[i];
221 * Pcode will not expose all QGV points when
222 * SAGV is forced to off/min/med/max.
224 if (qgv_point >= bi->num_qgv_points)
227 if (num_planes >= bi->num_planes)
228 return bi->deratedbw[qgv_point];
234 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
236 if (IS_GEN(dev_priv, 11))
237 icl_get_bw_info(dev_priv);
240 static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
243 if (IS_GEN(dev_priv, 11))
245 * FIXME with SAGV disabled maybe we can assume
246 * point 1 will always be used? Seems to match
247 * the behaviour observed in the wild.
249 return min3(icl_max_bw(dev_priv, num_planes, 0),
250 icl_max_bw(dev_priv, num_planes, 1),
251 icl_max_bw(dev_priv, num_planes, 2));
256 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
259 * We assume cursors are small enough
260 * to not not cause bandwidth problems.
262 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
265 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
267 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
268 unsigned int data_rate = 0;
269 enum plane_id plane_id;
271 for_each_plane_id_on_crtc(crtc, plane_id) {
273 * We assume cursors are small enough
274 * to not not cause bandwidth problems.
276 if (plane_id == PLANE_CURSOR)
279 data_rate += crtc_state->data_rate[plane_id];
285 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
286 const struct intel_crtc_state *crtc_state)
288 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
290 bw_state->data_rate[crtc->pipe] =
291 intel_bw_crtc_data_rate(crtc_state);
292 bw_state->num_active_planes[crtc->pipe] =
293 intel_bw_crtc_num_active_planes(crtc_state);
295 DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n",
296 pipe_name(crtc->pipe),
297 bw_state->data_rate[crtc->pipe],
298 bw_state->num_active_planes[crtc->pipe]);
301 static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
302 const struct intel_bw_state *bw_state)
304 unsigned int num_active_planes = 0;
307 for_each_pipe(dev_priv, pipe)
308 num_active_planes += bw_state->num_active_planes[pipe];
310 return num_active_planes;
313 static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
314 const struct intel_bw_state *bw_state)
316 unsigned int data_rate = 0;
319 for_each_pipe(dev_priv, pipe)
320 data_rate += bw_state->data_rate[pipe];
325 static struct intel_bw_state *
326 intel_atomic_get_bw_state(struct intel_atomic_state *state)
328 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
329 struct drm_private_state *bw_state;
331 bw_state = drm_atomic_get_private_obj_state(&state->base,
333 if (IS_ERR(bw_state))
334 return ERR_CAST(bw_state);
336 return to_intel_bw_state(bw_state);
339 int intel_bw_atomic_check(struct intel_atomic_state *state)
341 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
342 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
343 struct intel_bw_state *bw_state = NULL;
344 unsigned int data_rate, max_data_rate;
345 unsigned int num_active_planes;
346 struct intel_crtc *crtc;
349 /* FIXME earlier gens need some checks too */
350 if (INTEL_GEN(dev_priv) < 11)
353 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
355 unsigned int old_data_rate =
356 intel_bw_crtc_data_rate(old_crtc_state);
357 unsigned int new_data_rate =
358 intel_bw_crtc_data_rate(new_crtc_state);
359 unsigned int old_active_planes =
360 intel_bw_crtc_num_active_planes(old_crtc_state);
361 unsigned int new_active_planes =
362 intel_bw_crtc_num_active_planes(new_crtc_state);
365 * Avoid locking the bw state when
366 * nothing significant has changed.
368 if (old_data_rate == new_data_rate &&
369 old_active_planes == new_active_planes)
372 bw_state = intel_atomic_get_bw_state(state);
373 if (IS_ERR(bw_state))
374 return PTR_ERR(bw_state);
376 bw_state->data_rate[crtc->pipe] = new_data_rate;
377 bw_state->num_active_planes[crtc->pipe] = new_active_planes;
379 DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n",
380 pipe_name(crtc->pipe),
381 bw_state->data_rate[crtc->pipe],
382 bw_state->num_active_planes[crtc->pipe]);
388 data_rate = intel_bw_data_rate(dev_priv, bw_state);
389 num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
391 max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
393 data_rate = DIV_ROUND_UP(data_rate, 1000);
395 if (data_rate > max_data_rate) {
396 DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
397 data_rate, max_data_rate, num_active_planes);
404 static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj)
406 struct intel_bw_state *state;
408 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
412 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
417 static void intel_bw_destroy_state(struct drm_private_obj *obj,
418 struct drm_private_state *state)
423 static const struct drm_private_state_funcs intel_bw_funcs = {
424 .atomic_duplicate_state = intel_bw_duplicate_state,
425 .atomic_destroy_state = intel_bw_destroy_state,
428 int intel_bw_init(struct drm_i915_private *dev_priv)
430 struct intel_bw_state *state;
432 state = kzalloc(sizeof(*state), GFP_KERNEL);
436 drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj,
437 &state->base, &intel_bw_funcs);