2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/component.h>
25 #include <linux/kernel.h>
27 #include <drm/drm_edid.h>
28 #include <drm/i915_component.h>
31 #include "intel_atomic.h"
32 #include "intel_audio.h"
33 #include "intel_cdclk.h"
34 #include "intel_display_types.h"
35 #include "intel_lpe_audio.h"
38 * DOC: High Definition Audio over HDMI and Display Port
40 * The graphics and audio drivers together support High Definition Audio over
41 * HDMI and Display Port. The audio programming sequences are divided into audio
42 * codec and controller enable and disable sequences. The graphics driver
43 * handles the audio codec sequences, while the audio driver handles the audio
44 * controller sequences.
46 * The disable sequences must be performed before disabling the transcoder or
47 * port. The enable sequences may only be performed after enabling the
48 * transcoder and port, and after completed link training. Therefore the audio
49 * enable/disable sequences are part of the modeset sequence.
51 * The codec and controller sequences could be done either parallel or serial,
52 * but generally the ELDV/PD change in the codec sequence indicates to the audio
53 * driver that the controller sequence should start. Indeed, most of the
54 * co-operation between the graphics and audio drivers is handled via audio
55 * related registers. (The notable exception is the power management, not
58 * The struct &i915_audio_component is used to interact between the graphics
59 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
60 * defined in graphics driver and called in audio driver. The
61 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
65 #define LC_810M 810000
66 #define LC_540M 540000
67 #define LC_270M 270000
68 #define LC_162M 162000
77 struct hdmi_aud_ncts {
84 /* Values according to DP 1.4 Table 2-104 */
85 static const struct dp_aud_n_m dp_aud_n_m[] = {
86 { 32000, LC_162M, 1024, 10125 },
87 { 44100, LC_162M, 784, 5625 },
88 { 48000, LC_162M, 512, 3375 },
89 { 64000, LC_162M, 2048, 10125 },
90 { 88200, LC_162M, 1568, 5625 },
91 { 96000, LC_162M, 1024, 3375 },
92 { 128000, LC_162M, 4096, 10125 },
93 { 176400, LC_162M, 3136, 5625 },
94 { 192000, LC_162M, 2048, 3375 },
95 { 32000, LC_270M, 1024, 16875 },
96 { 44100, LC_270M, 784, 9375 },
97 { 48000, LC_270M, 512, 5625 },
98 { 64000, LC_270M, 2048, 16875 },
99 { 88200, LC_270M, 1568, 9375 },
100 { 96000, LC_270M, 1024, 5625 },
101 { 128000, LC_270M, 4096, 16875 },
102 { 176400, LC_270M, 3136, 9375 },
103 { 192000, LC_270M, 2048, 5625 },
104 { 32000, LC_540M, 1024, 33750 },
105 { 44100, LC_540M, 784, 18750 },
106 { 48000, LC_540M, 512, 11250 },
107 { 64000, LC_540M, 2048, 33750 },
108 { 88200, LC_540M, 1568, 18750 },
109 { 96000, LC_540M, 1024, 11250 },
110 { 128000, LC_540M, 4096, 33750 },
111 { 176400, LC_540M, 3136, 18750 },
112 { 192000, LC_540M, 2048, 11250 },
113 { 32000, LC_810M, 1024, 50625 },
114 { 44100, LC_810M, 784, 28125 },
115 { 48000, LC_810M, 512, 16875 },
116 { 64000, LC_810M, 2048, 50625 },
117 { 88200, LC_810M, 1568, 28125 },
118 { 96000, LC_810M, 1024, 16875 },
119 { 128000, LC_810M, 4096, 50625 },
120 { 176400, LC_810M, 3136, 28125 },
121 { 192000, LC_810M, 2048, 16875 },
124 static const struct dp_aud_n_m *
125 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
129 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
130 if (rate == dp_aud_n_m[i].sample_rate &&
131 crtc_state->port_clock == dp_aud_n_m[i].clock)
132 return &dp_aud_n_m[i];
138 static const struct {
141 } hdmi_audio_clock[] = {
142 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
143 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
144 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
145 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
146 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
147 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
148 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
149 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
150 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
151 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
152 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
153 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
154 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
155 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
158 /* HDMI N/CTS table */
159 #define TMDS_297M 297000
160 #define TMDS_296M 296703
161 #define TMDS_594M 594000
162 #define TMDS_593M 593407
164 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
165 { 32000, TMDS_296M, 5824, 421875 },
166 { 32000, TMDS_297M, 3072, 222750 },
167 { 32000, TMDS_593M, 5824, 843750 },
168 { 32000, TMDS_594M, 3072, 445500 },
169 { 44100, TMDS_296M, 4459, 234375 },
170 { 44100, TMDS_297M, 4704, 247500 },
171 { 44100, TMDS_593M, 8918, 937500 },
172 { 44100, TMDS_594M, 9408, 990000 },
173 { 88200, TMDS_296M, 8918, 234375 },
174 { 88200, TMDS_297M, 9408, 247500 },
175 { 88200, TMDS_593M, 17836, 937500 },
176 { 88200, TMDS_594M, 18816, 990000 },
177 { 176400, TMDS_296M, 17836, 234375 },
178 { 176400, TMDS_297M, 18816, 247500 },
179 { 176400, TMDS_593M, 35672, 937500 },
180 { 176400, TMDS_594M, 37632, 990000 },
181 { 48000, TMDS_296M, 5824, 281250 },
182 { 48000, TMDS_297M, 5120, 247500 },
183 { 48000, TMDS_593M, 5824, 562500 },
184 { 48000, TMDS_594M, 6144, 594000 },
185 { 96000, TMDS_296M, 11648, 281250 },
186 { 96000, TMDS_297M, 10240, 247500 },
187 { 96000, TMDS_593M, 11648, 562500 },
188 { 96000, TMDS_594M, 12288, 594000 },
189 { 192000, TMDS_296M, 23296, 281250 },
190 { 192000, TMDS_297M, 20480, 247500 },
191 { 192000, TMDS_593M, 23296, 562500 },
192 { 192000, TMDS_594M, 24576, 594000 },
195 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
196 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
197 #define TMDS_371M 371250
198 #define TMDS_370M 370878
200 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
201 { 32000, TMDS_370M, 5824, 527344 },
202 { 32000, TMDS_371M, 6144, 556875 },
203 { 44100, TMDS_370M, 8918, 585938 },
204 { 44100, TMDS_371M, 4704, 309375 },
205 { 88200, TMDS_370M, 17836, 585938 },
206 { 88200, TMDS_371M, 9408, 309375 },
207 { 176400, TMDS_370M, 35672, 585938 },
208 { 176400, TMDS_371M, 18816, 309375 },
209 { 48000, TMDS_370M, 11648, 703125 },
210 { 48000, TMDS_371M, 5120, 309375 },
211 { 96000, TMDS_370M, 23296, 703125 },
212 { 96000, TMDS_371M, 10240, 309375 },
213 { 192000, TMDS_370M, 46592, 703125 },
214 { 192000, TMDS_371M, 20480, 309375 },
217 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
218 #define TMDS_445_5M 445500
219 #define TMDS_445M 445054
221 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
222 { 32000, TMDS_445M, 5824, 632813 },
223 { 32000, TMDS_445_5M, 4096, 445500 },
224 { 44100, TMDS_445M, 8918, 703125 },
225 { 44100, TMDS_445_5M, 4704, 371250 },
226 { 88200, TMDS_445M, 17836, 703125 },
227 { 88200, TMDS_445_5M, 9408, 371250 },
228 { 176400, TMDS_445M, 35672, 703125 },
229 { 176400, TMDS_445_5M, 18816, 371250 },
230 { 48000, TMDS_445M, 5824, 421875 },
231 { 48000, TMDS_445_5M, 5120, 371250 },
232 { 96000, TMDS_445M, 11648, 421875 },
233 { 96000, TMDS_445_5M, 10240, 371250 },
234 { 192000, TMDS_445M, 23296, 421875 },
235 { 192000, TMDS_445_5M, 20480, 371250 },
238 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
239 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
241 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
242 const struct drm_display_mode *adjusted_mode =
243 &crtc_state->hw.adjusted_mode;
246 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
247 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
251 if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
252 i = ARRAY_SIZE(hdmi_audio_clock);
254 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
255 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
256 adjusted_mode->crtc_clock);
260 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
261 hdmi_audio_clock[i].clock,
262 hdmi_audio_clock[i].config);
264 return hdmi_audio_clock[i].config;
267 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
270 const struct hdmi_aud_ncts *hdmi_ncts_table;
273 if (crtc_state->pipe_bpp == 36) {
274 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
275 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
276 } else if (crtc_state->pipe_bpp == 30) {
277 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
278 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
280 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
281 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
284 for (i = 0; i < size; i++) {
285 if (rate == hdmi_ncts_table[i].sample_rate &&
286 crtc_state->port_clock == hdmi_ncts_table[i].clock) {
287 return hdmi_ncts_table[i].n;
293 static bool intel_eld_uptodate(struct drm_connector *connector,
294 i915_reg_t reg_eldv, u32 bits_eldv,
295 i915_reg_t reg_elda, u32 bits_elda,
298 struct drm_i915_private *dev_priv = to_i915(connector->dev);
299 const u8 *eld = connector->eld;
303 tmp = intel_de_read(dev_priv, reg_eldv);
309 tmp = intel_de_read(dev_priv, reg_elda);
311 intel_de_write(dev_priv, reg_elda, tmp);
313 for (i = 0; i < drm_eld_size(eld) / 4; i++)
314 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i))
320 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
321 const struct intel_crtc_state *old_crtc_state,
322 const struct drm_connector_state *old_conn_state)
324 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
327 drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n");
329 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
330 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
331 eldv = G4X_ELDV_DEVCL_DEVBLC;
333 eldv = G4X_ELDV_DEVCTG;
336 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
338 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
341 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
342 const struct intel_crtc_state *crtc_state,
343 const struct drm_connector_state *conn_state)
345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
346 struct drm_connector *connector = conn_state->connector;
347 const u8 *eld = connector->eld;
352 drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n",
355 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
356 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
357 eldv = G4X_ELDV_DEVCL_DEVBLC;
359 eldv = G4X_ELDV_DEVCTG;
361 if (intel_eld_uptodate(connector,
362 G4X_AUD_CNTL_ST, eldv,
363 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
367 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
368 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
369 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
370 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
372 len = min(drm_eld_size(eld) / 4, len);
373 drm_dbg(&dev_priv->drm, "ELD size %d\n", len);
374 for (i = 0; i < len; i++)
375 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
376 *((const u32 *)eld + i));
378 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
380 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
384 hsw_dp_audio_config_update(struct intel_encoder *encoder,
385 const struct intel_crtc_state *crtc_state)
387 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
388 struct i915_audio_component *acomp = dev_priv->audio_component;
389 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
390 enum port port = encoder->port;
391 const struct dp_aud_n_m *nm;
395 rate = acomp ? acomp->aud_sample_rate[port] : 0;
396 nm = audio_config_dp_get_n_m(crtc_state, rate);
398 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m,
401 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n");
403 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
404 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
405 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
406 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
407 tmp |= AUD_CONFIG_N_VALUE_INDEX;
410 tmp &= ~AUD_CONFIG_N_MASK;
411 tmp |= AUD_CONFIG_N(nm->n);
412 tmp |= AUD_CONFIG_N_PROG_ENABLE;
415 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
417 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
418 tmp &= ~AUD_CONFIG_M_MASK;
419 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
420 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
424 tmp |= AUD_M_CTS_M_VALUE_INDEX;
425 tmp |= AUD_M_CTS_M_PROG_ENABLE;
428 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
432 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
433 const struct intel_crtc_state *crtc_state)
435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
436 struct i915_audio_component *acomp = dev_priv->audio_component;
437 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
438 enum port port = encoder->port;
442 rate = acomp ? acomp->aud_sample_rate[port] : 0;
444 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
445 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
446 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
447 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
448 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
450 n = audio_config_hdmi_get_n(crtc_state, rate);
452 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n);
454 tmp &= ~AUD_CONFIG_N_MASK;
455 tmp |= AUD_CONFIG_N(n);
456 tmp |= AUD_CONFIG_N_PROG_ENABLE;
458 drm_dbg_kms(&dev_priv->drm, "using automatic N\n");
461 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
464 * Let's disable "Enable CTS or M Prog bit"
465 * and let HW calculate the value
467 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
468 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
469 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
470 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
474 hsw_audio_config_update(struct intel_encoder *encoder,
475 const struct intel_crtc_state *crtc_state)
477 if (intel_crtc_has_dp_encoder(crtc_state))
478 hsw_dp_audio_config_update(encoder, crtc_state);
480 hsw_hdmi_audio_config_update(encoder, crtc_state);
483 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
484 const struct intel_crtc_state *old_crtc_state,
485 const struct drm_connector_state *old_conn_state)
487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
488 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
491 drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n",
492 transcoder_name(cpu_transcoder));
494 mutex_lock(&dev_priv->av_mutex);
496 /* Disable timestamps */
497 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
498 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
499 tmp |= AUD_CONFIG_N_PROG_ENABLE;
500 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
501 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
502 if (intel_crtc_has_dp_encoder(old_crtc_state))
503 tmp |= AUD_CONFIG_N_VALUE_INDEX;
504 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
507 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
508 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
509 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
510 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
512 mutex_unlock(&dev_priv->av_mutex);
515 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
516 const struct intel_crtc_state *crtc_state,
517 const struct drm_connector_state *conn_state)
519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
520 struct drm_connector *connector = conn_state->connector;
521 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
522 const u8 *eld = connector->eld;
526 drm_dbg_kms(&dev_priv->drm,
527 "Enable audio codec on transcoder %s, %u bytes ELD\n",
528 transcoder_name(cpu_transcoder), drm_eld_size(eld));
530 mutex_lock(&dev_priv->av_mutex);
532 /* Enable audio presence detect, invalidate ELD */
533 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
534 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
535 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
536 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
539 * FIXME: We're supposed to wait for vblank here, but we have vblanks
540 * disabled during the mode set. The proper fix would be to push the
541 * rest of the setup into a vblank work item, queued here, but the
542 * infrastructure is not there yet.
545 /* Reset ELD write address */
546 tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
547 tmp &= ~IBX_ELD_ADDRESS_MASK;
548 intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
550 /* Up to 84 bytes of hw ELD buffer */
551 len = min(drm_eld_size(eld), 84);
552 for (i = 0; i < len / 4; i++)
553 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder),
554 *((const u32 *)eld + i));
557 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
558 tmp |= AUDIO_ELD_VALID(cpu_transcoder);
559 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
561 /* Enable timestamps */
562 hsw_audio_config_update(encoder, crtc_state);
564 mutex_unlock(&dev_priv->av_mutex);
567 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
568 const struct intel_crtc_state *old_crtc_state,
569 const struct drm_connector_state *old_conn_state)
571 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
572 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
573 enum pipe pipe = crtc->pipe;
574 enum port port = encoder->port;
576 i915_reg_t aud_config, aud_cntrl_st2;
578 drm_dbg_kms(&dev_priv->drm,
579 "Disable audio codec on [ENCODER:%d:%s], pipe %c\n",
580 encoder->base.base.id, encoder->base.name,
583 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
586 if (HAS_PCH_IBX(dev_priv)) {
587 aud_config = IBX_AUD_CFG(pipe);
588 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
589 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
590 aud_config = VLV_AUD_CFG(pipe);
591 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
593 aud_config = CPT_AUD_CFG(pipe);
594 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
597 /* Disable timestamps */
598 tmp = intel_de_read(dev_priv, aud_config);
599 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
600 tmp |= AUD_CONFIG_N_PROG_ENABLE;
601 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
602 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
603 if (intel_crtc_has_dp_encoder(old_crtc_state))
604 tmp |= AUD_CONFIG_N_VALUE_INDEX;
605 intel_de_write(dev_priv, aud_config, tmp);
607 eldv = IBX_ELD_VALID(port);
610 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
612 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
615 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
616 const struct intel_crtc_state *crtc_state,
617 const struct drm_connector_state *conn_state)
619 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
620 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
621 struct drm_connector *connector = conn_state->connector;
622 enum pipe pipe = crtc->pipe;
623 enum port port = encoder->port;
624 const u8 *eld = connector->eld;
627 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
629 drm_dbg_kms(&dev_priv->drm,
630 "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n",
631 encoder->base.base.id, encoder->base.name,
632 pipe_name(pipe), drm_eld_size(eld));
634 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
638 * FIXME: We're supposed to wait for vblank here, but we have vblanks
639 * disabled during the mode set. The proper fix would be to push the
640 * rest of the setup into a vblank work item, queued here, but the
641 * infrastructure is not there yet.
644 if (HAS_PCH_IBX(dev_priv)) {
645 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
646 aud_config = IBX_AUD_CFG(pipe);
647 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
648 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
649 } else if (IS_VALLEYVIEW(dev_priv) ||
650 IS_CHERRYVIEW(dev_priv)) {
651 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
652 aud_config = VLV_AUD_CFG(pipe);
653 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
654 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
656 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
657 aud_config = CPT_AUD_CFG(pipe);
658 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
659 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
662 eldv = IBX_ELD_VALID(port);
665 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
667 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
669 /* Reset ELD write address */
670 tmp = intel_de_read(dev_priv, aud_cntl_st);
671 tmp &= ~IBX_ELD_ADDRESS_MASK;
672 intel_de_write(dev_priv, aud_cntl_st, tmp);
674 /* Up to 84 bytes of hw ELD buffer */
675 len = min(drm_eld_size(eld), 84);
676 for (i = 0; i < len / 4; i++)
677 intel_de_write(dev_priv, hdmiw_hdmiedid,
678 *((const u32 *)eld + i));
681 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
683 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
685 /* Enable timestamps */
686 tmp = intel_de_read(dev_priv, aud_config);
687 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
688 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
689 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
690 if (intel_crtc_has_dp_encoder(crtc_state))
691 tmp |= AUD_CONFIG_N_VALUE_INDEX;
693 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
694 intel_de_write(dev_priv, aud_config, tmp);
698 * intel_audio_codec_enable - Enable the audio codec for HD audio
699 * @encoder: encoder on which to enable audio
700 * @crtc_state: pointer to the current crtc state.
701 * @conn_state: pointer to the current connector state.
703 * The enable sequences may only be performed after enabling the transcoder and
704 * port, and after completed link training.
706 void intel_audio_codec_enable(struct intel_encoder *encoder,
707 const struct intel_crtc_state *crtc_state,
708 const struct drm_connector_state *conn_state)
710 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
711 struct i915_audio_component *acomp = dev_priv->audio_component;
712 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
713 struct drm_connector *connector = conn_state->connector;
714 const struct drm_display_mode *adjusted_mode =
715 &crtc_state->hw.adjusted_mode;
716 enum port port = encoder->port;
717 enum pipe pipe = crtc->pipe;
719 /* FIXME precompute the ELD in .compute_config() */
720 if (!connector->eld[0])
721 drm_dbg_kms(&dev_priv->drm,
722 "Bogus ELD on [CONNECTOR:%d:%s]\n",
723 connector->base.id, connector->name);
725 drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
728 encoder->base.base.id,
731 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
733 if (dev_priv->display.audio_codec_enable)
734 dev_priv->display.audio_codec_enable(encoder,
738 mutex_lock(&dev_priv->av_mutex);
739 encoder->audio_connector = connector;
741 /* referred in audio callbacks */
742 dev_priv->av_enc_map[pipe] = encoder;
743 mutex_unlock(&dev_priv->av_mutex);
745 if (acomp && acomp->base.audio_ops &&
746 acomp->base.audio_ops->pin_eld_notify) {
747 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
748 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
750 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
751 (int) port, (int) pipe);
754 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
755 crtc_state->port_clock,
756 intel_crtc_has_dp_encoder(crtc_state));
760 * intel_audio_codec_disable - Disable the audio codec for HD audio
761 * @encoder: encoder on which to disable audio
762 * @old_crtc_state: pointer to the old crtc state.
763 * @old_conn_state: pointer to the old connector state.
765 * The disable sequences must be performed before disabling the transcoder or
768 void intel_audio_codec_disable(struct intel_encoder *encoder,
769 const struct intel_crtc_state *old_crtc_state,
770 const struct drm_connector_state *old_conn_state)
772 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
773 struct i915_audio_component *acomp = dev_priv->audio_component;
774 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
775 enum port port = encoder->port;
776 enum pipe pipe = crtc->pipe;
778 if (dev_priv->display.audio_codec_disable)
779 dev_priv->display.audio_codec_disable(encoder,
783 mutex_lock(&dev_priv->av_mutex);
784 encoder->audio_connector = NULL;
785 dev_priv->av_enc_map[pipe] = NULL;
786 mutex_unlock(&dev_priv->av_mutex);
788 if (acomp && acomp->base.audio_ops &&
789 acomp->base.audio_ops->pin_eld_notify) {
790 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
791 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
793 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
794 (int) port, (int) pipe);
797 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
801 * intel_init_audio_hooks - Set up chip specific audio hooks
802 * @dev_priv: device private
804 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
806 if (IS_G4X(dev_priv)) {
807 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
808 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
809 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
810 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
811 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
812 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
813 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
814 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
815 } else if (HAS_PCH_SPLIT(dev_priv)) {
816 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
817 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
821 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
822 struct intel_crtc *crtc,
825 struct intel_cdclk_state *cdclk_state;
828 /* need to hold at least one crtc lock for the global state */
829 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
833 cdclk_state = intel_atomic_get_cdclk_state(state);
834 if (IS_ERR(cdclk_state))
835 return PTR_ERR(cdclk_state);
837 cdclk_state->force_min_cdclk_changed = true;
838 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
840 ret = intel_atomic_lock_global_state(&cdclk_state->base);
844 return drm_atomic_commit(&state->base);
847 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
850 struct drm_modeset_acquire_ctx ctx;
851 struct drm_atomic_state *state;
852 struct intel_crtc *crtc;
855 crtc = intel_get_first_crtc(dev_priv);
859 drm_modeset_acquire_init(&ctx, 0);
860 state = drm_atomic_state_alloc(&dev_priv->drm);
861 if (drm_WARN_ON(&dev_priv->drm, !state))
864 state->acquire_ctx = &ctx;
867 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
869 if (ret == -EDEADLK) {
870 drm_atomic_state_clear(state);
871 drm_modeset_backoff(&ctx);
875 drm_WARN_ON(&dev_priv->drm, ret);
877 drm_atomic_state_put(state);
879 drm_modeset_drop_locks(&ctx);
880 drm_modeset_acquire_fini(&ctx);
883 static unsigned long i915_audio_component_get_power(struct device *kdev)
885 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
888 /* Catch potential impedance mismatches before they occur! */
889 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
891 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
893 if (dev_priv->audio_power_refcount++ == 0) {
894 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
895 intel_de_write(dev_priv, AUD_FREQ_CNTRL,
896 dev_priv->audio_freq_cntrl);
897 drm_dbg_kms(&dev_priv->drm,
898 "restored AUD_FREQ_CNTRL to 0x%x\n",
899 dev_priv->audio_freq_cntrl);
902 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
903 if (IS_GEMINILAKE(dev_priv))
904 glk_force_audio_cdclk(dev_priv, true);
906 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
907 intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
908 (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
914 static void i915_audio_component_put_power(struct device *kdev,
915 unsigned long cookie)
917 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
919 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
920 if (--dev_priv->audio_power_refcount == 0)
921 if (IS_GEMINILAKE(dev_priv))
922 glk_force_audio_cdclk(dev_priv, false);
924 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
927 static void i915_audio_component_codec_wake_override(struct device *kdev,
930 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
931 unsigned long cookie;
934 if (!IS_GEN(dev_priv, 9))
937 cookie = i915_audio_component_get_power(kdev);
940 * Enable/disable generating the codec wake signal, overriding the
941 * internal logic to generate the codec wake to controller.
943 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
944 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
945 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
946 usleep_range(1000, 1500);
949 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
950 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
951 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
952 usleep_range(1000, 1500);
955 i915_audio_component_put_power(kdev, cookie);
958 /* Get CDCLK in kHz */
959 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
961 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
963 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
966 return dev_priv->cdclk.hw.cdclk;
970 * get the intel_encoder according to the parameter port and pipe
971 * intel_encoder is saved by the index of pipe
972 * MST & (pipe >= 0): return the av_enc_map[pipe],
973 * when port is matched
974 * MST & (pipe < 0): this is invalid
975 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
976 * will get the right intel_encoder with port matched
977 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
979 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
982 struct intel_encoder *encoder;
986 if (drm_WARN_ON(&dev_priv->drm,
987 pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
990 encoder = dev_priv->av_enc_map[pipe];
992 * when bootup, audio driver may not know it is
993 * MST or not. So it will poll all the port & pipe
996 if (encoder != NULL && encoder->port == port &&
997 encoder->type == INTEL_OUTPUT_DP_MST)
1005 for_each_pipe(dev_priv, pipe) {
1006 encoder = dev_priv->av_enc_map[pipe];
1007 if (encoder == NULL)
1010 if (encoder->type == INTEL_OUTPUT_DP_MST)
1013 if (port == encoder->port)
1020 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1023 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1024 struct i915_audio_component *acomp = dev_priv->audio_component;
1025 struct intel_encoder *encoder;
1026 struct intel_crtc *crtc;
1027 unsigned long cookie;
1030 if (!HAS_DDI(dev_priv))
1033 cookie = i915_audio_component_get_power(kdev);
1034 mutex_lock(&dev_priv->av_mutex);
1036 /* 1. get the pipe */
1037 encoder = get_saved_enc(dev_priv, port, pipe);
1038 if (!encoder || !encoder->base.crtc) {
1039 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1045 crtc = to_intel_crtc(encoder->base.crtc);
1047 /* port must be valid now, otherwise the pipe will be invalid */
1048 acomp->aud_sample_rate[port] = rate;
1050 hsw_audio_config_update(encoder, crtc->config);
1053 mutex_unlock(&dev_priv->av_mutex);
1054 i915_audio_component_put_power(kdev, cookie);
1058 static int i915_audio_component_get_eld(struct device *kdev, int port,
1059 int pipe, bool *enabled,
1060 unsigned char *buf, int max_bytes)
1062 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1063 struct intel_encoder *intel_encoder;
1067 mutex_lock(&dev_priv->av_mutex);
1069 intel_encoder = get_saved_enc(dev_priv, port, pipe);
1070 if (!intel_encoder) {
1071 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1073 mutex_unlock(&dev_priv->av_mutex);
1078 *enabled = intel_encoder->audio_connector != NULL;
1080 eld = intel_encoder->audio_connector->eld;
1081 ret = drm_eld_size(eld);
1082 memcpy(buf, eld, min(max_bytes, ret));
1085 mutex_unlock(&dev_priv->av_mutex);
1089 static const struct drm_audio_component_ops i915_audio_component_ops = {
1090 .owner = THIS_MODULE,
1091 .get_power = i915_audio_component_get_power,
1092 .put_power = i915_audio_component_put_power,
1093 .codec_wake_override = i915_audio_component_codec_wake_override,
1094 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1095 .sync_audio_rate = i915_audio_component_sync_audio_rate,
1096 .get_eld = i915_audio_component_get_eld,
1099 static int i915_audio_component_bind(struct device *i915_kdev,
1100 struct device *hda_kdev, void *data)
1102 struct i915_audio_component *acomp = data;
1103 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1106 if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev))
1109 if (drm_WARN_ON(&dev_priv->drm,
1110 !device_link_add(hda_kdev, i915_kdev,
1111 DL_FLAG_STATELESS)))
1114 drm_modeset_lock_all(&dev_priv->drm);
1115 acomp->base.ops = &i915_audio_component_ops;
1116 acomp->base.dev = i915_kdev;
1117 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1118 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1119 acomp->aud_sample_rate[i] = 0;
1120 dev_priv->audio_component = acomp;
1121 drm_modeset_unlock_all(&dev_priv->drm);
1126 static void i915_audio_component_unbind(struct device *i915_kdev,
1127 struct device *hda_kdev, void *data)
1129 struct i915_audio_component *acomp = data;
1130 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1132 drm_modeset_lock_all(&dev_priv->drm);
1133 acomp->base.ops = NULL;
1134 acomp->base.dev = NULL;
1135 dev_priv->audio_component = NULL;
1136 drm_modeset_unlock_all(&dev_priv->drm);
1138 device_link_remove(hda_kdev, i915_kdev);
1141 static const struct component_ops i915_audio_component_bind_ops = {
1142 .bind = i915_audio_component_bind,
1143 .unbind = i915_audio_component_unbind,
1147 * i915_audio_component_init - initialize and register the audio component
1148 * @dev_priv: i915 device instance
1150 * This will register with the component framework a child component which
1151 * will bind dynamically to the snd_hda_intel driver's corresponding master
1152 * component when the latter is registered. During binding the child
1153 * initializes an instance of struct i915_audio_component which it receives
1154 * from the master. The master can then start to use the interface defined by
1155 * this struct. Each side can break the binding at any point by deregistering
1156 * its own component after which each side's component unbind callback is
1159 * We ignore any error during registration and continue with reduced
1160 * functionality (i.e. without HDMI audio).
1162 static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1166 ret = component_add_typed(dev_priv->drm.dev,
1167 &i915_audio_component_bind_ops,
1168 I915_COMPONENT_AUDIO);
1170 drm_err(&dev_priv->drm,
1171 "failed to add audio component (%d)\n", ret);
1172 /* continue with reduced functionality */
1176 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
1177 dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,
1179 drm_dbg_kms(&dev_priv->drm,
1180 "init value of AUD_FREQ_CNTRL of 0x%x\n",
1181 dev_priv->audio_freq_cntrl);
1184 dev_priv->audio_component_registered = true;
1188 * i915_audio_component_cleanup - deregister the audio component
1189 * @dev_priv: i915 device instance
1191 * Deregisters the audio component, breaking any existing binding to the
1192 * corresponding snd_hda_intel driver's master component.
1194 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1196 if (!dev_priv->audio_component_registered)
1199 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1200 dev_priv->audio_component_registered = false;
1204 * intel_audio_init() - Initialize the audio driver either using
1205 * component framework or using lpe audio bridge
1206 * @dev_priv: the i915 drm device private data
1209 void intel_audio_init(struct drm_i915_private *dev_priv)
1211 if (intel_lpe_audio_init(dev_priv) < 0)
1212 i915_audio_component_init(dev_priv);
1216 * intel_audio_deinit() - deinitialize the audio driver
1217 * @dev_priv: the i915 drm device private data
1220 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1222 if ((dev_priv)->lpe_audio.platdev != NULL)
1223 intel_lpe_audio_teardown(dev_priv);
1225 i915_audio_component_cleanup(dev_priv);