drivers/gpu/drm/i915/display/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/component.h>
  25 #include <linux/kernel.h>
  26
  27 #include <drm/drm_edid.h>
  28 #include <drm/i915_component.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_atomic.h"
  32 #include "intel_audio.h"
  33 #include "intel_cdclk.h"
  34 #include "intel_display_types.h"
  35 #include "intel_lpe_audio.h"
  36
  37 /**
  38  * DOC: High Definition Audio over HDMI and Display Port
  39  *
  40  * The graphics and audio drivers together support High Definition Audio over
  41  * HDMI and Display Port. The audio programming sequences are divided into audio
  42  * codec and controller enable and disable sequences. The graphics driver
  43  * handles the audio codec sequences, while the audio driver handles the audio
  44  * controller sequences.
  45  *
  46  * The disable sequences must be performed before disabling the transcoder or
  47  * port. The enable sequences may only be performed after enabling the
  48  * transcoder and port, and after completed link training. Therefore the audio
  49  * enable/disable sequences are part of the modeset sequence.
  50  *
  51  * The codec and controller sequences could be done either parallel or serial,
  52  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  53  * driver that the controller sequence should start. Indeed, most of the
  54  * co-operation between the graphics and audio drivers is handled via audio
  55  * related registers. (The notable exception is the power management, not
  56  * covered here.)
  57  *
  58  * The struct &i915_audio_component is used to interact between the graphics
  59  * and audio drivers. The struct &i915_audio_component_ops @ops in it is
  60  * defined in graphics driver and called in audio driver. The
  61  * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
  62  */
  63
  64 /* DP N/M table */
  65 #define LC_810M 810000
  66 #define LC_540M 540000
  67 #define LC_270M 270000
  68 #define LC_162M 162000
  69
  70 struct dp_aud_n_m {
  71         int sample_rate;
  72         int clock;
  73         u16 m;
  74         u16 n;
  75 };
  76
  77 struct hdmi_aud_ncts {
  78         int sample_rate;
  79         int clock;
  80         int n;
  81         int cts;
  82 };
  83
  84 /* Values according to DP 1.4 Table 2-104 */
  85 static const struct dp_aud_n_m dp_aud_n_m[] = {
  86         { 32000, LC_162M, 1024, 10125 },
  87         { 44100, LC_162M, 784, 5625 },
  88         { 48000, LC_162M, 512, 3375 },
  89         { 64000, LC_162M, 2048, 10125 },
  90         { 88200, LC_162M, 1568, 5625 },
  91         { 96000, LC_162M, 1024, 3375 },
  92         { 128000, LC_162M, 4096, 10125 },
  93         { 176400, LC_162M, 3136, 5625 },
  94         { 192000, LC_162M, 2048, 3375 },
  95         { 32000, LC_270M, 1024, 16875 },
  96         { 44100, LC_270M, 784, 9375 },
  97         { 48000, LC_270M, 512, 5625 },
  98         { 64000, LC_270M, 2048, 16875 },
  99         { 88200, LC_270M, 1568, 9375 },
 100         { 96000, LC_270M, 1024, 5625 },
 101         { 128000, LC_270M, 4096, 16875 },
 102         { 176400, LC_270M, 3136, 9375 },
 103         { 192000, LC_270M, 2048, 5625 },
 104         { 32000, LC_540M, 1024, 33750 },
 105         { 44100, LC_540M, 784, 18750 },
 106         { 48000, LC_540M, 512, 11250 },
 107         { 64000, LC_540M, 2048, 33750 },
 108         { 88200, LC_540M, 1568, 18750 },
 109         { 96000, LC_540M, 1024, 11250 },
 110         { 128000, LC_540M, 4096, 33750 },
 111         { 176400, LC_540M, 3136, 18750 },
 112         { 192000, LC_540M, 2048, 11250 },
 113         { 32000, LC_810M, 1024, 50625 },
 114         { 44100, LC_810M, 784, 28125 },
 115         { 48000, LC_810M, 512, 16875 },
 116         { 64000, LC_810M, 2048, 50625 },
 117         { 88200, LC_810M, 1568, 28125 },
 118         { 96000, LC_810M, 1024, 16875 },
 119         { 128000, LC_810M, 4096, 50625 },
 120         { 176400, LC_810M, 3136, 28125 },
 121         { 192000, LC_810M, 2048, 16875 },
 122 };
 123
 124 static const struct dp_aud_n_m *
 125 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
 126 {
 127         int i;
 128
 129         for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
 130                 if (rate == dp_aud_n_m[i].sample_rate &&
 131                     crtc_state->port_clock == dp_aud_n_m[i].clock)
 132                         return &dp_aud_n_m[i];
 133         }
 134
 135         return NULL;
 136 }
 137
 138 static const struct {
 139         int clock;
 140         u32 config;
 141 } hdmi_audio_clock[] = {
 142         { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
 143         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
 144         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
 145         { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
 146         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
 147         { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
 148         { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
 149         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
 150         { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
 151         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
 152         { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
 153         { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
 154         { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
 155         { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
 156 };
 157
 158 /* HDMI N/CTS table */
 159 #define TMDS_297M 297000
 160 #define TMDS_296M 296703
 161 #define TMDS_594M 594000
 162 #define TMDS_593M 593407
 163
 164 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
 165         { 32000, TMDS_296M, 5824, 421875 },
 166         { 32000, TMDS_297M, 3072, 222750 },
 167         { 32000, TMDS_593M, 5824, 843750 },
 168         { 32000, TMDS_594M, 3072, 445500 },
 169         { 44100, TMDS_296M, 4459, 234375 },
 170         { 44100, TMDS_297M, 4704, 247500 },
 171         { 44100, TMDS_593M, 8918, 937500 },
 172         { 44100, TMDS_594M, 9408, 990000 },
 173         { 88200, TMDS_296M, 8918, 234375 },
 174         { 88200, TMDS_297M, 9408, 247500 },
 175         { 88200, TMDS_593M, 17836, 937500 },
 176         { 88200, TMDS_594M, 18816, 990000 },
 177         { 176400, TMDS_296M, 17836, 234375 },
 178         { 176400, TMDS_297M, 18816, 247500 },
 179         { 176400, TMDS_593M, 35672, 937500 },
 180         { 176400, TMDS_594M, 37632, 990000 },
 181         { 48000, TMDS_296M, 5824, 281250 },
 182         { 48000, TMDS_297M, 5120, 247500 },
 183         { 48000, TMDS_593M, 5824, 562500 },
 184         { 48000, TMDS_594M, 6144, 594000 },
 185         { 96000, TMDS_296M, 11648, 281250 },
 186         { 96000, TMDS_297M, 10240, 247500 },
 187         { 96000, TMDS_593M, 11648, 562500 },
 188         { 96000, TMDS_594M, 12288, 594000 },
 189         { 192000, TMDS_296M, 23296, 281250 },
 190         { 192000, TMDS_297M, 20480, 247500 },
 191         { 192000, TMDS_593M, 23296, 562500 },
 192         { 192000, TMDS_594M, 24576, 594000 },
 193 };
 194
 195 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
 196 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
 197 #define TMDS_371M 371250
 198 #define TMDS_370M 370878
 199
 200 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
 201         { 32000, TMDS_370M, 5824, 527344 },
 202         { 32000, TMDS_371M, 6144, 556875 },
 203         { 44100, TMDS_370M, 8918, 585938 },
 204         { 44100, TMDS_371M, 4704, 309375 },
 205         { 88200, TMDS_370M, 17836, 585938 },
 206         { 88200, TMDS_371M, 9408, 309375 },
 207         { 176400, TMDS_370M, 35672, 585938 },
 208         { 176400, TMDS_371M, 18816, 309375 },
 209         { 48000, TMDS_370M, 11648, 703125 },
 210         { 48000, TMDS_371M, 5120, 309375 },
 211         { 96000, TMDS_370M, 23296, 703125 },
 212         { 96000, TMDS_371M, 10240, 309375 },
 213         { 192000, TMDS_370M, 46592, 703125 },
 214         { 192000, TMDS_371M, 20480, 309375 },
 215 };
 216
 217 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
 218 #define TMDS_445_5M 445500
 219 #define TMDS_445M 445054
 220
 221 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
 222         { 32000, TMDS_445M, 5824, 632813 },
 223         { 32000, TMDS_445_5M, 4096, 445500 },
 224         { 44100, TMDS_445M, 8918, 703125 },
 225         { 44100, TMDS_445_5M, 4704, 371250 },
 226         { 88200, TMDS_445M, 17836, 703125 },
 227         { 88200, TMDS_445_5M, 9408, 371250 },
 228         { 176400, TMDS_445M, 35672, 703125 },
 229         { 176400, TMDS_445_5M, 18816, 371250 },
 230         { 48000, TMDS_445M, 5824, 421875 },
 231         { 48000, TMDS_445_5M, 5120, 371250 },
 232         { 96000, TMDS_445M, 11648, 421875 },
 233         { 96000, TMDS_445_5M, 10240, 371250 },
 234         { 192000, TMDS_445M, 23296, 421875 },
 235         { 192000, TMDS_445_5M, 20480, 371250 },
 236 };
 237
 238 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 239 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
 240 {
 241         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 242         const struct drm_display_mode *adjusted_mode =
 243                 &crtc_state->hw.adjusted_mode;
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 247                 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 248                         break;
 249         }
 250
 251         if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
 252                 i = ARRAY_SIZE(hdmi_audio_clock);
 253
 254         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 255                 drm_dbg_kms(&dev_priv->drm,
 256                             "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 257                             adjusted_mode->crtc_clock);
 258                 i = 1;
 259         }
 260
 261         drm_dbg_kms(&dev_priv->drm,
 262                     "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 263                     hdmi_audio_clock[i].clock,
 264                     hdmi_audio_clock[i].config);
 265
 266         return hdmi_audio_clock[i].config;
 267 }
 268
 269 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
 270                                    int rate)
 271 {
 272         const struct hdmi_aud_ncts *hdmi_ncts_table;
 273         int i, size;
 274
 275         if (crtc_state->pipe_bpp == 36) {
 276                 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
 277                 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
 278         } else if (crtc_state->pipe_bpp == 30) {
 279                 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
 280                 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
 281         } else {
 282                 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
 283                 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
 284         }
 285
 286         for (i = 0; i < size; i++) {
 287                 if (rate == hdmi_ncts_table[i].sample_rate &&
 288                     crtc_state->port_clock == hdmi_ncts_table[i].clock) {
 289                         return hdmi_ncts_table[i].n;
 290                 }
 291         }
 292         return 0;
 293 }
 294
 295 static bool intel_eld_uptodate(struct drm_connector *connector,
 296                                i915_reg_t reg_eldv, u32 bits_eldv,
 297                                i915_reg_t reg_elda, u32 bits_elda,
 298                                i915_reg_t reg_edid)
 299 {
 300         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 301         const u8 *eld = connector->eld;
 302         u32 tmp;
 303         int i;
 304
 305         tmp = intel_de_read(dev_priv, reg_eldv);
 306         tmp &= bits_eldv;
 307
 308         if (!tmp)
 309                 return false;
 310
 311         tmp = intel_de_read(dev_priv, reg_elda);
 312         tmp &= ~bits_elda;
 313         intel_de_write(dev_priv, reg_elda, tmp);
 314
 315         for (i = 0; i < drm_eld_size(eld) / 4; i++)
 316                 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i))
 317                         return false;
 318
 319         return true;
 320 }
 321
 322 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
 323                                     const struct intel_crtc_state *old_crtc_state,
 324                                     const struct drm_connector_state *old_conn_state)
 325 {
 326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 327         u32 eldv, tmp;
 328
 329         drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n");
 330
 331         tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
 332         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 333                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 334         else
 335                 eldv = G4X_ELDV_DEVCTG;
 336
 337         /* Invalidate ELD */
 338         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 339         tmp &= ~eldv;
 340         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 341 }
 342
 343 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
 344                                    const struct intel_crtc_state *crtc_state,
 345                                    const struct drm_connector_state *conn_state)
 346 {
 347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 348         struct drm_connector *connector = conn_state->connector;
 349         const u8 *eld = connector->eld;
 350         u32 eldv;
 351         u32 tmp;
 352         int len, i;
 353
 354         drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n",
 355                     drm_eld_size(eld));
 356
 357         tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
 358         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 359                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 360         else
 361                 eldv = G4X_ELDV_DEVCTG;
 362
 363         if (intel_eld_uptodate(connector,
 364                                G4X_AUD_CNTL_ST, eldv,
 365                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 366                                G4X_HDMIW_HDMIEDID))
 367                 return;
 368
 369         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 370         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 371         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 372         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 373
 374         len = min(drm_eld_size(eld) / 4, len);
 375         drm_dbg(&dev_priv->drm, "ELD size %d\n", len);
 376         for (i = 0; i < len; i++)
 377                 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
 378                                *((const u32 *)eld + i));
 379
 380         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 381         tmp |= eldv;
 382         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 383 }
 384
 385 static void
 386 hsw_dp_audio_config_update(struct intel_encoder *encoder,
 387                            const struct intel_crtc_state *crtc_state)
 388 {
 389         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 390         struct i915_audio_component *acomp = dev_priv->audio_component;
 391         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 392         enum port port = encoder->port;
 393         const struct dp_aud_n_m *nm;
 394         int rate;
 395         u32 tmp;
 396
 397         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 398         nm = audio_config_dp_get_n_m(crtc_state, rate);
 399         if (nm)
 400                 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m,
 401                             nm->n);
 402         else
 403                 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n");
 404
 405         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 406         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 407         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 408         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 409         tmp |= AUD_CONFIG_N_VALUE_INDEX;
 410
 411         if (nm) {
 412                 tmp &= ~AUD_CONFIG_N_MASK;
 413                 tmp |= AUD_CONFIG_N(nm->n);
 414                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 415         }
 416
 417         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 418
 419         tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 420         tmp &= ~AUD_CONFIG_M_MASK;
 421         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 422         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 423
 424         if (nm) {
 425                 tmp |= nm->m;
 426                 tmp |= AUD_M_CTS_M_VALUE_INDEX;
 427                 tmp |= AUD_M_CTS_M_PROG_ENABLE;
 428         }
 429
 430         intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 431 }
 432
 433 static void
 434 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
 435                              const struct intel_crtc_state *crtc_state)
 436 {
 437         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 438         struct i915_audio_component *acomp = dev_priv->audio_component;
 439         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 440         enum port port = encoder->port;
 441         int n, rate;
 442         u32 tmp;
 443
 444         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 445
 446         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 447         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 448         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 449         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 450         tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 451
 452         n = audio_config_hdmi_get_n(crtc_state, rate);
 453         if (n != 0) {
 454                 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n);
 455
 456                 tmp &= ~AUD_CONFIG_N_MASK;
 457                 tmp |= AUD_CONFIG_N(n);
 458                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 459         } else {
 460                 drm_dbg_kms(&dev_priv->drm, "using automatic N\n");
 461         }
 462
 463         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 464
 465         /*
 466          * Let's disable "Enable CTS or M Prog bit"
 467          * and let HW calculate the value
 468          */
 469         tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 470         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 471         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 472         intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 473 }
 474
 475 static void
 476 hsw_audio_config_update(struct intel_encoder *encoder,
 477                         const struct intel_crtc_state *crtc_state)
 478 {
 479         if (intel_crtc_has_dp_encoder(crtc_state))
 480                 hsw_dp_audio_config_update(encoder, crtc_state);
 481         else
 482                 hsw_hdmi_audio_config_update(encoder, crtc_state);
 483 }
 484
 485 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
 486                                     const struct intel_crtc_state *old_crtc_state,
 487                                     const struct drm_connector_state *old_conn_state)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 490         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 491         u32 tmp;
 492
 493         drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n",
 494                     transcoder_name(cpu_transcoder));
 495
 496         mutex_lock(&dev_priv->av_mutex);
 497
 498         /* Disable timestamps */
 499         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 500         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 501         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 502         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 503         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 504         if (intel_crtc_has_dp_encoder(old_crtc_state))
 505                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 506         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 507
 508         /* Invalidate ELD */
 509         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 510         tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
 511         tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
 512         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 513
 514         mutex_unlock(&dev_priv->av_mutex);
 515 }
 516
 517 /* Add a factor to take care of rounding and truncations */
 518 #define ROUNDING_FACTOR 10000
 519
 520 static unsigned int get_hblank_early_enable_config(struct intel_encoder *encoder,
 521                                                    const struct intel_crtc_state *crtc_state)
 522 {
 523         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 524         unsigned int link_clks_available, link_clks_required;
 525         unsigned int tu_data, tu_line, link_clks_active;
 526         unsigned int hblank_rise, hblank_early_prog;
 527         unsigned int h_active, h_total, hblank_delta, pixel_clk, v_total;
 528         unsigned int fec_coeff, refresh_rate, cdclk, vdsc_bpp;
 529
 530         h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 531         h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 532         v_total = crtc_state->hw.adjusted_mode.crtc_vtotal;
 533         pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
 534         refresh_rate = crtc_state->hw.adjusted_mode.vrefresh;
 535         vdsc_bpp = crtc_state->dsc.compressed_bpp;
 536         cdclk = i915->cdclk.hw.cdclk;
 537         /* fec= 0.972261, using rounding multiplier of 1000000 */
 538         fec_coeff = 972261;
 539
 540         drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
 541                     "lanes = %u vdsc_bpp = %u cdclk = %u\n",
 542                     h_active, crtc_state->port_clock, crtc_state->lane_count,
 543                     vdsc_bpp, cdclk);
 544
 545         link_clks_available = ((((h_total - h_active) *
 546                                ((crtc_state->port_clock * ROUNDING_FACTOR) /
 547                                 pixel_clk)) / ROUNDING_FACTOR) - 28);
 548
 549         link_clks_required = DIV_ROUND_UP(192000, (refresh_rate *
 550                                           v_total)) * ((48 /
 551                                           crtc_state->lane_count) + 2);
 552
 553         if (link_clks_available > link_clks_required)
 554                 hblank_delta = 32;
 555         else
 556                 hblank_delta = DIV_ROUND_UP(((((5 * ROUNDING_FACTOR) /
 557                                             crtc_state->port_clock) + ((5 *
 558                                             ROUNDING_FACTOR) /
 559                                             cdclk)) * pixel_clk),
 560                                             ROUNDING_FACTOR);
 561
 562         tu_data = (pixel_clk * vdsc_bpp * 8) / ((crtc_state->port_clock *
 563                    crtc_state->lane_count * fec_coeff) / 1000000);
 564         tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
 565                    1000000) / (64 * pixel_clk));
 566         link_clks_active  = (tu_line - 1) * 64 + tu_data;
 567
 568         hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
 569                         250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
 570                         crtc_state->port_clock)) / ROUNDING_FACTOR;
 571
 572         hblank_early_prog = h_active - hblank_rise + hblank_delta;
 573
 574         return hblank_early_prog;
 575 }
 576
 577 static unsigned int get_sample_room_req_config(const struct intel_crtc_state *crtc_state)
 578 {
 579         unsigned int h_active, h_total, pixel_clk;
 580         unsigned int samples_room;
 581
 582         h_active = crtc_state->hw.adjusted_mode.hdisplay;
 583         h_total = crtc_state->hw.adjusted_mode.htotal;
 584         pixel_clk = crtc_state->hw.adjusted_mode.clock;
 585
 586         samples_room = ((((h_total - h_active) * ((crtc_state->port_clock *
 587                         ROUNDING_FACTOR) / pixel_clk)) /
 588                         ROUNDING_FACTOR) - 12) / ((48 /
 589                         crtc_state->lane_count) + 2);
 590
 591         return samples_room;
 592 }
 593
 594 static void enable_audio_dsc_wa(struct intel_encoder *encoder,
 595                                 const struct intel_crtc_state *crtc_state)
 596 {
 597         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 598         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 599         enum pipe pipe = crtc->pipe;
 600         unsigned int hblank_early_prog, samples_room, h_active;
 601         unsigned int val;
 602
 603         if (INTEL_GEN(i915) < 11)
 604                 return;
 605
 606         h_active = crtc_state->hw.adjusted_mode.hdisplay;
 607
 608         if (!(h_active && crtc_state->port_clock && crtc_state->lane_count &&
 609               crtc_state->dsc.compressed_bpp && i915->cdclk.hw.cdclk)) {
 610                 drm_err(&i915->drm, "Null Params rcvd for hblank early enabling\n");
 611                 WARN_ON(1);
 612                 return;
 613         }
 614
 615         val = intel_de_read(i915, AUD_CONFIG_BE);
 616
 617         if (INTEL_GEN(i915) == 11)
 618                 val |= HBLANK_EARLY_ENABLE_ICL(pipe);
 619         else if (INTEL_GEN(i915) >= 12)
 620                 val |= HBLANK_EARLY_ENABLE_TGL(pipe);
 621
 622         if (crtc_state->dsc.compression_enable &&
 623             (crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
 624             crtc_state->hw.adjusted_mode.vdisplay >= 2160)) {
 625                 /* Get hblank early enable value required */
 626                 hblank_early_prog = get_hblank_early_enable_config(encoder,
 627                                                                    crtc_state);
 628                 if (hblank_early_prog < 32) {
 629                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 630                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32);
 631                 } else if (hblank_early_prog < 64) {
 632                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 633                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64);
 634                 } else if (hblank_early_prog < 96) {
 635                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 636                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96);
 637                 } else {
 638                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 639                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128);
 640                 }
 641
 642                 /* Get samples room value required */
 643                 samples_room = get_sample_room_req_config(crtc_state);
 644                 if (samples_room < 3) {
 645                         val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
 646                         val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
 647                 } else {
 648                         /* Program 0 i.e "All Samples available in buffer" */
 649                         val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
 650                         val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
 651                 }
 652         }
 653
 654         intel_de_write(i915, AUD_CONFIG_BE, val);
 655 }
 656
 657 #undef ROUNDING_FACTOR
 658
 659 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
 660                                    const struct intel_crtc_state *crtc_state,
 661                                    const struct drm_connector_state *conn_state)
 662 {
 663         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 664         struct drm_connector *connector = conn_state->connector;
 665         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 666         const u8 *eld = connector->eld;
 667         u32 tmp;
 668         int len, i;
 669
 670         drm_dbg_kms(&dev_priv->drm,
 671                     "Enable audio codec on transcoder %s, %u bytes ELD\n",
 672                      transcoder_name(cpu_transcoder), drm_eld_size(eld));
 673
 674         mutex_lock(&dev_priv->av_mutex);
 675
 676         /* Enable Audio WA for 4k DSC usecases */
 677         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
 678                 enable_audio_dsc_wa(encoder, crtc_state);
 679
 680         /* Enable audio presence detect, invalidate ELD */
 681         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 682         tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
 683         tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
 684         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 685
 686         /*
 687          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 688          * disabled during the mode set. The proper fix would be to push the
 689          * rest of the setup into a vblank work item, queued here, but the
 690          * infrastructure is not there yet.
 691          */
 692
 693         /* Reset ELD write address */
 694         tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
 695         tmp &= ~IBX_ELD_ADDRESS_MASK;
 696         intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
 697
 698         /* Up to 84 bytes of hw ELD buffer */
 699         len = min(drm_eld_size(eld), 84);
 700         for (i = 0; i < len / 4; i++)
 701                 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder),
 702                                *((const u32 *)eld + i));
 703
 704         /* ELD valid */
 705         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 706         tmp |= AUDIO_ELD_VALID(cpu_transcoder);
 707         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 708
 709         /* Enable timestamps */
 710         hsw_audio_config_update(encoder, crtc_state);
 711
 712         mutex_unlock(&dev_priv->av_mutex);
 713 }
 714
 715 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
 716                                     const struct intel_crtc_state *old_crtc_state,
 717                                     const struct drm_connector_state *old_conn_state)
 718 {
 719         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 720         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 721         enum pipe pipe = crtc->pipe;
 722         enum port port = encoder->port;
 723         u32 tmp, eldv;
 724         i915_reg_t aud_config, aud_cntrl_st2;
 725
 726         drm_dbg_kms(&dev_priv->drm,
 727                     "Disable audio codec on [ENCODER:%d:%s], pipe %c\n",
 728                      encoder->base.base.id, encoder->base.name,
 729                      pipe_name(pipe));
 730
 731         if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
 732                 return;
 733
 734         if (HAS_PCH_IBX(dev_priv)) {
 735                 aud_config = IBX_AUD_CFG(pipe);
 736                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 737         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 738                 aud_config = VLV_AUD_CFG(pipe);
 739                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 740         } else {
 741                 aud_config = CPT_AUD_CFG(pipe);
 742                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 743         }
 744
 745         /* Disable timestamps */
 746         tmp = intel_de_read(dev_priv, aud_config);
 747         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 748         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 749         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 750         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 751         if (intel_crtc_has_dp_encoder(old_crtc_state))
 752                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 753         intel_de_write(dev_priv, aud_config, tmp);
 754
 755         eldv = IBX_ELD_VALID(port);
 756
 757         /* Invalidate ELD */
 758         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 759         tmp &= ~eldv;
 760         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 761 }
 762
 763 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
 764                                    const struct intel_crtc_state *crtc_state,
 765                                    const struct drm_connector_state *conn_state)
 766 {
 767         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 768         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 769         struct drm_connector *connector = conn_state->connector;
 770         enum pipe pipe = crtc->pipe;
 771         enum port port = encoder->port;
 772         const u8 *eld = connector->eld;
 773         u32 tmp, eldv;
 774         int len, i;
 775         i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 776
 777         drm_dbg_kms(&dev_priv->drm,
 778                     "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n",
 779                     encoder->base.base.id, encoder->base.name,
 780                     pipe_name(pipe), drm_eld_size(eld));
 781
 782         if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
 783                 return;
 784
 785         /*
 786          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 787          * disabled during the mode set. The proper fix would be to push the
 788          * rest of the setup into a vblank work item, queued here, but the
 789          * infrastructure is not there yet.
 790          */
 791
 792         if (HAS_PCH_IBX(dev_priv)) {
 793                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 794                 aud_config = IBX_AUD_CFG(pipe);
 795                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 796                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 797         } else if (IS_VALLEYVIEW(dev_priv) ||
 798                    IS_CHERRYVIEW(dev_priv)) {
 799                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 800                 aud_config = VLV_AUD_CFG(pipe);
 801                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 802                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 803         } else {
 804                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 805                 aud_config = CPT_AUD_CFG(pipe);
 806                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 807                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 808         }
 809
 810         eldv = IBX_ELD_VALID(port);
 811
 812         /* Invalidate ELD */
 813         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 814         tmp &= ~eldv;
 815         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 816
 817         /* Reset ELD write address */
 818         tmp = intel_de_read(dev_priv, aud_cntl_st);
 819         tmp &= ~IBX_ELD_ADDRESS_MASK;
 820         intel_de_write(dev_priv, aud_cntl_st, tmp);
 821
 822         /* Up to 84 bytes of hw ELD buffer */
 823         len = min(drm_eld_size(eld), 84);
 824         for (i = 0; i < len / 4; i++)
 825                 intel_de_write(dev_priv, hdmiw_hdmiedid,
 826                                *((const u32 *)eld + i));
 827
 828         /* ELD valid */
 829         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 830         tmp |= eldv;
 831         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 832
 833         /* Enable timestamps */
 834         tmp = intel_de_read(dev_priv, aud_config);
 835         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 836         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 837         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 838         if (intel_crtc_has_dp_encoder(crtc_state))
 839                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 840         else
 841                 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 842         intel_de_write(dev_priv, aud_config, tmp);
 843 }
 844
 845 /**
 846  * intel_audio_codec_enable - Enable the audio codec for HD audio
 847  * @encoder: encoder on which to enable audio
 848  * @crtc_state: pointer to the current crtc state.
 849  * @conn_state: pointer to the current connector state.
 850  *
 851  * The enable sequences may only be performed after enabling the transcoder and
 852  * port, and after completed link training.
 853  */
 854 void intel_audio_codec_enable(struct intel_encoder *encoder,
 855                               const struct intel_crtc_state *crtc_state,
 856                               const struct drm_connector_state *conn_state)
 857 {
 858         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 859         struct i915_audio_component *acomp = dev_priv->audio_component;
 860         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 861         struct drm_connector *connector = conn_state->connector;
 862         const struct drm_display_mode *adjusted_mode =
 863                 &crtc_state->hw.adjusted_mode;
 864         enum port port = encoder->port;
 865         enum pipe pipe = crtc->pipe;
 866
 867         /* FIXME precompute the ELD in .compute_config() */
 868         if (!connector->eld[0])
 869                 drm_dbg_kms(&dev_priv->drm,
 870                             "Bogus ELD on [CONNECTOR:%d:%s]\n",
 871                             connector->base.id, connector->name);
 872
 873         drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 874                 connector->base.id,
 875                 connector->name,
 876                 encoder->base.base.id,
 877                 encoder->base.name);
 878
 879         connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 880
 881         if (dev_priv->display.audio_codec_enable)
 882                 dev_priv->display.audio_codec_enable(encoder,
 883                                                      crtc_state,
 884                                                      conn_state);
 885
 886         mutex_lock(&dev_priv->av_mutex);
 887         encoder->audio_connector = connector;
 888
 889         /* referred in audio callbacks */
 890         dev_priv->av_enc_map[pipe] = encoder;
 891         mutex_unlock(&dev_priv->av_mutex);
 892
 893         if (acomp && acomp->base.audio_ops &&
 894             acomp->base.audio_ops->pin_eld_notify) {
 895                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 896                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 897                         pipe = -1;
 898                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 899                                                  (int) port, (int) pipe);
 900         }
 901
 902         intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
 903                                crtc_state->port_clock,
 904                                intel_crtc_has_dp_encoder(crtc_state));
 905 }
 906
 907 /**
 908  * intel_audio_codec_disable - Disable the audio codec for HD audio
 909  * @encoder: encoder on which to disable audio
 910  * @old_crtc_state: pointer to the old crtc state.
 911  * @old_conn_state: pointer to the old connector state.
 912  *
 913  * The disable sequences must be performed before disabling the transcoder or
 914  * port.
 915  */
 916 void intel_audio_codec_disable(struct intel_encoder *encoder,
 917                                const struct intel_crtc_state *old_crtc_state,
 918                                const struct drm_connector_state *old_conn_state)
 919 {
 920         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 921         struct i915_audio_component *acomp = dev_priv->audio_component;
 922         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 923         enum port port = encoder->port;
 924         enum pipe pipe = crtc->pipe;
 925
 926         if (dev_priv->display.audio_codec_disable)
 927                 dev_priv->display.audio_codec_disable(encoder,
 928                                                       old_crtc_state,
 929                                                       old_conn_state);
 930
 931         mutex_lock(&dev_priv->av_mutex);
 932         encoder->audio_connector = NULL;
 933         dev_priv->av_enc_map[pipe] = NULL;
 934         mutex_unlock(&dev_priv->av_mutex);
 935
 936         if (acomp && acomp->base.audio_ops &&
 937             acomp->base.audio_ops->pin_eld_notify) {
 938                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 939                 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
 940                         pipe = -1;
 941                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 942                                                  (int) port, (int) pipe);
 943         }
 944
 945         intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
 946 }
 947
 948 /**
 949  * intel_init_audio_hooks - Set up chip specific audio hooks
 950  * @dev_priv: device private
 951  */
 952 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 953 {
 954         if (IS_G4X(dev_priv)) {
 955                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 956                 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
 957         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 958                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 959                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 960         } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
 961                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 962                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 963         } else if (HAS_PCH_SPLIT(dev_priv)) {
 964                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 965                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 966         }
 967 }
 968
 969 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
 970                                         struct intel_crtc *crtc,
 971                                         bool enable)
 972 {
 973         struct intel_cdclk_state *cdclk_state;
 974         int ret;
 975
 976         /* need to hold at least one crtc lock for the global state */
 977         ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
 978         if (ret)
 979                 return ret;
 980
 981         cdclk_state = intel_atomic_get_cdclk_state(state);
 982         if (IS_ERR(cdclk_state))
 983                 return PTR_ERR(cdclk_state);
 984
 985         cdclk_state->force_min_cdclk_changed = true;
 986         cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
 987
 988         ret = intel_atomic_lock_global_state(&cdclk_state->base);
 989         if (ret)
 990                 return ret;
 991
 992         return drm_atomic_commit(&state->base);
 993 }
 994
 995 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
 996                                   bool enable)
 997 {
 998         struct drm_modeset_acquire_ctx ctx;
 999         struct drm_atomic_state *state;
1000         struct intel_crtc *crtc;
1001         int ret;
1002
1003         crtc = intel_get_first_crtc(dev_priv);
1004         if (!crtc)
1005                 return;
1006
1007         drm_modeset_acquire_init(&ctx, 0);
1008         state = drm_atomic_state_alloc(&dev_priv->drm);
1009         if (drm_WARN_ON(&dev_priv->drm, !state))
1010                 return;
1011
1012         state->acquire_ctx = &ctx;
1013
1014 retry:
1015         ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
1016                                            enable);
1017         if (ret == -EDEADLK) {
1018                 drm_atomic_state_clear(state);
1019                 drm_modeset_backoff(&ctx);
1020                 goto retry;
1021         }
1022
1023         drm_WARN_ON(&dev_priv->drm, ret);
1024
1025         drm_atomic_state_put(state);
1026
1027         drm_modeset_drop_locks(&ctx);
1028         drm_modeset_acquire_fini(&ctx);
1029 }
1030
1031 static unsigned long i915_audio_component_get_power(struct device *kdev)
1032 {
1033         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1034         intel_wakeref_t ret;
1035
1036         /* Catch potential impedance mismatches before they occur! */
1037         BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
1038
1039         ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1040
1041         if (dev_priv->audio_power_refcount++ == 0) {
1042                 if (INTEL_GEN(dev_priv) >= 9) {
1043                         intel_de_write(dev_priv, AUD_FREQ_CNTRL,
1044                                        dev_priv->audio_freq_cntrl);
1045                         drm_dbg_kms(&dev_priv->drm,
1046                                     "restored AUD_FREQ_CNTRL to 0x%x\n",
1047                                     dev_priv->audio_freq_cntrl);
1048                 }
1049
1050                 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
1051                 if (IS_GEMINILAKE(dev_priv))
1052                         glk_force_audio_cdclk(dev_priv, true);
1053
1054                 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1055                         intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
1056                                        (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
1057         }
1058
1059         return ret;
1060 }
1061
1062 static void i915_audio_component_put_power(struct device *kdev,
1063                                            unsigned long cookie)
1064 {
1065         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1066
1067         /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1068         if (--dev_priv->audio_power_refcount == 0)
1069                 if (IS_GEMINILAKE(dev_priv))
1070                         glk_force_audio_cdclk(dev_priv, false);
1071
1072         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
1073 }
1074
1075 static void i915_audio_component_codec_wake_override(struct device *kdev,
1076                                                      bool enable)
1077 {
1078         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1079         unsigned long cookie;
1080         u32 tmp;
1081
1082         if (INTEL_GEN(dev_priv) < 9)
1083                 return;
1084
1085         cookie = i915_audio_component_get_power(kdev);
1086
1087         /*
1088          * Enable/disable generating the codec wake signal, overriding the
1089          * internal logic to generate the codec wake to controller.
1090          */
1091         tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1092         tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
1093         intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1094         usleep_range(1000, 1500);
1095
1096         if (enable) {
1097                 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1098                 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
1099                 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1100                 usleep_range(1000, 1500);
1101         }
1102
1103         i915_audio_component_put_power(kdev, cookie);
1104 }
1105
1106 /* Get CDCLK in kHz  */
1107 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1108 {
1109         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1110
1111         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
1112                 return -ENODEV;
1113
1114         return dev_priv->cdclk.hw.cdclk;
1115 }
1116
1117 /*
1118  * get the intel_encoder according to the parameter port and pipe
1119  * intel_encoder is saved by the index of pipe
1120  * MST & (pipe >= 0): return the av_enc_map[pipe],
1121  *   when port is matched
1122  * MST & (pipe < 0): this is invalid
1123  * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
1124  *   will get the right intel_encoder with port matched
1125  * Non-MST & (pipe < 0): get the right intel_encoder with port matched
1126  */
1127 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
1128                                                int port, int pipe)
1129 {
1130         struct intel_encoder *encoder;
1131
1132         /* MST */
1133         if (pipe >= 0) {
1134                 if (drm_WARN_ON(&dev_priv->drm,
1135                                 pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
1136                         return NULL;
1137
1138                 encoder = dev_priv->av_enc_map[pipe];
1139                 /*
1140                  * when bootup, audio driver may not know it is
1141                  * MST or not. So it will poll all the port & pipe
1142                  * combinations
1143                  */
1144                 if (encoder != NULL && encoder->port == port &&
1145                     encoder->type == INTEL_OUTPUT_DP_MST)
1146                         return encoder;
1147         }
1148
1149         /* Non-MST */
1150         if (pipe > 0)
1151                 return NULL;
1152
1153         for_each_pipe(dev_priv, pipe) {
1154                 encoder = dev_priv->av_enc_map[pipe];
1155                 if (encoder == NULL)
1156                         continue;
1157
1158                 if (encoder->type == INTEL_OUTPUT_DP_MST)
1159                         continue;
1160
1161                 if (port == encoder->port)
1162                         return encoder;
1163         }
1164
1165         return NULL;
1166 }
1167
1168 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1169                                                 int pipe, int rate)
1170 {
1171         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1172         struct i915_audio_component *acomp = dev_priv->audio_component;
1173         struct intel_encoder *encoder;
1174         struct intel_crtc *crtc;
1175         unsigned long cookie;
1176         int err = 0;
1177
1178         if (!HAS_DDI(dev_priv))
1179                 return 0;
1180
1181         cookie = i915_audio_component_get_power(kdev);
1182         mutex_lock(&dev_priv->av_mutex);
1183
1184         /* 1. get the pipe */
1185         encoder = get_saved_enc(dev_priv, port, pipe);
1186         if (!encoder || !encoder->base.crtc) {
1187                 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1188                             port_name(port));
1189                 err = -ENODEV;
1190                 goto unlock;
1191         }
1192
1193         crtc = to_intel_crtc(encoder->base.crtc);
1194
1195         /* port must be valid now, otherwise the pipe will be invalid */
1196         acomp->aud_sample_rate[port] = rate;
1197
1198         hsw_audio_config_update(encoder, crtc->config);
1199
1200  unlock:
1201         mutex_unlock(&dev_priv->av_mutex);
1202         i915_audio_component_put_power(kdev, cookie);
1203         return err;
1204 }
1205
1206 static int i915_audio_component_get_eld(struct device *kdev, int port,
1207                                         int pipe, bool *enabled,
1208                                         unsigned char *buf, int max_bytes)
1209 {
1210         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1211         struct intel_encoder *intel_encoder;
1212         const u8 *eld;
1213         int ret = -EINVAL;
1214
1215         mutex_lock(&dev_priv->av_mutex);
1216
1217         intel_encoder = get_saved_enc(dev_priv, port, pipe);
1218         if (!intel_encoder) {
1219                 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1220                             port_name(port));
1221                 mutex_unlock(&dev_priv->av_mutex);
1222                 return ret;
1223         }
1224
1225         ret = 0;
1226         *enabled = intel_encoder->audio_connector != NULL;
1227         if (*enabled) {
1228                 eld = intel_encoder->audio_connector->eld;
1229                 ret = drm_eld_size(eld);
1230                 memcpy(buf, eld, min(max_bytes, ret));
1231         }
1232
1233         mutex_unlock(&dev_priv->av_mutex);
1234         return ret;
1235 }
1236
1237 static const struct drm_audio_component_ops i915_audio_component_ops = {
1238         .owner          = THIS_MODULE,
1239         .get_power      = i915_audio_component_get_power,
1240         .put_power      = i915_audio_component_put_power,
1241         .codec_wake_override = i915_audio_component_codec_wake_override,
1242         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1243         .sync_audio_rate = i915_audio_component_sync_audio_rate,
1244         .get_eld        = i915_audio_component_get_eld,
1245 };
1246
1247 static int i915_audio_component_bind(struct device *i915_kdev,
1248                                      struct device *hda_kdev, void *data)
1249 {
1250         struct i915_audio_component *acomp = data;
1251         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1252         int i;
1253
1254         if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev))
1255                 return -EEXIST;
1256
1257         if (drm_WARN_ON(&dev_priv->drm,
1258                         !device_link_add(hda_kdev, i915_kdev,
1259                                          DL_FLAG_STATELESS)))
1260                 return -ENOMEM;
1261
1262         drm_modeset_lock_all(&dev_priv->drm);
1263         acomp->base.ops = &i915_audio_component_ops;
1264         acomp->base.dev = i915_kdev;
1265         BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1266         for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1267                 acomp->aud_sample_rate[i] = 0;
1268         dev_priv->audio_component = acomp;
1269         drm_modeset_unlock_all(&dev_priv->drm);
1270
1271         return 0;
1272 }
1273
1274 static void i915_audio_component_unbind(struct device *i915_kdev,
1275                                         struct device *hda_kdev, void *data)
1276 {
1277         struct i915_audio_component *acomp = data;
1278         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1279
1280         drm_modeset_lock_all(&dev_priv->drm);
1281         acomp->base.ops = NULL;
1282         acomp->base.dev = NULL;
1283         dev_priv->audio_component = NULL;
1284         drm_modeset_unlock_all(&dev_priv->drm);
1285
1286         device_link_remove(hda_kdev, i915_kdev);
1287 }
1288
1289 static const struct component_ops i915_audio_component_bind_ops = {
1290         .bind   = i915_audio_component_bind,
1291         .unbind = i915_audio_component_unbind,
1292 };
1293
1294 /**
1295  * i915_audio_component_init - initialize and register the audio component
1296  * @dev_priv: i915 device instance
1297  *
1298  * This will register with the component framework a child component which
1299  * will bind dynamically to the snd_hda_intel driver's corresponding master
1300  * component when the latter is registered. During binding the child
1301  * initializes an instance of struct i915_audio_component which it receives
1302  * from the master. The master can then start to use the interface defined by
1303  * this struct. Each side can break the binding at any point by deregistering
1304  * its own component after which each side's component unbind callback is
1305  * called.
1306  *
1307  * We ignore any error during registration and continue with reduced
1308  * functionality (i.e. without HDMI audio).
1309  */
1310 static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1311 {
1312         int ret;
1313
1314         ret = component_add_typed(dev_priv->drm.dev,
1315                                   &i915_audio_component_bind_ops,
1316                                   I915_COMPONENT_AUDIO);
1317         if (ret < 0) {
1318                 drm_err(&dev_priv->drm,
1319                         "failed to add audio component (%d)\n", ret);
1320                 /* continue with reduced functionality */
1321                 return;
1322         }
1323
1324         if (INTEL_GEN(dev_priv) >= 9) {
1325                 dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,
1326                                                            AUD_FREQ_CNTRL);
1327                 drm_dbg_kms(&dev_priv->drm,
1328                             "init value of AUD_FREQ_CNTRL of 0x%x\n",
1329                             dev_priv->audio_freq_cntrl);
1330         }
1331
1332         dev_priv->audio_component_registered = true;
1333 }
1334
1335 /**
1336  * i915_audio_component_cleanup - deregister the audio component
1337  * @dev_priv: i915 device instance
1338  *
1339  * Deregisters the audio component, breaking any existing binding to the
1340  * corresponding snd_hda_intel driver's master component.
1341  */
1342 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1343 {
1344         if (!dev_priv->audio_component_registered)
1345                 return;
1346
1347         component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1348         dev_priv->audio_component_registered = false;
1349 }
1350
1351 /**
1352  * intel_audio_init() - Initialize the audio driver either using
1353  * component framework or using lpe audio bridge
1354  * @dev_priv: the i915 drm device private data
1355  *
1356  */
1357 void intel_audio_init(struct drm_i915_private *dev_priv)
1358 {
1359         if (intel_lpe_audio_init(dev_priv) < 0)
1360                 i915_audio_component_init(dev_priv);
1361 }
1362
1363 /**
1364  * intel_audio_deinit() - deinitialize the audio driver
1365  * @dev_priv: the i915 drm device private data
1366  *
1367  */
1368 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1369 {
1370         if ((dev_priv)->lpe_audio.platdev != NULL)
1371                 intel_lpe_audio_teardown(dev_priv);
1372         else
1373                 i915_audio_component_cleanup(dev_priv);
1374 }