drivers/gpu/drm/i915/display/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/component.h>
  25 #include <linux/kernel.h>
  26
  27 #include <drm/drm_edid.h>
  28 #include <drm/i915_component.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_atomic.h"
  32 #include "intel_audio.h"
  33 #include "intel_cdclk.h"
  34 #include "intel_display_types.h"
  35 #include "intel_lpe_audio.h"
  36
  37 /**
  38  * DOC: High Definition Audio over HDMI and Display Port
  39  *
  40  * The graphics and audio drivers together support High Definition Audio over
  41  * HDMI and Display Port. The audio programming sequences are divided into audio
  42  * codec and controller enable and disable sequences. The graphics driver
  43  * handles the audio codec sequences, while the audio driver handles the audio
  44  * controller sequences.
  45  *
  46  * The disable sequences must be performed before disabling the transcoder or
  47  * port. The enable sequences may only be performed after enabling the
  48  * transcoder and port, and after completed link training. Therefore the audio
  49  * enable/disable sequences are part of the modeset sequence.
  50  *
  51  * The codec and controller sequences could be done either parallel or serial,
  52  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  53  * driver that the controller sequence should start. Indeed, most of the
  54  * co-operation between the graphics and audio drivers is handled via audio
  55  * related registers. (The notable exception is the power management, not
  56  * covered here.)
  57  *
  58  * The struct &i915_audio_component is used to interact between the graphics
  59  * and audio drivers. The struct &i915_audio_component_ops @ops in it is
  60  * defined in graphics driver and called in audio driver. The
  61  * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
  62  */
  63
  64 /* DP N/M table */
  65 #define LC_810M 810000
  66 #define LC_540M 540000
  67 #define LC_270M 270000
  68 #define LC_162M 162000
  69
  70 struct dp_aud_n_m {
  71         int sample_rate;
  72         int clock;
  73         u16 m;
  74         u16 n;
  75 };
  76
  77 struct hdmi_aud_ncts {
  78         int sample_rate;
  79         int clock;
  80         int n;
  81         int cts;
  82 };
  83
  84 /* Values according to DP 1.4 Table 2-104 */
  85 static const struct dp_aud_n_m dp_aud_n_m[] = {
  86         { 32000, LC_162M, 1024, 10125 },
  87         { 44100, LC_162M, 784, 5625 },
  88         { 48000, LC_162M, 512, 3375 },
  89         { 64000, LC_162M, 2048, 10125 },
  90         { 88200, LC_162M, 1568, 5625 },
  91         { 96000, LC_162M, 1024, 3375 },
  92         { 128000, LC_162M, 4096, 10125 },
  93         { 176400, LC_162M, 3136, 5625 },
  94         { 192000, LC_162M, 2048, 3375 },
  95         { 32000, LC_270M, 1024, 16875 },
  96         { 44100, LC_270M, 784, 9375 },
  97         { 48000, LC_270M, 512, 5625 },
  98         { 64000, LC_270M, 2048, 16875 },
  99         { 88200, LC_270M, 1568, 9375 },
 100         { 96000, LC_270M, 1024, 5625 },
 101         { 128000, LC_270M, 4096, 16875 },
 102         { 176400, LC_270M, 3136, 9375 },
 103         { 192000, LC_270M, 2048, 5625 },
 104         { 32000, LC_540M, 1024, 33750 },
 105         { 44100, LC_540M, 784, 18750 },
 106         { 48000, LC_540M, 512, 11250 },
 107         { 64000, LC_540M, 2048, 33750 },
 108         { 88200, LC_540M, 1568, 18750 },
 109         { 96000, LC_540M, 1024, 11250 },
 110         { 128000, LC_540M, 4096, 33750 },
 111         { 176400, LC_540M, 3136, 18750 },
 112         { 192000, LC_540M, 2048, 11250 },
 113         { 32000, LC_810M, 1024, 50625 },
 114         { 44100, LC_810M, 784, 28125 },
 115         { 48000, LC_810M, 512, 16875 },
 116         { 64000, LC_810M, 2048, 50625 },
 117         { 88200, LC_810M, 1568, 28125 },
 118         { 96000, LC_810M, 1024, 16875 },
 119         { 128000, LC_810M, 4096, 50625 },
 120         { 176400, LC_810M, 3136, 28125 },
 121         { 192000, LC_810M, 2048, 16875 },
 122 };
 123
 124 static const struct dp_aud_n_m *
 125 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
 126 {
 127         int i;
 128
 129         for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
 130                 if (rate == dp_aud_n_m[i].sample_rate &&
 131                     crtc_state->port_clock == dp_aud_n_m[i].clock)
 132                         return &dp_aud_n_m[i];
 133         }
 134
 135         return NULL;
 136 }
 137
 138 static const struct {
 139         int clock;
 140         u32 config;
 141 } hdmi_audio_clock[] = {
 142         { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
 143         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
 144         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
 145         { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
 146         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
 147         { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
 148         { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
 149         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
 150         { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
 151         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
 152         { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
 153         { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
 154         { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
 155         { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
 156 };
 157
 158 /* HDMI N/CTS table */
 159 #define TMDS_297M 297000
 160 #define TMDS_296M 296703
 161 #define TMDS_594M 594000
 162 #define TMDS_593M 593407
 163
 164 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
 165         { 32000, TMDS_296M, 5824, 421875 },
 166         { 32000, TMDS_297M, 3072, 222750 },
 167         { 32000, TMDS_593M, 5824, 843750 },
 168         { 32000, TMDS_594M, 3072, 445500 },
 169         { 44100, TMDS_296M, 4459, 234375 },
 170         { 44100, TMDS_297M, 4704, 247500 },
 171         { 44100, TMDS_593M, 8918, 937500 },
 172         { 44100, TMDS_594M, 9408, 990000 },
 173         { 88200, TMDS_296M, 8918, 234375 },
 174         { 88200, TMDS_297M, 9408, 247500 },
 175         { 88200, TMDS_593M, 17836, 937500 },
 176         { 88200, TMDS_594M, 18816, 990000 },
 177         { 176400, TMDS_296M, 17836, 234375 },
 178         { 176400, TMDS_297M, 18816, 247500 },
 179         { 176400, TMDS_593M, 35672, 937500 },
 180         { 176400, TMDS_594M, 37632, 990000 },
 181         { 48000, TMDS_296M, 5824, 281250 },
 182         { 48000, TMDS_297M, 5120, 247500 },
 183         { 48000, TMDS_593M, 5824, 562500 },
 184         { 48000, TMDS_594M, 6144, 594000 },
 185         { 96000, TMDS_296M, 11648, 281250 },
 186         { 96000, TMDS_297M, 10240, 247500 },
 187         { 96000, TMDS_593M, 11648, 562500 },
 188         { 96000, TMDS_594M, 12288, 594000 },
 189         { 192000, TMDS_296M, 23296, 281250 },
 190         { 192000, TMDS_297M, 20480, 247500 },
 191         { 192000, TMDS_593M, 23296, 562500 },
 192         { 192000, TMDS_594M, 24576, 594000 },
 193 };
 194
 195 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
 196 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
 197 #define TMDS_371M 371250
 198 #define TMDS_370M 370878
 199
 200 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
 201         { 32000, TMDS_370M, 5824, 527344 },
 202         { 32000, TMDS_371M, 6144, 556875 },
 203         { 44100, TMDS_370M, 8918, 585938 },
 204         { 44100, TMDS_371M, 4704, 309375 },
 205         { 88200, TMDS_370M, 17836, 585938 },
 206         { 88200, TMDS_371M, 9408, 309375 },
 207         { 176400, TMDS_370M, 35672, 585938 },
 208         { 176400, TMDS_371M, 18816, 309375 },
 209         { 48000, TMDS_370M, 11648, 703125 },
 210         { 48000, TMDS_371M, 5120, 309375 },
 211         { 96000, TMDS_370M, 23296, 703125 },
 212         { 96000, TMDS_371M, 10240, 309375 },
 213         { 192000, TMDS_370M, 46592, 703125 },
 214         { 192000, TMDS_371M, 20480, 309375 },
 215 };
 216
 217 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
 218 #define TMDS_445_5M 445500
 219 #define TMDS_445M 445054
 220
 221 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
 222         { 32000, TMDS_445M, 5824, 632813 },
 223         { 32000, TMDS_445_5M, 4096, 445500 },
 224         { 44100, TMDS_445M, 8918, 703125 },
 225         { 44100, TMDS_445_5M, 4704, 371250 },
 226         { 88200, TMDS_445M, 17836, 703125 },
 227         { 88200, TMDS_445_5M, 9408, 371250 },
 228         { 176400, TMDS_445M, 35672, 703125 },
 229         { 176400, TMDS_445_5M, 18816, 371250 },
 230         { 48000, TMDS_445M, 5824, 421875 },
 231         { 48000, TMDS_445_5M, 5120, 371250 },
 232         { 96000, TMDS_445M, 11648, 421875 },
 233         { 96000, TMDS_445_5M, 10240, 371250 },
 234         { 192000, TMDS_445M, 23296, 421875 },
 235         { 192000, TMDS_445_5M, 20480, 371250 },
 236 };
 237
 238 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 239 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
 240 {
 241         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 242         const struct drm_display_mode *adjusted_mode =
 243                 &crtc_state->hw.adjusted_mode;
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 247                 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 248                         break;
 249         }
 250
 251         if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
 252                 i = ARRAY_SIZE(hdmi_audio_clock);
 253
 254         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 255                 drm_dbg_kms(&dev_priv->drm,
 256                             "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 257                             adjusted_mode->crtc_clock);
 258                 i = 1;
 259         }
 260
 261         drm_dbg_kms(&dev_priv->drm,
 262                     "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 263                     hdmi_audio_clock[i].clock,
 264                     hdmi_audio_clock[i].config);
 265
 266         return hdmi_audio_clock[i].config;
 267 }
 268
 269 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
 270                                    int rate)
 271 {
 272         const struct hdmi_aud_ncts *hdmi_ncts_table;
 273         int i, size;
 274
 275         if (crtc_state->pipe_bpp == 36) {
 276                 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
 277                 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
 278         } else if (crtc_state->pipe_bpp == 30) {
 279                 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
 280                 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
 281         } else {
 282                 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
 283                 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
 284         }
 285
 286         for (i = 0; i < size; i++) {
 287                 if (rate == hdmi_ncts_table[i].sample_rate &&
 288                     crtc_state->port_clock == hdmi_ncts_table[i].clock) {
 289                         return hdmi_ncts_table[i].n;
 290                 }
 291         }
 292         return 0;
 293 }
 294
 295 static bool intel_eld_uptodate(struct drm_connector *connector,
 296                                i915_reg_t reg_eldv, u32 bits_eldv,
 297                                i915_reg_t reg_elda, u32 bits_elda,
 298                                i915_reg_t reg_edid)
 299 {
 300         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 301         const u8 *eld = connector->eld;
 302         u32 tmp;
 303         int i;
 304
 305         tmp = intel_de_read(dev_priv, reg_eldv);
 306         tmp &= bits_eldv;
 307
 308         if (!tmp)
 309                 return false;
 310
 311         tmp = intel_de_read(dev_priv, reg_elda);
 312         tmp &= ~bits_elda;
 313         intel_de_write(dev_priv, reg_elda, tmp);
 314
 315         for (i = 0; i < drm_eld_size(eld) / 4; i++)
 316                 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i))
 317                         return false;
 318
 319         return true;
 320 }
 321
 322 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
 323                                     const struct intel_crtc_state *old_crtc_state,
 324                                     const struct drm_connector_state *old_conn_state)
 325 {
 326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 327         u32 eldv, tmp;
 328
 329         drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n");
 330
 331         tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
 332         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 333                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 334         else
 335                 eldv = G4X_ELDV_DEVCTG;
 336
 337         /* Invalidate ELD */
 338         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 339         tmp &= ~eldv;
 340         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 341 }
 342
 343 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
 344                                    const struct intel_crtc_state *crtc_state,
 345                                    const struct drm_connector_state *conn_state)
 346 {
 347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 348         struct drm_connector *connector = conn_state->connector;
 349         const u8 *eld = connector->eld;
 350         u32 eldv;
 351         u32 tmp;
 352         int len, i;
 353
 354         drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n",
 355                     drm_eld_size(eld));
 356
 357         tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
 358         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 359                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 360         else
 361                 eldv = G4X_ELDV_DEVCTG;
 362
 363         if (intel_eld_uptodate(connector,
 364                                G4X_AUD_CNTL_ST, eldv,
 365                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 366                                G4X_HDMIW_HDMIEDID))
 367                 return;
 368
 369         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 370         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 371         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 372         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 373
 374         len = min(drm_eld_size(eld) / 4, len);
 375         drm_dbg(&dev_priv->drm, "ELD size %d\n", len);
 376         for (i = 0; i < len; i++)
 377                 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
 378                                *((const u32 *)eld + i));
 379
 380         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 381         tmp |= eldv;
 382         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 383 }
 384
 385 static void
 386 hsw_dp_audio_config_update(struct intel_encoder *encoder,
 387                            const struct intel_crtc_state *crtc_state)
 388 {
 389         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 390         struct i915_audio_component *acomp = dev_priv->audio_component;
 391         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 392         enum port port = encoder->port;
 393         const struct dp_aud_n_m *nm;
 394         int rate;
 395         u32 tmp;
 396
 397         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 398         nm = audio_config_dp_get_n_m(crtc_state, rate);
 399         if (nm)
 400                 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m,
 401                             nm->n);
 402         else
 403                 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n");
 404
 405         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 406         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 407         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 408         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 409         tmp |= AUD_CONFIG_N_VALUE_INDEX;
 410
 411         if (nm) {
 412                 tmp &= ~AUD_CONFIG_N_MASK;
 413                 tmp |= AUD_CONFIG_N(nm->n);
 414                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 415         }
 416
 417         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 418
 419         tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 420         tmp &= ~AUD_CONFIG_M_MASK;
 421         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 422         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 423
 424         if (nm) {
 425                 tmp |= nm->m;
 426                 tmp |= AUD_M_CTS_M_VALUE_INDEX;
 427                 tmp |= AUD_M_CTS_M_PROG_ENABLE;
 428         }
 429
 430         intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 431 }
 432
 433 static void
 434 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
 435                              const struct intel_crtc_state *crtc_state)
 436 {
 437         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 438         struct i915_audio_component *acomp = dev_priv->audio_component;
 439         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 440         enum port port = encoder->port;
 441         int n, rate;
 442         u32 tmp;
 443
 444         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 445
 446         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 447         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 448         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 449         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 450         tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 451
 452         n = audio_config_hdmi_get_n(crtc_state, rate);
 453         if (n != 0) {
 454                 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n);
 455
 456                 tmp &= ~AUD_CONFIG_N_MASK;
 457                 tmp |= AUD_CONFIG_N(n);
 458                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 459         } else {
 460                 drm_dbg_kms(&dev_priv->drm, "using automatic N\n");
 461         }
 462
 463         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 464
 465         /*
 466          * Let's disable "Enable CTS or M Prog bit"
 467          * and let HW calculate the value
 468          */
 469         tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 470         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 471         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 472         intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 473 }
 474
 475 static void
 476 hsw_audio_config_update(struct intel_encoder *encoder,
 477                         const struct intel_crtc_state *crtc_state)
 478 {
 479         if (intel_crtc_has_dp_encoder(crtc_state))
 480                 hsw_dp_audio_config_update(encoder, crtc_state);
 481         else
 482                 hsw_hdmi_audio_config_update(encoder, crtc_state);
 483 }
 484
 485 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
 486                                     const struct intel_crtc_state *old_crtc_state,
 487                                     const struct drm_connector_state *old_conn_state)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 490         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 491         u32 tmp;
 492
 493         drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n",
 494                     transcoder_name(cpu_transcoder));
 495
 496         mutex_lock(&dev_priv->av_mutex);
 497
 498         /* Disable timestamps */
 499         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 500         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 501         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 502         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 503         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 504         if (intel_crtc_has_dp_encoder(old_crtc_state))
 505                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 506         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 507
 508         /* Invalidate ELD */
 509         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 510         tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
 511         tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
 512         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 513
 514         mutex_unlock(&dev_priv->av_mutex);
 515 }
 516
 517 /* Add a factor to take care of rounding and truncations */
 518 #define ROUNDING_FACTOR 10000
 519
 520 static unsigned int get_hblank_early_enable_config(struct intel_encoder *encoder,
 521                                                    const struct intel_crtc_state *crtc_state)
 522 {
 523         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 524         unsigned int link_clks_available, link_clks_required;
 525         unsigned int tu_data, tu_line, link_clks_active;
 526         unsigned int hblank_rise, hblank_early_prog;
 527         unsigned int h_active, h_total, hblank_delta, pixel_clk, v_total;
 528         unsigned int fec_coeff, refresh_rate, cdclk, vdsc_bpp;
 529
 530         h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 531         h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 532         v_total = crtc_state->hw.adjusted_mode.crtc_vtotal;
 533         pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
 534         refresh_rate = crtc_state->hw.adjusted_mode.vrefresh;
 535         vdsc_bpp = crtc_state->dsc.compressed_bpp;
 536         cdclk = i915->cdclk.hw.cdclk;
 537         /* fec= 0.972261, using rounding multiplier of 1000000 */
 538         fec_coeff = 972261;
 539
 540         drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
 541                     "lanes = %u vdsc_bpp = %u cdclk = %u\n",
 542                     h_active, crtc_state->port_clock, crtc_state->lane_count,
 543                     vdsc_bpp, cdclk);
 544
 545         if (WARN_ON(!crtc_state->port_clock || !crtc_state->lane_count ||
 546                     !crtc_state->dsc.compressed_bpp || !i915->cdclk.hw.cdclk))
 547                 return 0;
 548
 549         link_clks_available = ((((h_total - h_active) *
 550                                ((crtc_state->port_clock * ROUNDING_FACTOR) /
 551                                 pixel_clk)) / ROUNDING_FACTOR) - 28);
 552
 553         link_clks_required = DIV_ROUND_UP(192000, (refresh_rate *
 554                                           v_total)) * ((48 /
 555                                           crtc_state->lane_count) + 2);
 556
 557         if (link_clks_available > link_clks_required)
 558                 hblank_delta = 32;
 559         else
 560                 hblank_delta = DIV_ROUND_UP(((((5 * ROUNDING_FACTOR) /
 561                                             crtc_state->port_clock) + ((5 *
 562                                             ROUNDING_FACTOR) /
 563                                             cdclk)) * pixel_clk),
 564                                             ROUNDING_FACTOR);
 565
 566         tu_data = (pixel_clk * vdsc_bpp * 8) / ((crtc_state->port_clock *
 567                    crtc_state->lane_count * fec_coeff) / 1000000);
 568         tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
 569                    1000000) / (64 * pixel_clk));
 570         link_clks_active  = (tu_line - 1) * 64 + tu_data;
 571
 572         hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
 573                         250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
 574                         crtc_state->port_clock)) / ROUNDING_FACTOR;
 575
 576         hblank_early_prog = h_active - hblank_rise + hblank_delta;
 577
 578         return hblank_early_prog;
 579 }
 580
 581 static unsigned int get_sample_room_req_config(const struct intel_crtc_state *crtc_state)
 582 {
 583         unsigned int h_active, h_total, pixel_clk;
 584         unsigned int samples_room;
 585
 586         h_active = crtc_state->hw.adjusted_mode.hdisplay;
 587         h_total = crtc_state->hw.adjusted_mode.htotal;
 588         pixel_clk = crtc_state->hw.adjusted_mode.clock;
 589
 590         samples_room = ((((h_total - h_active) * ((crtc_state->port_clock *
 591                         ROUNDING_FACTOR) / pixel_clk)) /
 592                         ROUNDING_FACTOR) - 12) / ((48 /
 593                         crtc_state->lane_count) + 2);
 594
 595         return samples_room;
 596 }
 597
 598 static void enable_audio_dsc_wa(struct intel_encoder *encoder,
 599                                 const struct intel_crtc_state *crtc_state)
 600 {
 601         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 602         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 603         enum pipe pipe = crtc->pipe;
 604         unsigned int hblank_early_prog, samples_room;
 605         unsigned int val;
 606
 607         if (INTEL_GEN(i915) < 11)
 608                 return;
 609
 610         val = intel_de_read(i915, AUD_CONFIG_BE);
 611
 612         if (INTEL_GEN(i915) == 11)
 613                 val |= HBLANK_EARLY_ENABLE_ICL(pipe);
 614         else if (INTEL_GEN(i915) >= 12)
 615                 val |= HBLANK_EARLY_ENABLE_TGL(pipe);
 616
 617         if (crtc_state->dsc.compression_enable &&
 618             (crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
 619             crtc_state->hw.adjusted_mode.vdisplay >= 2160)) {
 620                 /* Get hblank early enable value required */
 621                 hblank_early_prog = get_hblank_early_enable_config(encoder,
 622                                                                    crtc_state);
 623                 if (hblank_early_prog < 32) {
 624                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 625                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32);
 626                 } else if (hblank_early_prog < 64) {
 627                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 628                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64);
 629                 } else if (hblank_early_prog < 96) {
 630                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 631                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96);
 632                 } else {
 633                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 634                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128);
 635                 }
 636
 637                 /* Get samples room value required */
 638                 samples_room = get_sample_room_req_config(crtc_state);
 639                 if (samples_room < 3) {
 640                         val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
 641                         val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
 642                 } else {
 643                         /* Program 0 i.e "All Samples available in buffer" */
 644                         val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
 645                         val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
 646                 }
 647         }
 648
 649         intel_de_write(i915, AUD_CONFIG_BE, val);
 650 }
 651
 652 #undef ROUNDING_FACTOR
 653
 654 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
 655                                    const struct intel_crtc_state *crtc_state,
 656                                    const struct drm_connector_state *conn_state)
 657 {
 658         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 659         struct drm_connector *connector = conn_state->connector;
 660         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 661         const u8 *eld = connector->eld;
 662         u32 tmp;
 663         int len, i;
 664
 665         drm_dbg_kms(&dev_priv->drm,
 666                     "Enable audio codec on transcoder %s, %u bytes ELD\n",
 667                      transcoder_name(cpu_transcoder), drm_eld_size(eld));
 668
 669         mutex_lock(&dev_priv->av_mutex);
 670
 671         /* Enable Audio WA for 4k DSC usecases */
 672         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
 673                 enable_audio_dsc_wa(encoder, crtc_state);
 674
 675         /* Enable audio presence detect, invalidate ELD */
 676         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 677         tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
 678         tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
 679         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 680
 681         /*
 682          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 683          * disabled during the mode set. The proper fix would be to push the
 684          * rest of the setup into a vblank work item, queued here, but the
 685          * infrastructure is not there yet.
 686          */
 687
 688         /* Reset ELD write address */
 689         tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
 690         tmp &= ~IBX_ELD_ADDRESS_MASK;
 691         intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
 692
 693         /* Up to 84 bytes of hw ELD buffer */
 694         len = min(drm_eld_size(eld), 84);
 695         for (i = 0; i < len / 4; i++)
 696                 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder),
 697                                *((const u32 *)eld + i));
 698
 699         /* ELD valid */
 700         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 701         tmp |= AUDIO_ELD_VALID(cpu_transcoder);
 702         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 703
 704         /* Enable timestamps */
 705         hsw_audio_config_update(encoder, crtc_state);
 706
 707         mutex_unlock(&dev_priv->av_mutex);
 708 }
 709
 710 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
 711                                     const struct intel_crtc_state *old_crtc_state,
 712                                     const struct drm_connector_state *old_conn_state)
 713 {
 714         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 715         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 716         enum pipe pipe = crtc->pipe;
 717         enum port port = encoder->port;
 718         u32 tmp, eldv;
 719         i915_reg_t aud_config, aud_cntrl_st2;
 720
 721         drm_dbg_kms(&dev_priv->drm,
 722                     "Disable audio codec on [ENCODER:%d:%s], pipe %c\n",
 723                      encoder->base.base.id, encoder->base.name,
 724                      pipe_name(pipe));
 725
 726         if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
 727                 return;
 728
 729         if (HAS_PCH_IBX(dev_priv)) {
 730                 aud_config = IBX_AUD_CFG(pipe);
 731                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 732         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 733                 aud_config = VLV_AUD_CFG(pipe);
 734                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 735         } else {
 736                 aud_config = CPT_AUD_CFG(pipe);
 737                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 738         }
 739
 740         /* Disable timestamps */
 741         tmp = intel_de_read(dev_priv, aud_config);
 742         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 743         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 744         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 745         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 746         if (intel_crtc_has_dp_encoder(old_crtc_state))
 747                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 748         intel_de_write(dev_priv, aud_config, tmp);
 749
 750         eldv = IBX_ELD_VALID(port);
 751
 752         /* Invalidate ELD */
 753         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 754         tmp &= ~eldv;
 755         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 756 }
 757
 758 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
 759                                    const struct intel_crtc_state *crtc_state,
 760                                    const struct drm_connector_state *conn_state)
 761 {
 762         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 763         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 764         struct drm_connector *connector = conn_state->connector;
 765         enum pipe pipe = crtc->pipe;
 766         enum port port = encoder->port;
 767         const u8 *eld = connector->eld;
 768         u32 tmp, eldv;
 769         int len, i;
 770         i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 771
 772         drm_dbg_kms(&dev_priv->drm,
 773                     "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n",
 774                     encoder->base.base.id, encoder->base.name,
 775                     pipe_name(pipe), drm_eld_size(eld));
 776
 777         if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
 778                 return;
 779
 780         /*
 781          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 782          * disabled during the mode set. The proper fix would be to push the
 783          * rest of the setup into a vblank work item, queued here, but the
 784          * infrastructure is not there yet.
 785          */
 786
 787         if (HAS_PCH_IBX(dev_priv)) {
 788                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 789                 aud_config = IBX_AUD_CFG(pipe);
 790                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 791                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 792         } else if (IS_VALLEYVIEW(dev_priv) ||
 793                    IS_CHERRYVIEW(dev_priv)) {
 794                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 795                 aud_config = VLV_AUD_CFG(pipe);
 796                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 797                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 798         } else {
 799                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 800                 aud_config = CPT_AUD_CFG(pipe);
 801                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 802                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 803         }
 804
 805         eldv = IBX_ELD_VALID(port);
 806
 807         /* Invalidate ELD */
 808         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 809         tmp &= ~eldv;
 810         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 811
 812         /* Reset ELD write address */
 813         tmp = intel_de_read(dev_priv, aud_cntl_st);
 814         tmp &= ~IBX_ELD_ADDRESS_MASK;
 815         intel_de_write(dev_priv, aud_cntl_st, tmp);
 816
 817         /* Up to 84 bytes of hw ELD buffer */
 818         len = min(drm_eld_size(eld), 84);
 819         for (i = 0; i < len / 4; i++)
 820                 intel_de_write(dev_priv, hdmiw_hdmiedid,
 821                                *((const u32 *)eld + i));
 822
 823         /* ELD valid */
 824         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 825         tmp |= eldv;
 826         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 827
 828         /* Enable timestamps */
 829         tmp = intel_de_read(dev_priv, aud_config);
 830         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 831         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 832         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 833         if (intel_crtc_has_dp_encoder(crtc_state))
 834                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 835         else
 836                 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 837         intel_de_write(dev_priv, aud_config, tmp);
 838 }
 839
 840 /**
 841  * intel_audio_codec_enable - Enable the audio codec for HD audio
 842  * @encoder: encoder on which to enable audio
 843  * @crtc_state: pointer to the current crtc state.
 844  * @conn_state: pointer to the current connector state.
 845  *
 846  * The enable sequences may only be performed after enabling the transcoder and
 847  * port, and after completed link training.
 848  */
 849 void intel_audio_codec_enable(struct intel_encoder *encoder,
 850                               const struct intel_crtc_state *crtc_state,
 851                               const struct drm_connector_state *conn_state)
 852 {
 853         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 854         struct i915_audio_component *acomp = dev_priv->audio_component;
 855         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 856         struct drm_connector *connector = conn_state->connector;
 857         const struct drm_display_mode *adjusted_mode =
 858                 &crtc_state->hw.adjusted_mode;
 859         enum port port = encoder->port;
 860         enum pipe pipe = crtc->pipe;
 861
 862         /* FIXME precompute the ELD in .compute_config() */
 863         if (!connector->eld[0])
 864                 drm_dbg_kms(&dev_priv->drm,
 865                             "Bogus ELD on [CONNECTOR:%d:%s]\n",
 866                             connector->base.id, connector->name);
 867
 868         drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 869                 connector->base.id,
 870                 connector->name,
 871                 encoder->base.base.id,
 872                 encoder->base.name);
 873
 874         connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 875
 876         if (dev_priv->display.audio_codec_enable)
 877                 dev_priv->display.audio_codec_enable(encoder,
 878                                                      crtc_state,
 879                                                      conn_state);
 880
 881         mutex_lock(&dev_priv->av_mutex);
 882         encoder->audio_connector = connector;
 883
 884         /* referred in audio callbacks */
 885         dev_priv->av_enc_map[pipe] = encoder;
 886         mutex_unlock(&dev_priv->av_mutex);
 887
 888         if (acomp && acomp->base.audio_ops &&
 889             acomp->base.audio_ops->pin_eld_notify) {
 890                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 891                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 892                         pipe = -1;
 893                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 894                                                  (int) port, (int) pipe);
 895         }
 896
 897         intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
 898                                crtc_state->port_clock,
 899                                intel_crtc_has_dp_encoder(crtc_state));
 900 }
 901
 902 /**
 903  * intel_audio_codec_disable - Disable the audio codec for HD audio
 904  * @encoder: encoder on which to disable audio
 905  * @old_crtc_state: pointer to the old crtc state.
 906  * @old_conn_state: pointer to the old connector state.
 907  *
 908  * The disable sequences must be performed before disabling the transcoder or
 909  * port.
 910  */
 911 void intel_audio_codec_disable(struct intel_encoder *encoder,
 912                                const struct intel_crtc_state *old_crtc_state,
 913                                const struct drm_connector_state *old_conn_state)
 914 {
 915         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 916         struct i915_audio_component *acomp = dev_priv->audio_component;
 917         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 918         enum port port = encoder->port;
 919         enum pipe pipe = crtc->pipe;
 920
 921         if (dev_priv->display.audio_codec_disable)
 922                 dev_priv->display.audio_codec_disable(encoder,
 923                                                       old_crtc_state,
 924                                                       old_conn_state);
 925
 926         mutex_lock(&dev_priv->av_mutex);
 927         encoder->audio_connector = NULL;
 928         dev_priv->av_enc_map[pipe] = NULL;
 929         mutex_unlock(&dev_priv->av_mutex);
 930
 931         if (acomp && acomp->base.audio_ops &&
 932             acomp->base.audio_ops->pin_eld_notify) {
 933                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 934                 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
 935                         pipe = -1;
 936                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 937                                                  (int) port, (int) pipe);
 938         }
 939
 940         intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
 941 }
 942
 943 /**
 944  * intel_init_audio_hooks - Set up chip specific audio hooks
 945  * @dev_priv: device private
 946  */
 947 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 948 {
 949         if (IS_G4X(dev_priv)) {
 950                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 951                 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
 952         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 953                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 954                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 955         } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
 956                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 957                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 958         } else if (HAS_PCH_SPLIT(dev_priv)) {
 959                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 960                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 961         }
 962 }
 963
 964 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
 965                                         struct intel_crtc *crtc,
 966                                         bool enable)
 967 {
 968         struct intel_cdclk_state *cdclk_state;
 969         int ret;
 970
 971         /* need to hold at least one crtc lock for the global state */
 972         ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
 973         if (ret)
 974                 return ret;
 975
 976         cdclk_state = intel_atomic_get_cdclk_state(state);
 977         if (IS_ERR(cdclk_state))
 978                 return PTR_ERR(cdclk_state);
 979
 980         cdclk_state->force_min_cdclk_changed = true;
 981         cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
 982
 983         ret = intel_atomic_lock_global_state(&cdclk_state->base);
 984         if (ret)
 985                 return ret;
 986
 987         return drm_atomic_commit(&state->base);
 988 }
 989
 990 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
 991                                   bool enable)
 992 {
 993         struct drm_modeset_acquire_ctx ctx;
 994         struct drm_atomic_state *state;
 995         struct intel_crtc *crtc;
 996         int ret;
 997
 998         crtc = intel_get_first_crtc(dev_priv);
 999         if (!crtc)
1000                 return;
1001
1002         drm_modeset_acquire_init(&ctx, 0);
1003         state = drm_atomic_state_alloc(&dev_priv->drm);
1004         if (drm_WARN_ON(&dev_priv->drm, !state))
1005                 return;
1006
1007         state->acquire_ctx = &ctx;
1008
1009 retry:
1010         ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
1011                                            enable);
1012         if (ret == -EDEADLK) {
1013                 drm_atomic_state_clear(state);
1014                 drm_modeset_backoff(&ctx);
1015                 goto retry;
1016         }
1017
1018         drm_WARN_ON(&dev_priv->drm, ret);
1019
1020         drm_atomic_state_put(state);
1021
1022         drm_modeset_drop_locks(&ctx);
1023         drm_modeset_acquire_fini(&ctx);
1024 }
1025
1026 static unsigned long i915_audio_component_get_power(struct device *kdev)
1027 {
1028         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1029         intel_wakeref_t ret;
1030
1031         /* Catch potential impedance mismatches before they occur! */
1032         BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
1033
1034         ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1035
1036         if (dev_priv->audio_power_refcount++ == 0) {
1037                 if (INTEL_GEN(dev_priv) >= 9) {
1038                         intel_de_write(dev_priv, AUD_FREQ_CNTRL,
1039                                        dev_priv->audio_freq_cntrl);
1040                         drm_dbg_kms(&dev_priv->drm,
1041                                     "restored AUD_FREQ_CNTRL to 0x%x\n",
1042                                     dev_priv->audio_freq_cntrl);
1043                 }
1044
1045                 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
1046                 if (IS_GEMINILAKE(dev_priv))
1047                         glk_force_audio_cdclk(dev_priv, true);
1048
1049                 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1050                         intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
1051                                        (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
1052         }
1053
1054         return ret;
1055 }
1056
1057 static void i915_audio_component_put_power(struct device *kdev,
1058                                            unsigned long cookie)
1059 {
1060         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1061
1062         /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1063         if (--dev_priv->audio_power_refcount == 0)
1064                 if (IS_GEMINILAKE(dev_priv))
1065                         glk_force_audio_cdclk(dev_priv, false);
1066
1067         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
1068 }
1069
1070 static void i915_audio_component_codec_wake_override(struct device *kdev,
1071                                                      bool enable)
1072 {
1073         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1074         unsigned long cookie;
1075         u32 tmp;
1076
1077         if (INTEL_GEN(dev_priv) < 9)
1078                 return;
1079
1080         cookie = i915_audio_component_get_power(kdev);
1081
1082         /*
1083          * Enable/disable generating the codec wake signal, overriding the
1084          * internal logic to generate the codec wake to controller.
1085          */
1086         tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1087         tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
1088         intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1089         usleep_range(1000, 1500);
1090
1091         if (enable) {
1092                 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1093                 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
1094                 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1095                 usleep_range(1000, 1500);
1096         }
1097
1098         i915_audio_component_put_power(kdev, cookie);
1099 }
1100
1101 /* Get CDCLK in kHz  */
1102 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1103 {
1104         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1105
1106         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
1107                 return -ENODEV;
1108
1109         return dev_priv->cdclk.hw.cdclk;
1110 }
1111
1112 /*
1113  * get the intel_encoder according to the parameter port and pipe
1114  * intel_encoder is saved by the index of pipe
1115  * MST & (pipe >= 0): return the av_enc_map[pipe],
1116  *   when port is matched
1117  * MST & (pipe < 0): this is invalid
1118  * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
1119  *   will get the right intel_encoder with port matched
1120  * Non-MST & (pipe < 0): get the right intel_encoder with port matched
1121  */
1122 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
1123                                                int port, int pipe)
1124 {
1125         struct intel_encoder *encoder;
1126
1127         /* MST */
1128         if (pipe >= 0) {
1129                 if (drm_WARN_ON(&dev_priv->drm,
1130                                 pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
1131                         return NULL;
1132
1133                 encoder = dev_priv->av_enc_map[pipe];
1134                 /*
1135                  * when bootup, audio driver may not know it is
1136                  * MST or not. So it will poll all the port & pipe
1137                  * combinations
1138                  */
1139                 if (encoder != NULL && encoder->port == port &&
1140                     encoder->type == INTEL_OUTPUT_DP_MST)
1141                         return encoder;
1142         }
1143
1144         /* Non-MST */
1145         if (pipe > 0)
1146                 return NULL;
1147
1148         for_each_pipe(dev_priv, pipe) {
1149                 encoder = dev_priv->av_enc_map[pipe];
1150                 if (encoder == NULL)
1151                         continue;
1152
1153                 if (encoder->type == INTEL_OUTPUT_DP_MST)
1154                         continue;
1155
1156                 if (port == encoder->port)
1157                         return encoder;
1158         }
1159
1160         return NULL;
1161 }
1162
1163 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1164                                                 int pipe, int rate)
1165 {
1166         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1167         struct i915_audio_component *acomp = dev_priv->audio_component;
1168         struct intel_encoder *encoder;
1169         struct intel_crtc *crtc;
1170         unsigned long cookie;
1171         int err = 0;
1172
1173         if (!HAS_DDI(dev_priv))
1174                 return 0;
1175
1176         cookie = i915_audio_component_get_power(kdev);
1177         mutex_lock(&dev_priv->av_mutex);
1178
1179         /* 1. get the pipe */
1180         encoder = get_saved_enc(dev_priv, port, pipe);
1181         if (!encoder || !encoder->base.crtc) {
1182                 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1183                             port_name(port));
1184                 err = -ENODEV;
1185                 goto unlock;
1186         }
1187
1188         crtc = to_intel_crtc(encoder->base.crtc);
1189
1190         /* port must be valid now, otherwise the pipe will be invalid */
1191         acomp->aud_sample_rate[port] = rate;
1192
1193         hsw_audio_config_update(encoder, crtc->config);
1194
1195  unlock:
1196         mutex_unlock(&dev_priv->av_mutex);
1197         i915_audio_component_put_power(kdev, cookie);
1198         return err;
1199 }
1200
1201 static int i915_audio_component_get_eld(struct device *kdev, int port,
1202                                         int pipe, bool *enabled,
1203                                         unsigned char *buf, int max_bytes)
1204 {
1205         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1206         struct intel_encoder *intel_encoder;
1207         const u8 *eld;
1208         int ret = -EINVAL;
1209
1210         mutex_lock(&dev_priv->av_mutex);
1211
1212         intel_encoder = get_saved_enc(dev_priv, port, pipe);
1213         if (!intel_encoder) {
1214                 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1215                             port_name(port));
1216                 mutex_unlock(&dev_priv->av_mutex);
1217                 return ret;
1218         }
1219
1220         ret = 0;
1221         *enabled = intel_encoder->audio_connector != NULL;
1222         if (*enabled) {
1223                 eld = intel_encoder->audio_connector->eld;
1224                 ret = drm_eld_size(eld);
1225                 memcpy(buf, eld, min(max_bytes, ret));
1226         }
1227
1228         mutex_unlock(&dev_priv->av_mutex);
1229         return ret;
1230 }
1231
1232 static const struct drm_audio_component_ops i915_audio_component_ops = {
1233         .owner          = THIS_MODULE,
1234         .get_power      = i915_audio_component_get_power,
1235         .put_power      = i915_audio_component_put_power,
1236         .codec_wake_override = i915_audio_component_codec_wake_override,
1237         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1238         .sync_audio_rate = i915_audio_component_sync_audio_rate,
1239         .get_eld        = i915_audio_component_get_eld,
1240 };
1241
1242 static int i915_audio_component_bind(struct device *i915_kdev,
1243                                      struct device *hda_kdev, void *data)
1244 {
1245         struct i915_audio_component *acomp = data;
1246         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1247         int i;
1248
1249         if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev))
1250                 return -EEXIST;
1251
1252         if (drm_WARN_ON(&dev_priv->drm,
1253                         !device_link_add(hda_kdev, i915_kdev,
1254                                          DL_FLAG_STATELESS)))
1255                 return -ENOMEM;
1256
1257         drm_modeset_lock_all(&dev_priv->drm);
1258         acomp->base.ops = &i915_audio_component_ops;
1259         acomp->base.dev = i915_kdev;
1260         BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1261         for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1262                 acomp->aud_sample_rate[i] = 0;
1263         dev_priv->audio_component = acomp;
1264         drm_modeset_unlock_all(&dev_priv->drm);
1265
1266         return 0;
1267 }
1268
1269 static void i915_audio_component_unbind(struct device *i915_kdev,
1270                                         struct device *hda_kdev, void *data)
1271 {
1272         struct i915_audio_component *acomp = data;
1273         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1274
1275         drm_modeset_lock_all(&dev_priv->drm);
1276         acomp->base.ops = NULL;
1277         acomp->base.dev = NULL;
1278         dev_priv->audio_component = NULL;
1279         drm_modeset_unlock_all(&dev_priv->drm);
1280
1281         device_link_remove(hda_kdev, i915_kdev);
1282
1283         if (dev_priv->audio_power_refcount)
1284                 drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",
1285                         dev_priv->audio_power_refcount);
1286 }
1287
1288 static const struct component_ops i915_audio_component_bind_ops = {
1289         .bind   = i915_audio_component_bind,
1290         .unbind = i915_audio_component_unbind,
1291 };
1292
1293 /**
1294  * i915_audio_component_init - initialize and register the audio component
1295  * @dev_priv: i915 device instance
1296  *
1297  * This will register with the component framework a child component which
1298  * will bind dynamically to the snd_hda_intel driver's corresponding master
1299  * component when the latter is registered. During binding the child
1300  * initializes an instance of struct i915_audio_component which it receives
1301  * from the master. The master can then start to use the interface defined by
1302  * this struct. Each side can break the binding at any point by deregistering
1303  * its own component after which each side's component unbind callback is
1304  * called.
1305  *
1306  * We ignore any error during registration and continue with reduced
1307  * functionality (i.e. without HDMI audio).
1308  */
1309 static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1310 {
1311         int ret;
1312
1313         ret = component_add_typed(dev_priv->drm.dev,
1314                                   &i915_audio_component_bind_ops,
1315                                   I915_COMPONENT_AUDIO);
1316         if (ret < 0) {
1317                 drm_err(&dev_priv->drm,
1318                         "failed to add audio component (%d)\n", ret);
1319                 /* continue with reduced functionality */
1320                 return;
1321         }
1322
1323         if (INTEL_GEN(dev_priv) >= 9) {
1324                 dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,
1325                                                            AUD_FREQ_CNTRL);
1326                 drm_dbg_kms(&dev_priv->drm,
1327                             "init value of AUD_FREQ_CNTRL of 0x%x\n",
1328                             dev_priv->audio_freq_cntrl);
1329         }
1330
1331         dev_priv->audio_component_registered = true;
1332 }
1333
1334 /**
1335  * i915_audio_component_cleanup - deregister the audio component
1336  * @dev_priv: i915 device instance
1337  *
1338  * Deregisters the audio component, breaking any existing binding to the
1339  * corresponding snd_hda_intel driver's master component.
1340  */
1341 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1342 {
1343         if (!dev_priv->audio_component_registered)
1344                 return;
1345
1346         component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1347         dev_priv->audio_component_registered = false;
1348 }
1349
1350 /**
1351  * intel_audio_init() - Initialize the audio driver either using
1352  * component framework or using lpe audio bridge
1353  * @dev_priv: the i915 drm device private data
1354  *
1355  */
1356 void intel_audio_init(struct drm_i915_private *dev_priv)
1357 {
1358         if (intel_lpe_audio_init(dev_priv) < 0)
1359                 i915_audio_component_init(dev_priv);
1360 }
1361
1362 /**
1363  * intel_audio_deinit() - deinitialize the audio driver
1364  * @dev_priv: the i915 drm device private data
1365  *
1366  */
1367 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1368 {
1369         if ((dev_priv)->lpe_audio.platdev != NULL)
1370                 intel_lpe_audio_teardown(dev_priv);
1371         else
1372                 i915_audio_component_cleanup(dev_priv);
1373 }