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25 * DOC: atomic plane helpers
27 * The functions here are used by the atomic plane helper functions to
28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
29 * drm_plane->disable_plane()). This allows plane updates to use the
30 * atomic state infrastructure and perform plane updates as separate
31 * prepare/check/commit/cleanup steps.
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_plane_helper.h>
38 #include "i915_trace.h"
39 #include "intel_atomic_plane.h"
40 #include "intel_cdclk.h"
41 #include "intel_display_types.h"
43 #include "intel_sprite.h"
45 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
46 struct intel_plane *plane)
48 memset(plane_state, 0, sizeof(*plane_state));
50 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
52 plane_state->scaler_id = -1;
55 struct intel_plane *intel_plane_alloc(void)
57 struct intel_plane_state *plane_state;
58 struct intel_plane *plane;
60 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
62 return ERR_PTR(-ENOMEM);
64 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
67 return ERR_PTR(-ENOMEM);
70 intel_plane_state_reset(plane_state, plane);
72 plane->base.state = &plane_state->uapi;
77 void intel_plane_free(struct intel_plane *plane)
79 intel_plane_destroy_state(&plane->base, plane->base.state);
84 * intel_plane_duplicate_state - duplicate plane state
87 * Allocates and returns a copy of the plane state (both common and
88 * Intel-specific) for the specified plane.
90 * Returns: The newly allocated plane state, or NULL on failure.
92 struct drm_plane_state *
93 intel_plane_duplicate_state(struct drm_plane *plane)
95 struct intel_plane_state *intel_state;
97 intel_state = to_intel_plane_state(plane->state);
98 intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
103 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
105 intel_state->vma = NULL;
106 intel_state->flags = 0;
108 /* add reference to fb */
109 if (intel_state->hw.fb)
110 drm_framebuffer_get(intel_state->hw.fb);
112 return &intel_state->uapi;
116 * intel_plane_destroy_state - destroy plane state
118 * @state: state object to destroy
120 * Destroys the plane state (both common and Intel-specific) for the
124 intel_plane_destroy_state(struct drm_plane *plane,
125 struct drm_plane_state *state)
127 struct intel_plane_state *plane_state = to_intel_plane_state(state);
128 drm_WARN_ON(plane->dev, plane_state->vma);
130 __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
131 if (plane_state->hw.fb)
132 drm_framebuffer_put(plane_state->hw.fb);
136 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
137 const struct intel_plane_state *plane_state)
139 unsigned int src_w, src_h, dst_w, dst_h;
140 unsigned int pixel_rate = crtc_state->pixel_rate;
142 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
143 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
144 dst_w = drm_rect_width(&plane_state->uapi.dst);
145 dst_h = drm_rect_height(&plane_state->uapi.dst);
147 /* Downscaling limits the maximum pixel rate */
148 dst_w = min(src_w, dst_w);
149 dst_h = min(src_h, dst_h);
151 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, src_w * src_h),
155 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
156 const struct intel_plane_state *plane_state)
158 const struct drm_framebuffer *fb = plane_state->hw.fb;
160 unsigned int pixel_rate;
162 if (!plane_state->uapi.visible)
165 pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
167 cpp = fb->format->cpp[0];
170 * Based on HSD#:1408715493
171 * NV12 cpp == 4, P010 cpp == 8
173 * FIXME what is the logic behind this?
175 if (fb->format->is_yuv && fb->format->num_planes > 1)
178 return pixel_rate * cpp;
181 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
182 struct intel_plane *plane,
183 bool *need_cdclk_calc)
185 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
186 const struct intel_plane_state *plane_state =
187 intel_atomic_get_new_plane_state(state, plane);
188 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
189 const struct intel_cdclk_state *cdclk_state;
190 const struct intel_crtc_state *old_crtc_state;
191 struct intel_crtc_state *new_crtc_state;
193 if (!plane_state->uapi.visible || !plane->min_cdclk)
196 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
197 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
199 new_crtc_state->min_cdclk[plane->id] =
200 plane->min_cdclk(new_crtc_state, plane_state);
203 * No need to check against the cdclk state if
204 * the min cdclk for the plane doesn't increase.
206 * Ie. we only ever increase the cdclk due to plane
207 * requirements. This can reduce back and forth
208 * display blinking due to constant cdclk changes.
210 if (new_crtc_state->min_cdclk[plane->id] <=
211 old_crtc_state->min_cdclk[plane->id])
214 cdclk_state = intel_atomic_get_cdclk_state(state);
215 if (IS_ERR(cdclk_state))
216 return PTR_ERR(cdclk_state);
219 * No need to recalculate the cdclk state if
220 * the min cdclk for the pipe doesn't increase.
222 * Ie. we only ever increase the cdclk due to plane
223 * requirements. This can reduce back and forth
224 * display blinking due to constant cdclk changes.
226 if (new_crtc_state->min_cdclk[plane->id] <=
227 cdclk_state->min_cdclk[crtc->pipe])
230 drm_dbg_kms(&dev_priv->drm,
231 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
232 plane->base.base.id, plane->base.name,
233 new_crtc_state->min_cdclk[plane->id],
234 crtc->base.base.id, crtc->base.name,
235 cdclk_state->min_cdclk[crtc->pipe]);
236 *need_cdclk_calc = true;
241 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
243 if (plane_state->hw.fb)
244 drm_framebuffer_put(plane_state->hw.fb);
246 memset(&plane_state->hw, 0, sizeof(plane_state->hw));
249 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
250 const struct intel_plane_state *from_plane_state)
252 intel_plane_clear_hw_state(plane_state);
254 plane_state->hw.crtc = from_plane_state->uapi.crtc;
255 plane_state->hw.fb = from_plane_state->uapi.fb;
256 if (plane_state->hw.fb)
257 drm_framebuffer_get(plane_state->hw.fb);
259 plane_state->hw.alpha = from_plane_state->uapi.alpha;
260 plane_state->hw.pixel_blend_mode =
261 from_plane_state->uapi.pixel_blend_mode;
262 plane_state->hw.rotation = from_plane_state->uapi.rotation;
263 plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
264 plane_state->hw.color_range = from_plane_state->uapi.color_range;
267 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
268 struct intel_plane_state *plane_state)
270 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
272 crtc_state->active_planes &= ~BIT(plane->id);
273 crtc_state->nv12_planes &= ~BIT(plane->id);
274 crtc_state->c8_planes &= ~BIT(plane->id);
275 crtc_state->data_rate[plane->id] = 0;
276 crtc_state->min_cdclk[plane->id] = 0;
278 plane_state->uapi.visible = false;
281 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
282 struct intel_crtc_state *new_crtc_state,
283 const struct intel_plane_state *old_plane_state,
284 struct intel_plane_state *new_plane_state)
286 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
287 const struct drm_framebuffer *fb = new_plane_state->hw.fb;
290 intel_plane_set_invisible(new_crtc_state, new_plane_state);
292 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
295 ret = plane->check_plane(new_crtc_state, new_plane_state);
299 /* FIXME pre-g4x don't work like this */
300 if (new_plane_state->uapi.visible)
301 new_crtc_state->active_planes |= BIT(plane->id);
303 if (new_plane_state->uapi.visible &&
304 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
305 new_crtc_state->nv12_planes |= BIT(plane->id);
307 if (new_plane_state->uapi.visible &&
308 fb->format->format == DRM_FORMAT_C8)
309 new_crtc_state->c8_planes |= BIT(plane->id);
311 if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
312 new_crtc_state->update_planes |= BIT(plane->id);
314 new_crtc_state->data_rate[plane->id] =
315 intel_plane_data_rate(new_crtc_state, new_plane_state);
317 return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
318 old_plane_state, new_plane_state);
321 static struct intel_crtc *
322 get_crtc_from_states(const struct intel_plane_state *old_plane_state,
323 const struct intel_plane_state *new_plane_state)
325 if (new_plane_state->uapi.crtc)
326 return to_intel_crtc(new_plane_state->uapi.crtc);
328 if (old_plane_state->uapi.crtc)
329 return to_intel_crtc(old_plane_state->uapi.crtc);
334 int intel_plane_atomic_check(struct intel_atomic_state *state,
335 struct intel_plane *plane)
337 struct intel_plane_state *new_plane_state =
338 intel_atomic_get_new_plane_state(state, plane);
339 const struct intel_plane_state *old_plane_state =
340 intel_atomic_get_old_plane_state(state, plane);
341 struct intel_crtc *crtc =
342 get_crtc_from_states(old_plane_state, new_plane_state);
343 const struct intel_crtc_state *old_crtc_state;
344 struct intel_crtc_state *new_crtc_state;
346 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
347 new_plane_state->uapi.visible = false;
351 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
352 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
354 return intel_plane_atomic_check_with_state(old_crtc_state,
360 static struct intel_plane *
361 skl_next_plane_to_commit(struct intel_atomic_state *state,
362 struct intel_crtc *crtc,
363 struct skl_ddb_entry entries_y[I915_MAX_PLANES],
364 struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
365 unsigned int *update_mask)
367 struct intel_crtc_state *crtc_state =
368 intel_atomic_get_new_crtc_state(state, crtc);
369 struct intel_plane_state *plane_state;
370 struct intel_plane *plane;
373 if (*update_mask == 0)
376 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
377 enum plane_id plane_id = plane->id;
379 if (crtc->pipe != plane->pipe ||
380 !(*update_mask & BIT(plane_id)))
383 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
385 I915_MAX_PLANES, plane_id) ||
386 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
388 I915_MAX_PLANES, plane_id))
391 *update_mask &= ~BIT(plane_id);
392 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
393 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
398 /* should never happen */
399 drm_WARN_ON(state->base.dev, 1);
404 void intel_update_plane(struct intel_plane *plane,
405 const struct intel_crtc_state *crtc_state,
406 const struct intel_plane_state *plane_state)
408 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
410 trace_intel_update_plane(&plane->base, crtc);
411 plane->update_plane(plane, crtc_state, plane_state);
414 void intel_disable_plane(struct intel_plane *plane,
415 const struct intel_crtc_state *crtc_state)
417 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
419 trace_intel_disable_plane(&plane->base, crtc);
420 plane->disable_plane(plane, crtc_state);
423 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
424 struct intel_crtc *crtc)
426 struct intel_crtc_state *old_crtc_state =
427 intel_atomic_get_old_crtc_state(state, crtc);
428 struct intel_crtc_state *new_crtc_state =
429 intel_atomic_get_new_crtc_state(state, crtc);
430 struct skl_ddb_entry entries_y[I915_MAX_PLANES];
431 struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
432 u32 update_mask = new_crtc_state->update_planes;
433 struct intel_plane *plane;
435 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
436 sizeof(old_crtc_state->wm.skl.plane_ddb_y));
437 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
438 sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
440 while ((plane = skl_next_plane_to_commit(state, crtc,
441 entries_y, entries_uv,
443 struct intel_plane_state *new_plane_state =
444 intel_atomic_get_new_plane_state(state, plane);
446 if (new_plane_state->uapi.visible ||
447 new_plane_state->planar_slave) {
448 intel_update_plane(plane, new_crtc_state, new_plane_state);
450 intel_disable_plane(plane, new_crtc_state);
455 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
456 struct intel_crtc *crtc)
458 struct intel_crtc_state *new_crtc_state =
459 intel_atomic_get_new_crtc_state(state, crtc);
460 u32 update_mask = new_crtc_state->update_planes;
461 struct intel_plane_state *new_plane_state;
462 struct intel_plane *plane;
465 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
466 if (crtc->pipe != plane->pipe ||
467 !(update_mask & BIT(plane->id)))
470 if (new_plane_state->uapi.visible)
471 intel_update_plane(plane, new_crtc_state, new_plane_state);
473 intel_disable_plane(plane, new_crtc_state);
477 const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
478 .prepare_fb = intel_prepare_plane_fb,
479 .cleanup_fb = intel_cleanup_plane_fb,