drivers/gpu/drm/i915/display/intel_atomic_plane.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic plane helpers
  26  *
  27  * The functions here are used by the atomic plane helper functions to
  28  * implement legacy plane updates (i.e., drm_plane->update_plane() and
  29  * drm_plane->disable_plane()).  This allows plane updates to use the
  30  * atomic state infrastructure and perform plane updates as separate
  31  * prepare/check/commit/cleanup steps.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_plane_helper.h>
  37
  38 #include "i915_trace.h"
  39 #include "intel_atomic_plane.h"
  40 #include "intel_cdclk.h"
  41 #include "intel_display_types.h"
  42 #include "intel_pm.h"
  43 #include "intel_sprite.h"
  44
  45 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
  46                                     struct intel_plane *plane)
  47 {
  48         memset(plane_state, 0, sizeof(*plane_state));
  49
  50         __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
  51
  52         plane_state->scaler_id = -1;
  53 }
  54
  55 struct intel_plane *intel_plane_alloc(void)
  56 {
  57         struct intel_plane_state *plane_state;
  58         struct intel_plane *plane;
  59
  60         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  61         if (!plane)
  62                 return ERR_PTR(-ENOMEM);
  63
  64         plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
  65         if (!plane_state) {
  66                 kfree(plane);
  67                 return ERR_PTR(-ENOMEM);
  68         }
  69
  70         intel_plane_state_reset(plane_state, plane);
  71
  72         plane->base.state = &plane_state->uapi;
  73
  74         return plane;
  75 }
  76
  77 void intel_plane_free(struct intel_plane *plane)
  78 {
  79         intel_plane_destroy_state(&plane->base, plane->base.state);
  80         kfree(plane);
  81 }
  82
  83 /**
  84  * intel_plane_duplicate_state - duplicate plane state
  85  * @plane: drm plane
  86  *
  87  * Allocates and returns a copy of the plane state (both common and
  88  * Intel-specific) for the specified plane.
  89  *
  90  * Returns: The newly allocated plane state, or NULL on failure.
  91  */
  92 struct drm_plane_state *
  93 intel_plane_duplicate_state(struct drm_plane *plane)
  94 {
  95         struct intel_plane_state *intel_state;
  96
  97         intel_state = to_intel_plane_state(plane->state);
  98         intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
  99
 100         if (!intel_state)
 101                 return NULL;
 102
 103         __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
 104
 105         intel_state->vma = NULL;
 106         intel_state->flags = 0;
 107
 108         /* add reference to fb */
 109         if (intel_state->hw.fb)
 110                 drm_framebuffer_get(intel_state->hw.fb);
 111
 112         return &intel_state->uapi;
 113 }
 114
 115 /**
 116  * intel_plane_destroy_state - destroy plane state
 117  * @plane: drm plane
 118  * @state: state object to destroy
 119  *
 120  * Destroys the plane state (both common and Intel-specific) for the
 121  * specified plane.
 122  */
 123 void
 124 intel_plane_destroy_state(struct drm_plane *plane,
 125                           struct drm_plane_state *state)
 126 {
 127         struct intel_plane_state *plane_state = to_intel_plane_state(state);
 128         WARN_ON(plane_state->vma);
 129
 130         __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
 131         if (plane_state->hw.fb)
 132                 drm_framebuffer_put(plane_state->hw.fb);
 133         kfree(plane_state);
 134 }
 135
 136 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 137                                    const struct intel_plane_state *plane_state)
 138 {
 139         const struct drm_framebuffer *fb = plane_state->hw.fb;
 140         unsigned int cpp;
 141
 142         if (!plane_state->uapi.visible)
 143                 return 0;
 144
 145         cpp = fb->format->cpp[0];
 146
 147         /*
 148          * Based on HSD#:1408715493
 149          * NV12 cpp == 4, P010 cpp == 8
 150          *
 151          * FIXME what is the logic behind this?
 152          */
 153         if (fb->format->is_yuv && fb->format->num_planes > 1)
 154                 cpp *= 4;
 155
 156         return cpp * crtc_state->pixel_rate;
 157 }
 158
 159 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 160                                struct intel_plane *plane,
 161                                bool *need_cdclk_calc)
 162 {
 163         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 164         const struct intel_plane_state *plane_state =
 165                 intel_atomic_get_new_plane_state(state, plane);
 166         struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
 167         const struct intel_cdclk_state *cdclk_state;
 168         struct intel_crtc_state *new_crtc_state =
 169                 intel_atomic_get_new_crtc_state(state, crtc);
 170         const struct intel_crtc_state *old_crtc_state =
 171                 intel_atomic_get_old_crtc_state(state, crtc);
 172
 173         if (!plane_state->uapi.visible || !plane->min_cdclk)
 174                 return 0;
 175
 176         new_crtc_state->min_cdclk[plane->id] =
 177                 plane->min_cdclk(new_crtc_state, plane_state);
 178
 179         /*
 180          * No need to check against the cdclk state if
 181          * the min cdclk for the plane doesn't increase.
 182          *
 183          * Ie. we only ever increase the cdclk due to plane
 184          * requirements. This can reduce back and forth
 185          * display blinking due to constant cdclk changes.
 186          */
 187         if (new_crtc_state->min_cdclk[plane->id] <=
 188             old_crtc_state->min_cdclk[plane->id])
 189                 return 0;
 190
 191         cdclk_state = intel_atomic_get_cdclk_state(state);
 192         if (IS_ERR(cdclk_state))
 193                 return PTR_ERR(cdclk_state);
 194
 195         /*
 196          * No need to recalculate the cdclk state if
 197          * the min cdclk for the pipe doesn't increase.
 198          *
 199          * Ie. we only ever increase the cdclk due to plane
 200          * requirements. This can reduce back and forth
 201          * display blinking due to constant cdclk changes.
 202          */
 203         if (new_crtc_state->min_cdclk[plane->id] <=
 204             cdclk_state->min_cdclk[crtc->pipe])
 205                 return 0;
 206
 207         drm_dbg_kms(&dev_priv->drm,
 208                     "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
 209                     plane->base.base.id, plane->base.name,
 210                     new_crtc_state->min_cdclk[plane->id],
 211                     crtc->base.base.id, crtc->base.name,
 212                     cdclk_state->min_cdclk[crtc->pipe]);
 213         *need_cdclk_calc = true;
 214
 215         return 0;
 216 }
 217
 218 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
 219 {
 220         if (plane_state->hw.fb)
 221                 drm_framebuffer_put(plane_state->hw.fb);
 222
 223         memset(&plane_state->hw, 0, sizeof(plane_state->hw));
 224 }
 225
 226 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 227                                        const struct intel_plane_state *from_plane_state)
 228 {
 229         intel_plane_clear_hw_state(plane_state);
 230
 231         plane_state->hw.crtc = from_plane_state->uapi.crtc;
 232         plane_state->hw.fb = from_plane_state->uapi.fb;
 233         if (plane_state->hw.fb)
 234                 drm_framebuffer_get(plane_state->hw.fb);
 235
 236         plane_state->hw.alpha = from_plane_state->uapi.alpha;
 237         plane_state->hw.pixel_blend_mode =
 238                 from_plane_state->uapi.pixel_blend_mode;
 239         plane_state->hw.rotation = from_plane_state->uapi.rotation;
 240         plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
 241         plane_state->hw.color_range = from_plane_state->uapi.color_range;
 242 }
 243
 244 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 245                                         struct intel_crtc_state *new_crtc_state,
 246                                         const struct intel_plane_state *old_plane_state,
 247                                         struct intel_plane_state *new_plane_state)
 248 {
 249         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 250         const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 251         int ret;
 252
 253         new_crtc_state->active_planes &= ~BIT(plane->id);
 254         new_crtc_state->nv12_planes &= ~BIT(plane->id);
 255         new_crtc_state->c8_planes &= ~BIT(plane->id);
 256         new_crtc_state->data_rate[plane->id] = 0;
 257         new_crtc_state->min_cdclk[plane->id] = 0;
 258         new_plane_state->uapi.visible = false;
 259
 260         if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 261                 return 0;
 262
 263         ret = plane->check_plane(new_crtc_state, new_plane_state);
 264         if (ret)
 265                 return ret;
 266
 267         /* FIXME pre-g4x don't work like this */
 268         if (new_plane_state->uapi.visible)
 269                 new_crtc_state->active_planes |= BIT(plane->id);
 270
 271         if (new_plane_state->uapi.visible &&
 272             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 273                 new_crtc_state->nv12_planes |= BIT(plane->id);
 274
 275         if (new_plane_state->uapi.visible &&
 276             fb->format->format == DRM_FORMAT_C8)
 277                 new_crtc_state->c8_planes |= BIT(plane->id);
 278
 279         if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 280                 new_crtc_state->update_planes |= BIT(plane->id);
 281
 282         new_crtc_state->data_rate[plane->id] =
 283                 intel_plane_data_rate(new_crtc_state, new_plane_state);
 284
 285         return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
 286                                                old_plane_state, new_plane_state);
 287 }
 288
 289 static struct intel_crtc *
 290 get_crtc_from_states(const struct intel_plane_state *old_plane_state,
 291                      const struct intel_plane_state *new_plane_state)
 292 {
 293         if (new_plane_state->uapi.crtc)
 294                 return to_intel_crtc(new_plane_state->uapi.crtc);
 295
 296         if (old_plane_state->uapi.crtc)
 297                 return to_intel_crtc(old_plane_state->uapi.crtc);
 298
 299         return NULL;
 300 }
 301
 302 int intel_plane_atomic_check(struct intel_atomic_state *state,
 303                              struct intel_plane *plane)
 304 {
 305         struct intel_plane_state *new_plane_state =
 306                 intel_atomic_get_new_plane_state(state, plane);
 307         const struct intel_plane_state *old_plane_state =
 308                 intel_atomic_get_old_plane_state(state, plane);
 309         struct intel_crtc *crtc =
 310                 get_crtc_from_states(old_plane_state, new_plane_state);
 311         const struct intel_crtc_state *old_crtc_state;
 312         struct intel_crtc_state *new_crtc_state;
 313
 314         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
 315         new_plane_state->uapi.visible = false;
 316         if (!crtc)
 317                 return 0;
 318
 319         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
 320         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 321
 322         return intel_plane_atomic_check_with_state(old_crtc_state,
 323                                                    new_crtc_state,
 324                                                    old_plane_state,
 325                                                    new_plane_state);
 326 }
 327
 328 static struct intel_plane *
 329 skl_next_plane_to_commit(struct intel_atomic_state *state,
 330                          struct intel_crtc *crtc,
 331                          struct skl_ddb_entry entries_y[I915_MAX_PLANES],
 332                          struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
 333                          unsigned int *update_mask)
 334 {
 335         struct intel_crtc_state *crtc_state =
 336                 intel_atomic_get_new_crtc_state(state, crtc);
 337         struct intel_plane_state *plane_state;
 338         struct intel_plane *plane;
 339         int i;
 340
 341         if (*update_mask == 0)
 342                 return NULL;
 343
 344         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 345                 enum plane_id plane_id = plane->id;
 346
 347                 if (crtc->pipe != plane->pipe ||
 348                     !(*update_mask & BIT(plane_id)))
 349                         continue;
 350
 351                 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
 352                                                 entries_y,
 353                                                 I915_MAX_PLANES, plane_id) ||
 354                     skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
 355                                                 entries_uv,
 356                                                 I915_MAX_PLANES, plane_id))
 357                         continue;
 358
 359                 *update_mask &= ~BIT(plane_id);
 360                 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 361                 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
 362
 363                 return plane;
 364         }
 365
 366         /* should never happen */
 367         WARN_ON(1);
 368
 369         return NULL;
 370 }
 371
 372 void intel_update_plane(struct intel_plane *plane,
 373                         const struct intel_crtc_state *crtc_state,
 374                         const struct intel_plane_state *plane_state)
 375 {
 376         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 377
 378         trace_intel_update_plane(&plane->base, crtc);
 379         plane->update_plane(plane, crtc_state, plane_state);
 380 }
 381
 382 void intel_disable_plane(struct intel_plane *plane,
 383                          const struct intel_crtc_state *crtc_state)
 384 {
 385         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 386
 387         trace_intel_disable_plane(&plane->base, crtc);
 388         plane->disable_plane(plane, crtc_state);
 389 }
 390
 391 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
 392                                struct intel_crtc *crtc)
 393 {
 394         struct intel_crtc_state *old_crtc_state =
 395                 intel_atomic_get_old_crtc_state(state, crtc);
 396         struct intel_crtc_state *new_crtc_state =
 397                 intel_atomic_get_new_crtc_state(state, crtc);
 398         struct skl_ddb_entry entries_y[I915_MAX_PLANES];
 399         struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
 400         u32 update_mask = new_crtc_state->update_planes;
 401         struct intel_plane *plane;
 402
 403         memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
 404                sizeof(old_crtc_state->wm.skl.plane_ddb_y));
 405         memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
 406                sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
 407
 408         while ((plane = skl_next_plane_to_commit(state, crtc,
 409                                                  entries_y, entries_uv,
 410                                                  &update_mask))) {
 411                 struct intel_plane_state *new_plane_state =
 412                         intel_atomic_get_new_plane_state(state, plane);
 413
 414                 if (new_plane_state->uapi.visible ||
 415                     new_plane_state->planar_slave) {
 416                         intel_update_plane(plane, new_crtc_state, new_plane_state);
 417                 } else {
 418                         intel_disable_plane(plane, new_crtc_state);
 419                 }
 420         }
 421 }
 422
 423 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
 424                                 struct intel_crtc *crtc)
 425 {
 426         struct intel_crtc_state *new_crtc_state =
 427                 intel_atomic_get_new_crtc_state(state, crtc);
 428         u32 update_mask = new_crtc_state->update_planes;
 429         struct intel_plane_state *new_plane_state;
 430         struct intel_plane *plane;
 431         int i;
 432
 433         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 434                 if (crtc->pipe != plane->pipe ||
 435                     !(update_mask & BIT(plane->id)))
 436                         continue;
 437
 438                 if (new_plane_state->uapi.visible)
 439                         intel_update_plane(plane, new_crtc_state, new_plane_state);
 440                 else
 441                         intel_disable_plane(plane, new_crtc_state);
 442         }
 443 }
 444
 445 const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
 446         .prepare_fb = intel_prepare_plane_fb,
 447         .cleanup_fb = intel_cleanup_plane_fb,
 448 };