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21 * DEALINGS IN THE SOFTWARE.
25 * DOC: atomic modeset support
27 * The functions here implement the state management and hardware programming
28 * dispatch required by the atomic modeset infrastructure.
29 * See intel_atomic_plane.c for the plane-specific atomic functionality.
32 #include <drm/drm_atomic.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_plane_helper.h>
37 #include "intel_atomic.h"
38 #include "intel_display_types.h"
39 #include "intel_hdcp.h"
40 #include "intel_sprite.h"
43 * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
44 * @connector: Connector to get the property for.
45 * @state: Connector state to retrieve the property from.
46 * @property: Property to retrieve.
47 * @val: Return value for the property.
49 * Returns the atomic property value for a digital connector.
51 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
52 const struct drm_connector_state *state,
53 struct drm_property *property,
56 struct drm_device *dev = connector->dev;
57 struct drm_i915_private *dev_priv = to_i915(dev);
58 struct intel_digital_connector_state *intel_conn_state =
59 to_intel_digital_connector_state(state);
61 if (property == dev_priv->force_audio_property)
62 *val = intel_conn_state->force_audio;
63 else if (property == dev_priv->broadcast_rgb_property)
64 *val = intel_conn_state->broadcast_rgb;
66 DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
67 property->base.id, property->name);
75 * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property.
76 * @connector: Connector to set the property for.
77 * @state: Connector state to set the property on.
78 * @property: Property to set.
79 * @val: New value for the property.
81 * Sets the atomic property value for a digital connector.
83 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
84 struct drm_connector_state *state,
85 struct drm_property *property,
88 struct drm_device *dev = connector->dev;
89 struct drm_i915_private *dev_priv = to_i915(dev);
90 struct intel_digital_connector_state *intel_conn_state =
91 to_intel_digital_connector_state(state);
93 if (property == dev_priv->force_audio_property) {
94 intel_conn_state->force_audio = val;
98 if (property == dev_priv->broadcast_rgb_property) {
99 intel_conn_state->broadcast_rgb = val;
103 DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
104 property->base.id, property->name);
108 static bool blob_equal(const struct drm_property_blob *a,
109 const struct drm_property_blob *b)
112 return a->length == b->length &&
113 !memcmp(a->data, b->data, a->length);
118 int intel_digital_connector_atomic_check(struct drm_connector *conn,
119 struct drm_atomic_state *state)
121 struct drm_connector_state *new_state =
122 drm_atomic_get_new_connector_state(state, conn);
123 struct intel_digital_connector_state *new_conn_state =
124 to_intel_digital_connector_state(new_state);
125 struct drm_connector_state *old_state =
126 drm_atomic_get_old_connector_state(state, conn);
127 struct intel_digital_connector_state *old_conn_state =
128 to_intel_digital_connector_state(old_state);
129 struct drm_crtc_state *crtc_state;
131 intel_hdcp_atomic_check(conn, old_state, new_state);
133 if (!new_state->crtc)
136 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
139 * These properties are handled by fastset, and might not end
142 if (new_conn_state->force_audio != old_conn_state->force_audio ||
143 new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
144 new_conn_state->base.colorspace != old_conn_state->base.colorspace ||
145 new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
146 new_conn_state->base.content_type != old_conn_state->base.content_type ||
147 new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
148 !blob_equal(new_conn_state->base.hdr_output_metadata,
149 old_conn_state->base.hdr_output_metadata))
150 crtc_state->mode_changed = true;
156 * intel_digital_connector_duplicate_state - duplicate connector state
157 * @connector: digital connector
159 * Allocates and returns a copy of the connector state (both common and
160 * digital connector specific) for the specified connector.
162 * Returns: The newly allocated connector state, or NULL on failure.
164 struct drm_connector_state *
165 intel_digital_connector_duplicate_state(struct drm_connector *connector)
167 struct intel_digital_connector_state *state;
169 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
173 __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
178 * intel_crtc_duplicate_state - duplicate crtc state
181 * Allocates and returns a copy of the crtc state (both common and
182 * Intel-specific) for the specified crtc.
184 * Returns: The newly allocated crtc state, or NULL on failure.
186 struct drm_crtc_state *
187 intel_crtc_duplicate_state(struct drm_crtc *crtc)
189 const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
190 struct intel_crtc_state *crtc_state;
192 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
196 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
198 /* copy color blobs */
199 if (crtc_state->hw.degamma_lut)
200 drm_property_blob_get(crtc_state->hw.degamma_lut);
201 if (crtc_state->hw.ctm)
202 drm_property_blob_get(crtc_state->hw.ctm);
203 if (crtc_state->hw.gamma_lut)
204 drm_property_blob_get(crtc_state->hw.gamma_lut);
206 crtc_state->update_pipe = false;
207 crtc_state->disable_lp_wm = false;
208 crtc_state->disable_cxsr = false;
209 crtc_state->update_wm_pre = false;
210 crtc_state->update_wm_post = false;
211 crtc_state->fifo_changed = false;
212 crtc_state->preload_luts = false;
213 crtc_state->wm.need_postvbl_update = false;
214 crtc_state->fb_bits = 0;
215 crtc_state->update_planes = 0;
217 return &crtc_state->uapi;
220 static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
222 drm_property_blob_put(crtc_state->hw.degamma_lut);
223 drm_property_blob_put(crtc_state->hw.gamma_lut);
224 drm_property_blob_put(crtc_state->hw.ctm);
227 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
229 intel_crtc_put_color_blobs(crtc_state);
232 void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
234 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
235 crtc_state->uapi.degamma_lut);
236 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
237 crtc_state->uapi.gamma_lut);
238 drm_property_replace_blob(&crtc_state->hw.ctm,
239 crtc_state->uapi.ctm);
243 * intel_crtc_destroy_state - destroy crtc state
245 * @state: the state to destroy
247 * Destroys the crtc state (both common and Intel-specific) for the
251 intel_crtc_destroy_state(struct drm_crtc *crtc,
252 struct drm_crtc_state *state)
254 struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
256 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
257 intel_crtc_free_hw_state(crtc_state);
261 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
262 int num_scalers_need, struct intel_crtc *intel_crtc,
263 const char *name, int idx,
264 struct intel_plane_state *plane_state,
267 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
271 if (*scaler_id < 0) {
272 /* find a free scaler */
273 for (j = 0; j < intel_crtc->num_scalers; j++) {
274 if (scaler_state->scalers[j].in_use)
278 scaler_state->scalers[*scaler_id].in_use = 1;
283 if (WARN(*scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx))
286 /* set scaler mode */
287 if (plane_state && plane_state->hw.fb &&
288 plane_state->hw.fb->format->is_yuv &&
289 plane_state->hw.fb->format->num_planes > 1) {
290 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
291 if (IS_GEN(dev_priv, 9) &&
292 !IS_GEMINILAKE(dev_priv)) {
293 mode = SKL_PS_SCALER_MODE_NV12;
294 } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
296 * On gen11+'s HDR planes we only use the scaler for
297 * scaling. They have a dedicated chroma upsampler, so
298 * we don't need the scaler to upsample the UV plane.
300 mode = PS_SCALER_MODE_NORMAL;
302 struct intel_plane *linked =
303 plane_state->planar_linked_plane;
305 mode = PS_SCALER_MODE_PLANAR;
308 mode |= PS_PLANE_Y_SEL(linked->id);
310 } else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
311 mode = PS_SCALER_MODE_NORMAL;
312 } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
314 * when only 1 scaler is in use on a pipe with 2 scalers
315 * scaler 0 operates in high quality (HQ) mode.
316 * In this case use scaler 0 to take advantage of HQ mode
318 scaler_state->scalers[*scaler_id].in_use = 0;
320 scaler_state->scalers[0].in_use = 1;
321 mode = SKL_PS_SCALER_MODE_HQ;
323 mode = SKL_PS_SCALER_MODE_DYN;
326 DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
327 intel_crtc->pipe, *scaler_id, name, idx);
328 scaler_state->scalers[*scaler_id].mode = mode;
332 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
333 * @dev_priv: i915 device
334 * @intel_crtc: intel crtc
335 * @crtc_state: incoming crtc_state to validate and setup scalers
337 * This function sets up scalers based on staged scaling requests for
338 * a @crtc and its planes. It is called from crtc level check path. If request
339 * is a supportable request, it attaches scalers to requested planes and crtc.
341 * This function takes into account the current scaler(s) in use by any planes
342 * not being part of this atomic state
345 * 0 - scalers were setup succesfully
346 * error code - otherwise
348 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
349 struct intel_crtc *intel_crtc,
350 struct intel_crtc_state *crtc_state)
352 struct drm_plane *plane = NULL;
353 struct intel_plane *intel_plane;
354 struct intel_plane_state *plane_state = NULL;
355 struct intel_crtc_scaler_state *scaler_state =
356 &crtc_state->scaler_state;
357 struct drm_atomic_state *drm_state = crtc_state->uapi.state;
358 struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
359 int num_scalers_need;
362 num_scalers_need = hweight32(scaler_state->scaler_users);
366 * - staged scaler requests are already in scaler_state->scaler_users
367 * - check whether staged scaling requests can be supported
368 * - add planes using scalers that aren't in current transaction
369 * - assign scalers to requested users
370 * - as part of plane commit, scalers will be committed
371 * (i.e., either attached or detached) to respective planes in hw
372 * - as part of crtc_commit, scaler will be either attached or detached
376 /* fail if required scalers > available scalers */
377 if (num_scalers_need > intel_crtc->num_scalers){
378 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
379 num_scalers_need, intel_crtc->num_scalers);
383 /* walkthrough scaler_users bits and start assigning scalers */
384 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
389 /* skip if scaler not required */
390 if (!(scaler_state->scaler_users & (1 << i)))
393 if (i == SKL_CRTC_INDEX) {
395 idx = intel_crtc->base.base.id;
397 /* panel fitter case: assign as a crtc scaler */
398 scaler_id = &scaler_state->scaler_id;
402 /* plane scaler case: assign as a plane scaler */
403 /* find the plane that set the bit as scaler_user */
404 plane = drm_state->planes[i].ptr;
407 * to enable/disable hq mode, add planes that are using scaler
408 * into this transaction
411 struct drm_plane_state *state;
414 * GLK+ scalers don't have a HQ mode so it
415 * isn't necessary to change between HQ and dyn mode
416 * on those platforms.
418 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
421 plane = drm_plane_from_index(&dev_priv->drm, i);
422 state = drm_atomic_get_plane_state(drm_state, plane);
424 DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
426 return PTR_ERR(state);
430 intel_plane = to_intel_plane(plane);
431 idx = plane->base.id;
433 /* plane on different crtc cannot be a scaler user of this crtc */
434 if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
437 plane_state = intel_atomic_get_new_plane_state(intel_state,
439 scaler_id = &plane_state->scaler_id;
442 intel_atomic_setup_scaler(scaler_state, num_scalers_need,
443 intel_crtc, name, idx,
444 plane_state, scaler_id);
450 struct drm_atomic_state *
451 intel_atomic_state_alloc(struct drm_device *dev)
453 struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
455 if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
463 void intel_atomic_state_clear(struct drm_atomic_state *s)
465 struct intel_atomic_state *state = to_intel_atomic_state(s);
466 drm_atomic_state_default_clear(&state->base);
467 state->dpll_set = state->modeset = false;
468 state->global_state_changed = false;
469 state->active_pipes = 0;
470 memset(&state->min_cdclk, 0, sizeof(state->min_cdclk));
471 memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level));
472 memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical));
473 memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual));
474 state->cdclk.pipe = INVALID_PIPE;
477 struct intel_crtc_state *
478 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
479 struct intel_crtc *crtc)
481 struct drm_crtc_state *crtc_state;
482 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
483 if (IS_ERR(crtc_state))
484 return ERR_CAST(crtc_state);
486 return to_intel_crtc_state(crtc_state);
489 int intel_atomic_lock_global_state(struct intel_atomic_state *state)
491 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
492 struct intel_crtc *crtc;
494 state->global_state_changed = true;
496 for_each_intel_crtc(&dev_priv->drm, crtc) {
499 ret = drm_modeset_lock(&crtc->base.mutex,
500 state->base.acquire_ctx);
508 int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
510 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
511 struct intel_crtc *crtc;
513 state->global_state_changed = true;
515 for_each_intel_crtc(&dev_priv->drm, crtc) {
516 struct intel_crtc_state *crtc_state;
518 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
519 if (IS_ERR(crtc_state))
520 return PTR_ERR(crtc_state);