drivers/gpu/drm/i915/display/intel_atomic.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic modeset support
  26  *
  27  * The functions here implement the state management and hardware programming
  28  * dispatch required by the atomic modeset infrastructure.
  29  * See intel_atomic_plane.c for the plane-specific atomic functionality.
  30  */
  31
  32 #include <drm/drm_atomic.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_plane_helper.h>
  36
  37 #include "intel_atomic.h"
  38 #include "intel_cdclk.h"
  39 #include "intel_display_types.h"
  40 #include "intel_global_state.h"
  41 #include "intel_hdcp.h"
  42 #include "intel_psr.h"
  43 #include "skl_universal_plane.h"
  44
  45 /**
  46  * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
  47  * @connector: Connector to get the property for.
  48  * @state: Connector state to retrieve the property from.
  49  * @property: Property to retrieve.
  50  * @val: Return value for the property.
  51  *
  52  * Returns the atomic property value for a digital connector.
  53  */
  54 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
  55                                                 const struct drm_connector_state *state,
  56                                                 struct drm_property *property,
  57                                                 u64 *val)
  58 {
  59         struct drm_device *dev = connector->dev;
  60         struct drm_i915_private *dev_priv = to_i915(dev);
  61         struct intel_digital_connector_state *intel_conn_state =
  62                 to_intel_digital_connector_state(state);
  63
  64         if (property == dev_priv->force_audio_property)
  65                 *val = intel_conn_state->force_audio;
  66         else if (property == dev_priv->broadcast_rgb_property)
  67                 *val = intel_conn_state->broadcast_rgb;
  68         else {
  69                 drm_dbg_atomic(&dev_priv->drm,
  70                                "Unknown property [PROP:%d:%s]\n",
  71                                property->base.id, property->name);
  72                 return -EINVAL;
  73         }
  74
  75         return 0;
  76 }
  77
  78 /**
  79  * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property.
  80  * @connector: Connector to set the property for.
  81  * @state: Connector state to set the property on.
  82  * @property: Property to set.
  83  * @val: New value for the property.
  84  *
  85  * Sets the atomic property value for a digital connector.
  86  */
  87 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
  88                                                 struct drm_connector_state *state,
  89                                                 struct drm_property *property,
  90                                                 u64 val)
  91 {
  92         struct drm_device *dev = connector->dev;
  93         struct drm_i915_private *dev_priv = to_i915(dev);
  94         struct intel_digital_connector_state *intel_conn_state =
  95                 to_intel_digital_connector_state(state);
  96
  97         if (property == dev_priv->force_audio_property) {
  98                 intel_conn_state->force_audio = val;
  99                 return 0;
 100         }
 101
 102         if (property == dev_priv->broadcast_rgb_property) {
 103                 intel_conn_state->broadcast_rgb = val;
 104                 return 0;
 105         }
 106
 107         drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n",
 108                        property->base.id, property->name);
 109         return -EINVAL;
 110 }
 111
 112 int intel_digital_connector_atomic_check(struct drm_connector *conn,
 113                                          struct drm_atomic_state *state)
 114 {
 115         struct drm_connector_state *new_state =
 116                 drm_atomic_get_new_connector_state(state, conn);
 117         struct intel_digital_connector_state *new_conn_state =
 118                 to_intel_digital_connector_state(new_state);
 119         struct drm_connector_state *old_state =
 120                 drm_atomic_get_old_connector_state(state, conn);
 121         struct intel_digital_connector_state *old_conn_state =
 122                 to_intel_digital_connector_state(old_state);
 123         struct drm_crtc_state *crtc_state;
 124
 125         intel_hdcp_atomic_check(conn, old_state, new_state);
 126
 127         if (!new_state->crtc)
 128                 return 0;
 129
 130         crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
 131
 132         /*
 133          * These properties are handled by fastset, and might not end
 134          * up in a modeset.
 135          */
 136         if (new_conn_state->force_audio != old_conn_state->force_audio ||
 137             new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
 138             new_conn_state->base.colorspace != old_conn_state->base.colorspace ||
 139             new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
 140             new_conn_state->base.content_type != old_conn_state->base.content_type ||
 141             new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
 142             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state))
 143                 crtc_state->mode_changed = true;
 144
 145         return 0;
 146 }
 147
 148 /**
 149  * intel_digital_connector_duplicate_state - duplicate connector state
 150  * @connector: digital connector
 151  *
 152  * Allocates and returns a copy of the connector state (both common and
 153  * digital connector specific) for the specified connector.
 154  *
 155  * Returns: The newly allocated connector state, or NULL on failure.
 156  */
 157 struct drm_connector_state *
 158 intel_digital_connector_duplicate_state(struct drm_connector *connector)
 159 {
 160         struct intel_digital_connector_state *state;
 161
 162         state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
 163         if (!state)
 164                 return NULL;
 165
 166         __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
 167         return &state->base;
 168 }
 169
 170 /**
 171  * intel_connector_needs_modeset - check if connector needs a modeset
 172  * @state: the atomic state corresponding to this modeset
 173  * @connector: the connector
 174  */
 175 bool
 176 intel_connector_needs_modeset(struct intel_atomic_state *state,
 177                               struct drm_connector *connector)
 178 {
 179         const struct drm_connector_state *old_conn_state, *new_conn_state;
 180
 181         old_conn_state = drm_atomic_get_old_connector_state(&state->base, connector);
 182         new_conn_state = drm_atomic_get_new_connector_state(&state->base, connector);
 183
 184         return old_conn_state->crtc != new_conn_state->crtc ||
 185                (new_conn_state->crtc &&
 186                 drm_atomic_crtc_needs_modeset(drm_atomic_get_new_crtc_state(&state->base,
 187                                                                             new_conn_state->crtc)));
 188 }
 189
 190 /**
 191  * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset
 192  * @state: the atomic state corresponding to this modeset
 193  *
 194  * Returns true if any CRTC in @state needs a modeset.
 195  */
 196 bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state)
 197 {
 198         struct intel_crtc *crtc;
 199         struct intel_crtc_state *crtc_state;
 200         int i;
 201
 202         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 203                 if (intel_crtc_needs_modeset(crtc_state))
 204                         return true;
 205         }
 206
 207         return false;
 208 }
 209
 210 struct intel_digital_connector_state *
 211 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
 212                                          struct intel_connector *connector)
 213 {
 214         struct drm_connector_state *conn_state;
 215
 216         conn_state = drm_atomic_get_connector_state(&state->base,
 217                                                     &connector->base);
 218         if (IS_ERR(conn_state))
 219                 return ERR_CAST(conn_state);
 220
 221         return to_intel_digital_connector_state(conn_state);
 222 }
 223
 224 /**
 225  * intel_crtc_duplicate_state - duplicate crtc state
 226  * @crtc: drm crtc
 227  *
 228  * Allocates and returns a copy of the crtc state (both common and
 229  * Intel-specific) for the specified crtc.
 230  *
 231  * Returns: The newly allocated crtc state, or NULL on failure.
 232  */
 233 struct drm_crtc_state *
 234 intel_crtc_duplicate_state(struct drm_crtc *crtc)
 235 {
 236         const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
 237         struct intel_crtc_state *crtc_state;
 238
 239         crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
 240         if (!crtc_state)
 241                 return NULL;
 242
 243         __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
 244
 245         /* copy color blobs */
 246         if (crtc_state->hw.degamma_lut)
 247                 drm_property_blob_get(crtc_state->hw.degamma_lut);
 248         if (crtc_state->hw.ctm)
 249                 drm_property_blob_get(crtc_state->hw.ctm);
 250         if (crtc_state->hw.gamma_lut)
 251                 drm_property_blob_get(crtc_state->hw.gamma_lut);
 252
 253         crtc_state->update_pipe = false;
 254         crtc_state->disable_lp_wm = false;
 255         crtc_state->disable_cxsr = false;
 256         crtc_state->update_wm_pre = false;
 257         crtc_state->update_wm_post = false;
 258         crtc_state->fifo_changed = false;
 259         crtc_state->preload_luts = false;
 260         crtc_state->inherited = false;
 261         crtc_state->wm.need_postvbl_update = false;
 262         crtc_state->fb_bits = 0;
 263         crtc_state->update_planes = 0;
 264         crtc_state->dsb = NULL;
 265
 266         return &crtc_state->uapi;
 267 }
 268
 269 static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
 270 {
 271         drm_property_blob_put(crtc_state->hw.degamma_lut);
 272         drm_property_blob_put(crtc_state->hw.gamma_lut);
 273         drm_property_blob_put(crtc_state->hw.ctm);
 274 }
 275
 276 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
 277 {
 278         intel_crtc_put_color_blobs(crtc_state);
 279 }
 280
 281 void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
 282                                  const struct intel_crtc_state *from_crtc_state)
 283 {
 284         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
 285                                   from_crtc_state->uapi.degamma_lut);
 286         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
 287                                   from_crtc_state->uapi.gamma_lut);
 288         drm_property_replace_blob(&crtc_state->hw.ctm,
 289                                   from_crtc_state->uapi.ctm);
 290 }
 291
 292 /**
 293  * intel_crtc_destroy_state - destroy crtc state
 294  * @crtc: drm crtc
 295  * @state: the state to destroy
 296  *
 297  * Destroys the crtc state (both common and Intel-specific) for the
 298  * specified crtc.
 299  */
 300 void
 301 intel_crtc_destroy_state(struct drm_crtc *crtc,
 302                          struct drm_crtc_state *state)
 303 {
 304         struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 305
 306         drm_WARN_ON(crtc->dev, crtc_state->dsb);
 307
 308         __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 309         intel_crtc_free_hw_state(crtc_state);
 310         kfree(crtc_state);
 311 }
 312
 313 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
 314                                       int num_scalers_need, struct intel_crtc *intel_crtc,
 315                                       const char *name, int idx,
 316                                       struct intel_plane_state *plane_state,
 317                                       int *scaler_id)
 318 {
 319         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 320         int j;
 321         u32 mode;
 322
 323         if (*scaler_id < 0) {
 324                 /* find a free scaler */
 325                 for (j = 0; j < intel_crtc->num_scalers; j++) {
 326                         if (scaler_state->scalers[j].in_use)
 327                                 continue;
 328
 329                         *scaler_id = j;
 330                         scaler_state->scalers[*scaler_id].in_use = 1;
 331                         break;
 332                 }
 333         }
 334
 335         if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
 336                      "Cannot find scaler for %s:%d\n", name, idx))
 337                 return;
 338
 339         /* set scaler mode */
 340         if (plane_state && plane_state->hw.fb &&
 341             plane_state->hw.fb->format->is_yuv &&
 342             plane_state->hw.fb->format->num_planes > 1) {
 343                 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 344                 if (DISPLAY_VER(dev_priv) == 9) {
 345                         mode = SKL_PS_SCALER_MODE_NV12;
 346                 } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
 347                         /*
 348                          * On gen11+'s HDR planes we only use the scaler for
 349                          * scaling. They have a dedicated chroma upsampler, so
 350                          * we don't need the scaler to upsample the UV plane.
 351                          */
 352                         mode = PS_SCALER_MODE_NORMAL;
 353                 } else {
 354                         struct intel_plane *linked =
 355                                 plane_state->planar_linked_plane;
 356
 357                         mode = PS_SCALER_MODE_PLANAR;
 358
 359                         if (linked)
 360                                 mode |= PS_PLANE_Y_SEL(linked->id);
 361                 }
 362         } else if (DISPLAY_VER(dev_priv) >= 10) {
 363                 mode = PS_SCALER_MODE_NORMAL;
 364         } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
 365                 /*
 366                  * when only 1 scaler is in use on a pipe with 2 scalers
 367                  * scaler 0 operates in high quality (HQ) mode.
 368                  * In this case use scaler 0 to take advantage of HQ mode
 369                  */
 370                 scaler_state->scalers[*scaler_id].in_use = 0;
 371                 *scaler_id = 0;
 372                 scaler_state->scalers[0].in_use = 1;
 373                 mode = SKL_PS_SCALER_MODE_HQ;
 374         } else {
 375                 mode = SKL_PS_SCALER_MODE_DYN;
 376         }
 377
 378         drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
 379                     intel_crtc->pipe, *scaler_id, name, idx);
 380         scaler_state->scalers[*scaler_id].mode = mode;
 381 }
 382
 383 /**
 384  * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
 385  * @dev_priv: i915 device
 386  * @intel_crtc: intel crtc
 387  * @crtc_state: incoming crtc_state to validate and setup scalers
 388  *
 389  * This function sets up scalers based on staged scaling requests for
 390  * a @crtc and its planes. It is called from crtc level check path. If request
 391  * is a supportable request, it attaches scalers to requested planes and crtc.
 392  *
 393  * This function takes into account the current scaler(s) in use by any planes
 394  * not being part of this atomic state
 395  *
 396  *  Returns:
 397  *         0 - scalers were setup succesfully
 398  *         error code - otherwise
 399  */
 400 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 401                                struct intel_crtc *intel_crtc,
 402                                struct intel_crtc_state *crtc_state)
 403 {
 404         struct drm_plane *plane = NULL;
 405         struct intel_plane *intel_plane;
 406         struct intel_plane_state *plane_state = NULL;
 407         struct intel_crtc_scaler_state *scaler_state =
 408                 &crtc_state->scaler_state;
 409         struct drm_atomic_state *drm_state = crtc_state->uapi.state;
 410         struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
 411         int num_scalers_need;
 412         int i;
 413
 414         num_scalers_need = hweight32(scaler_state->scaler_users);
 415
 416         /*
 417          * High level flow:
 418          * - staged scaler requests are already in scaler_state->scaler_users
 419          * - check whether staged scaling requests can be supported
 420          * - add planes using scalers that aren't in current transaction
 421          * - assign scalers to requested users
 422          * - as part of plane commit, scalers will be committed
 423          *   (i.e., either attached or detached) to respective planes in hw
 424          * - as part of crtc_commit, scaler will be either attached or detached
 425          *   to crtc in hw
 426          */
 427
 428         /* fail if required scalers > available scalers */
 429         if (num_scalers_need > intel_crtc->num_scalers){
 430                 drm_dbg_kms(&dev_priv->drm,
 431                             "Too many scaling requests %d > %d\n",
 432                             num_scalers_need, intel_crtc->num_scalers);
 433                 return -EINVAL;
 434         }
 435
 436         /* walkthrough scaler_users bits and start assigning scalers */
 437         for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 438                 int *scaler_id;
 439                 const char *name;
 440                 int idx;
 441
 442                 /* skip if scaler not required */
 443                 if (!(scaler_state->scaler_users & (1 << i)))
 444                         continue;
 445
 446                 if (i == SKL_CRTC_INDEX) {
 447                         name = "CRTC";
 448                         idx = intel_crtc->base.base.id;
 449
 450                         /* panel fitter case: assign as a crtc scaler */
 451                         scaler_id = &scaler_state->scaler_id;
 452                 } else {
 453                         name = "PLANE";
 454
 455                         /* plane scaler case: assign as a plane scaler */
 456                         /* find the plane that set the bit as scaler_user */
 457                         plane = drm_state->planes[i].ptr;
 458
 459                         /*
 460                          * to enable/disable hq mode, add planes that are using scaler
 461                          * into this transaction
 462                          */
 463                         if (!plane) {
 464                                 struct drm_plane_state *state;
 465
 466                                 /*
 467                                  * GLK+ scalers don't have a HQ mode so it
 468                                  * isn't necessary to change between HQ and dyn mode
 469                                  * on those platforms.
 470                                  */
 471                                 if (DISPLAY_VER(dev_priv) >= 10)
 472                                         continue;
 473
 474                                 plane = drm_plane_from_index(&dev_priv->drm, i);
 475                                 state = drm_atomic_get_plane_state(drm_state, plane);
 476                                 if (IS_ERR(state)) {
 477                                         drm_dbg_kms(&dev_priv->drm,
 478                                                     "Failed to add [PLANE:%d] to drm_state\n",
 479                                                     plane->base.id);
 480                                         return PTR_ERR(state);
 481                                 }
 482                         }
 483
 484                         intel_plane = to_intel_plane(plane);
 485                         idx = plane->base.id;
 486
 487                         /* plane on different crtc cannot be a scaler user of this crtc */
 488                         if (drm_WARN_ON(&dev_priv->drm,
 489                                         intel_plane->pipe != intel_crtc->pipe))
 490                                 continue;
 491
 492                         plane_state = intel_atomic_get_new_plane_state(intel_state,
 493                                                                        intel_plane);
 494                         scaler_id = &plane_state->scaler_id;
 495                 }
 496
 497                 intel_atomic_setup_scaler(scaler_state, num_scalers_need,
 498                                           intel_crtc, name, idx,
 499                                           plane_state, scaler_id);
 500         }
 501
 502         return 0;
 503 }
 504
 505 struct drm_atomic_state *
 506 intel_atomic_state_alloc(struct drm_device *dev)
 507 {
 508         struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 509
 510         if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
 511                 kfree(state);
 512                 return NULL;
 513         }
 514
 515         return &state->base;
 516 }
 517
 518 void intel_atomic_state_free(struct drm_atomic_state *_state)
 519 {
 520         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 521
 522         drm_atomic_state_default_release(&state->base);
 523         kfree(state->global_objs);
 524
 525         i915_sw_fence_fini(&state->commit_ready);
 526
 527         kfree(state);
 528 }
 529
 530 void intel_atomic_state_clear(struct drm_atomic_state *s)
 531 {
 532         struct intel_atomic_state *state = to_intel_atomic_state(s);
 533
 534         drm_atomic_state_default_clear(&state->base);
 535         intel_atomic_clear_global_state(state);
 536
 537         state->dpll_set = state->modeset = false;
 538 }
 539
 540 struct intel_crtc_state *
 541 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
 542                             struct intel_crtc *crtc)
 543 {
 544         struct drm_crtc_state *crtc_state;
 545         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
 546         if (IS_ERR(crtc_state))
 547                 return ERR_CAST(crtc_state);
 548
 549         return to_intel_crtc_state(crtc_state);
 550 }