drivers/gpu/drm/i915/display/icl_dsi.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *   Madhav Chauhan <madhav.chauhan@intel.com>
  25  *   Jani Nikula <jani.nikula@intel.com>
  26  */
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_mipi_dsi.h>
  30
  31 #include "intel_atomic.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_dsi.h"
  36 #include "intel_panel.h"
  37
  38 static inline int header_credits_available(struct drm_i915_private *dev_priv,
  39                                            enum transcoder dsi_trans)
  40 {
  41         return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  42                 >> FREE_HEADER_CREDIT_SHIFT;
  43 }
  44
  45 static inline int payload_credits_available(struct drm_i915_private *dev_priv,
  46                                             enum transcoder dsi_trans)
  47 {
  48         return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  49                 >> FREE_PLOAD_CREDIT_SHIFT;
  50 }
  51
  52 static void wait_for_header_credits(struct drm_i915_private *dev_priv,
  53                                     enum transcoder dsi_trans)
  54 {
  55         if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
  56                         MAX_HEADER_CREDIT, 100))
  57                 DRM_ERROR("DSI header credits not released\n");
  58 }
  59
  60 static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
  61                                      enum transcoder dsi_trans)
  62 {
  63         if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
  64                         MAX_PLOAD_CREDIT, 100))
  65                 DRM_ERROR("DSI payload credits not released\n");
  66 }
  67
  68 static enum transcoder dsi_port_to_transcoder(enum port port)
  69 {
  70         if (port == PORT_A)
  71                 return TRANSCODER_DSI_0;
  72         else
  73                 return TRANSCODER_DSI_1;
  74 }
  75
  76 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
  77 {
  78         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  79         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  80         struct mipi_dsi_device *dsi;
  81         enum port port;
  82         enum transcoder dsi_trans;
  83         int ret;
  84
  85         /* wait for header/payload credits to be released */
  86         for_each_dsi_port(port, intel_dsi->ports) {
  87                 dsi_trans = dsi_port_to_transcoder(port);
  88                 wait_for_header_credits(dev_priv, dsi_trans);
  89                 wait_for_payload_credits(dev_priv, dsi_trans);
  90         }
  91
  92         /* send nop DCS command */
  93         for_each_dsi_port(port, intel_dsi->ports) {
  94                 dsi = intel_dsi->dsi_hosts[port]->device;
  95                 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
  96                 dsi->channel = 0;
  97                 ret = mipi_dsi_dcs_nop(dsi);
  98                 if (ret < 0)
  99                         DRM_ERROR("error sending DCS NOP command\n");
 100         }
 101
 102         /* wait for header credits to be released */
 103         for_each_dsi_port(port, intel_dsi->ports) {
 104                 dsi_trans = dsi_port_to_transcoder(port);
 105                 wait_for_header_credits(dev_priv, dsi_trans);
 106         }
 107
 108         /* wait for LP TX in progress bit to be cleared */
 109         for_each_dsi_port(port, intel_dsi->ports) {
 110                 dsi_trans = dsi_port_to_transcoder(port);
 111                 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
 112                                   LPTX_IN_PROGRESS), 20))
 113                         DRM_ERROR("LPTX bit not cleared\n");
 114         }
 115 }
 116
 117 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
 118                                u32 len)
 119 {
 120         struct intel_dsi *intel_dsi = host->intel_dsi;
 121         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 122         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 123         int free_credits;
 124         int i, j;
 125
 126         for (i = 0; i < len; i += 4) {
 127                 u32 tmp = 0;
 128
 129                 free_credits = payload_credits_available(dev_priv, dsi_trans);
 130                 if (free_credits < 1) {
 131                         DRM_ERROR("Payload credit not available\n");
 132                         return false;
 133                 }
 134
 135                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 136                         tmp |= *data++ << 8 * j;
 137
 138                 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
 139         }
 140
 141         return true;
 142 }
 143
 144 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 145                             struct mipi_dsi_packet pkt, bool enable_lpdt)
 146 {
 147         struct intel_dsi *intel_dsi = host->intel_dsi;
 148         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 149         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 150         u32 tmp;
 151         int free_credits;
 152
 153         /* check if header credit available */
 154         free_credits = header_credits_available(dev_priv, dsi_trans);
 155         if (free_credits < 1) {
 156                 DRM_ERROR("send pkt header failed, not enough hdr credits\n");
 157                 return -1;
 158         }
 159
 160         tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
 161
 162         if (pkt.payload)
 163                 tmp |= PAYLOAD_PRESENT;
 164         else
 165                 tmp &= ~PAYLOAD_PRESENT;
 166
 167         tmp &= ~VBLANK_FENCE;
 168
 169         if (enable_lpdt)
 170                 tmp |= LP_DATA_TRANSFER;
 171
 172         tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 173         tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
 174         tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
 175         tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
 176         tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
 177         I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
 178
 179         return 0;
 180 }
 181
 182 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 183                               struct mipi_dsi_packet pkt)
 184 {
 185         /* payload queue can accept *256 bytes*, check limit */
 186         if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
 187                 DRM_ERROR("payload size exceeds max queue limit\n");
 188                 return -1;
 189         }
 190
 191         /* load data into command payload queue */
 192         if (!add_payld_to_queue(host, pkt.payload,
 193                                 pkt.payload_length)) {
 194                 DRM_ERROR("adding payload to queue failed\n");
 195                 return -1;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 202 {
 203         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 204         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 205         enum phy phy;
 206         u32 tmp;
 207         int lane;
 208
 209         for_each_dsi_phy(phy, intel_dsi->phys) {
 210                 /*
 211                  * Program voltage swing and pre-emphasis level values as per
 212                  * table in BSPEC under DDI buffer programing
 213                  */
 214                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
 215                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 216                 tmp |= SCALING_MODE_SEL(0x2);
 217                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 218                 tmp |= RTERM_SELECT(0x6);
 219                 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
 220
 221                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
 222                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 223                 tmp |= SCALING_MODE_SEL(0x2);
 224                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 225                 tmp |= RTERM_SELECT(0x6);
 226                 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
 227
 228                 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
 229                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 230                          RCOMP_SCALAR_MASK);
 231                 tmp |= SWING_SEL_UPPER(0x2);
 232                 tmp |= SWING_SEL_LOWER(0x2);
 233                 tmp |= RCOMP_SCALAR(0x98);
 234                 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
 235
 236                 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
 237                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 238                          RCOMP_SCALAR_MASK);
 239                 tmp |= SWING_SEL_UPPER(0x2);
 240                 tmp |= SWING_SEL_LOWER(0x2);
 241                 tmp |= RCOMP_SCALAR(0x98);
 242                 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
 243
 244                 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
 245                 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 246                          CURSOR_COEFF_MASK);
 247                 tmp |= POST_CURSOR_1(0x0);
 248                 tmp |= POST_CURSOR_2(0x0);
 249                 tmp |= CURSOR_COEFF(0x3f);
 250                 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
 251
 252                 for (lane = 0; lane <= 3; lane++) {
 253                         /* Bspec: must not use GRP register for write */
 254                         tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
 255                         tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 256                                  CURSOR_COEFF_MASK);
 257                         tmp |= POST_CURSOR_1(0x0);
 258                         tmp |= POST_CURSOR_2(0x0);
 259                         tmp |= CURSOR_COEFF(0x3f);
 260                         I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 261                 }
 262         }
 263 }
 264
 265 static void configure_dual_link_mode(struct intel_encoder *encoder,
 266                                      const struct intel_crtc_state *pipe_config)
 267 {
 268         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 269         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 270         u32 dss_ctl1;
 271
 272         dss_ctl1 = I915_READ(DSS_CTL1);
 273         dss_ctl1 |= SPLITTER_ENABLE;
 274         dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 275         dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 276
 277         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 278                 const struct drm_display_mode *adjusted_mode =
 279                                         &pipe_config->hw.adjusted_mode;
 280                 u32 dss_ctl2;
 281                 u16 hactive = adjusted_mode->crtc_hdisplay;
 282                 u16 dl_buffer_depth;
 283
 284                 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 285                 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 286
 287                 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 288                         DRM_ERROR("DL buffer depth exceed max value\n");
 289
 290                 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 291                 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 292                 dss_ctl2 = I915_READ(DSS_CTL2);
 293                 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
 294                 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 295                 I915_WRITE(DSS_CTL2, dss_ctl2);
 296         } else {
 297                 /* Interleave */
 298                 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 299         }
 300
 301         I915_WRITE(DSS_CTL1, dss_ctl1);
 302 }
 303
 304 /* aka DSI 8X clock */
 305 static int afe_clk(struct intel_encoder *encoder)
 306 {
 307         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 308         int bpp;
 309
 310         bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 311
 312         return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 313 }
 314
 315 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 316 {
 317         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 318         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 319         enum port port;
 320         int afe_clk_khz;
 321         u32 esc_clk_div_m;
 322
 323         afe_clk_khz = afe_clk(encoder);
 324         esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 325
 326         for_each_dsi_port(port, intel_dsi->ports) {
 327                 I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
 328                            esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 329                 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
 330         }
 331
 332         for_each_dsi_port(port, intel_dsi->ports) {
 333                 I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
 334                            esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 335                 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
 336         }
 337 }
 338
 339 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
 340                                      struct intel_dsi *intel_dsi)
 341 {
 342         enum port port;
 343
 344         for_each_dsi_port(port, intel_dsi->ports) {
 345                 WARN_ON(intel_dsi->io_wakeref[port]);
 346                 intel_dsi->io_wakeref[port] =
 347                         intel_display_power_get(dev_priv,
 348                                                 port == PORT_A ?
 349                                                 POWER_DOMAIN_PORT_DDI_A_IO :
 350                                                 POWER_DOMAIN_PORT_DDI_B_IO);
 351         }
 352 }
 353
 354 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 355 {
 356         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 357         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 358         enum port port;
 359         u32 tmp;
 360
 361         for_each_dsi_port(port, intel_dsi->ports) {
 362                 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
 363                 tmp |= COMBO_PHY_MODE_DSI;
 364                 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
 365         }
 366
 367         get_dsi_io_power_domains(dev_priv, intel_dsi);
 368 }
 369
 370 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 371 {
 372         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 373         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 374         enum phy phy;
 375
 376         for_each_dsi_phy(phy, intel_dsi->phys)
 377                 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 378                                                intel_dsi->lane_count, false);
 379 }
 380
 381 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 382 {
 383         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 384         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 385         enum phy phy;
 386         u32 tmp;
 387         int lane;
 388
 389         /* Step 4b(i) set loadgen select for transmit and aux lanes */
 390         for_each_dsi_phy(phy, intel_dsi->phys) {
 391                 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
 392                 tmp &= ~LOADGEN_SELECT;
 393                 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
 394                 for (lane = 0; lane <= 3; lane++) {
 395                         tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
 396                         tmp &= ~LOADGEN_SELECT;
 397                         if (lane != 2)
 398                                 tmp |= LOADGEN_SELECT;
 399                         I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 400                 }
 401         }
 402
 403         /* Step 4b(ii) set latency optimization for transmit and aux lanes */
 404         for_each_dsi_phy(phy, intel_dsi->phys) {
 405                 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
 406                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 407                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 408                 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
 409                 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
 410                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 411                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 412                 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
 413
 414                 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
 415                 if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
 416                         tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
 417                         tmp &= ~LATENCY_OPTIM_MASK;
 418                         tmp |= LATENCY_OPTIM_VAL(0);
 419                         I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
 420
 421                         tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
 422                         tmp &= ~LATENCY_OPTIM_MASK;
 423                         tmp |= LATENCY_OPTIM_VAL(0x1);
 424                         I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
 425                 }
 426         }
 427
 428 }
 429
 430 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 431 {
 432         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 433         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 434         u32 tmp;
 435         enum phy phy;
 436
 437         /* clear common keeper enable bit */
 438         for_each_dsi_phy(phy, intel_dsi->phys) {
 439                 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
 440                 tmp &= ~COMMON_KEEPER_EN;
 441                 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
 442                 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
 443                 tmp &= ~COMMON_KEEPER_EN;
 444                 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
 445         }
 446
 447         /*
 448          * Set SUS Clock Config bitfield to 11b
 449          * Note: loadgen select program is done
 450          * as part of lane phy sequence configuration
 451          */
 452         for_each_dsi_phy(phy, intel_dsi->phys) {
 453                 tmp = I915_READ(ICL_PORT_CL_DW5(phy));
 454                 tmp |= SUS_CLOCK_CONFIG;
 455                 I915_WRITE(ICL_PORT_CL_DW5(phy), tmp);
 456         }
 457
 458         /* Clear training enable to change swing values */
 459         for_each_dsi_phy(phy, intel_dsi->phys) {
 460                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
 461                 tmp &= ~TX_TRAINING_EN;
 462                 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
 463                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
 464                 tmp &= ~TX_TRAINING_EN;
 465                 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
 466         }
 467
 468         /* Program swing and de-emphasis */
 469         dsi_program_swing_and_deemphasis(encoder);
 470
 471         /* Set training enable to trigger update */
 472         for_each_dsi_phy(phy, intel_dsi->phys) {
 473                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
 474                 tmp |= TX_TRAINING_EN;
 475                 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
 476                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
 477                 tmp |= TX_TRAINING_EN;
 478                 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
 479         }
 480 }
 481
 482 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 483 {
 484         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 485         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 486         u32 tmp;
 487         enum port port;
 488
 489         for_each_dsi_port(port, intel_dsi->ports) {
 490                 tmp = I915_READ(DDI_BUF_CTL(port));
 491                 tmp |= DDI_BUF_CTL_ENABLE;
 492                 I915_WRITE(DDI_BUF_CTL(port), tmp);
 493
 494                 if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
 495                                   DDI_BUF_IS_IDLE),
 496                                   500))
 497                         DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
 498         }
 499 }
 500
 501 static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 502 {
 503         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 504         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 505         u32 tmp;
 506         enum port port;
 507         enum phy phy;
 508
 509         /* Program T-INIT master registers */
 510         for_each_dsi_port(port, intel_dsi->ports) {
 511                 tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
 512                 tmp &= ~MASTER_INIT_TIMER_MASK;
 513                 tmp |= intel_dsi->init_count;
 514                 I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
 515         }
 516
 517         /* Program DPHY clock lanes timings */
 518         for_each_dsi_port(port, intel_dsi->ports) {
 519                 I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
 520
 521                 /* shadow register inside display core */
 522                 I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
 523         }
 524
 525         /* Program DPHY data lanes timings */
 526         for_each_dsi_port(port, intel_dsi->ports) {
 527                 I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
 528                            intel_dsi->dphy_data_lane_reg);
 529
 530                 /* shadow register inside display core */
 531                 I915_WRITE(DSI_DATA_TIMING_PARAM(port),
 532                            intel_dsi->dphy_data_lane_reg);
 533         }
 534
 535         /*
 536          * If DSI link operating at or below an 800 MHz,
 537          * TA_SURE should be override and programmed to
 538          * a value '0' inside TA_PARAM_REGISTERS otherwise
 539          * leave all fields at HW default values.
 540          */
 541         if (IS_GEN(dev_priv, 11)) {
 542                 if (intel_dsi_bitrate(intel_dsi) <= 800000) {
 543                         for_each_dsi_port(port, intel_dsi->ports) {
 544                                 tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
 545                                 tmp &= ~TA_SURE_MASK;
 546                                 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 547                                 I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
 548
 549                                 /* shadow register inside display core */
 550                                 tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
 551                                 tmp &= ~TA_SURE_MASK;
 552                                 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 553                                 I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
 554                         }
 555                 }
 556         }
 557
 558         if (IS_ELKHARTLAKE(dev_priv)) {
 559                 for_each_dsi_phy(phy, intel_dsi->phys) {
 560                         tmp = I915_READ(ICL_DPHY_CHKN(phy));
 561                         tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
 562                         I915_WRITE(ICL_DPHY_CHKN(phy), tmp);
 563                 }
 564         }
 565 }
 566
 567 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 568 {
 569         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 570         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 571         u32 tmp;
 572         enum phy phy;
 573
 574         mutex_lock(&dev_priv->dpll_lock);
 575         tmp = I915_READ(ICL_DPCLKA_CFGCR0);
 576         for_each_dsi_phy(phy, intel_dsi->phys)
 577                 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 578
 579         I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
 580         mutex_unlock(&dev_priv->dpll_lock);
 581 }
 582
 583 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 584 {
 585         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 586         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 587         u32 tmp;
 588         enum phy phy;
 589
 590         mutex_lock(&dev_priv->dpll_lock);
 591         tmp = I915_READ(ICL_DPCLKA_CFGCR0);
 592         for_each_dsi_phy(phy, intel_dsi->phys)
 593                 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 594
 595         I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
 596         mutex_unlock(&dev_priv->dpll_lock);
 597 }
 598
 599 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 600                               const struct intel_crtc_state *crtc_state)
 601 {
 602         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 603         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 604         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 605         enum phy phy;
 606         u32 val;
 607
 608         mutex_lock(&dev_priv->dpll_lock);
 609
 610         val = I915_READ(ICL_DPCLKA_CFGCR0);
 611         for_each_dsi_phy(phy, intel_dsi->phys) {
 612                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 613                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 614         }
 615         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
 616
 617         for_each_dsi_phy(phy, intel_dsi->phys) {
 618                 if (INTEL_GEN(dev_priv) >= 12)
 619                         val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 620                 else
 621                         val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 622         }
 623         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
 624
 625         POSTING_READ(ICL_DPCLKA_CFGCR0);
 626
 627         mutex_unlock(&dev_priv->dpll_lock);
 628 }
 629
 630 static void
 631 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 632                                const struct intel_crtc_state *pipe_config)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 635         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 636         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 637         enum pipe pipe = intel_crtc->pipe;
 638         u32 tmp;
 639         enum port port;
 640         enum transcoder dsi_trans;
 641
 642         for_each_dsi_port(port, intel_dsi->ports) {
 643                 dsi_trans = dsi_port_to_transcoder(port);
 644                 tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
 645
 646                 if (intel_dsi->eotp_pkt)
 647                         tmp &= ~EOTP_DISABLED;
 648                 else
 649                         tmp |= EOTP_DISABLED;
 650
 651                 /* enable link calibration if freq > 1.5Gbps */
 652                 if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
 653                         tmp &= ~LINK_CALIBRATION_MASK;
 654                         tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 655                 }
 656
 657                 /* configure continuous clock */
 658                 tmp &= ~CONTINUOUS_CLK_MASK;
 659                 if (intel_dsi->clock_stop)
 660                         tmp |= CLK_ENTER_LP_AFTER_DATA;
 661                 else
 662                         tmp |= CLK_HS_CONTINUOUS;
 663
 664                 /* configure buffer threshold limit to minimum */
 665                 tmp &= ~PIX_BUF_THRESHOLD_MASK;
 666                 tmp |= PIX_BUF_THRESHOLD_1_4;
 667
 668                 /* set virtual channel to '0' */
 669                 tmp &= ~PIX_VIRT_CHAN_MASK;
 670                 tmp |= PIX_VIRT_CHAN(0);
 671
 672                 /* program BGR transmission */
 673                 if (intel_dsi->bgr_enabled)
 674                         tmp |= BGR_TRANSMISSION;
 675
 676                 /* select pixel format */
 677                 tmp &= ~PIX_FMT_MASK;
 678                 switch (intel_dsi->pixel_format) {
 679                 default:
 680                         MISSING_CASE(intel_dsi->pixel_format);
 681                         /* fallthrough */
 682                 case MIPI_DSI_FMT_RGB565:
 683                         tmp |= PIX_FMT_RGB565;
 684                         break;
 685                 case MIPI_DSI_FMT_RGB666_PACKED:
 686                         tmp |= PIX_FMT_RGB666_PACKED;
 687                         break;
 688                 case MIPI_DSI_FMT_RGB666:
 689                         tmp |= PIX_FMT_RGB666_LOOSE;
 690                         break;
 691                 case MIPI_DSI_FMT_RGB888:
 692                         tmp |= PIX_FMT_RGB888;
 693                         break;
 694                 }
 695
 696                 if (INTEL_GEN(dev_priv) >= 12) {
 697                         if (is_vid_mode(intel_dsi))
 698                                 tmp |= BLANKING_PACKET_ENABLE;
 699                 }
 700
 701                 /* program DSI operation mode */
 702                 if (is_vid_mode(intel_dsi)) {
 703                         tmp &= ~OP_MODE_MASK;
 704                         switch (intel_dsi->video_mode_format) {
 705                         default:
 706                                 MISSING_CASE(intel_dsi->video_mode_format);
 707                                 /* fallthrough */
 708                         case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
 709                                 tmp |= VIDEO_MODE_SYNC_EVENT;
 710                                 break;
 711                         case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
 712                                 tmp |= VIDEO_MODE_SYNC_PULSE;
 713                                 break;
 714                         }
 715                 }
 716
 717                 I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 718         }
 719
 720         /* enable port sync mode if dual link */
 721         if (intel_dsi->dual_link) {
 722                 for_each_dsi_port(port, intel_dsi->ports) {
 723                         dsi_trans = dsi_port_to_transcoder(port);
 724                         tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
 725                         tmp |= PORT_SYNC_MODE_ENABLE;
 726                         I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
 727                 }
 728
 729                 /* configure stream splitting */
 730                 configure_dual_link_mode(encoder, pipe_config);
 731         }
 732
 733         for_each_dsi_port(port, intel_dsi->ports) {
 734                 dsi_trans = dsi_port_to_transcoder(port);
 735
 736                 /* select data lane width */
 737                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
 738                 tmp &= ~DDI_PORT_WIDTH_MASK;
 739                 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 740
 741                 /* select input pipe */
 742                 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 743                 switch (pipe) {
 744                 default:
 745                         MISSING_CASE(pipe);
 746                         /* fallthrough */
 747                 case PIPE_A:
 748                         tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 749                         break;
 750                 case PIPE_B:
 751                         tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 752                         break;
 753                 case PIPE_C:
 754                         tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 755                         break;
 756                 case PIPE_D:
 757                         tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
 758                         break;
 759                 }
 760
 761                 /* enable DDI buffer */
 762                 tmp |= TRANS_DDI_FUNC_ENABLE;
 763                 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
 764         }
 765
 766         /* wait for link ready */
 767         for_each_dsi_port(port, intel_dsi->ports) {
 768                 dsi_trans = dsi_port_to_transcoder(port);
 769                 if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
 770                                 LINK_READY), 2500))
 771                         DRM_ERROR("DSI link not ready\n");
 772         }
 773 }
 774
 775 static void
 776 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 777                                  const struct intel_crtc_state *pipe_config)
 778 {
 779         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 780         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 781         const struct drm_display_mode *adjusted_mode =
 782                                         &pipe_config->hw.adjusted_mode;
 783         enum port port;
 784         enum transcoder dsi_trans;
 785         /* horizontal timings */
 786         u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 787         u16 hback_porch;
 788         /* vertical timings */
 789         u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 790
 791         hactive = adjusted_mode->crtc_hdisplay;
 792         htotal = adjusted_mode->crtc_htotal;
 793         hsync_start = adjusted_mode->crtc_hsync_start;
 794         hsync_end = adjusted_mode->crtc_hsync_end;
 795         hsync_size  = hsync_end - hsync_start;
 796         hback_porch = (adjusted_mode->crtc_htotal -
 797                        adjusted_mode->crtc_hsync_end);
 798         vactive = adjusted_mode->crtc_vdisplay;
 799         vtotal = adjusted_mode->crtc_vtotal;
 800         vsync_start = adjusted_mode->crtc_vsync_start;
 801         vsync_end = adjusted_mode->crtc_vsync_end;
 802         vsync_shift = hsync_start - htotal / 2;
 803
 804         if (intel_dsi->dual_link) {
 805                 hactive /= 2;
 806                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 807                         hactive += intel_dsi->pixel_overlap;
 808                 htotal /= 2;
 809         }
 810
 811         /* minimum hactive as per bspec: 256 pixels */
 812         if (adjusted_mode->crtc_hdisplay < 256)
 813                 DRM_ERROR("hactive is less then 256 pixels\n");
 814
 815         /* if RGB666 format, then hactive must be multiple of 4 pixels */
 816         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 817                 DRM_ERROR("hactive pixels are not multiple of 4\n");
 818
 819         /* program TRANS_HTOTAL register */
 820         for_each_dsi_port(port, intel_dsi->ports) {
 821                 dsi_trans = dsi_port_to_transcoder(port);
 822                 I915_WRITE(HTOTAL(dsi_trans),
 823                            (hactive - 1) | ((htotal - 1) << 16));
 824         }
 825
 826         /* TRANS_HSYNC register to be programmed only for video mode */
 827         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
 828                 if (intel_dsi->video_mode_format ==
 829                     VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 830                         /* BSPEC: hsync size should be atleast 16 pixels */
 831                         if (hsync_size < 16)
 832                                 DRM_ERROR("hsync size < 16 pixels\n");
 833                 }
 834
 835                 if (hback_porch < 16)
 836                         DRM_ERROR("hback porch < 16 pixels\n");
 837
 838                 if (intel_dsi->dual_link) {
 839                         hsync_start /= 2;
 840                         hsync_end /= 2;
 841                 }
 842
 843                 for_each_dsi_port(port, intel_dsi->ports) {
 844                         dsi_trans = dsi_port_to_transcoder(port);
 845                         I915_WRITE(HSYNC(dsi_trans),
 846                                    (hsync_start - 1) | ((hsync_end - 1) << 16));
 847                 }
 848         }
 849
 850         /* program TRANS_VTOTAL register */
 851         for_each_dsi_port(port, intel_dsi->ports) {
 852                 dsi_trans = dsi_port_to_transcoder(port);
 853                 /*
 854                  * FIXME: Programing this by assuming progressive mode, since
 855                  * non-interlaced info from VBT is not saved inside
 856                  * struct drm_display_mode.
 857                  * For interlace mode: program required pixel minus 2
 858                  */
 859                 I915_WRITE(VTOTAL(dsi_trans),
 860                            (vactive - 1) | ((vtotal - 1) << 16));
 861         }
 862
 863         if (vsync_end < vsync_start || vsync_end > vtotal)
 864                 DRM_ERROR("Invalid vsync_end value\n");
 865
 866         if (vsync_start < vactive)
 867                 DRM_ERROR("vsync_start less than vactive\n");
 868
 869         /* program TRANS_VSYNC register */
 870         for_each_dsi_port(port, intel_dsi->ports) {
 871                 dsi_trans = dsi_port_to_transcoder(port);
 872                 I915_WRITE(VSYNC(dsi_trans),
 873                            (vsync_start - 1) | ((vsync_end - 1) << 16));
 874         }
 875
 876         /*
 877          * FIXME: It has to be programmed only for interlaced
 878          * modes. Put the check condition here once interlaced
 879          * info available as described above.
 880          * program TRANS_VSYNCSHIFT register
 881          */
 882         for_each_dsi_port(port, intel_dsi->ports) {
 883                 dsi_trans = dsi_port_to_transcoder(port);
 884                 I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
 885         }
 886
 887         /* program TRANS_VBLANK register, should be same as vtotal programmed */
 888         if (INTEL_GEN(dev_priv) >= 12) {
 889                 for_each_dsi_port(port, intel_dsi->ports) {
 890                         dsi_trans = dsi_port_to_transcoder(port);
 891                         I915_WRITE(VBLANK(dsi_trans),
 892                                    (vactive - 1) | ((vtotal - 1) << 16));
 893                 }
 894         }
 895 }
 896
 897 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 898 {
 899         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 900         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 901         enum port port;
 902         enum transcoder dsi_trans;
 903         u32 tmp;
 904
 905         for_each_dsi_port(port, intel_dsi->ports) {
 906                 dsi_trans = dsi_port_to_transcoder(port);
 907                 tmp = I915_READ(PIPECONF(dsi_trans));
 908                 tmp |= PIPECONF_ENABLE;
 909                 I915_WRITE(PIPECONF(dsi_trans), tmp);
 910
 911                 /* wait for transcoder to be enabled */
 912                 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
 913                                           I965_PIPECONF_ACTIVE, 10))
 914                         DRM_ERROR("DSI transcoder not enabled\n");
 915         }
 916 }
 917
 918 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 919 {
 920         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 921         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 922         enum port port;
 923         enum transcoder dsi_trans;
 924         u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
 925
 926         /*
 927          * escape clock count calculation:
 928          * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
 929          * UI (nsec) = (10^6)/Bitrate
 930          * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
 931          * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
 932          */
 933         divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
 934         mul = 8 * 1000000;
 935         hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
 936                                      divisor);
 937         lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
 938         ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
 939
 940         for_each_dsi_port(port, intel_dsi->ports) {
 941                 dsi_trans = dsi_port_to_transcoder(port);
 942
 943                 /* program hst_tx_timeout */
 944                 tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
 945                 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
 946                 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
 947                 I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
 948
 949                 /* FIXME: DSI_CALIB_TO */
 950
 951                 /* program lp_rx_host timeout */
 952                 tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
 953                 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
 954                 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
 955                 I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
 956
 957                 /* FIXME: DSI_PWAIT_TO */
 958
 959                 /* program turn around timeout */
 960                 tmp = I915_READ(DSI_TA_TO(dsi_trans));
 961                 tmp &= ~TA_TIMEOUT_VALUE_MASK;
 962                 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
 963                 I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
 964         }
 965 }
 966
 967 static void
 968 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 969                               const struct intel_crtc_state *pipe_config)
 970 {
 971         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 972
 973         /* step 4a: power up all lanes of the DDI used by DSI */
 974         gen11_dsi_power_up_lanes(encoder);
 975
 976         /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
 977         gen11_dsi_config_phy_lanes_sequence(encoder);
 978
 979         /* step 4c: configure voltage swing and skew */
 980         gen11_dsi_voltage_swing_program_seq(encoder);
 981
 982         /* enable DDI buffer */
 983         gen11_dsi_enable_ddi_buffer(encoder);
 984
 985         /* setup D-PHY timings */
 986         gen11_dsi_setup_dphy_timings(encoder);
 987
 988         /* step 4h: setup DSI protocol timeouts */
 989         gen11_dsi_setup_timeouts(encoder);
 990
 991         /* Step (4h, 4i, 4j, 4k): Configure transcoder */
 992         gen11_dsi_configure_transcoder(encoder, pipe_config);
 993
 994         /* Step 4l: Gate DDI clocks */
 995         if (IS_GEN(dev_priv, 11))
 996                 gen11_dsi_gate_clocks(encoder);
 997 }
 998
 999 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1000 {
1001         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1002         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1003         struct mipi_dsi_device *dsi;
1004         enum port port;
1005         enum transcoder dsi_trans;
1006         u32 tmp;
1007         int ret;
1008
1009         /* set maximum return packet size */
1010         for_each_dsi_port(port, intel_dsi->ports) {
1011                 dsi_trans = dsi_port_to_transcoder(port);
1012
1013                 /*
1014                  * FIXME: This uses the number of DW's currently in the payload
1015                  * receive queue. This is probably not what we want here.
1016                  */
1017                 tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
1018                 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1019                 /* multiply "Number Rx Payload DW" by 4 to get max value */
1020                 tmp = tmp * 4;
1021                 dsi = intel_dsi->dsi_hosts[port]->device;
1022                 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1023                 if (ret < 0)
1024                         DRM_ERROR("error setting max return pkt size%d\n", tmp);
1025         }
1026
1027         /* panel power on related mipi dsi vbt sequences */
1028         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1029         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
1030         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1031         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1032         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1033
1034         /* ensure all panel commands dispatched before enabling transcoder */
1035         wait_for_cmds_dispatched_to_panel(encoder);
1036 }
1037
1038 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
1039                                      const struct intel_crtc_state *pipe_config,
1040                                      const struct drm_connector_state *conn_state)
1041 {
1042         /* step2: enable IO power */
1043         gen11_dsi_enable_io_power(encoder);
1044
1045         /* step3: enable DSI PLL */
1046         gen11_dsi_program_esc_clk_div(encoder);
1047 }
1048
1049 static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
1050                                  const struct intel_crtc_state *pipe_config,
1051                                  const struct drm_connector_state *conn_state)
1052 {
1053         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1054
1055         /* step3b */
1056         gen11_dsi_map_pll(encoder, pipe_config);
1057
1058         /* step4: enable DSI port and DPHY */
1059         gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1060
1061         /* step5: program and powerup panel */
1062         gen11_dsi_powerup_panel(encoder);
1063
1064         /* step6c: configure transcoder timings */
1065         gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1066
1067         /* step6d: enable dsi transcoder */
1068         gen11_dsi_enable_transcoder(encoder);
1069
1070         /* step7: enable backlight */
1071         intel_panel_enable_backlight(pipe_config, conn_state);
1072         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1073 }
1074
1075 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1076 {
1077         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1078         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1079         enum port port;
1080         enum transcoder dsi_trans;
1081         u32 tmp;
1082
1083         for_each_dsi_port(port, intel_dsi->ports) {
1084                 dsi_trans = dsi_port_to_transcoder(port);
1085
1086                 /* disable transcoder */
1087                 tmp = I915_READ(PIPECONF(dsi_trans));
1088                 tmp &= ~PIPECONF_ENABLE;
1089                 I915_WRITE(PIPECONF(dsi_trans), tmp);
1090
1091                 /* wait for transcoder to be disabled */
1092                 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1093                                             I965_PIPECONF_ACTIVE, 50))
1094                         DRM_ERROR("DSI trancoder not disabled\n");
1095         }
1096 }
1097
1098 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1099 {
1100         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1101
1102         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1103         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1104         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1105
1106         /* ensure cmds dispatched to panel */
1107         wait_for_cmds_dispatched_to_panel(encoder);
1108 }
1109
1110 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1111 {
1112         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1113         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1114         enum port port;
1115         enum transcoder dsi_trans;
1116         u32 tmp;
1117
1118         /* put dsi link in ULPS */
1119         for_each_dsi_port(port, intel_dsi->ports) {
1120                 dsi_trans = dsi_port_to_transcoder(port);
1121                 tmp = I915_READ(DSI_LP_MSG(dsi_trans));
1122                 tmp |= LINK_ENTER_ULPS;
1123                 tmp &= ~LINK_ULPS_TYPE_LP11;
1124                 I915_WRITE(DSI_LP_MSG(dsi_trans), tmp);
1125
1126                 if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) &
1127                                 LINK_IN_ULPS),
1128                                 10))
1129                         DRM_ERROR("DSI link not in ULPS\n");
1130         }
1131
1132         /* disable ddi function */
1133         for_each_dsi_port(port, intel_dsi->ports) {
1134                 dsi_trans = dsi_port_to_transcoder(port);
1135                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1136                 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1137                 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1138         }
1139
1140         /* disable port sync mode if dual link */
1141         if (intel_dsi->dual_link) {
1142                 for_each_dsi_port(port, intel_dsi->ports) {
1143                         dsi_trans = dsi_port_to_transcoder(port);
1144                         tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
1145                         tmp &= ~PORT_SYNC_MODE_ENABLE;
1146                         I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1147                 }
1148         }
1149 }
1150
1151 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1152 {
1153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1154         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1155         u32 tmp;
1156         enum port port;
1157
1158         gen11_dsi_ungate_clocks(encoder);
1159         for_each_dsi_port(port, intel_dsi->ports) {
1160                 tmp = I915_READ(DDI_BUF_CTL(port));
1161                 tmp &= ~DDI_BUF_CTL_ENABLE;
1162                 I915_WRITE(DDI_BUF_CTL(port), tmp);
1163
1164                 if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) &
1165                                  DDI_BUF_IS_IDLE),
1166                                  8))
1167                         DRM_ERROR("DDI port:%c buffer not idle\n",
1168                                   port_name(port));
1169         }
1170         gen11_dsi_gate_clocks(encoder);
1171 }
1172
1173 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1174 {
1175         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1176         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1177         enum port port;
1178         u32 tmp;
1179
1180         for_each_dsi_port(port, intel_dsi->ports) {
1181                 intel_wakeref_t wakeref;
1182
1183                 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1184                 intel_display_power_put(dev_priv,
1185                                         port == PORT_A ?
1186                                         POWER_DOMAIN_PORT_DDI_A_IO :
1187                                         POWER_DOMAIN_PORT_DDI_B_IO,
1188                                         wakeref);
1189         }
1190
1191         /* set mode to DDI */
1192         for_each_dsi_port(port, intel_dsi->ports) {
1193                 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
1194                 tmp &= ~COMBO_PHY_MODE_DSI;
1195                 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
1196         }
1197 }
1198
1199 static void gen11_dsi_disable(struct intel_encoder *encoder,
1200                               const struct intel_crtc_state *old_crtc_state,
1201                               const struct drm_connector_state *old_conn_state)
1202 {
1203         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1204
1205         /* step1: turn off backlight */
1206         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1207         intel_panel_disable_backlight(old_conn_state);
1208
1209         /* step2d,e: disable transcoder and wait */
1210         gen11_dsi_disable_transcoder(encoder);
1211
1212         /* step2f,g: powerdown panel */
1213         gen11_dsi_powerdown_panel(encoder);
1214
1215         /* step2h,i,j: deconfig trancoder */
1216         gen11_dsi_deconfigure_trancoder(encoder);
1217
1218         /* step3: disable port */
1219         gen11_dsi_disable_port(encoder);
1220
1221         /* step4: disable IO power */
1222         gen11_dsi_disable_io_power(encoder);
1223 }
1224
1225 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1226                                   struct intel_crtc_state *pipe_config)
1227 {
1228         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1229         struct drm_display_mode *adjusted_mode =
1230                                         &pipe_config->hw.adjusted_mode;
1231
1232         if (intel_dsi->dual_link) {
1233                 adjusted_mode->crtc_hdisplay *= 2;
1234                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1235                         adjusted_mode->crtc_hdisplay -=
1236                                                 intel_dsi->pixel_overlap;
1237                 adjusted_mode->crtc_htotal *= 2;
1238         }
1239         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1240         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1241
1242         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1243                 if (intel_dsi->dual_link) {
1244                         adjusted_mode->crtc_hsync_start *= 2;
1245                         adjusted_mode->crtc_hsync_end *= 2;
1246                 }
1247         }
1248         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1249         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1250 }
1251
1252 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1253                                  struct intel_crtc_state *pipe_config)
1254 {
1255         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1256         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1257         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1258
1259         /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
1260         pipe_config->port_clock =
1261                 cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
1262
1263         pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1264         if (intel_dsi->dual_link)
1265                 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1266
1267         gen11_dsi_get_timings(encoder, pipe_config);
1268         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1269         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1270 }
1271
1272 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1273                                     struct intel_crtc_state *pipe_config,
1274                                     struct drm_connector_state *conn_state)
1275 {
1276         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1277                                                    base);
1278         struct intel_connector *intel_connector = intel_dsi->attached_connector;
1279         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1280         const struct drm_display_mode *fixed_mode =
1281                                         intel_connector->panel.fixed_mode;
1282         struct drm_display_mode *adjusted_mode =
1283                                         &pipe_config->hw.adjusted_mode;
1284
1285         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1286         intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1287         intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
1288
1289         adjusted_mode->flags = 0;
1290
1291         /* Dual link goes to trancoder DSI'0' */
1292         if (intel_dsi->ports == BIT(PORT_B))
1293                 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1294         else
1295                 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1296
1297         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1298                 pipe_config->pipe_bpp = 24;
1299         else
1300                 pipe_config->pipe_bpp = 18;
1301
1302         pipe_config->clock_set = true;
1303         pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
1304
1305         return 0;
1306 }
1307
1308 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1309                                         struct intel_crtc_state *crtc_state)
1310 {
1311         get_dsi_io_power_domains(to_i915(encoder->base.dev),
1312                                  enc_to_intel_dsi(&encoder->base));
1313 }
1314
1315 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1316                                    enum pipe *pipe)
1317 {
1318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1319         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1320         enum transcoder dsi_trans;
1321         intel_wakeref_t wakeref;
1322         enum port port;
1323         bool ret = false;
1324         u32 tmp;
1325
1326         wakeref = intel_display_power_get_if_enabled(dev_priv,
1327                                                      encoder->power_domain);
1328         if (!wakeref)
1329                 return false;
1330
1331         for_each_dsi_port(port, intel_dsi->ports) {
1332                 dsi_trans = dsi_port_to_transcoder(port);
1333                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1334                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1335                 case TRANS_DDI_EDP_INPUT_A_ON:
1336                         *pipe = PIPE_A;
1337                         break;
1338                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1339                         *pipe = PIPE_B;
1340                         break;
1341                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1342                         *pipe = PIPE_C;
1343                         break;
1344                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1345                         *pipe = PIPE_D;
1346                         break;
1347                 default:
1348                         DRM_ERROR("Invalid PIPE input\n");
1349                         goto out;
1350                 }
1351
1352                 tmp = I915_READ(PIPECONF(dsi_trans));
1353                 ret = tmp & PIPECONF_ENABLE;
1354         }
1355 out:
1356         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1357         return ret;
1358 }
1359
1360 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1361 {
1362         intel_encoder_destroy(encoder);
1363 }
1364
1365 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1366         .destroy = gen11_dsi_encoder_destroy,
1367 };
1368
1369 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1370         .late_register = intel_connector_register,
1371         .early_unregister = intel_connector_unregister,
1372         .destroy = intel_connector_destroy,
1373         .fill_modes = drm_helper_probe_single_connector_modes,
1374         .atomic_get_property = intel_digital_connector_atomic_get_property,
1375         .atomic_set_property = intel_digital_connector_atomic_set_property,
1376         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1377         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1378 };
1379
1380 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1381         .get_modes = intel_dsi_get_modes,
1382         .mode_valid = intel_dsi_mode_valid,
1383         .atomic_check = intel_digital_connector_atomic_check,
1384 };
1385
1386 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1387                                  struct mipi_dsi_device *dsi)
1388 {
1389         return 0;
1390 }
1391
1392 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1393                                  struct mipi_dsi_device *dsi)
1394 {
1395         return 0;
1396 }
1397
1398 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1399                                        const struct mipi_dsi_msg *msg)
1400 {
1401         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1402         struct mipi_dsi_packet dsi_pkt;
1403         ssize_t ret;
1404         bool enable_lpdt = false;
1405
1406         ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1407         if (ret < 0)
1408                 return ret;
1409
1410         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1411                 enable_lpdt = true;
1412
1413         /* send packet header */
1414         ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1415         if (ret < 0)
1416                 return ret;
1417
1418         /* only long packet contains payload */
1419         if (mipi_dsi_packet_format_is_long(msg->type)) {
1420                 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1421                 if (ret < 0)
1422                         return ret;
1423         }
1424
1425         //TODO: add payload receive code if needed
1426
1427         ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1428
1429         return ret;
1430 }
1431
1432 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1433         .attach = gen11_dsi_host_attach,
1434         .detach = gen11_dsi_host_detach,
1435         .transfer = gen11_dsi_host_transfer,
1436 };
1437
1438 #define ICL_PREPARE_CNT_MAX     0x7
1439 #define ICL_CLK_ZERO_CNT_MAX    0xf
1440 #define ICL_TRAIL_CNT_MAX       0x7
1441 #define ICL_TCLK_PRE_CNT_MAX    0x3
1442 #define ICL_TCLK_POST_CNT_MAX   0x7
1443 #define ICL_HS_ZERO_CNT_MAX     0xf
1444 #define ICL_EXIT_ZERO_CNT_MAX   0x7
1445
1446 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1447 {
1448         struct drm_device *dev = intel_dsi->base.base.dev;
1449         struct drm_i915_private *dev_priv = to_i915(dev);
1450         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1451         u32 tlpx_ns;
1452         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1453         u32 ths_prepare_ns, tclk_trail_ns;
1454         u32 hs_zero_cnt;
1455         u32 tclk_pre_cnt, tclk_post_cnt;
1456
1457         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1458
1459         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1460         ths_prepare_ns = max(mipi_config->ths_prepare,
1461                              mipi_config->tclk_prepare);
1462
1463         /*
1464          * prepare cnt in escape clocks
1465          * this field represents a hexadecimal value with a precision
1466          * of 1.2 – i.e. the most significant bit is the integer
1467          * and the least significant 2 bits are fraction bits.
1468          * so, the field can represent a range of 0.25 to 1.75
1469          */
1470         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1471         if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1472                 DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
1473                 prepare_cnt = ICL_PREPARE_CNT_MAX;
1474         }
1475
1476         /* clk zero count in escape clocks */
1477         clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1478                                     ths_prepare_ns, tlpx_ns);
1479         if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1480                 DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1481                 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1482         }
1483
1484         /* trail cnt in escape clocks*/
1485         trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1486         if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1487                 DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
1488                 trail_cnt = ICL_TRAIL_CNT_MAX;
1489         }
1490
1491         /* tclk pre count in escape clocks */
1492         tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1493         if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1494                 DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1495                 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1496         }
1497
1498         /* tclk post count in escape clocks */
1499         tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1500         if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1501                 DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt);
1502                 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1503         }
1504
1505         /* hs zero cnt in escape clocks */
1506         hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1507                                    ths_prepare_ns, tlpx_ns);
1508         if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1509                 DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
1510                 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1511         }
1512
1513         /* hs exit zero cnt in escape clocks */
1514         exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1515         if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1516                 DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt);
1517                 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1518         }
1519
1520         /* clock lane dphy timings */
1521         intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1522                                CLK_PREPARE(prepare_cnt) |
1523                                CLK_ZERO_OVERRIDE |
1524                                CLK_ZERO(clk_zero_cnt) |
1525                                CLK_PRE_OVERRIDE |
1526                                CLK_PRE(tclk_pre_cnt) |
1527                                CLK_POST_OVERRIDE |
1528                                CLK_POST(tclk_post_cnt) |
1529                                CLK_TRAIL_OVERRIDE |
1530                                CLK_TRAIL(trail_cnt));
1531
1532         /* data lanes dphy timings */
1533         intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1534                                          HS_PREPARE(prepare_cnt) |
1535                                          HS_ZERO_OVERRIDE |
1536                                          HS_ZERO(hs_zero_cnt) |
1537                                          HS_TRAIL_OVERRIDE |
1538                                          HS_TRAIL(trail_cnt) |
1539                                          HS_EXIT_OVERRIDE |
1540                                          HS_EXIT(exit_zero_cnt));
1541
1542         intel_dsi_log_params(intel_dsi);
1543 }
1544
1545 static void icl_dsi_add_properties(struct intel_connector *connector)
1546 {
1547         u32 allowed_scalers;
1548
1549         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
1550                            BIT(DRM_MODE_SCALE_FULLSCREEN) |
1551                            BIT(DRM_MODE_SCALE_CENTER);
1552
1553         drm_connector_attach_scaling_mode_property(&connector->base,
1554                                                    allowed_scalers);
1555
1556         connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1557
1558         connector->base.display_info.panel_orientation =
1559                         intel_dsi_get_panel_orientation(connector);
1560         drm_connector_init_panel_orientation_property(&connector->base,
1561                                 connector->panel.fixed_mode->hdisplay,
1562                                 connector->panel.fixed_mode->vdisplay);
1563 }
1564
1565 void icl_dsi_init(struct drm_i915_private *dev_priv)
1566 {
1567         struct drm_device *dev = &dev_priv->drm;
1568         struct intel_dsi *intel_dsi;
1569         struct intel_encoder *encoder;
1570         struct intel_connector *intel_connector;
1571         struct drm_connector *connector;
1572         struct drm_display_mode *fixed_mode;
1573         enum port port;
1574
1575         if (!intel_bios_is_dsi_present(dev_priv, &port))
1576                 return;
1577
1578         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1579         if (!intel_dsi)
1580                 return;
1581
1582         intel_connector = intel_connector_alloc();
1583         if (!intel_connector) {
1584                 kfree(intel_dsi);
1585                 return;
1586         }
1587
1588         encoder = &intel_dsi->base;
1589         intel_dsi->attached_connector = intel_connector;
1590         connector = &intel_connector->base;
1591
1592         /* register DSI encoder with DRM subsystem */
1593         drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
1594                          DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1595
1596         encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1597         encoder->pre_enable = gen11_dsi_pre_enable;
1598         encoder->disable = gen11_dsi_disable;
1599         encoder->port = port;
1600         encoder->get_config = gen11_dsi_get_config;
1601         encoder->update_pipe = intel_panel_update_backlight;
1602         encoder->compute_config = gen11_dsi_compute_config;
1603         encoder->get_hw_state = gen11_dsi_get_hw_state;
1604         encoder->type = INTEL_OUTPUT_DSI;
1605         encoder->cloneable = 0;
1606         encoder->pipe_mask = ~0;
1607         encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1608         encoder->get_power_domains = gen11_dsi_get_power_domains;
1609
1610         /* register DSI connector with DRM subsystem */
1611         drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
1612                            DRM_MODE_CONNECTOR_DSI);
1613         drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1614         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1615         connector->interlace_allowed = false;
1616         connector->doublescan_allowed = false;
1617         intel_connector->get_hw_state = intel_connector_get_hw_state;
1618
1619         /* attach connector to encoder */
1620         intel_connector_attach_encoder(intel_connector, encoder);
1621
1622         mutex_lock(&dev->mode_config.mutex);
1623         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1624         mutex_unlock(&dev->mode_config.mutex);
1625
1626         if (!fixed_mode) {
1627                 DRM_ERROR("DSI fixed mode info missing\n");
1628                 goto err;
1629         }
1630
1631         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1632         intel_panel_setup_backlight(connector, INVALID_PIPE);
1633
1634         if (dev_priv->vbt.dsi.config->dual_link)
1635                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1636         else
1637                 intel_dsi->ports = BIT(port);
1638
1639         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1640         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1641
1642         for_each_dsi_port(port, intel_dsi->ports) {
1643                 struct intel_dsi_host *host;
1644
1645                 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
1646                 if (!host)
1647                         goto err;
1648
1649                 intel_dsi->dsi_hosts[port] = host;
1650         }
1651
1652         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1653                 DRM_DEBUG_KMS("no device found\n");
1654                 goto err;
1655         }
1656
1657         icl_dphy_param_init(intel_dsi);
1658
1659         icl_dsi_add_properties(intel_connector);
1660         return;
1661
1662 err:
1663         drm_encoder_cleanup(&encoder->base);
1664         kfree(intel_dsi);
1665         kfree(intel_connector);
1666 }