drivers/gpu/drm/i915/display/icl_dsi.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *   Madhav Chauhan <madhav.chauhan@intel.com>
  25  *   Jani Nikula <jani.nikula@intel.com>
  26  */
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_mipi_dsi.h>
  30
  31 #include "intel_atomic.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_dsi.h"
  36 #include "intel_panel.h"
  37 #include "intel_vdsc.h"
  38 #include "skl_scaler.h"
  39 #include "skl_universal_plane.h"
  40
  41 static int header_credits_available(struct drm_i915_private *dev_priv,
  42                                     enum transcoder dsi_trans)
  43 {
  44         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  45                 >> FREE_HEADER_CREDIT_SHIFT;
  46 }
  47
  48 static int payload_credits_available(struct drm_i915_private *dev_priv,
  49                                      enum transcoder dsi_trans)
  50 {
  51         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  52                 >> FREE_PLOAD_CREDIT_SHIFT;
  53 }
  54
  55 static void wait_for_header_credits(struct drm_i915_private *dev_priv,
  56                                     enum transcoder dsi_trans)
  57 {
  58         if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
  59                         MAX_HEADER_CREDIT, 100))
  60                 drm_err(&dev_priv->drm, "DSI header credits not released\n");
  61 }
  62
  63 static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
  64                                      enum transcoder dsi_trans)
  65 {
  66         if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
  67                         MAX_PLOAD_CREDIT, 100))
  68                 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
  69 }
  70
  71 static enum transcoder dsi_port_to_transcoder(enum port port)
  72 {
  73         if (port == PORT_A)
  74                 return TRANSCODER_DSI_0;
  75         else
  76                 return TRANSCODER_DSI_1;
  77 }
  78
  79 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
  80 {
  81         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  82         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
  83         struct mipi_dsi_device *dsi;
  84         enum port port;
  85         enum transcoder dsi_trans;
  86         int ret;
  87
  88         /* wait for header/payload credits to be released */
  89         for_each_dsi_port(port, intel_dsi->ports) {
  90                 dsi_trans = dsi_port_to_transcoder(port);
  91                 wait_for_header_credits(dev_priv, dsi_trans);
  92                 wait_for_payload_credits(dev_priv, dsi_trans);
  93         }
  94
  95         /* send nop DCS command */
  96         for_each_dsi_port(port, intel_dsi->ports) {
  97                 dsi = intel_dsi->dsi_hosts[port]->device;
  98                 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
  99                 dsi->channel = 0;
 100                 ret = mipi_dsi_dcs_nop(dsi);
 101                 if (ret < 0)
 102                         drm_err(&dev_priv->drm,
 103                                 "error sending DCS NOP command\n");
 104         }
 105
 106         /* wait for header credits to be released */
 107         for_each_dsi_port(port, intel_dsi->ports) {
 108                 dsi_trans = dsi_port_to_transcoder(port);
 109                 wait_for_header_credits(dev_priv, dsi_trans);
 110         }
 111
 112         /* wait for LP TX in progress bit to be cleared */
 113         for_each_dsi_port(port, intel_dsi->ports) {
 114                 dsi_trans = dsi_port_to_transcoder(port);
 115                 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
 116                                   LPTX_IN_PROGRESS), 20))
 117                         drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
 118         }
 119 }
 120
 121 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
 122                                u32 len)
 123 {
 124         struct intel_dsi *intel_dsi = host->intel_dsi;
 125         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 126         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 127         int free_credits;
 128         int i, j;
 129
 130         for (i = 0; i < len; i += 4) {
 131                 u32 tmp = 0;
 132
 133                 free_credits = payload_credits_available(dev_priv, dsi_trans);
 134                 if (free_credits < 1) {
 135                         drm_err(&dev_priv->drm,
 136                                 "Payload credit not available\n");
 137                         return false;
 138                 }
 139
 140                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 141                         tmp |= *data++ << 8 * j;
 142
 143                 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp);
 144         }
 145
 146         return true;
 147 }
 148
 149 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 150                             struct mipi_dsi_packet pkt, bool enable_lpdt)
 151 {
 152         struct intel_dsi *intel_dsi = host->intel_dsi;
 153         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 154         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 155         u32 tmp;
 156         int free_credits;
 157
 158         /* check if header credit available */
 159         free_credits = header_credits_available(dev_priv, dsi_trans);
 160         if (free_credits < 1) {
 161                 drm_err(&dev_priv->drm,
 162                         "send pkt header failed, not enough hdr credits\n");
 163                 return -1;
 164         }
 165
 166         tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
 167
 168         if (pkt.payload)
 169                 tmp |= PAYLOAD_PRESENT;
 170         else
 171                 tmp &= ~PAYLOAD_PRESENT;
 172
 173         tmp &= ~VBLANK_FENCE;
 174
 175         if (enable_lpdt)
 176                 tmp |= LP_DATA_TRANSFER;
 177
 178         tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 179         tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
 180         tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
 181         tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
 182         tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
 183         intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
 184
 185         return 0;
 186 }
 187
 188 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 189                               struct mipi_dsi_packet pkt)
 190 {
 191         struct intel_dsi *intel_dsi = host->intel_dsi;
 192         struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 193
 194         /* payload queue can accept *256 bytes*, check limit */
 195         if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
 196                 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
 197                 return -1;
 198         }
 199
 200         /* load data into command payload queue */
 201         if (!add_payld_to_queue(host, pkt.payload,
 202                                 pkt.payload_length)) {
 203                 drm_err(&i915->drm, "adding payload to queue failed\n");
 204                 return -1;
 205         }
 206
 207         return 0;
 208 }
 209
 210 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
 211 {
 212         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 213         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 214         u32 tmp, mode_flags;
 215         enum port port;
 216
 217         mode_flags = crtc_state->mode_flags;
 218
 219         /*
 220          * case 1 also covers dual link
 221          * In case of dual link, frame update should be set on
 222          * DSI_0
 223          */
 224         if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
 225                 port = PORT_A;
 226         else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
 227                 port = PORT_B;
 228         else
 229                 return;
 230
 231         tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
 232         tmp |= DSI_FRAME_UPDATE_REQUEST;
 233         intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
 234 }
 235
 236 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 237 {
 238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 239         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 240         enum phy phy;
 241         u32 tmp;
 242         int lane;
 243
 244         for_each_dsi_phy(phy, intel_dsi->phys) {
 245                 /*
 246                  * Program voltage swing and pre-emphasis level values as per
 247                  * table in BSPEC under DDI buffer programing
 248                  */
 249                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
 250                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 251                 tmp |= SCALING_MODE_SEL(0x2);
 252                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 253                 tmp |= RTERM_SELECT(0x6);
 254                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 255
 256                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
 257                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 258                 tmp |= SCALING_MODE_SEL(0x2);
 259                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 260                 tmp |= RTERM_SELECT(0x6);
 261                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
 262
 263                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
 264                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 265                          RCOMP_SCALAR_MASK);
 266                 tmp |= SWING_SEL_UPPER(0x2);
 267                 tmp |= SWING_SEL_LOWER(0x2);
 268                 tmp |= RCOMP_SCALAR(0x98);
 269                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 270
 271                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
 272                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 273                          RCOMP_SCALAR_MASK);
 274                 tmp |= SWING_SEL_UPPER(0x2);
 275                 tmp |= SWING_SEL_LOWER(0x2);
 276                 tmp |= RCOMP_SCALAR(0x98);
 277                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
 278
 279                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
 280                 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 281                          CURSOR_COEFF_MASK);
 282                 tmp |= POST_CURSOR_1(0x0);
 283                 tmp |= POST_CURSOR_2(0x0);
 284                 tmp |= CURSOR_COEFF(0x3f);
 285                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
 286
 287                 for (lane = 0; lane <= 3; lane++) {
 288                         /* Bspec: must not use GRP register for write */
 289                         tmp = intel_de_read(dev_priv,
 290                                             ICL_PORT_TX_DW4_LN(lane, phy));
 291                         tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 292                                  CURSOR_COEFF_MASK);
 293                         tmp |= POST_CURSOR_1(0x0);
 294                         tmp |= POST_CURSOR_2(0x0);
 295                         tmp |= CURSOR_COEFF(0x3f);
 296                         intel_de_write(dev_priv,
 297                                        ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 298                 }
 299         }
 300 }
 301
 302 static void configure_dual_link_mode(struct intel_encoder *encoder,
 303                                      const struct intel_crtc_state *pipe_config)
 304 {
 305         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 306         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 307         u32 dss_ctl1;
 308
 309         dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
 310         dss_ctl1 |= SPLITTER_ENABLE;
 311         dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 312         dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 313
 314         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 315                 const struct drm_display_mode *adjusted_mode =
 316                                         &pipe_config->hw.adjusted_mode;
 317                 u32 dss_ctl2;
 318                 u16 hactive = adjusted_mode->crtc_hdisplay;
 319                 u16 dl_buffer_depth;
 320
 321                 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 322                 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 323
 324                 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 325                         drm_err(&dev_priv->drm,
 326                                 "DL buffer depth exceed max value\n");
 327
 328                 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 329                 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 330                 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
 331                 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
 332                 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 333                 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2);
 334         } else {
 335                 /* Interleave */
 336                 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 337         }
 338
 339         intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
 340 }
 341
 342 /* aka DSI 8X clock */
 343 static int afe_clk(struct intel_encoder *encoder,
 344                    const struct intel_crtc_state *crtc_state)
 345 {
 346         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 347         int bpp;
 348
 349         if (crtc_state->dsc.compression_enable)
 350                 bpp = crtc_state->dsc.compressed_bpp;
 351         else
 352                 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 353
 354         return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 355 }
 356
 357 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 358                                           const struct intel_crtc_state *crtc_state)
 359 {
 360         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 361         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 362         enum port port;
 363         int afe_clk_khz;
 364         u32 esc_clk_div_m;
 365
 366         afe_clk_khz = afe_clk(encoder, crtc_state);
 367         esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 368
 369         for_each_dsi_port(port, intel_dsi->ports) {
 370                 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
 371                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 372                 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
 373         }
 374
 375         for_each_dsi_port(port, intel_dsi->ports) {
 376                 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
 377                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 378                 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
 379         }
 380 }
 381
 382 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
 383                                      struct intel_dsi *intel_dsi)
 384 {
 385         enum port port;
 386
 387         for_each_dsi_port(port, intel_dsi->ports) {
 388                 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
 389                 intel_dsi->io_wakeref[port] =
 390                         intel_display_power_get(dev_priv,
 391                                                 port == PORT_A ?
 392                                                 POWER_DOMAIN_PORT_DDI_A_IO :
 393                                                 POWER_DOMAIN_PORT_DDI_B_IO);
 394         }
 395 }
 396
 397 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 398 {
 399         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 400         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 401         enum port port;
 402         u32 tmp;
 403
 404         for_each_dsi_port(port, intel_dsi->ports) {
 405                 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
 406                 tmp |= COMBO_PHY_MODE_DSI;
 407                 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
 408         }
 409
 410         get_dsi_io_power_domains(dev_priv, intel_dsi);
 411 }
 412
 413 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 414 {
 415         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 416         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 417         enum phy phy;
 418
 419         for_each_dsi_phy(phy, intel_dsi->phys)
 420                 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 421                                                intel_dsi->lane_count, false);
 422 }
 423
 424 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 425 {
 426         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 427         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 428         enum phy phy;
 429         u32 tmp;
 430         int lane;
 431
 432         /* Step 4b(i) set loadgen select for transmit and aux lanes */
 433         for_each_dsi_phy(phy, intel_dsi->phys) {
 434                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
 435                 tmp &= ~LOADGEN_SELECT;
 436                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
 437                 for (lane = 0; lane <= 3; lane++) {
 438                         tmp = intel_de_read(dev_priv,
 439                                             ICL_PORT_TX_DW4_LN(lane, phy));
 440                         tmp &= ~LOADGEN_SELECT;
 441                         if (lane != 2)
 442                                 tmp |= LOADGEN_SELECT;
 443                         intel_de_write(dev_priv,
 444                                        ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 445                 }
 446         }
 447
 448         /* Step 4b(ii) set latency optimization for transmit and aux lanes */
 449         for_each_dsi_phy(phy, intel_dsi->phys) {
 450                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
 451                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 452                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 453                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
 454                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
 455                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 456                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 457                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 458
 459                 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
 460                 if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
 461                         tmp = intel_de_read(dev_priv,
 462                                             ICL_PORT_PCS_DW1_AUX(phy));
 463                         tmp &= ~LATENCY_OPTIM_MASK;
 464                         tmp |= LATENCY_OPTIM_VAL(0);
 465                         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 466                                        tmp);
 467
 468                         tmp = intel_de_read(dev_priv,
 469                                             ICL_PORT_PCS_DW1_LN0(phy));
 470                         tmp &= ~LATENCY_OPTIM_MASK;
 471                         tmp |= LATENCY_OPTIM_VAL(0x1);
 472                         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
 473                                        tmp);
 474                 }
 475         }
 476
 477 }
 478
 479 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 480 {
 481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 482         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 483         u32 tmp;
 484         enum phy phy;
 485
 486         /* clear common keeper enable bit */
 487         for_each_dsi_phy(phy, intel_dsi->phys) {
 488                 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
 489                 tmp &= ~COMMON_KEEPER_EN;
 490                 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
 491                 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
 492                 tmp &= ~COMMON_KEEPER_EN;
 493                 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp);
 494         }
 495
 496         /*
 497          * Set SUS Clock Config bitfield to 11b
 498          * Note: loadgen select program is done
 499          * as part of lane phy sequence configuration
 500          */
 501         for_each_dsi_phy(phy, intel_dsi->phys) {
 502                 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
 503                 tmp |= SUS_CLOCK_CONFIG;
 504                 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp);
 505         }
 506
 507         /* Clear training enable to change swing values */
 508         for_each_dsi_phy(phy, intel_dsi->phys) {
 509                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
 510                 tmp &= ~TX_TRAINING_EN;
 511                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 512                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
 513                 tmp &= ~TX_TRAINING_EN;
 514                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
 515         }
 516
 517         /* Program swing and de-emphasis */
 518         dsi_program_swing_and_deemphasis(encoder);
 519
 520         /* Set training enable to trigger update */
 521         for_each_dsi_phy(phy, intel_dsi->phys) {
 522                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
 523                 tmp |= TX_TRAINING_EN;
 524                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 525                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
 526                 tmp |= TX_TRAINING_EN;
 527                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
 528         }
 529 }
 530
 531 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 532 {
 533         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 534         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 535         u32 tmp;
 536         enum port port;
 537
 538         for_each_dsi_port(port, intel_dsi->ports) {
 539                 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 540                 tmp |= DDI_BUF_CTL_ENABLE;
 541                 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
 542
 543                 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 544                                   DDI_BUF_IS_IDLE),
 545                                   500))
 546                         drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
 547                                 port_name(port));
 548         }
 549 }
 550
 551 static void
 552 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 553                              const struct intel_crtc_state *crtc_state)
 554 {
 555         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 556         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 557         u32 tmp;
 558         enum port port;
 559         enum phy phy;
 560
 561         /* Program T-INIT master registers */
 562         for_each_dsi_port(port, intel_dsi->ports) {
 563                 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port));
 564                 tmp &= ~MASTER_INIT_TIMER_MASK;
 565                 tmp |= intel_dsi->init_count;
 566                 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp);
 567         }
 568
 569         /* Program DPHY clock lanes timings */
 570         for_each_dsi_port(port, intel_dsi->ports) {
 571                 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
 572                                intel_dsi->dphy_reg);
 573
 574                 /* shadow register inside display core */
 575                 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
 576                                intel_dsi->dphy_reg);
 577         }
 578
 579         /* Program DPHY data lanes timings */
 580         for_each_dsi_port(port, intel_dsi->ports) {
 581                 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
 582                                intel_dsi->dphy_data_lane_reg);
 583
 584                 /* shadow register inside display core */
 585                 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
 586                                intel_dsi->dphy_data_lane_reg);
 587         }
 588
 589         /*
 590          * If DSI link operating at or below an 800 MHz,
 591          * TA_SURE should be override and programmed to
 592          * a value '0' inside TA_PARAM_REGISTERS otherwise
 593          * leave all fields at HW default values.
 594          */
 595         if (IS_GEN(dev_priv, 11)) {
 596                 if (afe_clk(encoder, crtc_state) <= 800000) {
 597                         for_each_dsi_port(port, intel_dsi->ports) {
 598                                 tmp = intel_de_read(dev_priv,
 599                                                     DPHY_TA_TIMING_PARAM(port));
 600                                 tmp &= ~TA_SURE_MASK;
 601                                 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 602                                 intel_de_write(dev_priv,
 603                                                DPHY_TA_TIMING_PARAM(port),
 604                                                tmp);
 605
 606                                 /* shadow register inside display core */
 607                                 tmp = intel_de_read(dev_priv,
 608                                                     DSI_TA_TIMING_PARAM(port));
 609                                 tmp &= ~TA_SURE_MASK;
 610                                 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 611                                 intel_de_write(dev_priv,
 612                                                DSI_TA_TIMING_PARAM(port), tmp);
 613                         }
 614                 }
 615         }
 616
 617         if (IS_JSL_EHL(dev_priv)) {
 618                 for_each_dsi_phy(phy, intel_dsi->phys) {
 619                         tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
 620                         tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
 621                         intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp);
 622                 }
 623         }
 624 }
 625
 626 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 627 {
 628         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 629         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 630         u32 tmp;
 631         enum phy phy;
 632
 633         mutex_lock(&dev_priv->dpll.lock);
 634         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 635         for_each_dsi_phy(phy, intel_dsi->phys)
 636                 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 637
 638         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 639         mutex_unlock(&dev_priv->dpll.lock);
 640 }
 641
 642 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 643 {
 644         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 645         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 646         u32 tmp;
 647         enum phy phy;
 648
 649         mutex_lock(&dev_priv->dpll.lock);
 650         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 651         for_each_dsi_phy(phy, intel_dsi->phys)
 652                 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 653
 654         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 655         mutex_unlock(&dev_priv->dpll.lock);
 656 }
 657
 658 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 659                               const struct intel_crtc_state *crtc_state)
 660 {
 661         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 662         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 663         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 664         enum phy phy;
 665         u32 val;
 666
 667         mutex_lock(&dev_priv->dpll.lock);
 668
 669         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 670         for_each_dsi_phy(phy, intel_dsi->phys) {
 671                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 672                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 673         }
 674         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 675
 676         for_each_dsi_phy(phy, intel_dsi->phys) {
 677                 if (INTEL_GEN(dev_priv) >= 12)
 678                         val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 679                 else
 680                         val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 681         }
 682         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 683
 684         intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
 685
 686         mutex_unlock(&dev_priv->dpll.lock);
 687 }
 688
 689 static void
 690 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 691                                const struct intel_crtc_state *pipe_config)
 692 {
 693         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 694         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 695         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 696         enum pipe pipe = intel_crtc->pipe;
 697         u32 tmp;
 698         enum port port;
 699         enum transcoder dsi_trans;
 700
 701         for_each_dsi_port(port, intel_dsi->ports) {
 702                 dsi_trans = dsi_port_to_transcoder(port);
 703                 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
 704
 705                 if (intel_dsi->eotp_pkt)
 706                         tmp &= ~EOTP_DISABLED;
 707                 else
 708                         tmp |= EOTP_DISABLED;
 709
 710                 /* enable link calibration if freq > 1.5Gbps */
 711                 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
 712                         tmp &= ~LINK_CALIBRATION_MASK;
 713                         tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 714                 }
 715
 716                 /* configure continuous clock */
 717                 tmp &= ~CONTINUOUS_CLK_MASK;
 718                 if (intel_dsi->clock_stop)
 719                         tmp |= CLK_ENTER_LP_AFTER_DATA;
 720                 else
 721                         tmp |= CLK_HS_CONTINUOUS;
 722
 723                 /* configure buffer threshold limit to minimum */
 724                 tmp &= ~PIX_BUF_THRESHOLD_MASK;
 725                 tmp |= PIX_BUF_THRESHOLD_1_4;
 726
 727                 /* set virtual channel to '0' */
 728                 tmp &= ~PIX_VIRT_CHAN_MASK;
 729                 tmp |= PIX_VIRT_CHAN(0);
 730
 731                 /* program BGR transmission */
 732                 if (intel_dsi->bgr_enabled)
 733                         tmp |= BGR_TRANSMISSION;
 734
 735                 /* select pixel format */
 736                 tmp &= ~PIX_FMT_MASK;
 737                 if (pipe_config->dsc.compression_enable) {
 738                         tmp |= PIX_FMT_COMPRESSED;
 739                 } else {
 740                         switch (intel_dsi->pixel_format) {
 741                         default:
 742                                 MISSING_CASE(intel_dsi->pixel_format);
 743                                 fallthrough;
 744                         case MIPI_DSI_FMT_RGB565:
 745                                 tmp |= PIX_FMT_RGB565;
 746                                 break;
 747                         case MIPI_DSI_FMT_RGB666_PACKED:
 748                                 tmp |= PIX_FMT_RGB666_PACKED;
 749                                 break;
 750                         case MIPI_DSI_FMT_RGB666:
 751                                 tmp |= PIX_FMT_RGB666_LOOSE;
 752                                 break;
 753                         case MIPI_DSI_FMT_RGB888:
 754                                 tmp |= PIX_FMT_RGB888;
 755                                 break;
 756                         }
 757                 }
 758
 759                 if (INTEL_GEN(dev_priv) >= 12) {
 760                         if (is_vid_mode(intel_dsi))
 761                                 tmp |= BLANKING_PACKET_ENABLE;
 762                 }
 763
 764                 /* program DSI operation mode */
 765                 if (is_vid_mode(intel_dsi)) {
 766                         tmp &= ~OP_MODE_MASK;
 767                         switch (intel_dsi->video_mode_format) {
 768                         default:
 769                                 MISSING_CASE(intel_dsi->video_mode_format);
 770                                 fallthrough;
 771                         case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
 772                                 tmp |= VIDEO_MODE_SYNC_EVENT;
 773                                 break;
 774                         case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
 775                                 tmp |= VIDEO_MODE_SYNC_PULSE;
 776                                 break;
 777                         }
 778                 } else {
 779                         /*
 780                          * FIXME: Retrieve this info from VBT.
 781                          * As per the spec when dsi transcoder is operating
 782                          * in TE GATE mode, TE comes from GPIO
 783                          * which is UTIL PIN for DSI 0.
 784                          * Also this GPIO would not be used for other
 785                          * purposes is an assumption.
 786                          */
 787                         tmp &= ~OP_MODE_MASK;
 788                         tmp |= CMD_MODE_TE_GATE;
 789                         tmp |= TE_SOURCE_GPIO;
 790                 }
 791
 792                 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 793         }
 794
 795         /* enable port sync mode if dual link */
 796         if (intel_dsi->dual_link) {
 797                 for_each_dsi_port(port, intel_dsi->ports) {
 798                         dsi_trans = dsi_port_to_transcoder(port);
 799                         tmp = intel_de_read(dev_priv,
 800                                             TRANS_DDI_FUNC_CTL2(dsi_trans));
 801                         tmp |= PORT_SYNC_MODE_ENABLE;
 802                         intel_de_write(dev_priv,
 803                                        TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
 804                 }
 805
 806                 /* configure stream splitting */
 807                 configure_dual_link_mode(encoder, pipe_config);
 808         }
 809
 810         for_each_dsi_port(port, intel_dsi->ports) {
 811                 dsi_trans = dsi_port_to_transcoder(port);
 812
 813                 /* select data lane width */
 814                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
 815                 tmp &= ~DDI_PORT_WIDTH_MASK;
 816                 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 817
 818                 /* select input pipe */
 819                 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 820                 switch (pipe) {
 821                 default:
 822                         MISSING_CASE(pipe);
 823                         fallthrough;
 824                 case PIPE_A:
 825                         tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 826                         break;
 827                 case PIPE_B:
 828                         tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 829                         break;
 830                 case PIPE_C:
 831                         tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 832                         break;
 833                 case PIPE_D:
 834                         tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
 835                         break;
 836                 }
 837
 838                 /* enable DDI buffer */
 839                 tmp |= TRANS_DDI_FUNC_ENABLE;
 840                 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
 841         }
 842
 843         /* wait for link ready */
 844         for_each_dsi_port(port, intel_dsi->ports) {
 845                 dsi_trans = dsi_port_to_transcoder(port);
 846                 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
 847                                  LINK_READY), 2500))
 848                         drm_err(&dev_priv->drm, "DSI link not ready\n");
 849         }
 850 }
 851
 852 static void
 853 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 854                                  const struct intel_crtc_state *crtc_state)
 855 {
 856         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 857         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 858         const struct drm_display_mode *adjusted_mode =
 859                 &crtc_state->hw.adjusted_mode;
 860         enum port port;
 861         enum transcoder dsi_trans;
 862         /* horizontal timings */
 863         u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 864         u16 hback_porch;
 865         /* vertical timings */
 866         u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 867         int mul = 1, div = 1;
 868
 869         /*
 870          * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
 871          * for slower link speed if DSC is enabled.
 872          *
 873          * The compression frequency ratio is the ratio between compressed and
 874          * non-compressed link speeds, and simplifies down to the ratio between
 875          * compressed and non-compressed bpp.
 876          */
 877         if (crtc_state->dsc.compression_enable) {
 878                 mul = crtc_state->dsc.compressed_bpp;
 879                 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 880         }
 881
 882         hactive = adjusted_mode->crtc_hdisplay;
 883
 884         if (is_vid_mode(intel_dsi))
 885                 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
 886         else
 887                 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
 888
 889         hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
 890         hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
 891         hsync_size  = hsync_end - hsync_start;
 892         hback_porch = (adjusted_mode->crtc_htotal -
 893                        adjusted_mode->crtc_hsync_end);
 894         vactive = adjusted_mode->crtc_vdisplay;
 895
 896         if (is_vid_mode(intel_dsi)) {
 897                 vtotal = adjusted_mode->crtc_vtotal;
 898         } else {
 899                 int bpp, line_time_us, byte_clk_period_ns;
 900
 901                 if (crtc_state->dsc.compression_enable)
 902                         bpp = crtc_state->dsc.compressed_bpp;
 903                 else
 904                         bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 905
 906                 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
 907                 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
 908                 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
 909         }
 910         vsync_start = adjusted_mode->crtc_vsync_start;
 911         vsync_end = adjusted_mode->crtc_vsync_end;
 912         vsync_shift = hsync_start - htotal / 2;
 913
 914         if (intel_dsi->dual_link) {
 915                 hactive /= 2;
 916                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 917                         hactive += intel_dsi->pixel_overlap;
 918                 htotal /= 2;
 919         }
 920
 921         /* minimum hactive as per bspec: 256 pixels */
 922         if (adjusted_mode->crtc_hdisplay < 256)
 923                 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
 924
 925         /* if RGB666 format, then hactive must be multiple of 4 pixels */
 926         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 927                 drm_err(&dev_priv->drm,
 928                         "hactive pixels are not multiple of 4\n");
 929
 930         /* program TRANS_HTOTAL register */
 931         for_each_dsi_port(port, intel_dsi->ports) {
 932                 dsi_trans = dsi_port_to_transcoder(port);
 933                 intel_de_write(dev_priv, HTOTAL(dsi_trans),
 934                                (hactive - 1) | ((htotal - 1) << 16));
 935         }
 936
 937         /* TRANS_HSYNC register to be programmed only for video mode */
 938         if (is_vid_mode(intel_dsi)) {
 939                 if (intel_dsi->video_mode_format ==
 940                     VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 941                         /* BSPEC: hsync size should be atleast 16 pixels */
 942                         if (hsync_size < 16)
 943                                 drm_err(&dev_priv->drm,
 944                                         "hsync size < 16 pixels\n");
 945                 }
 946
 947                 if (hback_porch < 16)
 948                         drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
 949
 950                 if (intel_dsi->dual_link) {
 951                         hsync_start /= 2;
 952                         hsync_end /= 2;
 953                 }
 954
 955                 for_each_dsi_port(port, intel_dsi->ports) {
 956                         dsi_trans = dsi_port_to_transcoder(port);
 957                         intel_de_write(dev_priv, HSYNC(dsi_trans),
 958                                        (hsync_start - 1) | ((hsync_end - 1) << 16));
 959                 }
 960         }
 961
 962         /* program TRANS_VTOTAL register */
 963         for_each_dsi_port(port, intel_dsi->ports) {
 964                 dsi_trans = dsi_port_to_transcoder(port);
 965                 /*
 966                  * FIXME: Programing this by assuming progressive mode, since
 967                  * non-interlaced info from VBT is not saved inside
 968                  * struct drm_display_mode.
 969                  * For interlace mode: program required pixel minus 2
 970                  */
 971                 intel_de_write(dev_priv, VTOTAL(dsi_trans),
 972                                (vactive - 1) | ((vtotal - 1) << 16));
 973         }
 974
 975         if (vsync_end < vsync_start || vsync_end > vtotal)
 976                 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
 977
 978         if (vsync_start < vactive)
 979                 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
 980
 981         /* program TRANS_VSYNC register for video mode only */
 982         if (is_vid_mode(intel_dsi)) {
 983                 for_each_dsi_port(port, intel_dsi->ports) {
 984                         dsi_trans = dsi_port_to_transcoder(port);
 985                         intel_de_write(dev_priv, VSYNC(dsi_trans),
 986                                        (vsync_start - 1) | ((vsync_end - 1) << 16));
 987                 }
 988         }
 989
 990         /*
 991          * FIXME: It has to be programmed only for video modes and interlaced
 992          * modes. Put the check condition here once interlaced
 993          * info available as described above.
 994          * program TRANS_VSYNCSHIFT register
 995          */
 996         if (is_vid_mode(intel_dsi)) {
 997                 for_each_dsi_port(port, intel_dsi->ports) {
 998                         dsi_trans = dsi_port_to_transcoder(port);
 999                         intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans),
1000                                        vsync_shift);
1001                 }
1002         }
1003
1004         /* program TRANS_VBLANK register, should be same as vtotal programmed */
1005         if (INTEL_GEN(dev_priv) >= 12) {
1006                 for_each_dsi_port(port, intel_dsi->ports) {
1007                         dsi_trans = dsi_port_to_transcoder(port);
1008                         intel_de_write(dev_priv, VBLANK(dsi_trans),
1009                                        (vactive - 1) | ((vtotal - 1) << 16));
1010                 }
1011         }
1012 }
1013
1014 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1015 {
1016         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1017         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1018         enum port port;
1019         enum transcoder dsi_trans;
1020         u32 tmp;
1021
1022         for_each_dsi_port(port, intel_dsi->ports) {
1023                 dsi_trans = dsi_port_to_transcoder(port);
1024                 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1025                 tmp |= PIPECONF_ENABLE;
1026                 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1027
1028                 /* wait for transcoder to be enabled */
1029                 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
1030                                           I965_PIPECONF_ACTIVE, 10))
1031                         drm_err(&dev_priv->drm,
1032                                 "DSI transcoder not enabled\n");
1033         }
1034 }
1035
1036 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1037                                      const struct intel_crtc_state *crtc_state)
1038 {
1039         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1040         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1041         enum port port;
1042         enum transcoder dsi_trans;
1043         u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1044
1045         /*
1046          * escape clock count calculation:
1047          * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1048          * UI (nsec) = (10^6)/Bitrate
1049          * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1050          * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
1051          */
1052         divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1053         mul = 8 * 1000000;
1054         hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1055                                      divisor);
1056         lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1057         ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1058
1059         for_each_dsi_port(port, intel_dsi->ports) {
1060                 dsi_trans = dsi_port_to_transcoder(port);
1061
1062                 /* program hst_tx_timeout */
1063                 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans));
1064                 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
1065                 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
1066                 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp);
1067
1068                 /* FIXME: DSI_CALIB_TO */
1069
1070                 /* program lp_rx_host timeout */
1071                 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans));
1072                 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
1073                 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
1074                 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp);
1075
1076                 /* FIXME: DSI_PWAIT_TO */
1077
1078                 /* program turn around timeout */
1079                 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans));
1080                 tmp &= ~TA_TIMEOUT_VALUE_MASK;
1081                 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
1082                 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp);
1083         }
1084 }
1085
1086 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1087                                       bool enable)
1088 {
1089         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1090         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1091         u32 tmp;
1092
1093         /*
1094          * used as TE i/p for DSI0,
1095          * for dual link/DSI1 TE is from slave DSI1
1096          * through GPIO.
1097          */
1098         if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1099                 return;
1100
1101         tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1102
1103         if (enable) {
1104                 tmp |= UTIL_PIN_DIRECTION_INPUT;
1105                 tmp |= UTIL_PIN_ENABLE;
1106         } else {
1107                 tmp &= ~UTIL_PIN_ENABLE;
1108         }
1109         intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1110 }
1111
1112 static void
1113 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1114                               const struct intel_crtc_state *crtc_state)
1115 {
1116         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1117
1118         /* step 4a: power up all lanes of the DDI used by DSI */
1119         gen11_dsi_power_up_lanes(encoder);
1120
1121         /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1122         gen11_dsi_config_phy_lanes_sequence(encoder);
1123
1124         /* step 4c: configure voltage swing and skew */
1125         gen11_dsi_voltage_swing_program_seq(encoder);
1126
1127         /* enable DDI buffer */
1128         gen11_dsi_enable_ddi_buffer(encoder);
1129
1130         /* setup D-PHY timings */
1131         gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1132
1133         /* Since transcoder is configured to take events from GPIO */
1134         gen11_dsi_config_util_pin(encoder, true);
1135
1136         /* step 4h: setup DSI protocol timeouts */
1137         gen11_dsi_setup_timeouts(encoder, crtc_state);
1138
1139         /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1140         gen11_dsi_configure_transcoder(encoder, crtc_state);
1141
1142         /* Step 4l: Gate DDI clocks */
1143         if (IS_GEN(dev_priv, 11))
1144                 gen11_dsi_gate_clocks(encoder);
1145 }
1146
1147 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1148 {
1149         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1150         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1151         struct mipi_dsi_device *dsi;
1152         enum port port;
1153         enum transcoder dsi_trans;
1154         u32 tmp;
1155         int ret;
1156
1157         /* set maximum return packet size */
1158         for_each_dsi_port(port, intel_dsi->ports) {
1159                 dsi_trans = dsi_port_to_transcoder(port);
1160
1161                 /*
1162                  * FIXME: This uses the number of DW's currently in the payload
1163                  * receive queue. This is probably not what we want here.
1164                  */
1165                 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1166                 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1167                 /* multiply "Number Rx Payload DW" by 4 to get max value */
1168                 tmp = tmp * 4;
1169                 dsi = intel_dsi->dsi_hosts[port]->device;
1170                 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1171                 if (ret < 0)
1172                         drm_err(&dev_priv->drm,
1173                                 "error setting max return pkt size%d\n", tmp);
1174         }
1175
1176         /* panel power on related mipi dsi vbt sequences */
1177         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1178         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
1179         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1180         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1181         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1182
1183         /* ensure all panel commands dispatched before enabling transcoder */
1184         wait_for_cmds_dispatched_to_panel(encoder);
1185 }
1186
1187 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1188                                      struct intel_encoder *encoder,
1189                                      const struct intel_crtc_state *crtc_state,
1190                                      const struct drm_connector_state *conn_state)
1191 {
1192         /* step2: enable IO power */
1193         gen11_dsi_enable_io_power(encoder);
1194
1195         /* step3: enable DSI PLL */
1196         gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1197 }
1198
1199 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1200                                  struct intel_encoder *encoder,
1201                                  const struct intel_crtc_state *pipe_config,
1202                                  const struct drm_connector_state *conn_state)
1203 {
1204         /* step3b */
1205         gen11_dsi_map_pll(encoder, pipe_config);
1206
1207         /* step4: enable DSI port and DPHY */
1208         gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1209
1210         /* step5: program and powerup panel */
1211         gen11_dsi_powerup_panel(encoder);
1212
1213         intel_dsc_enable(encoder, pipe_config);
1214
1215         /* step6c: configure transcoder timings */
1216         gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1217 }
1218
1219 static void gen11_dsi_enable(struct intel_atomic_state *state,
1220                              struct intel_encoder *encoder,
1221                              const struct intel_crtc_state *crtc_state,
1222                              const struct drm_connector_state *conn_state)
1223 {
1224         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1225
1226         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
1227
1228         /* step6d: enable dsi transcoder */
1229         gen11_dsi_enable_transcoder(encoder);
1230
1231         /* step7: enable backlight */
1232         intel_panel_enable_backlight(crtc_state, conn_state);
1233         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1234
1235         intel_crtc_vblank_on(crtc_state);
1236 }
1237
1238 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1239 {
1240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1241         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1242         enum port port;
1243         enum transcoder dsi_trans;
1244         u32 tmp;
1245
1246         for_each_dsi_port(port, intel_dsi->ports) {
1247                 dsi_trans = dsi_port_to_transcoder(port);
1248
1249                 /* disable transcoder */
1250                 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1251                 tmp &= ~PIPECONF_ENABLE;
1252                 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1253
1254                 /* wait for transcoder to be disabled */
1255                 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1256                                             I965_PIPECONF_ACTIVE, 50))
1257                         drm_err(&dev_priv->drm,
1258                                 "DSI trancoder not disabled\n");
1259         }
1260 }
1261
1262 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1263 {
1264         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1265
1266         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1267         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1268         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1269
1270         /* ensure cmds dispatched to panel */
1271         wait_for_cmds_dispatched_to_panel(encoder);
1272 }
1273
1274 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1275 {
1276         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1277         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1278         enum port port;
1279         enum transcoder dsi_trans;
1280         u32 tmp;
1281
1282         /* disable periodic update mode */
1283         if (is_cmd_mode(intel_dsi)) {
1284                 for_each_dsi_port(port, intel_dsi->ports) {
1285                         tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
1286                         tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
1287                         intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
1288                 }
1289         }
1290
1291         /* put dsi link in ULPS */
1292         for_each_dsi_port(port, intel_dsi->ports) {
1293                 dsi_trans = dsi_port_to_transcoder(port);
1294                 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1295                 tmp |= LINK_ENTER_ULPS;
1296                 tmp &= ~LINK_ULPS_TYPE_LP11;
1297                 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1298
1299                 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1300                                  LINK_IN_ULPS),
1301                                 10))
1302                         drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1303         }
1304
1305         /* disable ddi function */
1306         for_each_dsi_port(port, intel_dsi->ports) {
1307                 dsi_trans = dsi_port_to_transcoder(port);
1308                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1309                 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1310                 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1311         }
1312
1313         /* disable port sync mode if dual link */
1314         if (intel_dsi->dual_link) {
1315                 for_each_dsi_port(port, intel_dsi->ports) {
1316                         dsi_trans = dsi_port_to_transcoder(port);
1317                         tmp = intel_de_read(dev_priv,
1318                                             TRANS_DDI_FUNC_CTL2(dsi_trans));
1319                         tmp &= ~PORT_SYNC_MODE_ENABLE;
1320                         intel_de_write(dev_priv,
1321                                        TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1322                 }
1323         }
1324 }
1325
1326 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1327 {
1328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1329         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1330         u32 tmp;
1331         enum port port;
1332
1333         gen11_dsi_ungate_clocks(encoder);
1334         for_each_dsi_port(port, intel_dsi->ports) {
1335                 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1336                 tmp &= ~DDI_BUF_CTL_ENABLE;
1337                 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
1338
1339                 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1340                                  DDI_BUF_IS_IDLE),
1341                                  8))
1342                         drm_err(&dev_priv->drm,
1343                                 "DDI port:%c buffer not idle\n",
1344                                 port_name(port));
1345         }
1346         gen11_dsi_gate_clocks(encoder);
1347 }
1348
1349 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1350 {
1351         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1352         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1353         enum port port;
1354         u32 tmp;
1355
1356         for_each_dsi_port(port, intel_dsi->ports) {
1357                 intel_wakeref_t wakeref;
1358
1359                 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1360                 intel_display_power_put(dev_priv,
1361                                         port == PORT_A ?
1362                                         POWER_DOMAIN_PORT_DDI_A_IO :
1363                                         POWER_DOMAIN_PORT_DDI_B_IO,
1364                                         wakeref);
1365         }
1366
1367         /* set mode to DDI */
1368         for_each_dsi_port(port, intel_dsi->ports) {
1369                 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
1370                 tmp &= ~COMBO_PHY_MODE_DSI;
1371                 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
1372         }
1373 }
1374
1375 static void gen11_dsi_disable(struct intel_atomic_state *state,
1376                               struct intel_encoder *encoder,
1377                               const struct intel_crtc_state *old_crtc_state,
1378                               const struct drm_connector_state *old_conn_state)
1379 {
1380         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1381
1382         /* step1: turn off backlight */
1383         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1384         intel_panel_disable_backlight(old_conn_state);
1385
1386         /* step2d,e: disable transcoder and wait */
1387         gen11_dsi_disable_transcoder(encoder);
1388
1389         /* step2f,g: powerdown panel */
1390         gen11_dsi_powerdown_panel(encoder);
1391
1392         /* step2h,i,j: deconfig trancoder */
1393         gen11_dsi_deconfigure_trancoder(encoder);
1394
1395         /* step3: disable port */
1396         gen11_dsi_disable_port(encoder);
1397
1398         gen11_dsi_config_util_pin(encoder, false);
1399
1400         /* step4: disable IO power */
1401         gen11_dsi_disable_io_power(encoder);
1402 }
1403
1404 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1405                                    struct intel_encoder *encoder,
1406                                    const struct intel_crtc_state *old_crtc_state,
1407                                    const struct drm_connector_state *old_conn_state)
1408 {
1409         intel_crtc_vblank_off(old_crtc_state);
1410
1411         intel_dsc_disable(old_crtc_state);
1412
1413         skl_scaler_disable(old_crtc_state);
1414 }
1415
1416 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1417                                                  struct drm_display_mode *mode)
1418 {
1419         /* FIXME: DSC? */
1420         return intel_dsi_mode_valid(connector, mode);
1421 }
1422
1423 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1424                                   struct intel_crtc_state *pipe_config)
1425 {
1426         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1427         struct drm_display_mode *adjusted_mode =
1428                                         &pipe_config->hw.adjusted_mode;
1429
1430         if (pipe_config->dsc.compressed_bpp) {
1431                 int div = pipe_config->dsc.compressed_bpp;
1432                 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1433
1434                 adjusted_mode->crtc_htotal =
1435                         DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1436                 adjusted_mode->crtc_hsync_start =
1437                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1438                 adjusted_mode->crtc_hsync_end =
1439                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1440         }
1441
1442         if (intel_dsi->dual_link) {
1443                 adjusted_mode->crtc_hdisplay *= 2;
1444                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1445                         adjusted_mode->crtc_hdisplay -=
1446                                                 intel_dsi->pixel_overlap;
1447                 adjusted_mode->crtc_htotal *= 2;
1448         }
1449         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1450         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1451
1452         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1453                 if (intel_dsi->dual_link) {
1454                         adjusted_mode->crtc_hsync_start *= 2;
1455                         adjusted_mode->crtc_hsync_end *= 2;
1456                 }
1457         }
1458         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1459         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1460 }
1461
1462 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1463 {
1464         struct drm_device *dev = intel_dsi->base.base.dev;
1465         struct drm_i915_private *dev_priv = to_i915(dev);
1466         enum transcoder dsi_trans;
1467         u32 val;
1468
1469         if (intel_dsi->ports == BIT(PORT_B))
1470                 dsi_trans = TRANSCODER_DSI_1;
1471         else
1472                 dsi_trans = TRANSCODER_DSI_0;
1473
1474         val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1475         return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1476 }
1477
1478 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1479                                           struct intel_crtc_state *pipe_config)
1480 {
1481         if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1482                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1483                                             I915_MODE_FLAG_DSI_USE_TE0;
1484         else if (intel_dsi->ports == BIT(PORT_B))
1485                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1486         else
1487                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1488 }
1489
1490 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1491                                  struct intel_crtc_state *pipe_config)
1492 {
1493         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1494         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1495         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1496
1497         /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
1498         pipe_config->port_clock = intel_dpll_get_freq(i915,
1499                                                       pipe_config->shared_dpll,
1500                                                       &pipe_config->dpll_hw_state);
1501
1502         pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1503         if (intel_dsi->dual_link)
1504                 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1505
1506         gen11_dsi_get_timings(encoder, pipe_config);
1507         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1508         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1509
1510         /* Get the details on which TE should be enabled */
1511         if (is_cmd_mode(intel_dsi))
1512                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1513
1514         if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1515                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1516 }
1517
1518 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1519                                         struct intel_crtc_state *crtc_state)
1520 {
1521         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1522         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1523         int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
1524         bool use_dsc;
1525         int ret;
1526
1527         use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1528         if (!use_dsc)
1529                 return 0;
1530
1531         if (crtc_state->pipe_bpp < 8 * 3)
1532                 return -EINVAL;
1533
1534         /* FIXME: split only when necessary */
1535         if (crtc_state->dsc.slice_count > 1)
1536                 crtc_state->dsc.dsc_split = true;
1537
1538         vdsc_cfg->convert_rgb = true;
1539
1540         /* FIXME: initialize from VBT */
1541         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1542
1543         ret = intel_dsc_compute_params(encoder, crtc_state);
1544         if (ret)
1545                 return ret;
1546
1547         /* DSI specific sanity checks on the common code */
1548         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1549         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1550         drm_WARN_ON(&dev_priv->drm,
1551                     vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1552         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1553         drm_WARN_ON(&dev_priv->drm,
1554                     vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1555
1556         ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1557         if (ret)
1558                 return ret;
1559
1560         crtc_state->dsc.compression_enable = true;
1561
1562         return 0;
1563 }
1564
1565 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1566                                     struct intel_crtc_state *pipe_config,
1567                                     struct drm_connector_state *conn_state)
1568 {
1569         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1570         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1571                                                    base);
1572         struct intel_connector *intel_connector = intel_dsi->attached_connector;
1573         const struct drm_display_mode *fixed_mode =
1574                 intel_connector->panel.fixed_mode;
1575         struct drm_display_mode *adjusted_mode =
1576                 &pipe_config->hw.adjusted_mode;
1577         int ret;
1578
1579         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1580         intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1581
1582         ret = intel_pch_panel_fitting(pipe_config, conn_state);
1583         if (ret)
1584                 return ret;
1585
1586         adjusted_mode->flags = 0;
1587
1588         /* Dual link goes to trancoder DSI'0' */
1589         if (intel_dsi->ports == BIT(PORT_B))
1590                 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1591         else
1592                 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1593
1594         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1595                 pipe_config->pipe_bpp = 24;
1596         else
1597                 pipe_config->pipe_bpp = 18;
1598
1599         pipe_config->clock_set = true;
1600
1601         if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1602                 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1603
1604         pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1605
1606         /*
1607          * In case of TE GATE cmd mode, we
1608          * receive TE from the slave if
1609          * dual link is enabled
1610          */
1611         if (is_cmd_mode(intel_dsi))
1612                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1613
1614         return 0;
1615 }
1616
1617 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1618                                         struct intel_crtc_state *crtc_state)
1619 {
1620         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1621
1622         get_dsi_io_power_domains(i915,
1623                                  enc_to_intel_dsi(encoder));
1624 }
1625
1626 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1627                                    enum pipe *pipe)
1628 {
1629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1630         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1631         enum transcoder dsi_trans;
1632         intel_wakeref_t wakeref;
1633         enum port port;
1634         bool ret = false;
1635         u32 tmp;
1636
1637         wakeref = intel_display_power_get_if_enabled(dev_priv,
1638                                                      encoder->power_domain);
1639         if (!wakeref)
1640                 return false;
1641
1642         for_each_dsi_port(port, intel_dsi->ports) {
1643                 dsi_trans = dsi_port_to_transcoder(port);
1644                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1645                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1646                 case TRANS_DDI_EDP_INPUT_A_ON:
1647                         *pipe = PIPE_A;
1648                         break;
1649                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1650                         *pipe = PIPE_B;
1651                         break;
1652                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1653                         *pipe = PIPE_C;
1654                         break;
1655                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1656                         *pipe = PIPE_D;
1657                         break;
1658                 default:
1659                         drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1660                         goto out;
1661                 }
1662
1663                 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1664                 ret = tmp & PIPECONF_ENABLE;
1665         }
1666 out:
1667         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1668         return ret;
1669 }
1670
1671 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1672                                             struct intel_crtc_state *crtc_state)
1673 {
1674         if (crtc_state->dsc.compression_enable) {
1675                 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1676                 crtc_state->uapi.mode_changed = true;
1677
1678                 return false;
1679         }
1680
1681         return true;
1682 }
1683
1684 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1685 {
1686         intel_encoder_destroy(encoder);
1687 }
1688
1689 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1690         .destroy = gen11_dsi_encoder_destroy,
1691 };
1692
1693 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1694         .detect = intel_panel_detect,
1695         .late_register = intel_connector_register,
1696         .early_unregister = intel_connector_unregister,
1697         .destroy = intel_connector_destroy,
1698         .fill_modes = drm_helper_probe_single_connector_modes,
1699         .atomic_get_property = intel_digital_connector_atomic_get_property,
1700         .atomic_set_property = intel_digital_connector_atomic_set_property,
1701         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1702         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1703 };
1704
1705 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1706         .get_modes = intel_dsi_get_modes,
1707         .mode_valid = gen11_dsi_mode_valid,
1708         .atomic_check = intel_digital_connector_atomic_check,
1709 };
1710
1711 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1712                                  struct mipi_dsi_device *dsi)
1713 {
1714         return 0;
1715 }
1716
1717 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1718                                  struct mipi_dsi_device *dsi)
1719 {
1720         return 0;
1721 }
1722
1723 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1724                                        const struct mipi_dsi_msg *msg)
1725 {
1726         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1727         struct mipi_dsi_packet dsi_pkt;
1728         ssize_t ret;
1729         bool enable_lpdt = false;
1730
1731         ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1732         if (ret < 0)
1733                 return ret;
1734
1735         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1736                 enable_lpdt = true;
1737
1738         /* send packet header */
1739         ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1740         if (ret < 0)
1741                 return ret;
1742
1743         /* only long packet contains payload */
1744         if (mipi_dsi_packet_format_is_long(msg->type)) {
1745                 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1746                 if (ret < 0)
1747                         return ret;
1748         }
1749
1750         //TODO: add payload receive code if needed
1751
1752         ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1753
1754         return ret;
1755 }
1756
1757 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1758         .attach = gen11_dsi_host_attach,
1759         .detach = gen11_dsi_host_detach,
1760         .transfer = gen11_dsi_host_transfer,
1761 };
1762
1763 #define ICL_PREPARE_CNT_MAX     0x7
1764 #define ICL_CLK_ZERO_CNT_MAX    0xf
1765 #define ICL_TRAIL_CNT_MAX       0x7
1766 #define ICL_TCLK_PRE_CNT_MAX    0x3
1767 #define ICL_TCLK_POST_CNT_MAX   0x7
1768 #define ICL_HS_ZERO_CNT_MAX     0xf
1769 #define ICL_EXIT_ZERO_CNT_MAX   0x7
1770
1771 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1772 {
1773         struct drm_device *dev = intel_dsi->base.base.dev;
1774         struct drm_i915_private *dev_priv = to_i915(dev);
1775         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1776         u32 tlpx_ns;
1777         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1778         u32 ths_prepare_ns, tclk_trail_ns;
1779         u32 hs_zero_cnt;
1780         u32 tclk_pre_cnt, tclk_post_cnt;
1781
1782         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1783
1784         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1785         ths_prepare_ns = max(mipi_config->ths_prepare,
1786                              mipi_config->tclk_prepare);
1787
1788         /*
1789          * prepare cnt in escape clocks
1790          * this field represents a hexadecimal value with a precision
1791          * of 1.2 – i.e. the most significant bit is the integer
1792          * and the least significant 2 bits are fraction bits.
1793          * so, the field can represent a range of 0.25 to 1.75
1794          */
1795         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1796         if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1797                 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1798                             prepare_cnt);
1799                 prepare_cnt = ICL_PREPARE_CNT_MAX;
1800         }
1801
1802         /* clk zero count in escape clocks */
1803         clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1804                                     ths_prepare_ns, tlpx_ns);
1805         if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1806                 drm_dbg_kms(&dev_priv->drm,
1807                             "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1808                 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1809         }
1810
1811         /* trail cnt in escape clocks*/
1812         trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1813         if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1814                 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1815                             trail_cnt);
1816                 trail_cnt = ICL_TRAIL_CNT_MAX;
1817         }
1818
1819         /* tclk pre count in escape clocks */
1820         tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1821         if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1822                 drm_dbg_kms(&dev_priv->drm,
1823                             "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1824                 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1825         }
1826
1827         /* tclk post count in escape clocks */
1828         tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1829         if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1830                 drm_dbg_kms(&dev_priv->drm,
1831                             "tclk_post_cnt out of range (%d)\n",
1832                             tclk_post_cnt);
1833                 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1834         }
1835
1836         /* hs zero cnt in escape clocks */
1837         hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1838                                    ths_prepare_ns, tlpx_ns);
1839         if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1840                 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1841                             hs_zero_cnt);
1842                 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1843         }
1844
1845         /* hs exit zero cnt in escape clocks */
1846         exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1847         if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1848                 drm_dbg_kms(&dev_priv->drm,
1849                             "exit_zero_cnt out of range (%d)\n",
1850                             exit_zero_cnt);
1851                 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1852         }
1853
1854         /* clock lane dphy timings */
1855         intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1856                                CLK_PREPARE(prepare_cnt) |
1857                                CLK_ZERO_OVERRIDE |
1858                                CLK_ZERO(clk_zero_cnt) |
1859                                CLK_PRE_OVERRIDE |
1860                                CLK_PRE(tclk_pre_cnt) |
1861                                CLK_POST_OVERRIDE |
1862                                CLK_POST(tclk_post_cnt) |
1863                                CLK_TRAIL_OVERRIDE |
1864                                CLK_TRAIL(trail_cnt));
1865
1866         /* data lanes dphy timings */
1867         intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1868                                          HS_PREPARE(prepare_cnt) |
1869                                          HS_ZERO_OVERRIDE |
1870                                          HS_ZERO(hs_zero_cnt) |
1871                                          HS_TRAIL_OVERRIDE |
1872                                          HS_TRAIL(trail_cnt) |
1873                                          HS_EXIT_OVERRIDE |
1874                                          HS_EXIT(exit_zero_cnt));
1875
1876         intel_dsi_log_params(intel_dsi);
1877 }
1878
1879 static void icl_dsi_add_properties(struct intel_connector *connector)
1880 {
1881         u32 allowed_scalers;
1882
1883         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
1884                            BIT(DRM_MODE_SCALE_FULLSCREEN) |
1885                            BIT(DRM_MODE_SCALE_CENTER);
1886
1887         drm_connector_attach_scaling_mode_property(&connector->base,
1888                                                    allowed_scalers);
1889
1890         connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1891
1892         drm_connector_set_panel_orientation_with_quirk(&connector->base,
1893                                 intel_dsi_get_panel_orientation(connector),
1894                                 connector->panel.fixed_mode->hdisplay,
1895                                 connector->panel.fixed_mode->vdisplay);
1896 }
1897
1898 void icl_dsi_init(struct drm_i915_private *dev_priv)
1899 {
1900         struct drm_device *dev = &dev_priv->drm;
1901         struct intel_dsi *intel_dsi;
1902         struct intel_encoder *encoder;
1903         struct intel_connector *intel_connector;
1904         struct drm_connector *connector;
1905         struct drm_display_mode *fixed_mode;
1906         enum port port;
1907
1908         if (!intel_bios_is_dsi_present(dev_priv, &port))
1909                 return;
1910
1911         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1912         if (!intel_dsi)
1913                 return;
1914
1915         intel_connector = intel_connector_alloc();
1916         if (!intel_connector) {
1917                 kfree(intel_dsi);
1918                 return;
1919         }
1920
1921         encoder = &intel_dsi->base;
1922         intel_dsi->attached_connector = intel_connector;
1923         connector = &intel_connector->base;
1924
1925         /* register DSI encoder with DRM subsystem */
1926         drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
1927                          DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1928
1929         encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1930         encoder->pre_enable = gen11_dsi_pre_enable;
1931         encoder->enable = gen11_dsi_enable;
1932         encoder->disable = gen11_dsi_disable;
1933         encoder->post_disable = gen11_dsi_post_disable;
1934         encoder->port = port;
1935         encoder->get_config = gen11_dsi_get_config;
1936         encoder->update_pipe = intel_panel_update_backlight;
1937         encoder->compute_config = gen11_dsi_compute_config;
1938         encoder->get_hw_state = gen11_dsi_get_hw_state;
1939         encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1940         encoder->type = INTEL_OUTPUT_DSI;
1941         encoder->cloneable = 0;
1942         encoder->pipe_mask = ~0;
1943         encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1944         encoder->get_power_domains = gen11_dsi_get_power_domains;
1945
1946         /* register DSI connector with DRM subsystem */
1947         drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
1948                            DRM_MODE_CONNECTOR_DSI);
1949         drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1950         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1951         connector->interlace_allowed = false;
1952         connector->doublescan_allowed = false;
1953         intel_connector->get_hw_state = intel_connector_get_hw_state;
1954
1955         /* attach connector to encoder */
1956         intel_connector_attach_encoder(intel_connector, encoder);
1957
1958         mutex_lock(&dev->mode_config.mutex);
1959         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1960         mutex_unlock(&dev->mode_config.mutex);
1961
1962         if (!fixed_mode) {
1963                 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
1964                 goto err;
1965         }
1966
1967         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1968         intel_panel_setup_backlight(connector, INVALID_PIPE);
1969
1970         if (dev_priv->vbt.dsi.config->dual_link)
1971                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1972         else
1973                 intel_dsi->ports = BIT(port);
1974
1975         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1976         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1977
1978         for_each_dsi_port(port, intel_dsi->ports) {
1979                 struct intel_dsi_host *host;
1980
1981                 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
1982                 if (!host)
1983                         goto err;
1984
1985                 intel_dsi->dsi_hosts[port] = host;
1986         }
1987
1988         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1989                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1990                 goto err;
1991         }
1992
1993         icl_dphy_param_init(intel_dsi);
1994
1995         icl_dsi_add_properties(intel_connector);
1996         return;
1997
1998 err:
1999         drm_connector_cleanup(connector);
2000         drm_encoder_cleanup(&encoder->base);
2001         kfree(intel_dsi);
2002         kfree(intel_connector);
2003 }