drivers/gpu/drm/i915/display/g4x_hdmi.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  *
   5  * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
   6  */
   7
   8 #include "g4x_hdmi.h"
   9 #include "intel_audio.h"
  10 #include "intel_connector.h"
  11 #include "intel_de.h"
  12 #include "intel_display_types.h"
  13 #include "intel_dpio_phy.h"
  14 #include "intel_fifo_underrun.h"
  15 #include "intel_hdmi.h"
  16 #include "intel_hotplug.h"
  17 #include "intel_sideband.h"
  18 #include "intel_sdvo.h"
  19
  20 static void intel_hdmi_prepare(struct intel_encoder *encoder,
  21                                const struct intel_crtc_state *crtc_state)
  22 {
  23         struct drm_device *dev = encoder->base.dev;
  24         struct drm_i915_private *dev_priv = to_i915(dev);
  25         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
  26         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  27         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
  28         u32 hdmi_val;
  29
  30         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
  31
  32         hdmi_val = SDVO_ENCODING_HDMI;
  33         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
  34                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
  35         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  36                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
  37         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  38                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
  39
  40         if (crtc_state->pipe_bpp > 24)
  41                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
  42         else
  43                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
  44
  45         if (crtc_state->has_hdmi_sink)
  46                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
  47
  48         if (HAS_PCH_CPT(dev_priv))
  49                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
  50         else if (IS_CHERRYVIEW(dev_priv))
  51                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
  52         else
  53                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
  54
  55         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
  56         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
  57 }
  58
  59 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  60                                     enum pipe *pipe)
  61 {
  62         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  63         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  64         intel_wakeref_t wakeref;
  65         bool ret;
  66
  67         wakeref = intel_display_power_get_if_enabled(dev_priv,
  68                                                      encoder->power_domain);
  69         if (!wakeref)
  70                 return false;
  71
  72         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
  73
  74         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
  75
  76         return ret;
  77 }
  78
  79 static void intel_hdmi_get_config(struct intel_encoder *encoder,
  80                                   struct intel_crtc_state *pipe_config)
  81 {
  82         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  83         struct drm_device *dev = encoder->base.dev;
  84         struct drm_i915_private *dev_priv = to_i915(dev);
  85         u32 tmp, flags = 0;
  86         int dotclock;
  87
  88         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
  89
  90         tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
  91
  92         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
  93                 flags |= DRM_MODE_FLAG_PHSYNC;
  94         else
  95                 flags |= DRM_MODE_FLAG_NHSYNC;
  96
  97         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
  98                 flags |= DRM_MODE_FLAG_PVSYNC;
  99         else
 100                 flags |= DRM_MODE_FLAG_NVSYNC;
 101
 102         if (tmp & HDMI_MODE_SELECT_HDMI)
 103                 pipe_config->has_hdmi_sink = true;
 104
 105         pipe_config->infoframes.enable |=
 106                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
 107
 108         if (pipe_config->infoframes.enable)
 109                 pipe_config->has_infoframe = true;
 110
 111         if (tmp & HDMI_AUDIO_ENABLE)
 112                 pipe_config->has_audio = true;
 113
 114         if (!HAS_PCH_SPLIT(dev_priv) &&
 115             tmp & HDMI_COLOR_RANGE_16_235)
 116                 pipe_config->limited_color_range = true;
 117
 118         pipe_config->hw.adjusted_mode.flags |= flags;
 119
 120         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 121                 dotclock = pipe_config->port_clock * 2 / 3;
 122         else
 123                 dotclock = pipe_config->port_clock;
 124
 125         if (pipe_config->pixel_multiplier)
 126                 dotclock /= pipe_config->pixel_multiplier;
 127
 128         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 129
 130         pipe_config->lane_count = 4;
 131
 132         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
 133
 134         intel_read_infoframe(encoder, pipe_config,
 135                              HDMI_INFOFRAME_TYPE_AVI,
 136                              &pipe_config->infoframes.avi);
 137         intel_read_infoframe(encoder, pipe_config,
 138                              HDMI_INFOFRAME_TYPE_SPD,
 139                              &pipe_config->infoframes.spd);
 140         intel_read_infoframe(encoder, pipe_config,
 141                              HDMI_INFOFRAME_TYPE_VENDOR,
 142                              &pipe_config->infoframes.hdmi);
 143 }
 144
 145 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 146                                     const struct intel_crtc_state *pipe_config,
 147                                     const struct drm_connector_state *conn_state)
 148 {
 149         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 150         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 151
 152         drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink);
 153         drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n",
 154                     pipe_name(crtc->pipe));
 155         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 156 }
 157
 158 static void g4x_enable_hdmi(struct intel_atomic_state *state,
 159                             struct intel_encoder *encoder,
 160                             const struct intel_crtc_state *pipe_config,
 161                             const struct drm_connector_state *conn_state)
 162 {
 163         struct drm_device *dev = encoder->base.dev;
 164         struct drm_i915_private *dev_priv = to_i915(dev);
 165         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 166         u32 temp;
 167
 168         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 169
 170         temp |= SDVO_ENABLE;
 171         if (pipe_config->has_audio)
 172                 temp |= HDMI_AUDIO_ENABLE;
 173
 174         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 175         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 176
 177         if (pipe_config->has_audio)
 178                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 179 }
 180
 181 static void ibx_enable_hdmi(struct intel_atomic_state *state,
 182                             struct intel_encoder *encoder,
 183                             const struct intel_crtc_state *pipe_config,
 184                             const struct drm_connector_state *conn_state)
 185 {
 186         struct drm_device *dev = encoder->base.dev;
 187         struct drm_i915_private *dev_priv = to_i915(dev);
 188         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 189         u32 temp;
 190
 191         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 192
 193         temp |= SDVO_ENABLE;
 194         if (pipe_config->has_audio)
 195                 temp |= HDMI_AUDIO_ENABLE;
 196
 197         /*
 198          * HW workaround, need to write this twice for issue
 199          * that may result in first write getting masked.
 200          */
 201         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 202         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 203         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 204         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 205
 206         /*
 207          * HW workaround, need to toggle enable bit off and on
 208          * for 12bpc with pixel repeat.
 209          *
 210          * FIXME: BSpec says this should be done at the end of
 211          * the modeset sequence, so not sure if this isn't too soon.
 212          */
 213         if (pipe_config->pipe_bpp > 24 &&
 214             pipe_config->pixel_multiplier > 1) {
 215                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
 216                                temp & ~SDVO_ENABLE);
 217                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 218
 219                 /*
 220                  * HW workaround, need to write this twice for issue
 221                  * that may result in first write getting masked.
 222                  */
 223                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 224                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 225                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 226                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 227         }
 228
 229         if (pipe_config->has_audio)
 230                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 231 }
 232
 233 static void cpt_enable_hdmi(struct intel_atomic_state *state,
 234                             struct intel_encoder *encoder,
 235                             const struct intel_crtc_state *pipe_config,
 236                             const struct drm_connector_state *conn_state)
 237 {
 238         struct drm_device *dev = encoder->base.dev;
 239         struct drm_i915_private *dev_priv = to_i915(dev);
 240         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 241         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 242         enum pipe pipe = crtc->pipe;
 243         u32 temp;
 244
 245         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 246
 247         temp |= SDVO_ENABLE;
 248         if (pipe_config->has_audio)
 249                 temp |= HDMI_AUDIO_ENABLE;
 250
 251         /*
 252          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
 253          *
 254          * The procedure for 12bpc is as follows:
 255          * 1. disable HDMI clock gating
 256          * 2. enable HDMI with 8bpc
 257          * 3. enable HDMI with 12bpc
 258          * 4. enable HDMI clock gating
 259          */
 260
 261         if (pipe_config->pipe_bpp > 24) {
 262                 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
 263                                intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
 264
 265                 temp &= ~SDVO_COLOR_FORMAT_MASK;
 266                 temp |= SDVO_COLOR_FORMAT_8bpc;
 267         }
 268
 269         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 270         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 271
 272         if (pipe_config->pipe_bpp > 24) {
 273                 temp &= ~SDVO_COLOR_FORMAT_MASK;
 274                 temp |= HDMI_COLOR_FORMAT_12bpc;
 275
 276                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 277                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 278
 279                 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
 280                                intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
 281         }
 282
 283         if (pipe_config->has_audio)
 284                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
 285 }
 286
 287 static void vlv_enable_hdmi(struct intel_atomic_state *state,
 288                             struct intel_encoder *encoder,
 289                             const struct intel_crtc_state *pipe_config,
 290                             const struct drm_connector_state *conn_state)
 291 {
 292 }
 293
 294 static void intel_disable_hdmi(struct intel_atomic_state *state,
 295                                struct intel_encoder *encoder,
 296                                const struct intel_crtc_state *old_crtc_state,
 297                                const struct drm_connector_state *old_conn_state)
 298 {
 299         struct drm_device *dev = encoder->base.dev;
 300         struct drm_i915_private *dev_priv = to_i915(dev);
 301         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 302         struct intel_digital_port *dig_port =
 303                 hdmi_to_dig_port(intel_hdmi);
 304         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 305         u32 temp;
 306
 307         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
 308
 309         temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
 310         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 311         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 312
 313         /*
 314          * HW workaround for IBX, we need to move the port
 315          * to transcoder A after disabling it to allow the
 316          * matching DP port to be enabled on transcoder A.
 317          */
 318         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
 319                 /*
 320                  * We get CPU/PCH FIFO underruns on the other pipe when
 321                  * doing the workaround. Sweep them under the rug.
 322                  */
 323                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 324                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 325
 326                 temp &= ~SDVO_PIPE_SEL_MASK;
 327                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
 328                 /*
 329                  * HW workaround, need to write this twice for issue
 330                  * that may result in first write getting masked.
 331                  */
 332                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 333                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 334                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 335                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 336
 337                 temp &= ~SDVO_ENABLE;
 338                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 339                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
 340
 341                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
 342                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 343                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 344         }
 345
 346         dig_port->set_infoframes(encoder,
 347                                        false,
 348                                        old_crtc_state, old_conn_state);
 349
 350         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
 351 }
 352
 353 static void g4x_disable_hdmi(struct intel_atomic_state *state,
 354                              struct intel_encoder *encoder,
 355                              const struct intel_crtc_state *old_crtc_state,
 356                              const struct drm_connector_state *old_conn_state)
 357 {
 358         if (old_crtc_state->has_audio)
 359                 intel_audio_codec_disable(encoder,
 360                                           old_crtc_state, old_conn_state);
 361
 362         intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
 363 }
 364
 365 static void pch_disable_hdmi(struct intel_atomic_state *state,
 366                              struct intel_encoder *encoder,
 367                              const struct intel_crtc_state *old_crtc_state,
 368                              const struct drm_connector_state *old_conn_state)
 369 {
 370         if (old_crtc_state->has_audio)
 371                 intel_audio_codec_disable(encoder,
 372                                           old_crtc_state, old_conn_state);
 373 }
 374
 375 static void pch_post_disable_hdmi(struct intel_atomic_state *state,
 376                                   struct intel_encoder *encoder,
 377                                   const struct intel_crtc_state *old_crtc_state,
 378                                   const struct drm_connector_state *old_conn_state)
 379 {
 380         intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
 381 }
 382
 383 static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
 384                                   struct intel_encoder *encoder,
 385                                   const struct intel_crtc_state *pipe_config,
 386                                   const struct drm_connector_state *conn_state)
 387 {
 388         struct intel_digital_port *dig_port =
 389                 enc_to_dig_port(encoder);
 390
 391         intel_hdmi_prepare(encoder, pipe_config);
 392
 393         dig_port->set_infoframes(encoder,
 394                                        pipe_config->has_infoframe,
 395                                        pipe_config, conn_state);
 396 }
 397
 398 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
 399                                 struct intel_encoder *encoder,
 400                                 const struct intel_crtc_state *pipe_config,
 401                                 const struct drm_connector_state *conn_state)
 402 {
 403         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 404         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 405
 406         vlv_phy_pre_encoder_enable(encoder, pipe_config);
 407
 408         /* HDMI 1.0V-2dB */
 409         vlv_set_phy_signal_level(encoder, pipe_config,
 410                                  0x2b245f5f, 0x00002000,
 411                                  0x5578b83a, 0x2b247878);
 412
 413         dig_port->set_infoframes(encoder,
 414                               pipe_config->has_infoframe,
 415                               pipe_config, conn_state);
 416
 417         g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
 418
 419         vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 420 }
 421
 422 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
 423                                     struct intel_encoder *encoder,
 424                                     const struct intel_crtc_state *pipe_config,
 425                                     const struct drm_connector_state *conn_state)
 426 {
 427         intel_hdmi_prepare(encoder, pipe_config);
 428
 429         vlv_phy_pre_pll_enable(encoder, pipe_config);
 430 }
 431
 432 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
 433                                     struct intel_encoder *encoder,
 434                                     const struct intel_crtc_state *pipe_config,
 435                                     const struct drm_connector_state *conn_state)
 436 {
 437         intel_hdmi_prepare(encoder, pipe_config);
 438
 439         chv_phy_pre_pll_enable(encoder, pipe_config);
 440 }
 441
 442 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
 443                                       struct intel_encoder *encoder,
 444                                       const struct intel_crtc_state *old_crtc_state,
 445                                       const struct drm_connector_state *old_conn_state)
 446 {
 447         chv_phy_post_pll_disable(encoder, old_crtc_state);
 448 }
 449
 450 static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
 451                                   struct intel_encoder *encoder,
 452                                   const struct intel_crtc_state *old_crtc_state,
 453                                   const struct drm_connector_state *old_conn_state)
 454 {
 455         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
 456         vlv_phy_reset_lanes(encoder, old_crtc_state);
 457 }
 458
 459 static void chv_hdmi_post_disable(struct intel_atomic_state *state,
 460                                   struct intel_encoder *encoder,
 461                                   const struct intel_crtc_state *old_crtc_state,
 462                                   const struct drm_connector_state *old_conn_state)
 463 {
 464         struct drm_device *dev = encoder->base.dev;
 465         struct drm_i915_private *dev_priv = to_i915(dev);
 466
 467         vlv_dpio_get(dev_priv);
 468
 469         /* Assert data lane reset */
 470         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
 471
 472         vlv_dpio_put(dev_priv);
 473 }
 474
 475 static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 476                                 struct intel_encoder *encoder,
 477                                 const struct intel_crtc_state *pipe_config,
 478                                 const struct drm_connector_state *conn_state)
 479 {
 480         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 481         struct drm_device *dev = encoder->base.dev;
 482         struct drm_i915_private *dev_priv = to_i915(dev);
 483
 484         chv_phy_pre_encoder_enable(encoder, pipe_config);
 485
 486         /* FIXME: Program the support xxx V-dB */
 487         /* Use 800mV-0dB */
 488         chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
 489
 490         dig_port->set_infoframes(encoder,
 491                               pipe_config->has_infoframe,
 492                               pipe_config, conn_state);
 493
 494         g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
 495
 496         vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 497
 498         /* Second common lane will stay alive on its own now */
 499         chv_phy_release_cl2_override(encoder);
 500 }
 501
 502 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 503         .destroy = intel_encoder_destroy,
 504 };
 505
 506 static enum intel_hotplug_state
 507 intel_hdmi_hotplug(struct intel_encoder *encoder,
 508                    struct intel_connector *connector)
 509 {
 510         enum intel_hotplug_state state;
 511
 512         state = intel_encoder_hotplug(encoder, connector);
 513
 514         /*
 515          * On many platforms the HDMI live state signal is known to be
 516          * unreliable, so we can't use it to detect if a sink is connected or
 517          * not. Instead we detect if it's connected based on whether we can
 518          * read the EDID or not. That in turn has a problem during disconnect,
 519          * since the HPD interrupt may be raised before the DDC lines get
 520          * disconnected (due to how the required length of DDC vs. HPD
 521          * connector pins are specified) and so we'll still be able to get a
 522          * valid EDID. To solve this schedule another detection cycle if this
 523          * time around we didn't detect any change in the sink's connection
 524          * status.
 525          */
 526         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
 527                 state = INTEL_HOTPLUG_RETRY;
 528
 529         return state;
 530 }
 531
 532 void g4x_hdmi_init(struct drm_i915_private *dev_priv,
 533                    i915_reg_t hdmi_reg, enum port port)
 534 {
 535         struct intel_digital_port *dig_port;
 536         struct intel_encoder *intel_encoder;
 537         struct intel_connector *intel_connector;
 538
 539         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
 540         if (!dig_port)
 541                 return;
 542
 543         intel_connector = intel_connector_alloc();
 544         if (!intel_connector) {
 545                 kfree(dig_port);
 546                 return;
 547         }
 548
 549         intel_encoder = &dig_port->base;
 550
 551         mutex_init(&dig_port->hdcp_mutex);
 552
 553         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
 554                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
 555                          "HDMI %c", port_name(port));
 556
 557         intel_encoder->hotplug = intel_hdmi_hotplug;
 558         intel_encoder->compute_config = intel_hdmi_compute_config;
 559         if (HAS_PCH_SPLIT(dev_priv)) {
 560                 intel_encoder->disable = pch_disable_hdmi;
 561                 intel_encoder->post_disable = pch_post_disable_hdmi;
 562         } else {
 563                 intel_encoder->disable = g4x_disable_hdmi;
 564         }
 565         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 566         intel_encoder->get_config = intel_hdmi_get_config;
 567         if (IS_CHERRYVIEW(dev_priv)) {
 568                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
 569                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
 570                 intel_encoder->enable = vlv_enable_hdmi;
 571                 intel_encoder->post_disable = chv_hdmi_post_disable;
 572                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
 573         } else if (IS_VALLEYVIEW(dev_priv)) {
 574                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
 575                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
 576                 intel_encoder->enable = vlv_enable_hdmi;
 577                 intel_encoder->post_disable = vlv_hdmi_post_disable;
 578         } else {
 579                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
 580                 if (HAS_PCH_CPT(dev_priv))
 581                         intel_encoder->enable = cpt_enable_hdmi;
 582                 else if (HAS_PCH_IBX(dev_priv))
 583                         intel_encoder->enable = ibx_enable_hdmi;
 584                 else
 585                         intel_encoder->enable = g4x_enable_hdmi;
 586         }
 587
 588         intel_encoder->type = INTEL_OUTPUT_HDMI;
 589         intel_encoder->power_domain = intel_port_to_power_domain(port);
 590         intel_encoder->port = port;
 591         if (IS_CHERRYVIEW(dev_priv)) {
 592                 if (port == PORT_D)
 593                         intel_encoder->pipe_mask = BIT(PIPE_C);
 594                 else
 595                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
 596         } else {
 597                 intel_encoder->pipe_mask = ~0;
 598         }
 599         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
 600         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
 601         /*
 602          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
 603          * to work on real hardware. And since g4x can send infoframes to
 604          * only one port anyway, nothing is lost by allowing it.
 605          */
 606         if (IS_G4X(dev_priv))
 607                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
 608
 609         dig_port->hdmi.hdmi_reg = hdmi_reg;
 610         dig_port->dp.output_reg = INVALID_MMIO_REG;
 611         dig_port->max_lanes = 4;
 612
 613         intel_infoframe_init(dig_port);
 614
 615         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 616         intel_hdmi_init_connector(dig_port, intel_connector);
 617 }