drivers/gpu/drm/i810/i810_drv.h

   1 /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28  *          Jeff Hartmann <jhartmann@valinux.com>
  29  *
  30  */
  31
  32 #ifndef _I810_DRV_H_
  33 #define _I810_DRV_H_
  34
  35 #include <drm/drm_ioctl.h>
  36 #include <drm/drm_legacy.h>
  37 #include <drm/i810_drm.h>
  38
  39 /* General customization:
  40  */
  41
  42 #define DRIVER_AUTHOR           "VA Linux Systems Inc."
  43
  44 #define DRIVER_NAME             "i810"
  45 #define DRIVER_DESC             "Intel i810"
  46 #define DRIVER_DATE             "20030605"
  47
  48 /* Interface history
  49  *
  50  * 1.1   - XFree86 4.1
  51  * 1.2   - XvMC interfaces
  52  *       - XFree86 4.2
  53  * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
  54  *       - Remove requirement for interrupt (leave stubs again)
  55  * 1.3   - Add page flipping.
  56  * 1.4   - fix DRM interface
  57  */
  58 #define DRIVER_MAJOR            1
  59 #define DRIVER_MINOR            4
  60 #define DRIVER_PATCHLEVEL       0
  61
  62 typedef struct drm_i810_buf_priv {
  63         u32 *in_use;
  64         int my_use_idx;
  65         int currently_mapped;
  66         void *virtual;
  67         void *kernel_virtual;
  68         drm_local_map_t map;
  69 } drm_i810_buf_priv_t;
  70
  71 typedef struct _drm_i810_ring_buffer {
  72         int tail_mask;
  73         unsigned long Start;
  74         unsigned long End;
  75         unsigned long Size;
  76         u8 *virtual_start;
  77         int head;
  78         int tail;
  79         int space;
  80         drm_local_map_t map;
  81 } drm_i810_ring_buffer_t;
  82
  83 typedef struct drm_i810_private {
  84         struct drm_local_map *sarea_map;
  85         struct drm_local_map *mmio_map;
  86
  87         drm_i810_sarea_t *sarea_priv;
  88         drm_i810_ring_buffer_t ring;
  89
  90         void *hw_status_page;
  91         unsigned long counter;
  92
  93         dma_addr_t dma_status_page;
  94
  95         struct drm_buf *mmap_buffer;
  96
  97         u32 front_di1, back_di1, zi1;
  98
  99         int back_offset;
 100         int depth_offset;
 101         int overlay_offset;
 102         int overlay_physical;
 103         int w, h;
 104         int pitch;
 105         int back_pitch;
 106         int depth_pitch;
 107
 108         int do_boxes;
 109         int dma_used;
 110
 111         int current_page;
 112         int page_flipping;
 113
 114         wait_queue_head_t irq_queue;
 115         atomic_t irq_received;
 116         atomic_t irq_emitted;
 117
 118         int front_offset;
 119 } drm_i810_private_t;
 120
 121                                 /* i810_dma.c */
 122 extern int i810_driver_dma_quiescent(struct drm_device *dev);
 123 void i810_driver_reclaim_buffers(struct drm_device *dev,
 124                                  struct drm_file *file_priv);
 125 extern int i810_driver_load(struct drm_device *, unsigned long flags);
 126 extern void i810_driver_lastclose(struct drm_device *dev);
 127 extern void i810_driver_preclose(struct drm_device *dev,
 128                                  struct drm_file *file_priv);
 129
 130 extern long i810_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 131 extern const struct drm_ioctl_desc i810_ioctls[];
 132 extern int i810_max_ioctl;
 133
 134 #define I810_BASE(reg)          ((unsigned long) \
 135                                 dev_priv->mmio_map->handle)
 136 #define I810_ADDR(reg)          (I810_BASE(reg) + reg)
 137 #define I810_DEREF(reg)         (*(__volatile__ int *)I810_ADDR(reg))
 138 #define I810_READ(reg)          I810_DEREF(reg)
 139 #define I810_WRITE(reg, val)    do { I810_DEREF(reg) = val; } while (0)
 140 #define I810_DEREF16(reg)       (*(__volatile__ u16 *)I810_ADDR(reg))
 141 #define I810_READ16(reg)        I810_DEREF16(reg)
 142 #define I810_WRITE16(reg, val)  do { I810_DEREF16(reg) = val; } while (0)
 143
 144 #define I810_VERBOSE 0
 145 #define RING_LOCALS     unsigned int outring, ringmask; \
 146                         volatile char *virt;
 147
 148 #define BEGIN_LP_RING(n) do {                                   \
 149         if (I810_VERBOSE)                                       \
 150                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", n);            \
 151         if (dev_priv->ring.space < n*4)                         \
 152                 i810_wait_ring(dev, n*4);                       \
 153         dev_priv->ring.space -= n*4;                            \
 154         outring = dev_priv->ring.tail;                          \
 155         ringmask = dev_priv->ring.tail_mask;                    \
 156         virt = dev_priv->ring.virtual_start;                    \
 157 } while (0)
 158
 159 #define ADVANCE_LP_RING() do {                                  \
 160         if (I810_VERBOSE)                                       \
 161                 DRM_DEBUG("ADVANCE_LP_RING\n");                 \
 162         dev_priv->ring.tail = outring;                          \
 163         I810_WRITE(LP_RING + RING_TAIL, outring);               \
 164 } while (0)
 165
 166 #define OUT_RING(n) do {                                        \
 167         if (I810_VERBOSE)                                       \
 168                 DRM_DEBUG("   OUT_RING %x\n", (int)(n));        \
 169         *(volatile unsigned int *)(virt + outring) = n;         \
 170         outring += 4;                                           \
 171         outring &= ringmask;                                    \
 172 } while (0)
 173
 174 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 175 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 176 #define CMD_REPORT_HEAD                 (7<<23)
 177 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 178 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 179
 180 #define INST_PARSER_CLIENT   0x00000000
 181 #define INST_OP_FLUSH        0x02000000
 182 #define INST_FLUSH_MAP_CACHE 0x00000001
 183
 184 #define BB1_START_ADDR_MASK   (~0x7)
 185 #define BB1_PROTECTED         (1<<0)
 186 #define BB1_UNPROTECTED       (0<<0)
 187 #define BB2_END_ADDR_MASK     (~0x7)
 188
 189 #define I810REG_HWSTAM          0x02098
 190 #define I810REG_INT_IDENTITY_R  0x020a4
 191 #define I810REG_INT_MASK_R      0x020a8
 192 #define I810REG_INT_ENABLE_R    0x020a0
 193
 194 #define LP_RING                 0x2030
 195 #define HP_RING                 0x2040
 196 #define RING_TAIL               0x00
 197 #define TAIL_ADDR               0x000FFFF8
 198 #define RING_HEAD               0x04
 199 #define HEAD_WRAP_COUNT         0xFFE00000
 200 #define HEAD_WRAP_ONE           0x00200000
 201 #define HEAD_ADDR               0x001FFFFC
 202 #define RING_START              0x08
 203 #define START_ADDR              0x00FFFFF8
 204 #define RING_LEN                0x0C
 205 #define RING_NR_PAGES           0x000FF000
 206 #define RING_REPORT_MASK        0x00000006
 207 #define RING_REPORT_64K         0x00000002
 208 #define RING_REPORT_128K        0x00000004
 209 #define RING_NO_REPORT          0x00000000
 210 #define RING_VALID_MASK         0x00000001
 211 #define RING_VALID              0x00000001
 212 #define RING_INVALID            0x00000000
 213
 214 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 215 #define SC_UPDATE_SCISSOR       (0x1<<1)
 216 #define SC_ENABLE_MASK          (0x1<<0)
 217 #define SC_ENABLE               (0x1<<0)
 218
 219 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 220 #define SCI_YMIN_MASK      (0xffff<<16)
 221 #define SCI_XMIN_MASK      (0xffff<<0)
 222 #define SCI_YMAX_MASK      (0xffff<<16)
 223 #define SCI_XMAX_MASK      (0xffff<<0)
 224
 225 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 226 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 227 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x2)
 228 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 229 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 230 #define GFX_OP_PRIMITIVE         ((0x3<<29)|(0x1f<<24))
 231
 232 #define CMD_OP_Z_BUFFER_INFO     ((0x0<<29)|(0x16<<23))
 233 #define CMD_OP_DESTBUFFER_INFO   ((0x0<<29)|(0x15<<23))
 234 #define CMD_OP_FRONTBUFFER_INFO  ((0x0<<29)|(0x14<<23))
 235 #define CMD_OP_WAIT_FOR_EVENT    ((0x0<<29)|(0x03<<23))
 236
 237 #define BR00_BITBLT_CLIENT   0x40000000
 238 #define BR00_OP_COLOR_BLT    0x10000000
 239 #define BR00_OP_SRC_COPY_BLT 0x10C00000
 240 #define BR13_SOLID_PATTERN   0x80000000
 241
 242 #define WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 243 #define WAIT_FOR_PLANE_A_FLIP      (1<<2)
 244 #define WAIT_FOR_VBLANK (1<<3)
 245
 246 #endif