2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/component.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/hdmi.h>
21 #include <linux/module.h>
22 #include <linux/platform_data/tda9950.h>
23 #include <linux/irq.h>
24 #include <sound/asoundef.h>
25 #include <sound/hdmi-codec.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_edid.h>
30 #include <drm/drm_of.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/i2c/tda998x.h>
34 #include <media/cec-notifier.h>
36 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
44 struct tda998x_audio_route {
50 struct tda998x_audio_settings {
51 const struct tda998x_audio_route *route;
52 struct tda998x_audio_params params;
59 struct i2c_client *cec;
60 struct i2c_client *hdmi;
66 bool supports_infoframes;
71 unsigned long tmds_clock;
72 struct tda998x_audio_settings audio;
74 struct platform_device *audio_pdev;
75 struct mutex audio_mutex;
77 struct mutex edid_mutex;
78 wait_queue_head_t wq_edid;
79 volatile int wq_edid_wait;
81 struct work_struct detect_work;
82 struct timer_list edid_delay_timer;
83 wait_queue_head_t edid_delay_waitq;
84 bool edid_delay_active;
86 struct drm_encoder encoder;
87 struct drm_bridge bridge;
88 struct drm_connector connector;
90 u8 audio_port_enable[AUDIO_ROUTE_NUM];
91 struct tda9950_glue cec_glue;
92 struct gpio_desc *calib;
93 struct cec_notifier *cec_notify;
96 #define conn_to_tda998x_priv(x) \
97 container_of(x, struct tda998x_priv, connector)
98 #define enc_to_tda998x_priv(x) \
99 container_of(x, struct tda998x_priv, encoder)
100 #define bridge_to_tda998x_priv(x) \
101 container_of(x, struct tda998x_priv, bridge)
103 /* The TDA9988 series of devices use a paged register scheme.. to simplify
104 * things we encode the page # in upper bits of the register #. To read/
105 * write a given register, we need to make sure CURPAGE register is set
106 * appropriately. Which implies reads/writes are not atomic. Fun!
109 #define REG(page, addr) (((page) << 8) | (addr))
110 #define REG2ADDR(reg) ((reg) & 0xff)
111 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
113 #define REG_CURPAGE 0xff /* write */
116 /* Page 00h: General Control */
117 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
118 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
119 # define MAIN_CNTRL0_SR (1 << 0)
120 # define MAIN_CNTRL0_DECS (1 << 1)
121 # define MAIN_CNTRL0_DEHS (1 << 2)
122 # define MAIN_CNTRL0_CECS (1 << 3)
123 # define MAIN_CNTRL0_CEHS (1 << 4)
124 # define MAIN_CNTRL0_SCALER (1 << 7)
125 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
126 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
127 # define SOFTRESET_AUDIO (1 << 0)
128 # define SOFTRESET_I2C_MASTER (1 << 1)
129 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
130 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
131 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
132 # define I2C_MASTER_DIS_MM (1 << 0)
133 # define I2C_MASTER_DIS_FILT (1 << 1)
134 # define I2C_MASTER_APP_STRT_LAT (1 << 2)
135 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
136 # define FEAT_POWERDOWN_PREFILT BIT(0)
137 # define FEAT_POWERDOWN_CSC BIT(1)
138 # define FEAT_POWERDOWN_SPDIF (1 << 3)
139 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
140 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
141 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
142 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
143 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
144 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
145 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
146 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
147 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
148 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
149 # define VIP_CNTRL_0_MIRR_A (1 << 7)
150 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
151 # define VIP_CNTRL_0_MIRR_B (1 << 3)
152 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
153 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
154 # define VIP_CNTRL_1_MIRR_C (1 << 7)
155 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
156 # define VIP_CNTRL_1_MIRR_D (1 << 3)
157 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
158 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
159 # define VIP_CNTRL_2_MIRR_E (1 << 7)
160 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
161 # define VIP_CNTRL_2_MIRR_F (1 << 3)
162 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
163 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
164 # define VIP_CNTRL_3_X_TGL (1 << 0)
165 # define VIP_CNTRL_3_H_TGL (1 << 1)
166 # define VIP_CNTRL_3_V_TGL (1 << 2)
167 # define VIP_CNTRL_3_EMB (1 << 3)
168 # define VIP_CNTRL_3_SYNC_DE (1 << 4)
169 # define VIP_CNTRL_3_SYNC_HS (1 << 5)
170 # define VIP_CNTRL_3_DE_INT (1 << 6)
171 # define VIP_CNTRL_3_EDGE (1 << 7)
172 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
173 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
174 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
175 # define VIP_CNTRL_4_CCIR656 (1 << 4)
176 # define VIP_CNTRL_4_656_ALT (1 << 5)
177 # define VIP_CNTRL_4_TST_656 (1 << 6)
178 # define VIP_CNTRL_4_TST_PAT (1 << 7)
179 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
180 # define VIP_CNTRL_5_CKCASE (1 << 0)
181 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
182 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
183 # define MUX_AP_SELECT_I2S 0x64
184 # define MUX_AP_SELECT_SPDIF 0x40
185 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
186 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
187 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
188 # define MAT_CONTRL_MAT_BP (1 << 2)
189 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
190 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
191 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
192 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
193 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
194 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
195 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
196 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
197 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
198 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
199 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
200 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
201 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
202 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
203 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
204 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
205 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
206 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
207 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
208 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
209 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
210 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
211 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
212 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
213 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
214 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
215 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
216 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
217 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
218 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
219 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
220 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
221 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
222 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
223 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
224 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
225 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
226 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
227 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
228 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
229 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
230 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
231 # define TBG_CNTRL_0_TOP_TGL (1 << 0)
232 # define TBG_CNTRL_0_TOP_SEL (1 << 1)
233 # define TBG_CNTRL_0_DE_EXT (1 << 2)
234 # define TBG_CNTRL_0_TOP_EXT (1 << 3)
235 # define TBG_CNTRL_0_FRAME_DIS (1 << 5)
236 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
237 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
238 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
239 # define TBG_CNTRL_1_H_TGL (1 << 0)
240 # define TBG_CNTRL_1_V_TGL (1 << 1)
241 # define TBG_CNTRL_1_TGL_EN (1 << 2)
242 # define TBG_CNTRL_1_X_EXT (1 << 3)
243 # define TBG_CNTRL_1_H_EXT (1 << 4)
244 # define TBG_CNTRL_1_V_EXT (1 << 5)
245 # define TBG_CNTRL_1_DWIN_DIS (1 << 6)
246 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
247 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
248 # define HVF_CNTRL_0_SM (1 << 7)
249 # define HVF_CNTRL_0_RWB (1 << 6)
250 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
251 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
252 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
253 # define HVF_CNTRL_1_FOR (1 << 0)
254 # define HVF_CNTRL_1_YUVBLK (1 << 1)
255 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
256 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
257 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
258 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
259 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
260 # define I2S_FORMAT_PHILIPS (0 << 0)
261 # define I2S_FORMAT_LEFT_J (2 << 0)
262 # define I2S_FORMAT_RIGHT_J (3 << 0)
263 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
264 # define AIP_CLKSEL_AIP_SPDIF (0 << 3)
265 # define AIP_CLKSEL_AIP_I2S (1 << 3)
266 # define AIP_CLKSEL_FS_ACLK (0 << 0)
267 # define AIP_CLKSEL_FS_MCLK (1 << 0)
268 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
270 /* Page 02h: PLL settings */
271 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
272 # define PLL_SERIAL_1_SRL_FDN (1 << 0)
273 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
274 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
275 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
276 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
277 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
278 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
279 # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
280 # define PLL_SERIAL_3_SRL_DE (1 << 2)
281 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
282 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
283 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
284 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
285 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
286 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
287 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
288 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
289 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
290 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
291 # define AUDIO_DIV_SERCLK_1 0
292 # define AUDIO_DIV_SERCLK_2 1
293 # define AUDIO_DIV_SERCLK_4 2
294 # define AUDIO_DIV_SERCLK_8 3
295 # define AUDIO_DIV_SERCLK_16 4
296 # define AUDIO_DIV_SERCLK_32 5
297 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
298 # define SEL_CLK_SEL_CLK1 (1 << 0)
299 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
300 # define SEL_CLK_ENA_SC_CLK (1 << 3)
301 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
304 /* Page 09h: EDID Control */
305 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
306 /* next 127 successive registers are the EDID block */
307 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
308 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
309 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
310 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
311 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
314 /* Page 10h: information frames and packets */
315 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
316 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
317 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
318 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
319 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
322 /* Page 11h: audio settings and content info packets */
323 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
324 # define AIP_CNTRL_0_RST_FIFO (1 << 0)
325 # define AIP_CNTRL_0_SWAP (1 << 1)
326 # define AIP_CNTRL_0_LAYOUT (1 << 2)
327 # define AIP_CNTRL_0_ACR_MAN (1 << 5)
328 # define AIP_CNTRL_0_RST_CTS (1 << 6)
329 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
330 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
331 # define CA_I2S_HBR_CHSTAT (1 << 6)
332 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
333 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
334 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
335 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
336 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
337 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
338 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
339 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
340 # define CTS_N_K(x) (((x) & 7) << 0)
341 # define CTS_N_M(x) (((x) & 3) << 4)
342 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
343 # define ENC_CNTRL_RST_ENC (1 << 0)
344 # define ENC_CNTRL_RST_SEL (1 << 1)
345 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
346 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
347 # define DIP_FLAGS_ACR (1 << 0)
348 # define DIP_FLAGS_GC (1 << 1)
349 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
350 # define DIP_IF_FLAGS_IF1 (1 << 1)
351 # define DIP_IF_FLAGS_IF2 (1 << 2)
352 # define DIP_IF_FLAGS_IF3 (1 << 3)
353 # define DIP_IF_FLAGS_IF4 (1 << 4)
354 # define DIP_IF_FLAGS_IF5 (1 << 5)
355 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
358 /* Page 12h: HDCP and OTP */
359 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
360 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
361 # define TX4_PD_RAM (1 << 1)
362 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
363 # define TX33_HDMI (1 << 1)
366 /* Page 13h: Gamut related metadata packets */
370 /* CEC registers: (not paged)
372 #define REG_CEC_INTSTATUS 0xee /* read */
373 # define CEC_INTSTATUS_CEC (1 << 0)
374 # define CEC_INTSTATUS_HDMI (1 << 1)
375 #define REG_CEC_CAL_XOSC_CTRL1 0xf2
376 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0)
377 #define REG_CEC_DES_FREQ2 0xf5
378 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
379 #define REG_CEC_CLK 0xf6
380 # define CEC_CLK_FRO 0x11
381 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
382 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
383 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
384 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
385 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
386 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
387 #define REG_CEC_RXSHPDINT 0xfd /* read */
388 # define CEC_RXSHPDINT_RXSENS BIT(0)
389 # define CEC_RXSHPDINT_HPD BIT(1)
390 #define REG_CEC_RXSHPDLEV 0xfe /* read */
391 # define CEC_RXSHPDLEV_RXSENS (1 << 0)
392 # define CEC_RXSHPDLEV_HPD (1 << 1)
394 #define REG_CEC_ENAMODS 0xff /* read/write */
395 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7)
396 # define CEC_ENAMODS_DIS_FRO (1 << 6)
397 # define CEC_ENAMODS_DIS_CCLK (1 << 5)
398 # define CEC_ENAMODS_EN_RXSENS (1 << 2)
399 # define CEC_ENAMODS_EN_HDMI (1 << 1)
400 # define CEC_ENAMODS_EN_CEC (1 << 0)
403 /* Device versions: */
404 #define TDA9989N2 0x0101
405 #define TDA19989 0x0201
406 #define TDA19989N2 0x0202
407 #define TDA19988 0x0301
410 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
412 u8 buf[] = {addr, val};
413 struct i2c_msg msg = {
414 .addr = priv->cec_addr,
420 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
422 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
427 cec_read(struct tda998x_priv *priv, u8 addr)
430 struct i2c_msg msg[2] = {
432 .addr = priv->cec_addr,
436 .addr = priv->cec_addr,
444 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
446 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
454 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
456 int val = cec_read(priv, REG_CEC_ENAMODS);
466 cec_write(priv, REG_CEC_ENAMODS, val);
469 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
474 cec_write(priv, 0xf3, 0xc0);
475 cec_write(priv, 0xf4, 0xd4);
477 /* Enable automatic calibration mode */
478 val = cec_read(priv, REG_CEC_DES_FREQ2);
479 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
480 cec_write(priv, REG_CEC_DES_FREQ2, val);
482 /* Enable free running oscillator */
483 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
484 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
486 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
487 CEC_CAL_XOSC_CTRL1_ENA_CAL);
489 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
494 * Calibration for the internal oscillator: we need to set calibration mode,
495 * and then pulse the IRQ line low for a 10ms ± 1% period.
497 static void tda998x_cec_calibration(struct tda998x_priv *priv)
499 struct gpio_desc *calib = priv->calib;
501 mutex_lock(&priv->edid_mutex);
502 if (priv->hdmi->irq > 0)
503 disable_irq(priv->hdmi->irq);
504 gpiod_direction_output(calib, 1);
505 tda998x_cec_set_calibration(priv, true);
508 gpiod_set_value(calib, 0);
510 gpiod_set_value(calib, 1);
513 tda998x_cec_set_calibration(priv, false);
514 gpiod_direction_input(calib);
515 if (priv->hdmi->irq > 0)
516 enable_irq(priv->hdmi->irq);
517 mutex_unlock(&priv->edid_mutex);
520 static int tda998x_cec_hook_init(void *data)
522 struct tda998x_priv *priv = data;
523 struct gpio_desc *calib;
525 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
527 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
529 return PTR_ERR(calib);
537 static void tda998x_cec_hook_exit(void *data)
539 struct tda998x_priv *priv = data;
541 gpiod_put(priv->calib);
545 static int tda998x_cec_hook_open(void *data)
547 struct tda998x_priv *priv = data;
549 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
550 tda998x_cec_calibration(priv);
555 static void tda998x_cec_hook_release(void *data)
557 struct tda998x_priv *priv = data;
559 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
563 set_page(struct tda998x_priv *priv, u16 reg)
565 if (REG2PAGE(reg) != priv->current_page) {
566 struct i2c_client *client = priv->hdmi;
568 REG_CURPAGE, REG2PAGE(reg)
570 int ret = i2c_master_send(client, buf, sizeof(buf));
572 dev_err(&client->dev, "%s %04x err %d\n", __func__,
577 priv->current_page = REG2PAGE(reg);
583 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
585 struct i2c_client *client = priv->hdmi;
586 u8 addr = REG2ADDR(reg);
589 mutex_lock(&priv->mutex);
590 ret = set_page(priv, reg);
594 ret = i2c_master_send(client, &addr, sizeof(addr));
598 ret = i2c_master_recv(client, buf, cnt);
605 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
607 mutex_unlock(&priv->mutex);
611 #define MAX_WRITE_RANGE_BUF 32
614 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
616 struct i2c_client *client = priv->hdmi;
617 /* This is the maximum size of the buffer passed in */
618 u8 buf[MAX_WRITE_RANGE_BUF + 1];
621 if (cnt > MAX_WRITE_RANGE_BUF) {
622 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
623 MAX_WRITE_RANGE_BUF);
627 buf[0] = REG2ADDR(reg);
628 memcpy(&buf[1], p, cnt);
630 mutex_lock(&priv->mutex);
631 ret = set_page(priv, reg);
635 ret = i2c_master_send(client, buf, cnt + 1);
637 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
639 mutex_unlock(&priv->mutex);
643 reg_read(struct tda998x_priv *priv, u16 reg)
648 ret = reg_read_range(priv, reg, &val, sizeof(val));
655 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
657 struct i2c_client *client = priv->hdmi;
658 u8 buf[] = {REG2ADDR(reg), val};
661 mutex_lock(&priv->mutex);
662 ret = set_page(priv, reg);
666 ret = i2c_master_send(client, buf, sizeof(buf));
668 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
670 mutex_unlock(&priv->mutex);
674 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
676 struct i2c_client *client = priv->hdmi;
677 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
680 mutex_lock(&priv->mutex);
681 ret = set_page(priv, reg);
685 ret = i2c_master_send(client, buf, sizeof(buf));
687 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
689 mutex_unlock(&priv->mutex);
693 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
697 old_val = reg_read(priv, reg);
699 reg_write(priv, reg, old_val | val);
703 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
707 old_val = reg_read(priv, reg);
709 reg_write(priv, reg, old_val & ~val);
713 tda998x_reset(struct tda998x_priv *priv)
715 /* reset audio and i2c master: */
716 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
718 reg_write(priv, REG_SOFTRESET, 0);
721 /* reset transmitter: */
722 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
723 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
725 /* PLL registers common configuration */
726 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
727 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
728 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
729 reg_write(priv, REG_SERIALIZER, 0x00);
730 reg_write(priv, REG_BUFFER_OUT, 0x00);
731 reg_write(priv, REG_PLL_SCG1, 0x00);
732 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
733 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
734 reg_write(priv, REG_PLL_SCGN1, 0xfa);
735 reg_write(priv, REG_PLL_SCGN2, 0x00);
736 reg_write(priv, REG_PLL_SCGR1, 0x5b);
737 reg_write(priv, REG_PLL_SCGR2, 0x00);
738 reg_write(priv, REG_PLL_SCG2, 0x10);
740 /* Write the default value MUX register */
741 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
745 * The TDA998x has a problem when trying to read the EDID close to a
746 * HPD assertion: it needs a delay of 100ms to avoid timing out while
747 * trying to read EDID data.
749 * However, tda998x_connector_get_modes() may be called at any moment
750 * after tda998x_connector_detect() indicates that we are connected, so
751 * we need to delay probing modes in tda998x_connector_get_modes() after
752 * we have seen a HPD inactive->active transition. This code implements
755 static void tda998x_edid_delay_done(struct timer_list *t)
757 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
759 priv->edid_delay_active = false;
760 wake_up(&priv->edid_delay_waitq);
761 schedule_work(&priv->detect_work);
764 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
766 priv->edid_delay_active = true;
767 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
770 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
772 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
776 * We need to run the KMS hotplug event helper outside of our threaded
777 * interrupt routine as this can call back into our get_modes method,
778 * which will want to make use of interrupts.
780 static void tda998x_detect_work(struct work_struct *work)
782 struct tda998x_priv *priv =
783 container_of(work, struct tda998x_priv, detect_work);
784 struct drm_device *dev = priv->connector.dev;
787 drm_kms_helper_hotplug_event(dev);
791 * only 2 interrupts may occur: screen plug/unplug and EDID read
793 static irqreturn_t tda998x_irq_thread(int irq, void *data)
795 struct tda998x_priv *priv = data;
796 u8 sta, cec, lvl, flag0, flag1, flag2;
797 bool handled = false;
799 sta = cec_read(priv, REG_CEC_INTSTATUS);
800 if (sta & CEC_INTSTATUS_HDMI) {
801 cec = cec_read(priv, REG_CEC_RXSHPDINT);
802 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
803 flag0 = reg_read(priv, REG_INT_FLAGS_0);
804 flag1 = reg_read(priv, REG_INT_FLAGS_1);
805 flag2 = reg_read(priv, REG_INT_FLAGS_2);
807 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
808 sta, cec, lvl, flag0, flag1, flag2);
810 if (cec & CEC_RXSHPDINT_HPD) {
811 if (lvl & CEC_RXSHPDLEV_HPD) {
812 tda998x_edid_delay_start(priv);
814 schedule_work(&priv->detect_work);
815 cec_notifier_set_phys_addr(priv->cec_notify,
816 CEC_PHYS_ADDR_INVALID);
822 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
823 priv->wq_edid_wait = 0;
824 wake_up(&priv->wq_edid);
829 return IRQ_RETVAL(handled);
833 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
834 union hdmi_infoframe *frame)
836 u8 buf[MAX_WRITE_RANGE_BUF];
839 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
841 dev_err(&priv->hdmi->dev,
842 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
843 frame->any.type, len);
847 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
848 reg_write_range(priv, addr, buf, len);
849 reg_set(priv, REG_DIP_IF_FLAGS, bit);
852 static void tda998x_write_aif(struct tda998x_priv *priv,
853 const struct hdmi_audio_infoframe *cea)
855 union hdmi_infoframe frame;
859 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
863 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
865 union hdmi_infoframe frame;
867 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
868 &priv->connector, mode);
869 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
871 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
876 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
877 [AUDIO_ROUTE_I2S] = {
879 .mux_ap = MUX_AP_SELECT_I2S,
880 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
882 [AUDIO_ROUTE_SPDIF] = {
884 .mux_ap = MUX_AP_SELECT_SPDIF,
885 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
889 /* Configure the TDA998x audio data and clock routing. */
890 static int tda998x_derive_routing(struct tda998x_priv *priv,
891 struct tda998x_audio_settings *s,
894 s->route = &tda998x_audio_route[route];
895 s->ena_ap = priv->audio_port_enable[route];
896 if (s->ena_ap == 0) {
897 dev_err(&priv->hdmi->dev, "no audio configuration found\n");
905 * The audio clock divisor register controls a divider producing Audio_Clk_Out
906 * from SERclk by dividing it by 2^n where 0 <= n <= 5. We don't know what
907 * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
909 * It seems that Audio_Clk_Out must be the smallest value that is greater
910 * than 128*fs, otherwise audio does not function. There is some suggestion
911 * that 126*fs is a better value.
913 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
915 unsigned long min_audio_clk = fs * 128;
916 unsigned long ser_clk = priv->tmds_clock * 1000;
919 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
920 if (ser_clk > min_audio_clk << adiv)
923 dev_dbg(&priv->hdmi->dev,
924 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
925 ser_clk, fs, min_audio_clk, adiv);
931 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
932 * generate the CTS value. It appears that the "measured time stamp" is
933 * the number of TDMS clock cycles within a number of audio input clock
934 * cycles defined by the k and N parameters defined below, in a similar
935 * way to that which is set out in the CTS generation in the HDMI spec.
937 * tmdsclk ----> mts -> /m ---> CTS
941 * CTS = mts / m, where m is 2^M.
942 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
943 * /N is a divider based on the HDMI specified N value.
945 * This produces the following equation:
946 * CTS = tmds_clock * k * N / (sclk * m)
948 * When combined with the sink-side equation, and realising that sclk is
949 * bclk_ratio * fs, we end up with:
950 * k = m * bclk_ratio / 128.
952 * Note: S/PDIF always uses a bclk_ratio of 64.
954 static int tda998x_derive_cts_n(struct tda998x_priv *priv,
955 struct tda998x_audio_settings *settings,
960 settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
963 settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
966 settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
969 settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
972 settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
975 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
982 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
985 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
986 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
987 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
989 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
993 static void tda998x_configure_audio(struct tda998x_priv *priv)
995 const struct tda998x_audio_settings *settings = &priv->audio;
999 /* If audio is not configured, there is nothing to do. */
1000 if (settings->ena_ap == 0)
1003 adiv = tda998x_get_adiv(priv, settings->params.sample_rate);
1005 /* Enable audio ports */
1006 reg_write(priv, REG_ENA_AP, settings->ena_ap);
1007 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1008 reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1009 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1010 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1011 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1012 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
1013 reg_write(priv, REG_CTS_N, settings->cts_n);
1014 reg_write(priv, REG_AUDIO_DIV, adiv);
1017 * This is the approximate value of N, which happens to be
1018 * the recommended values for non-coherent clocks.
1020 n = 128 * settings->params.sample_rate / 1000;
1022 /* Write the CTS and N values */
1029 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1031 /* Reset CTS generator */
1032 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1033 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1035 /* Write the channel status
1036 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1037 * there is a separate register for each I2S wire.
1039 buf[0] = settings->params.status[0];
1040 buf[1] = settings->params.status[1];
1041 buf[2] = settings->params.status[3];
1042 buf[3] = settings->params.status[4];
1043 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1045 tda998x_audio_mute(priv, true);
1047 tda998x_audio_mute(priv, false);
1049 tda998x_write_aif(priv, &settings->params.cea);
1052 static int tda998x_audio_hw_params(struct device *dev, void *data,
1053 struct hdmi_codec_daifmt *daifmt,
1054 struct hdmi_codec_params *params)
1056 struct tda998x_priv *priv = dev_get_drvdata(dev);
1057 unsigned int bclk_ratio;
1058 bool spdif = daifmt->fmt == HDMI_SPDIF;
1060 struct tda998x_audio_settings audio = {
1062 .sample_width = params->sample_width,
1063 .sample_rate = params->sample_rate,
1068 memcpy(audio.params.status, params->iec.status,
1069 min(sizeof(audio.params.status), sizeof(params->iec.status)));
1071 switch (daifmt->fmt) {
1073 audio.i2s_format = I2S_FORMAT_PHILIPS;
1076 audio.i2s_format = I2S_FORMAT_LEFT_J;
1079 audio.i2s_format = I2S_FORMAT_RIGHT_J;
1082 audio.i2s_format = 0;
1085 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1090 (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1091 daifmt->bit_clk_master || daifmt->frame_clk_master)) {
1092 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1093 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1094 daifmt->bit_clk_master,
1095 daifmt->frame_clk_master);
1099 ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1103 bclk_ratio = spdif ? 64 : params->sample_width * 2;
1104 ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1108 mutex_lock(&priv->audio_mutex);
1109 priv->audio = audio;
1110 if (priv->supports_infoframes && priv->sink_has_audio)
1111 tda998x_configure_audio(priv);
1112 mutex_unlock(&priv->audio_mutex);
1117 static void tda998x_audio_shutdown(struct device *dev, void *data)
1119 struct tda998x_priv *priv = dev_get_drvdata(dev);
1121 mutex_lock(&priv->audio_mutex);
1123 reg_write(priv, REG_ENA_AP, 0);
1124 priv->audio.ena_ap = 0;
1126 mutex_unlock(&priv->audio_mutex);
1129 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1131 struct tda998x_priv *priv = dev_get_drvdata(dev);
1133 mutex_lock(&priv->audio_mutex);
1135 tda998x_audio_mute(priv, enable);
1137 mutex_unlock(&priv->audio_mutex);
1141 static int tda998x_audio_get_eld(struct device *dev, void *data,
1142 uint8_t *buf, size_t len)
1144 struct tda998x_priv *priv = dev_get_drvdata(dev);
1146 mutex_lock(&priv->audio_mutex);
1147 memcpy(buf, priv->connector.eld,
1148 min(sizeof(priv->connector.eld), len));
1149 mutex_unlock(&priv->audio_mutex);
1154 static const struct hdmi_codec_ops audio_codec_ops = {
1155 .hw_params = tda998x_audio_hw_params,
1156 .audio_shutdown = tda998x_audio_shutdown,
1157 .digital_mute = tda998x_audio_digital_mute,
1158 .get_eld = tda998x_audio_get_eld,
1161 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1164 struct hdmi_codec_pdata codec_data = {
1165 .ops = &audio_codec_ops,
1166 .max_i2s_channels = 2,
1169 if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1171 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1172 codec_data.spdif = 1;
1174 priv->audio_pdev = platform_device_register_data(
1175 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1176 &codec_data, sizeof(codec_data));
1178 return PTR_ERR_OR_ZERO(priv->audio_pdev);
1181 /* DRM connector functions */
1183 static enum drm_connector_status
1184 tda998x_connector_detect(struct drm_connector *connector, bool force)
1186 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1187 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1189 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1190 connector_status_disconnected;
1193 static void tda998x_connector_destroy(struct drm_connector *connector)
1195 drm_connector_cleanup(connector);
1198 static const struct drm_connector_funcs tda998x_connector_funcs = {
1199 .reset = drm_atomic_helper_connector_reset,
1200 .fill_modes = drm_helper_probe_single_connector_modes,
1201 .detect = tda998x_connector_detect,
1202 .destroy = tda998x_connector_destroy,
1203 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1204 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1207 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1209 struct tda998x_priv *priv = data;
1213 offset = (blk & 1) ? 128 : 0;
1216 mutex_lock(&priv->edid_mutex);
1218 reg_write(priv, REG_DDC_ADDR, 0xa0);
1219 reg_write(priv, REG_DDC_OFFS, offset);
1220 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1221 reg_write(priv, REG_DDC_SEGM, segptr);
1223 /* enable reading EDID: */
1224 priv->wq_edid_wait = 1;
1225 reg_write(priv, REG_EDID_CTRL, 0x1);
1227 /* flag must be cleared by sw: */
1228 reg_write(priv, REG_EDID_CTRL, 0x0);
1230 /* wait for block read to complete: */
1231 if (priv->hdmi->irq) {
1232 i = wait_event_timeout(priv->wq_edid,
1233 !priv->wq_edid_wait,
1234 msecs_to_jiffies(100));
1236 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1241 for (i = 100; i > 0; i--) {
1243 ret = reg_read(priv, REG_INT_FLAGS_2);
1246 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1252 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1257 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1258 if (ret != length) {
1259 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1267 mutex_unlock(&priv->edid_mutex);
1271 static int tda998x_connector_get_modes(struct drm_connector *connector)
1273 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1278 * If we get killed while waiting for the HPD timeout, return
1279 * no modes found: we are not in a restartable path, so we
1280 * can't handle signals gracefully.
1282 if (tda998x_edid_delay_wait(priv))
1285 if (priv->rev == TDA19988)
1286 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1288 edid = drm_do_get_edid(connector, read_edid_block, priv);
1290 if (priv->rev == TDA19988)
1291 reg_set(priv, REG_TX4, TX4_PD_RAM);
1294 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1298 drm_connector_update_edid_property(connector, edid);
1299 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1301 mutex_lock(&priv->audio_mutex);
1302 n = drm_add_edid_modes(connector, edid);
1303 priv->sink_has_audio = drm_detect_monitor_audio(edid);
1304 mutex_unlock(&priv->audio_mutex);
1311 static struct drm_encoder *
1312 tda998x_connector_best_encoder(struct drm_connector *connector)
1314 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1316 return priv->bridge.encoder;
1320 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1321 .get_modes = tda998x_connector_get_modes,
1322 .best_encoder = tda998x_connector_best_encoder,
1325 static int tda998x_connector_init(struct tda998x_priv *priv,
1326 struct drm_device *drm)
1328 struct drm_connector *connector = &priv->connector;
1331 connector->interlace_allowed = 1;
1333 if (priv->hdmi->irq)
1334 connector->polled = DRM_CONNECTOR_POLL_HPD;
1336 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1337 DRM_CONNECTOR_POLL_DISCONNECT;
1339 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1340 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1341 DRM_MODE_CONNECTOR_HDMIA);
1345 drm_connector_attach_encoder(&priv->connector,
1346 priv->bridge.encoder);
1351 /* DRM bridge functions */
1353 static int tda998x_bridge_attach(struct drm_bridge *bridge)
1355 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1357 return tda998x_connector_init(priv, bridge->dev);
1360 static void tda998x_bridge_detach(struct drm_bridge *bridge)
1362 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1364 drm_connector_cleanup(&priv->connector);
1367 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1368 const struct drm_display_mode *mode)
1370 /* TDA19988 dotclock can go up to 165MHz */
1371 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1373 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1374 return MODE_CLOCK_HIGH;
1375 if (mode->htotal >= BIT(13))
1376 return MODE_BAD_HVALUE;
1377 if (mode->vtotal >= BIT(11))
1378 return MODE_BAD_VVALUE;
1382 static void tda998x_bridge_enable(struct drm_bridge *bridge)
1384 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1387 /* enable video ports, audio will be enabled later */
1388 reg_write(priv, REG_ENA_VP_0, 0xff);
1389 reg_write(priv, REG_ENA_VP_1, 0xff);
1390 reg_write(priv, REG_ENA_VP_2, 0xff);
1391 /* set muxing after enabling ports: */
1392 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1393 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1394 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1400 static void tda998x_bridge_disable(struct drm_bridge *bridge)
1402 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1405 /* disable video ports */
1406 reg_write(priv, REG_ENA_VP_0, 0x00);
1407 reg_write(priv, REG_ENA_VP_1, 0x00);
1408 reg_write(priv, REG_ENA_VP_2, 0x00);
1410 priv->is_on = false;
1414 static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1415 const struct drm_display_mode *mode,
1416 const struct drm_display_mode *adjusted_mode)
1418 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1419 unsigned long tmds_clock;
1420 u16 ref_pix, ref_line, n_pix, n_line;
1421 u16 hs_pix_s, hs_pix_e;
1422 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1423 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1424 u16 vwin1_line_s, vwin1_line_e;
1425 u16 vwin2_line_s, vwin2_line_e;
1426 u16 de_pix_s, de_pix_e;
1430 * Internally TDA998x is using ITU-R BT.656 style sync but
1431 * we get VESA style sync. TDA998x is using a reference pixel
1432 * relative to ITU to sync to the input frame and for output
1433 * sync generation. Currently, we are using reference detection
1434 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1435 * which is position of rising VS with coincident rising HS.
1437 * Now there is some issues to take care of:
1438 * - HDMI data islands require sync-before-active
1439 * - TDA998x register values must be > 0 to be enabled
1440 * - REFLINE needs an additional offset of +1
1441 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1443 * So we add +1 to all horizontal and vertical register values,
1444 * plus an additional +3 for REFPIX as we are using RGB input only.
1446 n_pix = mode->htotal;
1447 n_line = mode->vtotal;
1449 hs_pix_e = mode->hsync_end - mode->hdisplay;
1450 hs_pix_s = mode->hsync_start - mode->hdisplay;
1451 de_pix_e = mode->htotal;
1452 de_pix_s = mode->htotal - mode->hdisplay;
1453 ref_pix = 3 + hs_pix_s;
1456 * Attached LCD controllers may generate broken sync. Allow
1457 * those to adjust the position of the rising VS edge by adding
1460 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1461 ref_pix += adjusted_mode->hskew;
1463 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1464 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1465 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1466 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1467 vs1_pix_s = vs1_pix_e = hs_pix_s;
1468 vs1_line_s = mode->vsync_start - mode->vdisplay;
1469 vs1_line_e = vs1_line_s +
1470 mode->vsync_end - mode->vsync_start;
1471 vwin2_line_s = vwin2_line_e = 0;
1472 vs2_pix_s = vs2_pix_e = 0;
1473 vs2_line_s = vs2_line_e = 0;
1475 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1476 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1477 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1478 vs1_pix_s = vs1_pix_e = hs_pix_s;
1479 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1480 vs1_line_e = vs1_line_s +
1481 (mode->vsync_end - mode->vsync_start)/2;
1482 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1483 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1484 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1485 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1486 vs2_line_e = vs2_line_s +
1487 (mode->vsync_end - mode->vsync_start)/2;
1490 tmds_clock = mode->clock;
1493 * The divisor is power-of-2. The TDA9983B datasheet gives
1494 * this as ranges of Msample/s, which is 10x the TMDS clock:
1495 * 0 - 800 to 1500 Msample/s
1496 * 1 - 400 to 800 Msample/s
1497 * 2 - 200 to 400 Msample/s
1500 for (div = 0; div < 3; div++)
1501 if (80000 >> div <= tmds_clock)
1504 mutex_lock(&priv->audio_mutex);
1506 /* mute the audio FIFO: */
1507 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1509 /* set HDMI HDCP mode off: */
1510 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1511 reg_clear(priv, REG_TX33, TX33_HDMI);
1512 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1514 /* no pre-filter or interpolator: */
1515 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1516 HVF_CNTRL_0_INTPOL(0));
1517 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1518 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1519 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1520 VIP_CNTRL_4_BLC(0));
1522 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1523 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1524 PLL_SERIAL_3_SRL_DE);
1525 reg_write(priv, REG_SERIALIZER, 0);
1526 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1528 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1530 reg_write(priv, REG_RPT_CNTRL, 0);
1531 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
1532 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1534 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1535 PLL_SERIAL_2_SRL_PR(rep));
1537 /* set color matrix bypass flag: */
1538 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1539 MAT_CONTRL_MAT_SC(1));
1540 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1542 /* set BIAS tmds value: */
1543 reg_write(priv, REG_ANA_GENERAL, 0x09);
1546 * Sync on rising HSYNC/VSYNC
1548 reg = VIP_CNTRL_3_SYNC_HS;
1551 * TDA19988 requires high-active sync at input stage,
1552 * so invert low-active sync provided by master encoder here
1554 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1555 reg |= VIP_CNTRL_3_H_TGL;
1556 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1557 reg |= VIP_CNTRL_3_V_TGL;
1558 reg_write(priv, REG_VIP_CNTRL_3, reg);
1560 reg_write(priv, REG_VIDFORMAT, 0x00);
1561 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1562 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1563 reg_write16(priv, REG_NPIX_MSB, n_pix);
1564 reg_write16(priv, REG_NLINE_MSB, n_line);
1565 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1566 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1567 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1568 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1569 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1570 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1571 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1572 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1573 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1574 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1575 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1576 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1577 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1578 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1579 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1580 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1582 if (priv->rev == TDA19988) {
1583 /* let incoming pixels fill the active space (if any) */
1584 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1588 * Always generate sync polarity relative to input sync and
1589 * revert input stage toggled sync at output stage
1591 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1592 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1593 reg |= TBG_CNTRL_1_H_TGL;
1594 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1595 reg |= TBG_CNTRL_1_V_TGL;
1596 reg_write(priv, REG_TBG_CNTRL_1, reg);
1598 /* must be last register set: */
1599 reg_write(priv, REG_TBG_CNTRL_0, 0);
1601 priv->tmds_clock = adjusted_mode->clock;
1603 /* CEA-861B section 6 says that:
1604 * CEA version 1 (CEA-861) has no support for infoframes.
1605 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1606 * and optional basic audio.
1607 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1608 * and optional digital audio, with audio infoframes.
1610 * Since we only support generation of version 2 AVI infoframes,
1611 * ignore CEA version 2 and below (iow, behave as if we're a
1614 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1616 if (priv->supports_infoframes) {
1617 /* We need to turn HDMI HDCP stuff on to get audio through */
1618 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1619 reg_write(priv, REG_TBG_CNTRL_1, reg);
1620 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1621 reg_set(priv, REG_TX33, TX33_HDMI);
1623 tda998x_write_avi(priv, adjusted_mode);
1625 if (priv->sink_has_audio)
1626 tda998x_configure_audio(priv);
1629 mutex_unlock(&priv->audio_mutex);
1632 static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1633 .attach = tda998x_bridge_attach,
1634 .detach = tda998x_bridge_detach,
1635 .mode_valid = tda998x_bridge_mode_valid,
1636 .disable = tda998x_bridge_disable,
1637 .mode_set = tda998x_bridge_mode_set,
1638 .enable = tda998x_bridge_enable,
1641 /* I2C driver functions */
1643 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1644 struct device_node *np)
1646 const u32 *port_data;
1650 port_data = of_get_property(np, "audio-ports", &size);
1654 size /= sizeof(u32);
1655 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1656 dev_err(&priv->hdmi->dev,
1657 "Bad number of elements in audio-ports dt-property\n");
1663 for (i = 0; i < size; i++) {
1665 u8 afmt = be32_to_cpup(&port_data[2*i]);
1666 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1670 route = AUDIO_ROUTE_I2S;
1673 route = AUDIO_ROUTE_SPDIF;
1676 dev_err(&priv->hdmi->dev,
1677 "Bad audio format %u\n", afmt);
1681 if (priv->audio_port_enable[route]) {
1682 dev_err(&priv->hdmi->dev,
1683 "There can only be on I2S port and one SPDIF port\n");
1687 priv->audio_port_enable[route] = ena_ap;
1692 static int tda998x_set_config(struct tda998x_priv *priv,
1693 const struct tda998x_encoder_params *p)
1695 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1696 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1697 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1698 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1699 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1700 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1701 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1702 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1703 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1704 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1705 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1706 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1708 if (p->audio_params.format != AFMT_UNUSED) {
1709 unsigned int ratio, route;
1710 bool spdif = p->audio_params.format == AFMT_SPDIF;
1712 route = AUDIO_ROUTE_I2S + spdif;
1714 priv->audio.route = &tda998x_audio_route[route];
1715 priv->audio.params = p->audio_params;
1716 priv->audio.ena_ap = p->audio_params.config;
1717 priv->audio.i2s_format = I2S_FORMAT_PHILIPS;
1719 ratio = spdif ? 64 : p->audio_params.sample_width * 2;
1720 return tda998x_derive_cts_n(priv, &priv->audio, ratio);
1726 static void tda998x_destroy(struct device *dev)
1728 struct tda998x_priv *priv = dev_get_drvdata(dev);
1730 drm_bridge_remove(&priv->bridge);
1732 /* disable all IRQs and free the IRQ handler */
1733 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1734 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1736 if (priv->audio_pdev)
1737 platform_device_unregister(priv->audio_pdev);
1739 if (priv->hdmi->irq)
1740 free_irq(priv->hdmi->irq, priv);
1742 del_timer_sync(&priv->edid_delay_timer);
1743 cancel_work_sync(&priv->detect_work);
1745 i2c_unregister_device(priv->cec);
1747 if (priv->cec_notify)
1748 cec_notifier_put(priv->cec_notify);
1751 static int tda998x_create(struct device *dev)
1753 struct i2c_client *client = to_i2c_client(dev);
1754 struct device_node *np = client->dev.of_node;
1755 struct i2c_board_info cec_info;
1756 struct tda998x_priv *priv;
1758 int rev_lo, rev_hi, ret;
1760 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1764 dev_set_drvdata(dev, priv);
1766 mutex_init(&priv->mutex); /* protect the page access */
1767 mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1768 mutex_init(&priv->edid_mutex);
1769 INIT_LIST_HEAD(&priv->bridge.list);
1770 init_waitqueue_head(&priv->edid_delay_waitq);
1771 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1772 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1774 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1775 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1776 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1778 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1779 priv->cec_addr = 0x34 + (client->addr & 0x03);
1780 priv->current_page = 0xff;
1781 priv->hdmi = client;
1783 /* wake up the device: */
1784 cec_write(priv, REG_CEC_ENAMODS,
1785 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1787 tda998x_reset(priv);
1790 rev_lo = reg_read(priv, REG_VERSION_LSB);
1792 dev_err(dev, "failed to read version: %d\n", rev_lo);
1796 rev_hi = reg_read(priv, REG_VERSION_MSB);
1798 dev_err(dev, "failed to read version: %d\n", rev_hi);
1802 priv->rev = rev_lo | rev_hi << 8;
1804 /* mask off feature bits: */
1805 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1807 switch (priv->rev) {
1809 dev_info(dev, "found TDA9989 n2");
1812 dev_info(dev, "found TDA19989");
1815 dev_info(dev, "found TDA19989 n2");
1818 dev_info(dev, "found TDA19988");
1821 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1825 /* after reset, enable DDC: */
1826 reg_write(priv, REG_DDC_DISABLE, 0x00);
1828 /* set clock on DDC channel: */
1829 reg_write(priv, REG_TX3, 39);
1831 /* if necessary, disable multi-master: */
1832 if (priv->rev == TDA19989)
1833 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1835 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1836 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1838 /* ensure interrupts are disabled */
1839 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1841 /* clear pending interrupts */
1842 cec_read(priv, REG_CEC_RXSHPDINT);
1843 reg_read(priv, REG_INT_FLAGS_0);
1844 reg_read(priv, REG_INT_FLAGS_1);
1845 reg_read(priv, REG_INT_FLAGS_2);
1847 /* initialize the optional IRQ */
1849 unsigned long irq_flags;
1851 /* init read EDID waitqueue and HDP work */
1852 init_waitqueue_head(&priv->wq_edid);
1855 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1857 priv->cec_glue.irq_flags = irq_flags;
1859 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1860 ret = request_threaded_irq(client->irq, NULL,
1861 tda998x_irq_thread, irq_flags,
1864 dev_err(dev, "failed to request IRQ#%u: %d\n",
1869 /* enable HPD irq */
1870 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1873 priv->cec_notify = cec_notifier_get(dev);
1874 if (!priv->cec_notify) {
1879 priv->cec_glue.parent = dev;
1880 priv->cec_glue.data = priv;
1881 priv->cec_glue.init = tda998x_cec_hook_init;
1882 priv->cec_glue.exit = tda998x_cec_hook_exit;
1883 priv->cec_glue.open = tda998x_cec_hook_open;
1884 priv->cec_glue.release = tda998x_cec_hook_release;
1887 * Some TDA998x are actually two I2C devices merged onto one piece
1888 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1889 * with a slightly modified TDA9950 CEC device. The CEC device
1890 * is at the TDA9950 address, with the address pins strapped across
1891 * to the TDA998x address pins. Hence, it always has the same
1894 memset(&cec_info, 0, sizeof(cec_info));
1895 strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1896 cec_info.addr = priv->cec_addr;
1897 cec_info.platform_data = &priv->cec_glue;
1898 cec_info.irq = client->irq;
1900 priv->cec = i2c_new_device(client->adapter, &cec_info);
1906 /* enable EDID read irq: */
1907 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1910 /* get the device tree parameters */
1911 ret = of_property_read_u32(np, "video-ports", &video);
1913 priv->vip_cntrl_0 = video >> 16;
1914 priv->vip_cntrl_1 = video >> 8;
1915 priv->vip_cntrl_2 = video;
1918 ret = tda998x_get_audio_ports(priv, np);
1922 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1923 priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1924 tda998x_audio_codec_init(priv, &client->dev);
1925 } else if (dev->platform_data) {
1926 ret = tda998x_set_config(priv, dev->platform_data);
1931 priv->bridge.funcs = &tda998x_bridge_funcs;
1933 priv->bridge.of_node = dev->of_node;
1936 drm_bridge_add(&priv->bridge);
1941 tda998x_destroy(dev);
1946 /* DRM encoder functions */
1948 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1950 drm_encoder_cleanup(encoder);
1953 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1954 .destroy = tda998x_encoder_destroy,
1957 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
1959 struct tda998x_priv *priv = dev_get_drvdata(dev);
1964 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1966 /* If no CRTCs were found, fall back to our old behaviour */
1968 dev_warn(dev, "Falling back to first CRTC\n");
1972 priv->encoder.possible_crtcs = crtcs;
1974 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1975 DRM_MODE_ENCODER_TMDS, NULL);
1979 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL);
1986 drm_encoder_cleanup(&priv->encoder);
1991 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1993 struct drm_device *drm = data;
1995 return tda998x_encoder_init(dev, drm);
1998 static void tda998x_unbind(struct device *dev, struct device *master,
2001 struct tda998x_priv *priv = dev_get_drvdata(dev);
2003 drm_encoder_cleanup(&priv->encoder);
2006 static const struct component_ops tda998x_ops = {
2007 .bind = tda998x_bind,
2008 .unbind = tda998x_unbind,
2012 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
2016 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2017 dev_warn(&client->dev, "adapter does not support I2C\n");
2021 ret = tda998x_create(&client->dev);
2025 ret = component_add(&client->dev, &tda998x_ops);
2027 tda998x_destroy(&client->dev);
2031 static int tda998x_remove(struct i2c_client *client)
2033 component_del(&client->dev, &tda998x_ops);
2034 tda998x_destroy(&client->dev);
2039 static const struct of_device_id tda998x_dt_ids[] = {
2040 { .compatible = "nxp,tda998x", },
2043 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2046 static const struct i2c_device_id tda998x_ids[] = {
2050 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2052 static struct i2c_driver tda998x_driver = {
2053 .probe = tda998x_probe,
2054 .remove = tda998x_remove,
2057 .of_match_table = of_match_ptr(tda998x_dt_ids),
2059 .id_table = tda998x_ids,
2062 module_i2c_driver(tda998x_driver);
2064 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2065 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2066 MODULE_LICENSE("GPL");