drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/hdmi.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_data/tda9950.h>
  23 #include <linux/irq.h>
  24 #include <sound/asoundef.h>
  25 #include <sound/hdmi-codec.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_of.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/i2c/tda998x.h>
  33
  34 #include <media/cec-notifier.h>
  35
  36 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  37
  38 enum {
  39         AUDIO_ROUTE_I2S,
  40         AUDIO_ROUTE_SPDIF,
  41         AUDIO_ROUTE_NUM
  42 };
  43
  44 struct tda998x_audio_route {
  45         u8 ena_aclk;
  46         u8 mux_ap;
  47         u8 aip_clksel;
  48 };
  49
  50 struct tda998x_audio_settings {
  51         const struct tda998x_audio_route *route;
  52         struct hdmi_audio_infoframe cea;
  53         unsigned int sample_rate;
  54         u8 status[5];
  55         u8 ena_ap;
  56         u8 i2s_format;
  57         u8 cts_n;
  58 };
  59
  60 struct tda998x_priv {
  61         struct i2c_client *cec;
  62         struct i2c_client *hdmi;
  63         struct mutex mutex;
  64         u16 rev;
  65         u8 cec_addr;
  66         u8 current_page;
  67         bool is_on;
  68         bool supports_infoframes;
  69         bool sink_has_audio;
  70         enum hdmi_quantization_range rgb_quant_range;
  71         u8 vip_cntrl_0;
  72         u8 vip_cntrl_1;
  73         u8 vip_cntrl_2;
  74         unsigned long tmds_clock;
  75         struct tda998x_audio_settings audio;
  76
  77         struct platform_device *audio_pdev;
  78         struct mutex audio_mutex;
  79
  80         struct mutex edid_mutex;
  81         wait_queue_head_t wq_edid;
  82         volatile int wq_edid_wait;
  83
  84         struct work_struct detect_work;
  85         struct timer_list edid_delay_timer;
  86         wait_queue_head_t edid_delay_waitq;
  87         bool edid_delay_active;
  88
  89         struct drm_encoder encoder;
  90         struct drm_bridge bridge;
  91         struct drm_connector connector;
  92
  93         u8 audio_port_enable[AUDIO_ROUTE_NUM];
  94         struct tda9950_glue cec_glue;
  95         struct gpio_desc *calib;
  96         struct cec_notifier *cec_notify;
  97 };
  98
  99 #define conn_to_tda998x_priv(x) \
 100         container_of(x, struct tda998x_priv, connector)
 101 #define enc_to_tda998x_priv(x) \
 102         container_of(x, struct tda998x_priv, encoder)
 103 #define bridge_to_tda998x_priv(x) \
 104         container_of(x, struct tda998x_priv, bridge)
 105
 106 /* The TDA9988 series of devices use a paged register scheme.. to simplify
 107  * things we encode the page # in upper bits of the register #.  To read/
 108  * write a given register, we need to make sure CURPAGE register is set
 109  * appropriately.  Which implies reads/writes are not atomic.  Fun!
 110  */
 111
 112 #define REG(page, addr) (((page) << 8) | (addr))
 113 #define REG2ADDR(reg)   ((reg) & 0xff)
 114 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
 115
 116 #define REG_CURPAGE               0xff                /* write */
 117
 118
 119 /* Page 00h: General Control */
 120 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
 121 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
 122 # define MAIN_CNTRL0_SR           (1 << 0)
 123 # define MAIN_CNTRL0_DECS         (1 << 1)
 124 # define MAIN_CNTRL0_DEHS         (1 << 2)
 125 # define MAIN_CNTRL0_CECS         (1 << 3)
 126 # define MAIN_CNTRL0_CEHS         (1 << 4)
 127 # define MAIN_CNTRL0_SCALER       (1 << 7)
 128 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
 129 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
 130 # define SOFTRESET_AUDIO          (1 << 0)
 131 # define SOFTRESET_I2C_MASTER     (1 << 1)
 132 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
 133 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
 134 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
 135 # define I2C_MASTER_DIS_MM        (1 << 0)
 136 # define I2C_MASTER_DIS_FILT      (1 << 1)
 137 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
 138 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
 139 # define FEAT_POWERDOWN_PREFILT   BIT(0)
 140 # define FEAT_POWERDOWN_CSC       BIT(1)
 141 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
 142 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 143 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 144 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 145 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
 146 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 147 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 148 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 149 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 150 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 151 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 152 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 153 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 154 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 155 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 156 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 157 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 158 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 159 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 160 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 161 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 162 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 163 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 164 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 165 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 166 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 167 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 168 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 169 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 170 # define VIP_CNTRL_3_EMB          (1 << 3)
 171 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 172 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 173 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 174 # define VIP_CNTRL_3_EDGE         (1 << 7)
 175 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 176 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 177 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 178 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 179 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 180 # define VIP_CNTRL_4_TST_656      (1 << 6)
 181 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 182 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 183 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 184 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 185 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 186 # define MUX_AP_SELECT_I2S        0x64
 187 # define MUX_AP_SELECT_SPDIF      0x40
 188 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 189 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 190 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 191 # define MAT_CONTRL_MAT_BP        (1 << 2)
 192 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 193 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 194 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 195 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 196 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 197 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 198 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 199 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 200 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 201 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 202 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 203 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 204 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 205 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 206 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 207 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 208 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 209 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 210 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 211 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 212 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 213 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 214 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 215 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 216 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 217 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 218 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 219 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 220 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 221 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 222 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 223 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 224 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 225 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 226 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 227 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 228 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 229 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 230 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 231 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 232 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 233 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 234 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 235 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 236 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 237 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 238 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 239 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 240 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 241 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 242 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 243 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 244 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 245 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 246 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 247 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 248 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 249 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 250 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 251 # define HVF_CNTRL_0_SM           (1 << 7)
 252 # define HVF_CNTRL_0_RWB          (1 << 6)
 253 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 254 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 255 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 256 # define HVF_CNTRL_1_FOR          (1 << 0)
 257 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 258 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 259 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 260 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 261 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 262 # define RPT_CNTRL_REPEAT(x)      ((x) & 15)
 263 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 264 # define I2S_FORMAT_PHILIPS       (0 << 0)
 265 # define I2S_FORMAT_LEFT_J        (2 << 0)
 266 # define I2S_FORMAT_RIGHT_J       (3 << 0)
 267 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 268 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 269 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 270 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 271 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 272 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 273
 274 /* Page 02h: PLL settings */
 275 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 276 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 277 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 278 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 279 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 280 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 281 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 282 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 283 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 284 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 285 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 286 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 287 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 288 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 289 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 290 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 291 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 292 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 293 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 294 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 295 # define AUDIO_DIV_SERCLK_1       0
 296 # define AUDIO_DIV_SERCLK_2       1
 297 # define AUDIO_DIV_SERCLK_4       2
 298 # define AUDIO_DIV_SERCLK_8       3
 299 # define AUDIO_DIV_SERCLK_16      4
 300 # define AUDIO_DIV_SERCLK_32      5
 301 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 302 # define SEL_CLK_SEL_CLK1         (1 << 0)
 303 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 304 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 305 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 306
 307
 308 /* Page 09h: EDID Control */
 309 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 310 /* next 127 successive registers are the EDID block */
 311 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 312 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 313 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 314 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 315 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 316
 317
 318 /* Page 10h: information frames and packets */
 319 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 320 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 321 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 322 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 323 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 324
 325
 326 /* Page 11h: audio settings and content info packets */
 327 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 328 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 329 # define AIP_CNTRL_0_SWAP         (1 << 1)
 330 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 331 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 332 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 333 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 334 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 335 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 336 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 337 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 338 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 339 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 340 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 341 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 342 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 343 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 344 # define CTS_N_K(x)               (((x) & 7) << 0)
 345 # define CTS_N_M(x)               (((x) & 3) << 4)
 346 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 347 # define ENC_CNTRL_RST_ENC        (1 << 0)
 348 # define ENC_CNTRL_RST_SEL        (1 << 1)
 349 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 350 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 351 # define DIP_FLAGS_ACR            (1 << 0)
 352 # define DIP_FLAGS_GC             (1 << 1)
 353 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 354 # define DIP_IF_FLAGS_IF1         (1 << 1)
 355 # define DIP_IF_FLAGS_IF2         (1 << 2)
 356 # define DIP_IF_FLAGS_IF3         (1 << 3)
 357 # define DIP_IF_FLAGS_IF4         (1 << 4)
 358 # define DIP_IF_FLAGS_IF5         (1 << 5)
 359 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 360
 361
 362 /* Page 12h: HDCP and OTP */
 363 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 364 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 365 # define TX4_PD_RAM               (1 << 1)
 366 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 367 # define TX33_HDMI                (1 << 1)
 368
 369
 370 /* Page 13h: Gamut related metadata packets */
 371
 372
 373
 374 /* CEC registers: (not paged)
 375  */
 376 #define REG_CEC_INTSTATUS         0xee                /* read */
 377 # define CEC_INTSTATUS_CEC        (1 << 0)
 378 # define CEC_INTSTATUS_HDMI       (1 << 1)
 379 #define REG_CEC_CAL_XOSC_CTRL1    0xf2
 380 # define CEC_CAL_XOSC_CTRL1_ENA_CAL     BIT(0)
 381 #define REG_CEC_DES_FREQ2         0xf5
 382 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
 383 #define REG_CEC_CLK               0xf6
 384 # define CEC_CLK_FRO              0x11
 385 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 386 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 387 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 388 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 389 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 390 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 391 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 392 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 393 # define CEC_RXSHPDINT_HPD        BIT(1)
 394 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 395 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 396 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 397
 398 #define REG_CEC_ENAMODS           0xff                /* read/write */
 399 # define CEC_ENAMODS_EN_CEC_CLK   (1 << 7)
 400 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 401 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 402 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 403 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 404 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 405
 406
 407 /* Device versions: */
 408 #define TDA9989N2                 0x0101
 409 #define TDA19989                  0x0201
 410 #define TDA19989N2                0x0202
 411 #define TDA19988                  0x0301
 412
 413 static void
 414 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 415 {
 416         u8 buf[] = {addr, val};
 417         struct i2c_msg msg = {
 418                 .addr = priv->cec_addr,
 419                 .len = 2,
 420                 .buf = buf,
 421         };
 422         int ret;
 423
 424         ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
 425         if (ret < 0)
 426                 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
 427                         ret, addr);
 428 }
 429
 430 static u8
 431 cec_read(struct tda998x_priv *priv, u8 addr)
 432 {
 433         u8 val;
 434         struct i2c_msg msg[2] = {
 435                 {
 436                         .addr = priv->cec_addr,
 437                         .len = 1,
 438                         .buf = &addr,
 439                 }, {
 440                         .addr = priv->cec_addr,
 441                         .flags = I2C_M_RD,
 442                         .len = 1,
 443                         .buf = &val,
 444                 },
 445         };
 446         int ret;
 447
 448         ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
 449         if (ret < 0) {
 450                 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
 451                         ret, addr);
 452                 val = 0;
 453         }
 454
 455         return val;
 456 }
 457
 458 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
 459 {
 460         int val = cec_read(priv, REG_CEC_ENAMODS);
 461
 462         if (val < 0)
 463                 return;
 464
 465         if (enable)
 466                 val |= mods;
 467         else
 468                 val &= ~mods;
 469
 470         cec_write(priv, REG_CEC_ENAMODS, val);
 471 }
 472
 473 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
 474 {
 475         if (enable) {
 476                 u8 val;
 477
 478                 cec_write(priv, 0xf3, 0xc0);
 479                 cec_write(priv, 0xf4, 0xd4);
 480
 481                 /* Enable automatic calibration mode */
 482                 val = cec_read(priv, REG_CEC_DES_FREQ2);
 483                 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
 484                 cec_write(priv, REG_CEC_DES_FREQ2, val);
 485
 486                 /* Enable free running oscillator */
 487                 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
 488                 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
 489
 490                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
 491                           CEC_CAL_XOSC_CTRL1_ENA_CAL);
 492         } else {
 493                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
 494         }
 495 }
 496
 497 /*
 498  * Calibration for the internal oscillator: we need to set calibration mode,
 499  * and then pulse the IRQ line low for a 10ms ± 1% period.
 500  */
 501 static void tda998x_cec_calibration(struct tda998x_priv *priv)
 502 {
 503         struct gpio_desc *calib = priv->calib;
 504
 505         mutex_lock(&priv->edid_mutex);
 506         if (priv->hdmi->irq > 0)
 507                 disable_irq(priv->hdmi->irq);
 508         gpiod_direction_output(calib, 1);
 509         tda998x_cec_set_calibration(priv, true);
 510
 511         local_irq_disable();
 512         gpiod_set_value(calib, 0);
 513         mdelay(10);
 514         gpiod_set_value(calib, 1);
 515         local_irq_enable();
 516
 517         tda998x_cec_set_calibration(priv, false);
 518         gpiod_direction_input(calib);
 519         if (priv->hdmi->irq > 0)
 520                 enable_irq(priv->hdmi->irq);
 521         mutex_unlock(&priv->edid_mutex);
 522 }
 523
 524 static int tda998x_cec_hook_init(void *data)
 525 {
 526         struct tda998x_priv *priv = data;
 527         struct gpio_desc *calib;
 528
 529         calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
 530         if (IS_ERR(calib)) {
 531                 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
 532                          PTR_ERR(calib));
 533                 return PTR_ERR(calib);
 534         }
 535
 536         priv->calib = calib;
 537
 538         return 0;
 539 }
 540
 541 static void tda998x_cec_hook_exit(void *data)
 542 {
 543         struct tda998x_priv *priv = data;
 544
 545         gpiod_put(priv->calib);
 546         priv->calib = NULL;
 547 }
 548
 549 static int tda998x_cec_hook_open(void *data)
 550 {
 551         struct tda998x_priv *priv = data;
 552
 553         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
 554         tda998x_cec_calibration(priv);
 555
 556         return 0;
 557 }
 558
 559 static void tda998x_cec_hook_release(void *data)
 560 {
 561         struct tda998x_priv *priv = data;
 562
 563         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
 564 }
 565
 566 static int
 567 set_page(struct tda998x_priv *priv, u16 reg)
 568 {
 569         if (REG2PAGE(reg) != priv->current_page) {
 570                 struct i2c_client *client = priv->hdmi;
 571                 u8 buf[] = {
 572                                 REG_CURPAGE, REG2PAGE(reg)
 573                 };
 574                 int ret = i2c_master_send(client, buf, sizeof(buf));
 575                 if (ret < 0) {
 576                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 577                                         reg, ret);
 578                         return ret;
 579                 }
 580
 581                 priv->current_page = REG2PAGE(reg);
 582         }
 583         return 0;
 584 }
 585
 586 static int
 587 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 588 {
 589         struct i2c_client *client = priv->hdmi;
 590         u8 addr = REG2ADDR(reg);
 591         int ret;
 592
 593         mutex_lock(&priv->mutex);
 594         ret = set_page(priv, reg);
 595         if (ret < 0)
 596                 goto out;
 597
 598         ret = i2c_master_send(client, &addr, sizeof(addr));
 599         if (ret < 0)
 600                 goto fail;
 601
 602         ret = i2c_master_recv(client, buf, cnt);
 603         if (ret < 0)
 604                 goto fail;
 605
 606         goto out;
 607
 608 fail:
 609         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 610 out:
 611         mutex_unlock(&priv->mutex);
 612         return ret;
 613 }
 614
 615 #define MAX_WRITE_RANGE_BUF 32
 616
 617 static void
 618 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 619 {
 620         struct i2c_client *client = priv->hdmi;
 621         /* This is the maximum size of the buffer passed in */
 622         u8 buf[MAX_WRITE_RANGE_BUF + 1];
 623         int ret;
 624
 625         if (cnt > MAX_WRITE_RANGE_BUF) {
 626                 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
 627                                 MAX_WRITE_RANGE_BUF);
 628                 return;
 629         }
 630
 631         buf[0] = REG2ADDR(reg);
 632         memcpy(&buf[1], p, cnt);
 633
 634         mutex_lock(&priv->mutex);
 635         ret = set_page(priv, reg);
 636         if (ret < 0)
 637                 goto out;
 638
 639         ret = i2c_master_send(client, buf, cnt + 1);
 640         if (ret < 0)
 641                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 642 out:
 643         mutex_unlock(&priv->mutex);
 644 }
 645
 646 static int
 647 reg_read(struct tda998x_priv *priv, u16 reg)
 648 {
 649         u8 val = 0;
 650         int ret;
 651
 652         ret = reg_read_range(priv, reg, &val, sizeof(val));
 653         if (ret < 0)
 654                 return ret;
 655         return val;
 656 }
 657
 658 static void
 659 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 660 {
 661         struct i2c_client *client = priv->hdmi;
 662         u8 buf[] = {REG2ADDR(reg), val};
 663         int ret;
 664
 665         mutex_lock(&priv->mutex);
 666         ret = set_page(priv, reg);
 667         if (ret < 0)
 668                 goto out;
 669
 670         ret = i2c_master_send(client, buf, sizeof(buf));
 671         if (ret < 0)
 672                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 673 out:
 674         mutex_unlock(&priv->mutex);
 675 }
 676
 677 static void
 678 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 679 {
 680         struct i2c_client *client = priv->hdmi;
 681         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 682         int ret;
 683
 684         mutex_lock(&priv->mutex);
 685         ret = set_page(priv, reg);
 686         if (ret < 0)
 687                 goto out;
 688
 689         ret = i2c_master_send(client, buf, sizeof(buf));
 690         if (ret < 0)
 691                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 692 out:
 693         mutex_unlock(&priv->mutex);
 694 }
 695
 696 static void
 697 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 698 {
 699         int old_val;
 700
 701         old_val = reg_read(priv, reg);
 702         if (old_val >= 0)
 703                 reg_write(priv, reg, old_val | val);
 704 }
 705
 706 static void
 707 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 708 {
 709         int old_val;
 710
 711         old_val = reg_read(priv, reg);
 712         if (old_val >= 0)
 713                 reg_write(priv, reg, old_val & ~val);
 714 }
 715
 716 static void
 717 tda998x_reset(struct tda998x_priv *priv)
 718 {
 719         /* reset audio and i2c master: */
 720         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 721         msleep(50);
 722         reg_write(priv, REG_SOFTRESET, 0);
 723         msleep(50);
 724
 725         /* reset transmitter: */
 726         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 727         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 728
 729         /* PLL registers common configuration */
 730         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 731         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 732         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 733         reg_write(priv, REG_SERIALIZER,   0x00);
 734         reg_write(priv, REG_BUFFER_OUT,   0x00);
 735         reg_write(priv, REG_PLL_SCG1,     0x00);
 736         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 737         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 738         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 739         reg_write(priv, REG_PLL_SCGN2,    0x00);
 740         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 741         reg_write(priv, REG_PLL_SCGR2,    0x00);
 742         reg_write(priv, REG_PLL_SCG2,     0x10);
 743
 744         /* Write the default value MUX register */
 745         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 746 }
 747
 748 /*
 749  * The TDA998x has a problem when trying to read the EDID close to a
 750  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 751  * trying to read EDID data.
 752  *
 753  * However, tda998x_connector_get_modes() may be called at any moment
 754  * after tda998x_connector_detect() indicates that we are connected, so
 755  * we need to delay probing modes in tda998x_connector_get_modes() after
 756  * we have seen a HPD inactive->active transition.  This code implements
 757  * that delay.
 758  */
 759 static void tda998x_edid_delay_done(struct timer_list *t)
 760 {
 761         struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
 762
 763         priv->edid_delay_active = false;
 764         wake_up(&priv->edid_delay_waitq);
 765         schedule_work(&priv->detect_work);
 766 }
 767
 768 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 769 {
 770         priv->edid_delay_active = true;
 771         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 772 }
 773
 774 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 775 {
 776         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 777 }
 778
 779 /*
 780  * We need to run the KMS hotplug event helper outside of our threaded
 781  * interrupt routine as this can call back into our get_modes method,
 782  * which will want to make use of interrupts.
 783  */
 784 static void tda998x_detect_work(struct work_struct *work)
 785 {
 786         struct tda998x_priv *priv =
 787                 container_of(work, struct tda998x_priv, detect_work);
 788         struct drm_device *dev = priv->connector.dev;
 789
 790         if (dev)
 791                 drm_kms_helper_hotplug_event(dev);
 792 }
 793
 794 /*
 795  * only 2 interrupts may occur: screen plug/unplug and EDID read
 796  */
 797 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 798 {
 799         struct tda998x_priv *priv = data;
 800         u8 sta, cec, lvl, flag0, flag1, flag2;
 801         bool handled = false;
 802
 803         sta = cec_read(priv, REG_CEC_INTSTATUS);
 804         if (sta & CEC_INTSTATUS_HDMI) {
 805                 cec = cec_read(priv, REG_CEC_RXSHPDINT);
 806                 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 807                 flag0 = reg_read(priv, REG_INT_FLAGS_0);
 808                 flag1 = reg_read(priv, REG_INT_FLAGS_1);
 809                 flag2 = reg_read(priv, REG_INT_FLAGS_2);
 810                 DRM_DEBUG_DRIVER(
 811                         "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 812                         sta, cec, lvl, flag0, flag1, flag2);
 813
 814                 if (cec & CEC_RXSHPDINT_HPD) {
 815                         if (lvl & CEC_RXSHPDLEV_HPD) {
 816                                 tda998x_edid_delay_start(priv);
 817                         } else {
 818                                 schedule_work(&priv->detect_work);
 819                                 cec_notifier_set_phys_addr(priv->cec_notify,
 820                                                    CEC_PHYS_ADDR_INVALID);
 821                         }
 822
 823                         handled = true;
 824                 }
 825
 826                 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 827                         priv->wq_edid_wait = 0;
 828                         wake_up(&priv->wq_edid);
 829                         handled = true;
 830                 }
 831         }
 832
 833         return IRQ_RETVAL(handled);
 834 }
 835
 836 static void
 837 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 838                  union hdmi_infoframe *frame)
 839 {
 840         u8 buf[MAX_WRITE_RANGE_BUF];
 841         ssize_t len;
 842
 843         len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 844         if (len < 0) {
 845                 dev_err(&priv->hdmi->dev,
 846                         "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 847                         frame->any.type, len);
 848                 return;
 849         }
 850
 851         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 852         reg_write_range(priv, addr, buf, len);
 853         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 854 }
 855
 856 static void tda998x_write_aif(struct tda998x_priv *priv,
 857                               const struct hdmi_audio_infoframe *cea)
 858 {
 859         union hdmi_infoframe frame;
 860
 861         frame.audio = *cea;
 862
 863         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 864 }
 865
 866 static void
 867 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
 868 {
 869         union hdmi_infoframe frame;
 870
 871         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 872                                                  &priv->connector, mode);
 873         frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 874         drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode,
 875                                            priv->rgb_quant_range);
 876
 877         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 878 }
 879
 880 static void tda998x_write_vsi(struct tda998x_priv *priv,
 881                               const struct drm_display_mode *mode)
 882 {
 883         union hdmi_infoframe frame;
 884
 885         if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 886                                                         &priv->connector,
 887                                                         mode))
 888                 reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
 889         else
 890                 tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame);
 891 }
 892
 893 /* Audio support */
 894
 895 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
 896         [AUDIO_ROUTE_I2S] = {
 897                 .ena_aclk = 1,
 898                 .mux_ap = MUX_AP_SELECT_I2S,
 899                 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
 900         },
 901         [AUDIO_ROUTE_SPDIF] = {
 902                 .ena_aclk = 0,
 903                 .mux_ap = MUX_AP_SELECT_SPDIF,
 904                 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
 905         },
 906 };
 907
 908 /* Configure the TDA998x audio data and clock routing. */
 909 static int tda998x_derive_routing(struct tda998x_priv *priv,
 910                                   struct tda998x_audio_settings *s,
 911                                   unsigned int route)
 912 {
 913         s->route = &tda998x_audio_route[route];
 914         s->ena_ap = priv->audio_port_enable[route];
 915         if (s->ena_ap == 0) {
 916                 dev_err(&priv->hdmi->dev, "no audio configuration found\n");
 917                 return -EINVAL;
 918         }
 919
 920         return 0;
 921 }
 922
 923 /*
 924  * The audio clock divisor register controls a divider producing Audio_Clk_Out
 925  * from SERclk by dividing it by 2^n where 0 <= n <= 5.  We don't know what
 926  * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
 927  *
 928  * It seems that Audio_Clk_Out must be the smallest value that is greater
 929  * than 128*fs, otherwise audio does not function. There is some suggestion
 930  * that 126*fs is a better value.
 931  */
 932 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
 933 {
 934         unsigned long min_audio_clk = fs * 128;
 935         unsigned long ser_clk = priv->tmds_clock * 1000;
 936         u8 adiv;
 937
 938         for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
 939                 if (ser_clk > min_audio_clk << adiv)
 940                         break;
 941
 942         dev_dbg(&priv->hdmi->dev,
 943                 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
 944                 ser_clk, fs, min_audio_clk, adiv);
 945
 946         return adiv;
 947 }
 948
 949 /*
 950  * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
 951  * generate the CTS value.  It appears that the "measured time stamp" is
 952  * the number of TDMS clock cycles within a number of audio input clock
 953  * cycles defined by the k and N parameters defined below, in a similar
 954  * way to that which is set out in the CTS generation in the HDMI spec.
 955  *
 956  *  tmdsclk ----> mts -> /m ---> CTS
 957  *                 ^
 958  *  sclk -> /k -> /N
 959  *
 960  * CTS = mts / m, where m is 2^M.
 961  * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
 962  * /N is a divider based on the HDMI specified N value.
 963  *
 964  * This produces the following equation:
 965  *  CTS = tmds_clock * k * N / (sclk * m)
 966  *
 967  * When combined with the sink-side equation, and realising that sclk is
 968  * bclk_ratio * fs, we end up with:
 969  *  k = m * bclk_ratio / 128.
 970  *
 971  * Note: S/PDIF always uses a bclk_ratio of 64.
 972  */
 973 static int tda998x_derive_cts_n(struct tda998x_priv *priv,
 974                                 struct tda998x_audio_settings *settings,
 975                                 unsigned int ratio)
 976 {
 977         switch (ratio) {
 978         case 16:
 979                 settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
 980                 break;
 981         case 32:
 982                 settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
 983                 break;
 984         case 48:
 985                 settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
 986                 break;
 987         case 64:
 988                 settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
 989                 break;
 990         case 128:
 991                 settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
 992                 break;
 993         default:
 994                 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
 995                         ratio);
 996                 return -EINVAL;
 997         }
 998         return 0;
 999 }
1000
1001 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
1002 {
1003         if (on) {
1004                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
1005                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
1006                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1007         } else {
1008                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1009         }
1010 }
1011
1012 static void tda998x_configure_audio(struct tda998x_priv *priv)
1013 {
1014         const struct tda998x_audio_settings *settings = &priv->audio;
1015         u8 buf[6], adiv;
1016         u32 n;
1017
1018         /* If audio is not configured, there is nothing to do. */
1019         if (settings->ena_ap == 0)
1020                 return;
1021
1022         adiv = tda998x_get_adiv(priv, settings->sample_rate);
1023
1024         /* Enable audio ports */
1025         reg_write(priv, REG_ENA_AP, settings->ena_ap);
1026         reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1027         reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1028         reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1029         reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1030         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1031                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
1032         reg_write(priv, REG_CTS_N, settings->cts_n);
1033         reg_write(priv, REG_AUDIO_DIV, adiv);
1034
1035         /*
1036          * This is the approximate value of N, which happens to be
1037          * the recommended values for non-coherent clocks.
1038          */
1039         n = 128 * settings->sample_rate / 1000;
1040
1041         /* Write the CTS and N values */
1042         buf[0] = 0x44;
1043         buf[1] = 0x42;
1044         buf[2] = 0x01;
1045         buf[3] = n;
1046         buf[4] = n >> 8;
1047         buf[5] = n >> 16;
1048         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1049
1050         /* Reset CTS generator */
1051         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1052         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1053
1054         /* Write the channel status
1055          * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1056          * there is a separate register for each I2S wire.
1057          */
1058         buf[0] = settings->status[0];
1059         buf[1] = settings->status[1];
1060         buf[2] = settings->status[3];
1061         buf[3] = settings->status[4];
1062         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1063
1064         tda998x_audio_mute(priv, true);
1065         msleep(20);
1066         tda998x_audio_mute(priv, false);
1067
1068         tda998x_write_aif(priv, &settings->cea);
1069 }
1070
1071 static int tda998x_audio_hw_params(struct device *dev, void *data,
1072                                    struct hdmi_codec_daifmt *daifmt,
1073                                    struct hdmi_codec_params *params)
1074 {
1075         struct tda998x_priv *priv = dev_get_drvdata(dev);
1076         unsigned int bclk_ratio;
1077         bool spdif = daifmt->fmt == HDMI_SPDIF;
1078         int ret;
1079         struct tda998x_audio_settings audio = {
1080                 .sample_rate = params->sample_rate,
1081                 .cea = params->cea,
1082         };
1083
1084         memcpy(audio.status, params->iec.status,
1085                min(sizeof(audio.status), sizeof(params->iec.status)));
1086
1087         switch (daifmt->fmt) {
1088         case HDMI_I2S:
1089                 audio.i2s_format = I2S_FORMAT_PHILIPS;
1090                 break;
1091         case HDMI_LEFT_J:
1092                 audio.i2s_format = I2S_FORMAT_LEFT_J;
1093                 break;
1094         case HDMI_RIGHT_J:
1095                 audio.i2s_format = I2S_FORMAT_RIGHT_J;
1096                 break;
1097         case HDMI_SPDIF:
1098                 audio.i2s_format = 0;
1099                 break;
1100         default:
1101                 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1102                 return -EINVAL;
1103         }
1104
1105         if (!spdif &&
1106             (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1107              daifmt->bit_clk_master || daifmt->frame_clk_master)) {
1108                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1109                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1110                         daifmt->bit_clk_master,
1111                         daifmt->frame_clk_master);
1112                 return -EINVAL;
1113         }
1114
1115         ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1116         if (ret < 0)
1117                 return ret;
1118
1119         bclk_ratio = spdif ? 64 : params->sample_width * 2;
1120         ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1121         if (ret < 0)
1122                 return ret;
1123
1124         mutex_lock(&priv->audio_mutex);
1125         priv->audio = audio;
1126         if (priv->supports_infoframes && priv->sink_has_audio)
1127                 tda998x_configure_audio(priv);
1128         mutex_unlock(&priv->audio_mutex);
1129
1130         return 0;
1131 }
1132
1133 static void tda998x_audio_shutdown(struct device *dev, void *data)
1134 {
1135         struct tda998x_priv *priv = dev_get_drvdata(dev);
1136
1137         mutex_lock(&priv->audio_mutex);
1138
1139         reg_write(priv, REG_ENA_AP, 0);
1140         priv->audio.ena_ap = 0;
1141
1142         mutex_unlock(&priv->audio_mutex);
1143 }
1144
1145 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1146 {
1147         struct tda998x_priv *priv = dev_get_drvdata(dev);
1148
1149         mutex_lock(&priv->audio_mutex);
1150
1151         tda998x_audio_mute(priv, enable);
1152
1153         mutex_unlock(&priv->audio_mutex);
1154         return 0;
1155 }
1156
1157 static int tda998x_audio_get_eld(struct device *dev, void *data,
1158                                  uint8_t *buf, size_t len)
1159 {
1160         struct tda998x_priv *priv = dev_get_drvdata(dev);
1161
1162         mutex_lock(&priv->audio_mutex);
1163         memcpy(buf, priv->connector.eld,
1164                min(sizeof(priv->connector.eld), len));
1165         mutex_unlock(&priv->audio_mutex);
1166
1167         return 0;
1168 }
1169
1170 static const struct hdmi_codec_ops audio_codec_ops = {
1171         .hw_params = tda998x_audio_hw_params,
1172         .audio_shutdown = tda998x_audio_shutdown,
1173         .digital_mute = tda998x_audio_digital_mute,
1174         .get_eld = tda998x_audio_get_eld,
1175 };
1176
1177 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1178                                     struct device *dev)
1179 {
1180         struct hdmi_codec_pdata codec_data = {
1181                 .ops = &audio_codec_ops,
1182                 .max_i2s_channels = 2,
1183         };
1184
1185         if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1186                 codec_data.i2s = 1;
1187         if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1188                 codec_data.spdif = 1;
1189
1190         priv->audio_pdev = platform_device_register_data(
1191                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1192                 &codec_data, sizeof(codec_data));
1193
1194         return PTR_ERR_OR_ZERO(priv->audio_pdev);
1195 }
1196
1197 /* DRM connector functions */
1198
1199 static enum drm_connector_status
1200 tda998x_connector_detect(struct drm_connector *connector, bool force)
1201 {
1202         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1203         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1204
1205         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1206                         connector_status_disconnected;
1207 }
1208
1209 static void tda998x_connector_destroy(struct drm_connector *connector)
1210 {
1211         drm_connector_cleanup(connector);
1212 }
1213
1214 static const struct drm_connector_funcs tda998x_connector_funcs = {
1215         .reset = drm_atomic_helper_connector_reset,
1216         .fill_modes = drm_helper_probe_single_connector_modes,
1217         .detect = tda998x_connector_detect,
1218         .destroy = tda998x_connector_destroy,
1219         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1220         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1221 };
1222
1223 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1224 {
1225         struct tda998x_priv *priv = data;
1226         u8 offset, segptr;
1227         int ret, i;
1228
1229         offset = (blk & 1) ? 128 : 0;
1230         segptr = blk / 2;
1231
1232         mutex_lock(&priv->edid_mutex);
1233
1234         reg_write(priv, REG_DDC_ADDR, 0xa0);
1235         reg_write(priv, REG_DDC_OFFS, offset);
1236         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1237         reg_write(priv, REG_DDC_SEGM, segptr);
1238
1239         /* enable reading EDID: */
1240         priv->wq_edid_wait = 1;
1241         reg_write(priv, REG_EDID_CTRL, 0x1);
1242
1243         /* flag must be cleared by sw: */
1244         reg_write(priv, REG_EDID_CTRL, 0x0);
1245
1246         /* wait for block read to complete: */
1247         if (priv->hdmi->irq) {
1248                 i = wait_event_timeout(priv->wq_edid,
1249                                         !priv->wq_edid_wait,
1250                                         msecs_to_jiffies(100));
1251                 if (i < 0) {
1252                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1253                         ret = i;
1254                         goto failed;
1255                 }
1256         } else {
1257                 for (i = 100; i > 0; i--) {
1258                         msleep(1);
1259                         ret = reg_read(priv, REG_INT_FLAGS_2);
1260                         if (ret < 0)
1261                                 goto failed;
1262                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1263                                 break;
1264                 }
1265         }
1266
1267         if (i == 0) {
1268                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1269                 ret = -ETIMEDOUT;
1270                 goto failed;
1271         }
1272
1273         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1274         if (ret != length) {
1275                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1276                         blk, ret);
1277                 goto failed;
1278         }
1279
1280         ret = 0;
1281
1282  failed:
1283         mutex_unlock(&priv->edid_mutex);
1284         return ret;
1285 }
1286
1287 static int tda998x_connector_get_modes(struct drm_connector *connector)
1288 {
1289         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1290         struct edid *edid;
1291         int n;
1292
1293         /*
1294          * If we get killed while waiting for the HPD timeout, return
1295          * no modes found: we are not in a restartable path, so we
1296          * can't handle signals gracefully.
1297          */
1298         if (tda998x_edid_delay_wait(priv))
1299                 return 0;
1300
1301         if (priv->rev == TDA19988)
1302                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1303
1304         edid = drm_do_get_edid(connector, read_edid_block, priv);
1305
1306         if (priv->rev == TDA19988)
1307                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1308
1309         if (!edid) {
1310                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1311                 return 0;
1312         }
1313
1314         drm_connector_update_edid_property(connector, edid);
1315         cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1316
1317         mutex_lock(&priv->audio_mutex);
1318         n = drm_add_edid_modes(connector, edid);
1319         priv->sink_has_audio = drm_detect_monitor_audio(edid);
1320         mutex_unlock(&priv->audio_mutex);
1321
1322         kfree(edid);
1323
1324         return n;
1325 }
1326
1327 static struct drm_encoder *
1328 tda998x_connector_best_encoder(struct drm_connector *connector)
1329 {
1330         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1331
1332         return priv->bridge.encoder;
1333 }
1334
1335 static
1336 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1337         .get_modes = tda998x_connector_get_modes,
1338         .best_encoder = tda998x_connector_best_encoder,
1339 };
1340
1341 static int tda998x_connector_init(struct tda998x_priv *priv,
1342                                   struct drm_device *drm)
1343 {
1344         struct drm_connector *connector = &priv->connector;
1345         int ret;
1346
1347         connector->interlace_allowed = 1;
1348
1349         if (priv->hdmi->irq)
1350                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1351         else
1352                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1353                         DRM_CONNECTOR_POLL_DISCONNECT;
1354
1355         drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1356         ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1357                                  DRM_MODE_CONNECTOR_HDMIA);
1358         if (ret)
1359                 return ret;
1360
1361         drm_connector_attach_encoder(&priv->connector,
1362                                      priv->bridge.encoder);
1363
1364         return 0;
1365 }
1366
1367 /* DRM bridge functions */
1368
1369 static int tda998x_bridge_attach(struct drm_bridge *bridge)
1370 {
1371         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1372
1373         return tda998x_connector_init(priv, bridge->dev);
1374 }
1375
1376 static void tda998x_bridge_detach(struct drm_bridge *bridge)
1377 {
1378         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1379
1380         drm_connector_cleanup(&priv->connector);
1381 }
1382
1383 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1384                                      const struct drm_display_mode *mode)
1385 {
1386         /* TDA19988 dotclock can go up to 165MHz */
1387         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1388
1389         if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1390                 return MODE_CLOCK_HIGH;
1391         if (mode->htotal >= BIT(13))
1392                 return MODE_BAD_HVALUE;
1393         if (mode->vtotal >= BIT(11))
1394                 return MODE_BAD_VVALUE;
1395         return MODE_OK;
1396 }
1397
1398 static void tda998x_bridge_enable(struct drm_bridge *bridge)
1399 {
1400         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1401
1402         if (!priv->is_on) {
1403                 /* enable video ports, audio will be enabled later */
1404                 reg_write(priv, REG_ENA_VP_0, 0xff);
1405                 reg_write(priv, REG_ENA_VP_1, 0xff);
1406                 reg_write(priv, REG_ENA_VP_2, 0xff);
1407                 /* set muxing after enabling ports: */
1408                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1409                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1410                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1411
1412                 priv->is_on = true;
1413         }
1414 }
1415
1416 static void tda998x_bridge_disable(struct drm_bridge *bridge)
1417 {
1418         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1419
1420         if (priv->is_on) {
1421                 /* disable video ports */
1422                 reg_write(priv, REG_ENA_VP_0, 0x00);
1423                 reg_write(priv, REG_ENA_VP_1, 0x00);
1424                 reg_write(priv, REG_ENA_VP_2, 0x00);
1425
1426                 priv->is_on = false;
1427         }
1428 }
1429
1430 static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1431                                     const struct drm_display_mode *mode,
1432                                     const struct drm_display_mode *adjusted_mode)
1433 {
1434         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1435         unsigned long tmds_clock;
1436         u16 ref_pix, ref_line, n_pix, n_line;
1437         u16 hs_pix_s, hs_pix_e;
1438         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1439         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1440         u16 vwin1_line_s, vwin1_line_e;
1441         u16 vwin2_line_s, vwin2_line_e;
1442         u16 de_pix_s, de_pix_e;
1443         u8 reg, div, rep, sel_clk;
1444
1445         /*
1446          * Since we are "computer" like, our source invariably produces
1447          * full-range RGB.  If the monitor supports full-range, then use
1448          * it, otherwise reduce to limited-range.
1449          */
1450         priv->rgb_quant_range =
1451                 priv->connector.display_info.rgb_quant_range_selectable ?
1452                 HDMI_QUANTIZATION_RANGE_FULL :
1453                 drm_default_rgb_quant_range(adjusted_mode);
1454
1455         /*
1456          * Internally TDA998x is using ITU-R BT.656 style sync but
1457          * we get VESA style sync. TDA998x is using a reference pixel
1458          * relative to ITU to sync to the input frame and for output
1459          * sync generation. Currently, we are using reference detection
1460          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1461          * which is position of rising VS with coincident rising HS.
1462          *
1463          * Now there is some issues to take care of:
1464          * - HDMI data islands require sync-before-active
1465          * - TDA998x register values must be > 0 to be enabled
1466          * - REFLINE needs an additional offset of +1
1467          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1468          *
1469          * So we add +1 to all horizontal and vertical register values,
1470          * plus an additional +3 for REFPIX as we are using RGB input only.
1471          */
1472         n_pix        = mode->htotal;
1473         n_line       = mode->vtotal;
1474
1475         hs_pix_e     = mode->hsync_end - mode->hdisplay;
1476         hs_pix_s     = mode->hsync_start - mode->hdisplay;
1477         de_pix_e     = mode->htotal;
1478         de_pix_s     = mode->htotal - mode->hdisplay;
1479         ref_pix      = 3 + hs_pix_s;
1480
1481         /*
1482          * Attached LCD controllers may generate broken sync. Allow
1483          * those to adjust the position of the rising VS edge by adding
1484          * HSKEW to ref_pix.
1485          */
1486         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1487                 ref_pix += adjusted_mode->hskew;
1488
1489         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1490                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
1491                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1492                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1493                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1494                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
1495                 vs1_line_e   = vs1_line_s +
1496                                mode->vsync_end - mode->vsync_start;
1497                 vwin2_line_s = vwin2_line_e = 0;
1498                 vs2_pix_s    = vs2_pix_e  = 0;
1499                 vs2_line_s   = vs2_line_e = 0;
1500         } else {
1501                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
1502                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1503                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1504                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1505                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
1506                 vs1_line_e   = vs1_line_s +
1507                                (mode->vsync_end - mode->vsync_start)/2;
1508                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1509                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1510                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
1511                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
1512                 vs2_line_e   = vs2_line_s +
1513                                (mode->vsync_end - mode->vsync_start)/2;
1514         }
1515
1516         /*
1517          * Select pixel repeat depending on the double-clock flag
1518          * (which means we have to repeat each pixel once.)
1519          */
1520         rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0;
1521         sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
1522                   SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0);
1523
1524         /* the TMDS clock is scaled up by the pixel repeat */
1525         tmds_clock = mode->clock * (1 + rep);
1526
1527         /*
1528          * The divisor is power-of-2. The TDA9983B datasheet gives
1529          * this as ranges of Msample/s, which is 10x the TMDS clock:
1530          *   0 - 800 to 1500 Msample/s
1531          *   1 - 400 to 800 Msample/s
1532          *   2 - 200 to 400 Msample/s
1533          *   3 - as 2 above
1534          */
1535         for (div = 0; div < 3; div++)
1536                 if (80000 >> div <= tmds_clock)
1537                         break;
1538
1539         mutex_lock(&priv->audio_mutex);
1540
1541         priv->tmds_clock = tmds_clock;
1542
1543         /* mute the audio FIFO: */
1544         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1545
1546         /* set HDMI HDCP mode off: */
1547         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1548         reg_clear(priv, REG_TX33, TX33_HDMI);
1549         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1550
1551         /* no pre-filter or interpolator: */
1552         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1553                         HVF_CNTRL_0_INTPOL(0));
1554         reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1555         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1556         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1557                         VIP_CNTRL_4_BLC(0));
1558
1559         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1560         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1561                                           PLL_SERIAL_3_SRL_DE);
1562         reg_write(priv, REG_SERIALIZER, 0);
1563         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1564
1565         reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1566         reg_write(priv, REG_SEL_CLK, sel_clk);
1567         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1568                         PLL_SERIAL_2_SRL_PR(rep));
1569
1570         /* set color matrix according to output rgb quant range */
1571         if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
1572                 static u8 tda998x_full_to_limited_range[] = {
1573                         MAT_CONTRL_MAT_SC(2),
1574                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1575                         0x03, 0x6f, 0x00, 0x00, 0x00, 0x00,
1576                         0x00, 0x00, 0x03, 0x6f, 0x00, 0x00,
1577                         0x00, 0x00, 0x00, 0x00, 0x03, 0x6f,
1578                         0x00, 0x40, 0x00, 0x40, 0x00, 0x40
1579                 };
1580                 reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1581                 reg_write_range(priv, REG_MAT_CONTRL,
1582                                 tda998x_full_to_limited_range,
1583                                 sizeof(tda998x_full_to_limited_range));
1584         } else {
1585                 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1586                                         MAT_CONTRL_MAT_SC(1));
1587                 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1588         }
1589
1590         /* set BIAS tmds value: */
1591         reg_write(priv, REG_ANA_GENERAL, 0x09);
1592
1593         /*
1594          * Sync on rising HSYNC/VSYNC
1595          */
1596         reg = VIP_CNTRL_3_SYNC_HS;
1597
1598         /*
1599          * TDA19988 requires high-active sync at input stage,
1600          * so invert low-active sync provided by master encoder here
1601          */
1602         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1603                 reg |= VIP_CNTRL_3_H_TGL;
1604         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1605                 reg |= VIP_CNTRL_3_V_TGL;
1606         reg_write(priv, REG_VIP_CNTRL_3, reg);
1607
1608         reg_write(priv, REG_VIDFORMAT, 0x00);
1609         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1610         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1611         reg_write16(priv, REG_NPIX_MSB, n_pix);
1612         reg_write16(priv, REG_NLINE_MSB, n_line);
1613         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1614         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1615         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1616         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1617         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1618         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1619         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1620         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1621         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1622         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1623         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1624         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1625         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1626         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1627         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1628         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1629
1630         if (priv->rev == TDA19988) {
1631                 /* let incoming pixels fill the active space (if any) */
1632                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1633         }
1634
1635         /*
1636          * Always generate sync polarity relative to input sync and
1637          * revert input stage toggled sync at output stage
1638          */
1639         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1640         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1641                 reg |= TBG_CNTRL_1_H_TGL;
1642         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1643                 reg |= TBG_CNTRL_1_V_TGL;
1644         reg_write(priv, REG_TBG_CNTRL_1, reg);
1645
1646         /* must be last register set: */
1647         reg_write(priv, REG_TBG_CNTRL_0, 0);
1648
1649         /* CEA-861B section 6 says that:
1650          * CEA version 1 (CEA-861) has no support for infoframes.
1651          * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1652          * and optional basic audio.
1653          * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1654          * and optional digital audio, with audio infoframes.
1655          *
1656          * Since we only support generation of version 2 AVI infoframes,
1657          * ignore CEA version 2 and below (iow, behave as if we're a
1658          * CEA-861 source.)
1659          */
1660         priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1661
1662         if (priv->supports_infoframes) {
1663                 /* We need to turn HDMI HDCP stuff on to get audio through */
1664                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1665                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1666                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1667                 reg_set(priv, REG_TX33, TX33_HDMI);
1668
1669                 tda998x_write_avi(priv, adjusted_mode);
1670                 tda998x_write_vsi(priv, adjusted_mode);
1671
1672                 if (priv->sink_has_audio)
1673                         tda998x_configure_audio(priv);
1674         }
1675
1676         mutex_unlock(&priv->audio_mutex);
1677 }
1678
1679 static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1680         .attach = tda998x_bridge_attach,
1681         .detach = tda998x_bridge_detach,
1682         .mode_valid = tda998x_bridge_mode_valid,
1683         .disable = tda998x_bridge_disable,
1684         .mode_set = tda998x_bridge_mode_set,
1685         .enable = tda998x_bridge_enable,
1686 };
1687
1688 /* I2C driver functions */
1689
1690 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1691                                    struct device_node *np)
1692 {
1693         const u32 *port_data;
1694         u32 size;
1695         int i;
1696
1697         port_data = of_get_property(np, "audio-ports", &size);
1698         if (!port_data)
1699                 return 0;
1700
1701         size /= sizeof(u32);
1702         if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1703                 dev_err(&priv->hdmi->dev,
1704                         "Bad number of elements in audio-ports dt-property\n");
1705                 return -EINVAL;
1706         }
1707
1708         size /= 2;
1709
1710         for (i = 0; i < size; i++) {
1711                 unsigned int route;
1712                 u8 afmt = be32_to_cpup(&port_data[2*i]);
1713                 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1714
1715                 switch (afmt) {
1716                 case AFMT_I2S:
1717                         route = AUDIO_ROUTE_I2S;
1718                         break;
1719                 case AFMT_SPDIF:
1720                         route = AUDIO_ROUTE_SPDIF;
1721                         break;
1722                 default:
1723                         dev_err(&priv->hdmi->dev,
1724                                 "Bad audio format %u\n", afmt);
1725                         return -EINVAL;
1726                 }
1727
1728                 if (!ena_ap) {
1729                         dev_err(&priv->hdmi->dev, "invalid zero port config\n");
1730                         continue;
1731                 }
1732
1733                 if (priv->audio_port_enable[route]) {
1734                         dev_err(&priv->hdmi->dev,
1735                                 "%s format already configured\n",
1736                                 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S");
1737                         return -EINVAL;
1738                 }
1739
1740                 priv->audio_port_enable[route] = ena_ap;
1741         }
1742         return 0;
1743 }
1744
1745 static int tda998x_set_config(struct tda998x_priv *priv,
1746                               const struct tda998x_encoder_params *p)
1747 {
1748         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1749                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1750                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
1751                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1752         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1753                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1754                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
1755                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1756         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1757                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1758                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
1759                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1760
1761         if (p->audio_params.format != AFMT_UNUSED) {
1762                 unsigned int ratio, route;
1763                 bool spdif = p->audio_params.format == AFMT_SPDIF;
1764
1765                 route = AUDIO_ROUTE_I2S + spdif;
1766
1767                 priv->audio.route = &tda998x_audio_route[route];
1768                 priv->audio.cea = p->audio_params.cea;
1769                 priv->audio.sample_rate = p->audio_params.sample_rate;
1770                 memcpy(priv->audio.status, p->audio_params.status,
1771                        min(sizeof(priv->audio.status),
1772                            sizeof(p->audio_params.status)));
1773                 priv->audio.ena_ap = p->audio_params.config;
1774                 priv->audio.i2s_format = I2S_FORMAT_PHILIPS;
1775
1776                 ratio = spdif ? 64 : p->audio_params.sample_width * 2;
1777                 return tda998x_derive_cts_n(priv, &priv->audio, ratio);
1778         }
1779
1780         return 0;
1781 }
1782
1783 static void tda998x_destroy(struct device *dev)
1784 {
1785         struct tda998x_priv *priv = dev_get_drvdata(dev);
1786
1787         drm_bridge_remove(&priv->bridge);
1788
1789         /* disable all IRQs and free the IRQ handler */
1790         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1791         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1792
1793         if (priv->audio_pdev)
1794                 platform_device_unregister(priv->audio_pdev);
1795
1796         if (priv->hdmi->irq)
1797                 free_irq(priv->hdmi->irq, priv);
1798
1799         del_timer_sync(&priv->edid_delay_timer);
1800         cancel_work_sync(&priv->detect_work);
1801
1802         i2c_unregister_device(priv->cec);
1803
1804         if (priv->cec_notify)
1805                 cec_notifier_put(priv->cec_notify);
1806 }
1807
1808 static int tda998x_create(struct device *dev)
1809 {
1810         struct i2c_client *client = to_i2c_client(dev);
1811         struct device_node *np = client->dev.of_node;
1812         struct i2c_board_info cec_info;
1813         struct tda998x_priv *priv;
1814         u32 video;
1815         int rev_lo, rev_hi, ret;
1816
1817         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1818         if (!priv)
1819                 return -ENOMEM;
1820
1821         dev_set_drvdata(dev, priv);
1822
1823         mutex_init(&priv->mutex);       /* protect the page access */
1824         mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1825         mutex_init(&priv->edid_mutex);
1826         INIT_LIST_HEAD(&priv->bridge.list);
1827         init_waitqueue_head(&priv->edid_delay_waitq);
1828         timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1829         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1830
1831         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1832         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1833         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1834
1835         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1836         priv->cec_addr = 0x34 + (client->addr & 0x03);
1837         priv->current_page = 0xff;
1838         priv->hdmi = client;
1839
1840         /* wake up the device: */
1841         cec_write(priv, REG_CEC_ENAMODS,
1842                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1843
1844         tda998x_reset(priv);
1845
1846         /* read version: */
1847         rev_lo = reg_read(priv, REG_VERSION_LSB);
1848         if (rev_lo < 0) {
1849                 dev_err(dev, "failed to read version: %d\n", rev_lo);
1850                 return rev_lo;
1851         }
1852
1853         rev_hi = reg_read(priv, REG_VERSION_MSB);
1854         if (rev_hi < 0) {
1855                 dev_err(dev, "failed to read version: %d\n", rev_hi);
1856                 return rev_hi;
1857         }
1858
1859         priv->rev = rev_lo | rev_hi << 8;
1860
1861         /* mask off feature bits: */
1862         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1863
1864         switch (priv->rev) {
1865         case TDA9989N2:
1866                 dev_info(dev, "found TDA9989 n2");
1867                 break;
1868         case TDA19989:
1869                 dev_info(dev, "found TDA19989");
1870                 break;
1871         case TDA19989N2:
1872                 dev_info(dev, "found TDA19989 n2");
1873                 break;
1874         case TDA19988:
1875                 dev_info(dev, "found TDA19988");
1876                 break;
1877         default:
1878                 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1879                 return -ENXIO;
1880         }
1881
1882         /* after reset, enable DDC: */
1883         reg_write(priv, REG_DDC_DISABLE, 0x00);
1884
1885         /* set clock on DDC channel: */
1886         reg_write(priv, REG_TX3, 39);
1887
1888         /* if necessary, disable multi-master: */
1889         if (priv->rev == TDA19989)
1890                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1891
1892         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1893                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1894
1895         /* ensure interrupts are disabled */
1896         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1897
1898         /* clear pending interrupts */
1899         cec_read(priv, REG_CEC_RXSHPDINT);
1900         reg_read(priv, REG_INT_FLAGS_0);
1901         reg_read(priv, REG_INT_FLAGS_1);
1902         reg_read(priv, REG_INT_FLAGS_2);
1903
1904         /* initialize the optional IRQ */
1905         if (client->irq) {
1906                 unsigned long irq_flags;
1907
1908                 /* init read EDID waitqueue and HDP work */
1909                 init_waitqueue_head(&priv->wq_edid);
1910
1911                 irq_flags =
1912                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1913
1914                 priv->cec_glue.irq_flags = irq_flags;
1915
1916                 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1917                 ret = request_threaded_irq(client->irq, NULL,
1918                                            tda998x_irq_thread, irq_flags,
1919                                            "tda998x", priv);
1920                 if (ret) {
1921                         dev_err(dev, "failed to request IRQ#%u: %d\n",
1922                                 client->irq, ret);
1923                         goto err_irq;
1924                 }
1925
1926                 /* enable HPD irq */
1927                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1928         }
1929
1930         priv->cec_notify = cec_notifier_get(dev);
1931         if (!priv->cec_notify) {
1932                 ret = -ENOMEM;
1933                 goto fail;
1934         }
1935
1936         priv->cec_glue.parent = dev;
1937         priv->cec_glue.data = priv;
1938         priv->cec_glue.init = tda998x_cec_hook_init;
1939         priv->cec_glue.exit = tda998x_cec_hook_exit;
1940         priv->cec_glue.open = tda998x_cec_hook_open;
1941         priv->cec_glue.release = tda998x_cec_hook_release;
1942
1943         /*
1944          * Some TDA998x are actually two I2C devices merged onto one piece
1945          * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1946          * with a slightly modified TDA9950 CEC device.  The CEC device
1947          * is at the TDA9950 address, with the address pins strapped across
1948          * to the TDA998x address pins.  Hence, it always has the same
1949          * offset.
1950          */
1951         memset(&cec_info, 0, sizeof(cec_info));
1952         strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1953         cec_info.addr = priv->cec_addr;
1954         cec_info.platform_data = &priv->cec_glue;
1955         cec_info.irq = client->irq;
1956
1957         priv->cec = i2c_new_device(client->adapter, &cec_info);
1958         if (!priv->cec) {
1959                 ret = -ENODEV;
1960                 goto fail;
1961         }
1962
1963         /* enable EDID read irq: */
1964         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1965
1966         if (np) {
1967                 /* get the device tree parameters */
1968                 ret = of_property_read_u32(np, "video-ports", &video);
1969                 if (ret == 0) {
1970                         priv->vip_cntrl_0 = video >> 16;
1971                         priv->vip_cntrl_1 = video >> 8;
1972                         priv->vip_cntrl_2 = video;
1973                 }
1974
1975                 ret = tda998x_get_audio_ports(priv, np);
1976                 if (ret)
1977                         goto fail;
1978
1979                 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1980                     priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1981                         tda998x_audio_codec_init(priv, &client->dev);
1982         } else if (dev->platform_data) {
1983                 ret = tda998x_set_config(priv, dev->platform_data);
1984                 if (ret)
1985                         goto fail;
1986         }
1987
1988         priv->bridge.funcs = &tda998x_bridge_funcs;
1989 #ifdef CONFIG_OF
1990         priv->bridge.of_node = dev->of_node;
1991 #endif
1992
1993         drm_bridge_add(&priv->bridge);
1994
1995         return 0;
1996
1997 fail:
1998         tda998x_destroy(dev);
1999 err_irq:
2000         return ret;
2001 }
2002
2003 /* DRM encoder functions */
2004
2005 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
2006 {
2007         drm_encoder_cleanup(encoder);
2008 }
2009
2010 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
2011         .destroy = tda998x_encoder_destroy,
2012 };
2013
2014 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
2015 {
2016         struct tda998x_priv *priv = dev_get_drvdata(dev);
2017         u32 crtcs = 0;
2018         int ret;
2019
2020         if (dev->of_node)
2021                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
2022
2023         /* If no CRTCs were found, fall back to our old behaviour */
2024         if (crtcs == 0) {
2025                 dev_warn(dev, "Falling back to first CRTC\n");
2026                 crtcs = 1 << 0;
2027         }
2028
2029         priv->encoder.possible_crtcs = crtcs;
2030
2031         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
2032                                DRM_MODE_ENCODER_TMDS, NULL);
2033         if (ret)
2034                 goto err_encoder;
2035
2036         ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL);
2037         if (ret)
2038                 goto err_bridge;
2039
2040         return 0;
2041
2042 err_bridge:
2043         drm_encoder_cleanup(&priv->encoder);
2044 err_encoder:
2045         return ret;
2046 }
2047
2048 static int tda998x_bind(struct device *dev, struct device *master, void *data)
2049 {
2050         struct drm_device *drm = data;
2051
2052         return tda998x_encoder_init(dev, drm);
2053 }
2054
2055 static void tda998x_unbind(struct device *dev, struct device *master,
2056                            void *data)
2057 {
2058         struct tda998x_priv *priv = dev_get_drvdata(dev);
2059
2060         drm_encoder_cleanup(&priv->encoder);
2061 }
2062
2063 static const struct component_ops tda998x_ops = {
2064         .bind = tda998x_bind,
2065         .unbind = tda998x_unbind,
2066 };
2067
2068 static int
2069 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
2070 {
2071         int ret;
2072
2073         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2074                 dev_warn(&client->dev, "adapter does not support I2C\n");
2075                 return -EIO;
2076         }
2077
2078         ret = tda998x_create(&client->dev);
2079         if (ret)
2080                 return ret;
2081
2082         ret = component_add(&client->dev, &tda998x_ops);
2083         if (ret)
2084                 tda998x_destroy(&client->dev);
2085         return ret;
2086 }
2087
2088 static int tda998x_remove(struct i2c_client *client)
2089 {
2090         component_del(&client->dev, &tda998x_ops);
2091         tda998x_destroy(&client->dev);
2092         return 0;
2093 }
2094
2095 #ifdef CONFIG_OF
2096 static const struct of_device_id tda998x_dt_ids[] = {
2097         { .compatible = "nxp,tda998x", },
2098         { }
2099 };
2100 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2101 #endif
2102
2103 static const struct i2c_device_id tda998x_ids[] = {
2104         { "tda998x", 0 },
2105         { }
2106 };
2107 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2108
2109 static struct i2c_driver tda998x_driver = {
2110         .probe = tda998x_probe,
2111         .remove = tda998x_remove,
2112         .driver = {
2113                 .name = "tda998x",
2114                 .of_match_table = of_match_ptr(tda998x_dt_ids),
2115         },
2116         .id_table = tda998x_ids,
2117 };
2118
2119 module_i2c_driver(tda998x_driver);
2120
2121 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2122 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2123 MODULE_LICENSE("GPL");