1 // SPDX-License-Identifier: GPL-2.0-only
2 /**************************************************************************
3 * Copyright (c) 2007, Intel Corporation.
6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
9 **************************************************************************/
11 #include <drm/drm_vblank.h>
15 #include "psb_intel_reg.h"
24 psb_pipestat(int pipe)
36 mid_pipe_event(int pipe)
39 return _PSB_PIPEA_EVENT_FLAG;
41 return _MDFLD_PIPEB_EVENT_FLAG;
43 return _MDFLD_PIPEC_EVENT_FLAG;
48 mid_pipe_vsync(int pipe)
51 return _PSB_VSYNC_PIPEA_FLAG;
53 return _PSB_VSYNC_PIPEB_FLAG;
55 return _MDFLD_PIPEC_VBLANK_FLAG;
60 mid_pipeconf(int pipe)
72 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
74 if ((dev_priv->pipestat[pipe] & mask) != mask) {
75 u32 reg = psb_pipestat(pipe);
76 dev_priv->pipestat[pipe] |= mask;
77 /* Enable the interrupt, clear any pending status */
78 if (gma_power_begin(dev_priv->dev, false)) {
79 u32 writeVal = PSB_RVDC32(reg);
80 writeVal |= (mask | (mask >> 16));
81 PSB_WVDC32(writeVal, reg);
82 (void) PSB_RVDC32(reg);
83 gma_power_end(dev_priv->dev);
89 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
91 if ((dev_priv->pipestat[pipe] & mask) != 0) {
92 u32 reg = psb_pipestat(pipe);
93 dev_priv->pipestat[pipe] &= ~mask;
94 if (gma_power_begin(dev_priv->dev, false)) {
95 u32 writeVal = PSB_RVDC32(reg);
97 PSB_WVDC32(writeVal, reg);
98 (void) PSB_RVDC32(reg);
99 gma_power_end(dev_priv->dev);
105 * Display controller interrupt handler for pipe event.
107 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
109 struct drm_psb_private *dev_priv =
110 (struct drm_psb_private *) dev->dev_private;
112 uint32_t pipe_stat_val = 0;
113 uint32_t pipe_stat_reg = psb_pipestat(pipe);
114 uint32_t pipe_enable = dev_priv->pipestat[pipe];
115 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
119 spin_lock(&dev_priv->irqmask_lock);
121 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
122 pipe_stat_val &= pipe_enable | pipe_status;
123 pipe_stat_val &= pipe_stat_val >> 16;
125 spin_unlock(&dev_priv->irqmask_lock);
127 /* Clear the 2nd level interrupt status bits
128 * Sometimes the bits are very sticky so we repeat until they unstick */
129 for (i = 0; i < 0xffff; i++) {
130 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
131 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
139 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
140 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
142 if (pipe_stat_val & PIPE_VBLANK_STATUS) {
143 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
144 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
147 drm_handle_vblank(dev, pipe);
149 spin_lock_irqsave(&dev->event_lock, flags);
150 if (gma_crtc->page_flip_event) {
151 drm_crtc_send_vblank_event(crtc,
152 gma_crtc->page_flip_event);
153 gma_crtc->page_flip_event = NULL;
154 drm_crtc_vblank_put(crtc);
156 spin_unlock_irqrestore(&dev->event_lock, flags);
161 * Display controller interrupt handler.
163 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
165 if (vdc_stat & _PSB_IRQ_ASLE)
166 psb_intel_opregion_asle_intr(dev);
168 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
169 mid_pipe_event_handler(dev, 0);
171 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
172 mid_pipe_event_handler(dev, 1);
176 * SGX interrupt handler
178 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
180 struct drm_psb_private *dev_priv = dev->dev_private;
183 if (stat_1 & _PSB_CE_TWOD_COMPLETE)
184 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
186 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
187 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
188 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
190 if (val & _PSB_CBI_STAT_PF_N_RW)
191 DRM_ERROR("SGX MMU page fault:");
193 DRM_ERROR("SGX MMU read / write protection fault:");
195 if (val & _PSB_CBI_STAT_FAULT_CACHE)
196 DRM_ERROR("\tCache requestor");
197 if (val & _PSB_CBI_STAT_FAULT_TA)
198 DRM_ERROR("\tTA requestor");
199 if (val & _PSB_CBI_STAT_FAULT_VDM)
200 DRM_ERROR("\tVDM requestor");
201 if (val & _PSB_CBI_STAT_FAULT_2D)
202 DRM_ERROR("\t2D requestor");
203 if (val & _PSB_CBI_STAT_FAULT_PBE)
204 DRM_ERROR("\tPBE requestor");
205 if (val & _PSB_CBI_STAT_FAULT_TSP)
206 DRM_ERROR("\tTSP requestor");
207 if (val & _PSB_CBI_STAT_FAULT_ISP)
208 DRM_ERROR("\tISP requestor");
209 if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
210 DRM_ERROR("\tUSSEPDS requestor");
211 if (val & _PSB_CBI_STAT_FAULT_HOST)
212 DRM_ERROR("\tHost requestor");
214 DRM_ERROR("\tMMU failing address is 0x%08x.\n",
220 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
221 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
222 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
225 irqreturn_t psb_irq_handler(int irq, void *arg)
227 struct drm_device *dev = arg;
228 struct drm_psb_private *dev_priv = dev->dev_private;
229 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
230 u32 sgx_stat_1, sgx_stat_2;
233 spin_lock(&dev_priv->irqmask_lock);
235 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
237 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
240 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
242 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
245 vdc_stat &= dev_priv->vdc_irq_mask;
246 spin_unlock(&dev_priv->irqmask_lock);
248 if (dsp_int && gma_power_is_on(dev)) {
249 psb_vdc_interrupt(dev, vdc_stat);
254 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
255 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
256 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
260 /* Note: this bit has other meanings on some devices, so we will
261 need to address that later if it ever matters */
262 if (hotplug_int && dev_priv->ops->hotplug) {
263 handled = dev_priv->ops->hotplug(dev);
264 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
267 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
268 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
277 void psb_irq_preinstall(struct drm_device *dev)
279 struct drm_psb_private *dev_priv =
280 (struct drm_psb_private *) dev->dev_private;
281 unsigned long irqflags;
283 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
285 if (gma_power_is_on(dev)) {
286 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
287 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
288 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
289 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
290 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
292 if (dev->vblank[0].enabled)
293 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
294 if (dev->vblank[1].enabled)
295 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
297 /* Revisit this area - want per device masks ? */
298 if (dev_priv->ops->hotplug)
299 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
300 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
302 /* This register is safe even if display island is off */
303 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
304 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
307 int psb_irq_postinstall(struct drm_device *dev)
309 struct drm_psb_private *dev_priv = dev->dev_private;
310 unsigned long irqflags;
313 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
315 /* Enable 2D and MMU fault interrupts */
316 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
317 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
318 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
320 /* This register is safe even if display island is off */
321 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
322 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
324 for (i = 0; i < dev->num_crtcs; ++i) {
325 if (dev->vblank[i].enabled)
326 psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
328 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
331 if (dev_priv->ops->hotplug_enable)
332 dev_priv->ops->hotplug_enable(dev, true);
334 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
338 void psb_irq_uninstall(struct drm_device *dev)
340 struct drm_psb_private *dev_priv = dev->dev_private;
341 unsigned long irqflags;
344 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
346 if (dev_priv->ops->hotplug_enable)
347 dev_priv->ops->hotplug_enable(dev, false);
349 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
351 for (i = 0; i < dev->num_crtcs; ++i) {
352 if (dev->vblank[i].enabled)
353 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
356 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
357 _PSB_IRQ_MSVDX_FLAG |
360 /* These two registers are safe even if display island is off */
361 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
362 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
366 /* This register is safe even if display island is off */
367 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
368 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
372 * It is used to enable VBLANK interrupt
374 int psb_enable_vblank(struct drm_crtc *crtc)
376 struct drm_device *dev = crtc->dev;
377 unsigned int pipe = crtc->index;
378 struct drm_psb_private *dev_priv = dev->dev_private;
379 unsigned long irqflags;
380 uint32_t reg_val = 0;
381 uint32_t pipeconf_reg = mid_pipeconf(pipe);
383 if (gma_power_begin(dev, false)) {
384 reg_val = REG_READ(pipeconf_reg);
388 if (!(reg_val & PIPEACONF_ENABLE))
391 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
394 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
396 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
398 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
399 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
400 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
402 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
408 * It is used to disable VBLANK interrupt
410 void psb_disable_vblank(struct drm_crtc *crtc)
412 struct drm_device *dev = crtc->dev;
413 unsigned int pipe = crtc->index;
414 struct drm_psb_private *dev_priv = dev->dev_private;
415 unsigned long irqflags;
417 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
420 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
422 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
424 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
425 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
426 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
428 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
431 /* Called from drm generic code, passed a 'crtc', which
432 * we use as a pipe index
434 u32 psb_get_vblank_counter(struct drm_crtc *crtc)
436 struct drm_device *dev = crtc->dev;
437 unsigned int pipe = crtc->index;
438 uint32_t high_frame = PIPEAFRAMEHIGH;
439 uint32_t low_frame = PIPEAFRAMEPIXEL;
440 uint32_t pipeconf_reg = PIPEACONF;
441 uint32_t reg_val = 0;
442 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
448 high_frame = PIPEBFRAMEHIGH;
449 low_frame = PIPEBFRAMEPIXEL;
450 pipeconf_reg = PIPEBCONF;
453 high_frame = PIPECFRAMEHIGH;
454 low_frame = PIPECFRAMEPIXEL;
455 pipeconf_reg = PIPECCONF;
458 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
462 if (!gma_power_begin(dev, false))
465 reg_val = REG_READ(pipeconf_reg);
467 if (!(reg_val & PIPEACONF_ENABLE)) {
468 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
470 goto psb_get_vblank_counter_exit;
474 * High & low register fields aren't synchronized, so make sure
475 * we get a low value that's stable across two reads of the high
479 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
480 PIPE_FRAME_HIGH_SHIFT);
481 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
482 PIPE_FRAME_LOW_SHIFT);
483 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
484 PIPE_FRAME_HIGH_SHIFT);
485 } while (high1 != high2);
487 count = (high1 << 8) | low;
489 psb_get_vblank_counter_exit: