1 // SPDX-License-Identifier: GPL-2.0-only
2 /**************************************************************************
3 * Copyright (c) 2011, Intel Corporation.
6 **************************************************************************/
9 * - Split functions by vbt type
10 * - Make them all take drm_device
11 * - Check ioremap failures
19 static void mid_get_fuse_settings(struct drm_device *dev)
21 struct drm_psb_private *dev_priv = dev->dev_private;
22 struct pci_dev *pdev = to_pci_dev(dev->dev);
23 struct pci_dev *pci_root =
24 pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
26 uint32_t fuse_value = 0;
27 uint32_t fuse_value_tmp = 0;
29 #define FB_REG06 0xD0810600
30 #define FB_MIPI_DISABLE (1 << 11)
31 #define FB_REG09 0xD0810900
32 #define FB_SKU_MASK 0x7000
33 #define FB_SKU_SHIFT 12
37 if (pci_root == NULL) {
43 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
44 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
46 /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
48 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
50 DRM_INFO("internal display is %s\n",
51 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
53 /* Prevent runtime suspend at start*/
54 if (dev_priv->iLVDS_enable) {
55 dev_priv->is_lvds_on = true;
56 dev_priv->is_mipi_on = false;
58 dev_priv->is_mipi_on = true;
59 dev_priv->is_lvds_on = false;
62 dev_priv->video_device_fuse = fuse_value;
64 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
65 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
67 dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
68 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
70 dev_priv->fuse_reg_value = fuse_value;
72 switch (fuse_value_tmp) {
74 dev_priv->core_freq = 200;
77 dev_priv->core_freq = 100;
80 dev_priv->core_freq = 166;
83 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
85 dev_priv->core_freq = 0;
87 dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
88 pci_dev_put(pci_root);
92 * Get the revison ID, B0:D2:F0;0x08
94 static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
96 uint32_t platform_rev_id = 0;
97 struct pci_dev *pdev = to_pci_dev(dev_priv->dev->dev);
98 int domain = pci_domain_nr(pdev->bus);
99 struct pci_dev *pci_gfx_root =
100 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
102 if (pci_gfx_root == NULL) {
106 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
107 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
108 pci_dev_put(pci_gfx_root);
109 dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
110 dev_priv->platform_rev_id);
113 struct mid_vbt_header {
118 /* The same for r0 and r1 */
120 struct mid_vbt_header vbt_header;
126 struct mid_vbt_header vbt_header;
130 u8 primary_panel_idx;
131 u8 secondary_panel_idx;
135 static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
137 void __iomem *vbt_virtual;
139 vbt_virtual = ioremap(addr, sizeof(*vbt));
140 if (vbt_virtual == NULL)
143 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
144 iounmap(vbt_virtual);
149 static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
151 void __iomem *vbt_virtual;
153 vbt_virtual = ioremap(addr, sizeof(*vbt));
157 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
158 iounmap(vbt_virtual);
163 static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
166 void __iomem *gct_virtual;
170 if (read_vbt_r0(addr, &vbt))
173 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
176 memcpy_fromio(&gct, gct_virtual, sizeof(gct));
177 iounmap(gct_virtual);
179 bpi = gct.PD.BootPanelIndex;
180 dev_priv->gct_data.bpi = bpi;
181 dev_priv->gct_data.pt = gct.PD.PanelType;
182 dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
183 dev_priv->gct_data.Panel_Port_Control =
184 gct.panel[bpi].Panel_Port_Control;
185 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
186 gct.panel[bpi].Panel_MIPI_Display_Descriptor;
191 static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
194 void __iomem *gct_virtual;
198 if (read_vbt_r0(addr, &vbt))
201 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
204 memcpy_fromio(&gct, gct_virtual, sizeof(gct));
205 iounmap(gct_virtual);
207 bpi = gct.PD.BootPanelIndex;
208 dev_priv->gct_data.bpi = bpi;
209 dev_priv->gct_data.pt = gct.PD.PanelType;
210 dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
211 dev_priv->gct_data.Panel_Port_Control =
212 gct.panel[bpi].Panel_Port_Control;
213 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
214 gct.panel[bpi].Panel_MIPI_Display_Descriptor;
219 static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
222 void __iomem *gct_virtual;
224 struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
225 struct gct_r10_timing_info *ti;
228 if (read_vbt_r10(addr, &vbt))
231 gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL);
235 gct_virtual = ioremap(addr + sizeof(vbt),
236 sizeof(*gct) * vbt.panel_count);
239 memcpy_fromio(gct, gct_virtual, sizeof(*gct));
240 iounmap(gct_virtual);
242 dev_priv->gct_data.bpi = vbt.primary_panel_idx;
243 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
244 gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
246 ti = &gct[vbt.primary_panel_idx].DTD;
247 dp_ti->pixel_clock = ti->pixel_clock;
248 dp_ti->hactive_hi = ti->hactive_hi;
249 dp_ti->hactive_lo = ti->hactive_lo;
250 dp_ti->hblank_hi = ti->hblank_hi;
251 dp_ti->hblank_lo = ti->hblank_lo;
252 dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
253 dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
254 dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
255 dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
256 dp_ti->vactive_hi = ti->vactive_hi;
257 dp_ti->vactive_lo = ti->vactive_lo;
258 dp_ti->vblank_hi = ti->vblank_hi;
259 dp_ti->vblank_lo = ti->vblank_lo;
260 dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
261 dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
262 dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
263 dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
271 static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
273 struct drm_device *dev = dev_priv->dev;
274 struct pci_dev *pdev = to_pci_dev(dev->dev);
276 u8 __iomem *vbt_virtual;
277 struct mid_vbt_header vbt_header;
278 struct pci_dev *pci_gfx_root =
279 pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
283 /* Get the address of the platform config vbt */
284 pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
285 pci_dev_put(pci_gfx_root);
287 dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
292 /* get the virtual address of the vbt */
293 vbt_virtual = ioremap(addr, sizeof(vbt_header));
297 memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
298 iounmap(vbt_virtual);
300 if (memcmp(&vbt_header.signature, "$GCT", 4))
303 dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
305 switch (vbt_header.revision) {
307 ret = mid_get_vbt_data_r0(dev_priv, addr);
310 ret = mid_get_vbt_data_r1(dev_priv, addr);
313 ret = mid_get_vbt_data_r10(dev_priv, addr);
316 dev_err(dev->dev, "Unknown revision of GCT!\n");
321 dev_err(dev->dev, "Unable to read GCT!");
323 dev_priv->has_gct = true;
326 int mid_chip_setup(struct drm_device *dev)
328 struct drm_psb_private *dev_priv = dev->dev_private;
329 mid_get_fuse_settings(dev);
330 mid_get_vbt_data(dev_priv);
331 mid_get_pci_revID(dev_priv);