1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
6 * Eric Anholt <eric@anholt.net>
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
12 #include <drm/drm_crtc.h>
14 #include "cdv_device.h"
15 #include "framebuffer.h"
16 #include "gma_display.h"
19 #include "psb_intel_drv.h"
20 #include "psb_intel_reg.h"
22 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
23 struct drm_crtc *crtc, int target,
24 int refclk, struct gma_clock_t *best_clock);
27 #define CDV_LIMIT_SINGLE_LVDS_96 0
28 #define CDV_LIMIT_SINGLE_LVDS_100 1
29 #define CDV_LIMIT_DAC_HDMI_27 2
30 #define CDV_LIMIT_DAC_HDMI_96 3
31 #define CDV_LIMIT_DP_27 4
32 #define CDV_LIMIT_DP_100 5
34 static const struct gma_limit_t cdv_intel_limits[] = {
35 { /* CDV_SINGLE_LVDS_96MHz */
36 .dot = {.min = 20000, .max = 115500},
37 .vco = {.min = 1800000, .max = 3600000},
38 .n = {.min = 2, .max = 6},
39 .m = {.min = 60, .max = 160},
40 .m1 = {.min = 0, .max = 0},
41 .m2 = {.min = 58, .max = 158},
42 .p = {.min = 28, .max = 140},
43 .p1 = {.min = 2, .max = 10},
44 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
45 .find_pll = gma_find_best_pll,
47 { /* CDV_SINGLE_LVDS_100MHz */
48 .dot = {.min = 20000, .max = 115500},
49 .vco = {.min = 1800000, .max = 3600000},
50 .n = {.min = 2, .max = 6},
51 .m = {.min = 60, .max = 160},
52 .m1 = {.min = 0, .max = 0},
53 .m2 = {.min = 58, .max = 158},
54 .p = {.min = 28, .max = 140},
55 .p1 = {.min = 2, .max = 10},
56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
59 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
60 .find_pll = gma_find_best_pll,
62 { /* CDV_DAC_HDMI_27MHz */
63 .dot = {.min = 20000, .max = 400000},
64 .vco = {.min = 1809000, .max = 3564000},
65 .n = {.min = 1, .max = 1},
66 .m = {.min = 67, .max = 132},
67 .m1 = {.min = 0, .max = 0},
68 .m2 = {.min = 65, .max = 130},
69 .p = {.min = 5, .max = 90},
70 .p1 = {.min = 1, .max = 9},
71 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
72 .find_pll = gma_find_best_pll,
74 { /* CDV_DAC_HDMI_96MHz */
75 .dot = {.min = 20000, .max = 400000},
76 .vco = {.min = 1800000, .max = 3600000},
77 .n = {.min = 2, .max = 6},
78 .m = {.min = 60, .max = 160},
79 .m1 = {.min = 0, .max = 0},
80 .m2 = {.min = 58, .max = 158},
81 .p = {.min = 5, .max = 100},
82 .p1 = {.min = 1, .max = 10},
83 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
84 .find_pll = gma_find_best_pll,
87 .dot = {.min = 160000, .max = 272000},
88 .vco = {.min = 1809000, .max = 3564000},
89 .n = {.min = 1, .max = 1},
90 .m = {.min = 67, .max = 132},
91 .m1 = {.min = 0, .max = 0},
92 .m2 = {.min = 65, .max = 130},
93 .p = {.min = 5, .max = 90},
94 .p1 = {.min = 1, .max = 9},
95 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
96 .find_pll = cdv_intel_find_dp_pll,
99 .dot = {.min = 160000, .max = 272000},
100 .vco = {.min = 1800000, .max = 3600000},
101 .n = {.min = 2, .max = 6},
102 .m = {.min = 60, .max = 164},
103 .m1 = {.min = 0, .max = 0},
104 .m2 = {.min = 58, .max = 162},
105 .p = {.min = 5, .max = 100},
106 .p1 = {.min = 1, .max = 10},
107 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
108 .find_pll = cdv_intel_find_dp_pll,
112 #define _wait_for(COND, MS, W) ({ \
113 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
116 if (time_after(jiffies, timeout__)) { \
117 ret__ = -ETIMEDOUT; \
120 if (W && !in_dbg_master()) \
126 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
129 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
133 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
135 DRM_ERROR("timeout waiting for SB to idle before read\n");
139 REG_WRITE(SB_ADDR, reg);
141 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
142 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
143 SET_FIELD(0xf, SB_BYTE_ENABLE));
145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
147 DRM_ERROR("timeout waiting for SB to idle after read\n");
151 *val = REG_READ(SB_DATA);
156 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
159 static bool dpio_debug = true;
163 if (cdv_sb_read(dev, reg, &temp) == 0)
164 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
165 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
168 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
170 DRM_ERROR("timeout waiting for SB to idle before write\n");
174 REG_WRITE(SB_ADDR, reg);
175 REG_WRITE(SB_DATA, val);
177 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
178 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
179 SET_FIELD(0xf, SB_BYTE_ENABLE));
181 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
183 DRM_ERROR("timeout waiting for SB to idle after write\n");
188 if (cdv_sb_read(dev, reg, &temp) == 0)
189 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
195 /* Reset the DPIO configuration register. The BIOS does this at every
198 void cdv_sb_reset(struct drm_device *dev)
201 REG_WRITE(DPIO_CFG, 0);
203 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
207 * are behind this sideband bus. They must be programmed while the
208 * DPLL reference clock is on in the DPLL control register, but before
209 * the DPLL is enabled in the DPLL control register.
212 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
213 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
215 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
216 int pipe = gma_crtc->pipe;
219 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
220 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
222 u32 lane_reg, lane_value;
226 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
230 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
231 ref_value = 0x68A701;
233 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
235 /* We don't know what the other fields of these regs are, so
236 * leave them in place.
239 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
240 * for the pipe A/B. Display spec 1.06 has wrong definition.
241 * Correct definition is like below:
243 * refclka mean use clock from same PLL
245 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
247 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
250 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
253 ref_value &= ~(REF_CLK_MASK);
255 /* use DPLL_A for pipeB on CRT/HDMI */
256 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
257 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
258 ref_value |= REF_CLK_DPLLA;
260 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
261 ref_value |= REF_CLK_DPLL;
263 ret = cdv_sb_write(dev, ref_sfr, ref_value);
267 ret = cdv_sb_read(dev, SB_M(pipe), &m);
270 m &= ~SB_M_DIVIDER_MASK;
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
272 ret = cdv_sb_write(dev, SB_M(pipe), m);
276 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
280 /* Follow the BIOS to program the N_DIVIDER REG */
283 n_vco &= ~(SB_N_VCO_SEL_MASK |
287 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
289 if (clock->vco < 2250000) {
290 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
291 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
292 } else if (clock->vco < 2750000) {
293 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
294 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
295 } else if (clock->vco < 3300000) {
296 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
297 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
299 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
300 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
303 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
307 ret = cdv_sb_read(dev, SB_P(pipe), &p);
310 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
311 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
314 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
317 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
320 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
323 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
326 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
329 ret = cdv_sb_write(dev, SB_P(pipe), p);
334 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
335 lane_reg = PSB_LANE0;
336 cdv_sb_read(dev, lane_reg, &lane_value);
337 lane_value &= ~(LANE_PLL_MASK);
338 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
339 cdv_sb_write(dev, lane_reg, lane_value);
341 lane_reg = PSB_LANE1;
342 cdv_sb_read(dev, lane_reg, &lane_value);
343 lane_value &= ~(LANE_PLL_MASK);
344 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
345 cdv_sb_write(dev, lane_reg, lane_value);
347 lane_reg = PSB_LANE2;
348 cdv_sb_read(dev, lane_reg, &lane_value);
349 lane_value &= ~(LANE_PLL_MASK);
350 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
351 cdv_sb_write(dev, lane_reg, lane_value);
353 lane_reg = PSB_LANE3;
354 cdv_sb_read(dev, lane_reg, &lane_value);
355 lane_value &= ~(LANE_PLL_MASK);
356 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
357 cdv_sb_write(dev, lane_reg, lane_value);
363 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
366 const struct gma_limit_t *limit;
367 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
369 * Now only single-channel LVDS is supported on CDV. If it is
370 * incorrect, please add the dual-channel LVDS.
373 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
375 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
376 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
377 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
379 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
381 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
384 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
386 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
391 /* m1 is reserved as 0 in CDV, n is a ring counter */
392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
394 clock->m = clock->m2 + 2;
395 clock->p = clock->p1 * clock->p2;
396 clock->vco = (refclk * clock->m) / clock->n;
397 clock->dot = clock->vco / clock->p;
400 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
401 struct drm_crtc *crtc, int target,
403 struct gma_clock_t *best_clock)
405 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
406 struct gma_clock_t clock;
408 memset(&clock, 0, sizeof(clock));
412 if (target < 200000) {
428 if (target < 200000) {
447 gma_crtc->clock_funcs->clock(refclk, &clock);
448 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
452 #define FIFO_PIPEA (1 << 0)
453 #define FIFO_PIPEB (1 << 1)
455 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
457 struct drm_crtc *crtc;
458 struct drm_psb_private *dev_priv = dev->dev_private;
459 struct gma_crtc *gma_crtc = NULL;
461 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
462 gma_crtc = to_gma_crtc(crtc);
464 if (crtc->primary->fb == NULL || !gma_crtc->active)
469 void cdv_disable_sr(struct drm_device *dev)
471 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
473 /* Disable self-refresh before adjust WM */
474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
475 REG_READ(FW_BLC_SELF);
477 gma_wait_for_vblank(dev);
479 /* Cedarview workaround to write ovelay plane, which force to leave
482 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
485 gma_wait_for_vblank(dev);
490 void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
492 struct drm_psb_private *dev_priv = dev->dev_private;
493 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
495 /* Is only one pipe enabled? */
496 if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
499 fw = REG_READ(DSPFW1);
500 fw &= ~DSP_FIFO_SR_WM_MASK;
501 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
502 fw &= ~CURSOR_B_FIFO_WM_MASK;
503 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
504 REG_WRITE(DSPFW1, fw);
506 fw = REG_READ(DSPFW2);
507 fw &= ~CURSOR_A_FIFO_WM_MASK;
508 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
509 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
510 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
511 REG_WRITE(DSPFW2, fw);
513 REG_WRITE(DSPFW3, 0x36000000);
517 /* Is pipe b lvds ? */
518 if (gma_crtc->pipe == 1 &&
519 gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
520 REG_WRITE(DSPFW5, 0x00040330);
522 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
523 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
524 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
525 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
526 REG_WRITE(DSPFW5, fw);
529 REG_WRITE(DSPFW6, 0x10);
531 gma_wait_for_vblank(dev);
533 /* enable self-refresh for single pipe active */
534 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
535 REG_READ(FW_BLC_SELF);
536 gma_wait_for_vblank(dev);
540 /* HW team suggested values... */
541 REG_WRITE(DSPFW1, 0x3f880808);
542 REG_WRITE(DSPFW2, 0x0b020202);
543 REG_WRITE(DSPFW3, 0x24000000);
544 REG_WRITE(DSPFW4, 0x08030202);
545 REG_WRITE(DSPFW5, 0x01010101);
546 REG_WRITE(DSPFW6, 0x1d0);
548 gma_wait_for_vblank(dev);
550 dev_priv->ops->disable_sr(dev);
555 * Return the pipe currently connected to the panel fitter,
556 * or -1 if the panel fitter is not present or not in use
558 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
562 pfit_control = REG_READ(PFIT_CONTROL);
564 /* See if the panel fitter is in use */
565 if ((pfit_control & PFIT_ENABLE) == 0)
567 return (pfit_control >> 29) & 0x3;
570 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
571 struct drm_display_mode *mode,
572 struct drm_display_mode *adjusted_mode,
574 struct drm_framebuffer *old_fb)
576 struct drm_device *dev = crtc->dev;
577 struct drm_psb_private *dev_priv = dev->dev_private;
578 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
579 int pipe = gma_crtc->pipe;
580 const struct psb_offset *map = &dev_priv->regmap[pipe];
582 struct gma_clock_t clock;
583 u32 dpll = 0, dspcntr, pipeconf;
585 bool is_lvds = false;
587 struct drm_mode_config *mode_config = &dev->mode_config;
588 struct drm_connector *connector;
589 const struct gma_limit_t *limit;
593 list_for_each_entry(connector, &mode_config->connector_list, head) {
594 struct gma_encoder *gma_encoder =
595 gma_attached_encoder(connector);
597 if (!connector->encoder
598 || connector->encoder->crtc != crtc)
601 ddi_select = gma_encoder->ddi_select;
602 switch (gma_encoder->type) {
603 case INTEL_OUTPUT_LVDS:
606 case INTEL_OUTPUT_ANALOG:
607 case INTEL_OUTPUT_HDMI:
609 case INTEL_OUTPUT_DISPLAYPORT:
612 case INTEL_OUTPUT_EDP:
616 DRM_ERROR("invalid output type.\n");
621 if (dev_priv->dplla_96mhz)
622 /* low-end sku, 96/100 mhz */
625 /* high-end sku, 27/100 mhz */
627 if (is_dp || is_edp) {
629 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
630 * unnecessary to consider it for DP/eDP.
631 * On the high-end SKU, it will use the 27/100M reference clk
632 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
633 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
634 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
642 if (is_lvds && dev_priv->lvds_use_ssc) {
643 refclk = dev_priv->lvds_ssc_freq * 1000;
644 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
647 drm_mode_debug_printmodeline(adjusted_mode);
649 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
651 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
654 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
655 adjusted_mode->clock, clock.dot);
659 dpll = DPLL_VGA_MODE_DIS;
661 if (is_dp || is_edp) {
662 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
664 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
665 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
666 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
667 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
670 dpll |= DPLL_SYNCLOCK_ENABLE;
672 dpll |= DPLLB_MODE_LVDS;
674 dpll |= DPLLB_MODE_DAC_SERIAL; */
675 /* dpll |= (2 << 11); */
678 pipeconf = REG_READ(map->conf);
680 pipeconf &= ~(PIPE_BPC_MASK);
682 switch (dev_priv->edp.bpp) {
684 pipeconf |= PIPE_8BPC;
687 pipeconf |= PIPE_6BPC;
690 pipeconf |= PIPE_10BPC;
693 pipeconf |= PIPE_8BPC;
696 } else if (is_lvds) {
697 /* the BPC will be 6 if it is 18-bit LVDS panel */
698 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
699 pipeconf |= PIPE_8BPC;
701 pipeconf |= PIPE_6BPC;
703 pipeconf |= PIPE_8BPC;
705 /* Set up the display plane register */
706 dspcntr = DISPPLANE_GAMMA_ENABLE;
709 dspcntr |= DISPPLANE_SEL_PIPE_A;
711 dspcntr |= DISPPLANE_SEL_PIPE_B;
713 dspcntr |= DISPLAY_PLANE_ENABLE;
714 pipeconf |= PIPEACONF_ENABLE;
716 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
719 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
724 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
725 * This is an exception to the general rule that mode_set doesn't turn
729 u32 lvds = REG_READ(LVDS);
732 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
734 /* Set the B0-B3 data pairs corresponding to
735 * whether we're going to
736 * set the DPLLs for dual-channel mode or not.
739 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
741 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
743 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
744 * appropriately here, but we need to look more
745 * thoroughly into how panels behave in the two modes.
748 REG_WRITE(LVDS, lvds);
752 dpll |= DPLL_VCO_ENABLE;
754 /* Disable the panel fitter if it was on our pipe */
755 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
756 REG_WRITE(PFIT_CONTROL, 0);
758 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
759 drm_mode_debug_printmodeline(mode);
762 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
764 /* Wait for the clocks to stabilize. */
765 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
767 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
768 dev_err(dev->dev, "Failed to get DPLL lock\n");
773 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
774 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
777 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
778 ((adjusted_mode->crtc_htotal - 1) << 16));
779 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
780 ((adjusted_mode->crtc_hblank_end - 1) << 16));
781 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
782 ((adjusted_mode->crtc_hsync_end - 1) << 16));
783 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
784 ((adjusted_mode->crtc_vtotal - 1) << 16));
785 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
786 ((adjusted_mode->crtc_vblank_end - 1) << 16));
787 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
788 ((adjusted_mode->crtc_vsync_end - 1) << 16));
789 /* pipesrc and dspsize control the size that is scaled from,
790 * which should always be the user's requested size.
793 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
794 REG_WRITE(map->pos, 0);
796 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
797 REG_WRITE(map->conf, pipeconf);
800 gma_wait_for_vblank(dev);
802 REG_WRITE(map->cntr, dspcntr);
804 /* Flush the plane changes */
806 const struct drm_crtc_helper_funcs *crtc_funcs =
807 crtc->helper_private;
808 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
811 gma_wait_for_vblank(dev);
816 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
818 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
820 static void i8xx_clock(int refclk, struct gma_clock_t *clock)
822 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
823 clock->p = clock->p1 * clock->p2;
824 clock->vco = refclk * clock->m / (clock->n + 2);
825 clock->dot = clock->vco / clock->p;
828 /* Returns the clock of the currently programmed mode of the given pipe. */
829 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
830 struct drm_crtc *crtc)
832 struct drm_psb_private *dev_priv = dev->dev_private;
833 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
834 int pipe = gma_crtc->pipe;
835 const struct psb_offset *map = &dev_priv->regmap[pipe];
838 struct gma_clock_t clock;
840 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
842 if (gma_power_begin(dev, false)) {
843 dpll = REG_READ(map->dpll);
844 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
845 fp = REG_READ(map->fp0);
847 fp = REG_READ(map->fp1);
848 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
852 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
857 is_lvds = (pipe == 1) &&
858 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
861 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
862 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
863 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
868 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
869 DPLL_FPA01_P1_POST_DIV_SHIFT);
872 dev_err(dev->dev, "PLL %d\n", dpll);
876 if ((dpll & PLL_REF_INPUT_MASK) ==
877 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
878 /* XXX: might not be 66MHz */
879 i8xx_clock(66000, &clock);
881 i8xx_clock(48000, &clock);
883 if (dpll & PLL_P1_DIVIDE_BY_TWO)
888 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
889 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
891 if (dpll & PLL_P2_DIVIDE_BY_4)
896 i8xx_clock(48000, &clock);
899 /* XXX: It would be nice to validate the clocks, but we can't reuse
900 * i830PllIsValid() because it relies on the xf86_config connector
901 * configuration being accurate, which it isn't necessarily.
907 /** Returns the currently programmed mode of the given pipe. */
908 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
909 struct drm_crtc *crtc)
911 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
912 int pipe = gma_crtc->pipe;
913 struct drm_psb_private *dev_priv = dev->dev_private;
914 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
915 const struct psb_offset *map = &dev_priv->regmap[pipe];
916 struct drm_display_mode *mode;
922 if (gma_power_begin(dev, false)) {
923 htot = REG_READ(map->htotal);
924 hsync = REG_READ(map->hsync);
925 vtot = REG_READ(map->vtotal);
926 vsync = REG_READ(map->vsync);
935 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
939 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
940 mode->hdisplay = (htot & 0xffff) + 1;
941 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
942 mode->hsync_start = (hsync & 0xffff) + 1;
943 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
944 mode->vdisplay = (vtot & 0xffff) + 1;
945 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
946 mode->vsync_start = (vsync & 0xffff) + 1;
947 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
949 drm_mode_set_name(mode);
950 drm_mode_set_crtcinfo(mode, 0);
955 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
956 .dpms = gma_crtc_dpms,
957 .mode_set = cdv_intel_crtc_mode_set,
958 .mode_set_base = gma_pipe_set_base,
959 .prepare = gma_crtc_prepare,
960 .commit = gma_crtc_commit,
961 .disable = gma_crtc_disable,
964 const struct gma_clock_funcs cdv_clock_funcs = {
965 .clock = cdv_intel_clock,
966 .limit = cdv_intel_limit,
967 .pll_is_valid = gma_pll_is_valid,