drivers/gpu/drm/gma500/cdv_device.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**************************************************************************
   3  * Copyright (c) 2011, Intel Corporation.
   4  * All Rights Reserved.
   5  *
   6  **************************************************************************/
   7
   8 #include <linux/backlight.h>
   9 #include <linux/delay.h>
  10
  11 #include <drm/drm.h>
  12
  13 #include "cdv_device.h"
  14 #include "gma_device.h"
  15 #include "intel_bios.h"
  16 #include "psb_drv.h"
  17 #include "psb_intel_reg.h"
  18 #include "psb_reg.h"
  19
  20 #define VGA_SR_INDEX            0x3c4
  21 #define VGA_SR_DATA             0x3c5
  22
  23 static void cdv_disable_vga(struct drm_device *dev)
  24 {
  25         u8 sr1;
  26         u32 vga_reg;
  27
  28         vga_reg = VGACNTRL;
  29
  30         outb(1, VGA_SR_INDEX);
  31         sr1 = inb(VGA_SR_DATA);
  32         outb(sr1 | 1<<5, VGA_SR_DATA);
  33         udelay(300);
  34
  35         REG_WRITE(vga_reg, VGA_DISP_DISABLE);
  36         REG_READ(vga_reg);
  37 }
  38
  39 static int cdv_output_init(struct drm_device *dev)
  40 {
  41         struct drm_psb_private *dev_priv = dev->dev_private;
  42
  43         drm_mode_create_scaling_mode_property(dev);
  44
  45         cdv_disable_vga(dev);
  46
  47         cdv_intel_crt_init(dev, &dev_priv->mode_dev);
  48         cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
  49
  50         /* These bits indicate HDMI not SDVO on CDV */
  51         if (REG_READ(SDVOB) & SDVO_DETECTED) {
  52                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
  53                 if (REG_READ(DP_B) & DP_DETECTED)
  54                         cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B);
  55         }
  56
  57         if (REG_READ(SDVOC) & SDVO_DETECTED) {
  58                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
  59                 if (REG_READ(DP_C) & DP_DETECTED)
  60                         cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C);
  61         }
  62         return 0;
  63 }
  64
  65 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  66
  67 /*
  68  *      Cedartrail Backlght Interfaces
  69  */
  70
  71 static struct backlight_device *cdv_backlight_device;
  72
  73 static int cdv_backlight_combination_mode(struct drm_device *dev)
  74 {
  75         return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
  76 }
  77
  78 static u32 cdv_get_max_backlight(struct drm_device *dev)
  79 {
  80         u32 max = REG_READ(BLC_PWM_CTL);
  81
  82         if (max == 0) {
  83                 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
  84                 /* i915 does this, I believe which means that we should not
  85                  * smash PWM control as firmware will take control of it. */
  86                 return 1;
  87         }
  88
  89         max >>= 16;
  90         if (cdv_backlight_combination_mode(dev))
  91                 max *= 0xff;
  92         return max;
  93 }
  94
  95 static int cdv_get_brightness(struct backlight_device *bd)
  96 {
  97         struct drm_device *dev = bl_get_data(bd);
  98         struct pci_dev *pdev = to_pci_dev(dev->dev);
  99         u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 100
 101         if (cdv_backlight_combination_mode(dev)) {
 102                 u8 lbpc;
 103
 104                 val &= ~1;
 105                 pci_read_config_byte(pdev, 0xF4, &lbpc);
 106                 val *= lbpc;
 107         }
 108         return (val * 100)/cdv_get_max_backlight(dev);
 109
 110 }
 111
 112 static int cdv_set_brightness(struct backlight_device *bd)
 113 {
 114         struct drm_device *dev = bl_get_data(bd);
 115         struct pci_dev *pdev = to_pci_dev(dev->dev);
 116         int level = bd->props.brightness;
 117         u32 blc_pwm_ctl;
 118
 119         /* Percentage 1-100% being valid */
 120         if (level < 1)
 121                 level = 1;
 122
 123         level *= cdv_get_max_backlight(dev);
 124         level /= 100;
 125
 126         if (cdv_backlight_combination_mode(dev)) {
 127                 u32 max = cdv_get_max_backlight(dev);
 128                 u8 lbpc;
 129
 130                 lbpc = level * 0xfe / max + 1;
 131                 level /= lbpc;
 132
 133                 pci_write_config_byte(pdev, 0xF4, lbpc);
 134         }
 135
 136         blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 137         REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
 138                                 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
 139         return 0;
 140 }
 141
 142 static const struct backlight_ops cdv_ops = {
 143         .get_brightness = cdv_get_brightness,
 144         .update_status  = cdv_set_brightness,
 145 };
 146
 147 static int cdv_backlight_init(struct drm_device *dev)
 148 {
 149         struct drm_psb_private *dev_priv = dev->dev_private;
 150         struct backlight_properties props;
 151
 152         memset(&props, 0, sizeof(struct backlight_properties));
 153         props.max_brightness = 100;
 154         props.type = BACKLIGHT_PLATFORM;
 155
 156         cdv_backlight_device = backlight_device_register("psb-bl",
 157                                         NULL, (void *)dev, &cdv_ops, &props);
 158         if (IS_ERR(cdv_backlight_device))
 159                 return PTR_ERR(cdv_backlight_device);
 160
 161         cdv_backlight_device->props.brightness =
 162                         cdv_get_brightness(cdv_backlight_device);
 163         backlight_update_status(cdv_backlight_device);
 164         dev_priv->backlight_device = cdv_backlight_device;
 165         dev_priv->backlight_enabled = true;
 166         return 0;
 167 }
 168
 169 #endif
 170
 171 /*
 172  *      Provide the Cedarview specific chip logic and low level methods
 173  *      for power management
 174  *
 175  *      FIXME: we need to implement the apm/ospm base management bits
 176  *      for this and the MID devices.
 177  */
 178
 179 static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset)
 180 {
 181         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 182         uint32_t ret_val = 0;
 183         struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
 184         pci_write_config_dword(pci_root, 0xD0, mcr);
 185         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 186         pci_dev_put(pci_root);
 187         return ret_val;
 188 }
 189
 190 static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset,
 191                                    u32 value)
 192 {
 193         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 194         struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
 195         pci_write_config_dword(pci_root, 0xD4, value);
 196         pci_write_config_dword(pci_root, 0xD0, mcr);
 197         pci_dev_put(pci_root);
 198 }
 199
 200 #define PSB_PM_SSC                      0x20
 201 #define PSB_PM_SSS                      0x30
 202 #define PSB_PWRGT_GFX_ON                0x02
 203 #define PSB_PWRGT_GFX_OFF               0x01
 204 #define PSB_PWRGT_GFX_D0                0x00
 205 #define PSB_PWRGT_GFX_D3                0x03
 206
 207 static void cdv_init_pm(struct drm_device *dev)
 208 {
 209         struct drm_psb_private *dev_priv = dev->dev_private;
 210         struct pci_dev *pdev = to_pci_dev(dev->dev);
 211         u32 pwr_cnt;
 212         int domain = pci_domain_nr(pdev->bus);
 213         int i;
 214
 215         dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
 216                                                         PSB_APMBA) & 0xFFFF;
 217         dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
 218                                                         PSB_OSPMBA) & 0xFFFF;
 219
 220         /* Power status */
 221         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 222
 223         /* Enable the GPU */
 224         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 225         pwr_cnt |= PSB_PWRGT_GFX_ON;
 226         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 227
 228         /* Wait for the GPU power */
 229         for (i = 0; i < 5; i++) {
 230                 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 231                 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
 232                         return;
 233                 udelay(10);
 234         }
 235         dev_err(dev->dev, "GPU: power management timed out.\n");
 236 }
 237
 238 static void cdv_errata(struct drm_device *dev)
 239 {
 240         struct pci_dev *pdev = to_pci_dev(dev->dev);
 241
 242         /* Disable bonus launch.
 243          *      CPU and GPU competes for memory and display misses updates and
 244          *      flickers. Worst with dual core, dual displays.
 245          *
 246          *      Fixes were done to Win 7 gfx driver to disable a feature called
 247          *      Bonus Launch to work around the issue, by degrading
 248          *      performance.
 249          */
 250          CDV_MSG_WRITE32(pci_domain_nr(pdev->bus), 3, 0x30, 0x08027108);
 251 }
 252
 253 /**
 254  *      cdv_save_display_registers      -       save registers lost on suspend
 255  *      @dev: our DRM device
 256  *
 257  *      Save the state we need in order to be able to restore the interface
 258  *      upon resume from suspend
 259  */
 260 static int cdv_save_display_registers(struct drm_device *dev)
 261 {
 262         struct drm_psb_private *dev_priv = dev->dev_private;
 263         struct pci_dev *pdev = to_pci_dev(dev->dev);
 264         struct psb_save_area *regs = &dev_priv->regs;
 265         struct drm_connector *connector;
 266
 267         dev_dbg(dev->dev, "Saving GPU registers.\n");
 268
 269         pci_read_config_byte(pdev, 0xF4, &regs->cdv.saveLBB);
 270
 271         regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
 272         regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
 273
 274         regs->cdv.saveDSPARB = REG_READ(DSPARB);
 275         regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
 276         regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
 277         regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
 278         regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
 279         regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
 280         regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
 281
 282         regs->cdv.saveADPA = REG_READ(ADPA);
 283
 284         regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
 285         regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
 286         regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
 287         regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
 288         regs->cdv.saveLVDS = REG_READ(LVDS);
 289
 290         regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
 291
 292         regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
 293         regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
 294         regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
 295
 296         regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
 297
 298         regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
 299         regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
 300
 301         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 302                 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
 303
 304         return 0;
 305 }
 306
 307 /**
 308  *      cdv_restore_display_registers   -       restore lost register state
 309  *      @dev: our DRM device
 310  *
 311  *      Restore register state that was lost during suspend and resume.
 312  *
 313  *      FIXME: review
 314  */
 315 static int cdv_restore_display_registers(struct drm_device *dev)
 316 {
 317         struct drm_psb_private *dev_priv = dev->dev_private;
 318         struct pci_dev *pdev = to_pci_dev(dev->dev);
 319         struct psb_save_area *regs = &dev_priv->regs;
 320         struct drm_connector *connector;
 321         u32 temp;
 322
 323         pci_write_config_byte(pdev, 0xF4, regs->cdv.saveLBB);
 324
 325         REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
 326         REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
 327
 328         /* BIOS does below anyway */
 329         REG_WRITE(DPIO_CFG, 0);
 330         REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
 331
 332         temp = REG_READ(DPLL_A);
 333         if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
 334                 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
 335                 REG_READ(DPLL_A);
 336         }
 337
 338         temp = REG_READ(DPLL_B);
 339         if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
 340                 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
 341                 REG_READ(DPLL_B);
 342         }
 343
 344         udelay(500);
 345
 346         REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
 347         REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
 348         REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
 349         REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
 350         REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
 351         REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
 352
 353         REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
 354         REG_WRITE(ADPA, regs->cdv.saveADPA);
 355
 356         REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
 357         REG_WRITE(LVDS, regs->cdv.saveLVDS);
 358         REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
 359         REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
 360         REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
 361         REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
 362         REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
 363         REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
 364         REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
 365
 366         REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
 367
 368         REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
 369         REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
 370
 371         /* Fix arbitration bug */
 372         cdv_errata(dev);
 373
 374         drm_mode_config_reset(dev);
 375
 376         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 377                 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
 378
 379         /* Resume the modeset for every activated CRTC */
 380         drm_helper_resume_force_mode(dev);
 381         return 0;
 382 }
 383
 384 static int cdv_power_down(struct drm_device *dev)
 385 {
 386         struct drm_psb_private *dev_priv = dev->dev_private;
 387         u32 pwr_cnt, pwr_mask, pwr_sts;
 388         int tries = 5;
 389
 390         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 391         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 392         pwr_cnt |= PSB_PWRGT_GFX_OFF;
 393         pwr_mask = PSB_PWRGT_GFX_MASK;
 394
 395         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 396
 397         while (tries--) {
 398                 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 399                 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
 400                         return 0;
 401                 udelay(10);
 402         }
 403         return 0;
 404 }
 405
 406 static int cdv_power_up(struct drm_device *dev)
 407 {
 408         struct drm_psb_private *dev_priv = dev->dev_private;
 409         u32 pwr_cnt, pwr_mask, pwr_sts;
 410         int tries = 5;
 411
 412         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 413         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 414         pwr_cnt |= PSB_PWRGT_GFX_ON;
 415         pwr_mask = PSB_PWRGT_GFX_MASK;
 416
 417         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 418
 419         while (tries--) {
 420                 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 421                 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
 422                         return 0;
 423                 udelay(10);
 424         }
 425         return 0;
 426 }
 427
 428 static void cdv_hotplug_work_func(struct work_struct *work)
 429 {
 430         struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
 431                                                         hotplug_work);
 432         struct drm_device *dev = dev_priv->dev;
 433
 434         /* Just fire off a uevent and let userspace tell us what to do */
 435         drm_helper_hpd_irq_event(dev);
 436 }
 437
 438 /* The core driver has received a hotplug IRQ. We are in IRQ context
 439    so extract the needed information and kick off queued processing */
 440
 441 static int cdv_hotplug_event(struct drm_device *dev)
 442 {
 443         struct drm_psb_private *dev_priv = dev->dev_private;
 444         schedule_work(&dev_priv->hotplug_work);
 445         REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 446         return 1;
 447 }
 448
 449 static void cdv_hotplug_enable(struct drm_device *dev, bool on)
 450 {
 451         if (on) {
 452                 u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
 453                 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN |
 454                            HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN;
 455                 REG_WRITE(PORT_HOTPLUG_EN, hotplug);
 456         }  else {
 457                 REG_WRITE(PORT_HOTPLUG_EN, 0);
 458                 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 459         }
 460 }
 461
 462 static const char *force_audio_names[] = {
 463         "off",
 464         "auto",
 465         "on",
 466 };
 467
 468 void cdv_intel_attach_force_audio_property(struct drm_connector *connector)
 469 {
 470         struct drm_device *dev = connector->dev;
 471         struct drm_psb_private *dev_priv = dev->dev_private;
 472         struct drm_property *prop;
 473         int i;
 474
 475         prop = dev_priv->force_audio_property;
 476         if (prop == NULL) {
 477                 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
 478                                            "audio",
 479                                            ARRAY_SIZE(force_audio_names));
 480                 if (prop == NULL)
 481                         return;
 482
 483                 for (i = 0; i < ARRAY_SIZE(force_audio_names); i++)
 484                         drm_property_add_enum(prop, i-1, force_audio_names[i]);
 485
 486                 dev_priv->force_audio_property = prop;
 487         }
 488         drm_object_attach_property(&connector->base, prop, 0);
 489 }
 490
 491
 492 static const char *broadcast_rgb_names[] = {
 493         "Full",
 494         "Limited 16:235",
 495 };
 496
 497 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector)
 498 {
 499         struct drm_device *dev = connector->dev;
 500         struct drm_psb_private *dev_priv = dev->dev_private;
 501         struct drm_property *prop;
 502         int i;
 503
 504         prop = dev_priv->broadcast_rgb_property;
 505         if (prop == NULL) {
 506                 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
 507                                            "Broadcast RGB",
 508                                            ARRAY_SIZE(broadcast_rgb_names));
 509                 if (prop == NULL)
 510                         return;
 511
 512                 for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++)
 513                         drm_property_add_enum(prop, i, broadcast_rgb_names[i]);
 514
 515                 dev_priv->broadcast_rgb_property = prop;
 516         }
 517
 518         drm_object_attach_property(&connector->base, prop, 0);
 519 }
 520
 521 /* Cedarview */
 522 static const struct psb_offset cdv_regmap[2] = {
 523         {
 524                 .fp0 = FPA0,
 525                 .fp1 = FPA1,
 526                 .cntr = DSPACNTR,
 527                 .conf = PIPEACONF,
 528                 .src = PIPEASRC,
 529                 .dpll = DPLL_A,
 530                 .dpll_md = DPLL_A_MD,
 531                 .htotal = HTOTAL_A,
 532                 .hblank = HBLANK_A,
 533                 .hsync = HSYNC_A,
 534                 .vtotal = VTOTAL_A,
 535                 .vblank = VBLANK_A,
 536                 .vsync = VSYNC_A,
 537                 .stride = DSPASTRIDE,
 538                 .size = DSPASIZE,
 539                 .pos = DSPAPOS,
 540                 .base = DSPABASE,
 541                 .surf = DSPASURF,
 542                 .addr = DSPABASE,
 543                 .status = PIPEASTAT,
 544                 .linoff = DSPALINOFF,
 545                 .tileoff = DSPATILEOFF,
 546                 .palette = PALETTE_A,
 547         },
 548         {
 549                 .fp0 = FPB0,
 550                 .fp1 = FPB1,
 551                 .cntr = DSPBCNTR,
 552                 .conf = PIPEBCONF,
 553                 .src = PIPEBSRC,
 554                 .dpll = DPLL_B,
 555                 .dpll_md = DPLL_B_MD,
 556                 .htotal = HTOTAL_B,
 557                 .hblank = HBLANK_B,
 558                 .hsync = HSYNC_B,
 559                 .vtotal = VTOTAL_B,
 560                 .vblank = VBLANK_B,
 561                 .vsync = VSYNC_B,
 562                 .stride = DSPBSTRIDE,
 563                 .size = DSPBSIZE,
 564                 .pos = DSPBPOS,
 565                 .base = DSPBBASE,
 566                 .surf = DSPBSURF,
 567                 .addr = DSPBBASE,
 568                 .status = PIPEBSTAT,
 569                 .linoff = DSPBLINOFF,
 570                 .tileoff = DSPBTILEOFF,
 571                 .palette = PALETTE_B,
 572         }
 573 };
 574
 575 static int cdv_chip_setup(struct drm_device *dev)
 576 {
 577         struct drm_psb_private *dev_priv = dev->dev_private;
 578         struct pci_dev *pdev = to_pci_dev(dev->dev);
 579         INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
 580
 581         if (pci_enable_msi(pdev))
 582                 dev_warn(dev->dev, "Enabling MSI failed!\n");
 583         dev_priv->regmap = cdv_regmap;
 584         gma_get_core_freq(dev);
 585         psb_intel_opregion_init(dev);
 586         psb_intel_init_bios(dev);
 587         cdv_hotplug_enable(dev, false);
 588         return 0;
 589 }
 590
 591 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
 592
 593 const struct psb_ops cdv_chip_ops = {
 594         .name = "GMA3600/3650",
 595         .pipes = 2,
 596         .crtcs = 2,
 597         .hdmi_mask = (1 << 0) | (1 << 1),
 598         .lvds_mask = (1 << 1),
 599         .sdvo_mask = (1 << 0),
 600         .cursor_needs_phys = 0,
 601         .sgx_offset = MRST_SGX_OFFSET,
 602         .chip_setup = cdv_chip_setup,
 603         .errata = cdv_errata,
 604
 605         .crtc_helper = &cdv_intel_helper_funcs,
 606         .crtc_funcs = &gma_intel_crtc_funcs,
 607         .clock_funcs = &cdv_clock_funcs,
 608
 609         .output_init = cdv_output_init,
 610         .hotplug = cdv_hotplug_event,
 611         .hotplug_enable = cdv_hotplug_enable,
 612
 613 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 614         .backlight_init = cdv_backlight_init,
 615 #endif
 616
 617         .init_pm = cdv_init_pm,
 618         .save_regs = cdv_save_display_registers,
 619         .restore_regs = cdv_restore_display_registers,
 620         .save_crtc = gma_crtc_save,
 621         .restore_crtc = gma_crtc_restore,
 622         .power_down = cdv_power_down,
 623         .power_up = cdv_power_up,
 624         .update_wm = cdv_update_wm,
 625         .disable_sr = cdv_disable_sr,
 626 };