drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_atomic_helper.h>
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/wait.h>
  26 #include <linux/i2c.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/clk.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/io.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_device.h>
  37 #include <linux/of_gpio.h>
  38 #include <linux/hdmi.h>
  39 #include <linux/component.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/regmap.h>
  42
  43 #include <drm/exynos_drm.h>
  44
  45 #include "exynos_drm_drv.h"
  46 #include "exynos_drm_crtc.h"
  47 #include "exynos_mixer.h"
  48
  49 #include <linux/gpio.h>
  50
  51 #define ctx_from_connector(c)   container_of(c, struct hdmi_context, connector)
  52
  53 #define HOTPLUG_DEBOUNCE_MS             1100
  54
  55 /* AVI header and aspect ratio */
  56 #define HDMI_AVI_VERSION                0x02
  57 #define HDMI_AVI_LENGTH         0x0D
  58
  59 /* AUI header info */
  60 #define HDMI_AUI_VERSION        0x01
  61 #define HDMI_AUI_LENGTH 0x0A
  62 #define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
  63 #define AVI_4_3_CENTER_RATIO    0x9
  64 #define AVI_16_9_CENTER_RATIO   0xa
  65
  66 enum hdmi_type {
  67         HDMI_TYPE13,
  68         HDMI_TYPE14,
  69 };
  70
  71 struct hdmi_driver_data {
  72         unsigned int type;
  73         const struct hdmiphy_config *phy_confs;
  74         unsigned int phy_conf_count;
  75         unsigned int is_apb_phy:1;
  76 };
  77
  78 struct hdmi_resources {
  79         struct clk                      *hdmi;
  80         struct clk                      *sclk_hdmi;
  81         struct clk                      *sclk_pixel;
  82         struct clk                      *sclk_hdmiphy;
  83         struct clk                      *mout_hdmi;
  84         struct regulator_bulk_data      *regul_bulk;
  85         struct regulator                *reg_hdmi_en;
  86         int                             regul_count;
  87 };
  88
  89 struct hdmi_context {
  90         struct exynos_drm_encoder       encoder;
  91         struct device                   *dev;
  92         struct drm_device               *drm_dev;
  93         struct drm_connector            connector;
  94         bool                            hpd;
  95         bool                            powered;
  96         bool                            dvi_mode;
  97
  98         void __iomem                    *regs;
  99         int                             irq;
 100         struct delayed_work             hotplug_work;
 101
 102         struct i2c_adapter              *ddc_adpt;
 103         struct i2c_client               *hdmiphy_port;
 104
 105         /* current hdmiphy conf regs */
 106         struct drm_display_mode         current_mode;
 107         u8                              cea_video_id;
 108
 109         struct hdmi_resources           res;
 110         const struct hdmi_driver_data   *drv_data;
 111
 112         int                             hpd_gpio;
 113         void __iomem                    *regs_hdmiphy;
 114
 115         struct regmap                   *pmureg;
 116 };
 117
 118 static inline struct hdmi_context *encoder_to_hdmi(struct exynos_drm_encoder *e)
 119 {
 120         return container_of(e, struct hdmi_context, encoder);
 121 }
 122
 123 struct hdmiphy_config {
 124         int pixel_clock;
 125         u8 conf[32];
 126 };
 127
 128 /* list of phy config settings */
 129 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
 130         {
 131                 .pixel_clock = 27000000,
 132                 .conf = {
 133                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 134                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 135                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 136                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 137                 },
 138         },
 139         {
 140                 .pixel_clock = 27027000,
 141                 .conf = {
 142                         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 143                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 144                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 145                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 146                 },
 147         },
 148         {
 149                 .pixel_clock = 74176000,
 150                 .conf = {
 151                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 152                         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 153                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 154                         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 155                 },
 156         },
 157         {
 158                 .pixel_clock = 74250000,
 159                 .conf = {
 160                         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 161                         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 162                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 163                         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 164                 },
 165         },
 166         {
 167                 .pixel_clock = 148500000,
 168                 .conf = {
 169                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 170                         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 171                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 172                         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 173                 },
 174         },
 175 };
 176
 177 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
 178         {
 179                 .pixel_clock = 25200000,
 180                 .conf = {
 181                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 182                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 183                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 184                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 185                 },
 186         },
 187         {
 188                 .pixel_clock = 27000000,
 189                 .conf = {
 190                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 191                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 192                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 193                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 194                 },
 195         },
 196         {
 197                 .pixel_clock = 27027000,
 198                 .conf = {
 199                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 200                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 201                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 202                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 203                 },
 204         },
 205         {
 206                 .pixel_clock = 36000000,
 207                 .conf = {
 208                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 209                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 210                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 211                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 212                 },
 213         },
 214         {
 215                 .pixel_clock = 40000000,
 216                 .conf = {
 217                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 218                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 219                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 220                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 221                 },
 222         },
 223         {
 224                 .pixel_clock = 65000000,
 225                 .conf = {
 226                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 227                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 228                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 229                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 230                 },
 231         },
 232         {
 233                 .pixel_clock = 71000000,
 234                 .conf = {
 235                         0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
 236                         0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 237                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 238                         0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 239                 },
 240         },
 241         {
 242                 .pixel_clock = 73250000,
 243                 .conf = {
 244                         0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
 245                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 246                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 247                         0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 248                 },
 249         },
 250         {
 251                 .pixel_clock = 74176000,
 252                 .conf = {
 253                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 254                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 255                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 256                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 257                 },
 258         },
 259         {
 260                 .pixel_clock = 74250000,
 261                 .conf = {
 262                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 263                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 264                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 265                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 266                 },
 267         },
 268         {
 269                 .pixel_clock = 83500000,
 270                 .conf = {
 271                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 272                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 273                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 274                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 275                 },
 276         },
 277         {
 278                 .pixel_clock = 106500000,
 279                 .conf = {
 280                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 281                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 282                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 283                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 284                 },
 285         },
 286         {
 287                 .pixel_clock = 108000000,
 288                 .conf = {
 289                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 290                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 291                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 292                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 293                 },
 294         },
 295         {
 296                 .pixel_clock = 115500000,
 297                 .conf = {
 298                         0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
 299                         0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 300                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 301                         0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 302                 },
 303         },
 304         {
 305                 .pixel_clock = 119000000,
 306                 .conf = {
 307                         0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
 308                         0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 309                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 310                         0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 311                 },
 312         },
 313         {
 314                 .pixel_clock = 146250000,
 315                 .conf = {
 316                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 317                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 318                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 319                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 320                 },
 321         },
 322         {
 323                 .pixel_clock = 148500000,
 324                 .conf = {
 325                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 326                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 327                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 328                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 329                 },
 330         },
 331 };
 332
 333 static const struct hdmiphy_config hdmiphy_5420_configs[] = {
 334         {
 335                 .pixel_clock = 25200000,
 336                 .conf = {
 337                         0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
 338                         0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 339                         0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
 340                         0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 341                 },
 342         },
 343         {
 344                 .pixel_clock = 27000000,
 345                 .conf = {
 346                         0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
 347                         0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 348                         0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 349                         0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 350                 },
 351         },
 352         {
 353                 .pixel_clock = 27027000,
 354                 .conf = {
 355                         0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
 356                         0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 357                         0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 358                         0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 359                 },
 360         },
 361         {
 362                 .pixel_clock = 36000000,
 363                 .conf = {
 364                         0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
 365                         0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 366                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 367                         0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 368                 },
 369         },
 370         {
 371                 .pixel_clock = 40000000,
 372                 .conf = {
 373                         0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
 374                         0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 375                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 376                         0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 377                 },
 378         },
 379         {
 380                 .pixel_clock = 65000000,
 381                 .conf = {
 382                         0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
 383                         0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 384                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 385                         0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 386                 },
 387         },
 388         {
 389                 .pixel_clock = 71000000,
 390                 .conf = {
 391                         0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
 392                         0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 393                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 394                         0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 395                 },
 396         },
 397         {
 398                 .pixel_clock = 73250000,
 399                 .conf = {
 400                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
 401                         0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 402                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 403                         0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 404                 },
 405         },
 406         {
 407                 .pixel_clock = 74176000,
 408                 .conf = {
 409                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
 410                         0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 411                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 412                         0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 413                 },
 414         },
 415         {
 416                 .pixel_clock = 74250000,
 417                 .conf = {
 418                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
 419                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 420                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 421                         0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 422                 },
 423         },
 424         {
 425                 .pixel_clock = 83500000,
 426                 .conf = {
 427                         0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
 428                         0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 429                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 430                         0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 431                 },
 432         },
 433         {
 434                 .pixel_clock = 88750000,
 435                 .conf = {
 436                         0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
 437                         0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 438                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 439                         0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 440                 },
 441         },
 442         {
 443                 .pixel_clock = 106500000,
 444                 .conf = {
 445                         0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
 446                         0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 447                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 448                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 449                 },
 450         },
 451         {
 452                 .pixel_clock = 108000000,
 453                 .conf = {
 454                         0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
 455                         0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 456                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 457                         0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 458                 },
 459         },
 460         {
 461                 .pixel_clock = 115500000,
 462                 .conf = {
 463                         0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
 464                         0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 465                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 466                         0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 467                 },
 468         },
 469         {
 470                 .pixel_clock = 146250000,
 471                 .conf = {
 472                         0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
 473                         0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 474                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 475                         0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 476                 },
 477         },
 478         {
 479                 .pixel_clock = 148500000,
 480                 .conf = {
 481                         0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
 482                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 483                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 484                         0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
 485                 },
 486         },
 487 };
 488
 489 static struct hdmi_driver_data exynos5420_hdmi_driver_data = {
 490         .type           = HDMI_TYPE14,
 491         .phy_confs      = hdmiphy_5420_configs,
 492         .phy_conf_count = ARRAY_SIZE(hdmiphy_5420_configs),
 493         .is_apb_phy     = 1,
 494 };
 495
 496 static struct hdmi_driver_data exynos4212_hdmi_driver_data = {
 497         .type           = HDMI_TYPE14,
 498         .phy_confs      = hdmiphy_v14_configs,
 499         .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs),
 500         .is_apb_phy     = 0,
 501 };
 502
 503 static struct hdmi_driver_data exynos4210_hdmi_driver_data = {
 504         .type           = HDMI_TYPE13,
 505         .phy_confs      = hdmiphy_v13_configs,
 506         .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
 507         .is_apb_phy     = 0,
 508 };
 509
 510 static struct hdmi_driver_data exynos5_hdmi_driver_data = {
 511         .type           = HDMI_TYPE14,
 512         .phy_confs      = hdmiphy_v13_configs,
 513         .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
 514         .is_apb_phy     = 0,
 515 };
 516
 517 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 518 {
 519         return readl(hdata->regs + reg_id);
 520 }
 521
 522 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 523                                  u32 reg_id, u8 value)
 524 {
 525         writeb(value, hdata->regs + reg_id);
 526 }
 527
 528 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id,
 529                                    int bytes, u32 val)
 530 {
 531         while (--bytes >= 0) {
 532                 writeb(val & 0xff, hdata->regs + reg_id);
 533                 val >>= 8;
 534                 reg_id += 4;
 535         }
 536 }
 537
 538 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 539                                  u32 reg_id, u32 value, u32 mask)
 540 {
 541         u32 old = readl(hdata->regs + reg_id);
 542         value = (value & mask) | (old & ~mask);
 543         writel(value, hdata->regs + reg_id);
 544 }
 545
 546 static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
 547                         u32 reg_offset, u8 value)
 548 {
 549         if (hdata->hdmiphy_port) {
 550                 u8 buffer[2];
 551                 int ret;
 552
 553                 buffer[0] = reg_offset;
 554                 buffer[1] = value;
 555
 556                 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
 557                 if (ret == 2)
 558                         return 0;
 559                 return ret;
 560         } else {
 561                 writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
 562                 return 0;
 563         }
 564 }
 565
 566 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
 567                         u32 reg_offset, const u8 *buf, u32 len)
 568 {
 569         if ((reg_offset + len) > 32)
 570                 return -EINVAL;
 571
 572         if (hdata->hdmiphy_port) {
 573                 int ret;
 574
 575                 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
 576                 if (ret == len)
 577                         return 0;
 578                 return ret;
 579         } else {
 580                 int i;
 581                 for (i = 0; i < len; i++)
 582                         writeb(buf[i], hdata->regs_hdmiphy +
 583                                 ((reg_offset + i)<<2));
 584                 return 0;
 585         }
 586 }
 587
 588 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 589 {
 590 #define DUMPREG(reg_id) \
 591         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 592         readl(hdata->regs + reg_id))
 593         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 594         DUMPREG(HDMI_INTC_FLAG);
 595         DUMPREG(HDMI_INTC_CON);
 596         DUMPREG(HDMI_HPD_STATUS);
 597         DUMPREG(HDMI_V13_PHY_RSTOUT);
 598         DUMPREG(HDMI_V13_PHY_VPLL);
 599         DUMPREG(HDMI_V13_PHY_CMU);
 600         DUMPREG(HDMI_V13_CORE_RSTOUT);
 601
 602         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 603         DUMPREG(HDMI_CON_0);
 604         DUMPREG(HDMI_CON_1);
 605         DUMPREG(HDMI_CON_2);
 606         DUMPREG(HDMI_SYS_STATUS);
 607         DUMPREG(HDMI_V13_PHY_STATUS);
 608         DUMPREG(HDMI_STATUS_EN);
 609         DUMPREG(HDMI_HPD);
 610         DUMPREG(HDMI_MODE_SEL);
 611         DUMPREG(HDMI_V13_HPD_GEN);
 612         DUMPREG(HDMI_V13_DC_CONTROL);
 613         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 614
 615         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 616         DUMPREG(HDMI_H_BLANK_0);
 617         DUMPREG(HDMI_H_BLANK_1);
 618         DUMPREG(HDMI_V13_V_BLANK_0);
 619         DUMPREG(HDMI_V13_V_BLANK_1);
 620         DUMPREG(HDMI_V13_V_BLANK_2);
 621         DUMPREG(HDMI_V13_H_V_LINE_0);
 622         DUMPREG(HDMI_V13_H_V_LINE_1);
 623         DUMPREG(HDMI_V13_H_V_LINE_2);
 624         DUMPREG(HDMI_VSYNC_POL);
 625         DUMPREG(HDMI_INT_PRO_MODE);
 626         DUMPREG(HDMI_V13_V_BLANK_F_0);
 627         DUMPREG(HDMI_V13_V_BLANK_F_1);
 628         DUMPREG(HDMI_V13_V_BLANK_F_2);
 629         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 630         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 631         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 632         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 633         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 634         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 635         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 636         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 637         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 638         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 639         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 640         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 641
 642         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 643         DUMPREG(HDMI_TG_CMD);
 644         DUMPREG(HDMI_TG_H_FSZ_L);
 645         DUMPREG(HDMI_TG_H_FSZ_H);
 646         DUMPREG(HDMI_TG_HACT_ST_L);
 647         DUMPREG(HDMI_TG_HACT_ST_H);
 648         DUMPREG(HDMI_TG_HACT_SZ_L);
 649         DUMPREG(HDMI_TG_HACT_SZ_H);
 650         DUMPREG(HDMI_TG_V_FSZ_L);
 651         DUMPREG(HDMI_TG_V_FSZ_H);
 652         DUMPREG(HDMI_TG_VSYNC_L);
 653         DUMPREG(HDMI_TG_VSYNC_H);
 654         DUMPREG(HDMI_TG_VSYNC2_L);
 655         DUMPREG(HDMI_TG_VSYNC2_H);
 656         DUMPREG(HDMI_TG_VACT_ST_L);
 657         DUMPREG(HDMI_TG_VACT_ST_H);
 658         DUMPREG(HDMI_TG_VACT_SZ_L);
 659         DUMPREG(HDMI_TG_VACT_SZ_H);
 660         DUMPREG(HDMI_TG_FIELD_CHG_L);
 661         DUMPREG(HDMI_TG_FIELD_CHG_H);
 662         DUMPREG(HDMI_TG_VACT_ST2_L);
 663         DUMPREG(HDMI_TG_VACT_ST2_H);
 664         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 665         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 666         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 667         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 668         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 669         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 670         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 671         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 672 #undef DUMPREG
 673 }
 674
 675 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 676 {
 677         int i;
 678
 679 #define DUMPREG(reg_id) \
 680         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 681         readl(hdata->regs + reg_id))
 682
 683         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 684         DUMPREG(HDMI_INTC_CON);
 685         DUMPREG(HDMI_INTC_FLAG);
 686         DUMPREG(HDMI_HPD_STATUS);
 687         DUMPREG(HDMI_INTC_CON_1);
 688         DUMPREG(HDMI_INTC_FLAG_1);
 689         DUMPREG(HDMI_PHY_STATUS_0);
 690         DUMPREG(HDMI_PHY_STATUS_PLL);
 691         DUMPREG(HDMI_PHY_CON_0);
 692         DUMPREG(HDMI_PHY_RSTOUT);
 693         DUMPREG(HDMI_PHY_VPLL);
 694         DUMPREG(HDMI_PHY_CMU);
 695         DUMPREG(HDMI_CORE_RSTOUT);
 696
 697         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 698         DUMPREG(HDMI_CON_0);
 699         DUMPREG(HDMI_CON_1);
 700         DUMPREG(HDMI_CON_2);
 701         DUMPREG(HDMI_SYS_STATUS);
 702         DUMPREG(HDMI_PHY_STATUS_0);
 703         DUMPREG(HDMI_STATUS_EN);
 704         DUMPREG(HDMI_HPD);
 705         DUMPREG(HDMI_MODE_SEL);
 706         DUMPREG(HDMI_ENC_EN);
 707         DUMPREG(HDMI_DC_CONTROL);
 708         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 709
 710         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 711         DUMPREG(HDMI_H_BLANK_0);
 712         DUMPREG(HDMI_H_BLANK_1);
 713         DUMPREG(HDMI_V2_BLANK_0);
 714         DUMPREG(HDMI_V2_BLANK_1);
 715         DUMPREG(HDMI_V1_BLANK_0);
 716         DUMPREG(HDMI_V1_BLANK_1);
 717         DUMPREG(HDMI_V_LINE_0);
 718         DUMPREG(HDMI_V_LINE_1);
 719         DUMPREG(HDMI_H_LINE_0);
 720         DUMPREG(HDMI_H_LINE_1);
 721         DUMPREG(HDMI_HSYNC_POL);
 722
 723         DUMPREG(HDMI_VSYNC_POL);
 724         DUMPREG(HDMI_INT_PRO_MODE);
 725         DUMPREG(HDMI_V_BLANK_F0_0);
 726         DUMPREG(HDMI_V_BLANK_F0_1);
 727         DUMPREG(HDMI_V_BLANK_F1_0);
 728         DUMPREG(HDMI_V_BLANK_F1_1);
 729
 730         DUMPREG(HDMI_H_SYNC_START_0);
 731         DUMPREG(HDMI_H_SYNC_START_1);
 732         DUMPREG(HDMI_H_SYNC_END_0);
 733         DUMPREG(HDMI_H_SYNC_END_1);
 734
 735         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 736         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 737         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 738         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 739
 740         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 741         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 742         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 743         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 744
 745         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 746         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 747         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 748         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 749
 750         DUMPREG(HDMI_V_BLANK_F2_0);
 751         DUMPREG(HDMI_V_BLANK_F2_1);
 752         DUMPREG(HDMI_V_BLANK_F3_0);
 753         DUMPREG(HDMI_V_BLANK_F3_1);
 754         DUMPREG(HDMI_V_BLANK_F4_0);
 755         DUMPREG(HDMI_V_BLANK_F4_1);
 756         DUMPREG(HDMI_V_BLANK_F5_0);
 757         DUMPREG(HDMI_V_BLANK_F5_1);
 758
 759         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 760         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 761         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 762         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 763         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 764         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 765         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 766         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 767
 768         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 769         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 770         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 771         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 772         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 773         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 774         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 775         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 776
 777         DUMPREG(HDMI_VACT_SPACE_1_0);
 778         DUMPREG(HDMI_VACT_SPACE_1_1);
 779         DUMPREG(HDMI_VACT_SPACE_2_0);
 780         DUMPREG(HDMI_VACT_SPACE_2_1);
 781         DUMPREG(HDMI_VACT_SPACE_3_0);
 782         DUMPREG(HDMI_VACT_SPACE_3_1);
 783         DUMPREG(HDMI_VACT_SPACE_4_0);
 784         DUMPREG(HDMI_VACT_SPACE_4_1);
 785         DUMPREG(HDMI_VACT_SPACE_5_0);
 786         DUMPREG(HDMI_VACT_SPACE_5_1);
 787         DUMPREG(HDMI_VACT_SPACE_6_0);
 788         DUMPREG(HDMI_VACT_SPACE_6_1);
 789
 790         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 791         DUMPREG(HDMI_TG_CMD);
 792         DUMPREG(HDMI_TG_H_FSZ_L);
 793         DUMPREG(HDMI_TG_H_FSZ_H);
 794         DUMPREG(HDMI_TG_HACT_ST_L);
 795         DUMPREG(HDMI_TG_HACT_ST_H);
 796         DUMPREG(HDMI_TG_HACT_SZ_L);
 797         DUMPREG(HDMI_TG_HACT_SZ_H);
 798         DUMPREG(HDMI_TG_V_FSZ_L);
 799         DUMPREG(HDMI_TG_V_FSZ_H);
 800         DUMPREG(HDMI_TG_VSYNC_L);
 801         DUMPREG(HDMI_TG_VSYNC_H);
 802         DUMPREG(HDMI_TG_VSYNC2_L);
 803         DUMPREG(HDMI_TG_VSYNC2_H);
 804         DUMPREG(HDMI_TG_VACT_ST_L);
 805         DUMPREG(HDMI_TG_VACT_ST_H);
 806         DUMPREG(HDMI_TG_VACT_SZ_L);
 807         DUMPREG(HDMI_TG_VACT_SZ_H);
 808         DUMPREG(HDMI_TG_FIELD_CHG_L);
 809         DUMPREG(HDMI_TG_FIELD_CHG_H);
 810         DUMPREG(HDMI_TG_VACT_ST2_L);
 811         DUMPREG(HDMI_TG_VACT_ST2_H);
 812         DUMPREG(HDMI_TG_VACT_ST3_L);
 813         DUMPREG(HDMI_TG_VACT_ST3_H);
 814         DUMPREG(HDMI_TG_VACT_ST4_L);
 815         DUMPREG(HDMI_TG_VACT_ST4_H);
 816         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 817         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 818         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 819         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 820         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 821         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 822         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 823         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 824         DUMPREG(HDMI_TG_3D);
 825
 826         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 827         DUMPREG(HDMI_AVI_CON);
 828         DUMPREG(HDMI_AVI_HEADER0);
 829         DUMPREG(HDMI_AVI_HEADER1);
 830         DUMPREG(HDMI_AVI_HEADER2);
 831         DUMPREG(HDMI_AVI_CHECK_SUM);
 832         DUMPREG(HDMI_VSI_CON);
 833         DUMPREG(HDMI_VSI_HEADER0);
 834         DUMPREG(HDMI_VSI_HEADER1);
 835         DUMPREG(HDMI_VSI_HEADER2);
 836         for (i = 0; i < 7; ++i)
 837                 DUMPREG(HDMI_VSI_DATA(i));
 838
 839 #undef DUMPREG
 840 }
 841
 842 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 843 {
 844         if (hdata->drv_data->type == HDMI_TYPE13)
 845                 hdmi_v13_regs_dump(hdata, prefix);
 846         else
 847                 hdmi_v14_regs_dump(hdata, prefix);
 848 }
 849
 850 static u8 hdmi_chksum(struct hdmi_context *hdata,
 851                         u32 start, u8 len, u32 hdr_sum)
 852 {
 853         int i;
 854
 855         /* hdr_sum : header0 + header1 + header2
 856         * start : start address of packet byte1
 857         * len : packet bytes - 1 */
 858         for (i = 0; i < len; ++i)
 859                 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
 860
 861         /* return 2's complement of 8 bit hdr_sum */
 862         return (u8)(~(hdr_sum & 0xff) + 1);
 863 }
 864
 865 static void hdmi_reg_infoframe(struct hdmi_context *hdata,
 866                         union hdmi_infoframe *infoframe)
 867 {
 868         u32 hdr_sum;
 869         u8 chksum;
 870         u32 mod;
 871         u8 ar;
 872
 873         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 874         if (hdata->dvi_mode) {
 875                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 876                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 877                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 878                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 879                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 880                 return;
 881         }
 882
 883         switch (infoframe->any.type) {
 884         case HDMI_INFOFRAME_TYPE_AVI:
 885                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
 886                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
 887                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
 888                                 infoframe->any.version);
 889                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
 890                 hdr_sum = infoframe->any.type + infoframe->any.version +
 891                           infoframe->any.length;
 892
 893                 /* Output format zero hardcoded ,RGB YBCR selection */
 894                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
 895                         AVI_ACTIVE_FORMAT_VALID |
 896                         AVI_UNDERSCANNED_DISPLAY_VALID);
 897
 898                 /*
 899                  * Set the aspect ratio as per the mode, mentioned in
 900                  * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
 901                  */
 902                 ar = hdata->current_mode.picture_aspect_ratio;
 903                 switch (ar) {
 904                 case HDMI_PICTURE_ASPECT_4_3:
 905                         ar |= AVI_4_3_CENTER_RATIO;
 906                         break;
 907                 case HDMI_PICTURE_ASPECT_16_9:
 908                         ar |= AVI_16_9_CENTER_RATIO;
 909                         break;
 910                 case HDMI_PICTURE_ASPECT_NONE:
 911                 default:
 912                         ar |= AVI_SAME_AS_PIC_ASPECT_RATIO;
 913                         break;
 914                 }
 915                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), ar);
 916
 917                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->cea_video_id);
 918
 919                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
 920                                         infoframe->any.length, hdr_sum);
 921                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
 922                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
 923                 break;
 924         case HDMI_INFOFRAME_TYPE_AUDIO:
 925                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
 926                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
 927                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
 928                                 infoframe->any.version);
 929                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
 930                 hdr_sum = infoframe->any.type + infoframe->any.version +
 931                           infoframe->any.length;
 932                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
 933                                         infoframe->any.length, hdr_sum);
 934                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
 935                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
 936                 break;
 937         default:
 938                 break;
 939         }
 940 }
 941
 942 static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
 943                                 bool force)
 944 {
 945         struct hdmi_context *hdata = ctx_from_connector(connector);
 946
 947         if (gpio_get_value(hdata->hpd_gpio))
 948                 return connector_status_connected;
 949
 950         return connector_status_disconnected;
 951 }
 952
 953 static void hdmi_connector_destroy(struct drm_connector *connector)
 954 {
 955         drm_connector_unregister(connector);
 956         drm_connector_cleanup(connector);
 957 }
 958
 959 static struct drm_connector_funcs hdmi_connector_funcs = {
 960         .dpms = drm_atomic_helper_connector_dpms,
 961         .fill_modes = drm_helper_probe_single_connector_modes,
 962         .detect = hdmi_detect,
 963         .destroy = hdmi_connector_destroy,
 964         .reset = drm_atomic_helper_connector_reset,
 965         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 966         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 967 };
 968
 969 static int hdmi_get_modes(struct drm_connector *connector)
 970 {
 971         struct hdmi_context *hdata = ctx_from_connector(connector);
 972         struct edid *edid;
 973         int ret;
 974
 975         if (!hdata->ddc_adpt)
 976                 return -ENODEV;
 977
 978         edid = drm_get_edid(connector, hdata->ddc_adpt);
 979         if (!edid)
 980                 return -ENODEV;
 981
 982         hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
 983         DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
 984                 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
 985                 edid->width_cm, edid->height_cm);
 986
 987         drm_mode_connector_update_edid_property(connector, edid);
 988
 989         ret = drm_add_edid_modes(connector, edid);
 990
 991         kfree(edid);
 992
 993         return ret;
 994 }
 995
 996 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
 997 {
 998         int i;
 999
1000         for (i = 0; i < hdata->drv_data->phy_conf_count; i++)
1001                 if (hdata->drv_data->phy_confs[i].pixel_clock == pixel_clock)
1002                         return i;
1003
1004         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
1005         return -EINVAL;
1006 }
1007
1008 static int hdmi_mode_valid(struct drm_connector *connector,
1009                         struct drm_display_mode *mode)
1010 {
1011         struct hdmi_context *hdata = ctx_from_connector(connector);
1012         int ret;
1013
1014         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1015                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1016                 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
1017                 false, mode->clock * 1000);
1018
1019         ret = mixer_check_mode(mode);
1020         if (ret)
1021                 return MODE_BAD;
1022
1023         ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
1024         if (ret < 0)
1025                 return MODE_BAD;
1026
1027         return MODE_OK;
1028 }
1029
1030 static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
1031 {
1032         struct hdmi_context *hdata = ctx_from_connector(connector);
1033
1034         return &hdata->encoder.base;
1035 }
1036
1037 static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
1038         .get_modes = hdmi_get_modes,
1039         .mode_valid = hdmi_mode_valid,
1040         .best_encoder = hdmi_best_encoder,
1041 };
1042
1043 static int hdmi_create_connector(struct exynos_drm_encoder *exynos_encoder)
1044 {
1045         struct hdmi_context *hdata = encoder_to_hdmi(exynos_encoder);
1046         struct drm_connector *connector = &hdata->connector;
1047         int ret;
1048
1049         connector->interlace_allowed = true;
1050         connector->polled = DRM_CONNECTOR_POLL_HPD;
1051
1052         ret = drm_connector_init(hdata->drm_dev, connector,
1053                         &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1054         if (ret) {
1055                 DRM_ERROR("Failed to initialize connector with drm\n");
1056                 return ret;
1057         }
1058
1059         drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
1060         drm_connector_register(connector);
1061         drm_mode_connector_attach_encoder(connector, &exynos_encoder->base);
1062
1063         return 0;
1064 }
1065
1066 static void hdmi_mode_fixup(struct exynos_drm_encoder *encoder,
1067                                 struct drm_connector *connector,
1068                                 const struct drm_display_mode *mode,
1069                                 struct drm_display_mode *adjusted_mode)
1070 {
1071         struct drm_display_mode *m;
1072         int mode_ok;
1073
1074         DRM_DEBUG_KMS("%s\n", __FILE__);
1075
1076         drm_mode_set_crtcinfo(adjusted_mode, 0);
1077
1078         mode_ok = hdmi_mode_valid(connector, adjusted_mode);
1079
1080         /* just return if user desired mode exists. */
1081         if (mode_ok == MODE_OK)
1082                 return;
1083
1084         /*
1085          * otherwise, find the most suitable mode among modes and change it
1086          * to adjusted_mode.
1087          */
1088         list_for_each_entry(m, &connector->modes, head) {
1089                 mode_ok = hdmi_mode_valid(connector, m);
1090
1091                 if (mode_ok == MODE_OK) {
1092                         DRM_INFO("desired mode doesn't exist so\n");
1093                         DRM_INFO("use the most suitable mode among modes.\n");
1094
1095                         DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1096                                 m->hdisplay, m->vdisplay, m->vrefresh);
1097
1098                         drm_mode_copy(adjusted_mode, m);
1099                         break;
1100                 }
1101         }
1102 }
1103
1104 static void hdmi_set_acr(u32 freq, u8 *acr)
1105 {
1106         u32 n, cts;
1107
1108         switch (freq) {
1109         case 32000:
1110                 n = 4096;
1111                 cts = 27000;
1112                 break;
1113         case 44100:
1114                 n = 6272;
1115                 cts = 30000;
1116                 break;
1117         case 88200:
1118                 n = 12544;
1119                 cts = 30000;
1120                 break;
1121         case 176400:
1122                 n = 25088;
1123                 cts = 30000;
1124                 break;
1125         case 48000:
1126                 n = 6144;
1127                 cts = 27000;
1128                 break;
1129         case 96000:
1130                 n = 12288;
1131                 cts = 27000;
1132                 break;
1133         case 192000:
1134                 n = 24576;
1135                 cts = 27000;
1136                 break;
1137         default:
1138                 n = 0;
1139                 cts = 0;
1140                 break;
1141         }
1142
1143         acr[1] = cts >> 16;
1144         acr[2] = cts >> 8 & 0xff;
1145         acr[3] = cts & 0xff;
1146
1147         acr[4] = n >> 16;
1148         acr[5] = n >> 8 & 0xff;
1149         acr[6] = n & 0xff;
1150 }
1151
1152 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1153 {
1154         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1155         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1156         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1157         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1158         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1159         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1160         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1161         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1162         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1163
1164         if (hdata->drv_data->type == HDMI_TYPE13)
1165                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1166         else
1167                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1168 }
1169
1170 static void hdmi_audio_init(struct hdmi_context *hdata)
1171 {
1172         u32 sample_rate, bits_per_sample;
1173         u32 data_num, bit_ch, sample_frq;
1174         u32 val;
1175         u8 acr[7];
1176
1177         sample_rate = 44100;
1178         bits_per_sample = 16;
1179
1180         switch (bits_per_sample) {
1181         case 20:
1182                 data_num = 2;
1183                 bit_ch  = 1;
1184                 break;
1185         case 24:
1186                 data_num = 3;
1187                 bit_ch  = 1;
1188                 break;
1189         default:
1190                 data_num = 1;
1191                 bit_ch  = 0;
1192                 break;
1193         }
1194
1195         hdmi_set_acr(sample_rate, acr);
1196         hdmi_reg_acr(hdata, acr);
1197
1198         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1199                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1200                                 | HDMI_I2S_MUX_ENABLE);
1201
1202         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1203                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1204
1205         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1206
1207         sample_frq = (sample_rate == 44100) ? 0 :
1208                         (sample_rate == 48000) ? 2 :
1209                         (sample_rate == 32000) ? 3 :
1210                         (sample_rate == 96000) ? 0xa : 0x0;
1211
1212         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1213         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1214
1215         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1216         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1217
1218         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1219         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1220                         | HDMI_I2S_SEL_LRCK(6));
1221         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1222                         | HDMI_I2S_SEL_SDATA2(4));
1223         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1224                         | HDMI_I2S_SEL_SDATA2(2));
1225         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1226
1227         /* I2S_CON_1 & 2 */
1228         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1229                         | HDMI_I2S_L_CH_LOW_POL);
1230         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1231                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1232                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1233                         | HDMI_I2S_BASIC_FORMAT);
1234
1235         /* Configure register related to CUV information */
1236         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1237                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1238                         | HDMI_I2S_COPYRIGHT
1239                         | HDMI_I2S_LINEAR_PCM
1240                         | HDMI_I2S_CONSUMER_FORMAT);
1241         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1242         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1243         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1244                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1245         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1246                         HDMI_I2S_ORG_SMP_FREQ_44_1
1247                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1248                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1249
1250         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1251 }
1252
1253 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1254 {
1255         if (hdata->dvi_mode)
1256                 return;
1257
1258         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1259         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1260                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1261 }
1262
1263 static void hdmi_start(struct hdmi_context *hdata, bool start)
1264 {
1265         u32 val = start ? HDMI_TG_EN : 0;
1266
1267         if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1268                 val |= HDMI_FIELD_EN;
1269
1270         hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1271         hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
1272 }
1273
1274 static void hdmi_conf_init(struct hdmi_context *hdata)
1275 {
1276         union hdmi_infoframe infoframe;
1277
1278         /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1279         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1280                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1281
1282         /* choose HDMI mode */
1283         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1284                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1285         /* Apply Video preable and Guard band in HDMI mode only */
1286         hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
1287         /* disable bluescreen */
1288         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1289
1290         if (hdata->dvi_mode) {
1291                 /* choose DVI mode */
1292                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1293                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1294                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1295                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1296         }
1297
1298         if (hdata->drv_data->type == HDMI_TYPE13) {
1299                 /* choose bluescreen (fecal) color */
1300                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1301                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1302                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1303
1304                 /* enable AVI packet every vsync, fixes purple line problem */
1305                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1306                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1307                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1308                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1309
1310                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1311                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1312                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1313         } else {
1314                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1315                 infoframe.any.version = HDMI_AVI_VERSION;
1316                 infoframe.any.length = HDMI_AVI_LENGTH;
1317                 hdmi_reg_infoframe(hdata, &infoframe);
1318
1319                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1320                 infoframe.any.version = HDMI_AUI_VERSION;
1321                 infoframe.any.length = HDMI_AUI_LENGTH;
1322                 hdmi_reg_infoframe(hdata, &infoframe);
1323
1324                 /* enable AVI packet every vsync, fixes purple line problem */
1325                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1326         }
1327 }
1328
1329 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1330 {
1331         struct drm_display_mode *m = &hdata->current_mode;
1332         unsigned int val;
1333         int tries;
1334
1335         hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1336         hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3,
1337                         (m->htotal << 12) | m->vtotal);
1338
1339         val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1340         hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val);
1341
1342         val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1343         hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val);
1344
1345         val = (m->hsync_start - m->hdisplay - 2);
1346         val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1347         val |= ((m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0)<<20;
1348         hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val);
1349
1350         /*
1351          * Quirk requirement for exynos HDMI IP design,
1352          * 2 pixels less than the actual calculation for hsync_start
1353          * and end.
1354          */
1355
1356         /* Following values & calculations differ for different type of modes */
1357         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1358                 /* Interlaced Mode */
1359                 val = ((m->vsync_end - m->vdisplay) / 2);
1360                 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1361                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1362
1363                 val = m->vtotal / 2;
1364                 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1365                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1366
1367                 val = (m->vtotal +
1368                         ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1369                 val |= m->vtotal << 11;
1370                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val);
1371
1372                 val = ((m->vtotal / 2) + 7);
1373                 val |= ((m->vtotal / 2) + 2) << 12;
1374                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val);
1375
1376                 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1377                 val |= ((m->htotal / 2) +
1378                         (m->hsync_start - m->hdisplay)) << 12;
1379                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val);
1380
1381                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1382                                 (m->vtotal - m->vdisplay) / 2);
1383                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1384
1385                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249);
1386         } else {
1387                 /* Progressive Mode */
1388
1389                 val = m->vtotal;
1390                 val |= (m->vtotal - m->vdisplay) << 11;
1391                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1392
1393                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0);
1394
1395                 val = (m->vsync_end - m->vdisplay);
1396                 val |= ((m->vsync_start - m->vdisplay) << 12);
1397                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1398
1399                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001);
1400                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001);
1401                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1402                                 m->vtotal - m->vdisplay);
1403                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1404                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x248);
1405         }
1406
1407         /* Timing generator registers */
1408         hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1409         hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1410         hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1411         hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1412         hdmi_reg_writev(hdata, HDMI_TG_VSYNC_L, 2, 0x1);
1413         hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 0x233);
1414         hdmi_reg_writev(hdata, HDMI_TG_FIELD_CHG_L, 2, 0x233);
1415         hdmi_reg_writev(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, 2, 0x1);
1416         hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 0x233);
1417         hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1);
1418         hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 0x233);
1419
1420         /* waiting for HDMIPHY's PLL to get to steady state */
1421         for (tries = 100; tries; --tries) {
1422                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1423                 if (val & HDMI_PHY_STATUS_READY)
1424                         break;
1425                 usleep_range(1000, 2000);
1426         }
1427         /* steady state not achieved */
1428         if (tries == 0) {
1429                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1430                 hdmi_regs_dump(hdata, "timing apply");
1431         }
1432
1433         clk_disable_unprepare(hdata->res.sclk_hdmi);
1434         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1435         clk_prepare_enable(hdata->res.sclk_hdmi);
1436
1437         /* enable HDMI and timing generator */
1438         hdmi_start(hdata, true);
1439 }
1440
1441 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1442 {
1443         struct drm_display_mode *m = &hdata->current_mode;
1444         int tries;
1445
1446         hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1447         hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
1448         hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal);
1449         hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1,
1450                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1451         hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1,
1452                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1453         hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1,
1454                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1455
1456         /*
1457          * Quirk requirement for exynos 5 HDMI IP design,
1458          * 2 pixels less than the actual calculation for hsync_start
1459          * and end.
1460          */
1461
1462         /* Following values & calculations differ for different type of modes */
1463         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1464                 /* Interlaced Mode */
1465                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1466                         (m->vsync_end - m->vdisplay) / 2);
1467                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1468                         (m->vsync_start - m->vdisplay) / 2);
1469                 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2);
1470                 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1471                                 (m->vtotal - m->vdisplay) / 2);
1472                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2,
1473                                 m->vtotal - m->vdisplay / 2);
1474                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal);
1475                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2,
1476                                 (m->vtotal / 2) + 7);
1477                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2,
1478                                 (m->vtotal / 2) + 2);
1479                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2,
1480                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1481                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2,
1482                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1483                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1484                                 (m->vtotal - m->vdisplay) / 2);
1485                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1486                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2,
1487                                 m->vtotal - m->vdisplay / 2);
1488                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2,
1489                                 (m->vtotal / 2) + 1);
1490                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2,
1491                                 (m->vtotal / 2) + 1);
1492                 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2,
1493                                 (m->vtotal / 2) + 1);
1494                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0);
1495                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0);
1496         } else {
1497                 /* Progressive Mode */
1498                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1499                         m->vsync_end - m->vdisplay);
1500                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1501                         m->vsync_start - m->vdisplay);
1502                 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal);
1503                 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1504                                 m->vtotal - m->vdisplay);
1505                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff);
1506                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff);
1507                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff);
1508                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff);
1509                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff);
1510                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff);
1511                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1512                                 m->vtotal - m->vdisplay);
1513                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1514                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x248);
1515                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x47b);
1516                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x6ae);
1517                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 0x233);
1518                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 0x233);
1519                 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 0x233);
1520         }
1521
1522         /* Following values & calculations are same irrespective of mode type */
1523         hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2,
1524                         m->hsync_start - m->hdisplay - 2);
1525         hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2,
1526                         m->hsync_end - m->hdisplay - 2);
1527         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff);
1528         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff);
1529         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff);
1530         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff);
1531         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff);
1532         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff);
1533         hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff);
1534         hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff);
1535         hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff);
1536         hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff);
1537         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff);
1538         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff);
1539         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff);
1540         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff);
1541         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff);
1542         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff);
1543         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff);
1544         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
1545
1546         /* Timing generator registers */
1547         hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1548         hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1549         hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1550         hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1551         hdmi_reg_writev(hdata, HDMI_TG_VSYNC_L, 2, 0x1);
1552         hdmi_reg_writev(hdata, HDMI_TG_FIELD_CHG_L, 2, 0x233);
1553         hdmi_reg_writev(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, 2, 0x1);
1554         hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1);
1555         hdmi_reg_writev(hdata, HDMI_TG_3D, 1, 0x0);
1556
1557         /* waiting for HDMIPHY's PLL to get to steady state */
1558         for (tries = 100; tries; --tries) {
1559                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1560                 if (val & HDMI_PHY_STATUS_READY)
1561                         break;
1562                 usleep_range(1000, 2000);
1563         }
1564         /* steady state not achieved */
1565         if (tries == 0) {
1566                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1567                 hdmi_regs_dump(hdata, "timing apply");
1568         }
1569
1570         clk_disable_unprepare(hdata->res.sclk_hdmi);
1571         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1572         clk_prepare_enable(hdata->res.sclk_hdmi);
1573
1574         /* enable HDMI and timing generator */
1575         hdmi_start(hdata, true);
1576 }
1577
1578 static void hdmi_mode_apply(struct hdmi_context *hdata)
1579 {
1580         if (hdata->drv_data->type == HDMI_TYPE13)
1581                 hdmi_v13_mode_apply(hdata);
1582         else
1583                 hdmi_v14_mode_apply(hdata);
1584 }
1585
1586 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1587 {
1588         u32 reg;
1589
1590         clk_disable_unprepare(hdata->res.sclk_hdmi);
1591         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
1592         clk_prepare_enable(hdata->res.sclk_hdmi);
1593
1594         /* operation mode */
1595         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1596                                 HDMI_PHY_ENABLE_MODE_SET);
1597
1598         if (hdata->drv_data->type == HDMI_TYPE13)
1599                 reg = HDMI_V13_PHY_RSTOUT;
1600         else
1601                 reg = HDMI_PHY_RSTOUT;
1602
1603         /* reset hdmiphy */
1604         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1605         usleep_range(10000, 12000);
1606         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1607         usleep_range(10000, 12000);
1608 }
1609
1610 static void hdmiphy_poweron(struct hdmi_context *hdata)
1611 {
1612         if (hdata->drv_data->type != HDMI_TYPE14)
1613                 return;
1614
1615         DRM_DEBUG_KMS("\n");
1616
1617         /* For PHY Mode Setting */
1618         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1619                                 HDMI_PHY_ENABLE_MODE_SET);
1620         /* Phy Power On */
1621         hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1622                                 HDMI_PHY_POWER_ON);
1623         /* For PHY Mode Setting */
1624         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1625                                 HDMI_PHY_DISABLE_MODE_SET);
1626         /* PHY SW Reset */
1627         hdmiphy_conf_reset(hdata);
1628 }
1629
1630 static void hdmiphy_poweroff(struct hdmi_context *hdata)
1631 {
1632         if (hdata->drv_data->type != HDMI_TYPE14)
1633                 return;
1634
1635         DRM_DEBUG_KMS("\n");
1636
1637         /* PHY SW Reset */
1638         hdmiphy_conf_reset(hdata);
1639         /* For PHY Mode Setting */
1640         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1641                                 HDMI_PHY_ENABLE_MODE_SET);
1642
1643         /* PHY Power Off */
1644         hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1645                                 HDMI_PHY_POWER_OFF);
1646
1647         /* For PHY Mode Setting */
1648         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1649                                 HDMI_PHY_DISABLE_MODE_SET);
1650 }
1651
1652 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1653 {
1654         int ret;
1655         int i;
1656
1657         /* pixel clock */
1658         i = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
1659         if (i < 0) {
1660                 DRM_ERROR("failed to find hdmiphy conf\n");
1661                 return;
1662         }
1663
1664         ret = hdmiphy_reg_write_buf(hdata, 0,
1665                         hdata->drv_data->phy_confs[i].conf, 32);
1666         if (ret) {
1667                 DRM_ERROR("failed to configure hdmiphy\n");
1668                 return;
1669         }
1670
1671         usleep_range(10000, 12000);
1672
1673         ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1674                                 HDMI_PHY_DISABLE_MODE_SET);
1675         if (ret) {
1676                 DRM_ERROR("failed to enable hdmiphy\n");
1677                 return;
1678         }
1679
1680 }
1681
1682 static void hdmi_conf_apply(struct hdmi_context *hdata)
1683 {
1684         hdmiphy_conf_reset(hdata);
1685         hdmiphy_conf_apply(hdata);
1686
1687         hdmi_start(hdata, false);
1688         hdmi_conf_init(hdata);
1689
1690         hdmi_audio_init(hdata);
1691
1692         /* setting core registers */
1693         hdmi_mode_apply(hdata);
1694         hdmi_audio_control(hdata, true);
1695
1696         hdmi_regs_dump(hdata, "start");
1697 }
1698
1699 static void hdmi_mode_set(struct exynos_drm_encoder *encoder,
1700                         struct drm_display_mode *mode)
1701 {
1702         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1703         struct drm_display_mode *m = mode;
1704
1705         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1706                 m->hdisplay, m->vdisplay,
1707                 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1708                 "INTERLACED" : "PROGRESSIVE");
1709
1710         drm_mode_copy(&hdata->current_mode, mode);
1711         hdata->cea_video_id = drm_match_cea_mode(mode);
1712 }
1713
1714 static void hdmi_commit(struct exynos_drm_encoder *encoder)
1715 {
1716         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1717
1718         if (!hdata->powered)
1719                 return;
1720
1721         hdmi_conf_apply(hdata);
1722 }
1723
1724 static void hdmi_enable(struct exynos_drm_encoder *encoder)
1725 {
1726         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1727         struct hdmi_resources *res = &hdata->res;
1728
1729         if (hdata->powered)
1730                 return;
1731
1732         hdata->powered = true;
1733
1734         pm_runtime_get_sync(hdata->dev);
1735
1736         if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
1737                 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1738
1739         /* set pmu hdmiphy control bit to enable hdmiphy */
1740         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1741                         PMU_HDMI_PHY_ENABLE_BIT, 1);
1742
1743         clk_prepare_enable(res->hdmi);
1744         clk_prepare_enable(res->sclk_hdmi);
1745
1746         hdmiphy_poweron(hdata);
1747         hdmi_commit(encoder);
1748 }
1749
1750 static void hdmi_disable(struct exynos_drm_encoder *encoder)
1751 {
1752         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1753         struct hdmi_resources *res = &hdata->res;
1754         struct drm_crtc *crtc = hdata->encoder.base.crtc;
1755         const struct drm_crtc_helper_funcs *funcs = NULL;
1756
1757         if (!hdata->powered)
1758                 return;
1759
1760         /*
1761          * The SFRs of VP and Mixer are updated by Vertical Sync of
1762          * Timing generator which is a part of HDMI so the sequence
1763          * to disable TV Subsystem should be as following,
1764          *      VP -> Mixer -> HDMI
1765          *
1766          * Below codes will try to disable Mixer and VP(if used)
1767          * prior to disabling HDMI.
1768          */
1769         if (crtc)
1770                 funcs = crtc->helper_private;
1771         if (funcs && funcs->disable)
1772                 (*funcs->disable)(crtc);
1773
1774         /* HDMI System Disable */
1775         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
1776
1777         hdmiphy_poweroff(hdata);
1778
1779         cancel_delayed_work(&hdata->hotplug_work);
1780
1781         clk_disable_unprepare(res->sclk_hdmi);
1782         clk_disable_unprepare(res->hdmi);
1783
1784         /* reset pmu hdmiphy control bit to disable hdmiphy */
1785         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1786                         PMU_HDMI_PHY_ENABLE_BIT, 0);
1787
1788         regulator_bulk_disable(res->regul_count, res->regul_bulk);
1789
1790         pm_runtime_put_sync(hdata->dev);
1791
1792         hdata->powered = false;
1793 }
1794
1795 static struct exynos_drm_encoder_ops hdmi_encoder_ops = {
1796         .create_connector = hdmi_create_connector,
1797         .mode_fixup     = hdmi_mode_fixup,
1798         .mode_set       = hdmi_mode_set,
1799         .enable         = hdmi_enable,
1800         .disable        = hdmi_disable,
1801         .commit         = hdmi_commit,
1802 };
1803
1804 static void hdmi_hotplug_work_func(struct work_struct *work)
1805 {
1806         struct hdmi_context *hdata;
1807
1808         hdata = container_of(work, struct hdmi_context, hotplug_work.work);
1809
1810         if (hdata->drm_dev)
1811                 drm_helper_hpd_irq_event(hdata->drm_dev);
1812 }
1813
1814 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1815 {
1816         struct hdmi_context *hdata = arg;
1817
1818         mod_delayed_work(system_wq, &hdata->hotplug_work,
1819                         msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
1820
1821         return IRQ_HANDLED;
1822 }
1823
1824 static int hdmi_resources_init(struct hdmi_context *hdata)
1825 {
1826         struct device *dev = hdata->dev;
1827         struct hdmi_resources *res = &hdata->res;
1828         static char *supply[] = {
1829                 "vdd",
1830                 "vdd_osc",
1831                 "vdd_pll",
1832         };
1833         int i, ret;
1834
1835         DRM_DEBUG_KMS("HDMI resource init\n");
1836
1837         /* get clocks, power */
1838         res->hdmi = devm_clk_get(dev, "hdmi");
1839         if (IS_ERR(res->hdmi)) {
1840                 DRM_ERROR("failed to get clock 'hdmi'\n");
1841                 ret = PTR_ERR(res->hdmi);
1842                 goto fail;
1843         }
1844         res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
1845         if (IS_ERR(res->sclk_hdmi)) {
1846                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1847                 ret = PTR_ERR(res->sclk_hdmi);
1848                 goto fail;
1849         }
1850         res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
1851         if (IS_ERR(res->sclk_pixel)) {
1852                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1853                 ret = PTR_ERR(res->sclk_pixel);
1854                 goto fail;
1855         }
1856         res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
1857         if (IS_ERR(res->sclk_hdmiphy)) {
1858                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1859                 ret = PTR_ERR(res->sclk_hdmiphy);
1860                 goto fail;
1861         }
1862         res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
1863         if (IS_ERR(res->mout_hdmi)) {
1864                 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
1865                 ret = PTR_ERR(res->mout_hdmi);
1866                 goto fail;
1867         }
1868
1869         clk_set_parent(res->mout_hdmi, res->sclk_pixel);
1870
1871         res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
1872                 sizeof(res->regul_bulk[0]), GFP_KERNEL);
1873         if (!res->regul_bulk) {
1874                 ret = -ENOMEM;
1875                 goto fail;
1876         }
1877         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1878                 res->regul_bulk[i].supply = supply[i];
1879                 res->regul_bulk[i].consumer = NULL;
1880         }
1881         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
1882         if (ret) {
1883                 DRM_ERROR("failed to get regulators\n");
1884                 return ret;
1885         }
1886         res->regul_count = ARRAY_SIZE(supply);
1887
1888         res->reg_hdmi_en = devm_regulator_get(dev, "hdmi-en");
1889         if (IS_ERR(res->reg_hdmi_en) && PTR_ERR(res->reg_hdmi_en) != -ENOENT) {
1890                 DRM_ERROR("failed to get hdmi-en regulator\n");
1891                 return PTR_ERR(res->reg_hdmi_en);
1892         }
1893         if (!IS_ERR(res->reg_hdmi_en)) {
1894                 ret = regulator_enable(res->reg_hdmi_en);
1895                 if (ret) {
1896                         DRM_ERROR("failed to enable hdmi-en regulator\n");
1897                         return ret;
1898                 }
1899         } else
1900                 res->reg_hdmi_en = NULL;
1901
1902         return ret;
1903 fail:
1904         DRM_ERROR("HDMI resource init - failed\n");
1905         return ret;
1906 }
1907
1908 static struct of_device_id hdmi_match_types[] = {
1909         {
1910                 .compatible = "samsung,exynos5-hdmi",
1911                 .data = &exynos5_hdmi_driver_data,
1912         }, {
1913                 .compatible = "samsung,exynos4210-hdmi",
1914                 .data = &exynos4210_hdmi_driver_data,
1915         }, {
1916                 .compatible = "samsung,exynos4212-hdmi",
1917                 .data = &exynos4212_hdmi_driver_data,
1918         }, {
1919                 .compatible = "samsung,exynos5420-hdmi",
1920                 .data = &exynos5420_hdmi_driver_data,
1921         }, {
1922                 /* end node */
1923         }
1924 };
1925 MODULE_DEVICE_TABLE (of, hdmi_match_types);
1926
1927 static int hdmi_bind(struct device *dev, struct device *master, void *data)
1928 {
1929         struct drm_device *drm_dev = data;
1930         struct hdmi_context *hdata = dev_get_drvdata(dev);
1931
1932         hdata->drm_dev = drm_dev;
1933
1934         return exynos_drm_create_enc_conn(drm_dev, &hdata->encoder,
1935                                           EXYNOS_DISPLAY_TYPE_HDMI);
1936 }
1937
1938 static void hdmi_unbind(struct device *dev, struct device *master, void *data)
1939 {
1940 }
1941
1942 static const struct component_ops hdmi_component_ops = {
1943         .bind   = hdmi_bind,
1944         .unbind = hdmi_unbind,
1945 };
1946
1947 static struct device_node *hdmi_legacy_ddc_dt_binding(struct device *dev)
1948 {
1949         const char *compatible_str = "samsung,exynos4210-hdmiddc";
1950         struct device_node *np;
1951
1952         np = of_find_compatible_node(NULL, NULL, compatible_str);
1953         if (np)
1954                 return of_get_next_parent(np);
1955
1956         return NULL;
1957 }
1958
1959 static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev)
1960 {
1961         const char *compatible_str = "samsung,exynos4212-hdmiphy";
1962
1963         return of_find_compatible_node(NULL, NULL, compatible_str);
1964 }
1965
1966 static int hdmi_probe(struct platform_device *pdev)
1967 {
1968         struct device_node *ddc_node, *phy_node;
1969         const struct of_device_id *match;
1970         struct device *dev = &pdev->dev;
1971         struct hdmi_context *hdata;
1972         struct resource *res;
1973         int ret;
1974
1975         hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
1976         if (!hdata)
1977                 return -ENOMEM;
1978
1979         match = of_match_device(hdmi_match_types, dev);
1980         if (!match)
1981                 return -ENODEV;
1982
1983         hdata->drv_data = match->data;
1984         hdata->encoder.ops = &hdmi_encoder_ops;
1985
1986         platform_set_drvdata(pdev, hdata);
1987
1988         hdata->dev = dev;
1989         hdata->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpio", 0);
1990         if (hdata->hpd_gpio < 0) {
1991                 DRM_ERROR("cannot get hpd gpio property\n");
1992                 return hdata->hpd_gpio;
1993         }
1994
1995         ret = hdmi_resources_init(hdata);
1996         if (ret) {
1997                 DRM_ERROR("hdmi_resources_init failed\n");
1998                 return ret;
1999         }
2000
2001         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2002         hdata->regs = devm_ioremap_resource(dev, res);
2003         if (IS_ERR(hdata->regs)) {
2004                 ret = PTR_ERR(hdata->regs);
2005                 return ret;
2006         }
2007
2008         ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
2009         if (ret) {
2010                 DRM_ERROR("failed to request HPD gpio\n");
2011                 return ret;
2012         }
2013
2014         ddc_node = hdmi_legacy_ddc_dt_binding(dev);
2015         if (ddc_node)
2016                 goto out_get_ddc_adpt;
2017
2018         /* DDC i2c driver */
2019         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2020         if (!ddc_node) {
2021                 DRM_ERROR("Failed to find ddc node in device tree\n");
2022                 return -ENODEV;
2023         }
2024
2025 out_get_ddc_adpt:
2026         hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2027         if (!hdata->ddc_adpt) {
2028                 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
2029                 return -EPROBE_DEFER;
2030         }
2031
2032         phy_node = hdmi_legacy_phy_dt_binding(dev);
2033         if (phy_node)
2034                 goto out_get_phy_port;
2035
2036         /* hdmiphy i2c driver */
2037         phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2038         if (!phy_node) {
2039                 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2040                 ret = -ENODEV;
2041                 goto err_ddc;
2042         }
2043
2044 out_get_phy_port:
2045         if (hdata->drv_data->is_apb_phy) {
2046                 hdata->regs_hdmiphy = of_iomap(phy_node, 0);
2047                 if (!hdata->regs_hdmiphy) {
2048                         DRM_ERROR("failed to ioremap hdmi phy\n");
2049                         ret = -ENOMEM;
2050                         goto err_ddc;
2051                 }
2052         } else {
2053                 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2054                 if (!hdata->hdmiphy_port) {
2055                         DRM_ERROR("Failed to get hdmi phy i2c client\n");
2056                         ret = -EPROBE_DEFER;
2057                         goto err_ddc;
2058                 }
2059         }
2060
2061         hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2062         if (hdata->irq < 0) {
2063                 DRM_ERROR("failed to get GPIO irq\n");
2064                 ret = hdata->irq;
2065                 goto err_hdmiphy;
2066         }
2067
2068         INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2069
2070         ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2071                         hdmi_irq_thread, IRQF_TRIGGER_RISING |
2072                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2073                         "hdmi", hdata);
2074         if (ret) {
2075                 DRM_ERROR("failed to register hdmi interrupt\n");
2076                 goto err_hdmiphy;
2077         }
2078
2079         hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2080                         "samsung,syscon-phandle");
2081         if (IS_ERR(hdata->pmureg)) {
2082                 DRM_ERROR("syscon regmap lookup failed.\n");
2083                 ret = -EPROBE_DEFER;
2084                 goto err_hdmiphy;
2085         }
2086
2087         pm_runtime_enable(dev);
2088
2089         ret = component_add(&pdev->dev, &hdmi_component_ops);
2090         if (ret)
2091                 goto err_disable_pm_runtime;
2092
2093         return ret;
2094
2095 err_disable_pm_runtime:
2096         pm_runtime_disable(dev);
2097
2098 err_hdmiphy:
2099         if (hdata->hdmiphy_port)
2100                 put_device(&hdata->hdmiphy_port->dev);
2101 err_ddc:
2102         put_device(&hdata->ddc_adpt->dev);
2103
2104         return ret;
2105 }
2106
2107 static int hdmi_remove(struct platform_device *pdev)
2108 {
2109         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2110
2111         cancel_delayed_work_sync(&hdata->hotplug_work);
2112
2113         if (hdata->res.reg_hdmi_en)
2114                 regulator_disable(hdata->res.reg_hdmi_en);
2115
2116         if (hdata->hdmiphy_port)
2117                 put_device(&hdata->hdmiphy_port->dev);
2118         put_device(&hdata->ddc_adpt->dev);
2119
2120         pm_runtime_disable(&pdev->dev);
2121         component_del(&pdev->dev, &hdmi_component_ops);
2122
2123         return 0;
2124 }
2125
2126 struct platform_driver hdmi_driver = {
2127         .probe          = hdmi_probe,
2128         .remove         = hdmi_remove,
2129         .driver         = {
2130                 .name   = "exynos-hdmi",
2131                 .owner  = THIS_MODULE,
2132                 .of_match_table = hdmi_match_types,
2133         },
2134 };