drivers/gpu/drm/exynos/exynos_drm_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Samsung SoC MIPI DSI Master driver.
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd
   6  *
   7  * Contacts: Tomasz Figa <t.figa@samsung.com>
   8 */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/component.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/irq.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/regulator/consumer.h>
  20
  21 #include <asm/unaligned.h>
  22
  23 #include <video/mipi_display.h>
  24 #include <video/videomode.h>
  25
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_bridge.h>
  28 #include <drm/drm_fb_helper.h>
  29 #include <drm/drm_mipi_dsi.h>
  30 #include <drm/drm_panel.h>
  31 #include <drm/drm_print.h>
  32 #include <drm/drm_probe_helper.h>
  33 #include <drm/drm_simple_kms_helper.h>
  34
  35 #include "exynos_drm_crtc.h"
  36 #include "exynos_drm_drv.h"
  37
  38 /* returns true iff both arguments logically differs */
  39 #define NEQV(a, b) (!(a) ^ !(b))
  40
  41 /* DSIM_STATUS */
  42 #define DSIM_STOP_STATE_DAT(x)          (((x) & 0xf) << 0)
  43 #define DSIM_STOP_STATE_CLK             (1 << 8)
  44 #define DSIM_TX_READY_HS_CLK            (1 << 10)
  45 #define DSIM_PLL_STABLE                 (1 << 31)
  46
  47 /* DSIM_SWRST */
  48 #define DSIM_FUNCRST                    (1 << 16)
  49 #define DSIM_SWRST                      (1 << 0)
  50
  51 /* DSIM_TIMEOUT */
  52 #define DSIM_LPDR_TIMEOUT(x)            ((x) << 0)
  53 #define DSIM_BTA_TIMEOUT(x)             ((x) << 16)
  54
  55 /* DSIM_CLKCTRL */
  56 #define DSIM_ESC_PRESCALER(x)           (((x) & 0xffff) << 0)
  57 #define DSIM_ESC_PRESCALER_MASK         (0xffff << 0)
  58 #define DSIM_LANE_ESC_CLK_EN_CLK        (1 << 19)
  59 #define DSIM_LANE_ESC_CLK_EN_DATA(x)    (((x) & 0xf) << 20)
  60 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK  (0xf << 20)
  61 #define DSIM_BYTE_CLKEN                 (1 << 24)
  62 #define DSIM_BYTE_CLK_SRC(x)            (((x) & 0x3) << 25)
  63 #define DSIM_BYTE_CLK_SRC_MASK          (0x3 << 25)
  64 #define DSIM_PLL_BYPASS                 (1 << 27)
  65 #define DSIM_ESC_CLKEN                  (1 << 28)
  66 #define DSIM_TX_REQUEST_HSCLK           (1 << 31)
  67
  68 /* DSIM_CONFIG */
  69 #define DSIM_LANE_EN_CLK                (1 << 0)
  70 #define DSIM_LANE_EN(x)                 (((x) & 0xf) << 1)
  71 #define DSIM_NUM_OF_DATA_LANE(x)        (((x) & 0x3) << 5)
  72 #define DSIM_SUB_PIX_FORMAT(x)          (((x) & 0x7) << 8)
  73 #define DSIM_MAIN_PIX_FORMAT_MASK       (0x7 << 12)
  74 #define DSIM_MAIN_PIX_FORMAT_RGB888     (0x7 << 12)
  75 #define DSIM_MAIN_PIX_FORMAT_RGB666     (0x6 << 12)
  76 #define DSIM_MAIN_PIX_FORMAT_RGB666_P   (0x5 << 12)
  77 #define DSIM_MAIN_PIX_FORMAT_RGB565     (0x4 << 12)
  78 #define DSIM_SUB_VC                     (((x) & 0x3) << 16)
  79 #define DSIM_MAIN_VC                    (((x) & 0x3) << 18)
  80 #define DSIM_HSA_MODE                   (1 << 20)
  81 #define DSIM_HBP_MODE                   (1 << 21)
  82 #define DSIM_HFP_MODE                   (1 << 22)
  83 #define DSIM_HSE_MODE                   (1 << 23)
  84 #define DSIM_AUTO_MODE                  (1 << 24)
  85 #define DSIM_VIDEO_MODE                 (1 << 25)
  86 #define DSIM_BURST_MODE                 (1 << 26)
  87 #define DSIM_SYNC_INFORM                (1 << 27)
  88 #define DSIM_EOT_DISABLE                (1 << 28)
  89 #define DSIM_MFLUSH_VS                  (1 << 29)
  90 /* This flag is valid only for exynos3250/3472/5260/5430 */
  91 #define DSIM_CLKLANE_STOP               (1 << 30)
  92
  93 /* DSIM_ESCMODE */
  94 #define DSIM_TX_TRIGGER_RST             (1 << 4)
  95 #define DSIM_TX_LPDT_LP                 (1 << 6)
  96 #define DSIM_CMD_LPDT_LP                (1 << 7)
  97 #define DSIM_FORCE_BTA                  (1 << 16)
  98 #define DSIM_FORCE_STOP_STATE           (1 << 20)
  99 #define DSIM_STOP_STATE_CNT(x)          (((x) & 0x7ff) << 21)
 100 #define DSIM_STOP_STATE_CNT_MASK        (0x7ff << 21)
 101
 102 /* DSIM_MDRESOL */
 103 #define DSIM_MAIN_STAND_BY              (1 << 31)
 104 #define DSIM_MAIN_VRESOL(x, num_bits)   (((x) & ((1 << (num_bits)) - 1)) << 16)
 105 #define DSIM_MAIN_HRESOL(x, num_bits)   (((x) & ((1 << (num_bits)) - 1)) << 0)
 106
 107 /* DSIM_MVPORCH */
 108 #define DSIM_CMD_ALLOW(x)               ((x) << 28)
 109 #define DSIM_STABLE_VFP(x)              ((x) << 16)
 110 #define DSIM_MAIN_VBP(x)                ((x) << 0)
 111 #define DSIM_CMD_ALLOW_MASK             (0xf << 28)
 112 #define DSIM_STABLE_VFP_MASK            (0x7ff << 16)
 113 #define DSIM_MAIN_VBP_MASK              (0x7ff << 0)
 114
 115 /* DSIM_MHPORCH */
 116 #define DSIM_MAIN_HFP(x)                ((x) << 16)
 117 #define DSIM_MAIN_HBP(x)                ((x) << 0)
 118 #define DSIM_MAIN_HFP_MASK              ((0xffff) << 16)
 119 #define DSIM_MAIN_HBP_MASK              ((0xffff) << 0)
 120
 121 /* DSIM_MSYNC */
 122 #define DSIM_MAIN_VSA(x)                ((x) << 22)
 123 #define DSIM_MAIN_HSA(x)                ((x) << 0)
 124 #define DSIM_MAIN_VSA_MASK              ((0x3ff) << 22)
 125 #define DSIM_MAIN_HSA_MASK              ((0xffff) << 0)
 126
 127 /* DSIM_SDRESOL */
 128 #define DSIM_SUB_STANDY(x)              ((x) << 31)
 129 #define DSIM_SUB_VRESOL(x)              ((x) << 16)
 130 #define DSIM_SUB_HRESOL(x)              ((x) << 0)
 131 #define DSIM_SUB_STANDY_MASK            ((0x1) << 31)
 132 #define DSIM_SUB_VRESOL_MASK            ((0x7ff) << 16)
 133 #define DSIM_SUB_HRESOL_MASK            ((0x7ff) << 0)
 134
 135 /* DSIM_INTSRC */
 136 #define DSIM_INT_PLL_STABLE             (1 << 31)
 137 #define DSIM_INT_SW_RST_RELEASE         (1 << 30)
 138 #define DSIM_INT_SFR_FIFO_EMPTY         (1 << 29)
 139 #define DSIM_INT_SFR_HDR_FIFO_EMPTY     (1 << 28)
 140 #define DSIM_INT_BTA                    (1 << 25)
 141 #define DSIM_INT_FRAME_DONE             (1 << 24)
 142 #define DSIM_INT_RX_TIMEOUT             (1 << 21)
 143 #define DSIM_INT_BTA_TIMEOUT            (1 << 20)
 144 #define DSIM_INT_RX_DONE                (1 << 18)
 145 #define DSIM_INT_RX_TE                  (1 << 17)
 146 #define DSIM_INT_RX_ACK                 (1 << 16)
 147 #define DSIM_INT_RX_ECC_ERR             (1 << 15)
 148 #define DSIM_INT_RX_CRC_ERR             (1 << 14)
 149
 150 /* DSIM_FIFOCTRL */
 151 #define DSIM_RX_DATA_FULL               (1 << 25)
 152 #define DSIM_RX_DATA_EMPTY              (1 << 24)
 153 #define DSIM_SFR_HEADER_FULL            (1 << 23)
 154 #define DSIM_SFR_HEADER_EMPTY           (1 << 22)
 155 #define DSIM_SFR_PAYLOAD_FULL           (1 << 21)
 156 #define DSIM_SFR_PAYLOAD_EMPTY          (1 << 20)
 157 #define DSIM_I80_HEADER_FULL            (1 << 19)
 158 #define DSIM_I80_HEADER_EMPTY           (1 << 18)
 159 #define DSIM_I80_PAYLOAD_FULL           (1 << 17)
 160 #define DSIM_I80_PAYLOAD_EMPTY          (1 << 16)
 161 #define DSIM_SD_HEADER_FULL             (1 << 15)
 162 #define DSIM_SD_HEADER_EMPTY            (1 << 14)
 163 #define DSIM_SD_PAYLOAD_FULL            (1 << 13)
 164 #define DSIM_SD_PAYLOAD_EMPTY           (1 << 12)
 165 #define DSIM_MD_HEADER_FULL             (1 << 11)
 166 #define DSIM_MD_HEADER_EMPTY            (1 << 10)
 167 #define DSIM_MD_PAYLOAD_FULL            (1 << 9)
 168 #define DSIM_MD_PAYLOAD_EMPTY           (1 << 8)
 169 #define DSIM_RX_FIFO                    (1 << 4)
 170 #define DSIM_SFR_FIFO                   (1 << 3)
 171 #define DSIM_I80_FIFO                   (1 << 2)
 172 #define DSIM_SD_FIFO                    (1 << 1)
 173 #define DSIM_MD_FIFO                    (1 << 0)
 174
 175 /* DSIM_PHYACCHR */
 176 #define DSIM_AFC_EN                     (1 << 14)
 177 #define DSIM_AFC_CTL(x)                 (((x) & 0x7) << 5)
 178
 179 /* DSIM_PLLCTRL */
 180 #define DSIM_FREQ_BAND(x)               ((x) << 24)
 181 #define DSIM_PLL_EN                     (1 << 23)
 182 #define DSIM_PLL_P(x)                   ((x) << 13)
 183 #define DSIM_PLL_M(x)                   ((x) << 4)
 184 #define DSIM_PLL_S(x)                   ((x) << 1)
 185
 186 /* DSIM_PHYCTRL */
 187 #define DSIM_PHYCTRL_ULPS_EXIT(x)       (((x) & 0x1ff) << 0)
 188 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP  (1 << 30)
 189 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP  (1 << 14)
 190
 191 /* DSIM_PHYTIMING */
 192 #define DSIM_PHYTIMING_LPX(x)           ((x) << 8)
 193 #define DSIM_PHYTIMING_HS_EXIT(x)       ((x) << 0)
 194
 195 /* DSIM_PHYTIMING1 */
 196 #define DSIM_PHYTIMING1_CLK_PREPARE(x)  ((x) << 24)
 197 #define DSIM_PHYTIMING1_CLK_ZERO(x)     ((x) << 16)
 198 #define DSIM_PHYTIMING1_CLK_POST(x)     ((x) << 8)
 199 #define DSIM_PHYTIMING1_CLK_TRAIL(x)    ((x) << 0)
 200
 201 /* DSIM_PHYTIMING2 */
 202 #define DSIM_PHYTIMING2_HS_PREPARE(x)   ((x) << 16)
 203 #define DSIM_PHYTIMING2_HS_ZERO(x)      ((x) << 8)
 204 #define DSIM_PHYTIMING2_HS_TRAIL(x)     ((x) << 0)
 205
 206 #define DSI_MAX_BUS_WIDTH               4
 207 #define DSI_NUM_VIRTUAL_CHANNELS        4
 208 #define DSI_TX_FIFO_SIZE                2048
 209 #define DSI_RX_FIFO_SIZE                256
 210 #define DSI_XFER_TIMEOUT_MS             100
 211 #define DSI_RX_FIFO_EMPTY               0x30800002
 212
 213 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
 214
 215 static const char *const clk_names[5] = { "bus_clk", "sclk_mipi",
 216         "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
 217         "sclk_rgb_vclk_to_dsim0" };
 218
 219 enum exynos_dsi_transfer_type {
 220         EXYNOS_DSI_TX,
 221         EXYNOS_DSI_RX,
 222 };
 223
 224 struct exynos_dsi_transfer {
 225         struct list_head list;
 226         struct completion completed;
 227         int result;
 228         struct mipi_dsi_packet packet;
 229         u16 flags;
 230         u16 tx_done;
 231
 232         u8 *rx_payload;
 233         u16 rx_len;
 234         u16 rx_done;
 235 };
 236
 237 #define DSIM_STATE_ENABLED              BIT(0)
 238 #define DSIM_STATE_INITIALIZED          BIT(1)
 239 #define DSIM_STATE_CMD_LPM              BIT(2)
 240 #define DSIM_STATE_VIDOUT_AVAILABLE     BIT(3)
 241
 242 struct exynos_dsi_driver_data {
 243         const unsigned int *reg_ofs;
 244         unsigned int plltmr_reg;
 245         unsigned int has_freqband:1;
 246         unsigned int has_clklane_stop:1;
 247         unsigned int num_clks;
 248         unsigned int max_freq;
 249         unsigned int wait_for_reset;
 250         unsigned int num_bits_resol;
 251         const unsigned int *reg_values;
 252 };
 253
 254 struct exynos_dsi {
 255         struct drm_encoder encoder;
 256         struct mipi_dsi_host dsi_host;
 257         struct drm_connector connector;
 258         struct drm_panel *panel;
 259         struct list_head bridge_chain;
 260         struct drm_bridge *out_bridge;
 261         struct device *dev;
 262
 263         void __iomem *reg_base;
 264         struct phy *phy;
 265         struct clk **clks;
 266         struct regulator_bulk_data supplies[2];
 267         int irq;
 268         int te_gpio;
 269
 270         u32 pll_clk_rate;
 271         u32 burst_clk_rate;
 272         u32 esc_clk_rate;
 273         u32 lanes;
 274         u32 mode_flags;
 275         u32 format;
 276
 277         int state;
 278         struct drm_property *brightness;
 279         struct completion completed;
 280
 281         spinlock_t transfer_lock; /* protects transfer_list */
 282         struct list_head transfer_list;
 283
 284         const struct exynos_dsi_driver_data *driver_data;
 285         struct device_node *in_bridge_node;
 286 };
 287
 288 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
 289 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
 290
 291 static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
 292 {
 293         return container_of(e, struct exynos_dsi, encoder);
 294 }
 295
 296 enum reg_idx {
 297         DSIM_STATUS_REG,        /* Status register */
 298         DSIM_SWRST_REG,         /* Software reset register */
 299         DSIM_CLKCTRL_REG,       /* Clock control register */
 300         DSIM_TIMEOUT_REG,       /* Time out register */
 301         DSIM_CONFIG_REG,        /* Configuration register */
 302         DSIM_ESCMODE_REG,       /* Escape mode register */
 303         DSIM_MDRESOL_REG,
 304         DSIM_MVPORCH_REG,       /* Main display Vporch register */
 305         DSIM_MHPORCH_REG,       /* Main display Hporch register */
 306         DSIM_MSYNC_REG,         /* Main display sync area register */
 307         DSIM_INTSRC_REG,        /* Interrupt source register */
 308         DSIM_INTMSK_REG,        /* Interrupt mask register */
 309         DSIM_PKTHDR_REG,        /* Packet Header FIFO register */
 310         DSIM_PAYLOAD_REG,       /* Payload FIFO register */
 311         DSIM_RXFIFO_REG,        /* Read FIFO register */
 312         DSIM_FIFOCTRL_REG,      /* FIFO status and control register */
 313         DSIM_PLLCTRL_REG,       /* PLL control register */
 314         DSIM_PHYCTRL_REG,
 315         DSIM_PHYTIMING_REG,
 316         DSIM_PHYTIMING1_REG,
 317         DSIM_PHYTIMING2_REG,
 318         NUM_REGS
 319 };
 320
 321 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
 322                                     u32 val)
 323 {
 324
 325         writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 326 }
 327
 328 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
 329 {
 330         return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 331 }
 332
 333 static const unsigned int exynos_reg_ofs[] = {
 334         [DSIM_STATUS_REG] =  0x00,
 335         [DSIM_SWRST_REG] =  0x04,
 336         [DSIM_CLKCTRL_REG] =  0x08,
 337         [DSIM_TIMEOUT_REG] =  0x0c,
 338         [DSIM_CONFIG_REG] =  0x10,
 339         [DSIM_ESCMODE_REG] =  0x14,
 340         [DSIM_MDRESOL_REG] =  0x18,
 341         [DSIM_MVPORCH_REG] =  0x1c,
 342         [DSIM_MHPORCH_REG] =  0x20,
 343         [DSIM_MSYNC_REG] =  0x24,
 344         [DSIM_INTSRC_REG] =  0x2c,
 345         [DSIM_INTMSK_REG] =  0x30,
 346         [DSIM_PKTHDR_REG] =  0x34,
 347         [DSIM_PAYLOAD_REG] =  0x38,
 348         [DSIM_RXFIFO_REG] =  0x3c,
 349         [DSIM_FIFOCTRL_REG] =  0x44,
 350         [DSIM_PLLCTRL_REG] =  0x4c,
 351         [DSIM_PHYCTRL_REG] =  0x5c,
 352         [DSIM_PHYTIMING_REG] =  0x64,
 353         [DSIM_PHYTIMING1_REG] =  0x68,
 354         [DSIM_PHYTIMING2_REG] =  0x6c,
 355 };
 356
 357 static const unsigned int exynos5433_reg_ofs[] = {
 358         [DSIM_STATUS_REG] = 0x04,
 359         [DSIM_SWRST_REG] = 0x0C,
 360         [DSIM_CLKCTRL_REG] = 0x10,
 361         [DSIM_TIMEOUT_REG] = 0x14,
 362         [DSIM_CONFIG_REG] = 0x18,
 363         [DSIM_ESCMODE_REG] = 0x1C,
 364         [DSIM_MDRESOL_REG] = 0x20,
 365         [DSIM_MVPORCH_REG] = 0x24,
 366         [DSIM_MHPORCH_REG] = 0x28,
 367         [DSIM_MSYNC_REG] = 0x2C,
 368         [DSIM_INTSRC_REG] = 0x34,
 369         [DSIM_INTMSK_REG] = 0x38,
 370         [DSIM_PKTHDR_REG] = 0x3C,
 371         [DSIM_PAYLOAD_REG] = 0x40,
 372         [DSIM_RXFIFO_REG] = 0x44,
 373         [DSIM_FIFOCTRL_REG] = 0x4C,
 374         [DSIM_PLLCTRL_REG] = 0x94,
 375         [DSIM_PHYCTRL_REG] = 0xA4,
 376         [DSIM_PHYTIMING_REG] = 0xB4,
 377         [DSIM_PHYTIMING1_REG] = 0xB8,
 378         [DSIM_PHYTIMING2_REG] = 0xBC,
 379 };
 380
 381 enum reg_value_idx {
 382         RESET_TYPE,
 383         PLL_TIMER,
 384         STOP_STATE_CNT,
 385         PHYCTRL_ULPS_EXIT,
 386         PHYCTRL_VREG_LP,
 387         PHYCTRL_SLEW_UP,
 388         PHYTIMING_LPX,
 389         PHYTIMING_HS_EXIT,
 390         PHYTIMING_CLK_PREPARE,
 391         PHYTIMING_CLK_ZERO,
 392         PHYTIMING_CLK_POST,
 393         PHYTIMING_CLK_TRAIL,
 394         PHYTIMING_HS_PREPARE,
 395         PHYTIMING_HS_ZERO,
 396         PHYTIMING_HS_TRAIL
 397 };
 398
 399 static const unsigned int reg_values[] = {
 400         [RESET_TYPE] = DSIM_SWRST,
 401         [PLL_TIMER] = 500,
 402         [STOP_STATE_CNT] = 0xf,
 403         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
 404         [PHYCTRL_VREG_LP] = 0,
 405         [PHYCTRL_SLEW_UP] = 0,
 406         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
 407         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
 408         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
 409         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
 410         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
 411         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
 412         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
 413         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
 414         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
 415 };
 416
 417 static const unsigned int exynos5422_reg_values[] = {
 418         [RESET_TYPE] = DSIM_SWRST,
 419         [PLL_TIMER] = 500,
 420         [STOP_STATE_CNT] = 0xf,
 421         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
 422         [PHYCTRL_VREG_LP] = 0,
 423         [PHYCTRL_SLEW_UP] = 0,
 424         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
 425         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
 426         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 427         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
 428         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 429         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
 430         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
 431         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
 432         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
 433 };
 434
 435 static const unsigned int exynos5433_reg_values[] = {
 436         [RESET_TYPE] = DSIM_FUNCRST,
 437         [PLL_TIMER] = 22200,
 438         [STOP_STATE_CNT] = 0xa,
 439         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
 440         [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
 441         [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
 442         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
 443         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
 444         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 445         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
 446         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 447         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
 448         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
 449         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
 450         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
 451 };
 452
 453 static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
 454         .reg_ofs = exynos_reg_ofs,
 455         .plltmr_reg = 0x50,
 456         .has_freqband = 1,
 457         .has_clklane_stop = 1,
 458         .num_clks = 2,
 459         .max_freq = 1000,
 460         .wait_for_reset = 1,
 461         .num_bits_resol = 11,
 462         .reg_values = reg_values,
 463 };
 464
 465 static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
 466         .reg_ofs = exynos_reg_ofs,
 467         .plltmr_reg = 0x50,
 468         .has_freqband = 1,
 469         .has_clklane_stop = 1,
 470         .num_clks = 2,
 471         .max_freq = 1000,
 472         .wait_for_reset = 1,
 473         .num_bits_resol = 11,
 474         .reg_values = reg_values,
 475 };
 476
 477 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
 478         .reg_ofs = exynos_reg_ofs,
 479         .plltmr_reg = 0x58,
 480         .num_clks = 2,
 481         .max_freq = 1000,
 482         .wait_for_reset = 1,
 483         .num_bits_resol = 11,
 484         .reg_values = reg_values,
 485 };
 486
 487 static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
 488         .reg_ofs = exynos5433_reg_ofs,
 489         .plltmr_reg = 0xa0,
 490         .has_clklane_stop = 1,
 491         .num_clks = 5,
 492         .max_freq = 1500,
 493         .wait_for_reset = 0,
 494         .num_bits_resol = 12,
 495         .reg_values = exynos5433_reg_values,
 496 };
 497
 498 static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
 499         .reg_ofs = exynos5433_reg_ofs,
 500         .plltmr_reg = 0xa0,
 501         .has_clklane_stop = 1,
 502         .num_clks = 2,
 503         .max_freq = 1500,
 504         .wait_for_reset = 1,
 505         .num_bits_resol = 12,
 506         .reg_values = exynos5422_reg_values,
 507 };
 508
 509 static const struct of_device_id exynos_dsi_of_match[] = {
 510         { .compatible = "samsung,exynos3250-mipi-dsi",
 511           .data = &exynos3_dsi_driver_data },
 512         { .compatible = "samsung,exynos4210-mipi-dsi",
 513           .data = &exynos4_dsi_driver_data },
 514         { .compatible = "samsung,exynos5410-mipi-dsi",
 515           .data = &exynos5_dsi_driver_data },
 516         { .compatible = "samsung,exynos5422-mipi-dsi",
 517           .data = &exynos5422_dsi_driver_data },
 518         { .compatible = "samsung,exynos5433-mipi-dsi",
 519           .data = &exynos5433_dsi_driver_data },
 520         { }
 521 };
 522
 523 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
 524 {
 525         if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
 526                 return;
 527
 528         dev_err(dsi->dev, "timeout waiting for reset\n");
 529 }
 530
 531 static void exynos_dsi_reset(struct exynos_dsi *dsi)
 532 {
 533         u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
 534
 535         reinit_completion(&dsi->completed);
 536         exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
 537 }
 538
 539 #ifndef MHZ
 540 #define MHZ     (1000*1000)
 541 #endif
 542
 543 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
 544                 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
 545 {
 546         const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 547         unsigned long best_freq = 0;
 548         u32 min_delta = 0xffffffff;
 549         u8 p_min, p_max;
 550         u8 _p, uninitialized_var(best_p);
 551         u16 _m, uninitialized_var(best_m);
 552         u8 _s, uninitialized_var(best_s);
 553
 554         p_min = DIV_ROUND_UP(fin, (12 * MHZ));
 555         p_max = fin / (6 * MHZ);
 556
 557         for (_p = p_min; _p <= p_max; ++_p) {
 558                 for (_s = 0; _s <= 5; ++_s) {
 559                         u64 tmp;
 560                         u32 delta;
 561
 562                         tmp = (u64)fout * (_p << _s);
 563                         do_div(tmp, fin);
 564                         _m = tmp;
 565                         if (_m < 41 || _m > 125)
 566                                 continue;
 567
 568                         tmp = (u64)_m * fin;
 569                         do_div(tmp, _p);
 570                         if (tmp < 500 * MHZ ||
 571                                         tmp > driver_data->max_freq * MHZ)
 572                                 continue;
 573
 574                         tmp = (u64)_m * fin;
 575                         do_div(tmp, _p << _s);
 576
 577                         delta = abs(fout - tmp);
 578                         if (delta < min_delta) {
 579                                 best_p = _p;
 580                                 best_m = _m;
 581                                 best_s = _s;
 582                                 min_delta = delta;
 583                                 best_freq = tmp;
 584                         }
 585                 }
 586         }
 587
 588         if (best_freq) {
 589                 *p = best_p;
 590                 *m = best_m;
 591                 *s = best_s;
 592         }
 593
 594         return best_freq;
 595 }
 596
 597 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
 598                                         unsigned long freq)
 599 {
 600         const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 601         unsigned long fin, fout;
 602         int timeout;
 603         u8 p, s;
 604         u16 m;
 605         u32 reg;
 606
 607         fin = dsi->pll_clk_rate;
 608         fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
 609         if (!fout) {
 610                 dev_err(dsi->dev,
 611                         "failed to find PLL PMS for requested frequency\n");
 612                 return 0;
 613         }
 614         dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
 615
 616         writel(driver_data->reg_values[PLL_TIMER],
 617                         dsi->reg_base + driver_data->plltmr_reg);
 618
 619         reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
 620
 621         if (driver_data->has_freqband) {
 622                 static const unsigned long freq_bands[] = {
 623                         100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
 624                         270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
 625                         510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
 626                         770 * MHZ, 870 * MHZ, 950 * MHZ,
 627                 };
 628                 int band;
 629
 630                 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
 631                         if (fout < freq_bands[band])
 632                                 break;
 633
 634                 dev_dbg(dsi->dev, "band %d\n", band);
 635
 636                 reg |= DSIM_FREQ_BAND(band);
 637         }
 638
 639         exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
 640
 641         timeout = 1000;
 642         do {
 643                 if (timeout-- == 0) {
 644                         dev_err(dsi->dev, "PLL failed to stabilize\n");
 645                         return 0;
 646                 }
 647                 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
 648         } while ((reg & DSIM_PLL_STABLE) == 0);
 649
 650         return fout;
 651 }
 652
 653 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
 654 {
 655         unsigned long hs_clk, byte_clk, esc_clk;
 656         unsigned long esc_div;
 657         u32 reg;
 658
 659         hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
 660         if (!hs_clk) {
 661                 dev_err(dsi->dev, "failed to configure DSI PLL\n");
 662                 return -EFAULT;
 663         }
 664
 665         byte_clk = hs_clk / 8;
 666         esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
 667         esc_clk = byte_clk / esc_div;
 668
 669         if (esc_clk > 20 * MHZ) {
 670                 ++esc_div;
 671                 esc_clk = byte_clk / esc_div;
 672         }
 673
 674         dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
 675                 hs_clk, byte_clk, esc_clk);
 676
 677         reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
 678         reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
 679                         | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
 680                         | DSIM_BYTE_CLK_SRC_MASK);
 681         reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
 682                         | DSIM_ESC_PRESCALER(esc_div)
 683                         | DSIM_LANE_ESC_CLK_EN_CLK
 684                         | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
 685                         | DSIM_BYTE_CLK_SRC(0)
 686                         | DSIM_TX_REQUEST_HSCLK;
 687         exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
 688
 689         return 0;
 690 }
 691
 692 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
 693 {
 694         const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 695         const unsigned int *reg_values = driver_data->reg_values;
 696         u32 reg;
 697
 698         if (driver_data->has_freqband)
 699                 return;
 700
 701         /* B D-PHY: D-PHY Master & Slave Analog Block control */
 702         reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
 703                 reg_values[PHYCTRL_SLEW_UP];
 704         exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
 705
 706         /*
 707          * T LPX: Transmitted length of any Low-Power state period
 708          * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
 709          *      burst
 710          */
 711         reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
 712         exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
 713
 714         /*
 715          * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
 716          *      Line state immediately before the HS-0 Line state starting the
 717          *      HS transmission
 718          * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
 719          *      transmitting the Clock.
 720          * T CLK_POST: Time that the transmitter continues to send HS clock
 721          *      after the last associated Data Lane has transitioned to LP Mode
 722          *      Interval is defined as the period from the end of T HS-TRAIL to
 723          *      the beginning of T CLK-TRAIL
 724          * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
 725          *      the last payload clock bit of a HS transmission burst
 726          */
 727         reg = reg_values[PHYTIMING_CLK_PREPARE] |
 728                 reg_values[PHYTIMING_CLK_ZERO] |
 729                 reg_values[PHYTIMING_CLK_POST] |
 730                 reg_values[PHYTIMING_CLK_TRAIL];
 731
 732         exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
 733
 734         /*
 735          * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
 736          *      Line state immediately before the HS-0 Line state starting the
 737          *      HS transmission
 738          * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
 739          *      transmitting the Sync sequence.
 740          * T HS-TRAIL: Time that the transmitter drives the flipped differential
 741          *      state after last payload data bit of a HS transmission burst
 742          */
 743         reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
 744                 reg_values[PHYTIMING_HS_TRAIL];
 745         exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
 746 }
 747
 748 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
 749 {
 750         u32 reg;
 751
 752         reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
 753         reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
 754                         | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
 755         exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
 756
 757         reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
 758         reg &= ~DSIM_PLL_EN;
 759         exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
 760 }
 761
 762 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
 763 {
 764         u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
 765         reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
 766                         DSIM_LANE_EN(lane));
 767         exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
 768 }
 769
 770 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
 771 {
 772         const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
 773         int timeout;
 774         u32 reg;
 775         u32 lanes_mask;
 776
 777         /* Initialize FIFO pointers */
 778         reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
 779         reg &= ~0x1f;
 780         exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
 781
 782         usleep_range(9000, 11000);
 783
 784         reg |= 0x1f;
 785         exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
 786         usleep_range(9000, 11000);
 787
 788         /* DSI configuration */
 789         reg = 0;
 790
 791         /*
 792          * The first bit of mode_flags specifies display configuration.
 793          * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
 794          * mode, otherwise it will support command mode.
 795          */
 796         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 797                 reg |= DSIM_VIDEO_MODE;
 798
 799                 /*
 800                  * The user manual describes that following bits are ignored in
 801                  * command mode.
 802                  */
 803                 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
 804                         reg |= DSIM_MFLUSH_VS;
 805                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 806                         reg |= DSIM_SYNC_INFORM;
 807                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 808                         reg |= DSIM_BURST_MODE;
 809                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
 810                         reg |= DSIM_AUTO_MODE;
 811                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
 812                         reg |= DSIM_HSE_MODE;
 813                 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
 814                         reg |= DSIM_HFP_MODE;
 815                 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
 816                         reg |= DSIM_HBP_MODE;
 817                 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
 818                         reg |= DSIM_HSA_MODE;
 819         }
 820
 821         if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
 822                 reg |= DSIM_EOT_DISABLE;
 823
 824         switch (dsi->format) {
 825         case MIPI_DSI_FMT_RGB888:
 826                 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
 827                 break;
 828         case MIPI_DSI_FMT_RGB666:
 829                 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
 830                 break;
 831         case MIPI_DSI_FMT_RGB666_PACKED:
 832                 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
 833                 break;
 834         case MIPI_DSI_FMT_RGB565:
 835                 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
 836                 break;
 837         default:
 838                 dev_err(dsi->dev, "invalid pixel format\n");
 839                 return -EINVAL;
 840         }
 841
 842         /*
 843          * Use non-continuous clock mode if the periparal wants and
 844          * host controller supports
 845          *
 846          * In non-continous clock mode, host controller will turn off
 847          * the HS clock between high-speed transmissions to reduce
 848          * power consumption.
 849          */
 850         if (driver_data->has_clklane_stop &&
 851                         dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
 852                 reg |= DSIM_CLKLANE_STOP;
 853         }
 854         exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
 855
 856         lanes_mask = BIT(dsi->lanes) - 1;
 857         exynos_dsi_enable_lane(dsi, lanes_mask);
 858
 859         /* Check clock and data lane state are stop state */
 860         timeout = 100;
 861         do {
 862                 if (timeout-- == 0) {
 863                         dev_err(dsi->dev, "waiting for bus lanes timed out\n");
 864                         return -EFAULT;
 865                 }
 866
 867                 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
 868                 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
 869                     != DSIM_STOP_STATE_DAT(lanes_mask))
 870                         continue;
 871         } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
 872
 873         reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
 874         reg &= ~DSIM_STOP_STATE_CNT_MASK;
 875         reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
 876         exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
 877
 878         reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
 879         exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
 880
 881         return 0;
 882 }
 883
 884 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
 885 {
 886         struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode;
 887         unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
 888         u32 reg;
 889
 890         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 891                 reg = DSIM_CMD_ALLOW(0xf)
 892                         | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
 893                         | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
 894                 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
 895
 896                 reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
 897                         | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
 898                 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
 899
 900                 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
 901                         | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
 902                 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
 903         }
 904         reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
 905                 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
 906
 907         exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
 908
 909         dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
 910 }
 911
 912 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
 913 {
 914         u32 reg;
 915
 916         reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
 917         if (enable)
 918                 reg |= DSIM_MAIN_STAND_BY;
 919         else
 920                 reg &= ~DSIM_MAIN_STAND_BY;
 921         exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
 922 }
 923
 924 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
 925 {
 926         int timeout = 2000;
 927
 928         do {
 929                 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
 930
 931                 if (!(reg & DSIM_SFR_HEADER_FULL))
 932                         return 0;
 933
 934                 if (!cond_resched())
 935                         usleep_range(950, 1050);
 936         } while (--timeout);
 937
 938         return -ETIMEDOUT;
 939 }
 940
 941 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
 942 {
 943         u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
 944
 945         if (lpm)
 946                 v |= DSIM_CMD_LPDT_LP;
 947         else
 948                 v &= ~DSIM_CMD_LPDT_LP;
 949
 950         exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
 951 }
 952
 953 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
 954 {
 955         u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
 956         v |= DSIM_FORCE_BTA;
 957         exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
 958 }
 959
 960 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
 961                                         struct exynos_dsi_transfer *xfer)
 962 {
 963         struct device *dev = dsi->dev;
 964         struct mipi_dsi_packet *pkt = &xfer->packet;
 965         const u8 *payload = pkt->payload + xfer->tx_done;
 966         u16 length = pkt->payload_length - xfer->tx_done;
 967         bool first = !xfer->tx_done;
 968         u32 reg;
 969
 970         dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
 971                 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
 972
 973         if (length > DSI_TX_FIFO_SIZE)
 974                 length = DSI_TX_FIFO_SIZE;
 975
 976         xfer->tx_done += length;
 977
 978         /* Send payload */
 979         while (length >= 4) {
 980                 reg = get_unaligned_le32(payload);
 981                 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
 982                 payload += 4;
 983                 length -= 4;
 984         }
 985
 986         reg = 0;
 987         switch (length) {
 988         case 3:
 989                 reg |= payload[2] << 16;
 990                 /* Fall through */
 991         case 2:
 992                 reg |= payload[1] << 8;
 993                 /* Fall through */
 994         case 1:
 995                 reg |= payload[0];
 996                 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
 997                 break;
 998         }
 999
1000         /* Send packet header */
1001         if (!first)
1002                 return;
1003
1004         reg = get_unaligned_le32(pkt->header);
1005         if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
1006                 dev_err(dev, "waiting for header FIFO timed out\n");
1007                 return;
1008         }
1009
1010         if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1011                  dsi->state & DSIM_STATE_CMD_LPM)) {
1012                 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1013                 dsi->state ^= DSIM_STATE_CMD_LPM;
1014         }
1015
1016         exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
1017
1018         if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1019                 exynos_dsi_force_bta(dsi);
1020 }
1021
1022 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1023                                         struct exynos_dsi_transfer *xfer)
1024 {
1025         u8 *payload = xfer->rx_payload + xfer->rx_done;
1026         bool first = !xfer->rx_done;
1027         struct device *dev = dsi->dev;
1028         u16 length;
1029         u32 reg;
1030
1031         if (first) {
1032                 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1033
1034                 switch (reg & 0x3f) {
1035                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1036                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1037                         if (xfer->rx_len >= 2) {
1038                                 payload[1] = reg >> 16;
1039                                 ++xfer->rx_done;
1040                         }
1041                         /* Fall through */
1042                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1043                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1044                         payload[0] = reg >> 8;
1045                         ++xfer->rx_done;
1046                         xfer->rx_len = xfer->rx_done;
1047                         xfer->result = 0;
1048                         goto clear_fifo;
1049                 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1050                         dev_err(dev, "DSI Error Report: 0x%04x\n",
1051                                 (reg >> 8) & 0xffff);
1052                         xfer->result = 0;
1053                         goto clear_fifo;
1054                 }
1055
1056                 length = (reg >> 8) & 0xffff;
1057                 if (length > xfer->rx_len) {
1058                         dev_err(dev,
1059                                 "response too long (%u > %u bytes), stripping\n",
1060                                 xfer->rx_len, length);
1061                         length = xfer->rx_len;
1062                 } else if (length < xfer->rx_len)
1063                         xfer->rx_len = length;
1064         }
1065
1066         length = xfer->rx_len - xfer->rx_done;
1067         xfer->rx_done += length;
1068
1069         /* Receive payload */
1070         while (length >= 4) {
1071                 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1072                 payload[0] = (reg >>  0) & 0xff;
1073                 payload[1] = (reg >>  8) & 0xff;
1074                 payload[2] = (reg >> 16) & 0xff;
1075                 payload[3] = (reg >> 24) & 0xff;
1076                 payload += 4;
1077                 length -= 4;
1078         }
1079
1080         if (length) {
1081                 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1082                 switch (length) {
1083                 case 3:
1084                         payload[2] = (reg >> 16) & 0xff;
1085                         /* Fall through */
1086                 case 2:
1087                         payload[1] = (reg >> 8) & 0xff;
1088                         /* Fall through */
1089                 case 1:
1090                         payload[0] = reg & 0xff;
1091                 }
1092         }
1093
1094         if (xfer->rx_done == xfer->rx_len)
1095                 xfer->result = 0;
1096
1097 clear_fifo:
1098         length = DSI_RX_FIFO_SIZE / 4;
1099         do {
1100                 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1101                 if (reg == DSI_RX_FIFO_EMPTY)
1102                         break;
1103         } while (--length);
1104 }
1105
1106 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1107 {
1108         unsigned long flags;
1109         struct exynos_dsi_transfer *xfer;
1110         bool start = false;
1111
1112 again:
1113         spin_lock_irqsave(&dsi->transfer_lock, flags);
1114
1115         if (list_empty(&dsi->transfer_list)) {
1116                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1117                 return;
1118         }
1119
1120         xfer = list_first_entry(&dsi->transfer_list,
1121                                         struct exynos_dsi_transfer, list);
1122
1123         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1124
1125         if (xfer->packet.payload_length &&
1126             xfer->tx_done == xfer->packet.payload_length)
1127                 /* waiting for RX */
1128                 return;
1129
1130         exynos_dsi_send_to_fifo(dsi, xfer);
1131
1132         if (xfer->packet.payload_length || xfer->rx_len)
1133                 return;
1134
1135         xfer->result = 0;
1136         complete(&xfer->completed);
1137
1138         spin_lock_irqsave(&dsi->transfer_lock, flags);
1139
1140         list_del_init(&xfer->list);
1141         start = !list_empty(&dsi->transfer_list);
1142
1143         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1144
1145         if (start)
1146                 goto again;
1147 }
1148
1149 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1150 {
1151         struct exynos_dsi_transfer *xfer;
1152         unsigned long flags;
1153         bool start = true;
1154
1155         spin_lock_irqsave(&dsi->transfer_lock, flags);
1156
1157         if (list_empty(&dsi->transfer_list)) {
1158                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1159                 return false;
1160         }
1161
1162         xfer = list_first_entry(&dsi->transfer_list,
1163                                         struct exynos_dsi_transfer, list);
1164
1165         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1166
1167         dev_dbg(dsi->dev,
1168                 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1169                 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1170                 xfer->rx_done);
1171
1172         if (xfer->tx_done != xfer->packet.payload_length)
1173                 return true;
1174
1175         if (xfer->rx_done != xfer->rx_len)
1176                 exynos_dsi_read_from_fifo(dsi, xfer);
1177
1178         if (xfer->rx_done != xfer->rx_len)
1179                 return true;
1180
1181         spin_lock_irqsave(&dsi->transfer_lock, flags);
1182
1183         list_del_init(&xfer->list);
1184         start = !list_empty(&dsi->transfer_list);
1185
1186         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1187
1188         if (!xfer->rx_len)
1189                 xfer->result = 0;
1190         complete(&xfer->completed);
1191
1192         return start;
1193 }
1194
1195 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1196                                         struct exynos_dsi_transfer *xfer)
1197 {
1198         unsigned long flags;
1199         bool start;
1200
1201         spin_lock_irqsave(&dsi->transfer_lock, flags);
1202
1203         if (!list_empty(&dsi->transfer_list) &&
1204             xfer == list_first_entry(&dsi->transfer_list,
1205                                      struct exynos_dsi_transfer, list)) {
1206                 list_del_init(&xfer->list);
1207                 start = !list_empty(&dsi->transfer_list);
1208                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1209                 if (start)
1210                         exynos_dsi_transfer_start(dsi);
1211                 return;
1212         }
1213
1214         list_del_init(&xfer->list);
1215
1216         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1217 }
1218
1219 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1220                                         struct exynos_dsi_transfer *xfer)
1221 {
1222         unsigned long flags;
1223         bool stopped;
1224
1225         xfer->tx_done = 0;
1226         xfer->rx_done = 0;
1227         xfer->result = -ETIMEDOUT;
1228         init_completion(&xfer->completed);
1229
1230         spin_lock_irqsave(&dsi->transfer_lock, flags);
1231
1232         stopped = list_empty(&dsi->transfer_list);
1233         list_add_tail(&xfer->list, &dsi->transfer_list);
1234
1235         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1236
1237         if (stopped)
1238                 exynos_dsi_transfer_start(dsi);
1239
1240         wait_for_completion_timeout(&xfer->completed,
1241                                     msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1242         if (xfer->result == -ETIMEDOUT) {
1243                 struct mipi_dsi_packet *pkt = &xfer->packet;
1244                 exynos_dsi_remove_transfer(dsi, xfer);
1245                 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1246                         (int)pkt->payload_length, pkt->payload);
1247                 return -ETIMEDOUT;
1248         }
1249
1250         /* Also covers hardware timeout condition */
1251         return xfer->result;
1252 }
1253
1254 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1255 {
1256         struct exynos_dsi *dsi = dev_id;
1257         u32 status;
1258
1259         status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
1260         if (!status) {
1261                 static unsigned long int j;
1262                 if (printk_timed_ratelimit(&j, 500))
1263                         dev_warn(dsi->dev, "spurious interrupt\n");
1264                 return IRQ_HANDLED;
1265         }
1266         exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
1267
1268         if (status & DSIM_INT_SW_RST_RELEASE) {
1269                 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1270                         DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
1271                         DSIM_INT_SW_RST_RELEASE);
1272                 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
1273                 complete(&dsi->completed);
1274                 return IRQ_HANDLED;
1275         }
1276
1277         if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1278                         DSIM_INT_PLL_STABLE)))
1279                 return IRQ_HANDLED;
1280
1281         if (exynos_dsi_transfer_finish(dsi))
1282                 exynos_dsi_transfer_start(dsi);
1283
1284         return IRQ_HANDLED;
1285 }
1286
1287 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1288 {
1289         struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1290         struct drm_encoder *encoder = &dsi->encoder;
1291
1292         if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1293                 exynos_drm_crtc_te_handler(encoder->crtc);
1294
1295         return IRQ_HANDLED;
1296 }
1297
1298 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1299 {
1300         enable_irq(dsi->irq);
1301
1302         if (gpio_is_valid(dsi->te_gpio))
1303                 enable_irq(gpio_to_irq(dsi->te_gpio));
1304 }
1305
1306 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1307 {
1308         if (gpio_is_valid(dsi->te_gpio))
1309                 disable_irq(gpio_to_irq(dsi->te_gpio));
1310
1311         disable_irq(dsi->irq);
1312 }
1313
1314 static int exynos_dsi_init(struct exynos_dsi *dsi)
1315 {
1316         const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1317
1318         exynos_dsi_reset(dsi);
1319         exynos_dsi_enable_irq(dsi);
1320
1321         if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1322                 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1323
1324         exynos_dsi_enable_clock(dsi);
1325         if (driver_data->wait_for_reset)
1326                 exynos_dsi_wait_for_reset(dsi);
1327         exynos_dsi_set_phy_ctrl(dsi);
1328         exynos_dsi_init_link(dsi);
1329
1330         return 0;
1331 }
1332
1333 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
1334                                       struct device *panel)
1335 {
1336         int ret;
1337         int te_gpio_irq;
1338
1339         dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0);
1340         if (dsi->te_gpio == -ENOENT)
1341                 return 0;
1342
1343         if (!gpio_is_valid(dsi->te_gpio)) {
1344                 ret = dsi->te_gpio;
1345                 dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
1346                 goto out;
1347         }
1348
1349         ret = gpio_request(dsi->te_gpio, "te_gpio");
1350         if (ret) {
1351                 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1352                 goto out;
1353         }
1354
1355         te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1356         irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1357
1358         ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1359                                         IRQF_TRIGGER_RISING, "TE", dsi);
1360         if (ret) {
1361                 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1362                 gpio_free(dsi->te_gpio);
1363                 goto out;
1364         }
1365
1366 out:
1367         return ret;
1368 }
1369
1370 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1371 {
1372         if (gpio_is_valid(dsi->te_gpio)) {
1373                 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1374                 gpio_free(dsi->te_gpio);
1375                 dsi->te_gpio = -ENOENT;
1376         }
1377 }
1378
1379 static void exynos_dsi_enable(struct drm_encoder *encoder)
1380 {
1381         struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1382         struct drm_bridge *iter;
1383         int ret;
1384
1385         if (dsi->state & DSIM_STATE_ENABLED)
1386                 return;
1387
1388         pm_runtime_get_sync(dsi->dev);
1389         dsi->state |= DSIM_STATE_ENABLED;
1390
1391         if (dsi->panel) {
1392                 ret = drm_panel_prepare(dsi->panel);
1393                 if (ret < 0)
1394                         goto err_put_sync;
1395         } else {
1396                 list_for_each_entry_reverse(iter, &dsi->bridge_chain,
1397                                             chain_node) {
1398                         if (iter->funcs->pre_enable)
1399                                 iter->funcs->pre_enable(iter);
1400                 }
1401         }
1402
1403         exynos_dsi_set_display_mode(dsi);
1404         exynos_dsi_set_display_enable(dsi, true);
1405
1406         if (dsi->panel) {
1407                 ret = drm_panel_enable(dsi->panel);
1408                 if (ret < 0)
1409                         goto err_display_disable;
1410         } else {
1411                 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1412                         if (iter->funcs->enable)
1413                                 iter->funcs->enable(iter);
1414                 }
1415         }
1416
1417         dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1418         return;
1419
1420 err_display_disable:
1421         exynos_dsi_set_display_enable(dsi, false);
1422         drm_panel_unprepare(dsi->panel);
1423
1424 err_put_sync:
1425         dsi->state &= ~DSIM_STATE_ENABLED;
1426         pm_runtime_put(dsi->dev);
1427 }
1428
1429 static void exynos_dsi_disable(struct drm_encoder *encoder)
1430 {
1431         struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1432         struct drm_bridge *iter;
1433
1434         if (!(dsi->state & DSIM_STATE_ENABLED))
1435                 return;
1436
1437         dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1438
1439         drm_panel_disable(dsi->panel);
1440
1441         list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
1442                 if (iter->funcs->disable)
1443                         iter->funcs->disable(iter);
1444         }
1445
1446         exynos_dsi_set_display_enable(dsi, false);
1447         drm_panel_unprepare(dsi->panel);
1448
1449         list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1450                 if (iter->funcs->post_disable)
1451                         iter->funcs->post_disable(iter);
1452         }
1453
1454         dsi->state &= ~DSIM_STATE_ENABLED;
1455         pm_runtime_put_sync(dsi->dev);
1456 }
1457
1458 static enum drm_connector_status
1459 exynos_dsi_detect(struct drm_connector *connector, bool force)
1460 {
1461         return connector->status;
1462 }
1463
1464 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1465 {
1466         drm_connector_unregister(connector);
1467         drm_connector_cleanup(connector);
1468         connector->dev = NULL;
1469 }
1470
1471 static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
1472         .detect = exynos_dsi_detect,
1473         .fill_modes = drm_helper_probe_single_connector_modes,
1474         .destroy = exynos_dsi_connector_destroy,
1475         .reset = drm_atomic_helper_connector_reset,
1476         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1477         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1478 };
1479
1480 static int exynos_dsi_get_modes(struct drm_connector *connector)
1481 {
1482         struct exynos_dsi *dsi = connector_to_dsi(connector);
1483
1484         if (dsi->panel)
1485                 return drm_panel_get_modes(dsi->panel, connector);
1486
1487         return 0;
1488 }
1489
1490 static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1491         .get_modes = exynos_dsi_get_modes,
1492 };
1493
1494 static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1495 {
1496         struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1497         struct drm_connector *connector = &dsi->connector;
1498         struct drm_device *drm = encoder->dev;
1499         int ret;
1500
1501         connector->polled = DRM_CONNECTOR_POLL_HPD;
1502
1503         ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
1504                                  DRM_MODE_CONNECTOR_DSI);
1505         if (ret) {
1506                 DRM_DEV_ERROR(dsi->dev,
1507                               "Failed to initialize connector with drm\n");
1508                 return ret;
1509         }
1510
1511         connector->status = connector_status_disconnected;
1512         drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1513         drm_connector_attach_encoder(connector, encoder);
1514         if (!drm->registered)
1515                 return 0;
1516
1517         connector->funcs->reset(connector);
1518         drm_connector_register(connector);
1519         return 0;
1520 }
1521
1522 static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1523         .enable = exynos_dsi_enable,
1524         .disable = exynos_dsi_disable,
1525 };
1526
1527 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1528
1529 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1530                                   struct mipi_dsi_device *device)
1531 {
1532         struct exynos_dsi *dsi = host_to_dsi(host);
1533         struct drm_encoder *encoder = &dsi->encoder;
1534         struct drm_device *drm = encoder->dev;
1535         struct drm_bridge *out_bridge;
1536
1537         out_bridge  = of_drm_find_bridge(device->dev.of_node);
1538         if (out_bridge) {
1539                 drm_bridge_attach(encoder, out_bridge, NULL, 0);
1540                 dsi->out_bridge = out_bridge;
1541                 list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain);
1542         } else {
1543                 int ret = exynos_dsi_create_connector(encoder);
1544
1545                 if (ret) {
1546                         DRM_DEV_ERROR(dsi->dev,
1547                                       "failed to create connector ret = %d\n",
1548                                       ret);
1549                         drm_encoder_cleanup(encoder);
1550                         return ret;
1551                 }
1552
1553                 dsi->panel = of_drm_find_panel(device->dev.of_node);
1554                 if (IS_ERR(dsi->panel))
1555                         dsi->panel = NULL;
1556                 else
1557                         dsi->connector.status = connector_status_connected;
1558         }
1559
1560         /*
1561          * This is a temporary solution and should be made by more generic way.
1562          *
1563          * If attached panel device is for command mode one, dsi should register
1564          * TE interrupt handler.
1565          */
1566         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1567                 int ret = exynos_dsi_register_te_irq(dsi, &device->dev);
1568                 if (ret)
1569                         return ret;
1570         }
1571
1572         mutex_lock(&drm->mode_config.mutex);
1573
1574         dsi->lanes = device->lanes;
1575         dsi->format = device->format;
1576         dsi->mode_flags = device->mode_flags;
1577         exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
1578                         !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
1579
1580         mutex_unlock(&drm->mode_config.mutex);
1581
1582         if (drm->mode_config.poll_enabled)
1583                 drm_kms_helper_hotplug_event(drm);
1584
1585         return 0;
1586 }
1587
1588 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1589                                   struct mipi_dsi_device *device)
1590 {
1591         struct exynos_dsi *dsi = host_to_dsi(host);
1592         struct drm_device *drm = dsi->encoder.dev;
1593
1594         if (dsi->panel) {
1595                 mutex_lock(&drm->mode_config.mutex);
1596                 exynos_dsi_disable(&dsi->encoder);
1597                 dsi->panel = NULL;
1598                 dsi->connector.status = connector_status_disconnected;
1599                 mutex_unlock(&drm->mode_config.mutex);
1600         } else {
1601                 if (dsi->out_bridge->funcs->detach)
1602                         dsi->out_bridge->funcs->detach(dsi->out_bridge);
1603                 dsi->out_bridge = NULL;
1604                 INIT_LIST_HEAD(&dsi->bridge_chain);
1605         }
1606
1607         if (drm->mode_config.poll_enabled)
1608                 drm_kms_helper_hotplug_event(drm);
1609
1610         exynos_dsi_unregister_te_irq(dsi);
1611
1612         return 0;
1613 }
1614
1615 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1616                                          const struct mipi_dsi_msg *msg)
1617 {
1618         struct exynos_dsi *dsi = host_to_dsi(host);
1619         struct exynos_dsi_transfer xfer;
1620         int ret;
1621
1622         if (!(dsi->state & DSIM_STATE_ENABLED))
1623                 return -EINVAL;
1624
1625         if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1626                 ret = exynos_dsi_init(dsi);
1627                 if (ret)
1628                         return ret;
1629                 dsi->state |= DSIM_STATE_INITIALIZED;
1630         }
1631
1632         ret = mipi_dsi_create_packet(&xfer.packet, msg);
1633         if (ret < 0)
1634                 return ret;
1635
1636         xfer.rx_len = msg->rx_len;
1637         xfer.rx_payload = msg->rx_buf;
1638         xfer.flags = msg->flags;
1639
1640         ret = exynos_dsi_transfer(dsi, &xfer);
1641         return (ret < 0) ? ret : xfer.rx_done;
1642 }
1643
1644 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1645         .attach = exynos_dsi_host_attach,
1646         .detach = exynos_dsi_host_detach,
1647         .transfer = exynos_dsi_host_transfer,
1648 };
1649
1650 static int exynos_dsi_of_read_u32(const struct device_node *np,
1651                                   const char *propname, u32 *out_value)
1652 {
1653         int ret = of_property_read_u32(np, propname, out_value);
1654
1655         if (ret < 0)
1656                 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1657
1658         return ret;
1659 }
1660
1661 enum {
1662         DSI_PORT_IN,
1663         DSI_PORT_OUT
1664 };
1665
1666 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1667 {
1668         struct device *dev = dsi->dev;
1669         struct device_node *node = dev->of_node;
1670         int ret;
1671
1672         ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1673                                      &dsi->pll_clk_rate);
1674         if (ret < 0)
1675                 return ret;
1676
1677         ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
1678                                      &dsi->burst_clk_rate);
1679         if (ret < 0)
1680                 return ret;
1681
1682         ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
1683                                      &dsi->esc_clk_rate);
1684         if (ret < 0)
1685                 return ret;
1686
1687         dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0);
1688
1689         return 0;
1690 }
1691
1692 static int exynos_dsi_bind(struct device *dev, struct device *master,
1693                                 void *data)
1694 {
1695         struct drm_encoder *encoder = dev_get_drvdata(dev);
1696         struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1697         struct drm_device *drm_dev = data;
1698         struct drm_bridge *in_bridge;
1699         int ret;
1700
1701         drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
1702
1703         drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
1704
1705         ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD);
1706         if (ret < 0)
1707                 return ret;
1708
1709         if (dsi->in_bridge_node) {
1710                 in_bridge = of_drm_find_bridge(dsi->in_bridge_node);
1711                 if (in_bridge)
1712                         drm_bridge_attach(encoder, in_bridge, NULL, 0);
1713         }
1714
1715         return mipi_dsi_host_register(&dsi->dsi_host);
1716 }
1717
1718 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1719                                 void *data)
1720 {
1721         struct drm_encoder *encoder = dev_get_drvdata(dev);
1722         struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1723
1724         exynos_dsi_disable(encoder);
1725
1726         mipi_dsi_host_unregister(&dsi->dsi_host);
1727 }
1728
1729 static const struct component_ops exynos_dsi_component_ops = {
1730         .bind   = exynos_dsi_bind,
1731         .unbind = exynos_dsi_unbind,
1732 };
1733
1734 static int exynos_dsi_probe(struct platform_device *pdev)
1735 {
1736         struct device *dev = &pdev->dev;
1737         struct resource *res;
1738         struct exynos_dsi *dsi;
1739         int ret, i;
1740
1741         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1742         if (!dsi)
1743                 return -ENOMEM;
1744
1745         /* To be checked as invalid one */
1746         dsi->te_gpio = -ENOENT;
1747
1748         init_completion(&dsi->completed);
1749         spin_lock_init(&dsi->transfer_lock);
1750         INIT_LIST_HEAD(&dsi->transfer_list);
1751         INIT_LIST_HEAD(&dsi->bridge_chain);
1752
1753         dsi->dsi_host.ops = &exynos_dsi_ops;
1754         dsi->dsi_host.dev = dev;
1755
1756         dsi->dev = dev;
1757         dsi->driver_data = of_device_get_match_data(dev);
1758
1759         dsi->supplies[0].supply = "vddcore";
1760         dsi->supplies[1].supply = "vddio";
1761         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1762                                       dsi->supplies);
1763         if (ret) {
1764                 if (ret != -EPROBE_DEFER)
1765                         dev_info(dev, "failed to get regulators: %d\n", ret);
1766                 return ret;
1767         }
1768
1769         dsi->clks = devm_kcalloc(dev,
1770                         dsi->driver_data->num_clks, sizeof(*dsi->clks),
1771                         GFP_KERNEL);
1772         if (!dsi->clks)
1773                 return -ENOMEM;
1774
1775         for (i = 0; i < dsi->driver_data->num_clks; i++) {
1776                 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1777                 if (IS_ERR(dsi->clks[i])) {
1778                         if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1779                                 dsi->clks[i] = devm_clk_get(dev,
1780                                                         OLD_SCLK_MIPI_CLK_NAME);
1781                                 if (!IS_ERR(dsi->clks[i]))
1782                                         continue;
1783                         }
1784
1785                         dev_info(dev, "failed to get the clock: %s\n",
1786                                         clk_names[i]);
1787                         return PTR_ERR(dsi->clks[i]);
1788                 }
1789         }
1790
1791         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1792         dsi->reg_base = devm_ioremap_resource(dev, res);
1793         if (IS_ERR(dsi->reg_base)) {
1794                 dev_err(dev, "failed to remap io region\n");
1795                 return PTR_ERR(dsi->reg_base);
1796         }
1797
1798         dsi->phy = devm_phy_get(dev, "dsim");
1799         if (IS_ERR(dsi->phy)) {
1800                 dev_info(dev, "failed to get dsim phy\n");
1801                 return PTR_ERR(dsi->phy);
1802         }
1803
1804         dsi->irq = platform_get_irq(pdev, 0);
1805         if (dsi->irq < 0)
1806                 return dsi->irq;
1807
1808         irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1809         ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1810                                         exynos_dsi_irq, IRQF_ONESHOT,
1811                                         dev_name(dev), dsi);
1812         if (ret) {
1813                 dev_err(dev, "failed to request dsi irq\n");
1814                 return ret;
1815         }
1816
1817         ret = exynos_dsi_parse_dt(dsi);
1818         if (ret)
1819                 return ret;
1820
1821         platform_set_drvdata(pdev, &dsi->encoder);
1822
1823         pm_runtime_enable(dev);
1824
1825         ret = component_add(dev, &exynos_dsi_component_ops);
1826         if (ret)
1827                 goto err_disable_runtime;
1828
1829         return 0;
1830
1831 err_disable_runtime:
1832         pm_runtime_disable(dev);
1833         of_node_put(dsi->in_bridge_node);
1834
1835         return ret;
1836 }
1837
1838 static int exynos_dsi_remove(struct platform_device *pdev)
1839 {
1840         struct exynos_dsi *dsi = platform_get_drvdata(pdev);
1841
1842         of_node_put(dsi->in_bridge_node);
1843
1844         pm_runtime_disable(&pdev->dev);
1845
1846         component_del(&pdev->dev, &exynos_dsi_component_ops);
1847
1848         return 0;
1849 }
1850
1851 static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1852 {
1853         struct drm_encoder *encoder = dev_get_drvdata(dev);
1854         struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1855         const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1856         int ret, i;
1857
1858         usleep_range(10000, 20000);
1859
1860         if (dsi->state & DSIM_STATE_INITIALIZED) {
1861                 dsi->state &= ~DSIM_STATE_INITIALIZED;
1862
1863                 exynos_dsi_disable_clock(dsi);
1864
1865                 exynos_dsi_disable_irq(dsi);
1866         }
1867
1868         dsi->state &= ~DSIM_STATE_CMD_LPM;
1869
1870         phy_power_off(dsi->phy);
1871
1872         for (i = driver_data->num_clks - 1; i > -1; i--)
1873                 clk_disable_unprepare(dsi->clks[i]);
1874
1875         ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1876         if (ret < 0)
1877                 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1878
1879         return 0;
1880 }
1881
1882 static int __maybe_unused exynos_dsi_resume(struct device *dev)
1883 {
1884         struct drm_encoder *encoder = dev_get_drvdata(dev);
1885         struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1886         const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1887         int ret, i;
1888
1889         ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1890         if (ret < 0) {
1891                 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1892                 return ret;
1893         }
1894
1895         for (i = 0; i < driver_data->num_clks; i++) {
1896                 ret = clk_prepare_enable(dsi->clks[i]);
1897                 if (ret < 0)
1898                         goto err_clk;
1899         }
1900
1901         ret = phy_power_on(dsi->phy);
1902         if (ret < 0) {
1903                 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1904                 goto err_clk;
1905         }
1906
1907         return 0;
1908
1909 err_clk:
1910         while (--i > -1)
1911                 clk_disable_unprepare(dsi->clks[i]);
1912         regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1913
1914         return ret;
1915 }
1916
1917 static const struct dev_pm_ops exynos_dsi_pm_ops = {
1918         SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
1919         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1920                                 pm_runtime_force_resume)
1921 };
1922
1923 struct platform_driver dsi_driver = {
1924         .probe = exynos_dsi_probe,
1925         .remove = exynos_dsi_remove,
1926         .driver = {
1927                    .name = "exynos-dsi",
1928                    .owner = THIS_MODULE,
1929                    .pm = &exynos_dsi_pm_ops,
1930                    .of_match_table = exynos_dsi_of_match,
1931         },
1932 };
1933
1934 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1935 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1936 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1937 MODULE_LICENSE("GPL v2");