1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <drm/exynos_drm.h>
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <linux/kernel.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/exynos7_decon.h>
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_plane.h"
32 #include "exynos_drm_drv.h"
33 #include "exynos_drm_fb.h"
34 #include "exynos_drm_iommu.h"
37 * DECON stands for Display and Enhancement controller.
40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
44 struct decon_context {
46 struct drm_device *drm_dev;
47 struct exynos_drm_crtc *crtc;
48 struct exynos_drm_plane planes[WINDOWS_NR];
49 struct exynos_drm_plane_config configs[WINDOWS_NR];
55 unsigned long irq_flags;
59 wait_queue_head_t wait_vsync_queue;
60 atomic_t wait_vsync_event;
62 struct drm_encoder *encoder;
65 static const struct of_device_id decon_driver_dt_match[] = {
66 {.compatible = "samsung,exynos7-decon"},
69 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
71 static const uint32_t decon_formats[] = {
83 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
84 DRM_PLANE_TYPE_PRIMARY,
85 DRM_PLANE_TYPE_CURSOR,
88 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
90 struct decon_context *ctx = crtc->ctx;
95 atomic_set(&ctx->wait_vsync_event, 1);
98 * wait for DECON to signal VSYNC interrupt or return after
99 * timeout which is set to 50ms (refresh rate of 20).
101 if (!wait_event_timeout(ctx->wait_vsync_queue,
102 !atomic_read(&ctx->wait_vsync_event),
104 DRM_DEBUG_KMS("vblank wait timed out.\n");
107 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
109 struct decon_context *ctx = crtc->ctx;
110 unsigned int win, ch_enabled = 0;
112 DRM_DEBUG_KMS("%s\n", __FILE__);
114 /* Check if any channel is enabled. */
115 for (win = 0; win < WINDOWS_NR; win++) {
116 u32 val = readl(ctx->regs + WINCON(win));
118 if (val & WINCONx_ENWIN) {
119 val &= ~WINCONx_ENWIN;
120 writel(val, ctx->regs + WINCON(win));
125 /* Wait for vsync, as disable channel takes effect at next vsync */
127 decon_wait_for_vblank(ctx->crtc);
130 static int decon_ctx_initialize(struct decon_context *ctx,
131 struct drm_device *drm_dev)
133 struct exynos_drm_private *priv = drm_dev->dev_private;
136 ctx->drm_dev = drm_dev;
137 ctx->pipe = priv->pipe++;
139 decon_clear_channels(ctx->crtc);
141 ret = drm_iommu_attach_device(drm_dev, ctx->dev);
148 static void decon_ctx_remove(struct decon_context *ctx)
150 /* detach this sub driver from iommu mapping if supported. */
151 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
154 static u32 decon_calc_clkdiv(struct decon_context *ctx,
155 const struct drm_display_mode *mode)
157 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
160 /* Find the clock divider value that gets us closest to ideal_clk */
161 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
163 return (clkdiv < 0x100) ? clkdiv : 0xff;
166 static void decon_commit(struct exynos_drm_crtc *crtc)
168 struct decon_context *ctx = crtc->ctx;
169 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
175 /* nothing to do if we haven't set the mode yet */
176 if (mode->htotal == 0 || mode->vtotal == 0)
180 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
181 /* setup vertical timing values. */
182 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
183 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
184 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
186 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
187 writel(val, ctx->regs + VIDTCON0);
189 val = VIDTCON1_VSPW(vsync_len - 1);
190 writel(val, ctx->regs + VIDTCON1);
192 /* setup horizontal timing values. */
193 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
194 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
195 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
197 /* setup horizontal timing values. */
198 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
199 writel(val, ctx->regs + VIDTCON2);
201 val = VIDTCON3_HSPW(hsync_len - 1);
202 writel(val, ctx->regs + VIDTCON3);
205 /* setup horizontal and vertical display size. */
206 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
207 VIDTCON4_HOZVAL(mode->hdisplay - 1);
208 writel(val, ctx->regs + VIDTCON4);
210 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
213 * fields of register with prefix '_F' would be updated
214 * at vsync(same as dma start)
216 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
217 writel(val, ctx->regs + VIDCON0);
219 clkdiv = decon_calc_clkdiv(ctx, mode);
221 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
222 writel(val, ctx->regs + VCLKCON1);
223 writel(val, ctx->regs + VCLKCON2);
226 val = readl(ctx->regs + DECON_UPDATE);
227 val |= DECON_UPDATE_STANDALONE_F;
228 writel(val, ctx->regs + DECON_UPDATE);
231 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
233 struct decon_context *ctx = crtc->ctx;
239 if (!test_and_set_bit(0, &ctx->irq_flags)) {
240 val = readl(ctx->regs + VIDINTCON0);
242 val |= VIDINTCON0_INT_ENABLE;
245 val |= VIDINTCON0_INT_FRAME;
246 val &= ~VIDINTCON0_FRAMESEL0_MASK;
247 val |= VIDINTCON0_FRAMESEL0_VSYNC;
250 writel(val, ctx->regs + VIDINTCON0);
256 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
258 struct decon_context *ctx = crtc->ctx;
264 if (test_and_clear_bit(0, &ctx->irq_flags)) {
265 val = readl(ctx->regs + VIDINTCON0);
267 val &= ~VIDINTCON0_INT_ENABLE;
269 val &= ~VIDINTCON0_INT_FRAME;
271 writel(val, ctx->regs + VIDINTCON0);
275 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
276 struct drm_framebuffer *fb)
281 val = readl(ctx->regs + WINCON(win));
282 val &= ~WINCONx_BPPMODE_MASK;
284 switch (fb->format->format) {
285 case DRM_FORMAT_RGB565:
286 val |= WINCONx_BPPMODE_16BPP_565;
287 val |= WINCONx_BURSTLEN_16WORD;
289 case DRM_FORMAT_XRGB8888:
290 val |= WINCONx_BPPMODE_24BPP_xRGB;
291 val |= WINCONx_BURSTLEN_16WORD;
293 case DRM_FORMAT_XBGR8888:
294 val |= WINCONx_BPPMODE_24BPP_xBGR;
295 val |= WINCONx_BURSTLEN_16WORD;
297 case DRM_FORMAT_RGBX8888:
298 val |= WINCONx_BPPMODE_24BPP_RGBx;
299 val |= WINCONx_BURSTLEN_16WORD;
301 case DRM_FORMAT_BGRX8888:
302 val |= WINCONx_BPPMODE_24BPP_BGRx;
303 val |= WINCONx_BURSTLEN_16WORD;
305 case DRM_FORMAT_ARGB8888:
306 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
308 val |= WINCONx_BURSTLEN_16WORD;
310 case DRM_FORMAT_ABGR8888:
311 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
313 val |= WINCONx_BURSTLEN_16WORD;
315 case DRM_FORMAT_RGBA8888:
316 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
318 val |= WINCONx_BURSTLEN_16WORD;
320 case DRM_FORMAT_BGRA8888:
321 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
323 val |= WINCONx_BURSTLEN_16WORD;
326 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
328 val |= WINCONx_BPPMODE_24BPP_xRGB;
329 val |= WINCONx_BURSTLEN_16WORD;
333 DRM_DEBUG_KMS("bpp = %d\n", fb->format->cpp[0] * 8);
336 * In case of exynos, setting dma-burst to 16Word causes permanent
337 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
338 * switching which is based on plane size is not recommended as
339 * plane size varies a lot towards the end of the screen and rapid
340 * movement causes unstable DMA which results into iommu crash/tear.
343 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
344 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
345 val &= ~WINCONx_BURSTLEN_MASK;
346 val |= WINCONx_BURSTLEN_8WORD;
349 writel(val, ctx->regs + WINCON(win));
352 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
354 unsigned int keycon0 = 0, keycon1 = 0;
356 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
357 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
359 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
361 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
362 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
366 * shadow_protect_win() - disable updating values from shadow registers at vsync
368 * @win: window to protect registers for
369 * @protect: 1 to protect (disable updates)
371 static void decon_shadow_protect_win(struct decon_context *ctx,
372 unsigned int win, bool protect)
376 bits = SHADOWCON_WINx_PROTECT(win);
378 val = readl(ctx->regs + SHADOWCON);
383 writel(val, ctx->regs + SHADOWCON);
386 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
388 struct decon_context *ctx = crtc->ctx;
394 for (i = 0; i < WINDOWS_NR; i++)
395 decon_shadow_protect_win(ctx, i, true);
398 static void decon_update_plane(struct exynos_drm_crtc *crtc,
399 struct exynos_drm_plane *plane)
401 struct exynos_drm_plane_state *state =
402 to_exynos_plane_state(plane->base.state);
403 struct decon_context *ctx = crtc->ctx;
404 struct drm_framebuffer *fb = state->base.fb;
406 unsigned long val, alpha;
409 unsigned int win = plane->index;
410 unsigned int bpp = fb->format->cpp[0];
411 unsigned int pitch = fb->pitches[0];
417 * SHADOWCON/PRTCON register is used for enabling timing.
419 * for example, once only width value of a register is set,
420 * if the dma is started then decon hardware could malfunction so
421 * with protect window setting, the register fields with prefix '_F'
422 * wouldn't be updated at vsync also but updated once unprotect window
426 /* buffer start address */
427 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
428 writel(val, ctx->regs + VIDW_BUF_START(win));
430 padding = (pitch / bpp) - fb->width;
433 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
434 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
436 /* offset from the start of the buffer to read */
437 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
438 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
440 DRM_DEBUG_KMS("start addr = 0x%lx\n",
442 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
443 state->crtc.w, state->crtc.h);
445 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
446 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
447 writel(val, ctx->regs + VIDOSD_A(win));
449 last_x = state->crtc.x + state->crtc.w;
452 last_y = state->crtc.y + state->crtc.h;
456 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
458 writel(val, ctx->regs + VIDOSD_B(win));
460 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
461 state->crtc.x, state->crtc.y, last_x, last_y);
464 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
465 VIDOSDxC_ALPHA0_G_F(0x0) |
466 VIDOSDxC_ALPHA0_B_F(0x0);
468 writel(alpha, ctx->regs + VIDOSD_C(win));
470 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
471 VIDOSDxD_ALPHA1_G_F(0xff) |
472 VIDOSDxD_ALPHA1_B_F(0xff);
474 writel(alpha, ctx->regs + VIDOSD_D(win));
476 decon_win_set_pixfmt(ctx, win, fb);
478 /* hardware window 0 doesn't support color key. */
480 decon_win_set_colkey(ctx, win);
483 val = readl(ctx->regs + WINCON(win));
484 val |= WINCONx_TRIPLE_BUF_MODE;
485 val |= WINCONx_ENWIN;
486 writel(val, ctx->regs + WINCON(win));
488 /* Enable DMA channel and unprotect windows */
489 decon_shadow_protect_win(ctx, win, false);
491 val = readl(ctx->regs + DECON_UPDATE);
492 val |= DECON_UPDATE_STANDALONE_F;
493 writel(val, ctx->regs + DECON_UPDATE);
496 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
497 struct exynos_drm_plane *plane)
499 struct decon_context *ctx = crtc->ctx;
500 unsigned int win = plane->index;
506 /* protect windows */
507 decon_shadow_protect_win(ctx, win, true);
510 val = readl(ctx->regs + WINCON(win));
511 val &= ~WINCONx_ENWIN;
512 writel(val, ctx->regs + WINCON(win));
514 val = readl(ctx->regs + DECON_UPDATE);
515 val |= DECON_UPDATE_STANDALONE_F;
516 writel(val, ctx->regs + DECON_UPDATE);
519 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
521 struct decon_context *ctx = crtc->ctx;
527 for (i = 0; i < WINDOWS_NR; i++)
528 decon_shadow_protect_win(ctx, i, false);
529 exynos_crtc_handle_event(crtc);
532 static void decon_init(struct decon_context *ctx)
536 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
538 val = VIDOUTCON0_DISP_IF_0_ON;
540 val |= VIDOUTCON0_RGBIF;
541 writel(val, ctx->regs + VIDOUTCON0);
543 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
546 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
549 static void decon_enable(struct exynos_drm_crtc *crtc)
551 struct decon_context *ctx = crtc->ctx;
556 pm_runtime_get_sync(ctx->dev);
560 /* if vblank was enabled status, enable it again. */
561 if (test_and_clear_bit(0, &ctx->irq_flags))
562 decon_enable_vblank(ctx->crtc);
564 decon_commit(ctx->crtc);
566 ctx->suspended = false;
569 static void decon_disable(struct exynos_drm_crtc *crtc)
571 struct decon_context *ctx = crtc->ctx;
578 * We need to make sure that all windows are disabled before we
579 * suspend that connector. Otherwise we might try to scan from
580 * a destroyed buffer later.
582 for (i = 0; i < WINDOWS_NR; i++)
583 decon_disable_plane(crtc, &ctx->planes[i]);
585 pm_runtime_put_sync(ctx->dev);
587 ctx->suspended = true;
590 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
591 .enable = decon_enable,
592 .disable = decon_disable,
593 .commit = decon_commit,
594 .enable_vblank = decon_enable_vblank,
595 .disable_vblank = decon_disable_vblank,
596 .atomic_begin = decon_atomic_begin,
597 .update_plane = decon_update_plane,
598 .disable_plane = decon_disable_plane,
599 .atomic_flush = decon_atomic_flush,
603 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
605 struct decon_context *ctx = (struct decon_context *)dev_id;
608 val = readl(ctx->regs + VIDINTCON1);
610 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
612 writel(clear_bit, ctx->regs + VIDINTCON1);
614 /* check the crtc is detached already from encoder */
615 if (ctx->pipe < 0 || !ctx->drm_dev)
619 drm_crtc_handle_vblank(&ctx->crtc->base);
621 /* set wait vsync event to zero and wake up queue. */
622 if (atomic_read(&ctx->wait_vsync_event)) {
623 atomic_set(&ctx->wait_vsync_event, 0);
624 wake_up(&ctx->wait_vsync_queue);
631 static int decon_bind(struct device *dev, struct device *master, void *data)
633 struct decon_context *ctx = dev_get_drvdata(dev);
634 struct drm_device *drm_dev = data;
635 struct exynos_drm_plane *exynos_plane;
639 ret = decon_ctx_initialize(ctx, drm_dev);
641 DRM_ERROR("decon_ctx_initialize failed.\n");
645 for (i = 0; i < WINDOWS_NR; i++) {
646 ctx->configs[i].pixel_formats = decon_formats;
647 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
648 ctx->configs[i].zpos = i;
649 ctx->configs[i].type = decon_win_types[i];
651 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
652 1 << ctx->pipe, &ctx->configs[i]);
657 exynos_plane = &ctx->planes[DEFAULT_WIN];
658 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
659 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
660 &decon_crtc_ops, ctx);
661 if (IS_ERR(ctx->crtc)) {
662 decon_ctx_remove(ctx);
663 return PTR_ERR(ctx->crtc);
667 exynos_dpi_bind(drm_dev, ctx->encoder);
673 static void decon_unbind(struct device *dev, struct device *master,
676 struct decon_context *ctx = dev_get_drvdata(dev);
678 decon_disable(ctx->crtc);
681 exynos_dpi_remove(ctx->encoder);
683 decon_ctx_remove(ctx);
686 static const struct component_ops decon_component_ops = {
688 .unbind = decon_unbind,
691 static int decon_probe(struct platform_device *pdev)
693 struct device *dev = &pdev->dev;
694 struct decon_context *ctx;
695 struct device_node *i80_if_timings;
696 struct resource *res;
702 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
707 ctx->suspended = true;
709 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
712 of_node_put(i80_if_timings);
714 ctx->regs = of_iomap(dev->of_node, 0);
718 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
719 if (IS_ERR(ctx->pclk)) {
720 dev_err(dev, "failed to get bus clock pclk\n");
721 ret = PTR_ERR(ctx->pclk);
725 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
726 if (IS_ERR(ctx->aclk)) {
727 dev_err(dev, "failed to get bus clock aclk\n");
728 ret = PTR_ERR(ctx->aclk);
732 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
733 if (IS_ERR(ctx->eclk)) {
734 dev_err(dev, "failed to get eclock\n");
735 ret = PTR_ERR(ctx->eclk);
739 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
740 if (IS_ERR(ctx->vclk)) {
741 dev_err(dev, "failed to get vclock\n");
742 ret = PTR_ERR(ctx->vclk);
746 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
747 ctx->i80_if ? "lcd_sys" : "vsync");
749 dev_err(dev, "irq request failed.\n");
754 ret = devm_request_irq(dev, res->start, decon_irq_handler,
755 0, "drm_decon", ctx);
757 dev_err(dev, "irq request failed.\n");
761 init_waitqueue_head(&ctx->wait_vsync_queue);
762 atomic_set(&ctx->wait_vsync_event, 0);
764 platform_set_drvdata(pdev, ctx);
766 ctx->encoder = exynos_dpi_probe(dev);
767 if (IS_ERR(ctx->encoder)) {
768 ret = PTR_ERR(ctx->encoder);
772 pm_runtime_enable(dev);
774 ret = component_add(dev, &decon_component_ops);
776 goto err_disable_pm_runtime;
780 err_disable_pm_runtime:
781 pm_runtime_disable(dev);
789 static int decon_remove(struct platform_device *pdev)
791 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
793 pm_runtime_disable(&pdev->dev);
797 component_del(&pdev->dev, &decon_component_ops);
803 static int exynos7_decon_suspend(struct device *dev)
805 struct decon_context *ctx = dev_get_drvdata(dev);
807 clk_disable_unprepare(ctx->vclk);
808 clk_disable_unprepare(ctx->eclk);
809 clk_disable_unprepare(ctx->aclk);
810 clk_disable_unprepare(ctx->pclk);
815 static int exynos7_decon_resume(struct device *dev)
817 struct decon_context *ctx = dev_get_drvdata(dev);
820 ret = clk_prepare_enable(ctx->pclk);
822 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
826 ret = clk_prepare_enable(ctx->aclk);
828 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
832 ret = clk_prepare_enable(ctx->eclk);
834 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
838 ret = clk_prepare_enable(ctx->vclk);
840 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
848 static const struct dev_pm_ops exynos7_decon_pm_ops = {
849 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
853 struct platform_driver decon_driver = {
854 .probe = decon_probe,
855 .remove = decon_remove,
857 .name = "exynos-decon",
858 .pm = &exynos7_decon_pm_ops,
859 .of_match_table = decon_driver_dt_match,