drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* drivers/gpu/drm/exynos5433_drm_decon.c
   3  *
   4  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   5  * Authors:
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *      Hyungwon Hwang <human.hwang@samsung.com>
   8  */
   9
  10 #include <linux/platform_device.h>
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/irq.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20
  21 #include "exynos_drm_drv.h"
  22 #include "exynos_drm_crtc.h"
  23 #include "exynos_drm_fb.h"
  24 #include "exynos_drm_plane.h"
  25 #include "regs-decon5433.h"
  26
  27 #define DSD_CFG_MUX 0x1004
  28 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  29
  30 #define WINDOWS_NR      5
  31 #define PRIMARY_WIN     2
  32 #define CURSON_WIN      4
  33
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define I80_HW_TRG      (1 << 0)
  37 #define IFTYPE_HDMI     (1 << 1)
  38
  39 static const char * const decon_clks_name[] = {
  40         "pclk",
  41         "aclk_decon",
  42         "aclk_smmu_decon0x",
  43         "aclk_xiu_decon0x",
  44         "pclk_smmu_decon0x",
  45         "aclk_smmu_decon1x",
  46         "aclk_xiu_decon1x",
  47         "pclk_smmu_decon1x",
  48         "sclk_decon_vclk",
  49         "sclk_decon_eclk",
  50 };
  51
  52 struct decon_context {
  53         struct device                   *dev;
  54         struct drm_device               *drm_dev;
  55         struct exynos_drm_crtc          *crtc;
  56         struct exynos_drm_plane         planes[WINDOWS_NR];
  57         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  58         void __iomem                    *addr;
  59         struct regmap                   *sysreg;
  60         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  61         unsigned int                    irq;
  62         unsigned int                    irq_vsync;
  63         unsigned int                    irq_lcd_sys;
  64         unsigned int                    te_irq;
  65         unsigned long                   out_type;
  66         int                             first_win;
  67         spinlock_t                      vblank_lock;
  68         u32                             frame_id;
  69 };
  70
  71 static const uint32_t decon_formats[] = {
  72         DRM_FORMAT_XRGB1555,
  73         DRM_FORMAT_RGB565,
  74         DRM_FORMAT_XRGB8888,
  75         DRM_FORMAT_ARGB8888,
  76 };
  77
  78 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  79         [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
  80         [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
  81 };
  82
  83 static const unsigned int capabilities[WINDOWS_NR] = {
  84         0,
  85         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  86         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  87         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  88         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
  89 };
  90
  91 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  92                                   u32 val)
  93 {
  94         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  95         writel(val, ctx->addr + reg);
  96 }
  97
  98 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  99 {
 100         struct decon_context *ctx = crtc->ctx;
 101         u32 val;
 102
 103         val = VIDINTCON0_INTEN;
 104         if (crtc->i80_mode)
 105                 val |= VIDINTCON0_FRAMEDONE;
 106         else
 107                 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 108
 109         writel(val, ctx->addr + DECON_VIDINTCON0);
 110
 111         enable_irq(ctx->irq);
 112         if (!(ctx->out_type & I80_HW_TRG))
 113                 enable_irq(ctx->te_irq);
 114
 115         return 0;
 116 }
 117
 118 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 119 {
 120         struct decon_context *ctx = crtc->ctx;
 121
 122         if (!(ctx->out_type & I80_HW_TRG))
 123                 disable_irq_nosync(ctx->te_irq);
 124         disable_irq_nosync(ctx->irq);
 125
 126         writel(0, ctx->addr + DECON_VIDINTCON0);
 127 }
 128
 129 /* return number of starts/ends of frame transmissions since reset */
 130 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 131 {
 132         u32 frm, pfrm, status, cnt = 2;
 133
 134         /* To get consistent result repeat read until frame id is stable.
 135          * Usually the loop will be executed once, in rare cases when the loop
 136          * is executed at frame change time 2nd pass will be needed.
 137          */
 138         frm = readl(ctx->addr + DECON_CRFMID);
 139         do {
 140                 status = readl(ctx->addr + DECON_VIDCON1);
 141                 pfrm = frm;
 142                 frm = readl(ctx->addr + DECON_CRFMID);
 143         } while (frm != pfrm && --cnt);
 144
 145         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 146          * of RGB, it should be taken into account.
 147          */
 148         if (!frm)
 149                 return 0;
 150
 151         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 152         case VIDCON1_VSTATUS_VS:
 153                 if (!(ctx->crtc->i80_mode))
 154                         --frm;
 155                 break;
 156         case VIDCON1_VSTATUS_BP:
 157                 --frm;
 158                 break;
 159         case VIDCON1_I80_ACTIVE:
 160         case VIDCON1_VSTATUS_AC:
 161                 if (end)
 162                         --frm;
 163                 break;
 164         default:
 165                 break;
 166         }
 167
 168         return frm;
 169 }
 170
 171 static void decon_setup_trigger(struct decon_context *ctx)
 172 {
 173         if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
 174                 return;
 175
 176         if (!(ctx->out_type & I80_HW_TRG)) {
 177                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 178                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 179                        ctx->addr + DECON_TRIGCON);
 180                 return;
 181         }
 182
 183         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 184                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 185
 186         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 187                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 188                 DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
 189 }
 190
 191 static void decon_commit(struct exynos_drm_crtc *crtc)
 192 {
 193         struct decon_context *ctx = crtc->ctx;
 194         struct drm_display_mode *m = &crtc->base.mode;
 195         bool interlaced = false;
 196         u32 val;
 197
 198         if (ctx->out_type & IFTYPE_HDMI) {
 199                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 200                 m->crtc_hsync_end = m->crtc_htotal - 92;
 201                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 202                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 203                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 204                         interlaced = true;
 205         }
 206
 207         decon_setup_trigger(ctx);
 208
 209         /* lcd on and use command if */
 210         val = VIDOUT_LCD_ON;
 211         if (interlaced)
 212                 val |= VIDOUT_INTERLACE_EN_F;
 213         if (crtc->i80_mode) {
 214                 val |= VIDOUT_COMMAND_IF;
 215         } else {
 216                 val |= VIDOUT_RGB_IF;
 217         }
 218
 219         writel(val, ctx->addr + DECON_VIDOUTCON0);
 220
 221         if (interlaced)
 222                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 223                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 224         else
 225                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 226                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 227         writel(val, ctx->addr + DECON_VIDTCON2);
 228
 229         if (!crtc->i80_mode) {
 230                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 231                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 232
 233                 if (interlaced)
 234                         vbp = vbp / 2 - 1;
 235                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 236                 writel(val, ctx->addr + DECON_VIDTCON00);
 237
 238                 val = VIDTCON01_VSPW_F(
 239                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 240                 writel(val, ctx->addr + DECON_VIDTCON01);
 241
 242                 val = VIDTCON10_HBPD_F(
 243                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 244                         VIDTCON10_HFPD_F(
 245                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 246                 writel(val, ctx->addr + DECON_VIDTCON10);
 247
 248                 val = VIDTCON11_HSPW_F(
 249                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 250                 writel(val, ctx->addr + DECON_VIDTCON11);
 251         }
 252
 253         /* enable output and display signal */
 254         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 255
 256         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 257 }
 258
 259 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
 260                                 unsigned int alpha, unsigned int pixel_alpha)
 261 {
 262         u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf);
 263         u32 val = 0;
 264
 265         switch (pixel_alpha) {
 266         case DRM_MODE_BLEND_PIXEL_NONE:
 267         case DRM_MODE_BLEND_COVERAGE:
 268                 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A);
 269                 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
 270                 break;
 271         case DRM_MODE_BLEND_PREMULTI:
 272         default:
 273                 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
 274                         val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0);
 275                         val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
 276                 } else {
 277                         val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE);
 278                         val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
 279                 }
 280                 break;
 281         }
 282         decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
 283 }
 284
 285 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
 286                                  unsigned int alpha, unsigned int pixel_alpha)
 287 {
 288         u32 win_alpha = alpha >> 8;
 289         u32 val = 0;
 290
 291         switch (pixel_alpha) {
 292         case DRM_MODE_BLEND_PIXEL_NONE:
 293                 break;
 294         case DRM_MODE_BLEND_COVERAGE:
 295         case DRM_MODE_BLEND_PREMULTI:
 296         default:
 297                 val |= WINCONx_ALPHA_SEL_F;
 298                 val |= WINCONx_BLD_PIX_F;
 299                 val |= WINCONx_ALPHA_MUL_F;
 300                 break;
 301         }
 302         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
 303
 304         if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
 305                 val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
 306                       VIDOSD_Wx_ALPHA_G_F(win_alpha) |
 307                       VIDOSD_Wx_ALPHA_B_F(win_alpha);
 308                 decon_set_bits(ctx, DECON_VIDOSDxC(win),
 309                                VIDOSDxC_ALPHA0_RGB_MASK, val);
 310                 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
 311         }
 312 }
 313
 314 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 315                                  struct drm_framebuffer *fb)
 316 {
 317         struct exynos_drm_plane plane = ctx->planes[win];
 318         struct exynos_drm_plane_state *state =
 319                 to_exynos_plane_state(plane.base.state);
 320         unsigned int alpha = state->base.alpha;
 321         unsigned int pixel_alpha;
 322         unsigned long val;
 323
 324         if (fb->format->has_alpha)
 325                 pixel_alpha = state->base.pixel_blend_mode;
 326         else
 327                 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
 328
 329         val = readl(ctx->addr + DECON_WINCONx(win));
 330         val &= WINCONx_ENWIN_F;
 331
 332         switch (fb->format->format) {
 333         case DRM_FORMAT_XRGB1555:
 334                 val |= WINCONx_BPPMODE_16BPP_I1555;
 335                 val |= WINCONx_HAWSWP_F;
 336                 val |= WINCONx_BURSTLEN_16WORD;
 337                 break;
 338         case DRM_FORMAT_RGB565:
 339                 val |= WINCONx_BPPMODE_16BPP_565;
 340                 val |= WINCONx_HAWSWP_F;
 341                 val |= WINCONx_BURSTLEN_16WORD;
 342                 break;
 343         case DRM_FORMAT_XRGB8888:
 344                 val |= WINCONx_BPPMODE_24BPP_888;
 345                 val |= WINCONx_WSWP_F;
 346                 val |= WINCONx_BURSTLEN_16WORD;
 347                 break;
 348         case DRM_FORMAT_ARGB8888:
 349         default:
 350                 val |= WINCONx_BPPMODE_32BPP_A8888;
 351                 val |= WINCONx_WSWP_F;
 352                 val |= WINCONx_BURSTLEN_16WORD;
 353                 break;
 354         }
 355
 356         DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
 357
 358         /*
 359          * In case of exynos, setting dma-burst to 16Word causes permanent
 360          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 361          * switching which is based on plane size is not recommended as
 362          * plane size varies a lot towards the end of the screen and rapid
 363          * movement causes unstable DMA which results into iommu crash/tear.
 364          */
 365
 366         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 367                 val &= ~WINCONx_BURSTLEN_MASK;
 368                 val |= WINCONx_BURSTLEN_8WORD;
 369         }
 370         decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
 371
 372         if (win > 0) {
 373                 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
 374                 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
 375         }
 376 }
 377
 378 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
 379 {
 380         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
 381                        protect ? ~0 : 0);
 382 }
 383
 384 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 385 {
 386         struct decon_context *ctx = crtc->ctx;
 387
 388         decon_shadow_protect(ctx, true);
 389 }
 390
 391 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 392 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 393 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 394
 395 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 396                                struct exynos_drm_plane *plane)
 397 {
 398         struct exynos_drm_plane_state *state =
 399                                 to_exynos_plane_state(plane->base.state);
 400         struct decon_context *ctx = crtc->ctx;
 401         struct drm_framebuffer *fb = state->base.fb;
 402         unsigned int win = plane->index;
 403         unsigned int cpp = fb->format->cpp[0];
 404         unsigned int pitch = fb->pitches[0];
 405         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 406         u32 val;
 407
 408         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 409                 val = COORDINATE_X(state->crtc.x) |
 410                         COORDINATE_Y(state->crtc.y / 2);
 411                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 412
 413                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 414                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 415                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 416         } else {
 417                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 418                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 419
 420                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 421                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 422                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 423         }
 424
 425         val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
 426                 VIDOSD_Wx_ALPHA_B_F(0xff);
 427         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 428
 429         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 430                 VIDOSD_Wx_ALPHA_B_F(0x0);
 431         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 432
 433         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 434
 435         val = dma_addr + pitch * state->src.h;
 436         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 437
 438         if (!(ctx->out_type & IFTYPE_HDMI))
 439                 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
 440                         | BIT_VAL(state->crtc.w * cpp, 13, 0);
 441         else
 442                 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
 443                         | BIT_VAL(state->crtc.w * cpp, 14, 0);
 444         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 445
 446         decon_win_set_pixfmt(ctx, win, fb);
 447
 448         /* window enable */
 449         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 450 }
 451
 452 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 453                                 struct exynos_drm_plane *plane)
 454 {
 455         struct decon_context *ctx = crtc->ctx;
 456         unsigned int win = plane->index;
 457
 458         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 459 }
 460
 461 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 462 {
 463         struct decon_context *ctx = crtc->ctx;
 464         unsigned long flags;
 465
 466         spin_lock_irqsave(&ctx->vblank_lock, flags);
 467
 468         decon_shadow_protect(ctx, false);
 469
 470         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 471
 472         ctx->frame_id = decon_get_frame_count(ctx, true);
 473
 474         exynos_crtc_handle_event(crtc);
 475
 476         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 477 }
 478
 479 static void decon_swreset(struct decon_context *ctx)
 480 {
 481         unsigned long flags;
 482         u32 val;
 483         int ret;
 484
 485         writel(0, ctx->addr + DECON_VIDCON0);
 486         readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
 487                            ~val & VIDCON0_STOP_STATUS, 12, 20000);
 488
 489         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 490         ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
 491                                  ~val & VIDCON0_SWRESET, 12, 20000);
 492
 493         WARN(ret < 0, "failed to software reset DECON\n");
 494
 495         spin_lock_irqsave(&ctx->vblank_lock, flags);
 496         ctx->frame_id = 0;
 497         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 498
 499         if (!(ctx->out_type & IFTYPE_HDMI))
 500                 return;
 501
 502         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 503         decon_set_bits(ctx, DECON_CMU,
 504                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 505         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 506         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 507                ctx->addr + DECON_CRCCTRL);
 508 }
 509
 510 static void decon_enable(struct exynos_drm_crtc *crtc)
 511 {
 512         struct decon_context *ctx = crtc->ctx;
 513
 514         pm_runtime_get_sync(ctx->dev);
 515
 516         exynos_drm_pipe_clk_enable(crtc, true);
 517
 518         decon_swreset(ctx);
 519
 520         decon_commit(ctx->crtc);
 521 }
 522
 523 static void decon_disable(struct exynos_drm_crtc *crtc)
 524 {
 525         struct decon_context *ctx = crtc->ctx;
 526         int i;
 527
 528         if (!(ctx->out_type & I80_HW_TRG))
 529                 synchronize_irq(ctx->te_irq);
 530         synchronize_irq(ctx->irq);
 531
 532         /*
 533          * We need to make sure that all windows are disabled before we
 534          * suspend that connector. Otherwise we might try to scan from
 535          * a destroyed buffer later.
 536          */
 537         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 538                 decon_disable_plane(crtc, &ctx->planes[i]);
 539
 540         decon_swreset(ctx);
 541
 542         exynos_drm_pipe_clk_enable(crtc, false);
 543
 544         pm_runtime_put_sync(ctx->dev);
 545 }
 546
 547 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
 548 {
 549         struct decon_context *ctx = dev_id;
 550
 551         decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 552
 553         return IRQ_HANDLED;
 554 }
 555
 556 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 557 {
 558         struct decon_context *ctx = crtc->ctx;
 559         int win, i, ret;
 560
 561         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 562                 ret = clk_prepare_enable(ctx->clks[i]);
 563                 if (ret < 0)
 564                         goto err;
 565         }
 566
 567         decon_shadow_protect(ctx, true);
 568         for (win = 0; win < WINDOWS_NR; win++)
 569                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 570         decon_shadow_protect(ctx, false);
 571
 572         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 573
 574         /* TODO: wait for possible vsync */
 575         msleep(50);
 576
 577 err:
 578         while (--i >= 0)
 579                 clk_disable_unprepare(ctx->clks[i]);
 580 }
 581
 582 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
 583                 const struct drm_display_mode *mode)
 584 {
 585         struct decon_context *ctx = crtc->ctx;
 586
 587         ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
 588
 589         if (ctx->irq)
 590                 return MODE_OK;
 591
 592         dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
 593                         crtc->i80_mode ? "command" : "video");
 594
 595         return MODE_BAD;
 596 }
 597
 598 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 599         .enable                 = decon_enable,
 600         .disable                = decon_disable,
 601         .enable_vblank          = decon_enable_vblank,
 602         .disable_vblank         = decon_disable_vblank,
 603         .atomic_begin           = decon_atomic_begin,
 604         .update_plane           = decon_update_plane,
 605         .disable_plane          = decon_disable_plane,
 606         .mode_valid             = decon_mode_valid,
 607         .atomic_flush           = decon_atomic_flush,
 608 };
 609
 610 static int decon_bind(struct device *dev, struct device *master, void *data)
 611 {
 612         struct decon_context *ctx = dev_get_drvdata(dev);
 613         struct drm_device *drm_dev = data;
 614         struct exynos_drm_plane *exynos_plane;
 615         enum exynos_drm_output_type out_type;
 616         unsigned int win;
 617         int ret;
 618
 619         ctx->drm_dev = drm_dev;
 620
 621         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 622                 ctx->configs[win].pixel_formats = decon_formats;
 623                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 624                 ctx->configs[win].zpos = win - ctx->first_win;
 625                 ctx->configs[win].type = decon_win_types[win];
 626                 ctx->configs[win].capabilities = capabilities[win];
 627
 628                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 629                                         &ctx->configs[win]);
 630                 if (ret)
 631                         return ret;
 632         }
 633
 634         exynos_plane = &ctx->planes[PRIMARY_WIN];
 635         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 636                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 637         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 638                         out_type, &decon_crtc_ops, ctx);
 639         if (IS_ERR(ctx->crtc))
 640                 return PTR_ERR(ctx->crtc);
 641
 642         decon_clear_channels(ctx->crtc);
 643
 644         return exynos_drm_register_dma(drm_dev, dev);
 645 }
 646
 647 static void decon_unbind(struct device *dev, struct device *master, void *data)
 648 {
 649         struct decon_context *ctx = dev_get_drvdata(dev);
 650
 651         decon_disable(ctx->crtc);
 652
 653         /* detach this sub driver from iommu mapping if supported. */
 654         exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
 655 }
 656
 657 static const struct component_ops decon_component_ops = {
 658         .bind   = decon_bind,
 659         .unbind = decon_unbind,
 660 };
 661
 662 static void decon_handle_vblank(struct decon_context *ctx)
 663 {
 664         u32 frm;
 665
 666         spin_lock(&ctx->vblank_lock);
 667
 668         frm = decon_get_frame_count(ctx, true);
 669
 670         if (frm != ctx->frame_id) {
 671                 /* handle only if incremented, take care of wrap-around */
 672                 if ((s32)(frm - ctx->frame_id) > 0)
 673                         drm_crtc_handle_vblank(&ctx->crtc->base);
 674                 ctx->frame_id = frm;
 675         }
 676
 677         spin_unlock(&ctx->vblank_lock);
 678 }
 679
 680 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 681 {
 682         struct decon_context *ctx = dev_id;
 683         u32 val;
 684
 685         val = readl(ctx->addr + DECON_VIDINTCON1);
 686         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 687
 688         if (val) {
 689                 writel(val, ctx->addr + DECON_VIDINTCON1);
 690                 if (ctx->out_type & IFTYPE_HDMI) {
 691                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 692                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 693                         if (val ==
 694                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 695                                 return IRQ_HANDLED;
 696                 }
 697                 decon_handle_vblank(ctx);
 698         }
 699
 700         return IRQ_HANDLED;
 701 }
 702
 703 #ifdef CONFIG_PM
 704 static int exynos5433_decon_suspend(struct device *dev)
 705 {
 706         struct decon_context *ctx = dev_get_drvdata(dev);
 707         int i = ARRAY_SIZE(decon_clks_name);
 708
 709         while (--i >= 0)
 710                 clk_disable_unprepare(ctx->clks[i]);
 711
 712         return 0;
 713 }
 714
 715 static int exynos5433_decon_resume(struct device *dev)
 716 {
 717         struct decon_context *ctx = dev_get_drvdata(dev);
 718         int i, ret;
 719
 720         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 721                 ret = clk_prepare_enable(ctx->clks[i]);
 722                 if (ret < 0)
 723                         goto err;
 724         }
 725
 726         return 0;
 727
 728 err:
 729         while (--i >= 0)
 730                 clk_disable_unprepare(ctx->clks[i]);
 731
 732         return ret;
 733 }
 734 #endif
 735
 736 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 737         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 738                            NULL)
 739         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 740                                      pm_runtime_force_resume)
 741 };
 742
 743 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 744         {
 745                 .compatible = "samsung,exynos5433-decon",
 746                 .data = (void *)I80_HW_TRG
 747         },
 748         {
 749                 .compatible = "samsung,exynos5433-decon-tv",
 750                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 751         },
 752         {},
 753 };
 754 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 755
 756 static int decon_conf_irq(struct decon_context *ctx, const char *name,
 757                 irq_handler_t handler, unsigned long int flags)
 758 {
 759         struct platform_device *pdev = to_platform_device(ctx->dev);
 760         int ret, irq = platform_get_irq_byname(pdev, name);
 761
 762         if (irq < 0) {
 763                 switch (irq) {
 764                 case -EPROBE_DEFER:
 765                         return irq;
 766                 case -ENODATA:
 767                 case -ENXIO:
 768                         return 0;
 769                 default:
 770                         dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
 771                         return irq;
 772                 }
 773         }
 774         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 775         ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
 776         if (ret < 0) {
 777                 dev_err(ctx->dev, "IRQ %s request failed\n", name);
 778                 return ret;
 779         }
 780
 781         return irq;
 782 }
 783
 784 static int exynos5433_decon_probe(struct platform_device *pdev)
 785 {
 786         struct device *dev = &pdev->dev;
 787         struct decon_context *ctx;
 788         struct resource *res;
 789         int ret;
 790         int i;
 791
 792         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 793         if (!ctx)
 794                 return -ENOMEM;
 795
 796         ctx->dev = dev;
 797         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 798         spin_lock_init(&ctx->vblank_lock);
 799
 800         if (ctx->out_type & IFTYPE_HDMI)
 801                 ctx->first_win = 1;
 802
 803         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 804                 struct clk *clk;
 805
 806                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 807                 if (IS_ERR(clk))
 808                         return PTR_ERR(clk);
 809
 810                 ctx->clks[i] = clk;
 811         }
 812
 813         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 814         ctx->addr = devm_ioremap_resource(dev, res);
 815         if (IS_ERR(ctx->addr)) {
 816                 dev_err(dev, "ioremap failed\n");
 817                 return PTR_ERR(ctx->addr);
 818         }
 819
 820         ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
 821         if (ret < 0)
 822                 return ret;
 823         ctx->irq_vsync = ret;
 824
 825         ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
 826         if (ret < 0)
 827                 return ret;
 828         ctx->irq_lcd_sys = ret;
 829
 830         ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
 831                         IRQF_TRIGGER_RISING);
 832         if (ret < 0)
 833                         return ret;
 834         if (ret) {
 835                 ctx->te_irq = ret;
 836                 ctx->out_type &= ~I80_HW_TRG;
 837         }
 838
 839         if (ctx->out_type & I80_HW_TRG) {
 840                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 841                                                         "samsung,disp-sysreg");
 842                 if (IS_ERR(ctx->sysreg)) {
 843                         dev_err(dev, "failed to get system register\n");
 844                         return PTR_ERR(ctx->sysreg);
 845                 }
 846         }
 847
 848         platform_set_drvdata(pdev, ctx);
 849
 850         pm_runtime_enable(dev);
 851
 852         ret = component_add(dev, &decon_component_ops);
 853         if (ret)
 854                 goto err_disable_pm_runtime;
 855
 856         return 0;
 857
 858 err_disable_pm_runtime:
 859         pm_runtime_disable(dev);
 860
 861         return ret;
 862 }
 863
 864 static int exynos5433_decon_remove(struct platform_device *pdev)
 865 {
 866         pm_runtime_disable(&pdev->dev);
 867
 868         component_del(&pdev->dev, &decon_component_ops);
 869
 870         return 0;
 871 }
 872
 873 struct platform_driver exynos5433_decon_driver = {
 874         .probe          = exynos5433_decon_probe,
 875         .remove         = exynos5433_decon_remove,
 876         .driver         = {
 877                 .name   = "exynos5433-decon",
 878                 .pm     = &exynos5433_decon_pm_ops,
 879                 .of_match_table = exynos5433_decon_driver_dt_match,
 880         },
 881 };